2018 IEEE 4th Information Technology and Mechatronics Engineering Conference (ITOEC 2018)

A Cortex-M3-Based System-On-Chip Architecture

for Wireless Communications in Power Grid
Yingying Chi1,2*, Weilong Zhang1, Zhe Zheng1,3, Wenpeng Cui1,2
1. Global Energy Interconnection Research Institute Co.,Ltd.
2. State Grid Key Laboratory of Information & Network Security
3. State Grid Laboratory of Electric Power Communication Network Technology
Beijing, China
xingye_314529@126.com

Abstract—This paper presents a Cortex-M3-based system-on-
chip (SoC) architecture designed for power-grid-dedicated
wireless communication system based on IEEE 802.11ah protocol.
The SoC is integrated with a 32-bit embedded microprocessor
core using Thumb-2 instruction sets and multiple master/slave
devices being compliable with advanced microcontroller bus
architecture (AMBA) v2.0 protocol. Along with the various
communication interfaces to make the chip more applicable, the
whole system can accomplish data communication and processing
in power grid applications with high performance and low cost.
Keywords—system-on-chip, cortex-m3, wireless communication,
power grid
I. INTRODUCTION
With the rapid development of VLSI and the continuous
emergence of new devices, embedded system has been widely
used and the design of communication and control circuits has
been greatly changed. The design scheme using MPU and
many peripheral chips, such as memory, I/O extension, latch
and so on, has been replaced by system-level chip SoC. SoC,
taking account of the overall function and performance of the
system, has gradually become the mainstream design trend in
the field of wireless communication and control. It is a highly
integrated system with microprocessor and some digital/analog
peripherals being placed on one single chip. The chip is
programmable, configurable, flexible in design, high in
integration degree and reliability but low in power consumption
and area occupation, therefore it is very suitable as a control
and interface chip for wireless communication systems.
The proposed SoC architecture in this paper integrated the
cortex-m3 microcontroller, memories, Ethernet controller
GMAC, physical interface transceiver PHY, analog front-end
module, security module, various interface circuits and wireless
transceiver into a very small single chip, and has great potential
in short-range wireless communication systems of power-grid
applications which require high security, low power
consumption, low cost, multi-node and flexible networking.
The SoC is applicable for power grid communication systems
based on IEEE 802.11ah protocol such as electrical
information acquisition terminal, substation/transmission-line
status monitoring system, video surveillance, mobile patrol and
so on[1].
The paper is organized as follows. System architecture and
bus matrix will be presented in section Ⅱ. Microprocessor and
some key peripherals will be discussed in detail in section Ⅲ.
In section Ⅳ , clock domain and area occupancy of the
proposed architecture will be provided. Finally the conclusion
of the full paper will be made.
II. SYSTEM ARCHITECTURE
A. Overview
In the design method of on-chip system, IP (Intellectual
Property) core and the on-chip bus are the most important parts.
IP core is a RTL level module that realizes special circuit
function, and it can be transplanted and reused in different SoC
because of its independence of the process. The large number
of integration and cooperative interconnection of IP cores with
different functions determines the functions that can be realized
by a single SoC. On-chip bus structure is the mainstream
solution to the interconnection of various IP cores. Some
standard bus protocols, like CoreConnect bus by IBM
Company and AMBA bus by ARM Company, etc., have been
introduced to make the bus more compatible with the IP cores
provided by the third party.
B. SoC Architecture
The system architecture and the bus matrix of the proposed
SoC are illustrated in Figure 1 & Figure 2 separately.
AMBA2.0 bus protocol is adopted because it can standardize
several kinds of buses of different speed to adapt to more
complex applications and it supports a large number of third
party IP cores. The SoC is integrated with a 32-bit
microprocessor core using Thumb-2 instruction sets, a SPI-
flash, a SDRAM, four SRAMs and two FIFOs (TxFIFO &
RxFIFO) for different storage use, a DMA for data migration
between peripherals and memories, a GMAC (Gigabit Ethernet
MAC controller) and PHY to provide Ethernet access to SoC,
several communication interfaces like GPIO, UART, SPI and
I2C to facilitate the subsequent application expansion, a secure
encryption IP to ensure the security of data transmission and
processing and some other function modules like watchdog and
timers.
III. MAIN FUNCTION MODULE DESCRIPTION
The main processor (CPU) is responsible for genera data
processing, peripheral configuration, interrupt response, task
scheduling and so on. Other components, occupying the limited

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bus resources, are used for data transmission and interaction Based on the above considerations, in the design of SoC
under the control of the processor core. with Cortex-M3 as its core, it is better to attach FLASH to
Icode and Dcode bus corresponding to
FLASH
0x00000000~0x20000000 region, and the on-chip SRAM to

CM3DI

M0
Code Mux

S0
Controller TIMER0
TxFIFO
System bus which corresponds to 0x20000000~0x40000000
AHB master port
Cortex-M3

M1
SRAM0 TIMER1 AHB slave port
RxFIFO
region in the address space. In this way, the instruction and

CM3S
S1
AHB slave module

M2
SRAM1 Dualtimer
SPI AHB master module
read-only data from FLASH can be executed and fetched in

M3
AHB MUX
SRAM2 UART0
parallel by Icode and Dcode bus, while the data in SRAM can
bus bridge
I2C

INTEXP0
GMAC(s) DMA(m)
S2 APB slave module

M4
SRAM3
be read and written by System bus. The three buses have their
UART1
PHY DMA(s)
AFE
own division of labor, so that the performance of SoC is greatly
INTEXP1

GMAC(m)
S3

APB0

M5
GPIO0~3 SECURITY AHB2APB

SYSCTRL
WatchDog
improved. Table Ⅰshows the mapping of the memory system.
SDRAM
EXP0

EXP1
M6

M7

Reserved
Controller
CRC

TABLE I. CODE AND RAM MEMORY MAP

Fig. 1. Architecture of the proposed SoC
Type Start End Peripheral Size
CM3DI CM3S DMA GMAC 0x0000_0000 0x00FF_FFFF FLASH 16MB
CODE 0x0100_0000 0x0100_FFFF FLASH_reg 64KB
input_stage_0 input_stage_1 input_stage_2 input_stage_3 0x0101_0000 0x1FFF_FFFF Reserved -
0x2000_0000 0x2000_FFFF SRAM0 64KB
Decoder_cm3di Decoder_cm3s Decoder_exp0 Decoder_exp1
0x2001_0000 0x2001_FFFF SRAM1 64KB
Output_stage
0x2002_0000 0x2002_FFFF SRAM2 64KB
SPI-FLASH
Arbiter
RAM 0x2003_0000 0x2003_FFFF SRAM3 64KB
Output_stage SRAM0 0x2004_0000 0x200F_FFFF Reserved 768KB
0x2010_0000 0x21FF_FFFF Reserved -
Output_stage SRAM1
0x2200_0000 0x23FF_FFFF BitBandAlias 32MB
Output_stage SRAM2
BUS MATRIX
Output_stage SRAM3
C. Phsical and Media Access Control Layer
Output_stage EXP0
The chip is functionally divided into three layers: physical
layer (PHY), media access control layer (MAC) and protocol
layer[2]. Figure 3 is the hardware and software partition diagram.
Output_stage EXP1

Output_stage APB0
Gigabit Media Access Control (GMAC) module, modulation
Fig. 2. Bus matrix of the proposed SoC and demodulation part, CPU and together with interface circuit
constitute the baseband processing module.
A. Microprocessor Core Besides the control and management of the digital signal
ARM Cortex-M3 is a 32-bit processor core which adopts processing module of the whole wireless communication
the Harvard structure and the three-stage pipeline system. It has system, including timing, interrupt response, energy-saving
been favored by a lot of manufactures due to its high mode control and interface control, CPU also runs the upper
performance, low power consumption, low cost and layer application software of the communication terminal on
friendliness for development. There are three bus interfaces demand. Modem mainly completes the modulation and
outside the core, Icode-bus, Dcode-bus and System-bus. The demodulation based on the IEEE 802.11ah communication
Icode and Dcode bus interfaces make the parallel execution of protocol. GMAC is used to define the transmission mode of
instruction and data fetch from the code region of the address data frames in the medium. In a shared bandwidth link, access
space a reality while the System-bus interface makes the to the connection medium is on a first-come-first-served basis.
instruction and data fetch from the SRAM region of the address Physical addressing is defined at the MAC layer and the logical
space use the same interface, which cannot be executed in topology is also defined here. In addition, line control, error
parallel. notification, frame transmission order and optional flow control
are also implemented in this sublayer.
B. Memory System Software
The memory system of the proposed SoC is composed of Protocol Layer
one 16MB-FLASH, four 64KB-SRAMs and one 16MB-
SDRAM. The SRAM is directly connected to the bus interface
through a simple controller, and it is implemented on-chip,
while the FLASH and SDRAM are off-chip and they are
Media Access Control Layer(GMAC)
connected to the bus interface through corresponding on-chip
controllers. The FLASH can provide non-volatile storage of
operating system, most of the user application programs and
some constant application configuration data, While the on-
chip SRAM provides space for the read-write data which is Phisical Layer (PHY)

temporarily generated when the program is executed. Since the Hardware

on-chip SRAM space is limited, off-chip SDRAM is a solution
to the lack of program space. Fig. 3. Hardware and software partition of chip

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 The baseband system architecture is shown in Figure 4. The reserved state, and its configuration registers are all writable,
digital baseband data is interacted by RF front-end and PHY which can provide a channel for access between any peripheral
layer. After modulation or demodulation, the data are and memory. The configuration and occupancy of the channels
exchanged to GMAC to be parsed or packaged according to is shown in Figure 6.
IEEE 802.11ah standard. In short, GMAC implements data
frame protocol analysis and control while PHY implements
data processing including modulation /demodulation, channel DMA
equalization, etc.. HW request0 High priority
Channel 0

SW trigger 0

HW request1
AMBA BUS Channel 1
Internal
BUS_IF SW trigger 1 DMA request
HW request2
Channel 2

SW trigger 2

HW request3
Channel 3

SW trigger 3 Low priority

Fig. 5. Channel priority of DMA

Channel 0 Channel 2
FLASH SRAM SPI

SDRAM I2C
Channel 3 (Reserved)
Fig. 4. PHY and GMAC architecture in the baseband system
TxFIFO
UART0
D. Direct Memory Access RxFIFO

Direct Memory Access (DMA) allows hardware devices Channel 1

working at different frequencies to communicate with each
other without relying on the heavy outage load of CPU.
Otherwise, CPU needs to copy each fragment of data from the
source to cache and write it to a new place, which makes CPU
not available for other tasks at that time. A complete DMA
transmission process must go through four steps: DMA
request, DMA response, DMA transmission and the end.
As shown in Figure 5, the channel priority of DMA is
fixed. In order to avoid the situation of late response to some
peripheral requests, the real-time task should be taken into
account in the design of application software, and each
channel is configured to carry limited data to ensure that other
channels can be responded in time. When DMA is idle or has
just complete a DMA operation, one or more DMA requests
occur, at this time, the priority is set to get arbitrated, and the
high-priority peripheral request gets the DMA service fist. The
priority of CPU getting access to RAM is higher than that of
DMA.
In order to maximize efficiency and reduce hardware
resources, three of the four channels of DMA are configured in
a fixed mode to serve the specific requirements of the
proposed SoC. The configuration registers corresponding to
these three channels are set to read-only state and only a small
number of configurable registers are left for software to write
configuration data on demand so that the overhead of registers
can be greatly reduced. The remaining channel is set to a
CRC
Fig. 6. DMA channel configurations for special use
E. Interface Circuits and Others
According to the application environment and requirement
of the power-grid on-chip system, a variety of interface
circuits are set up on the SoC to facilitate the communication
between the SoC and the outside, along with the watchdog
circuit and system control circuit.
The SoC is integrated with some serial communication
interfaces like SPI (Serial Peripheral Interface), I2C (Inter-
Integrated Circuit) and UART (Universal Asynchronous
Receiver/Transmitter). UART is a two-line serial port
communicating with the bus bridge via the APB bus, and the
UART controller provides the function of serial
communication with MODEM or other peripheral devices.
The SPI module, working under the control of the serial clock
whose polarity and phase are programmable, can work in
master, and slave, or both modes, and a 32-byte buffer is
integrated for transmitting and receiving data. The I2C block is
designed to support a set of primitive operations and detect a
set of status conditions specific to the I2C protocol. These
primitive operations and conditions are manipulated and
combined at the firmware level to support the required data
transfer modes. The CPU will set up control options and issue
commands to the unit through I/O writes and obtain status

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through I/O reads and interrupts. The block operates in slave,
and master, or both modes.
The watchdog timer is actually a counter which is usually
initialized with a large number, and it starts counting
backwards when the program starts running. If the program
works properly, CPU should issue instructions for the
watchdog to reset and start counting backwards after some
time. Otherwise, if the watchdog counts to 0, it indicates that
the program is not working properly, and the whole system
should be forced to reset at this time.
System controller includes logics with regards to AHB
address remapping, module clock gating control, reset control
and reset information record.
IV. RESOURCE UTILIZATION Fig. 7. Area proportional distribution of the proposed SoC

A. Clock Domain V. CONCLUSION

The clock source of the SoC is provided by external This paper presented a Cortex-M3-based system-on-chip
oscillator which drives all the on-chip logic during initialization. (SoC) architecture designed for power-grid-dedicated wireless
According to the preset value in the configuration registers, the communication system based on IEEE 802.11ah protocol.
clock signal is multiplied by PLL (Phase Locked Loop) to a Being integrated with the high performance Cortex-M3
higher frequency which will be divided by specific division processor core and various peripheral interfaces, the proposed
ratios set during the boot phase to desired frequencies. The SoC can be used in plenty of areas, such as power information
processor is operating on the highest frequency and the FLASH collection, transmission line status monitoring, video
off-chip runs on a lower frequency via frequency conversion of monitoring, mobile inspection and so on with high security,
the bus bridge. The other peripherals may work on their own low power consumption and low cost.
clock frequency according to the communication needs.
ACKNOWLEDGMENT
B. Area Occupation
This work was supported by the project of development on
The proposed SoC is to be fabricated using SMIC55nm low
wireless communication chip of electric power system based on
power flash-embedded process. The areas of the main function
802.11ah under grant No. SGRIXTMMXS [2015]1128.
modules are shown in TABLE Ⅱ and the proportional
distribution is in Figure 7.
REFERENCES
[1] http://www.ieee802.org/11/.
TABLE Ⅱ. AREAS OF THE MAIN FUNCTION MODULES
[2] J. G.Nychis, T.Hottelier, Z.Yang, S.Seshan, and P.Steenkiste, “Enabling
Module Name Area/um2 Percentage/% MAC protocol implementations on software-defined radios,” USENIX
Cortex-M3 150307 14.13 Symposium on Networked Systems Design and Implementation, 2009,
AHB-Matrix 19645 1.85 pp.91-105.
SDRAM Controller 23291 2.19 [3] Weilong Zhang, Yuxiang Yuan, Yang Liu, etc., “A security coprocessor
FLASH Controller 7345 0.69 embedded system-on-chip architecture for smart metering, control and
Peripherals communication in power grid,” International Conference on Solid-State
53119 4.99 and Intergrated Circuit Technology, 2014, pp.1-3.
(GPIOs, dualtimer, UARTs, Watchdog, etc.)
SRAM 1588486 86.23 [4] https://wenku.baidu.com/view/e400fef60b4e767f5bcfce2b.html.
total 1842193 100 [5] Singer, Joel. “Enabling Tomorrow`s Electricity System: Report of the
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