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MATLAB to VHDL Converter Examples

Technical Report · February 2020

DOI: 10.13140/RG.2.2.20639.30887

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 University of Montenegro
Faculty of Electrical Engineering

MATLAB to VHDL Converter Examples

Olivera Nikčević, Filip Živković, Budimir Anđelić, . Radovan Stojanovć

Date and place: 14/01/2020

Podgorica

Contact: stox@ucg.ac.me

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Contents
Summary ....................................................................................................................................................... 3
Problem description...................................................................................................................................... 3
Software solution and simulation ................................................................................................................. 3
Steps.......................................................................................................................................................... 3
Examples ....................................................................................................................................................... 7
Example 1. ................................................................................................................................................. 8
MATLAB code ........................................................................................................................................ 8
MATLAB to VHDL code .......................................................................................................................... 8
Our VHDL code ...................................................................................................................................... 8
QUARTUS II testing................................................................................................................................ 8
Example 2. ................................................................................................................................................. 9
MATLAB code ........................................................................................................................................ 9
MATLAB to VHDL code ........................................................................................................................ 10
Our VHDL code .................................................................................................................................... 10
QUARTUS II testing.............................................................................................................................. 11
Conclusion ................................................................................................................................................... 12

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Summary
This is an exam project, made in MEDEL electronics lab at the University of Montenegro, with
mentoring of prof. Dr. Radovan Stojanović. In further text, the problem is explained in details and
offered an elegant solution. In addition to that, we have enclosed high level design and description of
our solution, alongside with hardware and software structure. The accent is on MATLAB to VHDL code
conversion.

Problem description
Our job is to explain the principle of converting MATLAB code to VHDL code. This project show
that knowledge of Altera QUARTUS program is not necessary, but generating the VHDL code can be
gotten through MATLAB. Will this be a good way for functional VHDL code we are going to show in one
of the following chapters.

Software solution and simulation

As a software solution we used Altera QUARTUS 9.1 which is approved and tested for all FPGA
and CPDL based systems. Below the text there are few steps for generating a code. Every step is
followed by an image, so it cannot be hard to learn.

Steps

1. Open MATLAB

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2. Write a function that you want to convert to VHDL

3. Go to Apps and search for HDL Coder

4. Open HDL Coder and make a new project

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5. Add MATLAB function file

6. Go to Workflow Advisor
7. Select Convert to fixed-point at build time because double operation is not suitable for FPGA

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8. Define input types

9. Go to Fixed-point conversion and define Static Min and Static Max

10. Compute Derived Ranges
11. Validate Types

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 12. Select Code Generation Target

13. HDL Code Generation – Select VHDL

14. Run

Examples
We will show two different examples, and describe each of them (showing the difference
between the code which is generated using HDL Coder, and the code without converting).

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 Example 1.

Multiplexer 2/1

MATLAB code

function [ y ] = mux_func( a,b,sel )

y = ((~sel)&a) | (sel&(b));
end

MATLAB to VHDL code Our VHDL code

LIBRARY IEEE; library ieee;

USE IEEE.std_logic_1164.ALL; use ieee.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY mux21_fixpt IS entity mux_2to1_top is
PORT( a port (w0, w1, s : in std_logic;
: IN std_logic; f : out std_logic);
b end mux_2to1_top;
: IN std_logic;
sel architecture behaviour of
: IN std_logic; mux_2to1_top is
y
: OUT std_logic begin
);
END mux21_fixpt;
ARCHITECTURE rtl OF mux21_fixpt IS f <= ( NOT s)ANDw0)OR(sANDw2);
BEGIN
y <= (( NOT sel) AND a) OR (sel
AND b); end behaviour;
END rtl;

QUARTUS II testing

MATLAB to VHDL code Our code

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Flow Summary

MATLAB to VHDL code Our code

Simulation:

MATLAB to VHDL code

Our code

In this example, a VHDL code for multiplexer 2/1 is generated from MATLAB code. We got a fully
functional code, and it is ready to be used properly, without any error. There is no difference between
code we got and a code we wrote directly in Altera QUARTUS.

Example 2.

4-bit Counter

MATLAB code

function count = %four bit synchronous up counter

mlhdlc_counter(enable_ctr) %persistent variable for the state

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persistent count_val; %limit to four bits
if isempty(count_val) if count_val>15
count_val = 0; count_val=0;
end end
%counting up end
if enable_ctr count=count_val;
count_val=count_val+1; end

MATLAB to VHDL code

LIBRARY IEEE; BEGIN

USE IEEE.std_logic_1164.ALL; enb <= clk_enable;
USE IEEE.numeric_std.ALL; --HDL code generation from MATLAB
ENTITY mlhdlc_counter_fixpt IS function: mlhdlc_counter_fixpt
PORT( clk --limit to four bits
: IN std_logic; tmp <= count_val +
reset to_unsigned(16#1#, 4);
: IN std_logic; --HDL code generation from MATLAB
clk_enable function:
: IN std_logic; mlhdlc_counter_fixpt_trueregionp1
enable_ctr count_val_1 <= tmp;
: IN std_logic; count_val_reg_process : PROCESS
ce_out (clk, reset)
: OUT std_logic; BEGIN
count IF reset = '1' THEN
: OUT std_logic_vector(3 DOWNTO count_val <=
0) -- ufix4 to_unsigned(16#0#, 4);
); ELSIF clk'EVENT AND clk = '1'
END mlhdlc_counter_fixpt; THEN
ARCHITECTURE rtl OF IF enb = '1' THEN
mlhdlc_counter_fixpt IS count_val <= tmp_1;
-- Signals END IF;
SIGNAL enb END IF;
: std_logic; END PROCESS
SIGNAL count_val count_val_reg_process;
: unsigned(3 DOWNTO 0); -- ufix4 tmp_1 <= count_val WHEN
SIGNAL tmp enable_ctr = '0' ELSE
: unsigned(3 DOWNTO 0); -- ufix4 count_val_1;
SIGNAL count_val_1 count <= std_logic_vector(tmp_1);
: unsigned(3 DOWNTO 0); -- ufix4 ce_out <= clk_enable;
SIGNAL tmp_1 END rtl;
: unsigned(3 DOWNTO 0); -- ufix4

Our VHDL code

library ieee; count : out integer range 0 to 15);

use ieee.std_logic_1164.all; end counter;
entity counter is architecture RTL of counter is
port( begin
clock_new: in std_logic; process(clock_new)
reset: in bit; variable brojac : integer range 0
enable : in bit; to 15;

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begin brojac:=0;
if(clock_new='1' and end if;
clock_new'event) then end if;
if (enable='1') then end if;
if(brojac<15) then count <=brojac;
brojac:=brojac+1; end process;
else end RTL;

QUARTUS II testing

MATLAB to VHDL code Our code

Flow Summary:

MATLAB to VHDL code Our code

Simulation:

MATLAB to VHDL code

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 Our code

In this second example, it is shown how to make 4 bit counter using two methods
(converting MATLAB code to VHDL code and writing it directly in Altera QUARTUS). Generating VHDL
code from MATLAB, we got also a fully functional code as in the first example, but this time there is
some difference between these two codes. At the first sight from the pictures above, difference is
obvious. In the generated code we have 41 lines of code, but in our VHDL code we have 26 lines of code,
what indicates that we need less lines of the code if we use Altera QUARTUS for making 4-bit counter,
and accordingly we need less memory. Also, using MATLAB for generating code we need more logics
elements as well as totals pins.

Conclusion
From this two examples, we can notice that the knowledge of Altera QUARTUS program for
solving some problems is very useful, but the MATLAB can be used as utility for generating the code for
the same problem. Using Altera program we can save a lot of memory because convertor is working only
to solve problem and make a functional code. It does not take care of how many lines of code it will use
or how much memory it will spend. We made an example for one combinational and one sequential
circuit. For the simple codes, converter is working in accordance with expectations, there is no
difference between two codes obtained in two different ways. But, as the code is more complex,
difference is bigger. It is necessary to use more logic elements, more pins, and for sure a much more
memory.

References:

[1] Radovan D. Stojanovic AUTOMATIZOVANO PROJEKTOVANJE DIGITALNIH SISTEMA (VHDL

i FPGA)
[2] HDL Coder, Generate VHDL and Verilog code for FPGA and ASIC designs,
https://www.mathworks.com/products/hdl-coder.html

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