c



   

(Affiliated to JNTUH Hyderabad and Approved by AICTE)
Vyasapuri, Bandlaguda, Post: Kesavagiri
Hyderabad ± 500 005


  

This is to certify that the Technical Seminar titled ³ 
    is
submitted by

[07E31A0414]

in partial fulfilment for the award of the degree of bachelor of technology in Electronics and
Communication Engineering to the Jawaharlal Nehru Technological University-Hyderabad
during the academic year 2010-2011 is a record of bonafide work carried out under our
supervision











 !"#   ! #!
$
c$"" %&!$'()()
B.E,M.TECH M.E, P.G.D, M.S.M, F.I.ETE, BE, M.Tech, PhD
M.I.S.T.E MISTE, MSEMC (I). Proffesor,Dept. of ECE
AsstProfessor  Professor,Dept.of ECE (MIST)
(MIST)


'  

In modern age Engineers have paved the way for a new generation of faster, more

powerful cell phones, computers and other electronics by developing a practical technique to

replace silicon with carbon on large surface. The capability of silicon, the material at the

heart of computer chips has been harnessed beyond its limits by engineers and carbon has

come up as an integrating replacement for the same.

The material called (
 which is a single layer of atoms arranged in

honeycomb lattice could let electronics to process information and produce radio

transmission many times better than silicon based devices such as transistors. Graphene is a

rapidly rising star on the horizon of materials science and condensed matter physics. This

strictly two-dimensional material exhibits exceptionally high crystal and electronic quality

and, despite its short history, has already revealed a cornucopia of new physics and potential

applications, one of which is a Graphene Transistor briefly discussed here.

Graphene Transistor is a single-electron transistor, which means that a single electron

passes through it at any one time. Graphene transistors could scale to transistor channels as

small as two manometers (nm) with terahertz speeds. More generally, Graphene represents a

conceptually new class of materials that are only one atom thick and, on this basis, offers new

inroads into low-dimensional physics that has never ceased to surprise and continues to

provide a fertile ground for applications.



 *

 $


Graphene is the name given to a flat monolayer of carbon atoms tightly packed into a

two-dimensional (2D) honeycomb lattice, and is a basic building block for graphitic materials

of all other dimensionalities (Figure 1). It can be wrapped up into 0D fullerenes, rolled into

1D nanotubes or stacked into 3D graphite. Theoretically, Graphene (or ³2D graphite´) has

been studied for sixty years and widely used for describing properties of various carbon-

based materials. Forty years later, it was realized that Graphene also provides an excellent

condensed-matter analogue of (2+1)-dimensional quantum electrodynamics, which propelled

Graphene into a thriving theoretical toy model. On the other hand, although known as integral

part of 3D materials, Graphene was presumed not to exist in the Free State, being described

as an ³academic´ material and believed to be unstable with respect to the formation of curved

structures such as soot, fullerenes and nanotubes. All of a sudden, the vintage model turned

into reality, when free-standing Graphene was unexpectedly found and, especially, when the

follow-up experiments confirmed that its charge carriers were indeed massless Dirac

fermions. So, the Graphene ³gold rush´ has begun.

**'
  


More than 70 years ago, Landau and Peierls argued that strictly two-dimensional (2D)

crystals were thermodynamically unstable and could not exist. Their theory pointed out that a

divergent contribution of thermal fluctuations in low-dimensional crystal lattices should lead

to such displacements of atoms that they become comparable to interatomic distances at any

finite temperature. The argument was later extended by Mermin and is strongly supported by

a whole omnibus of experimental observations. Indeed, the melting temperature of thin films
rapidly decreases with decreasing thickness, and they become unstable (segregate into islands

or decompose) at a thickness of, typically, dozens of atomic layers. For this reason, atomic

monolayers have so far been known only as an integral part of larger 3D structures, usually

grown epitaxial on top of monocrystals with matching crystal lattices. Without such a 3D

base, 2D materials were presumed not to exist until 2004, when the common wisdom was

flaunted by the experimental discovery of Graphene and other free-standing 2D atomic

crystals (for example, single-layer boron nitride and half-layer BSCCO). These crystals could

be obtained on top of non-crystalline substrates, in liquid suspension, and as suspended

membranes. Importantly, the 2D crystals were found not only to be continuous but to exhibit

high crystal quality. The latter is most obvious for the case of Graphene, in which charge

carriers can travel thousands interatomic distances without scattering. With the benefit of

hindsight, the existence of such one-atom-thick crystals can be reconciled with theory.

Indeed, it can be argued that the obtained 2D crystallites are quenched in a metastable state

because they are extracted from 3D materials, whereas their small size (<<1mm) and strong

interatomic bonds assure that thermal fluctuations cannot lead to the generation of

dislocations or other crystal defects even at elevated temperature

A complementary viewpoint is that the extracted 2D crystals become intrinsically

stable by gentle crumpling in the third dimension on a lateral scale of 10nm. Such 3D

warping observed experimentally leads to again in elastic energy but suppresses thermal

vibrations (anomalously large in 2D), which above a certain temperature can minimize the

total free energy.


*+$( )%,-

Graphene, though only recently confirmed experimentally, has been discussed in

conjunction with graphite for many years. Many of its properties had long been studied in

conjunction with the properties of graphite, including its band structure. For example,
graphene was predicted to be a semiconductor with no band gap at the corners of the

reciprocal lattice using the tight-binding approximation. But theoretical studies of graphene

were historically limited entirely to approximations for the properties of graphite. Graphene

as a free substance was largely ignored as a purely academic substance because it was

accepted that thermodynamic stresses prevented the existence of any free one- or two-

dimensional crystals. Additionally, there had been previous attempts to achieve two-

dimensional crystals, but in all cases, it was confirmed that reducing the thickness made the

crystals melt at increasingly low temperatures and it was agreed that two dimensional crystals

were too unstable to exist in a free state. A possible explanation for the disparity between

theory predicting the non-existence of two-dimensional crystals and their experimental

confirmation may be that the graphene monolayers are only approximately two-dimensional

and owe some of their stability to rippling perpendicular to the plane.

Fig 1.1
‘

 



   
 

 
    .

But in 2004, graphene was produced experimentally, defying decades of predictions

that it could not exist apart from a crystalline substrate. The procedure for acquiring the

monolayer graphene is comically simple: essentially, graphene is removed from a graphite

sample by using clear adhesive tape to remove layers from graphite. The tape is then stuck to

new clean tape several times to remove additional layers. After a few times, the tape is

dissolved and the graphite remains are examined to sort the graphene mono layers from the

ultrathin graphite films. The difficulty is in sorting the graphene from the graphite.

Fortunately, different thicknesses of graphite are distinguishable under optical microscopy on

a special silicon substrate. The adhesive tape technique produces extremely high quality

crystals of up to 100 micrometers in length, more than sufficient for most laboratory

experiments. And even better, the raw materials are very cheap.

*.,-/( ! ,!(

Before viewing about Graphene Transistors, it is useful to define what 2D crystals are

and their relevance to Graphene¶s electrical properties. Obviously, a single atomic plane is a

2D crystal, whereas 100 layers should be considered as a thin film of a 3D material. For the

case of Graphene, the situation has recently become reasonably clear. It was shown that the

electronic structure rapidly evolves with the number of layers, approaching the 3D limit of

graphite already at 10 layers. Moreover, only Graphene and, to a good approximation, its

bilayer have simple electronic spectra: they are both zero-gap semiconductors (can also be

referred to as zero-overlap semimetals) with one type of electrons and one type of holes. For

3 and more layers, the spectra become increasingly complicated: Several charge carriers

appear, and the conduction and valence bands start notably overlapping. This allows one to

distinguish between single-, double- and few- (3 to <10) layer Graphene as three different

types of 2D crystals (³Graphene´). Thicker structures should be considered, to all intents and

purposes, as thin films of graphite. From the experimental point of view, such a definition is

also sensible. The screening length in graphite is only 5Å (that is, less than 2 layers in

thickness) and, hence, one must differentiate between the surface and the bulk even for films

as thin as 5 layers. Earlier attempts to isolate Graphene concentrated on chemical exfoliation.

To this end, bulk graphite was first intercalated (to stage I) so that Graphene planes became

separated by layers of intervening atoms or molecules.

This usually resulted in new 3D materials. However, in certain cases, large molecules

could be inserted between atomic planes, providing greater separation such that the resulting

compounds could be considered as isolated Graphene layers embedded in a 3D matrix.

Furthermore, one can often get rid of intercalating molecules in a chemical reaction to obtain

a sludge consisting of restacked and scrolled Graphene sheets. Because of its uncontrollable

character, graphitic sludge has so far attracted only limited interest. There have also been a

small number of attempts to grow Graphene. The same approach as generally used for growth

of carbon nanotubes so far allowed graphite films only thicker than 100 layers. On the other

hand, single- and few-layer Graphene have been grown epitaxial by chemical vapour

deposition of hydrocarbons on metal substrates and by thermal decomposition of SiC. Such

films were studied by surface science techniques, and their quality and continuity remained

unknown. Only lately, few-layer Graphene obtained on SiC was characterized with respect to

its electronic properties, revealing high-mobility charge carriers.

Because it can form single, double and triple bonds, it forms thousands of chemical

compounds, and has numerous elemental structures, or allotropes. The most common

allotropes of carbon are diamond and graphite. Diamond consists of carbon atoms single-

bonded to four other carbon atoms producing a tetrahedral crystal lattice. Its structure leads

to its extreme hardness and thermal conductivity, but diamond is a very poor electrical

conductor. In contrast, graphite consists of stacked layers of carbon sheets. Within an

individual carbon sheet, known as graphene, the carbon atoms are sp2 hybridized and form a

planar hexagonal lattice. The sp2 hybridization means that the carbons are X-bonded in the

plane, but are also -bonded above and below the plane. Graphene thus possesses one of the
strongest bonds in nature and has a very high tensile strength. Graphene¶s perpendicular p-

orbital lead to electron delocalization because there is no distinction between neighbouring

bonds, as indicated in Figure below.

Fig 1.2
‘
 

      
 
 
   
  
 
  

This conjugated orbital system permits the electrons to travel freely above and

below the plane of carbon atoms with minimal scattering. Because of the minimal scattering

and strong delocalization of the electrons, graphite is a good conductor along the plane.

However, in graphite, electrostatic forces bind the layers together only very weakly, and

graphite is a very soft mineral. In addition, the other layers interfere with the behaviour of

the single sheets, even if not strongly. An ideal system would be to study free single-layer

graphene, but until a few years ago, two-dimensional systems like free graphene were

believed to be impossible.

In recent years, the two most familiar allotropes of carbon have been joined by a

number of newly discovered graphene-like materials. The first major graphene-related

substance discovered was C60, also known as buckminsterfullerene, buckyball, and fullerene,

a soccer-ball-like configuration of carbon atoms found in common lamp soot and known to
be very stable. Soon, the scientific community encountered similar fullerene-type carbon

structures called carbon nanotubes. Carbon nanotubes are needle-like tubes of rolled up

graphene sheets that exhibit many unusual and useful properties such as extreme tensile

strength and high conductivity. .

Epitaxial growth of Graphene offers probably the only viable route towards electronic

applications and, with so much at stake, a rapid progress in this direction is expected. The

approach that seems promising but has not been attempted yet is the use of the previously

demonstrated epistaxis on catalytic surfaces (such as Ni or Pt.) followed by the deposition of

an insulating support on top of Graphene and chemical removal of the primary metallic

substrate.

Fig 1.3
c 





 
0Graphene is a 2D building material for carbon materials of all other dimensionalities. It can

be wrapped up into 0D buckyballs, rolled into 1D nanotube or stacked into 3D graphite.´

In modern age Engineers have paved the way for a new generation of faster, more powerful

cell phones, computers and other electronics by developing a practical technique to replace

silicon with carbon on large surface.

The capability of silicon, the material at the heart of computer chips has been harnessed

beyond its limits by engineers and carbon has come up as an integrating replacement for the

same. The material called (
 which is a single layer of atoms arranged in

honeycomb lattice could let electronics to process information and produce radio

transmission 10 times better than silicon based devices. The new technology through that

they needed (
´ material is the same as the silicon used to make chips-a single

crystal of material eight or twelve inches wide and the largest single crystal Graphene sheet

made have not been wider than a couple of millimetre, which is not enough for a single chip.

It is widely used to describe properties of many carbon based material, including graphite,

large fullerences, nanotubes etc. Planer Graphene itself has been presumed not to exist in the

Free State being unstable with respect to formation of curved structure.


 +

  c $ 


A graphene transistor is a Nano scale device based on graphene, a component of

graphite with electronic properties far superior to those of silicon. The device is a single-

electron transistor, which means that a single electron passes through it at any one time. A

research team led by Professor Andre Geim of the Manchester Centre for Mesoscience

and Nanotechnology built a graphene transistor and described it in the March 2007 issue

of ?
 magazine. Scientists have predicted that graphene transistors could scale to

transistor channels as small as two nanometres (nm) with terahertz speeds.

Before we go into the details of the working of Graphene based Transistors it is important for

us to look into the electrical properties of Graphene which is base material of the transistor.

+*,-/( -1 ( !)(! 

But why is there such interest in graphene? Aside from the obvious interest in the

novelty of a two-dimensional crystal, graphene crystals exhibit unusual electrical properties

that may prove useful both theoretically and practically. In particular, Graphene¶s charge

carriers are very unusual in that they behave like mass less Dirac fermions and are most

effectively described by the Dirac equation rather than the non-relativistic Schrödinger

equation:

EN = [2ehc2 B(N+1/2= 1/2)]1/2.

++ "(2"!"
%% !,- 

In addition, graphene also exhibits an anomalous quantum hall effect. In classical

electromagnetism, the Hall effect arises when a magnetic field is applied perpendicular to the

surface of a solid carrying a current parallel to the surface. The Lorentz force causes positive

and negative charges to build up on opposite sides of the solid, parallel to the current,
producing a potential difference known as the Hall voltage. The direction the voltage points

determines the charge of the charge carriers in the material. The quantum Hall effect (QHE)

is identical to the classical Hall Effect except that the Hall voltage (and consequently the Hall

resistivity and the Hall conductivity) occurs only in discrete steps equal to an integer times

!. In addition to the integer quantum Hall effect, there is another effect known as the

fractional quantum Hall effect in which the Hall conductivity is equal to ! times a rational

fraction that is less well understood. In the presence of a magnetic field, graphene produces

yet another quantum Hall effect known as an anomalous quantum Hall effect. In the case of

graphene, the Hall conductivity occurs in discrete integer steps like the conventional QHE,

but is shifted by one-half of an integer as shown below in figure.

Fig 2.1

‘  
 "   # X* $
%   "
# * $
%  
 




 
 
 Graphene is an ideal system for examining the quantum Hall effect for a number of

reasons. First, graphene samples are available in such purity that the charge carrier

concentration can be tuned continuously from high concentrations of electrons to high

concentrations of holes simply by changing the gate voltage. Second, the purity of the

graphene samples is so high that the QHE can be observed even at room temperature,

whereas most materials only exhibit the QHE at much lower temperatures. Finally,

graphene¶s anomalous quantum Hall effect, by being shifted by half compared to most

systems, exhibits non-zero conductivity even as the charge carriers change from electrons to

holes (the neutrality point or the Dirac point). For most materials, as the charge carrier

concentration tends towards zero, so does the conductivity, so that there is a metal to

insulator transition at no temperatures. But graphene has shown no signs of a metal-insulator

transition even down to liquid helium temperatures.

Aside from the anomalous quantum Hall effect, one of the most exciting prospects for

graphene is that it may eventually prove useful in electronic applications

We start studying about Graphene Transistors by comparing the normal FET characteristics

to that of Graphene.

+. ,-( (34-!!!(5

A FET consists of a gate, a channel region connecting source and drain electrodes,

and a barrier separating the gate from the channel (Fig. 2a). The operation of a conventional

FET relies on the control of the channel conductivity, and thus the drain current, by a voltage,

ÊGS, applied between the gate and source. For high-speed applications, FETs should respond

quickly to variations in ÊGS; this requires short gates and fast carriers in the channel.

Unfortunately, FETs with short gates frequently suffer from degraded electrostatics and other

problems (collectively known as shortchannel effects), such as threshold-voltage roll-off,

drain-induced barrier lowering, and impaired drain-current saturation. Scaling theory predicts

that a FET with a thin barrier and a thin gate-controlled region (measured in the vertical

direction in Fig. 2a) will be robust against short-channel effects down to very short gate

lengths (measured in the horizontal direction in Fig. 2a). The possibility of having channels

that are just one atomic layer thick is perhaps the most attractive feature of graphene for use

in transistors. (Mobility, which is often considered to be graphene¶s most useful property for

applications in nanoelectronics, is discussed later.) By comparison, the channels in iii±v

HEMTs are typically 10±15 nm thick, and although silicon-on-insulator MOSFETs with

channel (that is, silicon body) thicknesses of less than 2 nm have been reported, rough

interfaces caused their mobility to deteriorate. More importantly, the body of these

MOSFETs showed thickness fluctuations that will lead to unacceptably large threshold-

voltage variations (and similar problems are expected to occur when the thickness of the

channel in a iii±v HEMT is reduced to only a few nanometres). These problems occur at

thicknesses that are many times greater than the thickness of graphene. The series resistances

between the channel and the source and drain terminals are also important, and their adverse

impact on the FET becomes more pronounced as the gate length decreases. Thus, device

engineers devote considerable effort to developing transistor designs in which short-channel

effects are suppressed and series resistances are minimized. Modern digital logic is based on

silicon complementary metal oxide semiconductor (CMOS) technology. CMOS logic gates

consist of both n- and p-channel MOSFETs that can switch between the onstate (with a large

on-current, pon, and ÊGS = }ÊDD, where ÊDD is the maximum voltage supplied to the

device) and the off-state (with a small off-current, poff, and ÊGS = 0). In the terminology of

digital logic, a gate is not the gate terminal of a transistor but a combination of two or more

transistors that can perform a certain logic operation. The value of ÊGS at which the FET is

just on the verge of switching on is the threshold voltage, ÊTh. Figure 2b shows the transfer
characteristics of an n-channel FET indicating the on-state and the off-state. Useful measures

with which to assess the switching behaviour are the sub threshold swing, V (relevant to the

sub threshold region), and the terminal transconductance, mt (relevant to the above-threshold

region). In the steady state, a certain number of the MOSFETs in a CMOS logic gate are

always switched off so that no current²except the small poff²flows through the gate14. The

ability of silicon MOSFETs to switch off enables silicon CMOS to offer extremely low static

power dissipation (which is the reason why silicon CMOS has bested all competing logic

technologies). Thus, any successor to the silicon MOSFET that is to be used in CMOS-like

logic must have excellent switching capabilities, as well as an on±off ratio, pon/poff, of

between 104 and 107. In a conventional FET, this requires semiconducting channels with a

sizeable band gap, preferably 0.4 eV or more. Moreover, n- and p-channel FETs with

symmetrical threshold voltages, that is, with ÊTh,n = íÊTh,p, are needed for proper CMOS

operation. In radiofrequency applications, however, switch-off is not required 
. In

small-signal amplifiers, for example, the transistor is operated in the on-state and small

radiofrequency signals that are to be amplified are superimposed onto the d.c. gate±source

voltage. To discuss the radiofrequency performance of FETs, I use the equivalent circuit from

Fig. 3a and focus on the cut-off frequency,

T, which is the frequency at which the magnitude

of the small-signal current gain rolls off to unity. The cut-off frequency is the most widely

used figure of merit for radiofrequency devices and is, in effect, the highest frequency at

which a FET is useful in radiofrequency applications. As can be seen from the expression for

T the cut-off frequency can be maximized by making the intrinsic transconductance, m, as

large as possible and making the drain conductance, ds, and all the capacitances and

resistances in the equivalent circuit as small as possible. However, the values of all these

quantities vary with the applied D.C. gate±source voltage, ÊGS, and the applied D.C. drain±

source voltage, ÊDS. As shown exemplarily for a typical GaAs HEMT15, 16, VDS has a
pronounced effect on the FET performance. For this transistor,
T peaks around ÊDS = 1 V,

that is, deep in the region of drain-current saturation, where m is near its peak and ds has

decreased sufficiently. For lower values of ÊDS, the device operates in the linear regime and

the cut-off frequency is low because m is small and ds is large. The bottom line for

radiofrequency performance is that although shorter gates, faster carriers and lower series

resistances all lead to higher cut-off frequencies, saturation of the drain current is essential to

reach the maximum possible operating speeds. This point is frequently missed in discussions

of transistor speeds. Drain-current saturation is also necessary to maximize the intrinsic gain,

&int = m/ ds, which has become a popular figure of merit for mixed-signal circuits.

+6,-,,!()!!!((!(

Single-layer graphene is a purely two-dimensional material. Its lattice consists of

regular hexagons with a carbon atom at each corner. The bond length between adjacent

carbon atoms, b, is 1.42 A and the lattice constant, , is 2.46 A. The first reports on this

material appeared decades ago, even before the name graphene had been coined, but it took

the pioneering 2004 paper by the Manchester group1 to spark the present explosion of

interest in the material. At present, the most popular approaches to graphene preparation are

mechanical exfoliation1, growth on metals and subsequent graphene transfer to insulating

substrates and thermal decomposition of SiC to produce so-called epitaxial graphene on top

of SiC wafers. Exfoliation is still popular for laboratory use but it is not suited to the

electronics industry, whereas the other two options both have the potential for producing

wafer-scale graphene. After the graphene has been prepared, common semiconductor

processing techniques (such as lithography, metallization and etching) can be applied to

fabricate graphene transistors. In this section, I discuss two important aspects of graphene:
the presence (or otherwise) of a band gap, and charge transport (mobility and high-field

transport) at room temperature.

+6*'#1, 

Large-area graphene is a semimetal with zero band gap. Its valence and conduction

bands are cone-shaped and meet at the K points of the Brillion zone (Fig. 4b). Because the

band gap is zero, devices with channels made of large-area graphene cannot be switches off

and therefore are not suitable for logic applications. However, the band structure of graphene

can be modified, and it is possible to open a band gap in three ways: by constraining large-

area graphene in one dimension to form graphene nanoribbons, by biasing bi-layer Graphene

and by applying strain to graphene. It has been predicted that both armchair nanoribbons and

zigzag nanoribbons (the two ideal types of nanoribbon) have a band gap that is, to a good

approximation, inversely proportional to the width of the nanoribbon. The opening of a band

gap in nanoribbons has been verified experimentally for widths down to about 1 nm, and

theory and experiments both reveal bandgaps in excess of 200 meV for widths below 20 nm

(Fig. 4c). However, it should be noted that real nanoribbons have rough edges and widths that

change along their lengths. Even modest edge disorder obliterates any difference in the

bandgap between nanoribbons with different edge geometries, and edge functionalization and

doping can also affect the bandgap. To open a bandgap useful for conventional field-effect

devices, very narrow nanoribbons with well-defined edges are needed. This represents a

serious challenge given the semiconductor processing equipment available at the moment.

Recently, nanoribbons that were uniform in width and had reduced edge roughness were

produced by µunzipping¶ carbon nanotubes45. However, even a perfect nanoribbon is not

perfect for electronics applications. In general, the larger the bandgap that opens in a

nanoribbon, the more the valence and conduction bands become parabolic (rather thancone-

shaped): this decreases the curvature around the K point and increases the effective mass of
the charge carriers46, which is likelyto decrease the mobility. Bilayer graphene is also

gapless (Fig. 4b), and its valence and conduction bands have a parabolic shape near the K

point. If an electric field is applied perpendicular to the bilayer, a bandgap opens and the

bands near the K point take on the so-called Mexican-hat shape. This opening was predicted

by theory and has been verified in experiments. Theoretical investigations have also shown

that the size of the bandgap depends on the strength of the perpendicular field and can reach

values of 200±250 meV for high fields ((1±3) × 107 V cmí1; refs ). The bandgap of large-

area single-layer epitaxial graphene is at present the subject of controversy. Although some

results suggest a zero bandgap, others report a bandgap of around 0.25 eV . The transfer

characteristics of epitaxial-Graphene MOSFETs show no switch-off, which suggests a zero

bandgap. However, a bandgap is consistently observed for epitaxial bilayer graphene. Finally,

strain has been discussed as a means of opening a band gap in large-area graphene, and the

effect of uniaxial strain on the band structure has been simulated. At present it seems that if it

is possible at all, opening a gap in this way will require a global uniaxial strain exceeding

20%, which will be difficult to achieve in practice. Moreover, little is known about the ways

in which other types of strain, such as biaxial strain and local strain, influence the band

structure of graphene. Thus, although there are a number of techniques for opening a bandgap

in graphene, they are all at the moment some way from being suitable for use in real-world

applications.

+6+c7!

The most frequently stated advantage of Graphene is its high carrier mobility at room

temperature. Mobilities of 10,000±15,000 cm2 Ví1 sí1 are routinely measured for exfoliated

graphene on SiO2-covered silicon wafers, and upper limits of between 40,000 and 70,000

cm2 Ví1 sí1 have been suggested. Moreover, in the absence of charged impurities and

ripples, mobilities of 200,000 cm2 Ví1 sí1 have been predicted, and a mobility of 106 cm2
Ví1 sí1 was recently reported for suspended graphene. For large-area graphene grown on

nickel and transferred to a substrate, mobilities greater than 3,700 cm2 Ví1 sí1 have been

measured. Finally, for epitaxial graphene on silicon carbide, the mobility depends on whether

the graphene is grown on the silicon face or the carbon face of SiC. Although graphene

grown on the carbon face has higher mobility (values of ~5,000 cm2 Ví1 sí1 have been

reported, compared with ~1,000 cm2 Ví1 sí1 for graphene grown on the silicon face), it is

easier to grow single-layer and bilayer graphene on the silicon face, which makes the silicon

face of SiC more suited for electronic applications. In early graphene MOS structures, the

mobility was affected by the use of a top-gate dielectric. However, the recent demonstration

of mobilities of around 23,000 cm2 Ví1 sí1 in top-gated Graphene MOS channels and the

observation of similar mobilities before and after top-gate formation show that high-mobility

Graphene

Fig 2.2
¢



 
 
 

Schematic of an armchair (ac) graphene nanoribbon (GNR) of length ac and width

ac. The nanoribbon shown here has ? = 9 carbon atoms along its width and thus belongs to

the 3 family, where  is an integer. 7, Band structure around the K point of (i) large-area

graphene, (ii) graphene nanoribbons, (iii) unbiased bilayer graphene, and (iv) bilayer
ð
 it

li  i l
 il
 
ð

 ð

 i
 il
 

ð
  t 

 
ð
 i  
 t l  l   iðit
l lt i
 v

B
ð
    
 i it   it
 
l l
ti
 B 
i t


ð
 ii

:ið
ð

 

 


it lt

t ti ttiitili
tti
ll

   iit  
  
 ið t   
 j t tt  
 
t  ti


 

 li t   it
l 
i t
it  t  t

 i  it  l 

t ið    ði lið

  t
it 
 
  

ð

 t   

t i
 l
t 

ðt

 
 


ð
it  t
 i l
 
 
 
t   ll it
 t 
 


l  t lt iit
t  t
 t 
t i
l i lt  
 t
l t  ð i

t
iðtlit
tit tið
tt 
i l lti
tl

t  

 iitlt itt
t
l  i l



 

Ô

 
 





 The first graphene transistor was demonstrated in 2004. But this leaked current and

could never switch it off, because electrons hopped too easily between the carbon atoms. We

have now made a graphene transistor that does not leak current that can control the flow of

just a single electron efficiently. The leak-free transistor is made from a "nano-ribbon" of

graphene less than 10 nanometres wide and just a single carbon atom thick (0.1 nm). The

device not only works at room temperature but, unlike other transistors of a similar size, it is

relatively simple to make. The ribbon at the heart of the device, as well as the surrounding

connections, can be cut from a graphene sheet using electron beam lithography - the same

method used to make silicon devices.

+8*,!%,- ((!(!
9:" ( 

Top-gated graphene transistors operating at high frequencies (GHz) have been

fabricated. The work represents a significant step towards the realization of graphene-based

electronics for high-frequency applications. Graphene is a two-dimensional (2D) material

with great potential for electronics with essentially the same lattice structure as an unwrapped

carbon nanotube, graphene shares many of the advantages of nanotubes, such as the highest

intrinsic carrier mobility at room temperature of any known materials. This makes these

carbon-based electronic materials particularly promising for high-frequency circuits.

However, due to the high impedance of a single carbon nanotube transistor, high-frequency

properties of nanotubes were investigated indirectly using various mixing techniques and

direct ac measurements of these devices at GHz frequencies were realized only recently

enabled by the larger device current in nanotube arrays. In contrast, one distinct advantage of

graphene lies in its 2D nature, so that the drive current of a graphene device, in principle, can

be easily scaled up by increasing the device channel width. This width scaling capability of

graphene is of great significance for realizing high-frequency graphene devices with

sufficient drive current for large circuits and associated measurements. Furthermore, the
l

 ð

ll   t
 i
ti   ð
 i
  itð
t i  it

tiliið llt
li l

   i t i t  i t 
 Rtl it 


 t
t ð
 i 
 iit  t ð
i i t i 
  
ð


it it
tiiti  ð
 
 t it ii ið   t
 t

  ti ð
t
it 
tt
ti
llt i



i ti  t t i t  i  it
l t i  t ið

     tð
t ð
 t
it    i  t ð
t lt
ð
 ð
t

lðt
  it ii  t ð
i   t ð
 t
it  
   t  
 it

i 
ið  
 llt i
l /   t   ti
l!"



i t l  i i t
 
 t
 ið        

t
tiðtit iiið    ti t
l ððt
ti
l!"li


i    ð
 t
it 

   t          

t 


 t iit t ð ð
t lt
ð 
 i   ti
l t t t


 t


 t   i  ti l  ti
ltt


 tð
tlðt
  
ð
tlðt #$

 
ið
%&'it
i



 

!ið
%
(
‘








 

!ið
%
#








 


!ið  %
(  t i l
 t   ð
 il t t
it  it  


 ið   ið   
 t

 
 
  
  
i
l

 li
ti 
 ið itiit i  t
t )$ *6+   
 l
    ,$$

t 
l i %
 R

 t  
 l t  t t      ð


l
 
!ið
 )B+ t ti
li
ð  
 
 l
  t ði t l t


iti it iðll
  ð


 
 
i lt  
    i


t
il
 
#$ti-  i
litð

li t

.%

ti.l%/,l
 
tit
til
 itiO  ;
t%#$0C
t

ð
ti l
t
1  t  
 i  
tið i

 ti
li
ti

l
 itið #$l 2/%M.)t itl
l i +
 i tit i t

tð t ð
ti

i2/%M. ti
li
til
 
ti
l  t. 

  t
i ti )o$ + ð
t ilt i  ð
it t   ið il

t
t
ð
tl

ð
ilt it
t . ð .l%/,it i 



 t
   t 
 t 3

#
 
tl $/#$ -/.  
 it



tt t  ttð
t


 As shown in Fig. 2.4, the source electrodes were designed to overlap the entire

graphene flake (see figure inset) in order to minimize the uncertainty in the de-embedding

process for high-frequency Sparameter measurements, as explained below.

In the device shown in Fig. 2.5, the distance between the source and drain electrodes

is 500 nm, and the top gate under laps the source-drain gap with a gate length LG of 360 nm.

The total gate width (or channel width), including both channels, is ~ 40ȝm.

Fig. 2.4 shows the optical image of the complete device layout where the standard

ground-signal-ground probing pads are realized for the gate and the drain to allow for

transition from coax to on-chip coplanar waveguide (CPW) electrodes. Measurements of dc

electrical properties of graphene devices were performed in order to gain insight into their

high-frequency response. In addition, the dc electrical characteristics were monitored at each

fabrication step so that issues affecting the final device performance could be identified.
 

 

c





 


 
 





lt i
l

t iti tltð
i
t titi

  t tð
t lt 
  i !ið

  it  t 
   t



ti )tð
t+lt
ð
t

ii
  4$$

 itt
ll/ 

titð
i
 ti
ll
il
 il tt
it 
ii
t

t""
ð
tit 
 1  

1tð
 il t

t
it  )!"+ t t
 t i i
t  lt 
 l   iti


ð
ti ð
t lt
ð til
 t  t
 ii  i t
 t i


it lt 
l

lt i tittt
 t



!ið
  t t  t t 

t iti 1     t ð
 t
it 
t


i ð
tlt
ð
1ti  t
tttð
t!"t i iit

lli


1     t 
&    t ð
t lt
ð
ð 
 
 i l
    t


t
tii tt
tt
tð
i
 ð
i t

1t
 ððt
t
t lit 
t
ti
t ið  i
 
 l
 t t  t 
t
ti  i

ð
 t
it 
 '  ið  
i  ilit 
   i  t
i ti


t
tilititit
ii
 
ti
lit t



   

t  tit t
 lt t    iit t  i

it iii t
 t t
i  tð
i

 t it 

i t
tlt i
l  ti 
ð
i



!ið
%
3





1 !ið
%
3 t   t ð
i%  
 it i 
ið  

lliðt/ lt  
ti
l!"

1
 ð l
!"ti/   

   %  i
lt t
 
 l  %$B/
  lt  t ð
t

i
 ði  4 /Ȧ Ô   Ȧ 4 %5 
 Ô i t ð
t 

it
 t
t
decreases with increasing frequency. Therefore, the 1/f dependence of current gain obtained

in Fig. 2.7 is significant because it not only validates the high-frequency measurements and

the de-embedding procedures used to extract the intrinsic GFET characteristics, but it also

suggests regular FET-like behaviours for graphene transistors as a function of frequency. One

of the important figures of merit for characterizing high-frequency transistors is the cut-off

frequency fT, defined as the frequency where the current gain becomes unity (21 = 1). In

practice, for a transistor possessing the ideal -20dB/decade slope for 21, the cut-off

frequency fT is determined by the product of 21 and frequency, i.e. f × 21(f), over the

measured frequency range. Thus, for the device shown in Fig. 2.7, the cut-off frequency fT

can be determined by either approach to be ~ 4 GHz. The high-frequency operation of the

graphene transistor is found to be highly dependent on the dc bias condition. Fig. 2.7 shows

the measured cut-off frequency fT of the GFET as a function of gate voltage. At all gate

voltages, the de-embedded current gain 21 exhibits the 1/f frequency dependence similar to

that shown in Fig.2.7 so that the cut-off frequency can be reliably determined. The -branch

of the graphene transistor is shown here because of the higher transconductance for electrons

than for holes in this device.

These results show that the high-frequency behaviour of these graphene transistors

can be described as an FET with a static, constant gate capacitance within a significant

portion of the bias range. In principle, the maximum cut-off frequency of an FET can be

improved by reducing the gate length. To investigate the length dependence of fT in graphene

devices, graphene transistors with various gate lengths down to 150 nm were fabricated and

investigated for their high-frequency operations.

All of the graphene devices studied here were prepared in one batch and on the same

chip in order to minimize the device-to-device variations introduced in the fabrication

processes. As before, mobility degradation was observed in all devices after ALD oxide
iti
 
i   
  t i 
 it   ð
t lðt
 t

  t#$ð
t!"

 t   
ið
%&'
t
i


i!ið
%
3
t
t 6lðtiitiðt
l 
   ð


t
it t
t


1  
 tð
t ð
 t
it    
i  ð
t lðt  
 i
t

 ti  ið    
 i tl 

t i  t

 

t 


 t
   ti  it  t ð
i  t i
l /    

 i iðt
 t
lit
t!"li
i   ð
i

.t

ð
t lt
ð i 
i t 
   
   t    ti
l t t  t


 t
 ð llið t l
ti  4 ð!)%5 C+

 ! t    
   t

i 
 it  
ið 
l lðt it t 
lið   7 / %   t

!" t i  
 .  
  t    
 ið
 %& ' 
 
   


#$ð
t ð
 t
it  t
liið t t
t   t
t   ð
 t
it 


  lt
lii
tt
ti tið ilit ð

   iðt

i
 i
ti  
  t   
 
ið ' 
 
i  

ð
!"it
ð
tlðt j t#$

i ilit %$$$%/6







  < v 
 

!ið
%
3
Ô?

 Sub-10nm wide graphene Nano ribbon field-effect transistors (GNRFETs) are studied

systematically. All sub-10nm GNRs afforded semiconducting FETs without exception, with
6
p /p ratio up to 10 and on-state current density as high as ~2000ȝA/ȝm. We estimated


2
carrier mobility ~200cm /Vs and scattering mean free path ~10nm in sub-10nm GNRs.

Scattering mechanisms by edges, acoustic phonon and defects are discussed. The sub-10nm

GNRFETs are comparable to small diameter (”~1.2nm) carbon nanotube FETs with Pd

contacts in on-state current density and p /p ratio, but have the advantage of producing all-


semiconducting devices.

Since our GNRFETs were Schottky barrier (SB) type FETs where the current was

modulated by carrier tunnelling probability through SB at contacts, high work function metal

Pd was used to minimize the SB height for holes in p-type transistors. In fact we used Ti/Au

as contact and found that Pd did give higher p in device with similar dimensions. 10nm SiO
 2

gate dielectrics was also important to achieve higher p because it significantly reduced SB


width at contacts compared to 300nm in previous work

For wide GNR devices, they all showed metallic behaviour because of vanishingly

small band gaps. Compared to sub-10nm GNRFETs with similar channel length, the current

density in wide GNR devices was usually higher (~3000ȝA/ȝm at Ê =1V for the device in.


We note that our wide GNRs showed relatively weak gate dependence in transfer

characteristics, likely due to interaction between layers. The Dirac point was usually not

observed around zero gate bias, indicating p-doping effects at the edges or by physisorbed

species during the chemical treatment steps.

 

!ið
%
3


 




 


Xt

llt2R!"
ttt
lliti  
liit

 
ið  it it t ti
l llið

  t ti
l l  t t


lliti   
 liit 
 ið
 iðl 
lliti 
l
 i
l t
t

) iitlð
tiB+


.   t ð 
tt ið
t  /-/ZB- ii 

 
ll i t  t 

t C t
ð
tt iðil
ti
t
ðt
i  ð

 

 
i 
ttl
  i t 
l
 i
ll i   t   t 
i
 .t ið 
i

i
t   ll
ti
tt ið
tðiið t
l
tt 
t t

 t
lti
ll
t


i 
 



/   $ 2R!"
 
lli tið 2

l t
it  t
t




l i   
 t 
ll i
t  
 
t  i
 2R
 il


i
t   t 2
lt i

 ! t     l    l i
tið t
ti

t t  t ð  2R
 l
titt  
 2R!"


itð
ti   lt
ti ið ilt i
  
ðð i 
l lðt 
lið i
l

t
itt lt t
tiið p
i
l t ll






 

  v

 

X  t lt i t
 t  it 
 ð
 iðl lt  t
it


 i it  
 ð
 il
 t t  
 
i lt  i
 t


ð
t iti

1tilt t
ti
llt 
lt l
t
lð
ð
t



iti
l
ð
t
t llið liði
t ðlti ti 

ð
tlt
ðii
tiðt  l
lit
tit
i 

Xitið
t ð


l   t t llið ð
 t 
 i t t iti
   t C l

l
 

 !  C l i
 
 t i i  t i

 ið
ti )i

 
i   ið
ti+  t
t
 
ðið  ð   8 ,
( 


ti
t


t iti ð
l  tt iti 
 8$



!ið
%
9
Ô
  
 


!ið
%
:






 
 
 

Here we investigate a fully tuneable single electron transistor (SET) that consists of a

width modulated grapheme structure exhibiting spatially separated transport gaps. SETs

consist of a conducting island connected by tunnelling barriers to two conducting leads.

Electronic transport through the device can be blocked by Coulomb interaction for

temperatures and bias voltages lower than the characteristic energy required to add an

electron to the island. The sample is fabricated based on single-layer grapheme flakes

obtained from mechanical exfoliation of bulk graphite. These flakes are deposited on a highly

doped silicon substrate with a 295 nm silicon oxide layer. Electron beam (e-beam)

lithography is used for patterning the isolated graphene flake by subsequent Ar/O2 reactive

ion etching. Finally, an additional e-beam and lift-off step is performed to pattern Ti/Au (2

nm/50 nm) electrodes.


‘' p   #


 


  
   
 


   
  
  c  #  
 

 


  ??
?¢ p

   


  ?¢ #   #   ??

#      

In conclusion, we have fabricated and characterized a fully tuneable graphene single

electron transistor based on an etched width-modulated graphene nanostructure with lateral

graphene gates. Its functionality was demonstrated by observing electrostatic control over the

tunnelling barriers. From Coulomb diamond measurements it was estimated that the charging

energy of the grapheme island is 3.4 meV, compatible with its lithographic dimensions.
These results give detailed insights into tuneable graphene quantum dot devices and open the

way to study graphene quantum dots with smaller dimensions and at lower temperatures.

+8. (% - !(! (  ,- # %% ! ((!( 4!-

 ! !(

Graphene field-effect transistors with Co contacts as source and drain electrodes show

anomalous distorted transfer characteristics. The anomaly appears only in short-channel

devices (shorter than approximately 3 ȝm) and originates from a contact-induced effect. Band

alteration of a graphene channel by the contacts is discussed as a possible mechanism for the

anomalous characteristics observed.

In order to construct such electronic devices, metallic materials should make a contact

with the grapheme layers. The effect of metal contacts can be detected using the structure of a

field-effect transistor (FET) and measuring the transfer characteristics (drain current, D I , vs.

gate voltage, G V , characteristics). For instance, the difference between the drain currents of

Graphene FETs at exactly opposite charge densities (at the same carrier densities with

opposite charge polarities) has been explained by a metal-contact effect. Charge transfer from

metal to graphene leads to a p-p, n-n or p-n junction in graphene, depending on the polarity of

carriers in the bulk of the graphene sheet. An additional resistance arises as a result of the

density step created along the graphene channel, which causes asymmetry.

In this we analyse the effect of metal contacts on the transfer characteristics of

graphene FETs. In particular, the choice of metal and the gap between the metal contacts

(source and drain electrodes) have been examined by employing a FET structure. It was

found that graphene FETs with Co contacts and short channels display anomalous distorted

transfer characteristics, indicating that the anomaly originates from Co contacts.

 

!ið
%
$










 l
      t
 iðl i  t
t it
 ,$$  ti

t 
l i l
  ið ti
l 
i
l  li
ti

 t
tið ð
it  t
l

 
   
it  ;

C 
ti

ti  t ð
 l
 

  t i t 
 i
tl  
ti   i i  
ti i

t
ið 
l
  t it
tti tti
lt
t


Mt
l lt  )C
 . +  
 i
t t t ð
 l
   lt  


litð

li t ti 

! t. lt #tiC 
it



i l
   i  t .  iti

  lt 
 i
t i ti t  

 tt
l

ti   #$
  !" 

t iti   
  i l 
 
t 

t
t 



 1+**







 () 
!‘ 
     *+
,

1+*+







 ()  
      
,

The transfer characteristics are shown in Figs. 1(b) and 1(c) for Cr/Au and Co

source/drain electrodes, respectively. Cr/Au is a conventionally used metallic material for

electronic devices, and Co is a popular material for spin-electronic devices as a source of

spin-polarized current. Although the graphene FET with Cr/Au contacts exhibits

conventional transfer characteristics, as widely reported previously, that with the Co contacts

displays anomalous distorted characteristics, especially in the negatively gated region.

The shorter channel results in lower channel resistance, and the resistance originating

from the contacts should have a more dominant effect on the two-terminal resistance. In fact,
the resistances at the D I minima are not proportional to the ratio of channel length to channel

width, and thus the contact-related effects contribute to the device resistance.


1+*.

  





 
 ()     

 ,
In the wide-ranging transfer characteristics of the 3 ȝm channel device decreases in

the current compared with ordinary transfer characteristics can be seen at gate voltages of -70

and +30 V in addition to the minimum at a gate voltage of +2 V. The minimum at +2 V is

considered to be the charge neutrality point (the so-called Dirac point); the other two

anomalous points are therefore a consequence of the metal contacts.

Another possible mechanism is the diffusion of Co atoms into/onto graphene

channels. In a single charge tunnelling device of a single CdTe Nano rod with Cr/Pd contacts,

a chemical transformation was found to occur by the diffusion of Pd atoms 20-30 nm into the

nanorod.20 However, the robust honeycomb lattice structure of graphene and the possibly

strong chemical interactions at Co/graphene interfaces should prevent Co atoms from

diffusing a long distance into and onto graphene channels. In summary, the effect of metallic

electrode materials contacting graphene channel layers was studied using FET structures.

Cr/Au and Co contacts were investigated, and it was found that graphene FETs with Co

contacts and short channels exhibit distorted transfer characteristics that have two peaks at -

0.20 and +0.13 ev. The present study ascertained the metal-induced alteration of the FET
characteristics of graphene. These results indicate particularly crucial issues for the

development of future graphene microelectronics that consist of short-channel devices.

+86,!=,- ((!( "7(!!(

This describes the behaviour of top gated transistors fabricated using carbon,

particularly epitaxial graphene on SiC, as the active material. In the past decade research has

identified carbon-based electronics as a possible alternative to silicon-based electronics. This

enthusiasm was spurred by high carbon nanotube carrier motilities. However, nanotube

production, placement, and control are all serious issues. Graphene, a thin sheet of graphitic

carbon, can overcome some of these problems and therefore is a promising new electronic

material.

Although graphene devices have been built before, in this work we provide the first

demonstration and systematic evaluation of arrays of a large number of transistors entirely

produced using standard microelectronics methods. Graphene devices presented feature high-

k dielectric, motilities up to 5000 cm2/Vs and, Ion/Ioff ratios of up to 7, and are methodically

analysed to provide insight into the substrate properties. Typical of graphene, these micron-

scale devices have negligible band gaps and therefore large leakage currents.


+>7 ! ((% (

We obtained the graphene suspension in Pm PV/DCE solution. We soaked the 10nm

++
SiO /p Si substrate with pre-patterned metal markers (2nm Ti/20nm Au) in the solution for
2

~20mins, rinsed with isopropanol and blew dry with argon. Then the chip was calcined in air

at 350ºC for ~10mins and annealed in vacuum at 600ºC for ~10mins to further clean the

surface. We used tapping mode AFM to find GNRs around the pre-patterned markers and

recorded the location. Next we used electron beam lithography to pattern the S/D of the

devices. 20nm Pd was then thermally evaporated as contact metal followed by a standard lift-

off process. Finally, we annealed the device in argon at 200ºC for ~15mins to improve the

contact.

+>*c!(#"7(!!,!

Graphitic films on SiC substrates were prepared by solid-state decomposition of

single crystal 4HSiC (0001) in vacuum. The method involves an inductively heated vacuum

furnace in which 3.5 mm X 4.5 mm X 0.3 mm SiC chips, are heated to about 1400 °C. In this

process, Si sublimes to produce carbon-rich surfaces that subsequently graphitize. The

graphitization produces epitaxial ordered stacked layers of graphene, with a high structural

coherence length. Figure 1 shows this multi-layered epitaxial graphene (MEG) at the

different stages of preparation.

 

!ið
%
(
¢ 



Ô! 

 !


- i  t itð
ti /iC i   

t i ið ti
l
 .!M


 t
tM1
1tii t
tttt
tiCitt iti<Ci

t=$$$>i ti


t j t tt
tt
tii
tt i

C
Ci l
iðtiCl
tti 
iðt
t
ti l

lðt)$$$+l



il
  ltitit
tilit i
t
i
llti



t
t i
t
i
lltC
 ið 


!ið
%
#





  


 


 """

 A typical SiC wafer will have a Si-face in the front with a [0001] normal, and a C-

face in the back with a [000-1] normal. During silicon sublimation graphene layers are

generated on both faces of the SiC wafer, however the film generated on the C-face has

different properties from the film generated on the Si-face.

+>+$) !1!3 

After characterization, G/SiC chips were mounted on 150-mm silicon carrier wafers

using epoxy bonding. This was done so that the silicon fabrication tools are able to process

the small chips. First, alignment marks were defined with standard g-line lithography and

etched into the G/SiC with Cl2/He plasma etches. These marks are required because the

active MEG layer is too difficult to see optically for consistent alignment of subsequent

layers. Following the alignment mark etches, the resist was stripped in 80°C sulphuric acid;

this strip did not affect the appearance or resistivity of the MEG layer. Next, the active MEG

layer was patterned using a low energy O2 plasma etches. The source/drain layers were

deposited directly on the MEG film layer and consisted of 2 nm Ti and 20 nm of Pt., defined

using a lift off process. A 40 nm HfO2 layer was then deposited over the entire chip, using

thermal evaporation. The HfO2 film was verified to have a dielectric constant of 23 via a

capacitive measurement of a finished device. Finally, a 100 nm Al gate was deposited and

defined using lift-off. The AFM of a finished device is shown in Figure 2.4.

The mask pattern used in this experiment contained approximately 100 devices, with

different gate lengths, graphene widths, and alignment conditions. The nominal device was a

one with a source to drain spacing of 10 ȝm, a graphene width of 5 ȝm, and a 15 ȝm gate

overlapping the source and drain by 2.5 ȝm on each face. Hundreds of transistors where

fabricated, with functional yield as high as 95% for some samples.

 


 v
  
 

  v

.lt ð  iið ð
 
 lt i
 
 t
l    it 



 titi tlð

 Mii   ti 
 t   
 i t

i 
i
ilit 
t  t ll

t
l ð
t ilt i  t   
 ' 

t i ll itð
ti        ð
 i  i l
tiðiC t
t i


t t
 
ið ð
 tlð il

  
i  i   
 ð


tlð i l
l ilit

 " iti  lii
  ittiliti  t #$$$

%/ 
 
i

 i i
l 
 $ ti tt  t
 ili tlð i


 
 
   tii
ti

1t 6t  

lt tt
t
t t  ð

itið
ti
   tii
ti ð
 i ill 
tiliti   $$$$

%/
ð 
ttt
lt
ð
tlðitl
 

ð

t 

inability to turn off conduction below a certain level. It is likely that some method of

obtaining an on/off ratio for current in the hundreds will be demonstrated in the near future.



 .
 

.*(! ,, !(

Graphene¶s high conductivity and its unusual electronic properties may lead to

unexpected advances in processor and electronic technologies. After carbon nanotubes have

so far failed to revolutionize the field, scientists are cautious in advertising the possible future

applications of graphene. For graphene, it is too early to tell whether graphene will

significantly affect the field of commercial electronics, but it¶s small scale and unusual

properties may contribute to the development of nanoscopic electronic components or

quantum computing. Graphene has been used to produce a functional transistor even though

this initial proof of concept transistor leaks electrons and is highly inefficient.

.+ -"!"%,-

Scientists acknowledge that graphene will be an important material in future

technologies. It might be used to store hydrogen in fuel cells or in batteries as electrodes. It

may serve a use in the production of ultra-thin fabrics that require great strength. If glues are

used between the graphene layers, it might be possible to assemble very strong materials. Its

chemistry can be controlled to change its electrical properties to be conducting, insulating or

semiconducting. It may even prove useful in the possible development of quantum

computing. Graphene¶s immense potential is especially exciting considering how easy and

cheap it is to produce.
..  "(

Although promising, graphene based electronics faces many obstacles before it can

become a competitive technology. Minimum conduction has to be decreased, device to

device variability has to be controlled, and a stable gate dielectric must be found. However

the chip level integration of hundreds of graphene devices on insulating SiC substrates is a

step towards making graphene technology possible. The main driver for a graphene

technology is clearly mobility.

This seminar report represents the whole knowledge of Graphene Transistor. In

everywhere in industries programmable logic controller is used. We can say that now a days

the grapheme transistor become the back bone of the modern electronic field.

However, many details about the potential performance of graphene transistors in real

applications remain unclear. Here the properties of graphene that are relevant to electron

devices, discuss the trade-offs among these properties and examine their effects on the

performance of graphene transistors in both logic and radiofrequency applications. I conclude

that the excellent mobility of graphene may not, as is often assumed, be its most compelling

feature from a device perspective. Rather, it may be the possibility of making devices with

channels that are extremely thin that will allow Graphene field-effect transistors to be scaled

to shorter channel lengths and higher speeds without encountering the adverse short channel

effects that restrict the performance of existing devices. Outstanding challenges for graphene

transistors include opening a sizeable and well-defined band gap in graphene, making large-
area graphene transistors that operate in the current saturation regime and fabricating

graphene Nano ribbons with well-defined widths and clean edges.