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PLL:

-->PLL is a phase lock loop


-->PLL is used for the purpose of generating the clock pulse.
-->It is an internal clock generator circuits
SFR Functions:
->PLLCFG->PLL Configuration
->PLLCON->PLL Control
->PLLSTAT->PLL Status register
->PLL FEED->PLL Feeding Register

PLLCON:
->It is a 8 bit register
->PLLE->PLL Enable
->PLLC->PLL Connect
PLLCON=0x03;
PLLCON=0x01;

PLLCFG:
->It is a 8 bit register
->MSEL->Multiplier
->PSEL->Divider
PLLCFG=0x24;

VPDIV-->VPDivider
VPDIV=0x00->1/4->15MHz
VPDIV=0x01->CPU(same as peripherals)
VPDIV->0x02->1/2->30MHz
VPDIV->0x03->Reserved

PLLFEED:
->It is a 8bit
->It is used for resetting purpose
PLLFEED=0x00->(Resetting)
PLLFEED=0xAA
PLLFEED=0x55 (Default Register)
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Programs for Timerd
#include<lpc21xx.h>

# define PRESCALAR 60000 // define prescalar as 60000

void pll();
void timer0_ini();
void delay(unsigned long int ms);

int main()
{
PINSEL0=0x00000000; // select gpio pin
IO0DIR=0XFFFFFFFF; // make gpio as output pin
pll(); // calling pll function
timer0_ini(); // calling timer function
while(1)
{
IO0SET=0X01; // high level
delay(0x0000000F); // delay
using timer 0
IO0CLR=0X01; // low level
delay(0x0000000F); // delay
using timer 0
}
return 0;

void pll()
{
//PLL IS CONFIGURED TO GET 60HZ pCLK
PLLCFG=0X24; // SET PSEL=2 AND MSEL=5
PLLCON=0X01; //PLL IS ACTIVE BUT NOT YET CONNECT
PLLFEED=0XAA; //FEED SEQUENCE
PLLFEED=0X55; //FEED SEQUENCE
while((PLLSTAT & 0X40)==0); //WAIT FOR FEED SEQUENCE TO
BE INSERTED
PLLCON=0X03; // PLL HAS BEEN ACTIVE AND BEING
CONNECTRD
VPBDIV=0X00; // SET PCLK SAME AS FCCLK
PLLFEED=0XAA; //FEED SEQUENCE
PLLFEED=0X55; //FEED SEQUENCE
}

void timer0_ini()
{
T0TCR=0X00; // to stop timer
T0PR=PRESCALAR-1; //load the timer value
T0TCR=0X02; //reset timer
}

void delay(unsigned long int ms)


{
T0TC=0x00000000; // t0 reset timer counting
T0TCR=0X02; // reset the timer
T0TCR=0X01; // start timer
//while(T0TC<=ms); // check the condition
T0TCR=0X00; // stop timer
}
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