Beruflich Dokumente
Kultur Dokumente
B.Tech
Electronics and Communication Engineering
Contact No.:- +91-7004158808
E-mail: sskk2428@gmail.com
CAREER OBJECTIVE:
I am looking forward to join the organization and work hard in order to complete the
objectives assigned to me.
EDUCATIONAL QUALIFICATIONS:
TECHNICAL SKILLS:
• HDL Language : Verilog (Data types, Types of Modelling,
Procedural Blocks ,UDP, Tasks and
Functions).
• HVL Language : System Verilog((Data types, Oops,
Interface, Randomization, Coverage,
Assertions),
UVM(Sound Knowledge).
• Scripting Language : Shell(Data types, Operators, Conditional
Statements, Loops, Sub routine),
Perl(Data types, Operators, Conditional
Statements, Loops, Sub routine).
• FPGA : Spartan 3E
• Software : Xilinx ISE Design Suite 14.5
• Protocol : AHB_LITE
• Operating Systems : Windows, Linux.
• Programming Languages : C (Data types, Conditional statements,
Loops, Pointers, Functions, Structures),
C++ ( Classes and Objects, Constructors
and Destructors, Functions, Inheritance,
Polymorphism, Operator overloading),
Python (Statements, Methods and
functions, Object oriented programming
in python, Error handling).
• Tools:
➢ Questasim 10.2c
➢ Modelsim
➢ Pyxis Layout and Simulation
Project:
1.PG:DVLSI: AMBA_3_AHB_LITE_PROTOCOL
.
• Description: Here we did single transaction , undefined transaction ,increment
transfer and wrap transfer.
• Tool used: EDA playground (Online HDL Development Environment) and Questa
Sim.
• Language used: Universal Verification Methodology (UVM).
SOFT SKILLS:
• Reliable
• Hard working
• Team work
• Time Management
PERSONAL DETAILS:
Date of Birth: 24th May 1997
DECLARATION
I hereby declare that the information produced above is true and to the best of my
belief and knowledge.
Sudhanshu Shekhar