Digital Design & Basic CMOS

Interview Series Level-1

1) The minimum number of 2 to 1 Multiplexers required for implementing the Boolean function

F (P, Q, R) = P’Q’R’ + PQ’R +PQR+P’Q’R+ Q’R

A) 5
B) 4
C) 3
D) 2

2) The boolean function F(A,B,C,D) = M(0,1,2,4,6,9,11,15) can be simplified to

A) A’D’+B’C’D+ACD
B) A’D’+A’B’C’+ACD
C) AD’+ABC’+A’BD
D) AD’+A’CD+BC’D

3) The minimum number of 2-input NAND gates required for implementing the
Boolean function F(X, Y, Z) = M (0, 3) is ____________
A) 9
B) 6
C) 8
D) 7

4) Consider the following circuit diagram which is CMOS logic. The output function F of this
circuit will be equal to

A) ∑m(3,5)
B) ∑m (3, 6)
C) ∑m (0, 3)
D) ∑m (1, 6)
6) Minimum number of NAND gates required to implement the function F = (X’+Y’). (Z+W)

A) 3
B) 4
C) 5
D) 6

7) For the circuit shown below, the output F is given by

A) 1
B) 0
C) X
D) X’

8) The logic function implemented by the circuit below is (ground implies a logic "0"
A) F= AND(P,Q)
B) F= OR(P,Q)
C) F= XOR(P,Q)
D) F= XNOR(P,Q)

9) In the circuit shown below, the output

expression Y is

A) A’B’+C’
B) (A+B).C
C) (A’+B’).C’
D) AB+C
10) What is the Boolean expression for the output f of the combinational logic circuit of?
A) (Q+R)’
B) (P+Q)’
C) (P+R)
D) (P+Q+R)’

11) Which is following is correct?

12) Let the number the number of NAND gates required to generate a half –adder is X number
of NOR gates required to generate the full-adder is Y. then the value of 2X+ Y =?
A) 15
B) 8
C) 19
D) 13

13) Simplify the Karnaugh map given below

A) A+B’
B) A+C’
C) A’+C’
D) A’+C
14) Let r denote the number system radix. The radix value of r satisfy the equation
√ (121) r = (11) r is/are
A) Decimal 10
B) Decimal 11
C) Decimal 10 & 11
D) Any value > 2

15) PQ +P’QR+P’QR’S Simplifies as:

A) PQ+QR+QS
B) P+Q+R+S
C) PQRS
D) Q(R+S)

16) A’ (A+B) + (B+A) (A+B’) Simplifies as:

A) AB
B) A
C) A+B

D) D) 1

17) Consider the logic circuit shown in this figure & implement the Boolean expression for F.
A) X’Y’Z’+XY+Y’Z
B) X’YZ’+XZ+Y’Z
C) X’YZ’+XY+Y’Z
D) X’Y’Z’+XZ+Y’Z

18) What are the minimum number of 2 to 1 Multiplexers required to implement 2 input AND
gate & 2 input Ex-OR gate?
A) 1 and 2
B) 1 and 3
C) 1 and 1
D) 2 and 2
19) The logic function implemented by the following circuit at the terminal OUT is
A) P NOR Q
B) P NAND Q
C) P OR Q
D) P AND Q

20) For the circuit shown, the counter state (Q1 Q0) follows the sequence
A) 00, 01,10,11,00…
B) 00, 01,10,00,01…
C) 00, 01,11,00,01…
D) 00, 10,11,00,10…

- Deepak Kumar