Time-Overcurrent Protection Device

PS 431

Version -302 -401 -602

 ! Warning
When electrical equipment is in operation dangerous voltage will be present in certain parts of the
equipment. Failure to observe warning notices, incorrect use or improper use may endanger
personnel and equipment and cause personal injury or physical damage.

Proper and safe operation of this device depends on appropriate shipping and handling, proper
storage, installation and commissioning, and on careful operation, maintenance and servicing.

For this reason only qualified personnel may work on or operate this device.

Qualified Personnel
are individuals who

o are familiar with the installation, commissioning and operation of the device and of the system to which it is being
connected;

o are able to perform switching operations in accordance with safety engineering standards and are authorized to
energize and de-energize equipment and to isolate, ground and label it;

o are trained in the care and use of safety apparatus in accordance with safety engineering standards;

o are trained in emergency procedures (first aid).

Note
The operating manual for this device gives instructions for its installation, commissioning and operation. However, the
manual cannot cover all conceivable circumstances or include detailed information on all topics. In the event of questions
or specific problems, do not take any action without proper authorization. Contact the appropriate AEG technical sales
office and request the necessary information.

Any agreements, commitments, and legal relationships and any obligations on the part of AEG, including settlement of
warranties, result solely from the applicable purchase contract, which is not affected by the contents of the operating
manual.

2 89431-302-401-602 / SLT.12.04950 EN
Modifications After Going to Press

89431-302-401-602 / SLT.12.04950 EN 3
4 89431-302-401-602 / SLT.12.04950 EN
Table of Contents

1 Application and Scope 7 6 Control 39

6.1 Display and Keyboard 39
2 Technical Data 8 6.2 Address Selection 40
2.1 Conformity Statement 8 6.3 Change-Enabling Function 40
2.2 General Data 8 6.4 Changing Settings 41
2.3 Tests 8 6.5 Memory Readout 42
2.3.1 Type Tests 8 6.5.1 Signal Memory Readout 42
2.3.2 Routine Tests 9 6.5.2 Monitoring Signal Memory Readout 43
2.4 Environmental Conditions 9 6.6 Resetting 44
2.5 Inputs and Outputs 10 6.7 Password-Protected Control Operations 45
2.6 Interfaces 10 6.8 Keyboard Lock 46
2.7 Information Output 10
2.8 Settings 11 7 Settings 47
2.9 Deviations 11 7.1 Device Identification 47
2.10 Power Supply 11 7.1.1 Ordering Information 47
7.1.2 Design Version 48
3 Operation 12 7.2 Configuration Parameters 48
3.1 Modular Structure 12 7.2.1 Control Interfaces 48
3.2 Man-Machine Communication 12 7.2.2 Binary Inputs 48
3.3 Operating Modes 13 7.2.3 Binary Outputs 49
3.4 Definite-time overcurrent protection 15 7.2.4 LED Indicators 49
(DTOC) 7.3 Function Parameters 49
3.5 Inverse-time overcurrent protection 16 7.3.1 Global 49
(IDMT) 7.3.2 Definite-time overcurrent protection 50
3.6 Blocking Logic 20 (DTOC)
3.6.1 Application to Busbar Protection by 20 7.3.3 Inverse-time overcurrent protection (IDMT) 50
‘Reverse Interlocking’ 7.3.4 Supplementary Functions 51
3.7 Circuit-Breaker Failure Protection (CBF) 22
3.8 Measuring Circuit Monitoring 22 8 Information and Control Functions 52
3.9 Tripping Logic 23 8.1 Measured Values 52
3.10 Output Relay Blocking 25 8.2 Signals 52
3.11 Operating Data Measurement 25 8.3 Counters 53
3.12 Fault Recording 26 8.4 Control and Testing 53
3.12.1 Fault Logging 27
3.12.2 Measured Fault Data 27
9 Commissioning 54
3.13 Self-Monitoring and Fault Diagnosis 28

10 Troubleshooting 57
4 Design 30
11 Maintenance 58
5 Installation and Connection 33
5.1 Unpacking and Packing 33 60
12 Storage
5.2 Checking the Nominal Data and the 33
Design Type 61
13 Accessories and Spare Parts
5.3 Location Requirements 33
5.4 Installation 34 62
14 Ordering Information
5.5 Protective and System Grounding 36
5.6 Connections 36 Appendix 63
5.6.1 Connecting the Measuring and Auxiliary 36
Voltage Circuits
5.6.2 Connecting the Binary Control Inputs 37
5.6.3 Connecting the PC Interface 37

89431-302-401-602 / SLT.12.04950 EN 5
6 89431-302-401-602 / SLT.12.04950 EN
1 Application and Scope

The numerical time-overcurrent protection device PS 431
may be used both for inverse-time (IDMT) and definite-time
short-circuit protection (DTOC) and may also be employed
as backup protection for differential or distance protection
devices.
With its measuring inputs in the three phases and in the
residual current path, the protection device is used in
networks with isolated neutral, resonant grounding or
impedance neutral grounding.
The PS 431 design includes a universal case which is
equally suitable for wall surface or flush panel mounting
owing to reversible connector blocks together with
adjustable mounting brackets.
The auxiliary supply voltage can be switched internally (by
means of a plug-in jumper) from 110 to 250 V DC to the
range 24 to 60 V DC.
Due to the frequency adaptability (50 / 60 Hz), the current
input transformers with taps for 1 A and 5 A and due to the
case design concept, optimum use and versatility is
realized with a single design version.
In the definite time delay short-circuit protection mode
(DTOC mode: definite-time overcurrent protection) the
protection device has the following protective functions:
¨ Four-pole measurement (A, B, C, N)
¨ Phase-selective phase current timer stage
¨ Time-lag high-set phase current timer stage
In the inverse time delay short-circuit protection mode
(IDMT mode: inverse-time overcurrent protection) the
protection device has the following protective functions:
¨ All the protective functions available in the DTOC mode
(listed above).
¨ Time-dependent phase current IDMT timer stage with a
selection of tripping characteristics according to
IEC 255 or BS 142. Normally inverse, very inverse,
extremely inverse, long-time ground fault or RI inverse
characteristics may be selected.
¨ Time-dependent residual current IDMT timer stage with
a selection of tripping characteristics as for the phase
current IDMT timer stage.
Besides the protective functions listed above, as well as
comprehensive self-monitoring and fault diagnosis, the
following functions are always available in the PS 431 for
optimum fault evaluation and system management:
¨ Operating data measurement
¨ Event counting
¨ Fault data measurement
¨ Fault logging
Information is exchanged through the integrated local
control panel. Parameters can also be set via the serial PC
interface.

¨ Residual current timer stage with separate setting

capability

¨ Time-lag high-set residual current timer stage

¨ Time-lag general starting signal

¨ Tripping matrix

¨ Optional latching of the individual tripping criteria

¨ Two signal inputs

¨ Four signal output relays

¨ Reverse interlocking capability

¨ Circuit breaker failure protection

¨ Measuring circuit monitoring

89431-302-401-602 / SLTS.12.04950 EN 7
2 Technical Data

2.1 Conformity Statement 2.3 Tests

Applicable to the PS 431, version -302 -602. 2.3.1 Type Tests

The product designated as "Time-Overcurrent Protection All tests according to EN 60255-6§ and
Device PS 431" has been developed and manufactured in DIN 57 435 Part 303
conformity with the international standard EN 60255-6 and
in accordance with the EMC Directive and the Low Voltage Electromagnetic Compatibility (EMC)
Directive issued by the European Community.
Interference suppression
According to EN 55022 and DIN VDE 0878 Part 3,
2.2 General Data class B

Design 1 MHz burst disturbance test

Case suitable for surface or flush mounting According to IEC 255§ Part 22-1, class III
Common mode test voltage: 2.5 kV
Installation position Differential test voltage: 1.0 kV
Vertical ± 30° Test duration: >2s
Source impedance: 200 Ω
Degree of device protection
IP 51 according to DIN VDE 0470 and EN 60259 or Immunity to electrostatic discharge
IEC 529 According to EN 60801§ Part 2, severity level 3
Contact discharge,
Weight Single discharges: > 10
Approx. 3.4 kg Holding time: >5s
Test voltage: 6 kV
Dimensions and connections Test generator: 50 to 100 MΩ, 150 pF/330 Ω
See dimensional drawings (Chapter 4) and terminal
connection diagrams (Chapter 5) Immunity to radiated electromagnetic energy
According to ENV 50140§, level 3
PC interface Antenna distance to tested device: > 1 m on all sides
Connector DIN 41 652, type D-Sub, 9-pin Test field strength, frequ. band 80 to 1000 MHz: 10 V/m
A special connecting cable is required for electrical Test using AM: 1 kHz / 80 %
isolation. Single test at 900 MHz: AM 200 Hz / 100 %

Connections Electrical fast transient / burst requirements

Threaded terminal ends M4, According to IEC 801-4, test severity level 3
self-centering with wire protection for conductor cross- Rise time of one pulse: 5 ns
sections from 0.5 mm² to 6 mm² or 2 × 2.5 mm² Impulse duration (50% value): 50 ns
Amplitude: 2 kV / 1 kV
Creepage distances and clearances Burst duration: 15 ms
According to IEC 255-5, series C Burst period: 300 ms
Source impedance: 50 Ω

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2 Technical Data
(continued)

Surge immunity test Mechanical Robustness

According to IEC 1000-4-5, test level 3
Testing of power supply circuits, Vibration test
unsymmetrically / symmetrically operated lines According to IEC 255-21-1§, test severity class 1
Open-circuit voltage front time / Frequency range, in operation:
/ time to half-value: 1.2 / 50 µs 10 to 60 Hz, 0.035 mm,
Short-circuit current front time / 60 to 150 Hz, 0.5 g
/ time to half-value: 8 / 20 µs Frequency range, during transport:
Amplitude: 1 / 2 kV 10 to 150 Hz, 1 g
Pulse frequency: > 5 / min
Source impedance: 12 / 42 Ω Shock response and withstand test, bump test
According to IEC 255-21-2§, test severity class 1
Power frequency magnetic field immunity Acceleration: 5 g/15 g
According to EN 61000-4-8§, level 4 Pulse duration: 11 ms
Frequency: 50 Hz
Test field strength: 30 A/m Seismic test
According to EN 60255-21-3§, test procedure A, class 1
Alternating component (ripple) in d.c. auxiliary energizing 5 to 8 Hz, 3.5/1.5 mm,
quantity of measuring relays 8 to 35 Hz, 10/5 m/s2
According to IEC 255-11 3 × 1 cycle
12%

Insulation
2.3.2 Routine Test
Voltage test
According to IEC 255-5 All tests according to EN 60255-6§ and
2 kV AC, 60 s DIN 57 435 Part 303
For the voltage test of the power supply inputs, direct
voltage (2.8 kV DC) must be used. Additional thermal test
The PC interface must not be subjected to the voltage test. 100 % controlled thermal endurance test, inputs loaded

Impulse voltage withstand test

According to IEC 255-5 2.4 Environmental Conditions
Front time: 1.2 µs
Time to half-value: 50 µs Allowable ambient temperatures
Peak value: 5 kV Operating temp.:
Source impedance: 500 Ω - 5 °C to + 55 °C
Storage temp.:
- 25 °C to + 55 °C
Shipping temp.:
- 25 °C to + 70 °C

Ambient humidity range

Relative humidity to preclude any condensation;
45 to 75 % (annual mean)

____________________________________________
Key:
§
For this EN, ENV or IEC standard, the DIN EN, DINV
ENV or DIN IEC edition, respectively, was used in the test.

89431-302-401-602 / SLTS.12.04950 EN 9
2 Technical Data
(continued)

2.5 Inputs and Outputs 2.6 Interfaces

Measurement Inputs Local control panel

Input/output of protection data:
Current via six keys and two four-digit displays

Nominal current Inom: 1 A and 5 A AC State and fault indications

8 LED indicators
Nominal consumption: < 0.3 VA per phase at Inom (2 permanently assigned, 6 freely configurable)

Load rating: Function assignment:

continuous: 4 Inom See address list (Appendix C)
for 10 s: 30 Inom
for 1 s: 100 Inom PC interface
Baud rate: 4800 Baud
Nominal surge current: 250 Inom

Frequency 2.7 Information Output

Nominal frequency fnom : 50 Hz / 60 Hz
Counters, measured data and signals:
Operating range: 0.95 to 1.05 fnom see address list (Appendix C)

Binary Inputs (Optical Couplers) Fault Logging

Number, function assignment and connections: Up to 5 faults are stored, then the oldest fault is erased.
see address list (Appendix C) and terminal connection
diagrams (Appendix E) Up to 64 signals per fault can be stored, subsequent
signals trigger the overflow indication.
Nominal input voltage VIn,nom: 24 to 250 V DC
Measured Fault Data
Operating range: 0.8 to 1.1 VIn,nom
with a residual ripple of up to 12 % of VIn,nom Operating time: 0.00 to 99.99 s, increments: 0.01
Fault current: 0.00 to 30.00 Inom, increments: 0.01
Power consumption per input:
VIn = 19 to 220 V DC: 1 W ± 30 % Self-Monitoring
VIn > 220 V DC: VIn×5 mA ±30 %
Up to 30 monitoring signals can be stored.
Binary Outputs (Output Relays)

Number, function assignment and connections:

see address list (Appendix C) and terminal connection
diagrams (Appendix E)

Fitted: 4 output relays, all freely configurable

Contact load rating:

- Rated voltage: 300 V DC, 250 V AC
- Continuous current: 5A
- Short-time current: 30 A for 0.5 s
- Making capacity: 1000 W (VA) at L/R = 40 ms
- Breaking capacity: 0.2 A at 220 V DC, L/R = 40 ms,
4 A at 220 V AC, cos ϕ ≥0.4

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2 Technical Data
(continued)

2.8 Settings 2.10 Power Supply

Settings, ranges and increments: Nominal auxiliary voltage VA,nom

see address list (Appendix C)
Typical Characteristics
Reset ratio for starting and measurement: approx. 0.95
Shortest tripping time: approx. 35 ms
Starting reset time: approx. 30 ms
Trip command reset time: approx. 100 ms
2.9 Deviations
Deviations relative to the set value for sinusoidal measured
variables, total harmonic distortion ≤ 2 %, ambient
temperature 20 °C and nominal auxiliary
voltage VA,nom.
24 to 60 V DC / 110 to 250 V DC, 100 to 230 V AC 1
(selectable using plug-in jumper)
Operating range for direct voltage:
0.8 to 1.1 VA,nom with a residual ripple of up to
12 % VA,nom
Operating range for alternating voltage:
0.8 to 1.1 VA,nom
2
fnom: 50 Hz / 60 Hz
Nominal consumption at VA,nom = 220 V DC:
approx. 5 W (VA)

Time-overcurrent protection
Currents > 0.2 Inom: deviation: ± 5%
Influence at 20°C ± 20 K: ± 2.5%
Influence at Unom ± 20%: ± 1%

Timer stages
Deviation: ± 1% or ± 30 ms
Influence at 20°C ± 20 K: ± 2.5%

Operating data measurement

Currents > 0.2 Inom: deviation: ± 5%
Influence at 20°C ± 20 K: ± 2.5%
Influence at Unom ± 20%: ± 1%

Measured fault data

Short-circuit current: deviation: ± 5%
Influence at 20°C ± 20 K: ± 2.5%
Influence at Unom ± 20%: ± 1%

1
Factory setting underlined

2
For AC voltage supply

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3 Operation
3.1 Modular Structure
The differential protection device PS 431 is part of the
series of numerical protection devices. The local control
panel is standardized for all device types of this series.
Figure 1 shows the basic hardware structure of the device
PS 431.
1 Basic hardware structure
The input transformers and optical couplers convert the
external analog and binary variables - electrically isolated -
to the internal processing levels. Commands and signals
generated within the device are accessible via floating
contacts. The external auxiliary voltage is applied to the
power supply module which provides the voltages required
internally.
3.2 Man-Machine Communication
The exchange of information between operator and device
is via the Integrated local control panel.
Each piece of information and each parameter is coded
with an ‘address’ consisting of two two-digit decimal
numbers x and y. Changing x or y allows selection of any
desired address for display or where necessary
modification of the information stored at that address.
(Please refer to Chapter 6.)
12
The addresses are standardized for all systems with the
advantage that the same information is coded with the
same address in each device type. The entire address
range is divided into the following three groups:
¨ Parameters:
This group contains all set values including the device
identification data, the configuration parameters for
adapting the device interfaces to the system and the
function parameters for adapting the protective function
to the process. All values of this group are stored in a
non-volatile memory, that is the values will be preserved
even if the power supply fails.
¨ Operation:
This group includes all information relevant for operation,
such as measured operating values and binary signal
states. This information is updated periodically and
consequently is not stored. In addition, various control
parameters are grouped here, for example those for
resetting counters, memories and displays.
¨ Events:
The third group is reserved for the recording of events.
Hence all information contained in this group is stored.
In particular the start/end signals during a fault, the
measured fault data as well as sampled fault records
are stored here and can be read out at a later time.
The appendix, section C, documents the addresses of the
numerical protection device PS 431. This address list is
complete and thus contains all addresses used with the
PS 431.
89431-302-401-602 / SLTS.12.04950 EN
3 Operation
(continued)

3.3 Operating Modes

The PS 431 is always a four-pole design. The current input After A / D conversion, the three phase currents IA, IB and
transformers are equipped with taps for 1 A and 5 A. The IC as well as the residual current IN are available for further
standard connections of the four measurement inputs to processing. Additionally, the maximum value IL,max is formed
the system current transformers are shown in Figure 2. from the three phase currents.

1
2 Connection to the system current transformers

1
IP,max in the figures corresponds to IL,max in the address list and text.

89431-302-401-602 / SLTS.12.04950 EN 13
3 Operation
(continued)

3 Switching between operation modes

The time-overcurrent protection device PS 431 can be

adjusted per software setting to execute one out of two
operation modes. The following operation modes are
possible:

¨ Operation mode DTOC:

Definite-time overcurrent protection

¨ Operation mode IDMT: 4 Enabling and disabling protection functions

Inverse-time overcurrent protection

The desired operation mode is selected via address 17 61

(see Figure 3). Functions of the set operation mode only are processed.

If the operation mode is switched, a cold restart is carried

out so that all settings are lost.

Figure 4 shows how all protection functions can be enabled

or disabled via address 03 30. The parameters marked ‘off’
in the address list can be changed only when the
protection is disabled (see Appendix C).

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3 Operation
(continued)
3.4 Definite-Time Overcurrent Protection (DTOC)
For the definite-time overcurrent protection mode, address
17 61 must be set to the value ‘1’. In this operation mode,
the following functions are available
(see Figure 5):
¨ Phase-selective phase current timer stage I> with time
lag tI>
¨ Time-lag high-set phase current timer stage I>> with
time lag tI>>
¨ Residual current timer stage IN> with time lag tIN>
¨ Time-lag high-set residual current timer stage IN>> with
time lag tIN>>
5 Definite-time overcurrent protection
89431-302-401-602 / SLTS.12.04950 EN
The output signals of the phase current timer stage I> and
of the residual current timer stage IN> represent the phase-
selective starting signals. From the output signals of all
overcurrent stages, the general starting signal is formed.
By means of a setting, the user selects whether the two
residual current stages IN> and IN>> participate in forming
the general starting signal. If the setting is such that one of
the two residual current stages does not lead to a general
starting, then the associated time lags tIN> and tIN>> are
automatically excluded from the formation of the trip
command (see ‘Tripping Logic’).
The elapsing of all timer stages can be blocked via a
selection matrix and a binary input (see ‘Blocking Logic’).
15
3 Operation
(continued)

3.5 Inverse -Time Overcurrent Protection (IDMT)
For the inverse-time overcurrent protection mode, address
17 61 must be set to the value ‘3’. In this operation mode,
the following functions are available
(see Figure 11):
¨ Phase-selective phase current timer stage I> (=1.1· IB)
with time lag tIB
¨ Time-lag high-set phase current timer stage I>> with
time lag tI>>
¨ Residual current timer stage IN> (= INB or 1.1· INB) with
time lag tIN>
¨ Time-lag high-set residual current timer stage IN>> with
time lag tIN>>
The residual current timer stage IN> may optionally be
operated in inverse (1.1· INB) or definite (INB) time-delay
mode. For the current-independent operation mode, the
reference current INB (which may be set) is the threshold
operate value. For the current-dependent mode, the
adjustable reference current INB is the reference quantity for
the threshold operate value and the operate delay. The
residual current timer stage operates when the current
exceeds a value of 1.1· IB . For the current-dependent time
delay, the tripping characteristics may be selected
according to IEC 255-4 or BS 142 as follows.
0.14
¨ Normally inverse: t = KG ⋅ s
(I INB )0.02 − 1
13 .5
¨ Very inverse: t = KG ⋅ s
( NB ) − 1
I I

The phase current timer stage I> (=1.1· IB) operates in 80

¨ Extremely inverse: t = KG ⋅ s
inverse time-delay mode. The reference current IB is the
reference quantity for the threshold operate value and the
(I INB )2 − 1
operate delay. The phase current timer stage operates
when the current exceeds a value of 1.1· IB. For the 120
¨ Long time inverse: t = KG ⋅ s
current-dependent time delay, the tripping characteristics (I INB ) − 1
can be selected according to IEC 255-4 or BS 142 as
follows. 1
¨ RI Inverse: t = KG ⋅ s
0.236
0.14 0.339 −
¨ Normally inverse: t = KL ⋅
0.02
s (I INB )
(I IB ) −1
Time-lag high-set phase current timer stage I>> and the
13 .5 time-lag high-set residual current timer stage IN>> are
¨ Very inverse: t = KL ⋅ s
(I IB ) − 1 always in definite time-delay mode.

The elapsing of all timer stages can be blocked via a

80
¨ Extremely inverse: t = KL ⋅ s selection matrix and a binary input (see ‘Blocking Logic’).
(I IB )2 − 1
The tripping characteristics are shown in Figures 6 to 10. In
120 these figures, K stands for KL and KG. For current levels in
¨ Long time inverse: t = KL ⋅ s excess of 20· I/IB· or I/INB the operate delays are limited
(I INB ) − 1 towards smaller values.

1
¨ RI Inverse: t = KL ⋅ s
0.236
0.339 −
(I IB )

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3 Operation
(continued)

1
6 Tripping characteristic ‘normally inverse’ 8 Tripping characteristic ‘extremely inverse’

7 Tripping characteristic ‘very inverse’ 9 Tripping characteristic ‘long time inverse’

1
Iref in the figures corresponds to IB (as reference current)
in the address list and text.

89431-302-401-602 / SLTS.12.04950 EN 17
3 Operation
(continued)

The output signals of the phase current timer stage I>

(=1.1· IB) and of the residual current timer stage IN> (= INB
or 1.1· INB) represent the phase-selective starting signals.
From the output signals of all overcurrent stages, the
general starting signal is formed. By means of a setting,
the user selects whether the two residual current stages
IN> and IN>> participate in forming the general starting
signal. If the setting is such that one of the two residual
current stages does not lead to a general starting, then the
associated time delays tIN> and tIN>> are automatically
excluded from the formation of the trip command (see
‘Tripping Logic’).

1
10 Tripping characteristic ‘RI inverse’

1
Iref in the figures corresponds to IB (as reference current)
in the address list and text.

18 89431-302-401-602 / SLTS.12.04950 EN
3 Operation
(continued)

11 Inverse-time overcurrent protection

Iref and IP,max in the figures correspond to IB (as reference current) and IL,max, respectively, in the address list and text.

89431-302-401-602 / SLTS.12.04950 EN 19
3 Operation
(continued)
3.6 Blocking Logic
The blocking logic allows the selection of the criteria for the
formation of a block (see Figure 12). The timer stages to be
blocked are selected via the blocking matrix.
The timer stages selected earlier are blocked when the
timer stages to be blocked are selected via address 17 90
‘MAIN: Block mode E1’and the binary input ‘MAIN: E1
block EXT’ is triggered.
Alternatively, differing previously selected timer stages can
be blocked via address 17 92 ‘MAIN: Block mode
E2’and triggering of the input ‘MAIN: E2 block EXT’.
One application is, for example, the formation of a reverse
interlocking mechanism for the purpose of busbar
protection.
12 Blocking logic
20
3.6.1 Application to Busbar Protection by
‘Reverse Interlocking’
In addition to the overcurrent protection functions described
above, special functions can be implemented by
connecting PS 431 protection devices with each other. In
radial networks with single-end infeed, grading times for
busbar faults can be reduced with the help of PS 431
protection devices by means of the ‘reverse interlocking’
principle. The principle of reverse interlocking is shown in
Figure 13.
The PS 431 ‘Infeed’ is the infeed protection device, the PS
431 devices ‘Feeder 1’ to ‘Feeder n’ represent the feeder
protection. The general startings GS of all feeder relays are
configured for an output relay and combined via an external
ring line. The tI>> blocking of the infeed protection is
configured for a binary input and connected to the ring line.
The following example for operation mode DTOC serves to
illustrate the ‘reverse interlocking’ action. On the basis of
the usual time grading, the PS 431 ‘Infeed’ has an operate
delay of 1.5 s, for example, the PS 431 devices ‘Feeder 1’
to ‘Feeder n’ have operate delays of, say, 1.0 s. The timer
stage tI>> of the infeed protection is set to 0.1 s (due to
the command and operating times, a minimum period of
0.1 s is required).
89431-302-401-602 / SLTS.12.04950 EN
3 Operation
(continued)
For the infeed protection, the following reactions are
observed:
¨ Feeder fault
The affected feeder protection starts and blocks timer
stage tI>> of the infeed protection device via the ring
line. The infeed protection is thereby rendered ineffective
until the fault is cleared by the feeder relay after the
preset time delay (1 s in the example). Should the
feeder protection fail to operate then a trip with the 1.5 s
operate time of the overcurrent timer stage tI> of the
infeed protection results.
13 The ‘reverse interlocking’ principle
89431-302-401-602 / SLTS.12.04950 EN
¨ Busbar fault
In the event of a busbar fault, none of the feeder
protection devices start. Consequently, timer stage tI>>
of the infeed protection is not blocked. The busbar fault
will be cleared with the short time lag (here 0.1 s) of the
infeed protection device.
The ‘reverse interlocking’ principle is applicable to both the
DTOC and the IDMT protection functions. It can also be
used in combination with other AEG protection devices.
21
3 Operation
(continued)
3.7 Circuit-Breaker Failure Protection
Once a trip command is issued, circuit breaker clearing is
monitored by the general starting. If the general starting
does not drop out during the set time lag after the trip
command has been issued, then the corresponding signal
is generated.
Caution! This output signal is not suited to tripping the
line-side circuit breaker(s) directly, as the
signal does not have a minimum output time
associated with it. In the event of premature
drop out, there is a risk of destruction of the
switching contact of the associated output
relay.
With a general starting scan, an external signal can be tied
into the trip command via the tripping logic.
14 Circuit-breaker failure protection
22
3.8 Measuring Circuit Monitoring
The integrated measuring circuit monitoring of the PS 431
is based on the phase current unbalance check (modulus
difference) according to the formula:
IL,max − IL,min
Imcm > = ⋅ Inom
IL,max
IL,max is the highest of the three phase currents, IL,min the
lowest. To suppress short-time transient effects, an
adjustable operate-delay timer stage tmcm> is connected in
series to the measuring stage Imcm>. Measuring circuit
monitoring is blocked during general starting.
For connection to two current transformers only (for
example in resonant-grounded networks), evaluation of the
current IB can be disabled (see Figure 15).
The following operation modes for measuring circuit
monitoring may be selected via address 17 28:
Operation Meaning
mode
000 Measuring circuit monitoring disabled.
101 Measuring circuit monitoring enabled.
Evaluation of IA and IC.
111 Measuring circuit monitoring enabled.
Evaluation of IA, IB and IC
(factory setting).
Enabling of measuring circuit monitoring does not produce
an entry in either the monitoring signal memory nor the
signal memory. The user may select the configuration of
the signal ‘tmcm>‘ for an LED indicator or for a binary
output. If configured for an LED indicator, the signal ‘tmcm>‘
latches. Reset is only possible by pressing the ‘R key’ (the
signal is retained in the event of general starting). If
configured for a binary output, the signal is updated, that is
when ‘tmcm>‘ drops out, the relevant output relay is reset.
89431-302-401-602 / SLTS.12.04950 EN
3 Operation
(continued)

1
15 Measuring circuit monitoring

3.9 Tripping Logic
Tripping logic allows the selection of the criteria for the
formation of a trip command. The differing phase current
timer stages or residual current timer stages can be used
in forming the trip command. Further tripping criteria can be
defined by means of the tripping matrix. The two residual
current timer stages tIN> und tIN>> automatically participate
in the formation of the trip command if they are set to lead
to a general starting signal when triggered.
A further matrix serves to determine which of the selection
criteria should cause trip command latching. Resetting is
via the local control panel or via an external signal.
As start signal for fault recording, the signal
ID M T / D T O C : T r i p c r i t e r i o n is generated. This signal
corresponds to the trip command but is non-latching.
For testing purposes, a manual trip command may be
issued via the local control panel.

1
IP,max and IP,min in the figures correspond to IL,max and IL,min, respectively, in the address list and text.

89431-302-401-602 / SLTS.12.04950 EN 23
3 Operation
(continued)

1
16 Tripping logic

1
Iref in the figures corresponds to IB (as reference current ) in the address list and text.

24 89431-302-401-602 / SLTS.12.04950 EN
3 Operation
(continued)

3.10 Output Relay Blocking

All output relays may be blocked via the local control panel
(address 21 14) or via a binary signal input (see Figure 17).
If, in setting the parameters, the function MON: W a r n i n g
has been assigned to the output relays then the
corresponding output relay cannot be blocked.

17 Output relay blocking

3.11 Operating Data Measurement Note: During a fault (see ‘Fault Recording’),
operating data measurement is not supported
The three phase currents, the maximum phase current and and the individual measured operation values
the residual current may be read out at the PS 431. All are displayed as ‘not measured’.
measured variables are referred to the nominal device .
current.

1
18 Operating data measurement

1
IP,max in the figures (as signal name) corresponds to IL,max in the address list and text.

89431-302-401-602 / SLTS.12.04950 EN 25
3 Operation
(continued)

3.12 Fault Recording
A fault, and hence the start of a fault recording, occurs if a
general starting or a trip criterion is present.
The faults are counted (address 04 20) and identified by
their serial number.
The fault records may be cleared in several ways. The
following mechanisms are provided:
¨ Automatic reset as a new fault occurs.
Fault signals configured for indication via LED indicators
and measured fault data displayed via the
corresponding addresses are erased.

¨ Manual reset by pressing reset key ‘R’ on the local

control panel or by means of an external reset signal.
Fault signals configured for indication via LED indicators
and measured fault data displayed via the
corresponding addresses are erased.

¨ Manual reset of the signal memory at the local control

panel via its reset address (address 03 06).
All fault recordings are erased and the fault counter
(address 04 20) changes to the value ‘0’. Fault signals
configured for indication via LED indicators and
measured fault data displayed via the corresponding
19 Fault counting addresses are erased as well.

In the event of any cold restart, for example when the

operation mode is changed at address 17 61, a general
Fault recordings are stored in volatile memory. However, reset is carried out automatically. All the other counters as
fault signals configured for indication via LED indicators are well as the fault counter are reset.
preserved even in the event of a power failure.

20 Resetting

26 89431-302-401-602 / SLTS.12.04950 EN
3 Operation
(continued)

3.12.1 Fault Logging 3.12.2 Measured Fault Data

A fault begins with the start of a general starting (GS) and After the end of a fault, the following fault data are
ends when the general starting drops out. displayed at the corresponding addresses:

Protection signals are stored fault-assigned in chronolo-
gical order. A total of five faults with a maximum of 64
start/end signals each can be held in a circular memory -
the signal memory. If more than five faults occur, and if the
memory has not been cleared in the meantime, the oldest
fault record will be overwritten. If more than 64 start/end
signals occur while a fault is running, the last signal
entered is F R E C : S i g n a l m e m . o v e r f l o w (address
35 01).
¨ Operating time: Time period from the start to the end of
the general starting.
¨ Short-circuit current: The maximum phase current
during the fault referred to the nominal device current.
Resetting will result in the relevant addresses showing the
symbol for "not measured" (....).

The fault records can be read at the local control panel.

21 Signal memory

22 Measured fault data

89431-302-401-602 / SLTS.12.04950 EN 27
3 Operation
(continued)
3.13 Self-Monitoring and Fault Diagnosis
Comprehensive monitoring routines in the differential
protection device PS 431 ensure that internal faults are
detected and do not lead to malfunctions of the protection
device.
After the supply voltage has been turned on, various tests
are carried out to verify full operability of the PS 431. The
display of the local control panel indicates which test is in
progress. If the PS 431 detects a fault during one of the
tests, startup is terminated and the display indicates which
test caused termination. Control actions are not possible.
A new startup of the PS 431 can be initiated only by
turning the supply voltage off and then on again.
After successful startup, cyclic self-monitoring tests are
run while the device is in operation. In the event of a
positive test result, a specified warning is output, which is
stored in a memory - the monitoring signal memory. A list
of all possible entries in the monitoring signal memory is
given in the address list (see Appendix Section C). The
memory area allows for a maximum of 30 entries.
If the monitoring signal memory contains one or more
entries, this fact is indicated by the red LED H1 of the local
control panel. Each new entry is indicated by a flashing
light. The composite indication for all monitoring signals
(address 36 70) can also be signaled via an output relay.
The output relay will operate as long as an internal fault is
detected.
The monitoring signal memory can only be cleared
manually at the local control panel (address 03 08). Entries
in the monitoring signal memory are not cleared
automatically even if the relevant test is negative during a
repetition of the test cycle. The content of the memory can
be read at the local control panel.
28
The response of the PS 431 to monitoring signals takes
one of the following forms depending on the signal:
¨ Signaling Only
If the signal is not caused by a malfunction, a monito-
ring signal only is given and there are no further
consequences. This situation occurs, for example,
when internal data acquisition memories overflow.
¨ Warm Restart
If the self-monitoring function detects a fault in the
hardware that might be eliminated by a restart of the
system, a so-called warm restart is carried out
automatically. The computer system is restored to a
defined state - as is the case with any startup. A warm
restart is characterized by the fact that all stored data,
and hence all setting parameters, are unaffected by the
procedure. A warm restart can also be triggered
manually by control action. While a warm restart is
running, the protective function will be blocked. If, after a
warm restart triggered by the self-monitoring function,
the same fault is detected again, the protective function
remains blocked.
¨ Cold Restart
If a serious fault not cleared by a renewed start-up is
diagnosed by the self-monitoring function, a cold restart
is carried out. This occurs, for example, if a corrupted
parameter set is diagnosed during the checksum
verification. A cold restart has the result that all internal
memories are brought to a defined state. After a cold
restart, this means that all settings of the protection
device have been discarded and the default settings as
found in the address list, column "Default" apply instead
(see Appendix Section C). With a view to a safe initial
state the default settings have been selected such that
the protective function is blocked. The monitoring signal
that triggered the cold restart and a notice on the loss
of parameters are entered in the monitoring signal
memory.
89431-302-401-602 / SLTS.12.04950 EN
3 Operation
(continued)

23 Monitoring signal memory

If the protective function is blocked, the condition is

signaled by continuous light of the yellow LED indicator H2
on the local control panel or, if desired, by signaling via a
configured output relay.

24 Signal ‘Blocked/faulty’

89431-302-401-602 / SLTS.12.04950 EN 29
4 Design

The PS 431 is mounted in an aluminium case. Connection Figures 25 and 26 show the case dimensions and fixture
is via threaded terminal ends. The case is suitable for positions.
either wall surface or flush panel mounting. The angle
brackets and connector blocks are adjustable for mounting
in the chosen configuration.

25 Dimensional drawing of the PS 431

30 89431-302-401-602 / SLTS.12.04950 EN
4 Design
(continued)

Regardless of the design version, the PS 431 – as the consisting of a total of 8 LED indicators is also
other device types of the ILS-P system – is equipped with incorporated into the local control panel. The meaning of
a standard local control panel. In order to protect the device the various displays is shown in plain text on a label strip.
according to the specified degree of protection, the local
control panel is covered with a tough film. In addition to the
essential control and indication elements, a parallel display

26 Side panel view of the PS 431 in the surface- and flush-mounting configurations

89431-302-401-602 / SLTS.12.04950 EN 31
4 Design
(continued)
The label strip is located in a pocket accessible from the
rear of the front panel. It can be replaced by user-specific
labels. A further label strip lists the addresses for
operation-related protection information and can also be
replaced by a strip with customized labeling. The
processor module with the local control module is attached
to the reverse side of the removable front plate and
connected to the I/O module via a ribbon cable.
32
The I/O module incorporates the power supply, the input
transformers and the power supply converters as well as
four output relays and two optical couplers for binary
signals.
The serial interface -X6 for parameter setting via a PC is set
into the front panel (Figure 25).
For wall surface mounting, the leads to the PS 431 are
normally run along the front side of the mounting level. If
the wiring is to be behind, an opening can be provided
below or above the terminal strip.
89431-302-401-602 / SLTS.12.04950 EN
5 Installation and Connection

5.1 Unpacking and Packing 5.3 Location Requirements

The PS 431 is packaged separately in its own carton and
shipped inside outer packaging. Use special care when
opening the cartons and unpacking the equipment, and do
not use force. In addition, make sure to remove from the
inside carton the Supporting Documents supplied with
each individual device.
The design revision level of each module included with the
device in its as-delivered condition can be determined from
the list of modules provided in the ‘Assembly List’ supplied
with the device (see ‘Components/Modules’). This list
should be carefully saved.
After unpacking the equipment, inspect it visually for sound
mechanical condition after transportation.
The PS 431 has been designed to conform to the standard
EN 60255-6. Therefore when choosing the installation
location it is important to make sure that it provides the
conditions specified in the Technical Data (see Chapter 2).
Several important conditions are listed below.
Climatic Conditions
¨ Ambient temperature: - 5 to + 55°C
¨ Air pressure: 800 to 1100 hPa
¨ Relative humidity:
The relative humidity must not result in the formation of
either condensed water or ice in the PS 431.

If the PS 431 is to be shipped, both inner and outer ¨ Ambient air:

packaging must be used. If the original packaging is no The ambient air must not be significantly polluted by
longer available, make sure that packaging conforms to dust, smoke, gases or vapors, or salt.
DIN ISO 2248 specifications for a drop height ≤ 0.8 m.
Mechanical Conditions
5.2 Checking the Nominal Data and the Design Type
¨ Vibration stress: 10 to 60 Hz, 0.035 mm
The PS 431 nominal data and design type can be and 60 to 150 Hz, 0.5 g
determined by consulting the type identification label (see
Figure 27). The type label is located on the underside of ¨ Earthquake resistance: 5 to 8 Hz, 3.5/1.5 mm and
the unit and on the lower side face in front of the terminal 8 to 35 Hz, 10/5 m/s2
strip. The type label is also affixed to the outside of the PS
431 packaging. Electrical Conditions for Auxiliary Voltage for the Power
Supply

¨ Operating range:
PS 431 Schaltbild/diagram 89431.401 CE 0.8 to 1.1 VA,nom
P 89431-0-XXXXXXX-302-401-602 XX.XX

I nom = 1/5 A f nom =50 / 60 Hz

Electromagnetic Conditions
UE,nom=24...250V DC U H,nom=24 ... 60 V DC/110 ... 250 V DC, 100 ... 230V AC
Appropriate measures taken in substations must
F 6.XXXXXX.X AEG-Nr. correspond to the state of the art (see, for example, the
Vorschrift / specification DIN EN 60255-6 2kV (III) Made in Germany VDEW ring binder entitled "Schutztechnik" [Protective
Systems], Section 8: "Recommendations for Measures to
27 PS 431 type identification label
Reduce Transient Overvoltage in Secondary Lines in High
Voltage Substations,” June 1992 edition).

The factory setting for the nominal auxiliary voltage VA,nom

(‘UH,nom ’) is underlined on the type identification label. The
nominal input voltage Vin,nom (‘UE,nom ’) is also shown on the
label.

With the auxiliary voltage on, identification via the built-in

display is also possible. After selecting the addresses
given in Section ‘Device Identification’ in the Appendix C to
this manual, the corresponding information is displayed.

89431-302-401-602 / SLTS.12.04950 EN 33
5 Installation and Connection
(continued)

5.4 Installation ¨ The two angle brackets D are now re-mounted using
bolts E with the longer leg of the angle bracket mounted
The case and mounting dimensions are given in Chapter 4. flat on the face surface.
The PS 431 is delivered in the wall surface mounting or the
flush panel mounting configuration depending on the order ¨ The upper sections of the two connector blocks B can
specifications. be pulled away after opening bolts A and remounted
after turning by 180 degrees (see Figure 28).
When the PS 431 is being installed in a cabinet door, for
example, special sealing steps must be followed in
accordance with the IP 51 protection required for the
* Please make sure
cabinet.
that all bolts A are loosened before attempting to pull off
Should the PS 431 mistakenly have been ordered for the upper sections of the connector blocks!
surface instead of flush mounting, the connector blocks
and angle brackets can be adjusted as shown in Figure 28. For flush panel mounting, a panel cutout as per Figure 29
is necessary.
¨ The two angle brackets D need to be removed after
undoing bolts C (three each on the upper and lower The panel thickness must not exceed 3 mm.
face). Subsequently, bolts C are repositioned and
tightened.

E A B C D

Front panel

Surface-mounting

Front panel

Flush-mounting

28 Reconfiguration for flush panel mounting

29 Panel cutout for the PS 431

34 89431-302-401-602 / SLTS.12.04950 EN
5 Installation and Connection
(continued)

For flush mounting, the PS 431 must be fastened using the The cutout edges and the bolt heads can be concealed
four bolts provided within the packing carton. using a cover frame with a snap-on fixture to the bolt heads
(see Figure 30).

30 Fixing the cover frame

89431-302-401-602 / SLTS.12.04950 EN 35
5 Installation and Connection
(continued)
5.5 Protective and System Grounding
The device case must be reliably grounded for reasons of
protective equipment grounding. This grounding step is also
absolutely essential for proper operation of the device and
is thus equivalent to system grounding. Potentials that
need to be grounded from an operational standpoint are
already properly connected to the equipment ground inside
the unit.
Holes for the grounding connection are located in the two
mounting brackets of the PS 431 and are labeled
accordingly.
A ground connection assembly kit is supplied with the unit.
The ground connection must be assembled as shown in
Figure 31.
Grounding must be low-inductance.
31 Ground connection assembly kit
36
5.6 Connections
5.6.1 Connecting the Measuring and Auxiliary
Voltage Circuits
Connect the PS 431 in accordance with the terminal
connection diagram specified on the type label. The
terminal connection diagram is included in the Supporting
Documents supplied with the unit and is also given in
Appendix E of this manual.
As a general principle, all connections run into the system
must have a defined potential. Pre-wired connections that
are not used must be grounded.
Connecting the Measuring Circuits
When connecting the system current transformers, the
user must first check to make sure the secondary nominal
currents of the system agree with those of the device. The
system current transformers must be connected in
accordance with the standard schematic diagram shown in
Figure 34. A connection in opposition (busbar-side
grounding of the system current transformers) does not
affect the protective functions. The PS 431 is always a four-
pole design. Three- or two-pole connection is possible,
however, where this is more appropriate to the relevant
system.
The PS 431 is suitable for nominal currents of 1 A or 5 A,
using different terminals for the connections.
Connecting the Auxiliary Circuits
Before connecting the auxiliary voltage VA for the
PS 431 power supply, make sure that the nominal value of
the auxiliary device voltage agrees with the nominal value of
the auxiliary system voltage.
Polarity reversal protection is provided in the form of a
rectifier bridge. To preserve uniformity with other protection
devices (L+ on terminal with smaller number), L+ should,
however, be connected to terminal 13. The PS 431 has an
auxiliary voltage supply that can be switched between
ranges and is factory-set for the voltage range of VA,nom =
110 to 250 V DC or 100 to 230 V AC.
89431-302-401-602 / SLTS.12.04950 EN
5 Installation and Connection
(continued)
The voltage range is switched by repositioning plug-in
jumpers on the I / O (input / output) module. After
loosening four bolts on the front side of the front panel and
two tab connectors (internal grounding) on the rear side,
the local control module (front panel and processor
module), which is connected to the I / O module by a plug-
in ribbon cable, can be removed. In the upper portion of the
I / O module, between output relay and current input
transformers, are plug-in jumpers, which are plugged in as
shown in Figures 32 and 33, depending on the desired
auxiliary voltage range.
32 Plug-in jumpers positioned for an auxiliary voltage of
110 to 250 V DC or 100 to 230 V AC (view from component side)
33 Plug-in jumpers positioned for an auxiliary voltage of 24 to 60 V
DC (view from component side)
89431-302-401-602 / SLTS.12.04950 EN
5.6.2 Connecting the Binary Control Inputs
When connecting the control voltage VIn for the binary
inputs of the PS 431, the user must first check to
determine whether the nominal value of the device control
voltage agrees with the nominal value of the system control
voltage. In addition, the user must check for matching
polarity (L+ on terminals 15 or 17). The device is protected
against damage from polarity reversal, but is not
operational if the polarity is incorrect. Voltages between 24
and 250 V DC are suitable for the control voltage VIn.
5.6.3 Connecting the PC Interface
The PC interface is provided so that the PS 431 can be
controlled from a personal computer (PC). Only the special
connection cable that is available as an accessory may be
used to connect the PS 431 to the PC.
The PC interface is not intended for
! permanent connection. Consequently the
socket does not have the extra insulation
from circuits connected to the system that is
required per VDE 0106 Part 101. Therefore
when plugging in the connection cable
make sure that you do not touch the socket
contacts.
After completing device control (parameter setting) via the
PC, disconnect the PC connection cable on the interface
socket to restore the specified degree of device protection.
37
5 Installation and Connection
(continued)

34 Standard connections for the PS 431

38 89431-302-401-602 / SLTS.12.04950 EN
6 Control
All data required for operation of the protection device are
entered from the local control panel, and the data important
for system management are read out there as well. The
local control panel permits the following specific functions:
¨ Readout and modification of settings
¨ Readout of current measured operating data and state
signals as well as stored monitoring signals
¨ Readout and resetting of counters and fault recordings
¨ Resetting of the parallel display (LEDs) and other
control functions for testing and startup
Control is also possible from the PC interface. In that case
the FPC operating program is required, along with a special
connection cable (see Chapter 13 “Accessories and Spare
Parts”) and a suitable PC.
6.1 Display and Keyboard
The local control panel consists of two 4-digit, 7-segment
displays, six function keys and 8 LED indicators.
F
Value
0 through a value range, which is defined separa- tely for
Address
03 10
x y
"Up" Key
"Down" Key
Enter Key
Reset Key
E R
35 View of the local control panel
The settings, signals and measured variables are
numerically coded. This code is called the address and is
displayed in the lower of the two 7-segment displays on the
local control panel. The value associated with the address
is displayed in the upper 7-segment display.
89431-302-401-602 / SLTS.12.04950 EN
¨ Value
The value of the information or parameter just selected
is displayed.
¨ Address
The address of the information or parameter just
selected is displayed.
¨ “Up” and “Down” Keys
Addresses can be selected, parameter values changed
and event records read out by pressing the “up” and
“down” keys.
Address Selection:
In the normal addressing mode, the two pairs of keys
are decoupled from one another and affect the address
display. The x coordinate of the address being
selected can be set using the left pair of keys, and the
y coordinate can be set using the right pair of keys.
The respective coordinate can be incremented by
pressing the “up” key and decremented by pressing
the “down” key.
Changing Parameter Values:
Parameter values can only be changed in the input
mode, which is signaled by the red LED indicator on
the enter key (E). In the input mode the two pairs of
“up” and “down” keys are generally coupled and have
the same effect on the value display. The system runs
each address together with the incrementation (see
“Address List” in the appendix). The next higher value
is obtained by pressing the “up” key, and the next
lower value by pressing the “down” key.
Event Record Readout:
Readout of event records is possible after the
appropriate memory has been accessed; this is
signaled by the red LED indicator on the enter key (E).
In this control mode the two pairs of “up” and “down”
keys are coupled and have the same effect on the
display.
¨ Enter
To enter the input mode, press enter key (E). Press a
second time to leave the input mode. Activation of the
input mode is signaled by the red LED indicator on the
enter key (E).
39
6 Control
(continued)

¨ Reset 6.3 Change-Enabling Function

The LED indicators can be reset by pressing the reset
key (R). The event records are not affected and remain
in the event memories. Other functions of the reset key
include deactivation of the input mode (with no further
consequences) and keyboard locking.
The following diagrams of the individual control steps
indicate which specific display can be changed by pressing
the “up” or “down” keys. A solid black dot in the upper left
corner of the enter key indicates that the red LED indicator
is lit up. The addresses used in the examples below are
not necessarily valid for the PS 431; they serve to illustrate
the principles of local control.
Although it is possible to select any address and read the
associated value by pressing the “up” and “down” keys, it
is not possible to switch directly to the input mode. This
safeguard prevents unwanted changes in the protection
setting. If the protection setting is to be changed, the
change-enabling function (address 03 10) must first be
activated. The change-enabling function is naturally the
only parameter that can be changed when the change-
enabling function itself is not activated.
Control Step or Action Display
Description

0 Select the address for the F

6.2 Address Selection change-enabling function by 0

pressing the “up” and “down” keys.
03 10
Addresses are selected by pressing the two pairs of “up”
x y
and “down” keys. As long as the keys are being pressed,
the value display remains dark. Approximately 1 second
after the keys are released the value associated with the
selected address will appear in the value display. In E R

principle, any address in the entire address range from

00 00 to 99 99 can be selected. If, however, an address is
selected that is not used in the PS 431, the value display 1 Press the enter key (E). The red E
F

0
will remain dark. The existence of entries in the signal or LED indicator on the enter key will
monitoring signal memories is indicated during operation. light up. The value can now be
03 10
changed by pressing the “up” or
This is indicated by the fact that while the “up” and “down” x y
“down” keys.
keys are being pressed the value display does not remain
dark; instead, the following messages are displayed:

¨ "L..." if there is information in the signal memory

E R

¨ "...E" if there is information in the monitoring signal

memory 2 Set the value to “1” by pressing F

one of the two “up” keys. 1

If “L” and/or “E” still remain in the value display 1 second 03 10

after the “up” and “down” keys have been released, then x y

there is no information stored for that particular address.

Example:
E R

Information in Information in Information in

Signal Memory Monitoring Signal Signal and
Memory Monitoring Signal
3 Press the enter key (E). The red E
F

LED indicator on the enter key will go 1

Memories
out. The change-enabling function is
03 10
F F F
active.
x y

L E L E

47 11 47 11 47 11
x y x y x y
E R

40 89431-302-401-602 / SLTS.12.04950 EN
6 Control
(continued)

To prevent the change-enabling function from accidentally Control Step or Action Display
remaining active after a protection setting has been Description
changed, the enabling function is automatically canceled 1 Select the desired address F

200 sec after the last key has been pressed. The address (address 03 13, for example) by 03 10
display immediately jumps to the settable return address pressing the “up” or “down” keys. 03 13
(address 03 13). The factory-set return address is the
x y
address for the change-enabling function. The return time is
restarted when any of the six control keys is pressed.

Even when the change-enabling function is activated, not E R

all parameters can be changed. For many settings it is

also necessary to deactivate the protection function
(address 03 30). Such settings include, for example, the 2 Press the enter key (E). The red E
F

configuration parameters by means of which the device LED indicator on the enter key will 03 10

interfaces can be adapted to the system. The following light up. The value can now be 03 13
changed by pressing the “up” or
entries in the “Change” column of the address list (see x y
“down” keys.
Appendix C) indicate whether values can be changed or
not:

¨ "on": The value can be changed even when the

E R

protective function is enabled.

¨ "off": The value can be changed provided that the

3 Set the new value (04 20, for F

example) by pressing an “up” or 04 20

protective function has been disabled. “down” key. During this process the
03 13
device continues to operate with the x y
¨ "-": The value cannot be modified by control old value.
action.

When the change-enabling function is activated, the E R

protective function can be deactivated from address 03 30

by setting the value to “0.” The protection device is factory-
set so that the protective function is deactivated. 4 Press the enter key (E). The red E
F

LED indicator on the enter key will go 04 20

6.4 Changing Settings out, and the device will now operate
03 13
with the new value. Another
x y
If all the conditions given above for a value change are address can be selected for value
satisfied, the desired setting can be entered. changing by pressing the “up” and
“down” keys.

E R
Control Step or Action Display
Description

0 Example of a display. The F 5 If the intended value change is

R
F

change-enabling function is activated 1 rejected during the setting process 03 10

and the protective function, if (red LED indicator on enter key is lit
03 10 03 13
applicable, is deactivated. up), then press the reset key (R).
x y x y
The red LED indicator on the enter
key will go out, and the device will
continue to operate unchanged with
the old value. Another address can
E R E R
be selected for value changing by
pressing the "up" or "down" keys.

89431-302-401-602 / SLTS.12.04950 EN 41
6 Control
(continued)

6.5 Memory Readout Control Step or Action Display

Description
Memories can be read out after they are accessed via the 3 When the “up” key is pressed F

appropriate entry address. For this purpose it is not there is no response. 2

necessary to activate the change-enabling function or even
0.4. 2.0.
to deactivate the protective function. Accidental clearance
x y
of a memory via its entry address is not possible.

6.5.1 Signal Memory Readout

E R

Control Step or Action Display

Description

0 Example of a display. F 4 When the “down” key is pressed,

F

1
0 the oldest signal of the most recent
fault is displayed (for example, 4.0. 0.0.
03 10
address 40 00 ‘General starting’). x y
x y
Here the value “1” in the value
display means that the signal has
started. The end of the signal is
indicated by the value “0” in the value E R
E R
display.

1 Select the address for entering F

5 If the “down” key continues to be F

pressed, the fault signal log is read in 1

the signal memory (03 00) by -- - L
chronological order, that is, in the
pressing the “up” or “down” keys. 4.0. 0.5.
03 00 direction of more recent signals.
x y
x y

E R
E R

2 Press the enter key (E). The ad- F

6 The next oldest signal is F

E
displayed by pressing the “up” key. 1
dress display changes from 03 00 to 2
04 20. A period is displayed after 4.0. 0.0.
0.4. 2.0.
each digit in the address. This x y
x y
indicates that a special memory mode
is now active. The fault number of
the most recent fault (for example,
number 2) appears in the value E R
E R
display for address 04 20. In every
fault record the fault number is
placed at the beginning of the related
fault log for identification purposes.
7 After the last entry in a fault log F

has been reached by repeatedly 1

Since for each new fault record the
pressing the “down” key, then the
actual value of address 04 20 is 0.4. 2.0.
next time the “down” key is pressed
increased by the value of "1" in order x y
the display sw itches to the beginning
to count faults, the fault number of
of the next oldest fault. The
the most recent fault also
beginning of this fault log is indicated
corresponds to the number of
again by the respective fault number,
recorded faults since the signal E R
which appears first in the top display
memory was last reset. If, after
(number 1 in this example).
entry into the signal memory, the
address 04 20 and the value "0" are
indicated, then no fault is stored in
the signal memory.

42 89431-302-401-602 / SLTS.12.04950 EN
6 Control
(continued)

Control Step or Action Display Control Step or Action Display

Description Description

8 When the “up” key is pressed the F 1 Select the address for entry into F

display does not jump again to the 2 the monitoring signal memory (03 01) E- --
last entry for the next most recent by pressing the “up” or “down” keys.
0.4. 2.0. 03 01
fault log but rather back to address
x y x y
04 20
(= fault number) and thus back to the
beginning of the record for the next
most recent fault.
E R E R

9 If the display does not change F 2 Press the enter key (E). The E
F

when the “down” key is pressed, 0 most recent monitoring signal 1

then the end of the record for the appears in the address and value
4.0. 0.0. 9.0. 2.8.
oldest stored fault has been displays (address 90 28 and the
x y x y
reached. value 1, for example). A period is
displayed after each digit in the
address. This indicates that a
special memory mode is now
E R E R
activated. If, after entry into the
monitoring signal memory, the
address 00 00 and the value "0" are
10 The signal memory is exited by
R
F
displayed, then no monitoring signals
pressing the reset key at any - - - L are stored in the monitoring signal
location in the signal memory. The memory.
03 00
periods displayed after each digit
x y
disappear, and the address for entry
into the signal memory is displayed
3 When the two “down” keys are F

pressed there is no response. 1

(03 00). Any address can then be
selected by pressing the “up” or 9.0. 2.8.
E R
“down” keys. x y

6.5.2 Monitoring Signal Memory Readout

E R

Control Step or Action Display

Description
4 The next oldest monitoring signal
0 Example of a display. F is displayed by pressing one of the
0 two “up” keys. All monitoring signals
can be read in reverse chronological
03 10
order, that is, in the direction of older
x y
signals, by repeatedly pressing one
of the two “up” keys.

E R
5 The next most recent signal is
displayed by pressing the “down”
keys.

6 If the display no longer changes F

when the “up” keys are pressed, 1

then the oldest stored monitoring
9.0. 2.8.
signal has been reached.
x y

E R

89431-302-401-602 / SLTS.12.04950 EN 43
6 Control
(continued)

Control Step or Action Display Control Step or Action Display

Description Description

7 The monitoring signal memory is

R
F 1 Press the “up” or “down” keys to F

exited by pressing the reset key (R) E- -- select the address for resetting the 2
at any location in the monitoring signal memory (03 06). The number
03 01 03 06
signal memory. The periods of faults recorded since the signal
x y x y
displayed after each digit in the memory was last reset will appear in
address display disappear, and the the value display (the number 2, for
address for entry into the monitoring example).
signal memory (03 01) is displayed.
E R E R
Any address can then be selected
by pressing the “up” or “down” keys.

6.6 Resetting
2 Press the enter key (E). The red E
F

LED indicator on the enter key will 2

light up. When the “up” and “down”
All information memories – particularly the signal and keys are pressed there is no
03 06
x y
monitoring signal memories – and LED indicators can be response.
reset manually. In addition, the LED indicators are
automatically cleared and reset at the start of a new fault
so that they always display the last fault. E R

The user can also reset the LED indicators manually by

pressing the reset key; this is always possible when the 3 Press the enter key (E). This E F

device is in the normal control mode. It always triggers an triggers an LED indicator test. After 0
LED indicator test. The signal memory is not affected by it is completed the red LED indicator
03 06
this process so that accidental erasing of the fault record on the entry key will go out, and all
x y
associated with the acknowledged signal is reliably fault records will be erased. Any
prevented. address can then be selected by
pressing the “up” and “down” keys.
Because of the signal memory’s ring structure the E R

information in this memory is automatically updated for five

consecutive events, so that in principle a manual reset
would not be necessary. However, if the signal memory 4 If, after exiting the normal control
R
F

should need to be cleared completely – after function tests, mode (red LED indicator is lit up), the 2

for example – this can be done via the corresponding reset request to erase fault records is 03 06
rejected, press the reset key (R).
address. x y
The red LED indicator on the enter
key will go out, and the fault records
Control Step or Action Display continue to be stored in the device
Description unchanged. Then any address can
0
E R
Example of a display. F
be selected by pressing the “up” and
0 “down” keys.

03 10
x y

E R

44 89431-302-401-602 / SLTS.12.04950 EN
6 Control
(continued)

6.7 Password-Protected Control Operations Control Step or Action Display

Description
Certain actions from the local control panel, such as a 4 Press the “down” key for y. F

manual trip command for testing purposes, have a special 0

access lock to prevent accidental output. This special lock,
03 40
called a password, consists of a specifically defined
x y
sequential combination of keys pressed within a certain
time period. The following example shows the password-
protected output of a manual trip command:
E R

Control Step or Action Display

Description

0 Example of a display. The F

5 Press the “up” key for y. F

0
change enabling command has been 1
issued (03 10=1). 03 40
03 10
x y
x y

E R
E R

1 Select the address for the F

6 Press the “down” key for x. The F

value display will change from 0 to 1. 1

manual trip command (03 40) by 0
pressing the “up” and “down” keys. 03 40
03 40
A zero will appear in the value x y
x y
display.

E R
E R

2 After the enter key (E) is pressed E

F
7 Press the enter key (E) to issue E
F

the trip command. The value display 0

the red LED on the enter key will light 0
will drop back to zero. If the reset
up. Although the change mode is 03 40
03 40 key (R) is pressed instead of the
active, the value cannot be changed x y
x y enter key, no trip command will be
by pressing the “up” and “down”
issued (value display returns to 0).
keys. A “change of value” is only
possible in this case by means of a
specified sequential key combination E R
E R
(control steps 3 to 6) within a
specific time period. The following
control steps, steps 3 to 6, must
therefore be carried out within 4
seconds.

3 Press the “up” key for x. F

03 40
x y

E R

89431-302-401-602 / SLTS.12.04950 EN 45
6 Control
(continued)

6.8 Keyboard Lock Control Step or Action Display

Description
After all settings have been made, the keyboard can be 0 Example of the display when the F

locked. This means that unauthorized or unintentional keyboard is locked. The reset key 0
changes are no longer possible. To lock the keyboard the (R) is enabled for resetting the LED
03 10
value “1” must be set at address 03 11 (password). When indicators.
x y
the keyboard is locked the only key still functionally active
is the reset key. When the “up” or “down” keys are pressed
there is no response from the device.
E R

Control Step or Action Display

Description 1 Press the “up” key for x. F

0
0
Example of a display. The F

keyboard is unlocked. Note: for this 0 03 10

procedure the value “1” must be set x y
03 10
at address 03 11 (password).
x y

E R

E R

2 Press the “down” key for y. F

1 Press the reset key (R) at any

R
0

address. All LEDs will light up. 03 10

x y

2 Wait until the LEDs go out. Press

R
F

the reset key (R) again. After this 0

nothing will happen when the x or y E R
03 10
“up” and “down” keys are pressed.
x y
After the automatic return time has
elapsed the address display will 3 Press the “up” key for y. F

show the return address, and the 0

associated value will appear in the
value display. The return address in E R 03 10
this example is 03 10. x y

If there is no response when the “up” and “down” keys or E R

the enter key are pressed (but the R key is active and
causes the LED indicators to be reset), then the keyboard
is locked. The lock can be released by carrying out the 4 Press the “down” key for x. F

following operations. However, the four keys must be Now the “up” and “down” keys for x 0
pressed within 4 seconds. and y are enabled for selection of a
03 10
new address.
x y

E R

46 89431-302-401-602 / SLTS.12.04950 EN
7 Settings

The PS 431 time-overcurrent protection device must be 7.1 Device Identification

adjusted to the system and to the protected equipment by
means of appropriate settings. This chapter gives The device identification values record the ordering
information for determining the appropriate settings. information and the design version of the protection device.
They have no effect on the various functions of the
The address list in the appendix (Section C) lists all protection device. The device identification settings should
parameters along with their setting ranges and not be changed unless the design version of the protection
incrementation or selection tables. The set value record device is modified.
sheets in the appendix (Section D) make it possible for the
user to keep a complete and well-organized record of all 7.1.1 Ordering Information
settings.
00 00 IDENT: Device type
The units are supplied with a factory-set configuration of The type designation number is displayed. The
settings that in most cases correspond to the “default display cannot be altered.
settings” given in the address list. If the factory settings
differ from the default settings, then this is indicated below 00 50 IDENT: Auxiliary voltage
at the appropriate points. The setting for the auxiliary voltage used, for
example, 220 for 220 V DC.
The default settings given in the address list are activated 00 55 IDENT: Control voltage
after a cold restart. The protection device is then blocked. The setting for the control voltage used, for
All settings must be re-entered after a cold restart. example, 60 for 60 V DC.

Note: The first setting to be made should be the

selection of the operation mode of protection via
address 17 61 (see ‘Global’). Changing this set
value automatically triggers a cold restart so that
all settings will be replaced with those given in
the“Default” column of the address list (see
Appendix C).

Note: Whenever the measurement range for INB (address

17 64) is changed, an offset adjustment of the A /
D converter needs to be carried out. First check to
make sure that no current is present in the
measurement inputs of the protection device. The
offset adjustment is performed by changing
address 17 63 to carry the value “1“. After
completing the offset adjustment, the value returns
to “0“.

89431-302-401-602 / SLTS.12.04950 EN 47
7 Settings
(continued)

7.1.2 Design Version 7.2.2 Binary Inputs

The software version (SW version) in the PS 431 can be The PS 431 has two optical coupler inputs for processing
read out at the addresses in this group. binary signals from the system. The connection scheme for
the binary inputs is shown in the terminal connection
02 00 IDENT: Data model diagram. The address list gives information on the
The version of the data model which needs to be configuration options for the binary inputs (see Appendix
installed in the PC for operation of the PS 431 Section C).
by the FPC operating program. This display
cannot be altered. When configuring binary inputs the user should take into
account that the same information cannot be processed by
02 18 IDENT: SW version L several binary signal inputs. This means that a given
The software version installed in the hardware is function can only be assigned to one binary signal input.
displayed. This display cannot be altered.
A standard setting that differs from the “default setting”
7.2 Configuration Parameters given in the address list has been factory-set for the two
inputs. The factory setting is given in the terminal
The device interfaces are adapted to the system conditions connection diagrams included in the documentation
by setting the configuration parameters. supplied with the device and also in Appendix E of this
manual. Depending on the assigned function, the PS 431
7.2.1 Control Interfaces will expect a triggering signal persisting for a minimum
period of time as given in the following table.
03 11 LOC: Access lock active
Since the local control panel is always Configurable Functions
accessible, measures have been taken to Value Description Min. trigger- Fig.
allow the local control panel to be locked. A ing time
"0" setting means “Locking not possible,” and - Without function
a setting of "1" means “Locking possible”. The
40 03 CBF: Input EXT < 10 ms 14
keyboard is then locked by pressing the “R“
key twice at any address. 40 14 MAIN: Block outp.rel. EXT < 10 ms 17
40 15 MAIN: Reset latch. EXT < 10 ms 16
03 13 LOC: Autom. return addr.
The address to which the display will return 40 23 MAIN: Reset indicat. EXT < 10 ms 20
after the automatic return time has elapsed is 40 35 MAIN: Reset latch.+indic. < 10 ms 22
set here. Thus the units will display specified 40 60 MAIN: E1 block EXT < 10 ms 12
information during operation.
40 61 MAIN: E2 block EXT < 10 ms 12

The operating mode of every binary signal input can be

specified. The user can choose whether the presence or
absence of a voltage (mode “active high" or mode “active
low", respectively) shall be interpreted as the logic "1"
signal.

54 01 INP: Fct. assignm. U 1

54 04 INP: Fct. assignm. U 2
Assign functions to binary signal inputs.
54 02 INP: Operating mode U 1
54 05 INP: Operating mode U 2
Specify the operating mode of the binary
signal inputs.

48 89431-302-401-602 / SLTS.12.04950 EN
7 Settings
(continued)

7.2.3 Binary Outputs 7.3 Function Parameters

The PS 431 has four output relays for the output of binary 7.3.1 Global
signals. The connection scheme for the output relays is
shown in the terminal connection diagram. The address list 03 30 MAIN: Protection active Fig. 4
gives information on the configuration options for the binary Enabling or disabling of all protection
outputs (see Appendix C). functions. The parameters marked in the
address list by the word “off” can only be
The contact data for the all-or-nothing relays permit them to changed when protection is disabled. The
be used either as command relays or as signal relays. devices are shipped with the protection
functions disabled.
51 01 OUTP: Fct. assignm. K 1
51 03 OUTP: Fct. assignm. K 2 17 27 MAIN: Gen. start mode Fig. 16
51 05 OUTP: Fct. assignm. K 3 This setting controls whether triggering of the
51 07 OUTP: Fct. assignm. K 4 residual current timer stage IN> or of the high-
Assign functions to output relays. set residual current timer stage IN>> triggers
the general starting signal. For the setting
Without IN> v IN>> the associated time lags
7.2.4 LED Indicators tIN> and tIN>> are automatically excluded from
the formation of the trip command.
The PS 431 has a total of 8 LED indicators for parallel
display of binary signals. The address list gives information 17 28 MAIN: Meas. circ. monitor Fig. 15
on the configuration options for all LED indicators (see Adaptation of measuring circuit monitoring to
Appendix C). the system current transformers.
17 31 MAIN: Fct.assignment Trip1/2 Fig. 16
A standard setting that differs from the “default setting” 17 33 MAIN: Fct.assignment Trip2/2 Fig. 16
given in the address list has been factory-set for some of
Controls which signals trigger the trip
the freely configurable LED indicators. The factory setting
command.
is given in the terminal connection diagram included in the
Supporting Documents supplied with the device and also in 17 32 MAIN: Latching mode 1/2 Fig. 16
Appendix E of this manual. 17 34 MAIN: Latching mode 2/2 Fig. 16
Controls which signals trigger latching of the
In general, the display is latching, that is, each signal trip command.
assigned to an LED indicator is stored as it starts (flip-flop
function). The stored LED indications can be reset 17 61 MAIN: Protection mode Fig. 3
manually. Also, a dynamic reset accompanies each new Setting the operation mode of protection.
general starting. At the onset of a general starting, the Note: Changing this set value automatically
existing LED indications are erased (with the exception of triggers a cold restart so that all
MON: t m c m) and overwritten during the fault so that the settings will be replaced with those
signals of the most recent fault are displayed. given in the“Default” column of the
address list (see Appendix C). The
57 05 LED: Fct. assignm. H 3 selection of the operation mode of
57 07 LED: Fct. assignm. H 4 protection should therefore be the first
57 09 LED: Fct. assignm. H 5 setting to be made.
57 11 LED: Fct. assignm. H 6
57 13 LED: Fct. assignm. H 7 17 90 MAIN: Block mode 1 Fig. 12
57 15 LED: Fct. assignm. H 8 17 92 MAIN: Block mode 2 Fig. 12
Assign functions to LED indicators. Controls which measuring stages are to be
blocked by the input signal.
21 14 MAIN: Outp.rel. block USR Fig. 17
Blocking all output relays. On delivery, the
output relays are not blocked.

89431-302-401-602 / SLTS.12.04950 EN 49
7 Settings
(continued)

7.3.2 Definite-Time Overcurrent Protection (DTOC) 7.3.3 Inverse -Time Overcurrent Protection (IDMT)

This function is available only if the DTOC operating mode This function is available only if the IDMT operating mode
has been set at address 17 61 (value “1“). has been set at address 17 61 (value “3“).

In preference, the addresses for the current threshold The device is shipped with the operate mode set to IDMT.
operate values of the individual measuring stages should
then be set sequentially and, in parallel, the addresses for The following functions should then be set, preferably in the
the associated time lags should be selected and set sequence listed below:
(according to the time grading schedule). The following
addresses are involved: 17 13 IDMT: IB Fig. 11
Setting the refererence current for the phase
17 00 DTOC: I> Fig. 5 current timer stage
Setting the threshold operate value of the
overcurrent timer stage 17 35 IDMT: Character. type L Fig. 11
Setting the tripping characteristic for the phase
17 01 IDMT/DTOC: I>> Fig. 5 current timer stage
Setting the threshold operate value of the high-
set current timer stage 17 36 IDMT: Character.factor kL Fig. 11
Setting the characteristic factor for the phase
Caution! The setting allows threshold current timer stage
operate values that are not
permitted as continuous 17 37 IDMT: Charact. category N Fig. 11
current (see Section 2.5). Controls whether the residual current timer
stage is to be operated in inverse or in definite
17 03 DTOC: IN> Fig. 5 time-delay mode
Setting the threshold operate value of the
residual current timer stage 17 14 IDMT: INB Fig. 11
Setting the reference current for the
17 04 DTOC: tI> Fig. 5 residual current timer stage as inverse
Setting the operate delay of the overcurrent time-delay stage, or
timer stage setting the threshold operate value of the
17 06 IDMT/DTOC: tI>> Fig. 5 residual current timer stage as definite
Setting the operate delay of the high-set time-delay stage
current timer stage (see address 17 37)

17 08 IDMT/DTOC: tIN> Fig. 5 17 08 IDMT/DTOC: tIN> Fig. 11

Setting the operate delay of the residual Setting the time lag of the residual current
current timer stage timer stage in definite time-delay mode
(see address 17 37)
17 09 IDMT/DTOC: IN>> Fig. 5
Setting the threshold operate value of the high- 17 38 IDMT: Character. type N Fig. 11
set residual current timer stage Setting the tripping characteristic for the
residual current timer stage as inverse
Caution! The setting allows threshold time-delay stage
operate values that are not (see address 17 37)
permitted as continuous
current (see Section 2.5). 17 39 IDMT: Character.factor kG Fig. 11
Setting the characteristic factor for the inverse
17 10 IDMT/DTOC: tIN>> Fig. 5 time-delay residual current timer stage
Setting the operate delay of the high-set (see address 17 37)
residual current timer stage

The threshold operate value or the operate delay of

functions that are not required are set to ∞ where this is
provided for (see ‘Range of Values’ in the address list in the
Appendix). This disables the relevant function.

50 89431-302-401-602 / SLTS.12.04950 EN
7 Settings
(continued)

17 01 IDMT/DTOC: I>> Fig. 11 7.3.4 Supplementary Functions

Setting the threshold operate value of the high-
set phase current timer stage 17 20 CBF: tCBF Fig. 14
Setting the time lag for the circuit breaker
Caution! The setting allows threshold
failure protection.
operate values that are not
permitted as continuous Example for this setting:
current (see Section 2.5). tCBF = breaker operate time + reset time of
the starting (approx. 25 ms) + safety margin
17 06 IDMT/DTOC: tI>> Fig. 11
For example: 75+25+150 = 250 ms
Setting of the time lag of the high-set phase
current timer stage 17 24 MON: tmcm> Fig. 15
Setting the threshold operate value of
17 09 IDMT/DTOC: IN>> Fig. 11
measuring circuit monitoring
Setting the threshold operate value of the high-
set residual current timer stage 17 23 MON: Imcm> Fig. 15
Setting the time lag for measuring circuit
Caution! The setting allows threshold
monitoring
operate values that are not
permitted as continuous
current (see Section 2.5).
17 10 IDMT/DTOC: tIN>> Fig. 11
Setting of the time lag of the high-set residual
current timer stage
17 64 MAIN: INB range Fig. 11
Setting the INB> measuring range. After
changing the measuring range, an offset
adjustment needs to be carried out (see
Section 7.3.1).

The threshold operate value of functions that are not

required is set to ∞ where this is provided for. This disables
the relevant function.

89431-302-401-602 / SLTS.12.04950 EN 51
8 Information and Control Functions

The PS 431 generates a large number of signals, 40 08 IDMT/DTOC: Starting GF Fig. 5

processes binary input signals, and acquires cyclically 40 10 DTOC: tI> elapsed def. Fig. 5
updated measured data during fault-free operation of the 40 11 IDMT/DTOC: tI>> elapsed Fig. 5
protected object. It also acquires measured fault-related 40 13 IDMT/DTOC: tIN> elapsed Fig. 5
data. A number of counters is maintained for statistical 40 14 MAIN: Block outp.rel. EXT Fig. 17
purposes. This information can be read out from the 40 15 MAIN: Reset latch. EXT Fig. 16
integrated control panel. Also, various control functions for 40 22 CBF: tCBF elapsed Fig. 14
setting, testing and resetting can be implemented via this
40 28 IDMT/DTOC: tIN>> elapsed Fig. 5
panel.
40 29 IDMT/DTOC: Starting I>> Fig. 5
40 35 MAIN: Reset latch.+indic. Fig. 20
8.1 Measured Values
40 60 MAIN: E1 block EXT Fig. 12

04 44 OMEAS: Current IN p.u. 40 61 MAIN: E2 block EXT Fig. 12

Fig. 18
Display of the updated value for the residual 04 65 MAIN: Blocked/faulty Fig. 24
current referred to the relay nominal current IDMT Operating Mode
Inom. 03 30 MAIN: Protection active Fig. 4
21 09 MAIN: Reset latch. USR Fig. 16
05 51 OMEAS: Curr. IL,max p.u. Fig. 18 21 14 MAIN:Outp.rel. block USR Fig. 17
Display of the updated value for the maximum 21 15 MAIN: Outp.relays blocked *) Fig. 17
phase current referred to the relay nominal 35 01 FREC: Signal mem.overflow Fig. 21
current Inom.
36 70 MON: Warning Fig. 23
05 52 OMEAS: Current A p.u. Fig. 18 40 00 IDMT/DTOC: Gen. starting Fig. 11
05 53 OMEAS: Current B p.u. Fig. 18 40 03 CBF: Input EXT Fig. 14
05 54 OMEAS: Current C p.u. Fig. 18 40 04 MAIN: Trip command Fig. 16
Display of the updated value for the respective 40 05 IDMT/DTOC: Starting A Fig. 11
phase current referred to the relay nominal 40 06 IDMT/DTOC: Starting B Fig. 11
current Inom. 40 07 IDMT/DTOC: Starting C Fig. 11
40 08 IDMT/DTOC: Starting GF Fig. 11
04 21 FMEAS: Operating time Fig. 22
40 11 IDMT/DTOC: tI>> elapsed Fig. 11
Display of the updated value for the operating
time of the most recent fault. 40 13 IDMT/DTOC: tIN> elapsed Fig. 11
The operating time is the period from the start 40 14 MAIN: Block outp.rel. EXT Fig. 17
to the end of a general starting. 40 15 MAIN: Reset latch. EXT Fig. 16
40 22 CBF: tCBF elapsed Fig. 14
04 25 FMEAS: Fault current p.u. Fig. 22 40 28 IDMT/DTOC: tIN>> elapsed Fig. 11
Display of the updated value for the short- 40 29 IDMT/DTOC: Starting I>> Fig. 11
circuit current of the most recent fault as 40 35 MAIN: Reset latch.+indic. Fig. 20
maximum phase current referred to the relay
40 50 IDMT: tI> elapsed inv. Fig. 11
nominal current Inom.
40 51 IDMT: tINB elapsed inv. Fig. 11
40 60 MAIN: E1 block EXT Fig. 12
8.2 Signals 40 61 MAIN: E2 block EXT Fig. 12
04 65 MAIN: Blocked/faulty Fig. 24
DTOC Operating Mode The logic conditions for the formation of the
03 30 MAIN: Protection active Fig. 4 individual signals are shown in the relevant
21 09 MAIN: Reset latch. USR Fig. 16 figures (as indicated in the table above) in
21 14 MAIN:Outp.rel. block USR Fig. 17 Chapter 3.
21 15 MAIN: Outp.relays blocked *) Fig. 17 The signal marked *) can be selected directly
35 01 FREC: Signal mem.overflow Fig. 21 via its address.
36 70 MON: Warning Fig. 23
40 00 IDMT/DTOC: Gen. starting Fig. 5
The updated value for the signal state is
40 03 CBF: Input EXT indicated as follows:
Fig. 14
40 04 MAIN: Trip command Fig. 16 o Value “0“ : Signal not transmitted
40 05 IDMT/DTOC: Starting A Fig. 5
o Value “1“ : Signal transmitted
40 06 IDMT/DTOC: Starting B Fig. 5
40 07 IDMT/DTOC: Starting C Fig. 5
52 89431-302-401-602 / SLTS.12.04950 EN
8 Information and Control Functions
(continued)

54 00 INP: State U 1 8.4 Control and Testing

54 03 INP: State U 2
The current state of the binary signal inputs is 03 06 FREC: Reset sig. memory Fig. 20
indicated as follows: The following memories are reset:
o LED indicators (latched)
¨ Value of "0": not energized
o Signal memory
¨ Value of "1": energized
o Fault counter
This display appears regardless of the mode
setting for the binary signal inputs. o Measured fault data

03 08 MON: Reset mon. sig. mem. Fig. 23

51 00 OUTP: State K 1 The following memories are reset:
51 02 OUTP: State K 2
o Monitoring signal memory
51 04 OUTP: State K 3
51 06 OUTP: State K 4 o Monitoring signal counter
The current state of the output relays is
03 10 LOC: Value change enable
indicated as follows:
The setting of the change-enabling function
allows or prevents the modification of values
¨ Value of "0": output relay inactive
from the local control panel.
¨ Value of "1": output relay active
03 39 MAIN: Warm restart
In a warm restart the protection device
8.3 Counters responds as it does when the auxiliary voltage
supply is turned on.
04 05 MAIN: No. of trip cmds Fig. 16
03 40 MAIN: Man. trip cmd. USR Fig. 16
Number of trip commands since the last reset.
Output of a trip command for 100 ms from the
04 20 FREC: No. of fault Fig. 19 local control panel. This control operation is
Number of faults since the last reset. password-protected (see Section 6.7).
17 63 MAIN: A/D offset adj.
Offset adjustment for the A / D converter.
Required after changing address 17 64. During
this procedure, the measuring inputs must be
current-free.
21 09 MAIN: Reset latch. USR Fig. 16
Resetting the trip command latching.

89431-302-401-602 / SLTS.12.04950 EN 53
9 Commissioning

Preparation In as-delivered condition the keyboard is not locked.

Therefore all settings can be made after the change-
After the PS 431 has been installed and connected as
enabling command (address 03 10) has been issued. The
described in Chapter 5 (Installation and Connection), the
procedure for entering settings from the integrated local
commissioning procedure can begin.
control panel is described in Chapter 6.
Before turning on the power supply voltage, the following
After the settings have been made, the following checks
items must be checked again:
should be carried out again before any blocks are cleared:
¨ Is the protection device correctly connected to
¨ Does the function assignment of the binary signal
protective grounding?
inputs agree with the terminal connection diagram?
¨ Does the nominal value of the auxiliary device voltage
¨ Has the correct operating mode been selected for the
VA,nom agree with the nominal value of the auxiliary
binary signal inputs?
system voltage?
¨ Does the function assignment of the output relays agree
¨ Is the polarity of the device control voltage VIn,nom for the
with the terminal connection diagram?
binary signal inputs correct?
¨ Have all settings been made correctly?
¨ Are the current transformer connections and phase
sequence correct?
Now the blocks at the following addresses can be cleared:
After all wiring has been completed, check the system to
¨ Set address 03 30 (" M A I N : P r o t e c t i o n a c t i v e " )
make sure it is properly isolated. The conditions given in
to the value "1" (" o n " ).
VDE 0100 must be satisfied.
¨ Set address 21 14 (" M A I N : O u t p . r e l . b l o c k
Once all checks have been made, the power supply voltage
U S R " ) to the value " 0 " (" n o " ).
may be turned on. After voltage has been applied, the
protection device will start up. During startup various
startup tests are carried out (see Section 3.11). After
approximately 10 s the PS 431 is ready for operation. This
is indicated by a change in the display from address 99 00
to the preset address (factory-setting: 03 10).

54 89431-302-401-602 / SLTS.12.04950 EN
9 Commissioning
(continued)

Testing Checking the Binary Signal Inputs

By using the signals and displays generated by the
PS 431 it is possible to determine whether the PS 431 is
properly set and integrated with the station. Signals are
signaled by output relays and LED indicators and entered
into the signal memory.
If the circuit breaker is not to be operated during testing,
then all output relays may be blocked via address 21 14 or
a binary signal input configured accordingly. However, the
signals transmitted via output relays are likewise blocked
in this case and cannot be tested under these conditions.
Testing the Measurement Inputs
By way of applying appropriate quantities to be measured
to the measurement inputs, the display of measured
operating values (see Section 8.1) may be used to test
whether the protection device recognizes the analog
signals with the specified accuracy.
By way of applying appropriate signals to the binary signal
inputs, the display of state signals (see Section 8.2) may
be used to test whether the protection device recognizes
the binary signals correctly.
o Address 54 00: Display of the updated value for the
state of the binary signal input U1.
o Address 54 03: Display of the updated value for the
state of the binary signal input U2.
The displayed values have the following meanings:
¨ Value of "0": Not energized.
¨ Value of "1": Energized.
This display appears regardless of the binary signal input
mode selected.

o Address 05 52: Display of the updated value for the
phase current IA referred to the nominal relay current
Inom.
o Address 05 53: Display of the updated value for the
phase current IB referred to the nominal relay current
Inom.
o Address 05 54: Display of the updated value for the
phase current IC referred to the nominal relay current
Inom.
o Address 04 44: Display of the updated value for the
residual current IN referred to the nominal relay current
Inom.
Checking the Output Relays
The trip command (address 40 04) may be tested directly
via the local control panel. Via address 03 40, a manual trip
command may be transmitted manually for a duration of
100 ms (see Section 6.7). All output relays configured to
the trip command are triggered in this case. This control
action is password-protected (see Section 6.7).
All other signals configured to the output relays can only
be formed - and thereby tested - via the relevant assigned
function.

Caution: In applying quantities to be measured to the

measurement inputs, the maximum load
rating of the measurement inputs (see
Section 2.5) must be respected.

89431-302-401-602 / SLTS.12.04950 EN 55
9 Commissioning
(continued)

Testing the Protection Functions 0.14

¨ Normally inverse: t = KG ⋅ s
in Operating Mode DTOC
(I INB )0.02 − 1
By way of applying appropriate quantities to be measured,
the overcurrent stages and the associated time lags may 13 .5
be tested. ¨ Very inverse: t = KG ⋅ s
( NB ) − 1
I I
Caution: In applying quantities to be measured to the
measurement inputs, the maximum load 80
¨ Extremely inverse: t = KG ⋅ s
rating of the measurement inputs (see
Section 2.5) must be respected.
(I INB )2 − 1

Testing the Protection Functions 120

¨ Long time inverse: t = KG ⋅ s
in Operating Mode IDMT (I INB ) − 1
By way of applying appropriate quantities to be measured,
the overcurrent stages and the associated time lags may 1
¨ RI Inverse: t = KG ⋅ s
be tested. 0.236
0.339 −
(I INB )
Caution: In applying quantities to be measured to the
measurement inputs, the maximum load
For currents in excess of 20žI/IB or I/INB the operate delays
rating of the measurement inputs (see
Section 2.5) must be respected. are limited towards smaller values.

The phase current timer stage I> (=1.1· IB) operates in Completion of Commissioning
inverse time-delay mode. Depending on the selected Before the protection device is released for operation, make
tripping characteristics, the tripping time is obtained as sure that
follows.
¨ An offset adjustment has been carried out (needed only
0.14 if the measurement range for INB has been changed at
¨ Normally inverse: t = KL ⋅ s
0.02
(I IB ) −1 address 17 64).

¨ All signal and monitoring signal memories are reset

13 .5 (reset at addresses 03 06 and 03 08).
¨ Very inverse: t = KL ⋅ s
(I IB ) − 1
¨ The desired return address is set
80 (at address 03 13.)
¨ Extremely inverse: t = KL ⋅ s
2
(I IB ) −1 ¨ Any relay blocking is lifted
(address 21 14, value of "0").
120
¨ Long time inverse: t = KL ⋅ s
( NB ) − 1
I I ¨ Protection is active ("on")
(address 03 30, value of "1").
1 ¨ The password is active
¨ RI Inverse: t = KL ⋅ s
0.236 (if the keyboard is to be locked)
0.339 −
(I IB ) (address 03 11, value of "1").

The residual current timer stage IN> (= INB or 1.1· INB) may
optionally be operated in inverse or definite time-delay
mode. For the inverse time-delay mode the tripping time is
obtained as follows depending on the set tripping
characteristic.
¨ The change-enabling function is disabled
(address 03 10, value of "0").
Finally, the keyboard may be locked as described in
Chapter 6.
Make sure that only the green LED indicator H2 is lit up
when you leave the device.

56 89431-302-401-602 / SLTS.12.04950 EN
10 Troubleshooting

Listed below are several conceivable problems, their 90 21 MON: Operat. watchdog
causes, and possible methods for eliminating them. This Processor malfunction.
section is intended as a general orientation only, and in Response: warm restart
cases of doubt it is better to return the PS 431 to the Output relay: latching
manufacturer. In such cases the packaging instructions in
the “Unpacking and Packing” section of Chapter 5 must be 90 22 MON: Aux. voltage
followed. Auxiliary voltage present but below the
minimum permitted value.
Malfunctioning Response: blocking (will be lifted when the
voltage is restored)
¨ The 7-segment displays do not light up after connection
Output relay: latching
to the supply voltage. 90 26 MON: Local system const.
n Test whether the ribbon cable between the I / O Checksum error in the internal constants
module and the processor board is plugged in. (The area.
front panel needs to be removed first.) Response: warm restart or blocking
Output relay: updating
¨ The protection device signals “Warning”.
Identify the specific problem by reading out the 90 27 MON: Timer
monitoring signal memory (see Chapter 6, Section Processor timer defective.
“Monitoring Signal Memory Readout”). The following Response: warm restart or blocking
table lists the possible monitoring signal entries, the Output relay: updating
faulty area, the PS 431 response and the mode of an 90 28 MON: Cold restart
output relay configured for the warning. A cold restart was carried out.
Response: none
90 00 MON: PROM Output relay: latching
Checksum error in the EPROM and
EEPROM area 98 30 MON: Meas.val.acquisition
Response: warm restart or blocking After carrying out the offset adjustment for
Output relay: updating the A / D converter, offset not computed.
Response: warm restart or blocking
90 01 MON: RAM Output relay: latching
Write or read error in the RAM area
Response: warm restart or blocking
Output relay: updating ¨ The PS 431 signals “Blocked/faulty“.

90 02 MON: Exception n Check to see whether there is a “Warning“ signal. If

Processor malfunction. so, read out the monitoring signal memory.
Response: warm restart or blocking n Check to see whether there the protection is
Output relay: latching switched off (at address 03 30).
90 03 MON: Parameters n Check to see whether the protection device is
Checksum error in the settings area. blocked via the integrated local control panel (check
Response: cold restart at address 21 14).
Output relay: updating
n Check to see whether the protection device is
blocked via a binary signal input.
90 13 MON: Signal memory
Checksum error in the area of fault signals. Should all testing procedures turn out to be without result
Response: warm restart or clearing of all and fail to remove the problem, then please return the
fault signals device, complete with a description of the problem, to the
Output relay: updating factory.
90 14 MON: Monitor sig. memory
Checksum error in the area of the
monitoring signal memory.
Response: warm restart or clearing of
monitoring signals
Output relay: updating

89431-302-401-602 / SLTS.12.04950 EN 57
11 Maintenance
The PS 431 is a low-maintenance device. The components
used in the units are selected so that they meet exacting
requirements.
Whenever the measurement range for INB (address 17 64) is
changed, or after a cold restart (warning at address 90 28),
an offset adjustment of the A / D converter needs to be
carried out. First check to make sure that no current is
present in the measurement inputs of the protection device.
The offset adjustment is performed by changing address 17
63 to carry the value “1“. After completing the offset
adjustment, the value returns to “0“.
The PD 551 is used as a safety device and must therefore
be routinely checked for proper operation. The first function
check after commissioning should be carried out after 6 to
12 months. Additional function checks should be carried
out at intervals of about 2 to 3 years – at the latest after
four years.
Routine Functional Testing
The PQ 731 digital protective device incorporates in its
system a very extensive self-monitoring function for
hardware and software. The internal structure guarantees,
for example, that communication within the processor
system will be checked on a continuing basis.
Nonetheless, there are a number of subfunctions that
cannot be checked by the self-monitoring feature without
running a test from the device terminals. The respective
device-specific properties and setting parameters must be
observed in such cases.
In particular, none of the control and signaling circuits run
to the device from the outside are checked by the self-
monitoring function.
58
Analog Input Circuits
Within the PS 431 an analog-digital converter is used to
convert analog measured variables. However, an instrument
transformer, filter, analog multiplexer and ⋅1/⋅8 amplifier are
also incorporated in each single measuring channel so that
a test from the device terminals is required in order to verify
proper functioning. The supply voltages are monitored
continuously.
A static test of the analog input circuits is best carried out
using operating value measurement of the primary
measured operating variables or with the aid of a suitable
testing device. A “small” measured variable (such as the
nominal current) and a “large” measured variable (for
example, 6⋅Inom ) should be used to check the effective
range of the A/D converter. In this way the total modulation
range is checked, including gain change-overs. The gain
change-over occurs at a modulation of 1/8 of full scale. For
the PS 431 this would be at approximately 5žInom in the
current path for a full modulation of 40žInom.
A check of the change-over point of the gain change-over is
difficult since the latter is determined by the hardware
configuration. The only indication is a change in the
measurement resolution. In the current path we obtain
quantization levels of approximately 0.02žInom in the lower
range and 0.16žInom in the upper range.
The operating data measurement error is <5%. An
important factor in evaluating device performance is the
long-term performance as determined from comparison with
previous measurements.
Additional testing in the analog area is not necessary.
89431-302-401-602 / SLTS.12.04950 EN
11 Maintenance
(continued)
Binary Inputs
The binary inputs are not checked as part of self-monito-
ring. Therefore a test function is integrated into the device
software so that the control state of the individual input can
be read out at a matrix point address (54 00 and 54 03),
where "0" is “low” (not controlled) and "1" is “high”
(controlled). This check should be performed for each input
being used, and if necessary it can be done without
disconnecting the unit wiring.
Binary Outputs
There is no monitoring function for the external contact
circuit. Therefore triggering of the all-or-nothing relays must
be initiated through protection functions. A test function is
integrated into the unit software so that the control state of
the individual output relay can be read out at a matrix point
address (51 00 and up): "0" means that the output relay is
inactive and "1" means that the output relay is active.
89431-302-401-602 / SLTS.12.04950 EN
Serial Interface
The entire communications system, including the
interconnection, is always completely monitored as long as
a link has been created by the FPC program.
Other Internal Functions
o Timer Stages
All timer stages in the digital protection device are
derived from the precision clock pulse of the
microprocessor. The oscillators have a maximum error
of < ± 100 ppm. This means that a timer stage of 10 s
has a maximum error of 1 ms. For this reason, it is not
possible to check the accuracy of the timer stages by
functional testing, since the scatter of the starting and
measuring times is greater than this error.
However, the processor clock frequency is checked as
part of a rough monitoring routine during startup of the
protection device so that it is possible to detect
complete failures. In this check during system start the
clock frequency of the microprocessor modules is
compared with the setpoint values specified for the unit.
o Power Supply Unit
In the area of system monitoring there is a check for the
presence of internal voltages. The internal operating
voltages used in normal operation have approximately
50% of their maximum operational load.
59
12 Storage

The device must be stored in a dry and clean environment.

A temperature range of -25°C to +55°C must be maintained
(see Chapter 2 "Technical Data"). Relative humidity must
not result in either condensation or ice formation.

60 89431-302-401-602 / SLTS.12.04950 EN
13 Accessories and Spare Parts

The PS 431 is supplied with standard labeling. User-

specific labeling can be written onto the reverse side of the Description: Order No.:
label strips or onto blank strips available as accessories.
The label strips can be accessed from the rear of the front Label strips 89512-4-0345616
panel. (10 sets, blank)

Turn off any auxiliary voltage before replacing the Cover frame with accessories 89412-4-0339264
! label strips. Components located behind the front
panel are energized. PC connection cable 255 002 096

After four bolts on the front face of the front panel are FPCC parameter setting 251 254 271
released and the two flat connectors (internal grounding) is program
detached from the rear of the front panel, it is possible to
remove the control module (front panel and computer FPC operating program 251 254 676
module), which is connected to the input / output module
by a plug-in ribbon cable. The label strip can be removed or
inserted from the lower rear side of the front panel.

Before mounting the front panel the flat connector

! of the grounding cable must be inserted on the
rear of the front panel.

Labeling can be applied to the label strips by one of the

following methods:

¨ Overhead projector pen, waterproof type, for example,

"Stabilo" brand pen, OH Pen 196 PS.

¨ Typewriter with a pure silk fabric ribbon, for example,

“Pelikan“ brand, type 58 A 371.

¨ Laser printer.

89431-302-401-602 / SLTS.12.04950 EN 61
14 Order Information

Designs Order No.

Time-Overcurrent Protection Device PS 431 89431 -0 - ¨ ¨ ¨ ¨ ¨ ¨ 0 -302 -401 ¨ ¨ -602

     
Design      
Case (surface-mounting) 1       
Case (flush) with cover frame 2       
      
Variants      
 
 
 
 
 
 

Nominal current I nom = 1A / 5A <3> 1      
Nominal frequency f nom = 50 / 60Hz 2     
Nominal auxiliary voltage VA ,nom     
VA,nom = 24 to 60 V DC / 110 to 250 V DC, 100 to 230 V AC T 3    
Control volt. VIn,nom = 24 to 250 V DC 3   
  
Relays with standard contact mat. 1  
  
Labels & and supp. documents in Engl. <1> -598 
Acceptance test certificate B according to DIN 50049 - 3.1B <2> -599

<1> Valid for ordering prior to device production. Available as accessory (separate position) for stock items.
<2> Must be ordered prior to device production. This order extension no. will not be printed on the name label of the device or shipping box.
<3> Nominal current user-selected via choice of connection terminal.
T Settable range, delivery setting underlined.

62 89431-302-401-602 / SLTS.12.04950 EN
Appendix

Appendix Table of Contents

A Glossary 64
A1 Function Groups 64
A2 Symbols 65
A3 Examples of Signal Names 69
A4 Symbols Used 69

B Internal Signal Names 70

C Address List 71
C1 Parameters 72
C 1.1 Device Identification 72
C 1.1.1 Ordering Information 72
C 1.1.2 Design Version 72
C 1.2. Configuration Parameters 73
C 1.2.1 Control Interfaces 73
C 1.2.2 Binary Inputs 73
C 1.2.3 Binary Outputs 73
C 1.2.4 LED Indicators 74
C 1.3 Function Parameters 75
C 1.3.1 Global 75
C 1.3.2 DTOC Protection Mode 76
C 1.3.3 IDMT Protection Mode 77
C 1.3.4 Supplementary Functions 78
C2 Operation 79
C 2.1 Operating Value Measurement 79
C 2.2 State Signals 79
C 2.2.1 Functions 79
C 2.2.2 Binary Inputs 79
C 2.2.3 Binary Outputs 79
C 2.3 Control and Testing 80
C 2.4 Monitoring Signals 80
C3 Events 81
C 3.1 Event Counters 81
C 3.2 Fault Data Acquisition 81
C 3.3 Fault Signals 81

D Set Value Record Sheets 82

D 1 Device Identification 83
D 1.1 Ordering Information 83
D 1.2 Design Version 83
D 2 Configuration Parameters 84
D 2.1 Control Interfaces 84
D 2.2 Binary Inputs 84
D 2.3 Binary Outputs 84
D 2.4 LED Indicators 84
D 3 Function Parameters 85
D 3.1 Global 85
D 3.2 DTOC Protection Mode 86
D 3.3 IDMT Protection Mode 86
D 3.4 Supplementary Functions 87

E Terminal Connection Diagram 88

89431-302-401-602 / SLTS.12.04950 EN 63
A Glossary

A 1 Function Groups

CBF: Circuit breaker failure protection

DTOC: Definite-time overcurrent protection
FMEAS: Fault data acquisition
IDENT: Device identification
IDMT: Inverse-time overcurrent protection
INP: Binary input
LED: LED indicator
LOC: Local control panel
MAIN: Main function
MCM: Measuring circuit monitoring
MON: Self-monitoring
OMEAS: Operating value measurement
OUTP: Binary output
PC: PC link

64 89431-302-401-602 / SLTS.12.04950 EN
A Glossary
(continued)
A 2 Symbols
Symbol
Graphic symbols for block diagrams
Binary elements
according to DIN 40900 Part 12, September 1992,
IEC 617-12: amended 1991
Analog information processing
according to DIN 40900 Part 13, January 1981
To document the linking of analog and binary signals,
additional symbols have been used, taken from several DIN
documents.
As a rule, direction of the signal flow is from left to right and
from top to bottom. Other flow directions are marked by an
arrow. Input signals are listed on the left side of the signal
flow, output signals on the right side.
Symbol Description
To obtain more space for
representing a group of related
elements, contours of the
elements may be joined or
= cascaded if the following rules
are met:
There is no functional linkage
between elements whose
common contour line is
oriented in the signal flow
direction.
Note:
This rule does not necessarily
apply to configurations with
two or more signal flow
directions, such as for
symbols with a control block
and an output block.
There exists at least one
logical link between elements
whose common contour line
runs perpendicularly to the
signal flow direction.
89431-302-401-602 / SLTS.12.04950 EN
Description
Components of a symbol
A symbol consists of a
contour or contour
combination and one or more
qualifiers.
Control block
A control block contains an
input function common to
several symbols. It is used for
the collective setting of several
trigger elements, for
example.
Output block
An output block contains an
output function common to
several symbols.
Settable control block
The four digits represent the
address under which the
function shown in the text after
the colon may be set via the
local control panel.
Settable control block with
function blocks
The digits in the function block
show the settings that are
possible at this address.
The text below the symbol
shows the setting and the
corresponding unit or meaning.
65
A Glossary
(continued)
Symbol Description
Static input
Only the state of the binary
input variable is effective.
Dynamic input
Only the transition from value
0 to value 1 is effective.
Negation of an output
The value up to the border line
is negated at the output.
Negation of an input
The input value is negated
before the border line.
Dynamic input with negation
Only the transition from value
1 to value 0 is effective.
AND element
The output variable will be 1
only if all input variables are 1.
OR element
The output variable will be 1
only if at least one input
variable is 1.
Threshold element
The output variable will be 1
only if at least two input
variables are 1. The number in
the symbol may be replaced
by any other number.
66
Symbol Description
(m out of n) element
The output variable will be 1
only if just one input variable is
1.
The number in the symbol
may be replaced by any other
number if the number of inputs
is increased or decreased
accordingly.
Delay element
The transition from value 0 to 1
at the output occurs after a
time delay of t1 relative to the
corresponding transition at the
input.
The transition from value 1 to 0
at the output occurs after a
time delay of t2 relative to the
corresponding transition at the
input.
t1 and t2 may be replaced by
the actual delay values (in
seconds or strobe ticks).
Monostable flip-flop
The output variable will be 1
only if the input variable
changes to 1. The output
variable will remain 1 for
100 ms, independent of the
duration of the input value 1
(non-retriggerable).
Without a 1 in the function
block the monostable flip-flop
is retriggerable.
The time is 100 ms in this
example, but it may be
changed to any other duration.
89431-302-401-602 / SLTS.12.04950 EN
A Glossary
(continued)

Symbol Description Symbol Description

Analog-digital converter Amplifier

An analog input signal is The output variable is 1 only if
converted to a binary signal. the input variable is also 1.

Band pass filter

Subtractor
The output only transmits the
The output variable is the
50 Hz component of the input
difference between the two
signals. All other frequencies
input variables.
(above and below 50 Hz) are
A summing element is
attenuated.
obtained by changing the
minus sign to a plus sign at
Counter
the symbol input.
At the + input the input
variable transitions from 0 to 1
Schmitt Trigger with binary
are counted and stored in the
output signal
function block.
The binary output variable will
At the R(eset) input a
be 1 if the input signal
transition of the input variable
exceeds a specific threshold.
from 0 to 1 resets the counter
The output variable remains 1
to 0.
until the input signal drops
below the threshold again.
Electromechanical drive
in general, here a relay, for
Memory, general
example.
Storage of a binary or analog
signal.

Signal level converter

Non-stable flip-flop with electrical isolation
When the input variable between input and output.
changes to 1, a pulse L+ = pos. voltage input
sequence is generated at the L- = neg. voltage input
output. U1 = device identifier

The ! to the left of the G

indicates that the pulse
sequence starts with the input
variable transition
(synchronized start).
If there is a ! to the right of the
G, the pulse sequence ends
with the ending of the 1 signal
at the input (synchronized
stop).

89431-302-401-602 / SLTS.12.04950 EN 67
A Glossary
(continued)

Symbol Description Symbol Description

Input transducer PC interface

with conductor and device with pin connections
identifiers
(according to DIN EN 60445)

Conductor identifiers for

current inputs:
for A: A1 and A2
for B: B1 and B2
for C: C1 and C2
for N: N1 and N2 Multiplier
The output variable is the
Conductor identifiers for result of the multiplication of
voltage inputs the two input variables.
via transformer 1:
for A: 1U Divider
for B: 1V The output variable is the
for C: 1W result of the division of the two
for N: 1N input variables.
via transformer 2:
for A: 2U Comparator
for B: 2V The output variable becomes 1
only if the input variable(s) are
Device identifiers for current equal to the function in the
transformers: function block.
for A: T1
for B: T2 Formula block
for C: T3 The output variable becomes 1
for N: T4 only if the input variable(s)
for voltage transformer 1: satisfy the equation in the
for A: T5 function block.
for B: T6
for C: T7
for N: T8
for VG-N transformer: T90
for voltage transformer 2:
for A: T15

Change-over contact
with device identifier

Special symbol
Output relay in normally-
energized arrangement
(‘closed-circuit operation’).

68 89431-302-401-602 / SLTS.12.04950 EN
A Glossary
(continued)
A 3 Examples of Signal Names
All settings and signals relevant for protection are shown in
the block diagrams of Chapter 3 as follows:
Signal Name Description
u FREC: Fault start Internal signal names are not
coded by an address. In the
block diagrams they are
marked with a diamond.
The internal signal names
used and their origins are
listed in Appendix B.
DIST: Signal names coded by an
Z1' triggered address are referred to once
[ 3904 ] by their address (in square
brackets). The source is
documented in Chapters 7 and
8.
DIST: Subsequent references use
Z1' triggered the signal name only.
MAIN: Control ext. A specific setting to be used
↑ no (off) later on is shown with its
signal name and the setting
with preceding setting arrow.
89431-302-401-602 / SLTS.12.04950 EN
A 4 Symbols Used
Symbol Meaning
t Time, duration
V Voltage, potential difference
V Complex voltage
I Electrical current
I Complex current
Z Complex impedance
Z Modulus of complex
impedance
f Frequency
δ Temperature in °C
Σ Sum, result
Ω Unit of electrical resistance
α Angle
ϕ Phase angle. With subscripts:
specific angle between a
defined current and a defined
voltage.
τ Time constant
∆T Temperature difference in K
69
B Internal Signal Names

Internal signal names are not coded by an address. They

are indicated by a diamond in the block diagram. 1

Internal signal names Figure

Self-monit. blocking 24
MAIN: Autom. reset 20
MAIN: Block. tI> 12
MAIN: Block. tI>> 12
MAIN: Block. tIN> 12
MAIN: Block. tIN>> 12
MAIN: General reset 20
MAIN: Manual reset 20
IDMT/DTOC: Trip criterion 16
IDMT/DTOC: tI>/tIref elapsed 3
IDMT/DTOC: tI>> elapsed 3
IDMT/DTOC: tIN>/tINref elapsed 3
IDMT/DTOC: tIN>> elapsed 3
CBF: Trip by CBF 14
Signals 17
FREC: Reset signal mem. 20
FREC: Fault running 19
Warning 24

1
Iref in the signal names corresponds to IB (as reference current)
in the address list.

70 89431-302-401-602 / SLTS.12.04950 EN
C Address List

Changing Values KEY

on: "on" (on-line) means that the value can be changed f): A change in value is possible without activating
even when the protective function is enabled. the value-change enabling function.
off: "off" (off-line) means that the value can be changed n): Indication "..." is possible and means that no
provided that the protective function is disabled. value has been measured.
-: "-" means that the value cannot be modified by o): Indication "-..-" is possible and means that the
control action. value is out of range.
p): The value change is password-protected.
u): The setting "∞" is represented by the "0--0"
display.

89431-302-401-602 / SLTS.12.04950 EN 71
C Address List
(continued)

C 1 Parameters

C 1.1 Device Identification

C 1.1.1 Ordering Information

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

00 00 IDENT: Device type - 431 PS 431

00 50 IDENT: Auxiliary voltage off 0 0 ... 999 V 1
00 55 IDENT: Control voltage off 0 0 ... 999 V 1

C 1.1.2 Design Version

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

02 00 IDENT: Data model - 101 100 ... 600 Version No. 1

02 18 IDENT: SW version L - 1.0x 0.00 ... 99.99 Version number 0.01
02 60 IDENT: Auxiliary address for internal use

72 89431-302-401-602 / SLTS.12.04950 EN
C Address List
(continued)

C 1.2 Configuration Parameters

C 1.2.1 Control Interfaces

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

03 11 LOC: Access lock active on 0 0 / 1 no / yes

03 13 LOC: Autom. return addr. on 310.0 0.00 ... 9999 1.00

C 1.2.2 Binary Inputs

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

54 01 INP: Fct. assignm. U 1 off - - Without function

54 04 INP: Fct. assignm. U 2 off - 4003 CBF: Input EXT
4014 MAIN: Block outp.rel. EXT
4015 MAIN: Reset latch. EXT
4023 MAIN: Reset indicat. EXT
4035 MAIN: Reset latch.+indic.
4060 MAIN: E1 block EXT
4061 MAIN: E2 block EXT

54 02 INP: Operating mode U 1 off 1 0 / 1 active "low" / "high"

54 05 INP: Operating mode U 2 off 1 0 / 1 active "low" / "high"

C 1.2.3 Binary Outputs

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

51 01 OUTP: Fct. assignm. K 1 off - - Without function

51 03 OUTP: Fct. assignm. K 2 off - 0465 MAIN: Blocked/faulty
51 05 OUTP: Fct. assignm. K 3 off - 3670 MON: Warning
51 07 OUTP: Fct. assignm. K 4 off - 4000 IDMT/DTOC: Gen. starting
4004 MAIN: Trip command
4008 IDMT/DTOC: Starting GF
4010 DTOC: tI> elapsed def. 1)
4011 IDMT/DTOC: tI>> elapsed
4013 IDMT/DTOC: tIN> elapsed
4022 CBF: tCBF elapsed
4027 MON: tmcm
4028 IDMT/DTOC: tIN>> elapsed
4029 IDMT/DTOC: Starting I>>
4031 IDMT/DTOC: tI(B)>/>>
4032 IDMT/DTOC: tIN(B)>/IN>>
4036 IDMT/DTOC: Start.I> V IB>
4050 IDMT: tI> elapsed inv. 2)
4051 IDMT: tINB elapsed inv. 2)

1) DTOC protection mode only

2) IDMT protection mode only

89431-302-401-602 / SLTS.12.04950 EN 73
C Address List
(continued)

C 1.2.4 LED Indicators

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

57 01 LED: Fct. assignm. H 1 - 36.70 3670 MON: Warning

57 03 LED: Fct. assignm. H 2 - 04.65 0465 MAIN: Blocked/faulty

57 05 LED: Fct. assignm. H 3 off - - Without function

57 07 LED: Fct. assignm. H 4 off - 4000 IDMT/DTOC: Gen. starting
57 09 LED: Fct. assignm. H 5 off - 4003 CBF: Input EXT
57 11 LED: Fct. assignm. H 6 off - 4004 MAIN: Trip command
57 13 LED: Fct. assignm. H 7 off - 4005 IDMT/DTOC: Starting A
57 15 LED: Fct. assignm. H 8 off - 4006 IDMT/DTOC: Starting B
4007 IDMT/DTOC: Starting C
4008 IDMT/DTOC: Starting GF
4010 DTOC: tI> elapsed def. 1)
4011 IDMT/DTOC: tI>> elapsed
4013 IDMT/DTOC: tIN> elapsed
4022 CBF: tCBF elapsed
4027 MON: tmcm
4028 IDMT/DTOC: tIN>> elapsed
4029 IDMT/DTOC: Starting I>>
4031 IDMT/DTOC: tI(B)>/>>
4032 IDMT/DTOC: tIN(B)>/IN>>
4036 IDMT/DTOC: Start.I> V IB>
4050 IDMT: tI> elapsed inv. 2)
4051 IDMT: tINB elapsed inv. 2)
4060 MAIN: E1 block EXT
4061 MAIN: E2 block EXT

1) DTOC protection mode only

2) IDMT protection mode only

74 89431-302-401-602 / SLTS.12.04950 EN
C Address List
(continued)

C 1.3 Function Parameters

C 1.3.1 Global

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment
03 30 MAIN: Protection active on 0 0 / 1 no (=off) / yes (=on)

17 27 MAIN: Gen. start. mode off 1 0 without IN> v IN>>

1 with IN> v IN>>

17 28 MON: Meas. circ. monitor on 111 000 without MCM

101 with I1, I3
111 with I1, I2, I3

17 31 MAIN: Fct.assignm.Trip1/2 off 1111 1000 tI>

1001 tI>, CBF
1010 tI>, tIN>
1011 tI>, tIN>,CBF
1100 tI>,tI>>
1101 tI>,tI>>, CBF
1110 tI>,tI>>,tIN>
1111 tI>,tI>>,tIN>,CBF

17 32 MAIN: Latching mode 1/2 off 0000 0000 without latching

0001 CBF
0010 tIN>
0011 tIN>,CBF
0100 tI>>
0101 tI>>, CBF
0110 tI>>,tIN>
0111 tI>>,tIN>,CBF
1000 tI>
1001 tI>, CBF
1010 tI>, tIN>
1011 tI>, tIN>,CBF
1100 tI>,tI>>
1101 tI>,tI>>, CBF
1110 tI>,tI>>,tIN>
1111 tI>,tI>>,tIN>,CBF

17 33 MAIN: Fct.assignm.Trip2/2 off 0010 0000 Without function

0010 tIN>>

17 34 MAIN: Latching mode 2/2 off 0000 0000 without latching

0010 tIN>>

17 61 MAIN: Protection mode off 3 1 DTOC } Cold restart

3 IDMT } when changed!

17 90 MAIN: Block mode E1 off 1100 0000 no blockage

17 92 MAIN: Block mode E2 off 0011 0001 tIN>>
0010 tIN>
0011 tIN>,tIN>>
0100 tI>>
0101 tI>>, tIN>>
0110 tI>>,tIN>
0111 tI>>,tIN>,tIN>>
1000 tI>
1001 tI>, tIN>>
1010 tI>, tIN>
1011 tI>, tIN>,tIN>>
1100 tI>,tI>>
1101 tI>,tI>>, tIN>>
1110 tI>,tI>>,tIN>
1111 tI>,tI>>,tIN>,tIN>>

21 14 MAIN: Outp.rel. block USR on 1 0 / 1 no / yes

89431-302-401-602 / SLTS.12.04950 EN 75
C Address List
(continued)

C 1.3.2 DTOC Protection Mode

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

17 00 DTOC: I> on 1.0 0.4 ... 4.0 I,nom 0.1

17 01 IDMT/DTOC: I>> on 4.0 0.4 ... 40.0 /∞ I,nom 0.1 u)
17 03 DTOC: IN> on 0.20 0.05 ... 2.00 /∞ I,nom 0.05 u)

17 04 DTOC: tI> on 1.00 0.00 ... 9.99 /∞ s 0.01 u)

10.0 ... 99.9 0.1

17 06 IDMT/DTOC: tI>> on 0.50 0.00 ... 9.99 /∞ s 0.01 u)

17 08 IDMT/DTOC: tIN> on 1.00 0.00 ... 9.99 /∞ s 0.01 u)

10.0 ... 99.9 0.1

17 09 IDMT/DTOC: IN>> on ∞ 0.10 ... 8.00 /∞ I,nom 0.05 u)

17 10 IDMT/DTOC: tIN>> on 0.50 0.00 ... 9.99 /∞ s 0.01 u)

10.0 ... 99.9 0.1

76 89431-302-401-602 / SLTS.12.04950 EN
C Address List
(continued)

C 1.3.3 IDMT Protection Mode

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

17 01 IDMT/DTOC: I>> on 4.0 0.4 ... 40.0 /∞ I,nom 0.1 u)

17 06 IDMT/DTOC: tI>> on 0.50 0.00 ... 9.99 /∞ s 0.01 u)

17 08 IDMT/DTOC: tIN> on 1.00 0.00 ... 9.99 /∞ s 0.01 u)

10.0 ... 99.9 0.1

17 09 IDMT/DTOC: IN>> on ∞ 0.10 ... 8.00 /∞ I,nom 0.05 u)

17 10 IDMT/DTOC: tIN>> on 0.50 0.00 ... 9.99 /∞ s 0.01 u)

10.0 ... 99.9 0.1

17 13 IDMT: IB on 1.00 0.40 ... 4.00 I,nom 0.01

17 14 IDMT: INB on 0.20 0.04 ... 0.40 /∞ I,nom with 1764 = 8 I,nom 0.01 u)
0.08 ... 0.80 /∞ I,nom with 1764 = 16 I,nom 0.01 u)

17 35 IDMT: Character. type L off 1 1 normally inverse

2 very inverse
3 extremely inverse
4 long time inverse
5 RI inverse

17 36 IDMT: Character.factor kL on 1.00 0.10 ... 1.00 0.05

17 37 IDMT: Charact. category N off 2 1 Definite-time delay(def.)

2 Inverse-time delay (inv.)

17 38 IDMT: Character. type N off 1 1 normally inverse

2 very inverse
3 extremely inverse
4 long time inverse
5 RI inverse

17 39 IDMT: Character.factor kG on 1.00 0.10 ... 1.00 0.05

17 64 MAIN: INB range off 8 8 INB > IDMT max. 0.4 I,nom
16 INB > IDMT max. 0.8 I,nom

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C Address List
(continued)

C 1.3.4 Supplementary Functions

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

Circuit Breaker Failure

Protection

17 20 CBF: tCBF on 1.00 0.00 ... 9.99 /∞ s 0.01 u)

Measuring Circuit Monitoring

17 23 MON: tmcm> on 5.00 0.00 ... 9.99 s 0.01

10.0 ... 99.9 0.1

17 24 MON: Imcm> on 0.50 0.25 ... 0.50 I,nom 0.05

78 89431-302-401-602 / SLTS.12.04950 EN
C Address List
(continued)

C 2 Operation

C 2.1 Operating Value Measurement

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

04 44 OMEAS: Current IN p.u. - 0.00 ... 3.50 I,nom 0.01 n)o)

05 51 OMEAS: Curr. IL,max p.u. - 0.00 ... 18.00 I,nom 0.01 n)o)
05 52 OMEAS: Current A p.u. - 0.00 ... 18.00 I,nom 0.01 n)o)
05 53 OMEAS: Current B p.u. - 0.00 ... 18.00 I,nom 0.01 n)o)
05 54 OMEAS: Current C p.u. - 0.00 ... 18.00 I,nom 0.01 n)o)

C 2.2 State Signals

C 2.2.1 Functions

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

21 15 MAIN: Outp.relays blocked - 0 / 1 no / yes

C 2.2.2 Binary Inputs

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

54 00 INP: State U 1 - 0 / 1 "low" / "high"

54 03 INP: State U 2 - 0 / 1 "low" / "high"

C 2.2.3 Binary Outputs

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

51 00 OUTP: State K 1 - 0 / 1 inactive/active

51 02 OUTP: State K 2 - 0 / 1 inactive/active
51 04 OUTP: State K 3 - 0 / 1 inactive/active
51 06 OUTP: State K 4 - 0 / 1 inactive/active

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C Address List
(continued)

C 2.3 Control and Testing

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

03 06 FREC: Reset sig. memory on 0 0 ... 9999 Reset : 2x E Key 1

03 08 MON: Reset mon. sig. mem. on 0 0 ... 30 Reset : 2x E Key 1

03 10 LOC: Value change enable on 0 0 / 1 no / yes

03 39 MAIN: Warm restart off 0 0 / 1 no / yes

03 40 MAIN: Man. trip cmd. USR on 0 0 / 1 no / yes

17 63 MAIN: A/D offset adj. off 0 0 / 1 no / yes

21 09 MAIN: Reset latch. USR on 0 0 / 1 no / yes

C 2.4 Monitoring Signals

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

03 01 MON: Mon. signal memory - 0 ... 30 Entry into memory 1

Possible Entries

90 00 MON: PROM - 0 EPROM

1 EEPROM

90 01 MON: RAM - 0 internal

1 external

90 02 MON: Exception - 3 DCX error reset

4 no interrupt active

90 03 MON: Parameters - 1 Checksum error

90 13 MON: Signal memory - 2 Checksum error
90 14 MON: Monitor sig. memory - 3 Checksum error
90 21 MON: Operat. watchdog - 7 Reset
90 22 MON: Aux. voltage - 0 Power fail w/o HW reset
90 26 MON: Local system const. - 2 Checksum
90 27 MON: Timer - 3 Not running
90 28 MON: Cold restart - 0 After checksum checking

98 30 MON: Meas.val.acquisition - 0 Calibration not carr. out

Cold / Warm Restart

99 00 MON: Initialization - 0 RAM (internal)

1 RAM (external)
6 EPROM
7 EEPROM
12 Activate operating system
14 Power failure
18 Cold restart

80 89431-302-401-602 / SLTS.12.04950 EN
C Address List
(continued)

C 3 Events

C 3.1 Event Counters

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

04 05 MAIN: No. of trip cmds - 0 ... 9999 Reset : 2x E Key 1 o)

04 20 FREC: No. of fault - 0 ... 9999 Reset via 03 06 1

C 3.2 Fault Data Acquisition

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

04 21 FMEAS: Operating time - 0.00 ... 99.99 s 0.01 o)

04 25 FMEAS: Fault current p.u. - 0.00 ... 36.00 Inom 0.01 n)o)

C 3.3 Fault Signals

Address Description Change Default Range of Values Unit or Meaning Incre-

x y ment

03 00 FREC: Signal memory - ---L Entry into memory 1

Possible Entries

03 30 MAIN: Protection active - 0 / 1 End / Start

21 09 MAIN: Reset latch. USR - 0 / 1 End / Start
21 14 MAIN: Outp.rel. block USR - 0 / 1 End / Start
35 01 FREC: Signal mem.overflow - 0 / 1 End / Start
36 70 MON: Warning - 0 / 1 End / Start
40 00 IDMT/DTOC: Gen. starting - 0 / 1 End / Start
40 03 CBF: Input EXT - 0 / 1 End / Start
40 04 MAIN: Trip command - 0 / 1 End / Start
40 05 IDMT/DTOC: Starting A - 0 / 1 End / Start
40 06 IDMT/DTOC: Starting B - 0 / 1 End / Start
40 07 IDMT/DTOC: Starting C - 0 / 1 End / Start
40 08 IDMT/DTOC: Starting GF - 0 / 1 End / Start
40 10 DTOC: tI> elapsed def. - 0 / 1 End / Start
40 11 IDMT/DTOC: tI>> elapsed - 0 / 1 End / Start
40 13 IDMT/DTOC: tIN> elapsed - 0 / 1 End / Start
40 14 MAIN: Block outp.rel. EXT - 0 / 1 End / Start
40 15 MAIN: Reset latch. EXT - 0 / 1 End / Start
40 22 CBF: tCBF elapsed - 0 / 1 End / Start
40 28 IDMT/DTOC: tIN>> elapsed - 0 / 1 End / Start
40 29 IDMT/DTOC: Starting I>> - 0 / 1 End / Start
40 35 MAIN: Reset latch.+indic. - 0 / 1 End / Start
40 50 IDMT: tI> elapsed inv. - 0 / 1 End / Start
40 51 IDMT: tINB elapsed inv. - 0 / 1 End / Start
40 60 MAIN: E1 block EXT - 0 / 1 End / Start
40 61 MAIN: E2 block EXT - 0 / 1 End / Start

89431-302-401-602 / SLTS.12.04950 EN 81
D Set Value Record Sheets

Serial No. 6.

Order No. 89431-0-

Diagram No. 89431.401

Nominal device data

Inom A AC

VA,nom V DC

82 89431-302-401-602 / SLTS.12.04950 EN
D Set Value Record Sheets
(continued)

D 1 Device Identification

D 1.1 Ordering Information

Address Description Value Unit or Meaning

x y

00 00 IDENT: Device type 431 PS 431

00 50 IDENT: Auxiliary voltage

00 55 IDENT: Control voltage

D 1.2 Design Version

Address Description Value Unit or Meaning

x y

02 00 IDENT: Data model 101

02 18 IDENT: SW version L 1.0x Version number

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D Set Value Record Sheets
(continued)

D 2 Configuration Parameters

D 2.1 Control Interfaces

Address Description Value Unit or Meaning

x y

03 11 LOC: Access lock active

03 13 LOC: Autom. return addr.

D 2.2 Binary Inputs

Address Description Value Unit or Meaning

x y

54 01 INP: Fct. assignm. U 1

54 04 INP: Fct. assignm. U 2

54 02 INP: Operating mode U 1

54 05 INP: Operating mode U 2

D 2.3 Binary Outputs

Address Description Value Unit or Meaning

x y

51 01 OUTP: Fct. assignm. K 1

51 03 OUTP: Fct. assignm. K 2

51 05 OUTP: Fct. assignm. K 3

51 07 OUTP: Fct. assignm. K 4

D 2.4 LED Indicators

Address Description Value Unit or Meaning

x y

57 01 LED: Fct. assignm. H 1 36 70 MON: Warning

57 03 LED: Fct. assignm. H 2 04 65 MAIN: Blocked/faulty

57 05 LED: Fct. assignm. H 3

57 07 LED: Fct. assignm. H 4

57 09 LED: Fct. assignm. H 5

57 11 LED: Fct. assignm. H 6

57 13 LED: Fct. assignm. H 7

57 15 LED: Fct. assignm. H 8

84 89431-302-401-602 / SLTS.12.04950 EN
D Set Value Record Sheets
(continued)

D 3 Function Parameters

D 3.1 Global

Address Description Value Unit or Meaning

x y

03 30 MAIN: Protection active

17 27 MAIN: Gen. start. mode

17 28 MON: Meas. circ. monitor

17 31 MAIN: Fct.assignm.Trip1/2

17 32 MAIN: Latching mode 1/2

17 33 MAIN: Fct.assignm.Trip2/2

17 34 MAIN: Latching mode 2/2

17 61 MAIN: Protection mode

17 90 MAIN: Block mode E1

17 92 MAIN: Block mode E2

21 14 MAIN: Outp.rel. block USR

89431-302-401-602 / SLTS.12.04950 EN 85
D Set Value Record Sheets
(continued)

D 3.2 DTOC Protection Mode

Address Description Value Unit or Meaning

x y

17 00 DTOC: I> Inom

17 01 IDMT/DTOC: I>> Inom

17 03 DTOC: IN> Inom

17 04 DTOC: tI> s

17 06 IDMT/DTOC: tI>> s

17 08 IDMT/DTOC: tIN> s

17 09 IDMT/DTOC: IN>> Inom

17 10 IDMT/DTOC: tIN>> s

D 3.3 IDMT Protection Mode

Address Description Value Unit or Meaning

x y

17 01 IDMT/DTOC: I>> Inom

17 06 IDMT/DTOC: tI>> s

17 08 IDMT/DTOC: tIN> s

17 09 IDMT/DTOC: IN>> Inom

17 10 IDMT/DTOC: tIN>> s

17 13 IDMT: IB Inom

17 14 IDMT: INB Inom

17 35 IDMT: Character. type L

17 36 IDMT: Character.factor kL

17 37 IDMT: Charact. category N

17 38 IDMT: Character. type N

17 39 IDMT: Character.factor kG

17 64 MAIN: INB range Inom

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D Set Value Record Sheets
(continued)

D 3.4 Supplementary Functions

Circuit Breaker Failure Protection:

Address Description Value Unit or Meaning

x y

17 20 CBF: tCBF s

Measuring Circuit Monitoring:

Address Description Value Unit or Meaning

x y

17 24 MON: Imcm> Inom

17 23 MON: tmcm> s

89431-302-401-602 / SLTS.12.04950 EN 87
E Terminal Connection Diagram

36 Terminal connection diagram for PS 431, diagram 89431-401 E

88 89431-302-401-602 / SLTS.11.04950 EN