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1 1

Compal Confidential
2 ZBWAA Bay Trail-M Schematics Document 2

Bay Trail-M Platform with DDR3L

LA-B303P REV 1.0 Schematic


3 3

Intel BayTrail-M Platform


Date : 2014/02/22 Version 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 Deciphered Date 2014/01/03 Title
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ZBWAA LA-B303P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 1 of 41
A B C D E
A B C D E

eDP 1X 5.4GT/s 204pin DDR3L-SO-DIMM X1


Memory BUS
1
P.15 1
LVDS Conn. LVDS Translator Dual Channel
Colay eDP P.17 RTD2132R-CG P.16
1.35V DDR3L 1066/1333

DDI Port1

DDI Port0 USB2.0 x3 port 0 port 2 port 3


HDMI Conn. 5V 480MHz
P.18

VALLEYVIEW-M USB3.0 x1 USB 3.0 Int. Camera USB HUB


Conn P.23 P.17 (STT) P.22
SATA II x2
2 2
port 1 port 0 SOC
SATA ODD SATA PCIE x4 NGFF E port 0

Conn. HDD/SSD 1.5V 5GT/s port 1 P.21


FCBGA 1170 Pin port 1 port 2
P.20 Conn. P.20
USB 2.0 Touch Screen
SPI VGAx1 Conn
page 05~12 P.23 P.17
Sub Boards
LPC BUS HD Audio
LS-B303P SPI ROM CRT Conn.
3 LAN(PCIE Port0)+USB(Port1) 1.8V (8MB) P.19 3
HDA Codec
Audio Combo Jack P.08 KB9012QF A4
ALC233
page 23 P.25 P.24

LS-B304P
Card Reader(PCIE Port2) + RTC CKT. KBD TP TPM SPK Conn
P.9
TP + Lid SW P.26 P.26 P.22 P.24
page 26
DC/DC Interface CKT.
P.27
LS-B301P
LED B page 26
4 Power Circuit DC/DC 4

P.28~P.35
LS-B302P Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/01/03 2014/01/03 Title
Deciphered Date Block Diagrams
Power Button B page 26 LED/Power On/Off THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
P.26 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 2 of 41
A B C D E
A B C D E

EC_ON
PU350
B+ DESIGN CURRENT 8A
Ipeak=8A, Imax=5.6A, Iocp=9A +5VALW
SY8208CQNC
SUSP#
U10
DESIGN CURRENT 6.2A +5VS
TPS22967DSGR
+5VS
U16
DESIGN CURRENT 1A +HDMI_5V_OUT
AP2151DWG-7
1 1
SUSP#
PUM00
DESIGN CURRENT 0.5A +1.5VSP
APL5930KAI

USB_EN#0
UR1
DESIGN CURRENT 2A +USB_VCCB
SY6288D20AAC

USB_EN#2
UR3
DESIGN CURRENT 2A +USB_VCCC
SY6288D20AAC

EC_ON
PU300 DESIGN CURRENT 0.5A +3VL
SY8206BQNC Ipeak=5A, Imax=3.5A, Iocp=6A DESIGN CURRENT 5A +3VALW
SUSP#
U11
DESIGN CURRENT 6A +3VS
TPS22967DSGR
LCD_ENVDD
2 2
U1
DESIGN CURRENT 2A +LCD_VDD
SY6288C20AAC

POK
PU1100
DESIGN CURRENT 3A +1.0VALW
SY8033BDBC
SUSP
Q11
DESIGN CURRENT 2.75A +1.0VS
WOWL_EN AO4354
U8
DESIGN CURRENT 2A +3V_WLAN
TPS22967DSGR

SUSP#
PUM00
Ipeak=0.5A, Imax=0.35A, Iocp=5.7A DESIGN CURRENT 0.5A +1.5VS
APL5930KAI-TRG

POK
PU1800
Ipeak=1A, Imax=0.7A, Iocp=2.5A DESIGN CURRENT 1A +1.8VALW
SY8032ABC
3 3
SUSP#
U9
DESIGN CURRENT 0.5A +1.8VS
TPS22966DPUR
SUSP#
PUH00
Ipeak=1A, Iocp=2.5A, Imax=0.7A DESIGN CURRENT 1A +1.05VS
SY8032ABC

SYSON: Enable 1.35V


susp#: Enable 0.675VS
PUW00 DESIGN CURRENT 9A
Ipeak=9A, Imax=6.3A, Iocp=11A +1.35V
RT8207MZQW SUSP#
U9
DESIGN CURRENT 0.5A +1.35VS
TPS22966DPUR

DESIGN CURRENT 1.5A +0.675VS

VR_ON
PUZ00
4 DESIGN CURRENT 14A +SOC_VNN 4

ISL95833BHRTZ

VR_ON
PUZ00
DESIGN CURRENT 12A +SOC_VCC
ISL95833BHRTZ
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/09/25 Deciphered Date 2016/09/25 Title
Power Map
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ZBWAA LA-B303P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 3 of 41
A B C D E
A B C D E

Voltage Rails BOM Option Table


Power Plane Description S0 S3 S4/S5
Item BOM Structure
VIN 19V Adapter power supply ON ON ON
BATT+ 12V Battery power supply ON ON ON
Unpop @
B+ AC or battery power rail for power circuit. (19V/12V) ON ON ON Connector CONN@
1 XDP (Debug Port) XDP@ 1

+RTCVCC Battery Power ON ON ON EMC requirement EMC@


+1.0VALW +1.0v Always power rail ON ON ON EMC requirement unpop @EMC@
EMI requirement EMI@
+1.8VALW +1.8v Always power rail ON ON ON EMI requirement unpop @EMI@
+3VALW +3.3v Always power rail ON ON ON R short RS@
+5VALW +5.0v Always power rail ON ON ON Test Point TEST@
+1.35V +1.35V power rail for DDR3L ON ON OFF ESD requirement ESD@
+SOC_VCC Core voltage for SOC ON OFF OFF
ESD requirement unpop @ESD@
+SOC_VNN GFX voltage for SOC ON OFF OFF
FAN FAN@
+0.675VS +0.675V power rail for DDR3L Terminator ON OFF OFF HUB_24P requirement HUB_24P@
+1.0VS +1.0v system power rail ON OFF OFF HUB_28P requirement HUB_28P@
2
+1.05VS +1.05v system power rail ON OFF OFF LVDS requirement LVDS@ 2

+1.35VS +1.35v system power rail ON OFF OFF


EDP requirement IEDP@
+1.5VS +1.5v system power rail ON OFF OFF
CRT requirement CRT@
+1.8VS +1.8v system power rail ON OFF OFF Thermal sensor equirement Thermal@
+3VS +3.3v system power rail ON OFF OFF ISCT requirement ISCT@
+5VS +5.0v system power rail ON OFF OFF
NOISCT requirement NOISCT@
TPM requirement TPM@
CRT EMI requirement CRT@EMI@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Camera EMI requirement CAM_EMI@
FIX code requirement FIX@
SOC SM Bus Address EC SM Bus2 Address HDMI requirement HDMI45@
9012 requirement 9012@
3 Device HEX Address Device HEX Address 9022 requirement 9022@ 3

SO-DIMM A (JDIMM1) A0 H 1010 0000 b Thermal sensor 4D H 01001101 b TPM EMC equirement TPM@EMC@

EC SM Bus1 Address
43 level BOM table
Device HEX Address
43 Level Description BOM Structure
Smart Battery 16 H 0001 0110 b
Smart Charger 12 H 0001 0010 b
SMT MB LA-B303P ZBWAA BAY TRAIL M ESD@/EMC@/FAN@/XDP@/LVDS@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 2014/01/03 Title
Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 4 of 41
A B C D E
5 4 3 2 1

D D

UC1A UC1B
<15> DDR_A_MA[0..15] DDR_A_D[0..63] <15>
DDR_A_MA0 K45 M36 DDR_A_D0 AY45 BG38
DDR_A_MA1 H47 DRAM0_MA_0 DRAM0_DQ_0 J36 DDR_A_D1 BB47 DRAM1_MA_0 DRAM1_DQ_0 BC40
DDR_A_MA2 L41 DRAM0_MA_1 DRAM0_DQ_1 P40 DDR_A_D2 AW41 DRAM1_MA_1 DRAM1_DQ_1 BA42
DDR_A_MA3 H44 DRAM0_MA_2 DRAM0_DQ_2 M40 DDR_A_D3 BB44 DRAM1_MA_2 DRAM1_DQ_2 BD42
DDR_A_MA4 H50 DRAM0_MA_3 DRAM0_DQ_3 P36 DDR_A_D4 BB50 DRAM1_MA_3 DRAM1_DQ_3 BC38
DDR_A_MA5 G53 DRAM0_MA_4 DRAM0_DQ_4 N36 DDR_A_D5 BC53 DRAM1_MA_4 DRAM1_DQ_4 BD36
DDR_A_MA6 H49 DRAM0_MA_5 DRAM0_DQ_5 K40 DDR_A_D6 BB49 DRAM1_MA_5 DRAM1_DQ_5 BF42
DDR_A_MA7 D50 DRAM0_MA_6 DRAM0_DQ_6 K42 DDR_A_D7 BF50 DRAM1_MA_6 DRAM1_DQ_6 BC44
DDR_A_MA8 G52 DRAM0_MA_7 DRAM0_DQ_7 B32 DDR_A_D8 BC52 DRAM1_MA_7 DRAM1_DQ_7 BH32
DDR_A_MA9 E52 DRAM0_MA_8 DRAM0_DQ_8 C32 DDR_A_D9 BE52 DRAM1_MA_8 DRAM1_DQ_8 BG32
DDR_A_MA10 K48 DRAM0_MA_9 DRAM0_DQ_9 C36 DDR_A_D10 AY48 DRAM1_MA_9 DRAM1_DQ_9 BG36
DDR_A_MA11 E51 DRAM0_MA_10 DRAM0_DQ_10 A37 DDR_A_D11 BE51 DRAM1_MA_10 DRAM1_DQ_10 BJ37
DDR_A_MA12 F47 DRAM0_MA_11 DRAM0_DQ_11 C33 DDR_A_D12 BD47 DRAM1_MA_11 DRAM1_DQ_11 BG33
DDR_A_MA13 J51 DRAM0_MA_12 DRAM0_DQ_12 A33 DDR_A_D13 BA51 DRAM1_MA_12 DRAM1_DQ_12 BJ33
DDR_A_MA14 B49 DRAM0_MA_13 DRAM0_DQ_13 C37 DDR_A_D14 BH49 DRAM1_MA_13 DRAM1_DQ_13 BG37
DDR_A_MA15 B50 DRAM0_MA_14 DRAM0_DQ_14 B38 DDR_A_D15 BH50 DRAM1_MA_14 DRAM1_DQ_14 BH38
DRAM0_MA_15 DRAM0_DQ_15 F36 DDR_A_D16 DRAM1_MA_15 DRAM1_DQ_15 AU36
<15> DDR_A_DM[0..7] G36 DRAM0_DQ_16 G38 BD38 DRAM1_DQ_16 AT36
DDR_A_DM0 DDR_A_D17
DDR_A_DM1 B36 DRAM0_DM_0 DRAM0_DQ_17 F42 DDR_A_D18 BH36 DRAM1_DM_0 DRAM1_DQ_17 AV40
DDR_A_DM2 F38 DRAM0_DM_1 DRAM0_DQ_18 J42 DDR_A_D19 BC36 DRAM1_DM_1 DRAM1_DQ_18 AT40
DDR_A_DM3 B42 DRAM0_DM_2 DRAM0_DQ_19 G40 DDR_A_D20 BH42 DRAM1_DM_2 DRAM1_DQ_19 BA36
DDR_A_DM4 P51 DRAM0_DM_3 DRAM0_DQ_20 C38 DDR_A_D21 AT51 DRAM1_DM_3 DRAM1_DQ_20 AV36
DDR_A_DM5 V42 DRAM0_DM_4 DRAM0_DQ_21 G44 DDR_A_D22 AM42 DRAM1_DM_4 DRAM1_DQ_21 AY42
DDR_A_DM6 Y50 DRAM0_DM_5 DRAM0_DQ_22 D42 DDR_A_D23 AK50 DRAM1_DM_5 DRAM1_DQ_22 AY40
DDR_A_DM7 Y52 DRAM0_DM_6 DRAM0_DQ_23 A41 DDR_A_D24 AK52 DRAM1_DM_6 DRAM1_DQ_23 BJ41
DRAM0_DM_7 DRAM0_DQ_24 C41 DDR_A_D25 DRAM1_DM_7 DRAM1_DQ_24 BG41
M45 DRAM0_DQ_25 A45 DDR_A_D26 AV45 DRAM1_DQ_25 BJ45
<15> DDR_A_RAS# M44 DRAM0_RAS# DRAM0_DQ_26 B46 AV44 DRAM1_RAS# DRAM1_DQ_26 BH46
DDR_A_D27
<15> DDR_A_CAS# DRAM0_CAS# DRAM0_DQ_27 DRAM1_CAS# DRAM1_DQ_27
H51 C40 DDR_A_D28 BB51 BG40
<15> DDR_A_WE# DRAM0_WE# DRAM0_DQ_28 B40 DRAM1_WE# DRAM1_DQ_28 BH40
DDR_A_D29
K47 DRAM0_DQ_29 B48 DDR_A_D30 AY47 DRAM1_DQ_29 BH48
<15> DDR_A_BS0 DRAM0_BS_0 DRAM0_DQ_30 DRAM1_BS_0 DRAM1_DQ_30
K44 B47 DDR_A_D31 AY44 BH47
<15> DDR_A_BS1 D52 DRAM0_BS_1 DRAM0_DQ_31 K52 BF52 DRAM1_BS_1 DRAM1_DQ_31 AY52
DDR_A_D32
<15> DDR_A_BS2 DRAM0_BS_2 DRAM0_DQ_32 DRAM1_BS_2 DRAM1_DQ_32
C K51 DDR_A_D33 AY51 C
P44 DRAM0_DQ_33 T52 DDR_A_D34 AT44 DRAM1_DQ_33 AP52
<15> DDR_A_CS0# DRAM0_CS_0# DRAM0_DQ_34 DRAM1_CS_0# DRAM1_DQ_34
T51 DDR_A_D35 AP51
P45 DRAM0_DQ_35 L51 DDR_A_D36 AT45 DRAM1_DQ_35 AW51
<15> DDR_A_CS2# DRAM0_CS_2# DRAM0_DQ_36 L53 DRAM1_CS_2# DRAM1_DQ_36 AW53
DDR_A_D37
DRAM0_DQ_37 R51 DDR_A_D38 DRAM1_DQ_37 AR51
C47 DRAM0_DQ_38 R53 DDR_A_D39 BG47 DRAM1_DQ_38 AR53
<15> DDR_A_CKE0 DRAM0_CKE_0 DRAM0_DQ_39 DRAM1_CKE_0 DRAM1_DQ_39
D48 T47 DDR_A_D40 BE46 AP47
F44 RESERVED_D48 DRAM0_DQ_40 T45 DDR_A_D41 BD44 RESERVED_BE46 DRAM1_DQ_40 AP45
<15> DDR_A_CKE2 E46 DRAM0_CKE_2 DRAM0_DQ_41 Y40 BF48 DRAM1_CKE_2 DRAM1_DQ_41 AK40
DDR_A_D42
RESERVED_E46 DRAM0_DQ_42 V41 DDR_A_D43 RESERVED_BF48 DRAM1_DQ_42 AM41
T41 DRAM0_DQ_43 T48 DDR_A_D44 AP41 DRAM1_DQ_43 AP48
<15> DDR_A_ODT0 DRAM0_ODT_0 DRAM0_DQ_44 DRAM1_ODT_0 DRAM1_DQ_44
T50 DDR_A_D45 AP50
P42 DRAM0_DQ_45 Y42 DDR_A_D46 AT42 DRAM1_DQ_45 AK42
<15> DDR_A_ODT2 DRAM0_ODT_2 DRAM0_DQ_46 AB40 DRAM1_ODT_2 DRAM1_DQ_46 AH40
DDR_A_D47
DRAM0_DQ_47 V45 DDR_A_D48 DRAM1_DQ_47 AM45
M50 DRAM0_DQ_48 V47 DDR_A_D49 AV50 DRAM1_DQ_48 AM47
<15> DDR_A_CLK0 DRAM0_CKP_0 DRAM0_DQ_49 DRAM1_CKP_0 DRAM1_DQ_49
M48 AD48 DDR_A_D50 AV48 AF48
<15> DDR_A_CLK0# DRAM0_CKN_0 DRAM0_DQ_50 DRAM1_CKN_0 DRAM1_DQ_50
AD50 DDR_A_D51 AF50
DRAM0_DQ_51 V48 DDR_A_D52 DRAM1_DQ_51 AM48
P50 DRAM0_DQ_52 V50 DDR_A_D53 DRAM1_DQ_52 AM50
<15> DDR_A_CLK2 P48 DRAM0_CKP_2 DRAM0_DQ_53 AB44 AT50 DRAM1_DQ_53 AH44
DDR_A_D54
<15> DDR_A_CLK2# DRAM0_CKN_2 DRAM0_DQ_54 DRAM1_CKP_2 DRAM1_DQ_54
Y45 DDR_A_D55 AT48 AK45
DRAM0_DQ_55 V52 DDR_A_D56 DRAM1_CKN_2 DRAM1_DQ_55 AM52
DRAM0_DQ_56 W51 DDR_A_D57 DRAM1_DQ_56 AL51
P41 DRAM0_DQ_57 AC53 DDR_A_D58 DRAM1_DQ_57 AG53
<15> DDR_A_RST# DRAM0_DRAMRST# DRAM0_DQ_58 AC51 AT41 DRAM1_DQ_58 AG51
DDR_A_D59
DRAM0_DQ_59 W53 DDR_A_D60 DRAM1_DRAMRST# DRAM1_DQ_59 AL53
DRAM0_DQ_60 Y51 DDR_A_D61 DRAM1_DQ_60 AK51
DRAM0_DQ_61 DRAM1_DQ_61
+DDR_SOC_VREF
AF44
DRAM_VREF 0.675V DRAM0_DQ_62
AD52 DDR_A_D62
DRAM1_DQ_62
AF52
AD51 DDR_A_D63 AF51
DRAM0_DQ_63 DRAM1_DQ_63
100K_0402_5% 1 2 RC1 DDR_TERMN0 AF42 J38 DDR_A_DQS0 BF40
100K_0402_5% 1 2 RC2 DDR_TERMN1 AH42 ICLK_DRAM_TERMN_AF42 DRAM0_DQSP_0 K38 DDR_A_DQS#0 DRAM1_DQSP_0 BD40
ICLK_DRAM_TERMN_AH42 DRAM0_DQSN_0 C35 DDR_A_DQS1 DRAM1_DQSN_0 BG35
DRAM0_DQSP_1 B34 DDR_A_DQS#1 DRAM1_DQSP_1 BH34
DRAM0_DQSN_1 D40 DDR_A_DQS2 DRAM1_DQSN_1 BA38
AD42 DRAM0_DQSP_2 F40 DDR_A_DQS#2 DRAM1_DQSP_2 AY38
B <32> DDR_PWROK DRAM_VDD_S4_PWROK DRAM0_DQSN_2 DRAM1_DQSN_2 B
AB42 B44 DDR_A_DQS3 BH44
<8> DDR_CORE_PWROK DRAM_CORE_PWROK DRAM0_DQSP_3 C43 DRAM1_DQSP_3 BG43
DDR_A_DQS#3
DRAM0_DQSN_3 N53 DDR_A_DQS4 DRAM1_DQSN_3 AU53
23.2_0402_1% 1 2 RC3 DDR_RCOMP0 AD44 DRAM0_DQSP_4 M52 DDR_A_DQS#4 DRAM1_DQSP_4 AV52
29.4_0402_1% 1 2 RC4 DDR_RCOMP1 AF45 DRAM_RCOMP_0 DRAM0_DQSN_4 T42 DDR_A_DQS5 DRAM1_DQSN_4 AP42
162_0402_1% 1 2 RC5 DDR_RCOMP2 AD45 DRAM_RCOMP_1 DRAM0_DQSP_5 T44 DDR_A_DQS#5 DRAM1_DQSP_5 AP44
DRAM_RCOMP_2 DRAM0_DQSN_5 Y47 DDR_A_DQS6 DRAM1_DQSN_5 AK47
DRAM0_DQSP_6 Y48 DDR_A_DQS#6 DRAM1_DQSP_6 AK48
Follow CRB v1.15
AF40 DRAM0_DQSN_6 AB52 DDR_A_DQS7 DRAM1_DQSN_6 AH52
AF41 RESERVED_AF40 DRAM0_DQSP_7 AA51 DDR_A_DQS#7 DRAM1_DQSP_7 AJ51
AD40 RESERVED_AF41 DRAM0_DQSN_7 DRAM1_DQSN_7
AD41 RESERVED_AD40
RESERVED_AD41 DDR_A_DQS[0..7] <15>
1 OF 13 2 OF 13
DDR_A_DQS#[0..7] <15>
VALLEYVIEW-M_FCBGA1170 VALLEYVIEW-M_FCBGA1170

Close To SOC Pin

+1.35V +DDR_SOC_VREF

1 2
RC6 1
4.7K_0402_1%
CC1
1 2 .1U_0402_16V7K
RC7 2
4.7K_0402_1%
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 Deciphered Date 2014/01/03 Title
VLV-M SOC Memory DDR3L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 5 of 41
5 4 3 2 1
5 4 3 2 1

RPC43
150_0804_8P4R_1%
UMA_CRT_B 8 1
UC1C UMA_CRT_R 7 2
UMA_CRT_G 6 3
AV3 AG3 5 4
<18> H_HDMI_TX2+ DDI0_TXP_0 DDI1_TXP_0 H_EDP_TXP0 <16>
<18> H_HDMI_TX2-
AV2
DDI0_TXN_0 1.0V 1.0V DDI1_TXN_0
AG1
H_EDP_TXN0 <16>
AT2 AF3 CRT@
<18> H_HDMI_TX1+ DDI0_TXP_1 DDI1_TXP_1 H_EDP_TXP1 <16>
AT3 AF2
<18> H_HDMI_TX1- DDI0_TXN_1 DDI1_TXN_1 H_EDP_TXN1 <16>
AR3 AD3 IEDP@
<18> H_HDMI_TX0+ DDI0_TXP_2 DDI1_TXP_2
AR1 AD2 EC_ENBKL_R 1 2
D <18> H_HDMI_TX0- DDI0_TXN_2 DDI1_TXN_2 EC_ENBKL <16,25> D
AP3 AC3 RC8 0_0402_5%
<18> H_HDMI_TXC+
AP2 DDI0_TXP_3 DDI1_TXP_3 AC1 eDP
HDMI <18> H_HDMI_TXC- DDI0_TXN_3 DDI1_TXN_3
AL3
DDI0_AUXP 1.0V DDI1_AUXP
AK3 H_EDP_AUXP <16>
+1.8VS
AL1
DDI0_AUXN 1.0V DDI1_AUXN
AK2 H_EDP_AUXN <16>

5
<18,7> HDMI_HPD#
D27
DDI0_HPD 1.8V 1.8V DDI1_HPD
K30
H_EDP_HPD# <17>
UC2
1

P
NC
<18> UMA_HDMI_DATA
C26
DDI0_DDCDATA 1.8V 1.8V DDI1_DDCDATA
P30 DDI1_ENABLE RC9 1 2 2.2K_0402_5% +1.8VS Y
4
EC_ENBKL_R <17>
C28 1.8V 1.8V G30 DDI1_ENBKL 2

G
<18> UMA_HDMI_CLK DDI0_DDCCLK DDI1_DDCCLK A
B28 1.8V N30 DDI1_ENVDD NL17SZ07DFT2G_SC70-5

3
DDI0_VDDEN DDI1_VDDEN
C27
DDI0_BKLTEN 1.8V DDI1_BKLTEN
J30 DDI1_ENBKL SA00004BV00
B26
DDI0_BKLTCTL 1.8V DDI1_BKLTCTL
M30 DDI1_PWM

AH3 1 @ 2
1 RC10 2 DDI0_RCOMPP AK12 VSS_AH3 AH2 RC35 0_0402_5%
DDI0_RCOMP_P VSS_AH2
Follow CRB v1.15 0ohm till to GND
402_0402_1% DDI0_RCOMPN AK13
AM14 DDI0_RCOMP_N AH14
AM13 RESERVED_AM14 RESERVED_AH14 AH13
AM3 RESERVED_AM13 RESERVED_AH13 AF14 +1.8VS
AM2 VSS_AM3 RESERVED_AF14 AF13
Follow CRB v1.15 0ohm till to GND VSS_AM2 RESERVED_AF13

5
BA3 UMA_CRT_R IEDP@ UC3
C VGA_RED UMA_CRT_R <19> C
AY2 UMA_CRT_B 1

P
VGA_BLUE UMA_CRT_B <19> NC
BA1 UMA_CRT_G 4LCD_ENVDD
VGA_GREEN UMA_CRT_G <19> Y LCD_ENVDD <17>
AW1 R1 1 2 357_0402_1% DDI1_ENVDD 2

G
VGA_IREF AY3 A
VGA_IRTN CRT NL17SZ07DFT2G_SC70-5

3
3.3V VGA_HSYNC
BD2
UMA_CRT_HSYNC <19>
SA00004BV00
3.3V VGA_VSYNC
BF2
UMA_CRT_VSYNC <19>

3.3V VGA_DDCCLK
BC1 UMA_CRT_CLK <19>
3.3V VGA_DDCDATA
BC2 UMA_CRT_DATA <19>
+1.8VS

T2 T7 IEDP@

5
T3 RESERVED_T2 RESERVED_T7 T9 UC4
AB3 RESERVED_T3 RESERVED_T9 AB13 1

P
AB2 RESERVED_AB3 RESERVED_AB13 AB12 NC 4 SOC_PWM_EDP
RESERVED_AB2 RESERVED_AB12 Y SOC_PWM_EDP <17>
Y3 Y12 DDI1_PWM 2

G
Y2 RESERVED_Y3 RESERVED_Y12 Y13 A
W3 RESERVED_Y2 RESERVED_Y13 V10 NL17SZ07DFT2G_SC70-5

3
W1 RESERVED_W3 RESERVED_V10 V9 SA00004BV00
V2 RESERVED_W1 RESERVED_V9 T12
V3 RESERVED_V2 RESERVED_T12 T10 +3VS
R3 RESERVED_V3 RESERVED_T10 V14
R1 RESERVED_R3 RESERVED_V14 V13
+1.8VS AD6 RESERVED_R1 RESERVED_V13 T14 LCD_ENVDD 1 IEDP@ 2
B B
AD4 RESERVED_AD6 RESERVED_T14 T13 RC83 4.7K_0402_5%
AB9 RESERVED_AD4 RESERVED_T13 T6 SOC_PWM_EDP 1 IEDP@ 2
1

AB7 RESERVED_AB9 RESERVED_T6 T4 RC82 4.7K_0402_5%


@ Y4 RESERVED_AB7 RESERVED_T4 P14 EC_ENBKL_R 1 2
RC12 Y6 RESERVED_Y4 RESERVED_P14 RC81 4.7K_0402_5%
10K_0402_5% V4 RESERVED_Y6 F34
V6 RESERVED_V4 GPIO_S0_NC_15 M32
2

GPIO_NC13 A29 RESERVED_V6 GPIO_S0_NC_16 D28


GPIO_NC14 C29 GPIO_S0_NC_13 GPIO_S0_NC_17 J28 RPC2
1

T1 GPIO_S0_NC14 GPIO_S0_NC_18
AB14 K34 DDI1_ENBKL 8 1
GPIO_NC12 B30 RESERVED_AB14 GPIO_S0_NC_19 D34 DDI1_ENVDD 7 2 0504
T2 GPIO_S0_NC_12 GPIO_S0_NC_20
RC13 C30 F32 DDI1_PWM 6 3
10K_0402_5% RESERVED_C30 GPIO_S0_NC_21 F28 5 4
GPIO_S0_NC_22 K28
2

GPIO_S0_NC_23 J34 100K_0804_8P4R_5%


GPIO_S0_NC_24 N32
GPIO_S0_NC_25 D32
Follow CRB v1.15 3 OF 10 GPIO_S0_NC_26

VALLEYVIEW-M_FCBGA1170
DDI1_PWM 1 RS@ 2
SOC_PWM_TL <16>
GPIO_S0_NC[13]: RC14 0_0402_5%
Multiplexed with Hardware Straps Pin:MDSI_DDCDATA
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 2014/01/03 Title
Deciphered Date VLV-M SOC Display
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 6 of 41
5 4 3 2 1
5 4 3 2 1

UC1D

BF6 AY7 PCIE_PTX_LANRX_P0 .1U_0402_16V7K 1 2 CC2


<20> SATA_PTX_DRX_P0 BG7 SATA_TXP_0 PCIE_TXP_0 AY6 PCIE_PTX_LANRX_N0 PCIE_PTX_C_LANRX_P0 <22>
.1U_0402_16V7K 1 2 CC3
<20> SATA_PTX_DRX_N0 SATA_TXN_0 PCIE_TXN_0 PCIE_PTX_C_LANRX_N0 <22>
HDD LAN
AU16 AT14 PCIE_PRX_C_LANTX_P0
D <20> SATA_PRX_C_DTX_P0 SATA_RXP_0 PCIE_RXP_0 PCIE_PRX_C_LANTX_P0 <22> D
AV16 AT13 PCIE_PRX_C_LANTX_N0
<20> SATA_PRX_C_DTX_N0 SATA_RXN_0 PCIE_RXN_0 PCIE_PRX_C_LANTX_N0 <22>
BD10 AV6 PCIE_PTX_WLANRX_P1 .1U_0402_16V7K 1 2 CC4
<20> SATA_PTX_DRX_P1 SATA_TXP_1 PCIE_TXP_1 PCIE_PTX_C_WLANRX_P1 <21>
BF10 AV4 PCIE_PTX_WLANRX_N1 .1U_0402_16V7K 1 2 CC5 WLAN
<20> SATA_PTX_DRX_N1 SATA_TXN_1 PCIE_TXN_1 PCIE_PTX_C_WLANRX_N1 <21>
ODD
AY16 AT10 PCIE_PRX_WLANTX_P1
<20> SATA_PRX_C_DTX_P1 BA16 SATA_RXP_1 PCIE_RXP_1 AT9 PCIE_PRX_WLANTX_N1 PCIE_PRX_WLANTX_P1 <21>
<20> SATA_PRX_C_DTX_N1 SATA_RXN_1 PCIE_RXN_1 PCIE_PRX_WLANTX_N1 <21>
BB10 AT7 PCIE_PTX_CRRX_P2 .1U_0402_16V7K 1 2 CC6
BC10 VSS_BB10 PCIE_TXP_2 AT6 PCIE_PTX_CRRX_N2 PCIE_PTX_C_CRRX_P2 <26>
Follow CRB V1.15 0ohm till to GND .1U_0402_16V7K 1 2 CC7
VSS_BC10 PCIE_TXN_2 PCIE_PTX_C_CRRX_N2 <26>
Card Reader
SOC_SCI# BA12 AP12 PCIE_PRX_C_CRTX_P2
<10> SOC_SCI# AY14 SATA_GP0 / GPIO_S0_SC_0 PCIE_RXP_2 AP10 PCIE_PRX_C_CRTX_N2 PCIE_PRX_C_CRTX_P2 <26>
DEVSLP_SOC
T3 SATA_GP1 / SATA_DEVSLP_0 / GPIO_S0_SC_1 PCIE_RXN_2 PCIE_PRX_C_CRTX_N2 <26>
+1.8VS 1 2 SATA_LED#_SOC AY12
RC15 10K_0402_5% SATA_LED# / GPIO_S0_SC_2 AP6
1 RC16 2 SATA_RCOMPP AU18 PCIE_TXP_3 AP4
402_0402_1% SATA_RCOMPN AT18 SATA_RCOMP_P PCIE_TXN_3
SATA_RCOMP_N AP9
PCIE_RXP_3 AP7 +1.8VS
AT22 PCIE_RXN_3 RPC3
MMC1_CLK / GPIO_S0_SC_16 BB7 PCIE_CLKREQ_3# 1 8
AV20 VSS_BB7 BB5 CLKREQ_LAN# 2 7
MMC1_D0 / GPIO_S0_SC_17 VSS_BB5
Follow CRB V1.15 0ohm till to GND
AU22 WLAN_CLKREQ# 3 6
AV22 MMC1_D1 / GPIO_S0_SC_18 BG3 CLKREQ_LAN# CLKREQ_CR# 4 5
C MMC1_D2 / GPIO_S0_SC_19 PCIE_CLKREQ_0# / GPIO_S0_SC_3 CLKREQ_LAN# <22> C
AT20 BD7 WLAN_CLKREQ#
MMC1_D3 / GPIO_S0_SC_20 PCIE_CLKREQ_1# / GPIO_S0_SC_4 WLAN_CLKREQ# <21>
AY24 BG5 CLKREQ_CR# 10K_0804_8P4R_5%
AU26 MMC1_D4 / GPIO_S0_SC_21 PCIE_CLKREQ_2# / GPIO_S0_SC_5 BE3 CLKREQ_CR# <26>
PCIE_CLKREQ_3#
AT26 MMC1_D5 / GPIO_S0_SC_22 PCIE_CLKREQ_3# / GPIO_S0_SC_6 BD5 RPC4
MMC1_D6 / GPIO_S0_SC_23 SD3_WP / GPIO_S0_SC_7 HDMI_HPD# <18,6>
AU20 HDA_SDOUT 8 1 AZ_SDOUT_HD <24>
MMC1_D7 / GPIO_S0_SC_24 AP14 PCIE_RCOMPP 1 RC17 2 HDA_SYNC 7 2
PCIE_RCOMP_P AZ_SYNC_HD <24>
AV26 AP13 PCIE_RCOMPN 402_0402_1% HDA_BIT_CLK 6 3 AZ_BITCLK_HD <24>
BA24 MMC1_CMD / GPIO_S0_SC_25 PCIE_RCOMP_N HDA_RST# 5 4
MMC1_RST# / SATA_DEVSLP_0 / GPIO_S0_SC_26 AZ_RST_HD# <24>
BB4
AY18 RESERVED_BB4 BB3 33_0804_8P4R_5%
MMC1_RCOMP RESERVED_BB3 EMC@
AV10
BA18 RESERVED_AV10 AV9
AY20 SD2_CLK / GPIO_S0_SC_27 RESERVED_AV9
BD20 SD2_D0 / GPIO_S0_SC_28 BF20 HDA_RCOMP 49.9_0402_1% 1 2 RC18
BA20 SD2_D1 / GPIO_S0_SC_29 HDA_LPE_RCOMP BG22 CC8
HDA_RST# For EMI
BD18 SD2_D2 / GPIO_S0_SC_30 HDA_RST# / LPE_I2S0_CLK / GPIO_S0_SC_8 BH20 HDA_SYNC AZ_BITCLK_HD1 2
BC18 SD2_D3_CD# / GPIO_S0_SC_31 HDA_SYNC / LPE_I2S0_FRM / GPIO_S0_SC_9 BJ21 HDA_BIT_CLK
SD2_CMD / GPIO_S0_SC_32 HDA_CLK / LPE_I2S0_DATAOUT / GPIO_S0_SC_10 BG20 HDA_SDOUT
HDA_SDO / LPE_I2S0_DATAIN / GPIO_S0_SC_11 BG19 22P_0402_50V8J
HDA_SDI0 / LPE_I2S1_CLK / GPIO_S0_SC_12 BG21 AZ_SDIN0_HD <24> @EMC@
HDA_SDI1 / LPE_I2S1_FRM / GPIO_S0_SC_13 T4
AY26 BH18
AT28 SD3_CLK / GPIO_S0_SC_33 HDA_DOCKRST# / LPE_I2S1_DATAOUT / GPIO_S0_SC_14 BG18 T5
BD26 SD3_D0 / GPIO_S0_SC_34 HDA_DOCKEN# / LPE_I2S1_DATAIN / GPIO_S0_SC_15 T6
B GPIO_S0_SC_63: GPIO_S0_SC_65: B
AU28 SD3_D1 / GPIO_S0_SC_35 BF28
SD3_D2 / GPIO_S0_SC_36 LPE_I2S2_CLK / SATA_DEVSLP_1 / GPIO_S0_SC_62 BIOS/EFI Boot Strap (BBS) Security Flash Descriptors
BA26 BA30 GPIO_S0_SC_63 BIOS Boot Selection 0 = Override
BC24 SD3_D3 / GPIO_S0_SC_37 LPE_I2S2_FRM / GPIO_S0_SC_63 BD28
AV28 SD3_CD# / GPIO_S0_SC_38 LPE_I2S2_DATAIN / GPIO_S0_SC_64 BC30 GPIO_S0_SC_65
0 = LPC 1 = Normal Operation
BF22 SD3_CMD / GPIO_S0_SC_39 LPE_I2S2_DATAOUT / GPIO_S0_SC_65 1 = SPI (Internal PU)
BD22 SD3_1P8EN / GPIO_S0_SC_40 P34 +1.8VS +1.8VS
SD3_PWREN# / GPIO_S0_SC_41 RESERVED_P34 N34 RC19
BF26 RESERVED_N34 73.2_0402_1%

1
SD3_RCOMP AK9 1 2
RESERVED_AK9 +1.0VS
AK7
RESERVED_AK7 RC20 RC21
C24 10K_0402_5% 10K_0402_5%
PROCHOT# H_PROCHOT# <25>
4 OF 10 Internal PD 2K EC programing :

2
2 GPIO_S0_SC_63 GPIO_S0_SC_65 "High"for Flash BIOS
VALLEYVIEW-M_FCBGA1170 ESD@

1
CC9 D
10P_0402_50V8J 2 QC1
1 <25> TXE_DBG G MESS138W-G_SOT323-3
S

3
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 2014/01/03 Title
Deciphered Date VLV-M SOC SATA/PCI-E/HDA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 7 of 41
5 4 3 2 1
5 4 3 2 1

Place near to YC2


Place near to YC1 0722 update
ILB_RTC_X1
XTAL_25M_IN ILB_RTC_X2 +1.8VS +3VALW +1.35VS
1 2

1
RC33 10M_0402_5%

1
RC22
YC1 1M_0402_5% RC32
YC2
25MHZ_10PF_7V25000014 10K_0402_5%

5
1 2 UC5 UC7

2
1 3 XTAL_25M_OUT 1 1

P
1.8V 3.3V VRTC 1.35V

2
1 3 NC 4 PLT_RST_BUF# NC 4
1 GND GND 1 1 1
32.768KHZ_12.5P_1TJF125DP1A000D Y PLT_RST_BUF# <21,22,25,26,9> Y DDR_CORE_PWROK <5>
CC10 CC11 CC16 PMC_PLTRST# 2 PMC_CORE_PWROK 2

G
12P_0402_50V8J 12P_0402_50V8J 15P_0402_50V8J CC17 A A
2 4 2
15P_0402_50V8J NL17SZ07DFT2G_SC70-5 NL17SZ07DFT2G_SC70-5

3
D 2 2 2 2 D
SA00004BV00 SA00004BV00 CC21
.1U_0402_16V7K
1
@ESD@
PLT_RST Buffer
UC1E

XTAL_25M_IN AH12 AU34 +1.8VALW


ICLK_OSCIN SIO_UART1_RXD / GPIO_S0_SC_70 DC4
XTAL_25M_OUT AH10 AV34 RPC5
ICLK_OSCOUT SIO_UART1_TXD / GPIO_S0_SC_71 BA34 1 2PMC_PCIE_WAKE# 1 8
SIO_UART1_RTS# / GPIO_S0_SC_72 <22,25> EC_SWI#
AD9 AY34 PMC_BATLOW# 2 7
RESERVED_AD9 SIO_UART1_CTS# / GPIO_S0_SC_73 GPIO_S5_14 3 6
RC25 1 2 4.02K_0402_1% ICLK_ICOMP AD14 BF34 RB751V40_SC76-2 4 5
RC26 1 2 47.5_0402_1% ICLK_RCOMP AD13 ICLK_ICOMP SIO_UART2_RXD / GPIO_S0_SC_74 BD34
ICLK_RCOMP SIO_UART2_TXD / GPIO_S0_SC_75 BD32 10K_0804_8P4R_5%
AD10 SIO_UART2_RTS# / GPIO_S0_SC_76 BF32
AD12 RESERVED_AD10 SIO_UART2_CTS# / GPIO_S0_SC_77
RESERVED_AD12
LAN AF6
<22> CLK_LAN# AF4 PCIE_CLKN_0 D26 FOR EMI/ESD Require 01/15
<22> CLK_LAN PCIE_CLKP_0 PMC_SUSPWRDNACK / GPIO_S5_11 G24
AF9 PMC_SUSCLK_0 / GPIO_S5_12 F18
<21> CLK_WLAN# PCIE_CLKN_1 PMC_SLP_S0IX# / GPIO_S5_13
WLAN AF7 F22 PMC_SLP_S4#
<21> CLK_WLAN PCIE_CLKP_1 PMC_SLP_S4# PMC_SLP_S4# <10>
D22 PMC_SLP_S3#
PMC_SLP_S3# J20 PMC_SLP_S3# <10> 1 2
GPIO_S5_14 RPH6 PMC_PLTRST#
AK4 GPIO_S5_14 D20 PMC_ACIN SPI_MOSI 1 8 SOC_SPI_MOSI CC13 ESD@
<26> CLK_CR# AK6 PCIE_CLKN_2 PMC_ACPRESENT F26 2 7
Card Reader PMC_PCIE_WAKE# SPI_CLK SOC_SPI_CLK 0.01U_0402_16V7K
<26> CLK_CR PCIE_CLKP_2 PMC_WAKE_PCIE_0# / GPIO_S5_15 K26 PMC_BATLOW# SPI_MISO 3 6 SOC_SPI_MISO
AM4 PMC_BATLOW# J26 PMC_PWRBTN# SPI_CS0# 4 5 SOC_SPI_CS0# PLT_RST_BUF# 1 2
AM6 PCIE_CLKN_3 PMC_PWRBTN# / GPIO_S5_16 BG9 PMC_PWRBTN# <10>
PMC_RSTBTN# CC19 ESD@
PCIE_CLKP_3 PMC_RSTBTN# F20 PMC_PLTRST# T18 22_0804_8P4R_5% .1U_0402_16V7K
AM9 PMC_PLTRST# J24 GPIO_S5_17
AM10 RESERVED_AM9 GPIO_S5_17 G18 T7
RESERVED_AM10 PMC_SUS_STAT# / GPIO_S5_18
EC_RSMRST# 1 2
C RC27 100K_0402_5% C
C11 RTC_TEST# RPH9
BH7 ILB_RTC_TEST# C12 RTC_RST# SPI_CS0# 1 8
PMC_PLT_CLK_0 / GPIO_S0_SC_96 ILB_RTC_RST# EC_CS0# <25>
BH5 SPI_MISO 2 7 PMC_CORE_PWROK 1 2
BH4 PMC_PLT_CLK_1 / GPIO_S0_SC_97 3 6 EC_SDIO <25>
SPI_CLK CC14 ESD@
PMC_PLT_CLK_2 / GPIO_S0_SC_98 EC_SCK <25>
BH8 B10 EC_RSMRST# SPI_MOSI 4 5 .1U_0402_16V7K
BH6 PMC_PLT_CLK_3 / GPIO_S0_SC_99 PMC_RSMRST# B7 EC_RSMRST# <25> EC_SDI <25>
PMC_CORE_PWROK
PMC_PLT_CLK_4 / GPIO_S0_SC_100 PMC_CORE_PWROK PMC_CORE_PWROK <25>
BJ9 22_0804_8P4R_5% PMC_CORE_PWROK 1 2
PMC_PLT_CLK_5 / GPIO_S0_SC_101 +1.0VS FIX@ RC40
RTC domain
C9 ILB_RTC_X1 100K_0402_5%
XDP_H_TCK D14 ILB_RTC_X1 A9 ILB_RTC_X2

1
XDP_H_TRST# G12 TAP_TCK ILB_RTC_X2 B8 ILB_RTC_EXTPAD 1 2
XDP_H_TMS F14 TAP_TRST# ILB_RTC_EXTPAD P22 CC15 RC28
TAP_TMS RTC_VCC_P22 +RTCVCC
XDP_H_TDI F12 .1U_0402_16V7K 73.2_0402_1%
XDP_H_TDO G16 TAP_TDI
XDP_H_PRDY# D18 TAP_TDO +1.8VS

2
XDP_H_PREQ_BUF# F16 TAP_PRDY# B24 VR_SVID_ALERT#_SOC RC29 1 2 20_0402_1%
TAP_PREQ# SVID_ALERT# VR_SVID_ALERT# <35>
AT34 A25 VR_SVID_DATA_SOC RC30 1 2 16.9_0402_1%
RESERVED_AT34 SVID_DATA VR_SVID_DATA <35>
C25
C23 SVID_CLK VR_SVID_CLK <35>
SOC_SPI_CS0# Close To SOC <1000mil @
T8 C21 PCU_SPI_CS_0# +1.8VALW TOUCH_DETECT# 1 2
SOC_SPI_MISO B22 PCU_SPI_CS_1# / GPIO_S5_21 AU32 RC41 2.2K_0402_5%
SOC_SPI_MOSI A21 PCU_SPI_MISO SIO_PWM_0 / GPIO_S0_SC_94 AT32 RC39 1 2 51_0402_5% XDP_H_TDO
PCU_SPI_MOSI SIO_PWM_1 / GPIO_S0_SC_95 TP_INTR# <26>
SOC_SPI_CLK C22 RC38 1 2 200_0402_5% XDP_H_PREQ_BUF# @
PCU_SPI_CLK 1 2 RC23 1 2 51_0402_5% XDP_H_PRDY# TOUCH_DETECT# 1 2
+1.8VS
RC31 10K_0402_5% RC65 10K_0402_5%
SOC_KBRST# B18 RP1
<10> SOC_KBRST# GPIO_S5_0
B16 K24 1 8 XDP_H_TCK
C18 GPIO_S5_1 / PMC_WAKE_PCIE_1 GPIO_S5_22 N24 2 7 XDP_H_TMS
A17 GPIO_S5_2 / PMC_WAKE_PCIE_2 GPIO_S5_23 M20 3 6 XDP_H_TDI
SOC_LID_OUT# C17 GPIO_S5_3 / PMC_WAKE_PCIE_3 GPIO_S5_24 J18 4 5 XDP_H_TRST#
<10> SOC_LID_OUT# C16 GPIO_S5_4 GPIO_S5_25 M18
B14 GPIO_S5_5 / PMU_SUSCLK_1 GPIO_S5_26 K18 51_0804_8P4R_5%
SOC_SMI# C15 GPIO_S5_6 / PMU_SUSCLK_2 GPIO_S5_27 K20
<10> SOC_SMI# GPIO_S5_7 / PMU_SUSCLK_3 GPIO_S5_28 M22 +1.8VALW
GPIO_S5_29 M24
GPIO_S5_30

1
C13
B GPIO_S5_8 B
A13
C19 GPIO_S5_9 AV32 RC24
GPIO_S5_10 SIO_SPI_CS# / GPIO_S0_SC_66 BA28 2.2K_0402_5%
SIO_SPI_MISO / GPIO_S0_SC_67 AY28

2
1 RC34 2 GPIO_RCOMP N26 SIO_SPI_MOSI / GPIO_S0_SC_68 AY30 TOUCH_DETECT# DC1
GPIO_RCOMP SIO_SPI_CLK / GPIO_S0_SC_69 TOUCH_DETECT# <17>
49.9_0402_1% 5 OF 13 PMC_ACIN 2 1
ACIN <25,30>
VALLEYVIEW-M_FCBGA1170 RB751V40_SC76-2

RTC schematic for non-chargeable


ESD@
1 2 PLT_RST_BUF#
CC82 0.1U_0402_10V7K
+BIOS_SPI +1.8VALW
1
+RTCVCC 1 2
+3VL +RTCBATT
RH35 1 RS@ 2 0_0402_5% CC18 +RTCVCC D16 RB751V40_SC76-2
+BIOS_SPI RC36 1U_0402_6.3V6K
CH19 1 2 .1U_0402_16V7K 20K_0402_1% 2
1 2 RTC_TEST# 1 2 1 1 2 +RTCBATT_R 2 1
1 2 RTC_TEST_R# <25>
UH3 RTC_RST# R31 0_0402_5% D17 RB751V40_SC76-2 R2 1K_0402_5%
RH38 1 2 3.3K_0402_5% SPI_CS0# 1 8 RH39 1 2 3.3K_0402_5% RC37 C1 @ @

1
SPI_MISO 2 CS# VCC 7 SPI_HOLD# 20K_0402_1% 0.1U_0402_16V4Z
DO(IO1) HOLD#(IO3) 1 2
RH40 1 2 3.3K_0402_5% 3 6

+
SPI_WP# SPI_CLK
4 WP#(IO2) CLK 5 SPI_MOSI CC20
GND DI(IO0) 1U_0402_6.3V6K +RTC_R
W25Q64DWSSIG_SO8 2 CLR_CMOS 1 RS@ 2 RTC_TEST# JRTC
R3 0_0402_5%
1 @ 2 RTC_RST# SUYIN_060003HA002G202ZL
1

JP@ R4 0_0402_5% 2 1
JCMOS R9 1K_0402_5% CONN@
SHORT PADS
2

Clear CMOS

-
Close to RAM door

2
A 0812 -> Add R2 for RTC reserve charge A

Reserve for EMI(Near SPI ROM)

1 2 2 1 SPI_CLK
CH21 @EMC@ RH41 @EMC@
10P_0402_50V8J 33_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 Deciphered Date 2014/01/03 Title
VLV-M SOC CLK/PMU/SPI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 8 of 41
5 4 3 2 1
5 4 3 2 1

+1.8VALW
RPC7 2 @ 1 USB_OC#0 <23,25>
1 8 USB_OC0# DC2 RB751V40_SC76-2
2 7 USB_OC1#
3 6 LAN_EN 2 @ 1 USB_OC#1 <22,23,25>
4 5 PASSWORD_CLEAR# DC3 RB751V40_SC76-2
UC1F
D D
10K_0804_8P4R_5%
PASSWORD_CLEAR# G2 M10
GPIO_S5_31 RESERVED_M10 M9
RESERVED_M9

1
JP@ M3 P6
JPW L1 GPIO_S5_32 RESERVED_P6 P7
no DDR door, laction don't care SHORT PADS K2 GPIO_S5_33 RESERVED_P7

2
K3 GPIO_S5_34
+1.8VS M2 GPIO_S5_35 M7
RPC8 N3 GPIO_S5_36 RESERVED_M7 M12 USB3_REXT0 1 2
5 4 PCU_SMB_CLK P2 GPIO_S5_37 USB3_REXT0 RC42
6 3 PCU_SMB_DATA L3 GPIO_S5_38 P10 1.24K_0402_1%
7 2 PCU_SMB_ALERT# GPIO_S5_39 RESERVED_P10 P12
8 1 PLT_RST_BUF# RESERVED_P12
+3VS PLT_RST_BUF# <21,22,25,26,8> M4
4.7K_0804_8P4R_5% J3 RESERVED_M4 M6
P3 GPIO_S5_40 RESERVED_M6
LAN_EN H3 GPIO_S5_41 D4
<22> LAN_EN GPIO_S5_42 USB3_RXP0 U3RXDP1 <23>
B12 E3
GPIO_S5_43 USB3_RXN0 U3RXDN1 <23>
K6
RIGHT PORT FRONT(3.0)
M16 USB3_TXP0 K7 U3TXDP1 <23>
<23> USB20_P0 USB_DP0 USB3_TXN0 U3TXDN1 <23>
RIGHT PORT FRONT(3.0 K16
<23> USB20_N0 USB_DN0
J14
<22> USB20_P1 USB_DP1
LEFT PORT(2.0 G14
<22> USB20_N1 USB_DN1
K12
<17> USB20_P2 J12 USB_DP2
Camera <17> USB20_N2 USB_DN2
K10
<23> USB20_P3 H10 USB_DP3 H8
USB Hub <23> USB20_N3 USB_DN3 RESERVED_H8 H7
RESERVED_H7
1K_0402_1% 1 2 RC43 ICLK_USB_TERMP D10
1K_0402_1% 1 2 RC44 ICLK_USB_TERMN F10 ICLK_USB_TERMP H4
ICLK_USB_TERMN RESERVED_H4 H5 +1.8VS
RESERVED_H5
C C
USB_OC0# C20

1
USB_OC1# B20 USB_OC_0# / GPIO_S5_19
USB_OC_1# / GPIO_S5_20 RC45 @
10K_0402_5%

RC46 1 2 USB_RCOMP D6 BD12 GPIO_S0_SC_56:

2
45.3_0402_1% C7 USB_RCOMPO GPIO_S0_SC_55 BC12 GPIO_S0_SC_56
USB_RCOMPI GPIO_S0_SC_56 A16 Swap Override
BD14 DBG_UART_TXD T9

1
@ GPIO_S0_SC_57 / PCU_UART_TXD BC14 0 = Enable
RC47 1 2 USB_PLL_MON M13 GPIO_S0_SC_58 BF14 RC48 @ 1 = Disable
0_0402_5% USB_PLL_MON GPIO_S0_SC_59 BD16 Reference EDS Page 216
GPIO_S0_SC_60 10K_0402_5%
BC16 DBG_UART_RXD T10
GPIO_S0_SC_61 / PCU_UART_RXD

2
B4
B5 USB_HSIC0_DATA BH12 SOC_SPKR
USB_HSIC0_STROBE ILB_8254_SPKR / GPIO_S0_SC_54 SOC_SPKR <24>

E2
D2 USB_HSIC1_DATA
NOTE: Ref checklist rev1.0 p.25 USB_HSIC1_STROBE BH22 22_0402_5% 1 @EMC@ 2 RC49 PM_I2CSDA1
USB_HSIC_RCOMP must NOT float if they are not being used. SIO_I2C0_DATA / GPIO_S0_SC_78 BG23 PM_I2CSDA1 <26>
22_0402_5% 1 @EMC@ 2 RC50 PM_I2CSCL1
SIO_I2C0_CLK / GPIO_S0_SC_79 PM_I2CSCL1 <26>
1 2 HSIC_RCOMP A7
RC51 45.3_0402_1% USB_HSIC_RCOMP
BG24
SIO_I2C1_DATA / GPIO_S0_SC_80 BH24
49.9_0402_1% 1 2 RC52 LPC_RCOMP BF18 SIO_I2C1_CLK / GPIO_S0_SC_81
BH16 LPC_RCOMP / VGA_RCOMP
<22,25> LPC_AD0 ILB_LPC_AD_0 / GPIO_S0_SC_42
BJ17 BG25 +3VS
<22,25> LPC_AD1 BJ13 ILB_LPC_AD_1 / GPIO_S0_SC_43 SIO_I2C2_DATA / GPIO_S0_SC_82 BJ25
ILB_LPC_CLK_0 : Output of 25MHz, <22,25> LPC_AD2 ILB_LPC_AD_2 / GPIO_S0_SC_44 SIO_I2C2_CLK / GPIO_S0_SC_83
Need Check with EC BG14
<22,25> LPC_AD3 BG17 ILB_LPC_AD_3 / GPIO_S0_SC_45 PM_I2CSDA1 R274 1 @ 2 1K_0402_5%
<22,25> LPC_FRAME# ILB_LPC_FRAME# / GPIO_S0_SC_46
22_0402_5% 1 EMC@ 2 RC53 LPC_CLK_0 BG15 BG26
<25> LPC_CLK_EC ILB_LPC_CLK_0 / GPIO_S0_SC_47 SIO_I2C3_DATA / GPIO_S0_SC_84
ILB_LPC_CLK_1 is for CLK_0 feedback.(Input) 22_0402_5% 1TPM@EMC@
2 RC54 BH14 BH26 PM_I2CSCL1 R272 1 @ 2 1K_0402_5%
<22> CLKOUT_LPC1 BG16 ILB_LPC_CLK_1 / GPIO_S0_SC_48 SIO_I2C3_CLK / GPIO_S0_SC_85
Set to Outpot for Normal Usage ILB_LPC_CLKRUN# / GPIO_S0_SC_49
BG13
<10> SOC_SERIRQ ILB_LPC_SERIRQ / GPIO_S0_SC_50 BF27
SIO_I2C4_DATA / GPIO_S0_SC_86 BG27
B SIO_I2C4_CLK / GPIO_S0_SC_87 B
Need to check the resistors value
2 1 LPC_CLK_0 BH28
CC22 @EMC@ PCU_SMB_DATA BG12 SIO_I2C5_DATA / GPIO_S0_SC_88 BG28
10P_0402_50V8J PCU_SMB_CLK BH10 PCU_SMB_DATA / GPIO_S0_SC_51 SIO_I2C5_CLK / GPIO_S0_SC_89
PCU_SMB_ALERT# BG11 PCU_SMB_CLK / GPIO_S0_SC_52
PCU_SMB_ALERT# / GPIO_S0_SC_53 BJ29
SIO_I2C6_DATA / GPIO_S0_SC_90 BG29
SIO_I2C6_CLK / GPIO_S0_SC_91 / SD3_WP

BH30 GPIO_S0_SC_92 T11


+3VS GPIO_S0_SC_092 BG30 GPIO_S0_SC_93 T12
GPIO_S0_SC_093
PDA (Platform Debug Assistant) Test Points
6 OF 13

VALLEYVIEW-M_FCBGA1170
2

1
4.7K_0402_5%

4.7K_0402_5%

RC85 RC84

thermal@ thermal@ +3VS


THERMAL SENSOR +3VS
1

1
<15,26> DDR_SMB_CK2
R109

0.1U_0402_16V7K
1
QC4 10K_0402_5%
CC120 @ @
MESS138W-G_SOT323-3

2
<15,26> DDR_SMB_DA2 2
D

ALERT_L 1 3 PCU_SMB_ALERT# UC6 SA00003PU00


1 8 EC_SMB_CK2
1

C VDD SCLK EC_SMB_CK2 <25,9>


@ 2 Q8
2 2 7
G

Pull High at EC side CC119 H_THERMDA EC_SMB_DA2


2

QC2 B D+ SDATA EC_SMB_DA2 <25,9>


MESS138W-G_SOT323-3 2200P_0402_50V7K E MMBT3904WH_SOT323-3 H_THERMDC 3 6 ALERT_L
3

thermal@ 1 thermal@ D- ALERT#


D

A RC63 1 2 1 3 PCU_SMB_CLK +3VS 1 2 CPU_THERM# 4 5 A


<25,9> EC_SMB_CK2 THERM# GND
0_0402_5% RC96 33K_0402_5%
QC3 thermal@
G

W83L771AWG-2
2
D

RC64 1 2 1 3 PCU_SMB_DATA ADDRESS:4Dh/10011010b


<25,9> EC_SMB_DA2
0_0402_5% thermal@
G
2

MESS138W-G_SOT323-3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/01/03 Deciphered Date 2014/01/03 Title
VLV-M SOC USB/LPC/SMBus
+1.8VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 9 of 41
5 4 3 2 1
5 4 3 2 1

+1.8VALW +3VL +3VALW


+3VS +1.8VS

1
1
@ RC70 RC78
RC77 4.7K_0402_5% 10K_0402_5%

5
2.2K_0402_5% UC54

2
5
1

P
UC66

2
1 NC 4 EC_SLP_S3#

P
NC 4 2 Y EC_SLP_S3# <25>
SOC_SCI# PMC_SLP_S3#

2
D EC_SCI# 2 Y SOC_SCI# <7> <8> PMC_SLP_S3# A D

G
<25> EC_SCI# A NL17SZ07DFT2G_SC70-5 RC11

3
NL17SZ07DFT2G_SC70-5 SA00004BV00

3
100K_0402_5%
SA00004BV00

1
9012@

+1.8VALW +3VL +3VALW

1
+3VL +1.8VALW

1
@ RC71 RC79
4.7K_0402_5% 10K_0402_5%

5
RC72 UC57

2
1

P
4.7K_0402_5%

5
UC58 NC 4 EC_SLP_S4#

2
1 PMC_SLP_S4# 2 Y EC_SLP_S4# <25>

2
NC 4 <8> PMC_SLP_S4# A
SOC_KBRST#
KB_RST# 2 Y SOC_KBRST# <8>
9012@ NL17SZ07DFT2G_SC70-5 RC66

3
G
<25> KB_RST# A SA00004BV00 100K_0402_5%
NL17SZ07DFT2G_SC70-5

3
SA00004BV00

1
9012@

9012@

+3VL +1.8VALW
+3VL +1.8VALW

1
1
C C
RC75
RC73 4.7K_0402_5%

5
2.2K_0402_5% UC63

2
5

P
UC59

2
1 NC 4 PMC_PWRBTN#
P

NC 4 2 Y PMC_PWRBTN# <8>
SOC_LID_OUT# PBTN_OUT# 9012@

G
2 Y SOC_LID_OUT# <8> <25> PBTN_OUT# A
EC_LID_OUT#
G

<25> EC_LID_OUT# A NL17SZ07DFT2G_SC70-5

3
NL17SZ07DFT2G_SC70-5 SA00004BV00
3

SA00004BV00
@
9012@

+3VS +1.8VALW
1

+1.8VS
RC76
2.2K_0402_5%
5

UC65
2

1
P

UC60 SA00007CX00
NC 4 SOC_SMI# 1 6
Y SOC_SMI# <8> VCCA VCCB 5 +3VL
EC_SMI# 2 2 RC74 1 2 4.7K_0402_5%
G

<25> EC_SMI# A GND EO 4 +1.8VS


SOC_SERIRQ 3 SERIRQ
<9> SOC_SERIRQ A4 B4 SERIRQ <22,25>
NL17SZ07DFT2G_SC70-5
3

SA00004BV00 G2129TL1U_SC70-6
B B
9012@

PMC_SLP_S4# 1 2 EC_SLP_S4#
RC67 9022@ 0_0402_5%
PMC_PWRBTN# 1 2 PBTN_OUT#
RC68 9022@ 0_0402_5%

RPC71
SOC_SCI# 5 4 EC_SCI#
SOC_KBRST# 6 3 KB_RST#
SOC_LID_OUT# 7 2 EC_LID_OUT#
SOC_SMI# 8 1 EC_SMI#

0_0804_8P4R_5%
9022@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/10/16 Deciphered Date 2014/10/16 Title
VLV-M SOC Level Shifter
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 10 of 41
5 4 3 2 1
5 4 3 2 1

+1.35V

D
12000mA +SOC_VCC UC1G 20mil For EVT measurement PJ1 JP@ D
AA27 AD38 +DRAM_VDD_S4_CLK RC55 1 RS@ 2 0_0402_5%
AA29 CORE_VCC_S0iX_AA27 DRAM_VDD_S4_AD38 AF38
AA30 CORE_VCC_S0iX_AA29 DRAM_VDD_S4_AF38 JUMP_43X118
AC27 CORE_VCC_S0iX_AA30 A48 CC23 1 2 1U_0402_6.3V6K PJ2 JP@
AC29 CORE_VCC_S0iX_AC27 DRAM_VDD_S4_A48 AK38 CC24 1 2 .1U_0402_16V7K
AC30 CORE_VCC_S0iX_AC29 DRAM_VDD_S4_AK38 AM38
CORE_VCC_S0iX_AC30 DRAM_VDD_S4_AM38 AV41 JUMP_43X118
AD27 DRAM_VDD_S4_AV41 AV42
AD29 CORE_VCC_S0iX_AD27 DRAM_VDD_S4_AV42 BB46
AD30 CORE_VCC_S0iX_AD29 DRAM_VDD_S4_BB46 BD49
AF27 CORE_VCC_S0iX_AD30 DRAM_VDD_S4_BD49 BD52
AF29 CORE_VCC_S0iX_AF27 DRAM_VDD_S4_BD52 BD53
AG27 CORE_VCC_S0iX_AF29 DRAM_VDD_S4_BD53 BF44 +1.35V_SOC
AG29 CORE_VCC_S0iX_AG27 DRAM_VDD_S4_BF44 BG51
AG30 CORE_VCC_S0iX_AG29 DRAM_VDD_S4_BG51 BJ48 CC25 2 1 2.2U_0402_6.3V6M
P26 CORE_VCC_S0iX_AG30 DRAM_VDD_S4_BJ48 C51 CC26 2 1 2.2U_0402_6.3V6M
P27 CORE_VCC_S0iX_P26 DRAM_VDD_S4_C51 D44 CC27 2 1 2.2U_0402_6.3V6M
U27 CORE_VCC_S0iX_P27 DRAM_VDD_S4_D44 F49 CC28 2 1 2.2U_0402_6.3V6M
U29 CORE_VCC_S0iX_U27 DRAM_VDD_S4_F49 F52
V27 CORE_VCC_S0iX_U29 DRAM_VDD_S4_F52 F53 CC83 2 1 10U_0603_6.3V6M
V29 CORE_VCC_S0iX_V27 DRAM_VDD_S4_F53 H46 CC84 2 1 10U_0603_6.3V6M
V30 CORE_VCC_S0iX_V29 DRAM_VDD_S4_H46 M41
Y27 CORE_VCC_S0iX_V30 DRAM_VDD_S4_M41 M42
C CORE_VCC_S0iX_Y27 DRAM_VDD_S4_M42 C
Y29 V38
Y30 CORE_VCC_S0iX_Y29 DRAM_VDD_S4_V38 Y38
CORE_VCC_S0iX_Y30 DRAM_VDD_S4_Y38

T13 TP2_CORE_VCC_S0iX AA22


TP2_CORE_VCC_S0iX
14000mA +SOC_VNN +1.35VS
420mA
AM22 AG18
AK32 UNCORE_VNN_S3_AM22 ICLK_V1P35_S3_F2_AG18 AJ19
AK30 UNCORE_VNN_S3_AK32 ICLK_V1P35_S3_F1_AJ19
AK29 UNCORE_VNN_S3_AK30 LC1 @
UNCORE_VNN_S3_AK29
45mA
AK27 BD1 +VGA_V1P35_S3_F1 1 2
AK25 UNCORE_VNN_S3_AK27 VGA_V1P35_S3_F1_BD1 BLM18AG601SN1D_2P
AK24 UNCORE_VNN_S3_AK25
UNCORE_VNN_S3_AK24
0715 Add for CRT fliker
AK22 1 2 +3VALW
AJ24 UNCORE_VNN_S3_AK22 AD36 CC29 10U_0603_6.3V6M U1
AJ22 UNCORE_VNN_S3_AJ24 DRAM_V1P35_S0iX_F1_AD36 +VGA_V1P35_S3_F1 5 1
+SOC_VNN +SOC_VCC AG24 UNCORE_VNN_S3_AJ22 AG32 OUT IN

1
AG22 UNCORE_VNN_S3_AG24 UNCORE_V1P35_S0iX_F2_AG32 V36 2
UNCORE_VNN_S3_AG22 UNCORE_V1P35_S0iX_F3_V36 GND 1
AF24 U36 CC30 1 2 22U_0603_6.3V6M
AF22 UNCORE_VNN_S3_AF24 UNCORE_V1P35_S0iX_F4_U36 CC31 1 2 1U_0402_6.3V6K R5 4 3 C2
1

AD22 UNCORE_VNN_S3_AF22 AA25 CC32 1 2 1U_0402_6.3V6K 8.06K_0402_1% BYP SHDN


UNCORE_VNN_S3_AD22 UNCORE_V1P35_S0iX_F5_AA25 1U_0402_6.3V6K
AC24 CC33 1 2 1U_0402_6.3V6K G916T1UF_SOT23-5 2

2
B B
RC56 RC57 AC22 UNCORE_VNN_S3_AC24 CC34 1 2 1U_0402_6.3V6K
100_0402_1% 100_0402_1% AA24 UNCORE_VNN_S3_AC22 CC35 1 2 1U_0402_6.3V6K

1
AD24 UNCORE_VNN_S3_AA24 CC36 1 2 1U_0402_6.3V6K
2

UNCORE_VNN_S3_AD24 CC37 1 2 1U_0402_6.3V6K


AF19 CC38 1 2 1U_0402_6.3V6K R6
BB8 UNCORE_V1P35_S0iX_F6_AF19 AG19 CC39 1 2 1U_0402_6.3V6K 100K_0402_1%
<35> VGFX_VSNS P28 UNCORE_VNN_SENSE UNCORE_V1P35_S0iX_F1_AG19

2
<35> VCORE_VSNS CORE_VCC_SENSE_P28 7 OF 13
N28
<35> VCORE_GSNS CORE_VSS_SENSE_N28
1

VALLEYVIEW-M_FCBGA1170 2 1
<25,27,32,34> SUSP#
RC58 R7 1
100_0402_1% 36K_0402_5%
C3
2

.1U_0402_16V7K
VOUT = 1.25 (1 + R1/R2). 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 2014/01/03 Title
Deciphered Date VLV-M SOC Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 11 of 41
5 4 3 2 1
5 4 3 2 1

D D

Follow CRBv1.15
UC1H +1.05VS
325mA
U22 AC32 +1.05VS_SOC RC59 1 RS@ 2 0_0402_5%
+1.0VALW UNCORE_V1P0_G3_U22 CORE_V1P0_S3_AC32
V22 Y32
CC40 1 2 1U_0402_6.3V6K C5 UNCORE_V1P0_G3_V22 CORE_V1P0_S3_Y32
UNCORE_V1P0_G3 1uF*4 CC41 1 2 1U_0402_6.3V6K B6 UNCORE_V1P0_G3_C5 AA33
CC42 1 2 1U_0402_6.3V6K UNCORE_V1P0_G3_B6 CORE_V1P05_S3_AA33 AF33
CC43 1 2 1U_0402_6.3V6K Y19 CORE_V1P05_S3_AF33 AG33 CC44 1 2 0.47U_0402_6.3V6K
C3 USB3_V1P0_G3_Y19 CORE_V1P05_S3_AG33 AG35
USB3_V1P0_G3 0.01uF*1 CC45 1 2 0.01U_0402_16V7K USB3_V1P0_G3_C3 CORE_V1P05_S3_AG35 U33 CC46 1 2 1U_0402_6.3V6K
CORE_V1P05_S3_U33 U35 CC47 1 2 1U_0402_6.3V6K CORE_V1P05_S3 1uF*3
CORE_V1P05_S3_U35 V33 CC48 1 2 1U_0402_6.3V6K
850mA CORE_V1P05_S3_V33
V32 1000mA
+1.0VS SVID_V1P0_S3_V32 +1.8VALW
BJ6
AD35 VGA_V1P0_S3_BJ6
AF35 DRAM_V1P0_S0iX_AD35 U24
CC49 1 2 1U_0402_6.3V6K AF36 DRAM_V1P0_S0iX_AF35 UNCORE_V1P8_G3_U24 V25
CC50 1 2 1U_0402_6.3V6K AA36 DRAM_V1P0_S0iX_AF36 PCU_V1P8_G3_V25 N20 CC51 1 2 1U_0402_6.3V6K PMC_V1P8_G3 1uF*1
DRAM_V1P0_S0iX 1uF*4 CC52 1 2 1U_0402_6.3V6K AJ36 DRAM_V1P0_S0iX_AA36 USB_V1P8_G3_N20 U25
DRAM_V1P0_S0iX_AJ36
65mA PMU_V1P8_G3_U25
CC53 1 2 1U_0402_6.3V6K AK35 AA18
C DRAM_V1P0_S0iX_AK35 UNCORE_V1P8_G3_AA18 C
AK36
Y35 DRAM_V1P0_S0iX_AK36 +1.8VS
CC54 1 2 1U_0402_6.3V6K Y36 DRAM_V1P0_S0iX_Y35
DRAM_V1P0_S0iX_Y36
10mA
CC55 1 2 1U_0402_6.3V6K AK19 AM30
DDI_V1P0_S0iX 1uF*4 CC56 1 2 1U_0402_6.3V6K AK21 DDI_V1P0_S0iX_AK19 UNCORE_V1P8_S3_AM30 AN32 CC57 1 2 1U_0402_6.3V6K UNCORE_V1P8_S3 1uF*4
CC58 1 2 1U_0402_6.3V6K AJ18 DDI_V1P0_S0iX_AK21 UNCORE_V1P8_S3_AN32 U38 CC59 1 2 1U_0402_6.3V6K
AM16 DDI_V1P0_S0iX_AJ18 UNCORE_V1P8_S3_U38 CC60 1 2 1U_0402_6.3V6K
AN29 DDI_V1P0_S0iX_AM16 CC61 1 2 1U_0402_6.3V6K +1.5VS
AN30 VIS_V1P0_S0iX_AN29
VIS_V1P0_S0iX_AN30
10mA
CC62 1 2 22U_0603_6.3V6M V24 AM32
UNCORE_V1P0_S0iX 22uF*3 CC63 1 2 22U_0603_6.3V6M Y22 VIS_V1P0_S0iX_V24 HDA_V1P5_S3_AM32 CC64 1 2 1U_0402_6.3V6K HDA_LPE_V1P5V1P8_S3 1uF*1
1uF*2 CC65 1 2 22U_0603_6.3V6M Y24 VIS_V1P0_S0iX_Y22 +3VALW
CC66 1 2 1U_0402_6.3V6K AF16 VIS_V1P0_S0iX_Y24
CC67 1 2 1U_0402_6.3V6K AF18 UNCORE_V1P0_S3_AF16 N22 +3VALW_SOC 1 RS@ 2 For EVT measurement
UNCORE_V1P0_S3_AF18
Y18
UNCORE_V1P0_S3_Y18
50mA PCU_V3P3_G3_N22 RC60 0_0402_5%
PCIE_SATA_V1P0_S3 1uF*1 CC68 1 2 1U_0402_6.3V6K G1 N18 CC69 1 2 .1U_0402_16V7K USB_V3P3_G3 0.1uF*1
UNCORE_V1P0_S3 1uF*1 CC70 1 2 1U_0402_6.3V6K AK18 UNCORE_V1P0_S3_G1 USB_V3P3_G3_N18 P18 CC71 1 2 1U_0402_6.3V6K USB_ULPI_V1P8_S3 1uF*1
PCIE_V1P0_S3 1uF*1 CC72 1 2 1U_0402_6.3V6K AM18 PCIE_V1P0_S3_AK18 USB_V3P3_G3_P18 CC73 1 2 1U_0402_6.3V6K PCU_V3P3_G3 1uF*1
VGA_V1P0_S3 1uF*1 CC74 1 2 1U_0402_6.3V6K AM21 PCIE_V1P0_S3_AM18 +3VS
USB_V1P0_S3 0.1uF*1 CC75 1 2 .1U_0402_16V7K AN21 PCIE_V1P0_S3_AM21
PCIE_V1P0_S3_AN21
33mA
USB3DEV_V1P0_S3 0.01uF*1 CC76 1 2 0.01U_0402_16V7K AN18 AN24 +3VS_SOC 1 RS@ 2 For EVT measurement
GPIO_V1P0_S3 1uF*1 CC77 1 2 1U_0402_6.3V6K AN19 PCIE_SATA_V1P0_S3_AN18 VGA_V3P3_S3_AN24 RC61 0_0402_5%
SVID_V1P0_S3 1uF*1 CC78 1 2 1U_0402_6.3V6K AF21 SATA_V1P0_S3_AN19 AN27 1 2 +3VS
AG21 UNCORE_V1P0_S0iX_AF21 SD3_V1P8V3P3_S3_AN27 CC79 1U_0402_6.3V6K
B B
M14 UNCORE_V1P0_S0iX_AG21 AM27
+3VS_LPC
U18 USB_V1P0_S3_M14 LPC_V1P8V3P3_S3_AM27 1 RS@ 2
U19 USB_V1P0_S3_U18 RC62 0_0402_5% VGA_V3P3_S3 1uF*1
AN25 USB_V1P0_S3_U19 1 2
GPIO_V1P0_S3_AN25
35mA
V18 CC81 1U_0402_6.3V6K +1.0VALW USB_HSIC_V1P2_G3 1uF*1
USB_HSIC_V1P2_G3_V18
Disable HSIC
If the USB HSIC is not used, pin V18 can be connected
F1 AD16 CC80 1 2 1U_0402_6.3V6K
RESERVED_F1 VSS_AD16 AD18 @
to either +V1P2A or +V1P0A.
T14 TP_CORE_V1P05_S4 AF30 VSS_AD18 Pop when use +1.2VALW
TP_CORE_V1P05_S4_AF30
8 OF 13
VALLEYVIEW-M_FCBGA1170

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 2014/01/03 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VLV-M SOC Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 12 of 41
5 4 3 2 1
5 4 3 2 1

D D

UC1I UC1J UC1K UC1L UC1M

A11 AC36 AG38 AH47 AT24 AY36 BF30 E8 K9 U3


A15 VSS_A11 VSS_AC36 AC38 AH4 VSS_AG38 VSS_AH47 AH48 AT27 VSS_AT24 VSS_AY36 AY4 BF36 VSS_BF30 VSS_E8 F19 L13 VSS_K9 VSS_U3 U30
A19 VSS_A15 VSS_AC38 AD19 AH41 VSS_AH4 VSS_AH48 AH50 AT30 VSS_AT27 VSS_AY4 AY50 BF4 VSS_BF36 VSS_F19 F2 L19 VSS_L13 VSS_U30 U32
A23 VSS_A19 VSS_AD19 AD21 AH45 VSS_AH41 VSS_AH50 AH51 AT35 VSS_AT30 VSS_AY50 AY9 BG31 VSS_BF4 VSS_F2 F24 L27 VSS_L19 VSS_U32 U40
A27 VSS_A23 VSS_AD21 AD25 AH7 VSS_AH45 VSS_AH51 AH6 AT38 VSS_AT35 VSS_AY9 BA14 BG34 VSS_BG31 VSS_F24 F27 L35 VSS_L27 VSS_U40 U42
A31 VSS_A27 VSS_AD25 AD32 AH9 VSS_AH7 VSS_AH6 AM44 AT4 VSS_AT38 VSS_BA14 BA19 BG39 VSS_BG34 VSS_F27 F30 M19 VSS_L35 VSS_U42 U43
A35 VSS_A31 VSS_AD32 AD33 AJ1 VSS_AH9 VSS_AM44 AM51 AT47 VSS_AT4 VSS_BA19 BA22 BG42 VSS_BG39 VSS_F30 F35 M26 VSS_M19 VSS_U43 U45
A39 VSS_A35 VSS_AD33 AD47 AJ16 VSS_AJ1 VSS_AM51 AM7 AT52 VSS_AT47 VSS_BA22 BA27 BG45 VSS_BG42 VSS_F35 F5 M27 VSS_M26 VSS_U45 U46
A43 VSS_A39 VSS_AD47 AD7 AJ21 VSS_AJ16 VSS_AM7 AN1 AU1 VSS_AT52 VSS_BA27 BA32 BG49 VSS_BG45 VSS_F5 F7 M34 VSS_M27 VSS_U46 U48
A47 VSS_A43 VSS_AD7 AE1 AJ25 VSS_AJ21 VSS_AN1 AN11 AU24 VSS_AU1 VSS_BA32 BA35 BJ11 VSS_BG49 VSS_F7 G10 M35 VSS_M34 VSS_U48 U49
AA1 VSS_A47 VSS_AE1 AE11 AJ27 VSS_AJ25 VSS_AN11 AN12 AU3 VSS_AU24 VSS_BA35 BA40 BJ15 VSS_BJ11 VSS_G10 G20 M38 VSS_M35 VSS_U49 U5
C VSS_AA1 VSS_AE11 VSS_AJ27 VSS_AN12 VSS_AU3 VSS_BA40 VSS_BJ15 VSS_G20 VSS_M38 VSS_U5 C
AA16 AE12 AJ29 AN14 AU30 BA53 BJ19 G22 M47 U51
AA19 VSS_AA16 VSS_AE12 AE14 AJ3 VSS_AJ29 VSS_AN14 AN22 AU38 VSS_AU30 VSS_BA53 BB19 BJ23 VSS_BJ19 VSS_G22 G26 M51 VSS_M47 VSS_U51 U53
AA21 VSS_AA19 VSS_AE14 AE3 AJ30 VSS_AJ3 VSS_AN22 AN3 AU51 VSS_AU38 VSS_BB19 BB27 BJ27 VSS_BJ23 VSS_G26 G28 N1 VSS_M51 VSS_U53 U6
AA3 VSS_AA21 VSS_AE3 AE4 AJ32 VSS_AJ30 VSS_AN3 AN33 AV12 VSS_AU51 VSS_BB27 BB35 BJ31 VSS_BJ27 VSS_G28 G32 N16 VSS_N1 VSS_U6 U8
AA32 VSS_AA3 VSS_AE4 AE40 AJ33 VSS_AJ32 VSS_AN33 AN35 AV13 VSS_AV12 VSS_BB35 BC20 BJ35 VSS_BJ31 VSS_G32 G34 N38 VSS_N16 VSS_U8 U9
AA35 VSS_AA32 VSS_AE40 AE42 AJ35 VSS_AJ33 VSS_AN35 AN36 AV14 VSS_AV13 VSS_BC20 BC22 BJ39 VSS_BJ35 VSS_G34 G42 N51 VSS_N38 VSS_U9 V12
AA38 VSS_AA35 VSS_AE42 AE43 AJ38 VSS_AJ35 VSS_AN36 AN38 AV18 VSS_AV14 VSS_BC22 BC26 BJ43 VSS_BJ39 VSS_G42 H19 P13 VSS_N51 VSS_V12 V16
AA53 VSS_AA38 VSS_AE43 AE45 AJ53 VSS_AJ38 VSS_AN38 AN40 AV19 VSS_AV18 VSS_BC26 BC28 BJ47 VSS_BJ43 VSS_H19 H27 P16 VSS_P13 VSS_V16 V19
AB10 VSS_AA53 VSS_AE45 AE46 AK10 VSS_AJ53 VSS_AN40 AN42 AV24 VSS_AV19 VSS_BC28 BC32 BJ7 VSS_BJ47 VSS_H27 H35 P19 VSS_P16 VSS_V19 V21
AB4 VSS_AB10 VSS_AE46 AE48 AK14 VSS_AK10 VSS_AN42 AN43 AV27 VSS_AV24 VSS_BC32 BC34 C14 VSS_BJ7 VSS_H35 J1 P20 VSS_P19 VSS_V21 V35
AB41 VSS_AB4 VSS_AE48 AE50 AK16 VSS_AK14 VSS_AN43 AN45 AV30 VSS_AV27 VSS_BC34 BC42 C31 VSS_C14 VSS_J1 J16 P24 VSS_P20 VSS_V35 V40
AB45 VSS_AB41 VSS_AE50 AE51 AK33 VSS_AK16 VSS_AN45 AN46 AV35 VSS_AV30 VSS_BC42 BD19 C34 VSS_C31 VSS_J16 J19 P32 VSS_P24 VSS_V40 V44
AB47 VSS_AB45 VSS_AE51 AE53 AK41 VSS_AK33 VSS_AN46 AN48 AV38 VSS_AV35 VSS_BD19 BD24 C39 VSS_C34 VSS_J19 J22 P35 VSS_P32 VSS_V44 V51
AB48 VSS_AB47 VSS_AE53 AE6 AK44 VSS_AK41 VSS_AN48 AN49 AV47 VSS_AV38 VSS_BD24 BD27 C42 VSS_C39 VSS_J22 J27 P38 VSS_P35 VSS_V51 V7
AB50 VSS_AB48 VSS_AE6 AE8 AM12 VSS_AK44 VSS_AN49 AN5 AV51 VSS_AV47 VSS_BD27 BD30 C45 VSS_C42 VSS_J27 J32 P4 VSS_P38 VSS_V7 Y10
AB51 VSS_AB50 VSS_AE8 AE9 AM19 VSS_AM12 VSS_AN5 AN51 AV7 VSS_AV51 VSS_BD30 BD35 C49 VSS_C45 VSS_J32 J35 P47 VSS_P4 VSS_Y10 Y14
AB6 VSS_AB51 VSS_AE9 AF10 AM24 VSS_AM19 VSS_AN51 AN53 AW13 VSS_AV7 VSS_BD35 BE19 D12 VSS_C49 VSS_J35 J40 P52 VSS_P47 VSS_Y14 Y16
AC16 VSS_AB6 VSS_AF10 AF12 AM25 VSS_AM24 VSS_AN53 AN6 AW19 VSS_AW13 VSS_BE19 BE2 D16 VSS_D12 VSS_J40 J53 P9 VSS_P52 VSS_Y16 Y21
AC18 VSS_AC16 VSS_AF12 AF25 AM29 VSS_AM25 VSS_AN6 AN8 AW27 VSS_AW19 VSS_BE2 BE35 D24 VSS_D16 VSS_J53 K14 T40 VSS_P9 VSS_Y21 Y25
AC19 VSS_AC18 VSS_AF25 AF32 AM33 VSS_AM29 VSS_AN8 AN9 AW3 VSS_AW27 VSS_BE35 BE8 D30 VSS_D24 VSS_K14 K22 U1 VSS_T40 VSS_Y25 Y33
AC21 VSS_AC19 VSS_AF32 AF47 AM35 VSS_AM33 VSS_AN9 AP40 AW35 VSS_AW3 VSS_BE8 BF12 D36 VSS_D30 VSS_K22 K32 U11 VSS_U1 VSS_Y33 Y41
AC25 VSS_AC21 VSS_AF47 AG16 AM36 VSS_AM35 VSS_AP40 AT12 AY10 VSS_AW35 VSS_BF12 BF16 D38 VSS_D36 VSS_K32 K36 U12 VSS_U11 VSS_Y41 Y44
AC33 VSS_AC25 VSS_AG16 AG25 AM40 VSS_AM36 VSS_AT12 AT16 AY22 VSS_AY10 VSS_BF16 BF24 E19 VSS_D38 VSS_K36 K4 U14 VSS_U12 VSS_Y44 Y7
AC35 VSS_AC33 VSS_AG25 AG36 M28 VSS_AM40 VSS_AT16 AT19 AY32 VSS_AY22 VSS_BF24 BF38 E35 VSS_E19 VSS_K4 K50 U21 VSS_U14 VSS_Y7 Y9
B B
B2 VSS_AC35 9 OF 13VSS_AG36 B52 VSS_M28 10 OF 13 VSS_AT19 VSS_AY32 11 OF 13
VSS_BF38 VSS_E35 12 OF 13 VSS_K50 VSS_U21 13 OF 13 VSS_Y9
A6 VSS_B2 VSS_B52 B53
A52 VSS_A6 VSS_B53 BE1 VALLEYVIEW-M_FCBGA1170 VALLEYVIEW-M_FCBGA1170 VALLEYVIEW-M_FCBGA1170 VALLEYVIEW-M_FCBGA1170
A51 VSS_A52 VSS_BE1 BE53
A5 VSS_A51 VSS_BE53 BG1
A49 VSS_A5 VSS_BG1 BJ2
A3 VSS_A49 VSS_BJ2 BJ3
BH53 VSS_A3 VSS_BJ3 BJ5
BH52 VSS_BH53 VSS_BJ5 BJ49
BH2 VSS_BH52 VSS_BJ49 BJ51
BH1 VSS_BH2 VSS_BJ51 BJ52
BG53 VSS_BH1 VSS_BJ52 C1
E53 VSS_BG53 VSS_C1 C53
VSS_E53 VSS_C53 E1
VSS_E1
U16
AN16 USB_VSSA_U16
VSSA_AN16

VALLEYVIEW-M_FCBGA1170

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 2014/01/03 Title
Deciphered Date VLV-M SOC GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 13 of 41
5 4 3 2 1
5 4 3 2 1

D D

Remove debug connector

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 2014/01/03 Title
Deciphered Date VLV-M SOC Debug
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 14 of 41
5 4 3 2 1
A B C D E

+DDR_A_VREF_DQ +1.35V CONN@ +1.35V Signal voltage level = 0.675 V


JDIMM1 PLACE TWO 4.7K RESISTORS CLOSE TO
1 2
3 VREF_DQ VSS 4 DDR_A_D4 DIMMS ON DIMM_VREF_CA / DIMM_VREF_DQ
DDR_A_D0 5 VSS DQ4 6 DDR_A_D5
DDR_A_DQS#[0..7] <5> Decoupling caps are needed; one 0.1 µF placed close to VREF pins of each DDR3 SODIMM.
DDR_A_D1 7 DQ0 DQ5 8
DQ1 VSS DDR_A_DQS[0..7] <5>
9 10 DDR_A_DQS#0
DDR_A_DM0 11 VSS DQS0# 12 DDR_A_DQS0
13 DM0 DQS0 14 DDR_A_D[0..63] <5>
DDR_A_D2 15 VSS VSS 16 DDR_A_D6 +1.35V +DDR_A_VREF_DQ
17 DQ2 DQ6 18 DDR_A_MA[0..15] <5>
DDR_A_D3 DDR_A_D7
19 DQ3 DQ7 20 1 2
VSS VSS DDR_A_DM[0..7] <5>
DDR_A_D8 21 22 DDR_A_D12 RD1
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13 4.7K_0402_1%
DQ9 DQ13 1
25 26 1 2
DDR_A_DQS#1 27 VSS VSS 28 DDR_A_DM1 RD2 CD1
DDR_A_DQS1 29 DQS1# DM1 30 4.7K_0402_1%
1 DQS1 RESET# DDR_A_RST# <5> .1U_0402_16V7K 1
31 32 2
DDR_A_D10 33 VSS VSS 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15 DDR_A_RST# 1 2
37 DQ11 DQ15 38 CD2
DDR_A_D16 39 VSS VSS 40 DDR_A_D20 .1U_0402_16V7K
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21 +1.35V +DDR_A_VREF_CA
43 DQ17 DQ21 44 FOR EMI/ESD Require 01/15
DDR_A_DQS#2 45 VSS VSS 46 DDR_A_DM2 1 2
DDR_A_DQS2 47 DQS2# DM2 48 RD3
49 DQS2 VSS 50 DDR_A_D22 4.7K_0402_1%
VSS DQ22 1
DDR_A_D18 51 52 DDR_A_D23 1 2
DDR_A_D19 53 DQ18 DQ23 54 RD4 CD3
55 DQ19 VSS 56 DDR_A_D28 4.7K_0402_1%
All VREF traces should VSS DQ28 .1U_0402_16V7K
DDR_A_D24 57 58 DDR_A_D29 2
have 10 mil trace width DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS 62 DDR_A_DQS#3
DDR_A_DM3 63 VSS DQS3# 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D26 67 VSS VSS 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS VSS

73 74
<5> DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE2 <5>
75 76
77 VDD VDD 78 DDR_A_MA15
79 NC A15 80 DDR_A_MA14
<5> DDR_A_BS2
81 BA2 A14 82
Layout Note:
DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11 Place near JDIMM1
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4 +1.35V
93 A5 A4 94
DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2 CD4 1 2 10U_0603_6.3V6M
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0 CD5 1 2 10U_0603_6.3V6M
99 A1 A0 100 CD6 1 2 10U_0603_6.3V6M
101 VDD VDD 102 CD7 1 2 10U_0603_6.3V6M
2 <5> DDR_A_CLK0 DDR_A_CLK2 <5> 2
103 CK0 CK1 104
<5> DDR_A_CLK0# CK0# CK1# DDR_A_CLK2# <5>
105 106
DDR_A_MA10 107 VDD VDD 108
A10/AP BA1 DDR_A_BS1 <5>
109 110
<5> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <5>
111 112
113 VDD VDD 114 CD8 1 2 .1U_0402_16V7K
<5> DDR_A_WE# WE# S0# DDR_A_CS0# <5>
<5> DDR_A_CAS# 115 116 CD9 1 2 .1U_0402_16V7K
CAS# ODT0 DDR_A_ODT0 <5>
117 118 CD10 1 2 .1U_0402_16V7K
DDR_A_MA13 119 VDD VDD 120 CD11 1 2 .1U_0402_16V7K
A13 ODT1 DDR_A_ODT2 <5>
<5> DDR_A_CS2# 121 122 CD12 1 2 .1U_0402_16V7K
123 S1# NC 124 CD13 1 2 .1U_0402_16V7K
125 VDD VDD 126 CD14 1 2 .1U_0402_16V7K
TEST VREF_CA +DDR_A_VREF_CA
127 128 CD15 1 2 .1U_0402_16V7K
DDR_A_D32 129 VSS VSS 130 DDR_A_D36
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37
133 DQ33 DQ37 134
DDR_A_DQS#4 135 VSS VSS 136 DDR_A_DM4
DDR_A_DQS4 137 DQS4# DM4 138
139 DQS4 VSS 140 DDR_A_D38
DDR_A_D34 141 VSS DQ38 142 DDR_A_D39
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS 146 DDR_A_D44
DDR_A_D40 147 VSS DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_A_DQS#5
DDR_A_DM5 153 VSS DQS5# 154 DDR_A_DQS5
DM5 DQS5
DDR_A_D42
155
157 VSS VSS
156
158 DDR_A_D46
Part Number Description
DQ42 DQ46
DDR_A_D43 159
161 DQ43 DQ47
160
162
DDR_A_D47 SF000002Z00 S_A-P_CAP 330U 2.5V M 6.3X4.2 R17M VLPS
DDR_A_D48 163 VSS VSS 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS VSS 170 DDR_A_DM6
DDR_A_DQS6 171 DQS6# DM6 172
173 DQS6 VSS 174 DDR_A_D54
DDR_A_D50 175 VSS DQ54 176 DDR_A_D55
3 DQ50 DQ55 3
DDR_A_D51 177 178
179 DQ51 VSS 180 DDR_A_D60
DDR_A_D56 181 VSS DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_A_DQS#7
DDR_A_DM7 187 VSS DQS7# 188 DDR_A_DQS7
189 DM7 DQS7 190 +0.675VS
DDR_A_D58 191 VSS VSS 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196
197 VSS VSS 198 CD17 1 2 10U_0603_6.3V6M
199 SA0 EVENT# 200 CD18 1 2 1U_0402_6.3V6K
+3VS VDDSPD SDA DDR_SMB_DA2 <26,9>
201 202 CD19 1 2 1U_0402_6.3V6K
203 SA1 SCL 204 DDR_SMB_CK2 <26,9>
+0.675VS VTT VTT +0.675VS
RS@ RS@ 205 206
2

RD5 RD6 207 GND1 GND2 208


1 BOSS1 BOSS2
Channel A
0_0402_5%

0_0402_5%

CD20
.1U_0402_16V7K TYCO_2-2013022-1
2
1

Part Number = SP07000P700


PCB Footprint = BELLW_80001-1021_204P
Layout Note:
Place near JDIMM1.203,204
<Address: SA1:SA0=00 (A0H)>

DIMM_1 STD H:4mm

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 Deciphered Date 2014/01/03 Title
DDR3L DIMMA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 15 of 41
A B C D E
5 4 3 2 1

Close to LT2 Close to Pin18 Close to LT3


Mode Configure
+3VS +3VS_RT +SWR_VDD +SWR_V12 ROM only mode : PIN 30 4.7k pull low, Pin 31 4.7k pull high.
80mil
EP mode : PIN 30 4.7k pull high, Pin 31 4.7k pull low.

10U_0603_6.3V6M

0.1U_0402_16V4Z

22U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
100mil 1 RS@ 2
100mil EEPROM : PIN 30 4.7k pull high, Pin 31 4.7k pull high.
1 1 1 1 1 1 1 1 1
RT1 0_0805_5%

CT1

CT2

CT3

CT4

CT5

CT6

CT7

CT8

CT9
Default mode
2 2 2 2 2
LVDS@ 2 2 2 2
Close to Pin3
+DP_V33 +3VS_RT +3VS_RT
LVDS@
10U_0603_6.3V6M

0.1U_0402_16V4Z

D 0.1U_0402_16V4Z D
LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@

2
1 1 1 Close to Pin13 Close to

2
Pin27 Close to Pin7 RT3
CT10

CT11

CT12
RT2 LVDS@ 4.7K_0402_5%
@ 4.7K_0402_5%
2 2 2 +3VS_RT

1
UT1 MIIC_SDA MIIC_SCL

1
LVDS@ 19
TXEC+ LCD_TXCLK+ <17>
LVDS@ LVDS@ LVDS@ LT1 2 1 +DP_V33 40mil 3 20

2
DP_V33 TXEC- LCD_TXCLK- <17>
FBMA-L11-201209-221LMA30T_0805
LVDS@ 100mil 13 21 RT4 RT5
LCD_TXOUT2+ <17>

Power
LT2 2 1 +SWR_VDD 18 SWR_VDD TXE2+ 22 LVDS@ 4.7K_0402_5% @ 4.7K_0402_5%
100mil 40mil

LVDS
PVCC TXE2- LCD_TXOUT2- <17>
FBMA-L11-201209-221LMA30T_0805
+SWR_V12 40mil 12 23 LCD_TL_TXOUT1+ PIN30 PIN31

1
11 SWR_LX TXE1+ 24 LCD_TL_TXOUT1-
40mil SWR_VCCK TXE1-
SWR / LDO Mode select 40mil 27
7 VCCK 25 LCD_TL_TXOUT0+
40mil DP_V12 TXE0+ 26 LCD_TL_TXOUT0-
TXE0-
LDO mode is adopted as default power regulator mode.
Also can implement SWR mode by add inductor. +3VS_RT

2
RTD2132R +LCD_VDD
1 LVDS@ 2 4.7K_0402_5%
H_EDP_AUXP_C_TL LCD_EDID_DATA_TL RT6

DP-IN
H_EDP_AUXN_C_TL 1 AUX_P 14 TL_INVT_PWM

GPIO
AUX_N GPIO(PWM OUT) TL_INVT_PWM <17>
15 80mil LCD_EDID_CLK_TL RT7 1 LVDS@ 2 4.7K_0402_5%
H_EDP_TXP0_C_TL 5 GPIO(Panel_VCC) 16
H_EDP_TXN0_C_TL 6 LANE0P GPIO(PWM IN) 17 ENBKL_TL 1 LVDS@ 2 SOC_PWM_TL <6>
LANE0N GPIO(BL_EN) EC_ENBKL <25,6>
RT13 0_0402_5%

9 LVDS 29 LCD_EDID_CLK_TL
<25> EC_SMB_CK3 10 CIICSCL1 MIICSCL1 28 LCD_EDID_DATA_TL
EDID

Other
<25> EC_SMB_DA3 CIICSDA1 MIICDA1
C C
SOC_PWM_TL 100k pull down resistance close to cpu side
32 ROM 31 MIIC_SCL
<17> EDP_HPD HPD MIICSCL0 30 MIIC_SDA
8 MIICSDA0
4 DP_REXT 33

2
DP_GND GND

RT8 LVDS@ RTD2132R-VE-CG_QFN32_5X5


12K_0402_1%
LVDS@

1
Close to Pin8
+LCD_VDD

+LCD_VDD 80mil ENBKL_TL

1
2
RT9 RT14
IEDP@ CT13 100K_0402_5% 100K_0402_5%
CT14 1 2 0.1U_0402_10V6K H_EDP_AUXP_C_R 4.7U_0603_6.3V6K LVDS@ LVDS@
LVDS@ 1

2
IEDP@ RPT1 LVDS@
CT15 1 2 0.1U_0402_10V6K H_EDP_AUXN_C_R LCD_EDID_CLK_TL 1 8
LCD_EDID_CLK <17>
LCD_EDID_DATA_TL 2 7 Close to Panel conn.
LCD_EDID_DATA <17>
LVDS@ LCD_TL_TXOUT0- 3 6
LCD_TXOUT0- <17>
CT16 1 2 0.1U_0402_10V6K H_EDP_AUXP_C_TL LCD_TL_TXOUT0+ 4 5
LCD_TXOUT0+ <17>
<6> H_EDP_AUXP
LVDS@ 0_0804_8P4R_5%
CT17 1 2 0.1U_0402_10V6K H_EDP_AUXN_C_TL
<6> H_EDP_AUXN
LVDS@ RPT2 IEDP@
B CT18 1 2 0.1U_0402_10V6K H_EDP_TXP0_C_TL H_EDP_AUXP_C_R 1 8 B
<6> H_EDP_TXP0 H_EDP_AUXN_C_R 2 7
LVDS@ H_EDP_TXN0_C_R 3 6
CT19 1 2 0.1U_0402_10V6K H_EDP_TXN0_C_TL H_EDP_TXP0_C_R 4 5 PIN15 PIN16 Accept voltage input (high level)
<6> H_EDP_TXN0
IEDP@ 0_0804_8P4R_5%
CT20 1 2 0.1U_0402_10V6K H_EDP_TXP0_C_R 2132S TL_ENVDD 2132S 3.3V
IEDP@
CT21 1 2 0.1U_0402_10V6K H_EDP_TXN0_C_R 2132R +LCD_VDD * 2132R 1.5~3.3V

* Version R internal Power Switch, can * Version R has internal level shifter, remove
Place co-lay Resistor back to back on TOP and BOT output 1A, Rds(on)=0.2 ohm level shifter circuit on AMD platform

Different between 2132S and 2132R

2132S 2132R
IEDP@
CT22 1 2 0.1U_0402_10V7K
<6> H_EDP_TXP1 LCD_TXOUT1+ <17> 1. Support SWR mode 1. Support LDO mode and SWR mode
IEDP@ 2. Internal ROM
CT23 1 2 0.1U_0402_10V7K
<6> H_EDP_TXN1 LCD_TXOUT1- <17>
3. Support LCD_VDD(internal Power switch)
LVDS@ 4. Integrates Level shifter
LCD_TL_TXOUT1+ RT10 1 2 0_0402_5%
A A
LVDS@
LCD_TL_TXOUT1- RT11 1 2 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 Deciphered Date 2014/01/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Translator - RTD2132S
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ZBWAA LA-B303P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 16 of 41
5 4 3 2 1
A B C D E

USB20_HUB_P2_R 1 RS@ 2
USB20_HUB_P2 <23>
R4280 0_0402_5%
BTO : TOUCH_EMI@ L61 DLW21HN900SQ2L_4P
4 3
4 3
LCD POWER CIRCUIT (For EDP panel only)
1 2
1 1 2 1
@EMI@
USB20_HUB_N2_R 1 RS@ 2
Reserver for power consumption
USB20_HUB_N2 <23> Remove on Pre MP phase
R4281 0_0402_5% I rush=2A
W=80mils
EMI request - Close to JEDP connector +LCD_VDD +3VS
1 RS@ 2 U2
R4283 0_0402_5% 1 RS@ 2 +LCD_VDD_R 1 5

C4
R106 0_0805_5% OUT IN
1@ 2
GND

4.7U_0603_6.3V6K
@CAM_EMI@
USB20_N2_R 1 2 3 4 LCD_ENVDD_R 1 R16 2
1 2 USB20_N2 <9> OC EN LCD_ENVDD <6>
0_0402_5%
2 SY6288C20AAC_SOT23-5 1 IEDP@
USB20_P2_R 4 3 SA000079400 C29
4 3 USB20_P2 <9>
IEDP@ @

0.1U_0402_25V6
L2 2
DLW21HN900HQ2L_4P

1 RS@ 2
R4282 0_0402_5%

LVDS colay eDP cable


Pin define will be change after ME ready
2 2

Irush=1.5A 60mils B+
+LCD_INV
L63 +5VS JTOUCH CONN@
+1.8VS
Touch 20mils
2 1 1 RS@ 2 +5VS_LVDS_TOUCH 1
FBMA-L11-201209-221LMA30T_0805 R431 0_0603_5% USB20_HUB_N2_R 2 1
EMI@ USB20_HUB_P2_R 3 2
BKOFF# 4 3
TOUCH_DETECT# 1 @ 2 TOUCH_DETECT_R# 5 4
TOUCH_DETECT# 1 @ 2 R30 0_0402_5% 6 5
<8> TOUCH_DETECT# 7 6
Camera R8 2.2K_0402_5%
8 GND
+3VS
20mils GND
JLVDS
1 RS@ 2 +3VS_LVDS_CAM 1 2
1 2 LCD_EDID_CLK <16>
R432 0_0603_5% USB20_P2_R 3 4
3 4 LCD_EDID_DATA <16>
USB20_N2_R 5 6 INT_MIC_CLK
7 5 6 8 INT_MIC_CLK <24>
INT_MIC_DATA
9 7 8 10 LED_PWM INT_MIC_DATA <24>
<16> LCD_TXOUT0+ 11 9 10 12 BKOFF#_R
<16> LCD_TXOUT0- 13 11 12 14 EDP_HPD
<16> LCD_TXOUT1+ 15 13 14 16 +1.8VS
<16> LCD_TXOUT1- 15 16 +3VS
Camera & MIC
17 18
<16> LCD_TXOUT2+ 19 17 18 20 D29 ESD@

1
<16> LCD_TXOUT2- 21 19 20 22 USB20_P2_R 4 3 USB20_N2_R
<16> LCD_TXCLK+ 21 22 +LCD_VDD Irush=1.5A 60mils 4 3
23 24
<16> LCD_TXCLK- 25 23 24 26 R13
27 25 26 28 10K_0402_5%
29 27 28 30 Irush=1.5A 60mils

2
29 30 +LCD_INV
31 32 <6> H_EDP_HPD#
3 31 32 +3VS 3

1
E-T_3753K-F30N-07R D Q1
2 EDP_HPD 5 2
EDP_HPD <16> Vbus GND
G

1
CONN@
2N7002KW_SOT323-3 S

3
R14
100K_0402_5%

2
INT_MIC_DATA 6 1 INT_MIC_CLK
6 1
SC300001400 close to LVDS conn.
+3VS D6 RB751V40_SC76-2
Reserve for eDP panel 1 2

@
D92 @ESD@
5

1 RS@ 2 1 RS@ 2 USB20_HUB_P2_R 6 3 USB20_HUB_N2_R


SOC_PWM_EDP <6> I/O4 I/O2
VCC

R18 0_0402_5% U50 R29 0_0402_5%


1 +5VS
BKOFF#_R 1 2 4 IN1 EC_ENBKL_R <6>
OUT 2 BKOFF# LED_PWM 1 2 5 2
GND

D4 RB751V40_SC76-2 TL_INVT_PWM <16>


IN2 BKOFF# <25> VDD GND
D5 RB751V40_SC76-2
1

@
LVDS@
R19
3

10K_0402_5% MC74VHC1G08DFT2G_SC70-5 BKOFF# 4 1


R20 I/O3 I/O1
AZC099-04S.R7G_SOT23-6
2

47K_0402_5%
4 1 2 LVDS@ close to JTOUCH conn. 4
2

R21 0_0402_5%
@
Reserve for LVDS panel

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 Deciphered Date 2014/01/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 17 of 41
A B C D E
A B C D E

+1.8VS

+1.8VS +3VS

1
+HDMI_5V_OUT

1
R145 RY1
HDMI_HPD_U 1 2 HDMI_HPD_C 10K_0402_5% R571

2
G
1K_0402_5% 2.2K_0402_5%

2
2

2
UMA_HDMI_CLK 3 1 HDMI_SCLK R186 C265

2
5

1
<6> UMA_HDMI_CLK <6,7> HDMI_HPD#

D
U12 100K_0402_5% 0.1U_0402_10V7K

6
G
1 1

OE#
P
QY1 D
MESS138W-G_SOT323-3 2 4 HDMI_HPD 1 QY3B G 2 HDMI_HPD
UMA_HDMI_DATA 3 1 HDMI_SDATA A Y DMN66D0LDW-7_SOT363-6 S

1
G
<6> UMA_HDMI_DATA

D
74AHCT1G125GW_SOT353-5

1
3
QY2
MESS138W-G_SOT323-3

HDMI Connector
DLW21HN900HQ2L_4P JHDMI CONN@
CY1 1 2 0.1U_0402_10V7K H_DVI_TXC- 4 3 HDMI_R_CK- HDMI_HPD_C 19
<6> H_HDMI_TXC- 4 3 18 HP_DET
+HDMI_5V_OUT +5V
17
CY2 1 2 0.1U_0402_10V7K H_DVI_TXC+ 1 2 HDMI_R_CK+ HDMI_SDATA 16 DDC/CEC_GND
<6> H_HDMI_TXC+ 1 2 15 SDA
HDMI_SCLK
LY1 EMI@ 14 SCL
LY2 EMI@ 13 Reserved
2 CY3 1 2 0.1U_0402_10V7K H_DVI_TXD0- 1 2 HDMI_R_D0- HDMI_R_CK- 12 CEC 2
<6> H_HDMI_TX0- 1 2 11 CK-
HDMI_R_CK+ 10 CK_shield
CY4 1 2 0.1U_0402_10V7K H_DVI_TXD0+ 4 3 HDMI_R_D0+ HDMI_R_D0- 9 CK+
<6> H_HDMI_TX0+ 4 3 8 D0-
DLW21HN900HQ2L_4P HDMI_R_D0+ 7 D0_shield
DLW21HN900HQ2L_4P HDMI_R_D1- 6 D0+
CY5 1 2 0.1U_0402_10V7K H_DVI_TXD1- 4 3 HDMI_R_D1- 5 D1-
<6> H_HDMI_TX1- 4 3 HDMI_R_D1+ 4 D1_shield 20
HDMI_R_D2- 3 D1+ GND 21
CY6 1 2 0.1U_0402_10V7K H_DVI_TXD1+ 1 2 HDMI_R_D1+ 2 D2- GND 22
<6> H_HDMI_TX1+ 1 2 1 D2_shield GND 23
HDMI_R_D2+
LY3 EMI@ D2+ GND
LY4 EMI@ ACON_HMR2U-AK120C
CY7 1 2 0.1U_0402_10V7K H_DVI_TXD2- 1 2 HDMI_R_D2-
<6> H_HDMI_TX2- 1 2

CY8 1 2 0.1U_0402_10V7K H_DVI_TXD2+ 4 3 HDMI_R_D2+


<6> H_HDMI_TX2+ 4 3
DLW21HN900HQ2L_4P
Common CHOKE use 90ohm

HDMI_R_D2- 1 RM1 2 619_0402_1%


3
HDMI_R_D2+
HDMI_R_D1+
1
1
RM2
RM3
2
2
619_0402_1%
619_0402_1%
HDMI POWER CIRCUIT 3
HDMI_R_D1- 1 RM4 2 619_0402_1% +HDMI_5V_OUT VIN = 5V, IOUT = 0.5A , RDS(ON) TYP=95m ; MAX=115m
ZZZ1 HDMI45@
HDMI Royalty Current Limit: TYP=0.8A ; MAX=1A
RPY1
+1.8VS 1 8 HDMI_SCLK
2 7 HDMI_SDATA
HDMI_R_CK+ 1 RM5 2 619_0402_1% 3 6 UMA_HDMI_CLK
HDMI W/Logo + HDCP HDMI_R_CK- 1 RM6 2 619_0402_1% 4 5 UMA_HDMI_DATA +HDMI_5V_OUT
HDMI_R_D0- 1 RM7 2 619_0402_1% UY1
HDMI W/O Logo: RO0000001HM HDMI_R_D0+ 1 RM8 2 619_0402_1% 2.2K_0804_8P4R_5% 1
OUT IN
5
+5VS
HDMI W/Logo: RO0000002HM 1 2
GND
HDMI W/Logo + HDCP: RO0000003HM CY9
3 4
0.1U_0402_10V7K FLG EN
please manually load
3

2 AP2151DWG-7_SOT25-5
D
this virtual material to 45@ BOM 5 G
QY3A SA00006H000
+5VS
S DMN66D0LDW-7_SOT363-6
4

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 Deciphered Date 2014/01/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 18 of 41
A B C D E
A B C D E

CRT CONNECTOR

1 1

<6> UMA_CRT_R UMA_CRT_R L4 1 2 NBQ100505T-800Y_0402 CRT_R_L


CRT@EMI@
<6> UMA_CRT_G UMA_CRT_G L5 1 2 NBQ100505T-800Y_0402 CRT_G_L
CRT@EMI@
<6> UMA_CRT_B UMA_CRT_B L6 1 2 NBQ100505T-800Y_0402 CRT_B_L
CRT@EMI@
JCRT CONN@
6
T15 PAD 11
CRT@ CRT@ CRT@ CRT@ CRT@

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
CRT@ CRT_R_L 1
1 1 1 1 1 1 7
CRT_DDC_DAT 12
C5 C6 C10 C7 C8 C9 CRT_G_L 2
8 G 16
2 2 2 2 2 2 HSYNC 13 17
G
CRT_B_L 3
RP44 9
+HDMI_5V_OUT
150_0804_8P4R_1% VSYNC 14
UMA_CRT_G 8 1 T16 PAD 4
UMA_CRT_R 7 2 10
UMA_CRT_B 6 3 CRT_DDC_CLK 15
5 4 5
USE HDMI POWER J-L_TNBNRACZZ013015

2 CRT@ 2

+HDMI_5V_OUT U4 CRT@ +HDMI_5V_OUT


1 8 1 2
VCC_SYNC BYP C11 0.22U_0402_16V7K

+3VS 2 3 CRT_R_L
VCC_VIDEO VIDEO1

2
+3VS 7 4 CRT_G_L R22 R23
VCC_DDC VIDEO2 4.7K_0402_5% 4.7K_0402_5%
CRT@ CRT@
UMA_CRT_DATA 10 5 CRT_B_L

1
<6> UMA_CRT_DATA DDC_IN1 VIDEO3

<6> UMA_CRT_CLK UMA_CRT_CLK 11 9 CRT_DDC_DAT


DDC_IN2 DDC_OUT1

3 UMA_CRT_VSYNC 13 12 CRT_DDC_CLK 3
<6> UMA_CRT_VSYNC SYNC_IN1 DDC_OUT2
R24 CRT@
UMA_CRT_HSYNC 15 14 VSYNC_R 1 2 22_0402_5% VSYNC
<6> UMA_CRT_HSYNC SYNC_IN2 SYNC_OUT1
R25 CRT@
6 16 HSYNC_R 1 2 22_0402_5% HSYNC
+3VS GND SYNC_OUT2

TPD7S019-15DBQR_SSOP16

2.2K_0402_5%
1 R71 2 UMA_CRT_DATA CRT@
CRT@

2.2K_0402_5%
1 R72 2 UMA_CRT_CLK
CRT@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/09/25 2016/09/25 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 19 of 41
A B C D E
A B C D E

SATA HDD/SSD Conn.


Close to JHDD
JHDD CONN@
1
GND 2 SATA_PTX_C_DRX_P0 C12 1 2 0.01U_0402_25V7K
RX+ 3 SATA_PTX_C_DRX_N0 1 2 0.01U_0402_25V7K SATA_PTX_DRX_P0 <7>
C13
RX- 4 SATA_PTX_DRX_N0 <7>
GND 5 SATA_PRX_DTX_N0 C14 1 2 0.01U_0402_25V7K
TX- 6 SATA_PRX_DTX_P0 1 2 0.01U_0402_25V7K SATA_PRX_C_DTX_N0 <7>
C15
TX+ 7 SATA_PRX_C_DTX_P0 <7>
GND

1 8 1
3.3V 9
3.3V 10 +3VS
3.3V 11
24 GND 12
23 GND GND 13
GND GND 14
5V 15
5V 16
5V 17 +5VS
GND 18
Rsv 19 +5VS
GND 20
Place closely JHDD SATA CONN.
12V
1.2A
21
12V 22 1 1

1
12V C16 C17 C18
SANTA_191503-1 10U_0805_6.3V6M 0.1U_0402_10V7K 0.1U_0402_10V7K

2
2 2

SATA ODD Conn


Power Consumption

2 2
Peak 1800 mA
Read (CD) 1100 mA
Read (DVD) 950 mA
Write 1300 mA
Standby 20mA

JODD CONN@

1
GND 2 SATA_PTX_C_DRX_P1 C19 1 2 0.01U_0402_25V7K
A+ 3 1 2 0.01U_0402_25V7K SATA_PTX_DRX_P1 <7>
SATA_PTX_C_DRX_N1 C20
A- 4 SATA_PTX_DRX_N1 <7>
GND 5 SATA_PRX_DTX_N1 C21 1 2 0.01U_0402_25V7K
B- 6 SATA_PRX_DTX_P1 1 2 0.01U_0402_25V7K SATA_PRX_C_DTX_N1 <7>
C22
B+ 7 SATA_PRX_C_DTX_P1 <7>
GND

8 +5VS
DP 9
80mils
+5V 10
+5V 1 1
11 ODD_MD
14 MD 12 T17 C23 C24
15 GND GND 13
GND GND 10U_0603_6.3V6M .1U_0402_16V7K
2 2

SANTA_201902-1

3 3

FAN Control Circuit


+5VS
CONN@
JFAN
1A +FAN2 1
1 RS@ 2 +5VS_FAN 2 1
R26 0_0603_5% @ 2 3 2
1

FAN@ C26 3
C25 4
10U_0805_6.3V6M 1000P_0402_50V7K 5 GND
2

U5 1 GND
1 8
EN GND ACES_50271-0030N
2 7 FAN@
+FAN2 3 VIN GND 6 R27 10K_0402_5%
4 VOUT GND 5 2 1
<25> DFAN1 VSET GND +3VS
10mil
1

P2793BB0_SO8 FAN_SPEED1
FAN_SPEED1 <25>
C27 1
10U_0805_6.3V6M FAN@ C28
2

FAN@ 0.01U_0402_25V7K
@
2
4 4
Main source SA00005CA00
2nd source SA00005JO00

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/09/25 Deciphered Date 2016/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA HDD/SSD/ODD
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 20 of 41
A B C D E
A B C D E

Slot 1 Half PCIe Mini Card-WLAN


NGFF-Slot1-E-Key-WLAN +3V_WLAN

0.1U_0402_10V7K
JWLAN CONN@ 1 1 1
+3V_WLAN 69 CM6 CM8 CM7
68 GND2
GND1 67 2 2 2
66 GND_75 65 0.1U_0402_10V7K 4.7U_0603_6.3V6K
64 3.3VAUX_74 RSVD_73 63
62 3.3VAUX_72 RSVD_71 61 Close to JWLAN

2
60 RSVD_70 GND_69 59
R75 58 RSVD_68 RSVD/PCIE_TX_N1 57
9022@ 56 RSVD_66 RSVD/PCIE_TX_P1 55
10K_0402_5% RSVD_64 GND_63
1 54 53 1
52 I2C_IRQ RSVD/PCIE_RX_N1 51

1
50 I2C_CLK RSVD/PCIE_RX_P1 49
48 I2C_DAT GND_57 47
<25> WL_OFF# W_DISABLE1# PEWAKE0# WLAN_WAKE# <25>
46 45 WLAN_CLKREQ# <7>
<25> BT_ON W_DISABLE2# CLKREQ0#
44 43
<22,25,26,8,9> PLT_RST_BUF# PERST0# GND_51
42 41 CLK_WLAN# <8>
40 SUSCLK(32KHz) REFCLK_N0 39
COEX1 REFCLK_P0 CLK_WLAN <8>
38 37
36 COEX2 GND_45 35
COEX3 PER_TX_N0 PCIE_PRX_WLANTX_N1 <7>
34 33 PCIE_PRX_WLANTX_P1 <7>
32 CLink_CLK PER_TX_P0 31
<25> E51_RXD
30 CLink_DATA GND_39 29
WLAN/ WiFi
<25> E51_TXD CLink_RST PET_RX_N0 PCIE_PTX_C_WLANRX_N1 <7>
28 27 PCIE_PTX_C_WLANRX_P1 <7>
26 UART_CTS PET_RX_P0 25
Debug card using UART_RTS GND_33
24
UART_RX
23
22 SDIO_RST 21
20 UART_TX SDIO_WAKE 19
18 UART_WAKE SDIO_DAT3 17
16 GND_18 SDIO_DAT2 15
14 LED2# SDIO_DAT1 13
12 PCM_IN SDIO_DAT0 11
pin 8-15 10 PCM_OUT SDIO_CMD 9
8 PCM_SYNC SDIO_CLK 7
Removed for key A 6 PCM_CLK GND_7 5
LED1# USB_D- USB20_HUB_N0 <23>
4
3.3VAUX_4 USB_D+
3
USB20_HUB_P0 <23> WiMax/ BT
2 1
3.3VAUX_2 GND_1
BELLW_80152-3221

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 Deciphered Date 2014/01/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-WLAN/mSATA/GCLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 21 of 41
A B C D E
5 4 3 2 1

Left USB 2.0 x 1


LAN/USB Small board Conn
Current Limit 2A
+USB_VCCC
JLAN CONN@ W=80mils
+5VALW +5VALW +USB_VCCC
1
1 2 @ UR1
D 2 3 1 RS@ 2 LR9 EMI@ 1 D
3 LAN_OFF# <25> 1 OUT
4 R17 0_0402_5% 1 2 USB20_N1 CR6 5
4 5 USB20_N1_R 1 2 USB20_N1 <9> IN 2

10U_0603_6.3V6M
5 6 USB20_P1_R 4 GND
6 2 <23,25> USB_EN#1 EN
7 4 3 USB20_P1 3
7 4 3 USB20_P1 <9> OCB USB_OC#1 <23,25,9>
8
8 PCIE_PRX_C_LANTX_P0 <7>
9 DLW21HN900HQ2L_4P R11 1 @EMI@ 2 0_0402_5% SY6288D20AAC_SOT23-5
9 PCIE_PRX_C_LANTX_N0 <7>
10 DLW21HN900HQ2L_4P SA00007AO00
10 11 PCIE_PTX_C_LANRX_P0 <7>
11 12 PCIE_PTX_C_LANRX_N0 <7> 1 2
EMI@ @ PJ77
12 13 CLK_LAN_R 1 2 CLK_LAN <8> 1 2
13 +3VALW 1 2 +3V_LAN
14 CLK_LAN#_R
14 15 4 3 JUMP_43X39
15 16 4 3 CLK_LAN# <8>
16 17 ISOLATE# EC_SWI# <25,8> Q10
17 L56
18 LANCLK_REQ# 1 2 AO3413_SOT23
18 19 PLT_RST_BUF# R10 0_0402_5% +5VALW @
19 PLT_RST_BUF# <21,25,26,8,9>

D
20 @EMI@ 3 1
20 +3V_LAN
21

CL1

CL2

CL3

CL4
21 22

1
22 PL <24>

G
23

2
23 PR <24> 2 2 1
24 RL6
EXT_MIC_L <24>

.1U_0402_16V7K
27 24 25 100K_0402_5%
NBA_PLUG# <24>

0.01U_0402_25V7K

1U_0402_6.3V6K
28 G1 25 26 @
G2 26

4.7U_0805_10V4Z
1
@ @ 1
@ 2
@

2
+3V_LAN > 40 mil
E-T_6905-E26N-01R

<25> WOL_EN1# 2 1
RL5 @ 47K_0402_5%
C C

LAN LAN_EN WOL


ISOLATEB
+3VS
S0 Sx S0 Sx
For LAN function ----------------------------------------------
0 0 0 0 1 1
1

RL1 2 1 10K_0402_5% LANCLK_REQ# 0 1 0 0 1 1


+1.8VS
1K_0402_5% 1 0 1 1 1 1
RL2
@ 1 1 1 1 1 0*
2

ISOLATE# RL3 1 2 0_0402_5%


WOL_EN# <25>
QL1 *
MESS138W-G_SOT323-3
S3: after SUSP# assert low over 100ms
D

1 3 LANCLK_REQ# RL4 S4/S5: after SYSON assert low over 100ms


<7> CLKREQ_LAN#
15K_0402_5%
Sx Enable Sx Disable
G
2

Wake up Wake up

<9> LAN_EN
WOL_EN# LOW HIGH +3V_LAN rising time (10%~90%) need > 1ms and <100ms.

B B

UT2 +3VALW
+3VS

TPM BADD ADDRESS

EEh - EFh
1 @ 2
1
2
6
9
GPIO0/XOR_OUT
GPIO1
GPIO2/GPX
VSB
VDD1
VDD2
5
19
24
0 RT12 10K_0402_5% 15 GPIO3/BADD
* Floating 7Eh - 7Fh GPIO4/CLKRUN# 8
26 TEST
<25,9> LPC_AD0 23 LAD0
<25,9> LPC_AD1 20 LAD1 3
<25,9> LPC_AD2 17 LAD2 NC0 10 +3VS +3VALW
For EMI <25,9> LPC_AD3 LAD3 NC1 11
NC2 12
CLKOUT_LPC1 28 NC3 13
LPCPD# NC4 Close to Pin5
CLKOUT_LPC1 21 14
1

<9> CLKOUT_LPC1 22 LCLK NC5


<25,9> LPC_FRAME# 16 LFRAME#
RT15 PLT_RST_BUF# 1 1 1 1 Close to Pin10 1 1
22_0402_5% @EMI@ 27 LRESET# 4 CT28 CT29
CT24 CT25 CT26 CT33

10U_0603_6.3V6M

0.1U_0402_10V7K
<10,25> SERIRQ SERIRQ VSS0

10U_0603_6.3V6M

0.1U_0402_10V7K
0.1U_0402_10V7K

0.1U_0402_10V7K
7 18
PP VSS1 25
2

VSS2 2 2 2 2 2 2
1
CT30 @EMI@ NPCT650AA0WX_TSSOP28
10P_0402_50V8J TPM@
2 TPM@

Pin10 connect to +3VS for co-lay with NPCT620 TPM@ TPM@ TPM@ TPM@ TPM@

A A
Pin11 connect to GND for co-lay with NPCT620 Close to Pin19 Close to Pin24

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/09/25 Deciphered Date 2016/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TPM
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 22 of 41
5 4 3 2 1
5 4 3 2 1

DLW21HN900HQ2L_4P
4 3 U3RXDP1_L
<9> U3RXDP1 4 3

1 2 U3RXDN1_L
<9> U3RXDN1 1 2
LR2 EMI@
Current Limit 2A
DLW21HN900HQ2L_4P
DR1 @ESD@ 1 2 U3TXDP1_C 4 3 U3TXDP1_C_L
<9> U3TXDP1 4 3
CR4 0.1U_0402_10V7K
8
W=80mils
3
D +5VALW +USB_VCCA 3 1 2 U3TXDN1_C 1 2 U3TXDN1_C_L D
<9> U3TXDN1 1 2
CR5 0.1U_0402_10V7K
5 6
UR6 U3TXDP1_C_L 5 6 U3TXDP1_C_L LR4 EMI@
1
OUT
5
IN
U3TXDN1_C_L 4 4 7 7 U3TXDN1_C_L LR3 EMI@
2 1 2 USB20_P0_R
GND <9> USB20_P0 1 2
<22,25> USB_EN#1 4
EN
U3RXDP1_L 2 2 9 8 U3RXDP1_L
3 USB_OC#1 <22,25,9>
OCB U3RXDN1_L 1 1 01 9 U3RXDN1_L
<9> USB20_N0
4
4 3
3 USB20_N0_R
SY6288D20AAC_SOT23-5
SA00007AO00 TVWDF1004AD0_SLP2510P8-10-9 DLW21HN900HQ2L_4P
DLW21HN900HQ2L_4P
@
USB20_HUB_N1 4 3 USB20_HUB_N1_R
4 3 @ PJ12
+USB_VCCA 1 2 +USB_VCCB
USB20_HUB_P1 1 2 USB20_HUB_P1_R 1 2
1 2 JUMP_43X79
LR5 EMI@

CLOSE UR3
CLOSE UR6 +USB_VCCB W=80mils CR13 for 2nd source Current Limit 2A JUSBF CONN@
W=80mils GMT droop issue. U3TXDP1_C_L 9
+5VALW +USB_VCCA +5VALW 1 SSTX+
JUSBR CONN@ +5VALW W=80mils +USB_VCCB +USB_VCCB
U3TXDN1_C_L 8 VBUS
W=100mils 1 USB20_N0_R 2 SSTX-
+USB_VCCA VBUS 1 D-
1 1 1 1 USB20_HUB_N1_R 2 1 1 1 1 1 @ UR3 7

100U_D2_6.3VM_R17M
CR2 CR22 CR19 CR20 USB20_HUB_P1_R 3 D- CR1 CR15 CR16 CR17 CR18 + CR13 1 USB20_P0_R 3 GND 10
4 D+ 5 OUT U3RXDP1_L 6 D+ GND 11
10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K
@ @ @ @ 5 SHIELD IN 2 4 SSRX+ GND 12
2 2 2 2 6 GND 2 2 2 2 2 2 4 GND U3RXDN1_L 5 GND GND 13
GND <25> USB_EN#0 EN SSRX- GND
7 3 USB_OC#0 <25,9>
C
8 GND OCB OCTEK_USB-09EAEB C
GND SY6288D20AAC_SOT23-5
SANTA_360131-1 SA00007AO00

+3VALW
+3V_HUB

RR2 1 2 100K_0402_5% HUB_XRSTJ close to UR5 Pin20 and UR4 Pin19 PA: For Z5WE3 schematic
2

RR3 1 2 100K_0402_5% HUB_BUSJ RR28


10K_0402_5% +5VALW +5V_HUB +3V_HUB
RR9 1HUB_28P@2 510K_0402_5% ENUSB_N @ +3V_HUB +5V_HUB close to UR5 Pin21 and UR4 Pin20
1 RS@ 2 +5V_HUB
1

RR8 1 @ 2 10K_0402_5% DRV RR6 1 1 1 Vonder suggest Voltage up 10V


HUB_VBUSM UR5 1 0_0603_5%
RR4 1 2 10K_0402_5% HUB_VBUSM 20 10 USB20_HUB_N0_P28 CR9 CR8 CR10
2

VDD5 DM1 11 USB20_HUB_P0_P28 CR7 10U_0603_10V6M


.1U_0402_16V7K .1U_0402_16V7K
CR11 1 2 0.01U_0402_16V7K RR27 21 DP1 2 2 2 REXT_GND +5V_HUB
VDD33F 10U_0603_6.3V6M
8 USB20_HUB_N1_P28 2
100K_0402_5%
DM2

19
20
25
@ USB20_N3_P28 15 9 USB20_HUB_P1_P28

1
close to UR5 Pin18 and UR4 Pin17 USB20_P3_P28 16 DMU DP2 UR4
1

DPU 6 RR5

VD33F
USB20_HUB_N2_P28

VSS
VDD5
ENUSB_N 25 DM3 7 USB20_HUB_P2_P28 10K_0402_5%
HUB_OVCJ 26 PWRJ DP3 USB20_HUB_P0_P24 12
OVCJ 4 USB20_HUB_N0_P24 11 DP1 1 HUB_OVCJ 1 2

2
DM4 5 USB20_HUB_P1_P24 10 DM1 OVCJ 2 CR12 0.01U_0402_16V7K
HUB_XRSTJ 17 DP4 USB20_HUB_N1_P24 9 DP2 TESTJ 3 HUB_XOUT
B B
1 RS@ 2 USB20_P3_P28 HUB_VBUSM 18 XRSTJ 27 USB20_HUB_P2_P24 8 DM2 XOUT 4 HUB_XIN
<9> USB20_P3 VBUSM TESTJ DP3 XIN
RR10 0_0402_5% HUB_BUSJ 19 23 USB20_HUB_N2_P24 7 5
DRV 22 BUSJ LED1 24 HUB_BUSJ 18 DM3 DM4 6
1HUB_24P@2 USB20_P3_P24 DRV LED2 HUB_VBUSM 17 BUSJ DP4 21
RR11 0_0402_5% 12 HUB_XRSTJ 16 VBUSM DRV 22
HUB_XIN 3 NC1 13 USB20_P3_P24 15 XRSTJ LED1 23
1 RS@ 2 USB20_N3_P28 HUB_XOUT 2 XIN NC2 28 USB20_N3_P24 14 DPU LED2 24
<9> USB20_N3 XOUT NC3 DMU PWRJ
RR12 0_0402_5% REXT_GND 1 2 REXT 13
REXT_GND 1 14 REXT RR7 2.7K_0402_1% REXT
1HUB_24P@2 USB20_N3_P24 VSS REXT FE1.1S-BQFN24B_WQFN24_4X4
RR13 0_0402_5%
FE1.1S-BSOP28BCTR_SSOP28 HUB_24P@
SJ10000C210
HUB_28P@ YR1
1 RS@ 2 USB20_HUB_P0_P28 HUB_XOUT 3 1 HUB_XIN
<21> USB20_HUB_P0
RR14 0_0402_5% 4 2
12MHZ_18PF_7V12000001
1HUB_24P@2 USB20_HUB_P0_P24 HUB_24P@
RR15 0_0402_5%

1 RS@ 2 USB20_HUB_N0_P28
<21> USB20_HUB_N0
RR16 0_0402_5% YR1
12MHZ_18PF_7V12000001
1HUB_24P@2 USB20_HUB_N0_P24 HUB_28P@
RR17 0_0402_5% USB20_HUB_P1 1 RS@ 2 USB20_HUB_P1_P28 SJ10000DH00
RR22 0_0402_5% 500MA 20mil

USB20_HUB_P1 1HUB_24P@2 USB20_HUB_P1_P24 REXT_GND RR26 1 2 0_0603_5%


RR23 0_0402_5%

USB20_HUB_N1 1 RS@ 2 USB20_HUB_N1_P28


RR25 0_0402_5%
1 RS@ 2 USB20_HUB_P2_P28
<17> USB20_HUB_P2
RR18 0_0402_5% USB20_HUB_N1 1HUB_24P@2 USB20_HUB_N1_P24
A A
RR24 0_0402_5%
1HUB_24P@2 USB20_HUB_P2_P24
RR19 0_0402_5%

1 RS@ 2 USB20_HUB_N2_P28
<17> USB20_HUB_N2
RR21 0_0402_5%

1HUB_24P@2 USB20_HUB_N2_P24
RR20 0_0402_5%
Security Classification Compal Secret Data
2014/01/03 2014/01/03 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0/USB2.0/Hub
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 23 of 41
5 4 3 2 1
5 4 3 2 1

+PVDD 1 RS@ 2
+5VS
1 2 RA1 0_0603_5% +AVDD1 1 RS@ 2
+MIC2_VREFO +5VS
UA1 CA3 1 1 RA2 0_0603_5%
16 1 +DVDD 0.1U_0402_10V7K CA1 CA2
RA3 4.7K_0402_5% 29 MONO-OUT DVDD 9 +DVDD_IO CA4 0.1U_0402_10V7K
MIC2-VREFO DVDD-IO
close to pin41
PR_R 2 1 MIC1-VREFO-R 30 2 1 10U_0603_6.3V6M close to pin26 1U_0402_6.3V6K
PR_L 2 1 MIC1-VREFO-L 31 MIC1-VREFO-R 26 +AVDD1 2 2
RA5 4.7K_0402_5% MIC1-VREFO-L AVDD1 40 +AVDD2
AVDD2 1
15 CA5
JDREF 41 +PVDD 0.1U_0402_10V7K
AC_VREF 28 PVDD1 46 +PVDD
VREF PVDD2
close to pin46
RA7 36 +DVDD 2
CPVDD For EMI reserve
PR_L 2 147_0402_1% HPOUT_L 32
PR_R 2 1 HPOUT_R 33 HPOUT-L(PORT-I-L) 2 INT_MIC_DATA <17>
RA4 47_0402_1% HPOUT-R(PORT-I-R) GPIO0/DMIC-DATA 3 INT_MIC_CLK_R RA8 CAM_EMI@
CA6 1 2 1U_0402_6.3V6K CBN 35 GPIO1/DMIC-CLK FBMA-10-100505-301T INT_MIC_CLK <17> +DVDD 1 RS@ 2
CBN +3VS

220P_0402_50V7K
D CBP 37 8 AZ_SDIN0_HD_R 2 1 22_0402_5% AZ_SDIN0_HD <7> 1 RA10 0_0603_5% D

EMI@
CBP SDATA-IN 5 RA9
SDATA-OUT AZ_SDOUT_HD <7>
CA9 1 2 1U_0402_6.3V6K CPVEE 34 +AVDD2 1 RS@ 2 +1.5VS CA10
CPVEE 6 AZ_BITCLK_HD RA11 0_0603_5% 1U_0402_6.3V6K
BCLK AZ_BITCLK_HD <7> 1 2
LDO1-CAP 27 CA11

CA8
CA7 1 2 4.7U_0402_6.3V6M LDO2-CAP 39 LDO1-CAP 10
CA12 1 2 4.7U_0402_6.3V6M LDO3-CAP 7 LDO2-CAP SYNC AZ_SYNC_HD <7> 1U_0402_6.3V6K
LDO3-CAP 12 MONO_IN 2
PCBEEP 1
close to pin, 10mil SPKL- 43 close to pin3 HDALink is 1.5V CA15
SPKL+ 42 SPK-OUT-L- 13 SENSE_A 0.1U_0402_10V7K
SPKR- 44 SPK-OUT-L+ Sense A 14 +3VALW
SPKR+ 45 SPK-OUT-R- Sense B CA14 4.7U_0402_6.3V6M 2
Reserve for solve bobo noise

1
RA12 SPK-OUT-R+ 19 1 2 +DVDD_IO 1 RS@ 2
MIC1-L(PORT-B-L) +1.5VS
1 @ 2 EC_MUTE_INT_R 48 20 RA14 0_0603_5% CA13
<25> EC_MUTE_INT 0_0402_5% SPDIF-OUT/GPIO2 MIC1-R(PORT-B-R) 17

2
MIC2-L(PORT-F-L) 1 4.7U_0402_6.3V6M
18 EXT_MIC 1
4 MIC2-R(PORT-F-R) CA32
RA15 1K_0402_5% CA33 close to pin1
25 DVSS 22 LINE1L CA16 1 2 2.2U_0402_6.3V6M LINE1-L_C 1 2 PR_L 0.1U_0402_16V4Z 1U_0402_6.3V6K
AVSS1 LINE1-L(PORT-C-L) 2 close to pin36
38 21 LINE1R CA17 1 2 2.2U_0402_6.3V6M LINE1-R_C 1 2 PR_R close to pin9 2
1 2 LDO1-CAP 49 AVSS2 LINE1-R(PORT-C-R) 24 RA16 1K_0402_5%
RA17 100K_0402_5% Thermal Pad LINE2-L(PORT-E-L) 23
LINE2-R(PORT-E-R)
11
1 2 RESETB AZ_RST_HD# <7>
2
CA18 4.7U_0402_6.3V6M 47

2
PDB EC_MUTE# <25> CA19
DGND ALC233-VB MQFN 48P RA19 0.01U_0402_25V7K 1 RS@ 2
4.7K_0402_5% 1 RA20 0_0603_5%
@ESD@
close to pin, 10mil @ For EMI reserve 1 RS@ 2
AGND RA21 0_0603_5%

1
close to codec 1 @ 2
Reserve for solve noise issue RA22 0_0603_5%
1 @EMI@ 2
AC_VREF Internal AMP AZ_BITCLK_HD RA23 2 1 CA20 1 2 RA24 0_0603_5%
EC_MUTE# 10_0402_5% EMI@ 10P_0402_50V8J EMI@ 1 @EMI@ 2
1 2 Hight Enable RA25 0_0603_5%
@ LOW Disable
C CA21 CA22 C
0.1U_0402_10V7K 2.2U_0402_6.3V6M
2 1

For EMI protection


Beep sound Combo Jack use SM01000GK00
Change material
RA26 2.2K_0402_5%
1 2 to SM01000GK00
+MIC2_VREFO
LA1
PR_R 1 RS@ 2 0_0402_5% PR <22>
PCI Beep CA23 EMI@
1 RA27 2 1 2 MONO_IN EXT_MIC LA2 1 2 EXT_MIC_L <22> LA3
<9> SOC_SPKR 1 RS@ 2 0_0402_5%
47K_0402_5% SBY100505T-470Y-N_2P PR_L PL <22>

100P_0402_50V8J
0.1U_0402_10V7K 1
1 1
2

CA27

CA24

100P_0402_50V8J
RA28 CA25 CA26
2

100P_0402_50V8J
4.7K_0402_5% 100P_0402_50V8J
@ @EMI@ 2 2 @EMI@
1

For better sound


by customer request

place close to chip


1 2
+3VS
B RA29 100K_0402_5% B

1 2 SENSE_A
<22> NBA_PLUG# RA30 200K_0402_1%

for Combo Jack normal Open

SPK

For EMI reserve SPK Conn.


close to codec DA8
3
SPKL+ 1 RS@ 2 SPK_L1 1
RA32 0_0603_5% 2

SPKL- 1 RS@ 2 SPK_L2


RA33 0_0603_5% YSDA0502C_SOT23-3
@ESD@
1 1
CA28 JSPK CONN@
1000P_0402_50V7K CA29 SPK_L1 1
EMI@ SPK_L2 2 1
1000P_0402_50V7K 2
2 2 SPK_R1 3 6
EMI@ 3 GND
SPK_R2 4 5 EXT_MIC EXT_MIC_L RING2 RING2_L
4 GND
DA9 Speaker 4 ohm: 40mil
A CVILU_CI4404M1HRT-LF A
3 Speaker 8 ohm: 20mil
SPKR+ 1 RS@ 2 SPK_R1 1
RA34 0_0603_5% 2
LA2 CA24
SPKR- 1 RS@ 2 SPK_R2 YSDA0502C_SOT23-3 close to small board connector
RA35 0_0603_5% @ESD@
1 1
EMI@ EMI@
CA30 CA31
1000P_0402_50V7K 1000P_0402_50V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2012/04/19 2015/04/19 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ALC282_233_283
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 24 of 41
5 4 3 2 1
A B C D E

+3VL +3VL H_PROCHOT#_EC 2 1


RB21 9022@ 0_0402_5%
0.1U_0402_10V7K 0.1U_0402_10V7K CB1
1 1 1 1 0.1U_0402_10V7K RB1 1 RS@ 2 0_0402_5% H_PROCHOT# <7>
1 2 <35> VR_HOT#
CB2 CB3 @ @ CB5

1
0.1U_0402_10V7K D QB1
For EMI CB4 2 H_PROCHOT#_EC 1
2 2 2 2 G CB6

111
125
22
33
96

67
0.1U_0402_10V7K 47P_0402_50V8J

9
LPC_CLK_EC UB1 S 2N7002KW_SOT323-3 9012@

3
2

EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
Reserve TRANS_PRSNT for panel timing tuning. 9012@

1
RB2
10_0402_5% +3VL
@EMI@ 1 21
1 2 GATEA20/GPIO00 GPIO0F 23 @ 1
2

<10> KB_RST# 3 KBRST#/GPIO01 BEEP#/GPIO10 26 TRANS_PRSNT BATT_PRES 1 2


1

2
<10,22> SERIRQ 4 SERIRQ GPIO12 27
CB9 WOWL_EN <27> @ CB7 100P_0402_50V8J
<22,9> LPC_FRAME# 5 LPC_FRAME# ACOFF/GPIO13
22P_0402_50V8J RB24
<22,9> LPC_AD3 7 LPC_AD3 ACIN 1 2
@EMI@ PWM Output 10K_0402_5%
2 <22,9> LPC_AD2 8 LPC_AD2 63 BATT_PRES CB10 100P_0402_50V8J
<22,9> LPC_AD1 10 LPC_AD1 BATT_TEMP/AD0/GPIO38 64 BATT_PRES <29>
LPC & MISC

1
<22,9> LPC_AD0 LPC_AD0 AD1/GPIO39 65 TRANS_PRSNT
LPC_CLK_EC 12 ADP_I/AD2/GPIO3A 66 ADP_I <29,30>
AD Input

2
<9> LPC_CLK_EC 13 CLK_PCI_EC AD3/GPIO3B 75 TRANS_SEL ADP_V <30> +3VS
@
<21,22,26,8,9> PLT_RST_BUF# EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76 RB23
+3VL RB3 20 EC_RST# IMON/AD5/GPIO43
<10> EC_SCI# EC_SCII#/GPIO0E 10K_0402_5%
47K_0402_5%9012@ 38 H_PROCHOT#_EC 1 @ 2
1 2 <22> WOL_EN1# GPIO1D
EC_RST# RB4 10K_0402_5%

1
68
DAC_BRIG/GPIO3C EC_SWI# <22,8>
9012@1
9012@ 2 DA Output 70
EN_DFAN1/GPIO3D DFAN1 <20> +3VL
CB8 0.1U_0402_10V7K KSI0 55 71
KSI1 56 KSI0/GPIO30 IREF/GPIO3E 72
57 KSI1/GPIO31 CHGVADJ/GPIO3F VGATE <35>
KSI2
KSI3 58 KSI2/GPIO32 83 LID_SW# 1 2
59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 EC_MUTE# <24>
KSI4 RB5 47K_0402_5%
KSI5 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 EC_SMB_CK3 USB_EN#0 <23>
KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 EC_SMB_DA3 EC_SMB_CK3 <16> WLAN_WAKE# 1 2
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D EC_SMB_DA3 <16>
KSI7 62 87 TP_CLK RB6 47K_0402_5%
KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA TP_CLK <26>
40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <26>
KSO1
KSI[0..7] KSO2 41 KSO1/GPIO21
<26> KSI[0..7] KSO3 42 KSO2/GPIO22 97 +3VS
KSO[0..17] KSO4 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 EC_MUTE_INT EC_ENBKL <16,6>
<26> KSO[0..17] 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 EC_MUTE_INT <24> 1 2
KSO5 TP_CLK
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 TXE_DBG <7>
VCIN0_PH connect to RB7 4.7K_0402_5%
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <29>
2 +3VALW KSO7/GPIO27 SPI Device Interface power portion (9012 only) 2
KSO8 47 TP_DATA 1 2
KSO9 48 KSO8/GPIO28 119 RB8 4.7K_0402_5%
49 KSO9/GPIO29 SPIDI/GPIO5B 120 EC_SDIO <8>
KSO10
50 KSO10/GPIO2A SPIDO/GPIO5C 126 EC_SDI <8> 1
KSO11 SPI Flash ROM EC_SMB_CK3 @ 2
1 2 USB_OC#0 KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128 EC_SCK <8>
RB9 2.2K_0402_5%
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A EC_CS0# <8>
RB10 10K_0402_5%
1 2 USB_OC#1 KSO14 53 KSO13/GPIO2D EC_SMB_DA3 1 @ 2
RB11 10K_0402_5% KSO15 54 KSO14/GPIO2E 73 WLAN_WAKE# RB12 2.2K_0402_5%
KSO16 81 KSO15/GPIO2F ENBKL/AD6/GPIO40 74 WLAN_WAKE# <21>
KSO17 82 KSO16/GPIO48 PECI_KB930/AD7/GPIO41 89 USB_OC#0 WOL_EN# <22> SYSON 1 2
KSO17/GPIO49 FSTCHG/GPIO50 90 USB_OC#0 <23,9>
RB13 4.7K_0402_5%
BATT_CHG_LED#/GPIO52 91 BATT_FULL_LED# <26>
RPB1
1 8 77 CAPS_LED#/GPIO53 92 CAPS_LED# <26> 1 2
EC_SMB_CK1 EC_SMB_CK1 GPIO SUSP#
+3VL <29,30> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PBTN_LED# <26>
2 7 EC_SMB_DA1 EC_SMB_DA1 78 93 RB14 10K_0402_5%
3 6 EC_SMB_CK2 <29,30> EC_SMB_DA1 EC_SMB_CK2 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON BATT_CHG_LOW_LED# <26>
+3VS <9> EC_SMB_CK2 SM
EC_SMB_CK2/GPIO46 Bus SYSON/GPIO56 SYSON <32>
4 5 EC_SMB_DA2 EC_SMB_DA2 80 121
<9> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 VR_ON <35>
VCOUT0_PH_L 1 RS@ 2
PM_SLP_S4#/GPIO59 VS_ON <31>
2.2K_8P4R_5% RB16 0_0402_5%
VCOUT0_PH connect to power portion (9012 only)
6 100
<10> EC_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_RSMRST# <8>
15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 EC_LID_OUT# <10>
<10> EC_SMI# 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 PROCHOT_IN <29>
USB_OC#1 H_PROCHOT#_EC PROCHOT_IN connect
1 2 <22,23,9> USB_OC#1 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104
E51_TXD VCOUT0_PH_L to power portion (9012 only)
<31,33> POK 18 GPIO0B VCOUT0_PH/GPXIOA07 105
RB15 100K_0402_5% GPO
<8> RTC_TEST_R# 19 GPIO0C BKOFF#/GPXIOA08 106 BKOFF# <17>
<22,23> USB_EN#1 GPIO0D GPIO PBTN_OUT#/GPXIOA09
25 107
<22> LAN_OFF# 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 3VALW_PWREN <31>
<20> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
29
<21> WL_OFF# E51_TXD 30 EC_PME#/GPIO15
<21> E51_TXD E51_RXD 31 EC_TX/GPIO16 110 ACIN
<21> E51_RXD 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 ACIN <30,8>
EC_ON
3 <8> PMC_CORE_PWROK 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <31> 3
1 2 EC_MUTE_INT <26> WL_BT_LED# 36 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 115 LID_SW# ON/OFFBTN# <26>
<26> NUM_LED# NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04 LID_SW# <26>
RB17 4.7K_0402_5% 116 SUSP#
SUSP#/GPXIOD05 117 SUSP# <11,27,32,34>
GPXIOD06 118 BT_ON <21> +1.8VALW
AGND/AGND

122 PECI_KB9012/GPXIOD07 9022@


<10> PBTN_OUT# XCLKI/GPIO5D
GND/GND
GND/GND
GND/GND
GND/GND

123 124 +EC_V18R 1 2 +3VL


<10> EC_SLP_S4# XCLKO/GPIO5E V18R
1 RB41 0_0603_5%
GND0

CB12 RB19
9012@ 4.7U_0805_10V4Z EC_SWI# 1 2
9012@ KB9012QF-A4_LQFP128_14X14 2 1K_0402_5%
11
24
35
94
113

69

Signal pull high is default status (ROM only mode).


If signal pull low, EC will send translator code to chip.(EP mode) UB1
S IC KB9022QC LQFP 128P EC CONTROLLER
+3VL 9022@
SA000075S20 Close to EC
EC DEBUG port Voltage Comparator Pins FOR 9012 A3
2

CONN@ ESD@
RB20 JDB SUSP# 1 2
LVDS@ 10K_0402_5% 1 VCIN0 pin109 >1.2V <1.2V CB14 180P_0402_50V8J
1 2 +3VS
E51_TXD VCIN1 pin102
2 3 E51_RXD
1

TRANS_SEL 3 4
4 HIGH
VCOUT0 pin104 LOW
2

ACES_85205-0400 (default)
RB22 LOW
@ 10K_0402_5% VCOUT1 pin103 HIGH
4 (default) 4
1

For Translator select

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/01/03 Deciphered Date 2014/01/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LPC-EC-KB9012&930
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 25 of 38
A B C D E
5 4 3 2 1

Screw Hole PCB Fedical Mark PAD


Power Button LED Small board to Conn PBTN/B to M/B
CPU FD1 FD2 FD3 FD4

H1 H2 H3 @ @ @ @
H_3P7 H_4P3x4P0 H_4P1

1
@ @ @ NOTICE: ON/OFFBTN# have

1
pull-hign resistance on
motherboard

PTH
CONN@
JLED
+3VL H4 H5 H6 H7 1 +5VALW
D H_3P0 H_3P0 H_3P0 H_3P0 1 2 JPWR CONN@ D
2 BATT_FULL_LED# <25> +5VALW
@ @ @ @ 3 1

2
3 BATT_CHG_LOW_LED# <25> 1 2
4

1
4 WL_BT_LED# <25> 2 3 PBTN_LED# <25>
R28 7 5 5 ON/OFFBTN#
8 G1 5 6 6 GND 3 4
100K_0402_5% G2 6 GND 4
TJG-533-V-T/R_6P 1 E-T_6916K-Q06N-00L CVILU_CF31041D0R4-10-NH
3 1 ON/OFFBTN# ON/OFFBTN# <25> H8 H9 H11
H_3P0 H_3P0 H_3P2
4 2 @ @ @

1
SW2 @
5
6

NPTH

Place near DDR connector for DQA easy access H10


H_3P0N
1 @ 2 ON/OFFBTN# @
R108 0_0805_5%

1
H15
H_4P2x3P2N
@

1
C Card Reader + TP + Lid SW C

KEYBOARD CONN.
JKB JCARD CONN@
1 +3VS 1
<25> NUM_LED# 1 1
2 2
3 2 3 2
+3VL
+3VS
2<25> CAPS_LED#
1 +3VS_CAP 4 3 4 3
4 <21,22,25,8,9> PLT_RST_BUF# 4
R33 300_0402_5% KSI1 5 5
5 <7> CLKREQ_CR# 5
KSI6 6 6
KSI5
KSI0
KSI4
7
8
9
6
7
8
R12 1 @EMI@ 2 0_0402_5%
<7>
<7>
PCIE_PTX_C_CRRX_P2
PCIE_PTX_C_CRRX_N2
7
8
9
6
7
8
ISPD
9 DLW21HN900HQ2L_4P <7> PCIE_PRX_C_CRTX_P2 9
KSI3 10 <7> PCIE_PRX_C_CRTX_N2 10
KSI2 11 10 1 2 11 10
KSI7 12 11 <8> CLK_CR 1 2 CLK_CR_R 12 11 ZZZ
KSO15 13 12 CLK_CR#_R 13 12
KSO12 14 13 4 3 14 13
KSO11 15 14 <8> CLK_CR# 4 3 15 14
15 L57 EMI@ <25> LID_SW# 15
KSO10 16 <8> TP_INTR# 16
KSO9 17 16 1 2 17 16
17 <25> TP_DATA 17
KSO8 18 R15 0_0402_5% 18 PCB LA-B303P
19 18 <25> TP_CLK 19 18
KSO13 @EMI@ TP_I2CSDA1
KSO7 20 19 TP_I2CSCL1 20 19
KSO6 21 20 20
KSO14 22 21 R477 1 @ 2 0_0402_5%
22 <9> PM_I2CSDA1
KSO5 23 R478 1 @ 2 0_0402_5%
23 <9> PM_I2CSCL1
KSO3 24 21
KSO4 25 24 R475 1 2 0_0402_5% 22 GND
25 <15,9> DDR_SMB_DA2 GND
KSO0 26 R476 1 2 0_0402_5%
26 <15,9> DDR_SMB_CK2
KSO1 27
KSO2 28 27 ACES_50578-0200N-001
29 28
30 29
B B
KSO17 31 30
32 31
KSO16 33 32
2 1 +3VS_NUM 34 33
+3VS 34
R34 300_0402_5% 35
GND1 36
GND2
CVILU_CF17341U0R0-NH
CONN@

KSI[0..7]
KSI[0..7] <25>
KSO[0..17]
KSO[0..17] <25>

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/09/25 Deciphered Date 2016/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TP/ISPD/KB/Screw
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 26 of 41
5 4 3 2 1
A B C D E

Vgs=10V,Id=14A,Rds=6mohm
Part number is SA000070S00
+1.0VALW TO +1.0VS VIN 5V (VBIAS=5V),IMAX=4A,Rds=22mohm

470_0805_5%
R223 +5VALW
+1.0VALW U10
+5VS
Q14_GATE 1 R225 2 1 7 PJ3 @

3 1
B+ VIN VOUT
1 220K_0402_5% 2 8 +5VS_LS 1 2

6
0.1U_0402_25V6
VIN VOUT C180 330P_0402_50V7K
1 1

4
C253 R222 @ C182 C552 SUSP# 3 6 1 2 PAD-OPEN 4x4m 2
5 820K_0402_5% Q13A Q13B 0.1U_0402_10V7K ON CT @ CV181

1U_0402_6.3V6K
6 3 2 2 SUSP5 ESD@

0.1U_0402_10V7K
7 2 2N7002DW-T/R7_SOT363-6 2 2 4

2
+5VALW VBIAS 1
8 1 2N7002DW-T/R7_SOT363-6 5

4
GND 9
1 1
+1.0VS GND
Q14
AO4354_SOIC-8 @PJ10
@ PJ10 TPS22967DSGR_SON8_2X2
1.0VS_LS 1 2
1 2
JUMP_43X79

1
@PJ11
@ PJ11
2
+5VALW TO +5VS
+1.0VS 1 2 +1.05VS
JUMP_43X39 Load switch

VIN 1.8V and 1.35V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm


+1.8VALW TO +1.8VS +1.8VALW
+1.8VS
U9 PJ9 @
+1.35V TO +1.35VS 1
2 VIN1 VOUT1
14
13
+1.8VS_LS 1 2
+5VALW +0.675VS
C543 VIN1 VOUT1 C549 PAD-OPEN 4x4m
Load Switch 1U_0402_6.3V6K
1
SUSP# 3 12 1 2270P_0402_50V7K 1

2
ON1 CT1 C551
@ +5VALW 4 11 0.1U_0402_10V7K R44 R43
2 VBIAS GND C544 330P_0402_50V7K @ 100K_0402_5% 22_0805_5%
SUSP# 5 10 1 2 2
ON2 CT2 +1.35VS

1
+1.35V 6 9 PJ8 @ SUSP
7 VIN2 VOUT2 8 +1.35VS_LS 1 2
VIN2 VOUT2

1
2 D Q6 2
15 PAD-OPEN 4x4m 1
GPAD

1
C545 2 D Q7
TPS22966DPUR_SON14_2X3 @ G SUSP# <11,25,32,34>
1 2 SUSP
@ C550
2 0.1U_0402_10V7K G
S 2N7002KW_SOT323-3

3
1U_0402_6.3V6K
2 S 2N7002KW_SOT323-3

3
+3VALW TO +3V_WLAN
for WOWL
+3VS 1 RS@ 2 +3V_WLAN
RM11 0_0805_5%

Part number is SA000070S00


VIN 3V (VBIAS=3V),IMAX=4A,Rds=22mohm
Part number is SA000070S00 +3VALW
3 VIN 0.8V-5.5V (VBIAS=5V),IMAX=4A,Rds=22mohm +3V_WLAN U11 3
+3VALW @PJ4
@ PJ4 +3VS
1 7
U8 ISCT@ 2 VIN VOUT 8 +3VS_LS 1 2
ISCT@ VIN VOUT C181 330P_0402_50V7K 1 2
1
1 7 +3V_WLAN_LS 1 2 @ C183 SUSP# 3 6 1 2 2
2 VIN VOUT 8 RM10 0_0805_5% ON CT JUMP_43X79 @ CV182

1U_0402_6.3V6K
C546 VIN VOUT
1

0.1U_0402_10V7K
1U_0402_6.3V6K WOWL_EN 3 6 2 4
<25> WOWL_EN ON CT +5VALW VBIAS 1
1 1 5
@ ISCT@ C547 GND 9
2 4 C548 0.1U_0402_10V7K GND
+5VALW VBIAS 5 270P_0402_50V7K @
GND 9 2 2 TPS22967DSGR_SON8_2X2
GND

TPS22967DSGR_SON8_2X2

please refer to the table to choose C548 +3VALW TO +3VS


for EC detect ISCT
WOWL_EN : HIGH -> NOISCT
WOWL_EN : LOW -> ISCT
Load switch
+3VALW
1

RM12
NOISCT@ 10K_0402_5%
2

4 4
WOWL_EN
1

RM13
ISCT@ 10K_0402_5%
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/09/25 Deciphered Date 2016/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC-DC INTERFACE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 27 of 41
A B C D E
5 4 3 2 1

Mark Green frame that means this part is not belong to layout module part .

Function Field :
D D

Support 37.1
RTC 38.2
EMI Part 47.1

VIN
@ PJP1
PF1 EMI@ PL1
ACES_50299-00401-001
5A_32V_0466005.NRHF FBMA-L11-201209-121LMA50T_0805
1 DC_IN 1 2 DC_IN_S1 1 2
1 2
2 3
3 4 1 2
4 EMI@ PL2
FBMA-L11-201209-121LMA50T_0805

1
EMI@ PC1 EMI@ PC2 EMI@ PC3 EMI@ PC4
2 1000P_0603_50V7K 100P_0603_50V8 100P_0603_50V8 1000P_0603_50V7K

2
C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 2012/07/11 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN / RTC Battery
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 28 of 41
5 4 3 2 1
5 4 3 2 1

Mark Green frame that means this part is not belong to layout module part .

Function Field :
Support 37.1
D
OTP 39.7 D
EMI Part 47.1
@ PJ5
1 2

+RTC_R_1
1 2
JUMP_43X39 +RTC_R
1
@EMI@ PL5
2 OTP
FBMA-L11-201209-121LMA50T_0805 VMB
EMI@ PL3
+3VL
@ PJP2 PF2 FBMA-L11-201209-121LMA50T_0805
BATT+
1 BATT_S1 1 2 1 2 <25,30> ADP_I
1 2

1
2 3 10A_24V_F1206HB10V024TM

1
3 4
4

1000P_0402_50V7K

0.1U_0402_25V4K

0.1U_0402_25V4K
5 1 2

0.01U_0402_25V7K
BATT_P5 PR6 PR9
5 6 EC_SMDA EMI@ PL4 12.1K_0402_1%
6 1K_0402_1%

EMI@ PC5

@EMI@ PC8

EMI@ PC6

@EMI@ PC9
7 EC_SMCA FBMA-L11-201209-121LMA50T_0805

2
1

1
10 7 8 @PR8
@ PR8 @ PR10

2
11 GND 8 9 PR1 0_0402_5% 0_0402_5%

100K_0402_1%_TSM0B104F4251RZ
GND 9 1K_0402_1% 1 2 1 2

2
<25> PROCHOT_IN <25> VCIN0_PH
SUYIN_200045MR009G171ZR

1
PR7

1
20K_0402_1% @ PC7

PH1
C 0.1U_0402_10V7K C
1

EMI@ PD2

2
PJSOT24C_SOT23-3

2
EMI@ PD1 2
PJSOT24C_SOT23-3 1
3
2

PR2
6.49K_0402_1%
1 2
+3VL
1

Initial Recovery
PR3
1K_0402_1%
2
1

PR5 PR4
45W 0.55V 0.43V
BATT_PRES <25>
100_0402_1% 100_0402_1% UMA
2

EC_SMB_DA1 <25,30>

Initial Recovery
EC_SMB_CK1 <25,30>

B B
CPU
OTP 90 C 70 C

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 2012/07/11 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Battery Conn / OTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 29 of 41
5 4 3 2 1
5 4 3 2 1

Module model information Mark Green frame that means this part is not belong to layout module part .
BQ24735A_V1.mdd
BQ24735A_V2.mdd Function Field :
Regulator 40.1
Support 40.2

1
D B+
D 2 D
G PQB05
EMI Part 47.1
2N7002KW_SOT323-3
S

3
PRB11
PRB12
1 2 1 2
1M_0402_5% 3M_0402_5%

VIN PQB03 PQB04


AON6414 P1 SI7716ADN-T1-GE3_POWERPAK8-5 P2 PQB07
1 1 PRB50 EMI@ PLB01 CHG_B+ SI7716ADN-T1-GE3_POWERPAK8-5
2 2 0.01_1206_1% 1UH_NRS4018T1R0NDGJ_3.2A_30% 1
5 3 3 5 1 4 1 2 2

2200P_0402_25V7K
10U_0805_25V6K

10U_0805_25V6K
5 3
2200P_0402_50V7K

0.1U_0402_25V6
2 3

0.1U_0402_25V6

@EMI@ PCB23

@EMI@ PCB24
4

4
1

1
0_0402_5%

PCB25

PCB26

0.01U_0402_50V7K
PCB10

@ PRB10

4
1

VIN
PCB11

PCB27
2

2
2

VF = 0.5V
2

2
3

2
PDB01

0.1U_0402_25V6
BQ24725A_ACDRV_1 BAS40CW_SOT323-3

0.1U_0402_25V6
BQ24725A_BATDRV 1 2 BQ24725A_BATDRV_1

1
1
PCB13

PCB15
PRB27

1 1

10_1206_1%
1 2 PCB01 4.12K_0603_1%

2
0.047U_0402_25V7K

PRB26
2
PCB14 1 2
0.1U_0402_25V6 VF = 0.37V

5
2.2_0603_5%
PRB25
C PDB02 C

BQ24725A_VCC2
RB751V-40_SOD323-2

AON7408L
BQ24725A_ACP
PRB28

PQB01
BQ24725A_REGN
0_0402_5%

BQ24725A_BST2

2
DH_CHG 1 2 4

BQ24725A_LX
4.12K_0603_1%

4.12K_0603_1%
1

PCB22 BATT+
PRB15

PRB16

DH_CHG
1 2 PLB03
4.7UH_PCMB063T-1R0MS_12A_20% PRB51

3
2
1
BQ24725A_ACN
1U_0603_25V6K 1 2 0.01_1206_1%
BQ24725A_LX 1 2 CHG1 4
2

PCB21

5
20

19

18

17

16
1U_0603_25V6K 2 3

CSON1
1

@EMI@ PCB02 @EMI@ PRB02


4.7_1206_5%

1 CSOP1
BTST
PHASE

HIDRV
VCC

REGN

10U_0805_25V6K

10U_0805_25V6K
AON7406L
21

PQB02

0.1U_0402_25V6

0.1U_0402_25V6
PAD

PCB05

PCB06
1

1
1 15 DL_CHG 4

1
PCB28

PCB29
ACN LODRV

2
2 14

2
ACP PUB00 GND PRB24

3
2
1

680P_0402_50V7K
BQ24725RGRR_QFN20_3P5X3P5 10_0603_1%
BQ24725A_CMSRC 3 13 SRP1 2 CSOP1

1
CMSRC SRP PRB23

2
6.8_0603_1%
BQ24725A_ACDRV 4 12 SRN1 2 CSON1

2
ACDRV SRN PCB20
0.1U_0603_16V7K
1 2 5 11 BQ24725A_BATDRV
+3VL ACOK BATDRV
ACDET

PRB17 100K_0402_1%
IOUT

SDA

SCL

ILIM
B B

<25,8> ACIN
6

10
+5VALW
BQ24725A_ACDET

BQ24725A_ILIM 1 2
BQ24725A_IOUT

PRB21
VIN

0.01U_0402_25V7K
1 590K_0402_1%

100K_0402_1%

1
PRB22

PCB19
PRB18
422K_0402_1%

1
1 2
2
VIN
PRB13
2

309K_0402_1%

2
Vin Dectector ADP_V <25>
Min. Typ Max.

1
66.5K_0402_1%

L-->H 17.16V 17.63V 18.12V


2200P_0402_50V7K

PRB14 @ PCB12
EC_SMB_CK1 <25,29>
100P_0402_50V8J

H-->L 16.76V 17.22V 17.70V 0.1U_0402_10V7K


1

47K_0402_1%

2
1

PCB17

1
PRB19
PCB16

2
VILIM = 20*ILIM*Rsr EC_SMB_DA1 <25,29>
2

ILIM = 3.3*100/(100+107)/20/0.02 @ PRB20


2

= 3.986 A 0_0402_5%
1 2
ADP_I <25,29>
For A51 ADP_V function
1

A A

Close EC chip @ PCB18


@PCB18
100P_0402_50V8J
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2014/07/02 Deciphered Date 2012/07/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CHARGER
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Common Circuit 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 30 of 41
5 4 3 2 1
5 4 3 2 1

Module model information Mark Green frame that means this part is not belong to layout module part .
SY8206B_V2.mdd

Function Field :
D Regulator 35.1 D

Support 35.2
EMI Part 47.1
PR304
499K_0402_1%
ENLDO_3V5V 1 2
3.3V LDO 150mA~300mA B+
PU300 PC303 PR303

1
1M_0402_1%
B+ EMI@ PL301 7 1 3V5V_EN_3 0.01U_0402_25V7K 1K_0402_5%

PR305
HCB2012KF-121T50_0805 EN2 EN1 1 2 1 2

2200P_0402_50V7K
1 2 3V_VIN 8 3 3V_FB
0.1U_0402_25V6
IN FB

10U_0805_25V6K
0.1U_0402_25V6

6 1
BST_3V 2 1 2

2
1

1
BS
@EMI@
ESD@ PC315

PC313

EMI@ PC314

PC311
PR301 PC301
0_0603_5% 0.1U_0603_25V7K PL303
2

2
10 LX_3V 1 2
LX +3VALWP
9 4 2.2UH_PCMB063T-1R0MS_12A_20%
+3VALWP

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
EMI@ PR302
GND OUT

680P_0603_50V7K 4.7_1206_5%
2 5

1
+3VLP

PC305

PC306

PC307
PG LDO
SY8206BQNC_QFN10_3X3
Ipeak : 5A

2
Imax : 3.5A

1 3V_SN
PC309

2
<25,33> POK

2
4.7U_0603_6.3V6M Iocp : 6A
PR310

EMI@ PC302
100K_0402_1%
1 2
FSW : 750KHz
+3VL

2
C C
@ PJ303
+3VALWP 1 2 +3VALW
1 2
JUMP_43X118

PR306 @ PJ302
2.2K_0402_5% 1 2
1 2 +3VLP 1 2 +3VL
<25> EC_ON JUMP_43X39
@ PR307
@PR307
1 2
<25> VS_ON Place to 3V EN1 pin
0_0402_5%
PR311 @ PR312
0_0402_5% 0_0402_5%
3V5V_EN 1 2 3V5V_EN_3 1 2
3VALW_PWREN <25>
Module model information 1M_0402_1%

4.7U_0402_6.3V6M

0.047U_0402_16V4Z
1

1
PR308

PC304

PC312
SY8208C_V2.mdd 2

2
@
2

B+ EMI@ PL351
HCB2012KF-121T50_0805
1 2 5V_VIN
B B
2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

PU350 PC353 PR353


8 1 3V5V_EN 6800P_0402_25V7K 1K_0402_5%
1

1
@EMI@ PC363

EMI@ PC364

PC361

PC362

IN EN1 1 2 1 2
3 5V_FB
EN2 +5VALWP
2

@ 6 BST_5V 1 2 1 2
BS
PR351 PC351
Ipeak : 8A
0_0603_5% 0.1U_0603_25V7K PL353
9 10 LX_5V 1 2 +5VALWP
Imax : 5.6A
GND LX
VCC_3V 5 4 2.2UH_PCMB063T-1R0MS_12A_20%
Iocp : 9A
1

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
680P_0603_50V7K 4.7_1206_5%
@EMI@ PR352
4.7U_0603_6.3V6M

VCC OUT

150U_D2_6.3V_Y
2 7
1 FSW : 750KHz
1

1
PC365

PC355

PC356

PC357

PC358

PC360
PG LDO +
4.7U_0603_6.3V6M

SY8208CQNC_QFN10_3X3
1 5V_SN
2

2
1

PC359

2@ @PJ352
@ PJ352
+5VALWP 1 2 +5VALW
1 2
2

@EMI@ PC352

JUMP_43X118
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+3VALW/+5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 31 of 41
5 4 3 2 1
5 4 3 2 1

Module model information


Mark Green frame that means this part is not belong to layout module part .
RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer

Function Field :
D D

Regulator 35.3
Support 35.4
EMI Part 47.1

EMI@ PLW01
HCB2012KF-121T50_0805
B+ 1 2 1.35V_B+ PRW01
0_0603_5%

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
BST_1.35V 1 2 BOOT_1.35V
@EMI@ PCW17

EMI@ PCW18
+1.35V
1

1
PCW15

PCW16
DH_1.35V +0.675VSP
2

10U_0603_6.3V6M

10U_0603_6.3V6M
SW_1.35V

1
PCW06

PCW07
PCW01

5
+1.35VP

16

17

18

19

20
0.1U_0603_25V7K

2
PHASE

BOOT

VTT
UGATE

VLDOIN
Ipeak : 9A 21
PQW01 PAD
Imax : 6.3A AON7408L_DFN8-5 4 DL_1.35V 15 1
LGATE VTTGND
Iocp : 11A
C 14 2 C
FSW : 500KHz PLW03 1 PRW03 PGND VTTSNS
2
3
1UH_VMPI0703AR-1R0M-Z01_11A_20% 15K_0402_1% PUW00
1 2 1 2 CS_1.35V 13 3
+1.35VP PCW14 CS RT8207PZQW_WQFN20_3X3 GND
1

1U_0603_10V6K
5

1 2 12 4 VTTREF_1.35V
@EMI@ PRW02 PRW14 VDDP VTTREF
4.7_1206_5% 5.1_0603_5%

1
1 2 VDD_1.35V 11 5
1 2

VDD VDDQ

PGOOD
PQW02 +5VALW +1.35VP PCW10
SI7716ADN 4 0.033U_0402_16V7K

TON

2
1

FB
S5

S3
@EMI@ PCW02
680P_0402_50V7K PCW13
2

1U_0603_10V6K +5VALW

10

6
1
2
3

+1.35VP 1 2

EN_0.675VSP

FB_1.35V
TON_1.35V

EN_1.35V
PRW13 100K_0402_5% PRW10
8.06K_0402_1%
<5> DDR_PWROK PRW12 1 2 +1.35VP
510K_0402_1%
+1.35VP +1.35V 1.35V_B+ 1 2

1
PRW11
@ PRW04 10K_0402_1%
0_0402_5%

2
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1 2
<25> SYSON
1

1
PCW61

PCW62

PCW63

PCW64

PCW65

PCW66

PCW67

PCW68

1
@ PCW12
B 0.1U_0402_10V7K B
2

@ @

2
@PRW05
@ PRW05
0_0402_5%
1 2
<11,25,27,34> SUSP#

1
@ PCW11
@ PJW02 0.1U_0402_10V7K

2
+1.35VP 1 2 +1.35V
1 2
JUMP_43X118

@ PJW04
1 2
+0.675VSP 1 2 +0.675VS
JUMP_43X39

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/07/20 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR / VTT
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 32 of 41
5 4 3 2 1
5 4 3 2 1

Module model information Mark Green frame that means this part is not belong to layout module part .
SY8033_V1.mdd

Function Field :
D D

+1.8V Regulator 35.15


+1.8V Support 35.16 +1.0VALWP
+1.0V Regulator 35.27
Ipeak : 3A
+1.0V Support 35.28
@EMI@ PL1101
Imax : 2.1A
EMI Part 47.1 FBMA-L11-201209-121LMA50T_0805
1 2
Iocp : 4A
PU1100 PL1103
FSW : 1MHz

4
@ PJ1101 1UH_PCMB063T-1R0MS_12A_20%
+3VALW 1 2 10 2 +1.0VALWP_LX 1 2

PG
1 2 PVIN LX +1.0VALWP
JUMP_43X39 9 3

68P_0402_50V8J
PVIN LX @ PJ1103

1
@EMI@ PR1102
4.7_0603_5%
PC1110 8 1 2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
PC1112
22U_0603_6.3V6M SVIN +1.0VALWP 1 2 +1.0VALW

2
6 PR1111 JUMP_43X79

1
PC1105

PC1106

PC1107
5 FB 6.8K_0402_1%

2
EN

NC

NC
TP

2
PR1104

2
0_0402_5%

11

1
1 2 +1.0VALWP_ON FB_1.0VALWP
<25,31,33> POK

0.1U_0402_16V7K
1

1
680P_0402_50V7K
@EMI@ PC1102
SY8033BDBC_DFN10_3X3

1
PC1111
PR1105
1M_0402_5% PR1112
C 10K_0402_1% C
2

2
2

2
PC1811 +1.8VALWP
22U_0603_6.3V6M

1 2 Ipeak :1A
@ PJ1801
Imax : 0.7A
JUMP_43X79 Iocp : 2.5A
+3VALW 1 2 PU1800
1 2 SY8032ABC_SOT23-6 PL1803
1UH_PH041H-1R0MS_3.8A_20%
FSW : 1MHz
B 4 3 LX_1.8VALWP 1 2 B
IN LX +1.8VALWP
5 2

68P_0402_50V8J
PG GND @ PJ1803

22U_0603_6.3V6M

22U_0603_6.3V6M
6 1 1 2

1
PC1812
FB EN +1.8VALWP 1 2 +1.8VALW
1

1
PC1805

PC1806
PR1804 PR1811 JUMP_43X79
0_0402_5% @EMI@ PR1802 20K_0402_1%

2
1 2 +1.8VALWP_ON 4.7_0603_5%

2
<25,31,33> POK
0.1U_0402_16V7K

2
1

FB_1.8VALWP
1

PC1813

PR1805
1M_0402_1%

1
2

1
2

@ @EMI@ PC1802 PR1812


680P_0402_50V7K 10K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/13 Deciphered Date 2012/06/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.0VALW / +1.8VALW
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 33 of 41
5 4 3 2 1
5 4 3 2 1

Module model information Mark Green frame that means this part is not belong to layout module part .
SY8033_V1.mdd

Function Field :
D PCH11 +1.05VSP D
22U_0603_6.3V6M
+1.05V Regulator 35.25
1 2
Ipeak :1A
+1.05V Support 35.26
@ PJH01
@PJH01
Imax : 0.7A
+1.5V Regulator 35.31 JUMP_43X79
+3VALW 1 2 PUH00
Iocp : 2.5A
+1.5V Support 35.32 1 2 SY8032ABC_SOT23-6 PLH03
1UH_PH041H-1R0MS_3.8A_20%
FSW : 1MHz
EMI Part 47.1 4 3 LX_1.05VSP 1 2
IN LX +1.05VSP
5 2

68P_0402_50V8J
PG GND @ PJH02

22U_0603_6.3V6M

22U_0603_6.3V6M
6 1 1 2

1
PCH12
FB EN +1.05VSP 1 2 +1.05VS

1
PCH05

PCH06
PRH05 PRH10 JUMP_43X79
0_0402_5% @EMI@ PRH02 7.5K_0402_1%

2
1 2 +1.05VSP_ON 4.7_0603_5%

2
<11,25,27,32,34> SUSP#

0.1U_0402_16V7K

2
1
FB_1.05VSP

PCH10
PRH06
1M_0402_1%

1
2

1
2
@ @EMI@ PCH02 PRH11
680P_0402_50V7K 10K_0402_1%

2
C C

+1.8VALW +5VALW
1

+1.5VSP
1

PCM13
@PJM01
@ PJM01 1U_0402_6.3V6K
JUMP_43X79
2

Ipeak : 0.5A
2
2

Imax : 0.35A
PCM11 PUM00
Iocp : 4.2A
1

4.7U_0603_6.3VAK APL5930KAI-TRG_SO8
6
5 VCNTL 3
2

PRM04 9 VIN VOUT 4


VIN VOUT
100K_0402_5% +1.5VSP

1
1 2 +1.5V_EN 8 @ PJM02

1
<11,25,27,32,34> SUSP# 7 EN 2 +1.5V_FB 1 2
GND

PRM11 PCM14 +1.5VSP +1.5VS


POK FB 1.54K_0402_1% 0.01U_0402_25V7K 1 2
1

JUMP_43X79

2
1

1
@ PRM05
@PRM05 @ PCM12 PCM05
1

2
B 47K_0402_5% 0.1U_0402_16V7K 22U_0603_6.3V6M B
2

2
2

PRM12
1.74K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VS / +1.5VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 34 of 41
5 4 3 2 1
5 4 3 2 1

Module model information Mark Green frame that means this part is not belong to layout module part . CPU_B+
ISL95833-BTM_V1A.mdd for IC portion
ISL95833-BTM_V1B.mdd for SW portion

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
1

EMI@ PCZ18
@ PCZ35
1000P_0402_50V7K

1
<11> VGFX_VSNS

PCZ17

PCZ16
2
PRZ09

2
1
D
Function Field : VCORE_GSNS 0_0603_5% D
PCZ36 1 2UGATEG1-1
0.01UF_0402_25V7K

2
Regulator 36.1 UGATEG1
PCZ02 PRZ02 0.36uH DCR= 1.4±5% m ohm +SOC_VNN
Driver 36.2

1
0.1U_0402_25V4K 2.2_0603_5%
1 2 1 2

D1

D1

D1

G1
Support 36.3 BOOTG
PCZ31 PCZ33 PLZ04
120P_0402_50V8J 470P_0402_50V7K 0.22UH_PDME064T-R36MS_24A_20%
Output Cap 36.4 1 2 1 2 1 2 10 9 PHASEG 1 4
PCZ37 PRZ36 D1 D2/S1
Acoustic Cap 37.2 6800P_0402_25V7K PCZ32 499_0402_1% 2 3
PQZ03

G2
S2

S2

S2
1 2 1000P_0402_50V7K
EMI Part 47.1

1
2K_0402_1%
1 2 1 2 1 2 AON7934_DFN3X3A-8-10

560U_D2_2V_Y
PRZ38
@EMI@

8
1

1
1
PRZ33 PRZ35 PRZ05
Close GFX

PC624
+3VALW
137K_0402_1% 2.05K_0402_1% 4.7_1206_5% PRZ42 +
choke PRZ37 PRZ34 LGATEG 3.65K_0603_1%

1 2
1
221_0402_1% 2K_0402_1%
VSUMG- 1 2 @EMI@ 2

1 2

2
PRZ32 PCZ05

1
21K_0402_1% 680P_0402_50V7K

VSUMG+
0.033U_0402_25V7K

VSUMG-
PCZ34

2
0.1U_0402_25V6K
PHZ04 330P_0402_50V7K

2
11K_0402_1%
10K_0402_1%_B25/50 3370K

1.91K_0402_1%
2.61K_0402_1%

PCZ39

PCZ38
2
1

1
PRZ39
EMI@ PLZ01
PR15 and PR27
PRZ40

HCB2012KF-121T50_0805

2
BOOTG CPU_B+ 1 2
27.4K ohm for 100 degree 2
UGATEG1-1 EMI@ PLZ02
2

2
61.9K ohm for 110 degree VSUMG+ PHASEG
HCB2012KF-121T50_0805
1 2 B+

PRZ31
C C
Close GFX L/S MOS +5VALW

10U_0805_25V6K

10U_0805_25V6K
@EMI@ PCZ15
0.1U_0402_25V6
LGATEG 1 1

33

32

31

30

29

28

27

26

25
Alert assert PRZ11 @

1
PCZ14

PCZ13
27.4K_0402_1% + PCZ12 + PCZ11

threshold: 100C 1 2NTCG_1 100U_25V_M 100U_25V_M

ISUMPG

ISUMNG

RTNG

FBG

COMPG

PGOODG

BOOTG

UGATEG
PAD

1U_0402_6.3V6K

2
PHZ01 PRZ10 2 2

1
PCZ30
470K_0402_5%_B25/50 4700K 3.83K_0402_1%
1 2 1 2 NTCG 1 24 @ PRZ30 PRZ29
NTCG PHASEG 0_0402_5% 1_0402_5% PRZ08

2
1 2 2 23 0_0603_5%
<25> VR_ON VR_ON LGATEG
@ PRZ07 0_0402_5% UGATE1 1 2 UGATE1-1

2
2
1 2 VR_SVID_CLK_R 3 22
<8> VR_SVID_CLK SCLK VCCP
PRZ12 20_0402_1% PUZ00
VR_SVID_ALERT# 4 ISL95833BHRTZ-T_TQFN32_4X4 21 PCZ01 PRZ01 0.36uH DCR= 1.4±5% m ohm +SOC_VCC

1
<8> VR_SVID_ALERT# ALERT# VDD 0.1U_0402_25V4K 2.2_0603_5%
1 2 VR_SVID_DATA_R 5 20 1 2 1 2 BOOT1

D1

D1

D1

G1
<8> VR_SVID_DATA SDA PWM2
PRZ14 16.9_0402_1% PLZ03

1
6 19 LGATE1 PCZ29 0.22UH_PDME064T-R36MS_24A_20%
<25> VR_HOT# VR_HOT# LGATE1 1U_0402_6.3V6K 10 9 PHASE1 1 4
NTC 7 18 PHASE1 D1 D2/S1

1
NTC PHASE1
3.83K_0402_1%

For VR_HOT#, already 2 3


1

PGOOD

G2
PQZ01

S2

S2

S2
BOOT1
1 2 8 17 @EMI@
ISUMN
ISUMP

COMP
ISEN1

pull high at PWR side. ISEN2 UGATE1


PRZ17

AON7934_DFN3X3A-8-10 PRZ04
RTN
1

499_0402_1%

FB
73.2_0402_1%

73.2_0402_1%

560U_D2_2V_Y
@ PCZ20 @ PRZ43 4.7_1206_5%

8
1

1
1
47P_0402_50V8J 0_0402_5%

PC623
PRZ16

PRZ15

PRZ13

UGATE1-1 PRZ41 +
2

10

11

12

13

14

15

16
470K_0402_5%_B25/50 4700K

NTC_1 LGATE1 3.65K_0603_1%


BOOT1

1
+5VALW @EMI@ 2
2

2
1

PCZ04
PHZ02

PRZ18 680P_0402_50V7K

VSUM+
VGATE <25> +SOC_VCC +SOC_VNN

VSUM-
@ 27.4K_0402_1%
B +1.0VS B
1 2 +3VALW
2

EDP :12A EDP : 14A


1

@ PCZ19 VR_Hot# assert PRZ28


TDC : TBD TDC : TBD
0.1U_0402_16V7K
threshold: 100C 1.91K_0402_1%
2

Iocp : 18A Iocp : 18A


Close CPU L/S MOS FSW : 600KHz FSW : 600KHz
+SOC_VNN
PCZ40 PRZ23 PRZ27 +SOC_VCC
330P_0402_50V7K 2K_0402_1% 76.8K_0402_1% VSUM+ PC610 1 2 22U_0603_6.3V6M
1 2 1 2 1 2 PC600 1 2 22U_0603_6.3V6M PC611 1 2 22U_0603_6.3V6M

2.61K_0402_1%
PC601 1 2 22U_0603_6.3V6M PC612 1 2 22U_0603_6.3V6M

1
PC602 1 2 22U_0603_6.3V6M PC613 1 2 22U_0603_6.3V6M
11K_0402_1%

PRZ22
PC603 1 2 22U_0603_6.3V6M
1
2K_0402_1%

0.033U_0402_16V7K

PCZ22 PRZ24 PCZ21 +SOC_VNN


PRZ19

470P_0402_50V7K 499_0402_1% 120P_0402_50V8J


0.1U_0402_25V6K

1 2 1 2 1 2
2
1

1
191_0402_1%

PCZ27

PCZ28

+SOC_VCC
PRZ20

PC614 1 2 10U_0603_6.3V6M
2

PC604 1 2 22U_0603_6.3V6M PC615 1 2 10U_0603_6.3V6M


2

Package Edge Cap


PRZ21

PRZ25 PRZ26 PCZ23 PHZ03 PC616 1 2 10U_0603_6.3V6M


2
6800P_0402_25V7K

1.78K_0402_1% 137K_0402_1% 1000P_0402_50V7K 10K_0402_1%_B25/50 3370K


2
1
PCZ26

1 2 1 2 1 2
2

PC605 1 2 10U_0603_6.3V6M
2

PC617 1 2 1U_0402_6.3V6K
VSUM- PC606 1 2 4.7U_0603_10V6K PC618 1 2 1U_0402_6.3V6K
PC607 1 2 4.7U_0603_10V6K PC619 1 2 1U_0402_6.3V6K Back Side Cap
@ PCZ24
Close CPU choke PC608 1 2 2.2U_0402_6.3V6M
A 330P_0402_50V7K PC609 1 2 2.2U_0402_6.3V6M A
1 2
@ PC620 1 2 0.1U_0402_16V7K
@ PC621 1 2 0.1U_0402_16V7K
@ PC622 1 2 0.1U_0402_16V7K
<11> VCORE_VSNS
1 2

PCZ25
0.01UF_0402_25V7K Security Classification Compal Secret Data Compal Electronics, Inc.
<11> VCORE_GSNS Issued Date 2012/12/01 2013/07/10 Title
Deciphered Date
PWR-CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet 35 of 41
5 4 3 2 1
5 4 3 2 1

PWR PIR (Product Improve Record)


ZBWAA LA-B303P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1
GERBER-OUT DATE: 2013/10/29
NO DATE PAGE MODIFICATION LIST PURPOSE
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
D
Item Date Page Action Component Request D
-----------------------------------------------------------------------------------------------------------------------------------------------------------------

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-PIR
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 36 of 41
5 4 3 2 1
5 4 3 2 1

HW PIR (Product Improve Record)


ZBWAA LA-B303P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2
GERBER-OUT DATE: 2013/11/13
NO DATE PAGE MODIFICATION LIST PURPOSE
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
D
Item Date Page Action Component Request D
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
1) 11/13 7,9 Change change QC1,QC2,QC3 PN to SB00000S700 For PJE request
2) 11/13 25 delete RPB2 for 9022 design For EC
3) 11/13 10 delete RC73,RC76,RC77 bom structure 9012 requirement For 9022 design
4) 11/13 22 change QL1 PN from SB000009Q80 to SB00000S700 FOR common design
5) 11/13 24 delete RA15,RA16 bom structure unpop for audio common design FOR common design
6) 11/13 16 delete RT16 for repeat schematic FOR LVDS translator
7) 11/13 25 change UB2 name to UB1 For EC
8) 11/13 22 change NPCT420@ to TPM@ for TPM common design FOR common design
9) 11/13 24 change audio codec PIN9 voltage level from 3vs to 1.5vs FOR common design
10) 11/13 22 change LANCLK_REQ# pull high voltage from 3vs to 1.8vs FOR common design
11) 11/13 17 change R21,D4 bom structure to @ FOR common design
12) 11/13 17 change change U3 to U50 delete U50,R18 bom structure FOR common design
13) 11/15 10 change KBRST# to KB_RST# FOR common design
14) 11/16 16 add RT13 for lvds translator FOR common design
15) 11/16 17 swap L2 signal swap for layout route kiter FOR layout
16) 11/20 21 add R75 pull high BT_ON for 9022@ bom struction For 9022 design
17) 11/20 12 Delete RC63 for LPC 3.3V when is used VGA For bay tail m
C
18) 11/20 25 add H11 for stand-off FOR layout C
19) 11/22 10 Delete UC54,UC60,RC74,RC70 bom structure 9012@ for LPC 3.3V For bay trail m
20) 11/22 10 change change UC60 VCCA,EO valtage from 1.8valw to 1.8vs For bay trail m EDS
21) 11/22 25 Delete delete RB42,RB43 for LPC 3.3V when is used VGA For LPC
22) 11/23 24 Remove ALC233 co-lay component, now is for ALC233VB only FOR common design
23) 11/23 24 change Unify analog output net name to PR_L/PR_R FOR common design
24) 11/26 23 Modify usb hub 24 PIN and usb hub 28PIN co-lay FOR USB HUB
25) 11/28 18 add add U12, R145, C265, R186 for HDMI_HPD FOR HDMI
26) 11/26 26 Add Add H11 for stand-off For layout
27) 11/27 25 Change Delete RB42,RB43 for LPC 3.3V when is used VGA For LPC
28) 11/27 18 Add U12,R145,C265,R186 for HDMI_HPD For HDMI
29) 11/28 23 Change Hub usb 24 pin and 28 pin co-lay For cost
30) 11/28 22 Change change LAN/USB Small board connector pin For Lan/usb small board
31) 11/28 24 Change change CA15 material to 10V7K For audio codec
32) 11/28 17 add add D6 For bay tail m edp
33) 11/28 9 change usb port assignment OK For SW request
34) 11/29 8 delete delete D1 For RTC
35) 11/29 8 add add D16,D17 For RTC
36) 11/29 23 Modify change CR16,CR17,CR18 package 0603 to 0805 For common design
37) 11/29 8 add add CC19,CC21,D92 For ESD
B B
38) 11/30 6 add add RC35,RT14 For ENBKL
39) 11/30 27 add add R106 For commom design
40) 12/02 27 add add PJ11 For LD request
41) 12/03 17 add add R4283,R4282 on EMI camera choke For EMI
42) 12/03 17 change Change L2 from CAM_EMI@ to @CAM_EMI@ For EMI
43) 12/03 18 delete delete RY2 For common design
44) 12/03 27 change change PJ11 from 43x79 to 43x39 For common design
45) 12/04 23 change change GNDA to REXT_GND For USB HUB co-lay
46) 12/04 23 add add UR6,CR2,CR22,CR19,CR20,PJ12 FOR USB issue
47) 12/07 23 change change UR6,CR2,CR22,CR19,CR20 bom struction to @ FOR USB issue
48) 12/07 25 change change RB19 materail from 1k_0402_5% to 100k_0402_5% FOR EC_SWI#
49) 12/07 22,26 change change part number from L56,L57 to SM070003K00 FOR X1 code
50) 12/07 23 change change RR9 bom struction to HUB_28P FOR USB HUB
51) 12/07 25 delete delete CA2,CA6,CA9,CA10,CA11,CA22,UA1 bom structure FOR Common design

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 37 of 41
5 4 3 2 1
5 4 3 2 1

HW PIR (Product Improve Record)


ZBWAA LA-B303P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.3
GERBER-OUT DATE: 2014/1/10
NO DATE PAGE MODIFICATION LIST PURPOSE
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
D D

Item Date Page Action Component Request


-----------------------------------------------------------------------------------------------------------------------------------------------------------------
1) 12/27 23 Change change YR1 PN to SJ10000C210 For main source request
2) 12/27 8,17 Change change D4,D5,DC1,DC2,DC3,DC4,D6,D16,D17 PN to SCS00003500 For main source request
3) 12/27 8 delete delete R9 bom structure @ For RTC circuit
4) 12/27 8 add Add D17,R2 bom structure @ For RTC circuit
5) 12/27 24 change change CA28,CA29,CA30,CA31 bom structure to EMI@ For EMI request
6) 12/27 10 change change RC77 PN from SD028470180 to SD028220180 For SOC_SCI# issue verify
7) 12/27 9 add Add DC2,DC3 bom structure @ FOR USB_OC# issue verify
8) 12/27 17 add Add R431 bom structure TOUCH@ For touch screen circuit
9) 12/27 8 change change CC10,CC11 PN to SE071120J80 For HW Design change
10) 12/27 8 change change CC16,CC17 PN to SE071150J80 for HW Design change
11) 12/27 17,25 change change Q1,Q6,QB1 PN to SB000009Q80 for main source request
12) 12/27 18 change change QY1,QY2 PN to SB00000S700 for main source request
13) 12/27 14 remove remove XDP related materail for ESD team request
14) 12/27 8 add add RC38,RC39 for XDP for XDP circuit
15) 01/02 10 add add RC78,RC79 for slp_S3&S4 for HW Design change
16) 01/02 10 add add RC70,RC71 bom structure @ for HW Design change
C C
17) 01/02 10 add add RC79 bom structure 9012@ for HW Design change
18) 01/02 25 delete delete R107 for 9022 circuit
19) 01/03 8 change change CC19 net from PMC_PLTRST# to PLT_RST_BUF# for ESD team requst
20) 01/03 8 change change CC19 bom structure form @ESD@ to ESD@ for ESD team requst
21) 01/03 10 change change RC73,RC76 PN from SD028470180 to SD028220180 for HW design change
22) 01/03 27 add add C552 on +5VALW for ESD team requst
23) 01/04 8 add add RC40 for PMC_CORE_PWROK for RTC power consumption
24) 01/06 9 add add thermal sensor schematic for thermal team requst
25) 01/08 20 change change JFAN footprint to ACES_50271-0030N-001_3P for DFX team request
26) 01/08 8 add add RC41,RC65 for touch screen detect for signal name rule
27) 01/08 17 change change +LCD_ENVDD_R to LCD_ENVDD_R for common design request
28) 01/09 17 change change D29 bom structure @ESD@ to ESD@ for ESD team request
29) 01/09 24 change change UA1 compal PN from SA00007BF00 to SA00007BF10 for audio codec
30) 01/09 25 add add UB1 107 pin net 3VALW_PWREN for commond design request
31) 01/09 25 change change RB19 to 1k_0402_5% for LAN wake circuit
32) 01/10 9 add add bom structure thermal@ config for thermal sensor circuit
33) 01/10 8 change change RC38 value from 51_0402_5% to 200_0402_5% for XDP circuit requst

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 38 of 41
5 4 3 2 1
5 4 3 2 1

HW PIR (Product Improve Record)


ZBWAA LA-B303P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.4
GERBER-OUT DATE: 2014/01/24
NO DATE PAGE MODIFICATION LIST PURPOSE
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
Item Date Page Action Component Request
D ----------------------------------------------------------------------------------------------------------------------------------------------------------------- D

1) 01/24 8 Change change RC41 BOM Structure from Touch@ to @ For HW design change
2) 01/24 8 Change change RC65 Bom Structure from Notouch@ to @ For HW design change
3) 01/24 17 Add add R8 for touch screen For HW design change
4) 01/27 22 Add add R17 for Disable/Enable lan chip For power consumption
5) 01/27 20 change change JHDD footprint to LCN_ASF98-2231S10-0002_22P For DFB request
6) 01/28 17 Add add R30 for touch screen For HW design change
7) 01/28 23 Add add RR27,RR28 for usb_hub For HW design change
8) 01/28 23 Add add CR13 for 2nd source droop issue For common design
9) 01/28 25 Add add EC pin 18 net name RTC_TEST# For common design
10) 01/28 25 Add add EC pin 25 net name LAN_OFF# For common design
11) 01/28 25 Add add R31 for RTC_TEST# For common design
12) 02/11 17 Change change R4280,R4281 BOM structure from touch_EMI@ to EMI@ For Touch screen
13) 02/11 17 Change change L61 BOM structure from @touch_EMI@ to @EMI@ For Touch screen
14) 02/11 17 delete delete R431 BOM structure touch@ For Touch screen

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 07, 2014 Sheet 39 of 41
5 4 3 2 1
5 4 3 2 1

HW PIR (Product Improve Record)


ZBWAA LA-B303P SCHEMATIC CHANGE LIST
REVISION CHANGE: 1.0
GERBER-OUT DATE: 2014/03/03
NO DATE PAGE MODIFICATION LIST PURPOSE
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
D
Item Date Page Action Component Request D
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
1) 02/22 10 Change change RC78,RC79 value 4.7K_0402_5% to 10K_0402_5% For HW design change
2) 02/22 10 Add Add RC11,RC66 For HW design change
3) 02/22 27 Change change C549 PN from SE074271KL0 to SE074271k80 For HW design change
4) 02/22 8 Change change RP1 PN from SD309510A80 to SD309510A10 For HW design change
5) 02/22 24 delete delete RA13&RA18 For audio common design
6) 02/22 24 change change 0 ohm RA1,RA2,RA10,RA11,RA14,RA20.RA21 to short pad For audio common design
7) 02/22 23 Add add YR1 SJ10000DH00 for USB_HUB_28P For vender request
8) 02/22 10 change change UC59 BOM structure 9012@ to @ For HW design change
9) 02/24 22 Add Add Q10,RL5,RL6,CL1,CL2,CL3,CL4 for reserve circuit For Lan lost issue
10) 02/24 22 change change RL3 short pad to 0 ohm For HW design change
11) 02/25 26 change change SW2 BOM config from mount to un-mount For Pre-MP phase
12) 02/25 26 change change screw hole size for H1,H2,H3. For ME request
13) 02/26 17~ change change 0 ohm R3,RC55,RC60,RC61,RC62,R18,R4280,R4281.R4282,
R4283,R17,RR10,RR12,RR14,RR16,RR18,RR21,RR22,RR25,R29,RC14,
R431,R432,R26,RR6,RT1,R106,RM11 to short pad For 0 ohm short pad
14) 02/26 17 change change R30,R8 mount to un-mount For HW design change

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 03, 2014 Sheet 40 of 41
5 4 3 2 1
5 4 3 2 1

Power Sequence AC mode

G3->S0 S0->S3 S3->S0 S0->S5


ACIN
ACIN
+3VLP
+3VLP
EC_ON
EC_ON 1.53ms
D D
+3VALW
+3VALW 1.58ms

+5VALW
+5VALW
SPOK
SPOK 7.28ms

+1.0VALW
+1.0VALW 8.23ms

+1.8VALW
+1.8VALW

ON/OFF
ON/OFF 95.38ms

101ms EC_RSMRST#
EC_RSMRST#
101ms PBTN_OUT#
PBTN_OUT#
102ms
EC_SLP_S4#
EC_SLP_S4#
102ms
EC_SLP_S3#
EC_SLP_S3#
222ms 204ms
SYSON
SYSON 0.6ms
3.29ms
C
+1.35V C
+1.35V 1.71ms
3.29ms
33.68ms DDR_PWROK
DDR_PWROK 21ms 22.32ms 36.20ms

VR_ON
VR_ON 2.49ms 2.50ms
8.85ms 9.81ms
+SOC_VCC
+SOC_VCC 2.50ms 2.50ms
10.55ms 11.5ms
+SOC_VNN
+SOC_VNN 0.28ms 279us

VGATE
VGATE 42.56ms
263ms 11.71ms 5.57ms
SUSP#
SUSP# 31.28us 31.12us
2.56ms 2.18ms
+1.0VS
+1.0VS 1.30ms 1.29ms
1.56ms 1.52ms
+1.05VS
+1.05VS 1.84ms 1.83ms
8ms 8.12ms
+1.35VS
+1.35VS 2.79ms 2.8ms
10.71ms 10.71ms
+1.5VS
+1.5VS 2.11ms 2.08ms
16.59ms 16.63ms
+1.8VS
+1.8VS 3.77ms 3.77ms
15.31ms 15.34ms
+3VS
+3VS 4.41ms 4.41ms
B 20.48ms 20.27ms B
+5VS
+5VS 12.83ms 12.77ms
19.61ms 19.60ms
+0.675VS
+0.675VS 49.83ms 49.87ms
148.3ms
144ms KBRST#
KBRST# 110ms 110ms
11.71ms
PMC_CORE_PWROK
PMC_CORE_PWROK 110ms 110ms
11.71ms
DDR_CORE_PWROK
DDR_CORE_PWROK 116ms 116ms
584ms 8.8ms SUSP#
PMC_PLTRST#
PMC_PLTRST#
2.38ms

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/04/12 Deciphered Date 2014/04/12 Title
Power Sequence
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ZBWAA LA-B303P
Date: Monday, March 03, 2014 Sheet 41 of 41
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