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OUTPUT
GND
VDD
Note 1: Duplicate pins must both be connected for proper operation.
INPUT
GND
2: Exposed pad of the DFN package is electrically isolated.
VDD
TC4451
Inverting
140 μA
300 mV Output
Cross-Conduction
Reduction and Pre-Drive Output
Circuitry
Input TC4452
Non-Inverting
4.7V
GND
Effective
Input
C = 25 pF
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, TA = +25°C with 4.5V ≤ VDD ≤ 18V.
Parameters Sym Min Typ Max Units Conditions
Input
Logic ‘1’, High Input Voltage VIH 2.4 1.5 — V
Logic ‘0’, Low Input Voltage VIL — 1.3 0.8 V
Input Current IIN –10 — +10 μA 0V ≤ VIN ≤ VDD
Input Voltage VIN –5 — VDD + 0.3 V
Output
High Output Voltage VOH VDD – 0.025 — — V DC Test
Low Output Voltage VOL — — 0.025 V DC Test
Output Resistance, High ROH — 1.0 1.5 Ω IOUT = 10 mA, VDD = 18V
Output Resistance, Low ROL — 0.9 1.5 Ω IOUT = 10 mA, VDD = 18V
Peak Output Current IPK — 13 — A VDD = 18V
Continuous Output Current IDC 2.6 — — A 10V ≤ VDD ≤ 18V (Note 2, Note 3)
Latch-Up Protection IREV — >1.5 — A Duty cycle ≤ 2%, t ≤ 300 μs
Withstand Reverse Current
Switching Time (Note 1)
Rise Time tR — 30 40 ns Figure 4-1, CL = 15,000 pF
Fall Time tF — 32 40 ns Figure 4-1, CL = 15,000 pF
Propagation Delay Time tD1 — 44 52 ns Figure 4-1, CL = 15,000 pF
Propagation Delay Time tD2 — 44 52 ns Figure 4-1, CL = 15,000 pF
Power Supply
Power Supply Current IS — 140 200 μA VIN = 3V
— 40 100 μA VIN = 0V
Operating Input Voltage VDD 4.5 — 18.0 V
Note 1: Switching times ensured by design.
2: Tested during characterization, not production tested.
3: Valid for AT and MF packages only. TA = +25°C.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply with 4.5V ≤ VDD ≤ 18V.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range (V) TA –40 — +125 °C
Maximum Junction Temperature TJ — — +150 °C
Storage Temperature Range TA –65 — +150 °C
Package Thermal Resistances
Thermal Resistance, 5L-TO-220 θJA — 71 — °C/W Without heat sink
Thermal Resistance, 8L-6x5 DFN θJA — 33.2 — °C/W Typical 4-layer board with
vias to ground plane
Thermal Resistance, 8L-PDIP θJA — 125 — °C/W
Thermal Resistance, 8L-SOIC θJA — 155 — °C/W
220 300
200 47,000 pF
180 250
5V
160
Rise Time (ns)
FIGURE 2-1: Rise Time vs. Supply FIGURE 2-4: Fall Time vs. Capacitive
Voltage. Load.
300 40
VDD = 18V
Rise and Fall Times (ns)
250 5V tRISE
30
Rise Time (ns)
200 tFALL
10V
150 20
100
18V 10
50
0 0
100 1000 10000 100000 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
Capacitive Load (pF)
FIGURE 2-2: Rise Time vs. Capacitive FIGURE 2-5: Rise and Fall Times vs.
Load. Temperature.
-7
220 10
1E-07
Crossover Energy (A·sec)
200 47,000 pF
180
160
Fall Time (ns)
140
120 10 -8
1E-08
100 22,000 pF
80
60
40
20 10,000 pF -9
10
1E-09
0
4 6 8 10 12 14 16 18
4 6 8 10 12 14 16 18
Supply Voltage (V) Supply Voltage (V)
FIGURE 2-3: Fall Time vs. Supply FIGURE 2-6: Crossover Energy vs.
Voltage. Supply Voltage.
95 140
CLOAD = 15,000 pF
90
VIN = 5V 120
Propagation Delay (ns)
85 INPUT = High
80
IQUIESCENT (μA)
100
75
70
80
65
60 60
55
tD2
50 INPUT = Low
40
45 tD1
40 20
4 6 8 10 12 14 16 18 4 6 8 10 12 14 16 18
Supply Voltage (V) Supply Voltage (V)
FIGURE 2-7: Propagation Delay vs. FIGURE 2-10: Quiescent Supply Current
Supply Voltage. vs. Supply Voltage.
100 220
CLOAD = 15,000 pF VDD = 18 V
95 200
Propagation Delay (ns)
VDD = 10V
90 180 INPUT = High
85
IQUIESCENT (μA)
160
80
75 140
70 120
65 100
60 80 INPUT = Low
tD2
55
50
60
45 tD1 40
40 20
2 3 4 5 6 7 8 9 10 -40 -25 -10 5 20 35 50 65 80 95 110 125
Input Amplitude (V) Temperature (oC)
FIGURE 2-8: Propagation Delay vs. Input FIGURE 2-11: Quiescent Supply Current
Amplitude. vs. Temperature.
60 2
VDD = 10V
VDD = 12 V
1.9
Propagation Delay (ns)
55 VIN = 5V
1.8
Input Threshold (V)
CLOAD = 15,000 pF
1.7
50
1.6
VIH
45 1.5
tD2 1.4
40 1.3
1.2 VIL
35
tD1 1.1
30 1
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
o
Temperature ( C) Temperature (oC)
FIGURE 2-9: Propagation Delay vs. FIGURE 2-12: Input Threshold vs.
Temperature. Temperature.
2 300
VDD = 18 V
1.9 200 kHz
250
1.7 200
100 kHz
1.6
VIH
1.5 150 2 MHz
50 kHz
1.4
100
1.3 1 MHz 10 kHz
1.2 VIL 50
1.1
1 0
4 6 8 10 12 14 16 18 100 1,000 10,000 100,000
Supply Voltage (V) Capacitive Load (pF)
FIGURE 2-13: Input Threshold vs. Supply FIGURE 2-16: Supply Current vs.
Voltage. Capacitive Load (VDD = 18V).
4.0 300
VIN = 5V (TC4452)
VDD = 12 V 1 MHz
3.5 VIN = 0V (TC4451) 250
2.5
2.0 TJ = 125oC 150 100 kHz
1.5
100 2 MHz 50 kHz
1.0
o
TJ = 25 C 50 10 kHz
0.5
0.0 0
4 6 8 10 12 14 16 18 100 1,000 10,000 100,000
Supply Voltage (V)
Capacitive Load (pF)
3.0 175
VDD = 6 V 2 MHz
VIN = 0V (TC4452) 1 MHz
155
VIN = 5V (TC4451)
2.5
Supply Current (mA)
135
2.0 115 200 kHz
ROUT-LO (Ω)
o
95
1.5 TJ = 125 C 100 kHz
75
1.0 55
50 kHz
35
0.5 o
TJ = 25 C 10 kHz
15
0.0 -5
4 6 8 10 12 14 16 18 100 1,000 10,000 100,000
Supply Voltage (V) Capacitive Load (pF)
250 250
VDD = 18 V VDD = 6 V
15,000 pF
200
10,000 pF 15,000 pF
22,000 pF
150 1,000 pF 150
47,000 pF 22,000 pF
FIGURE 2-19: Supply Current vs. FIGURE 2-21: Supply Current vs.
Frequency (VDD = 18V). Frequency (VDD = 6V).
250
VDD = 12 V
15,000 pF
Supply Current (mA)
200
0.1 μF
50 470 pF
0
10 100 1000 10000
Frequency (kHz)
Pin No.
Pin No. Pin No.
8-Pin PDIP, Symbol Description
8-Pin DFN 5-Pin TO-220
SOIC
1 1 — VDD Supply input, 4.5V to 18V
2 2 1 INPUT Control input, TTL/CMOS-compatible input
3 3 — NC No connection
4 4 2 GND Ground
5 5 4 GND Ground
6 6 5 OUTPUT CMOS push-pull output
7 7 — OUTPUT CMOS push-pull output
8 8 3 VDD Supply input, 4.5V to 18V
— PAD — NC Exposed metal pad
— — TAB VDD Metal tab is at the VDD potential
+5V
90%
Input
VDD = 18V 10%
0V
tD1 tD2
tF tR
0.1 μF +18V
0.1 μF 4.7 μF 90% 90%
1 8 Output
VDD VDD 10% 10%
0V
Inverting Driver
Input 2 Input Output 6 Output TC4451
Output 7
CL = 15,000 pF +5V
90%
GND GND Input
4 5
10%
0V
+18V 90%
tD1 90% tD2
Input: 100 kHz, Output tR tF
square wave,
0V 10% 10%
tRISE = tFALL ≤ 10 ns
Non-Inverting Driver
Note: Pinout shown is for the DFN, PDIP and SOIC packages. TC4452
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Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
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10/31/05
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