Revolution in Electronic EDA Education/ Research: GOSPL

Rahul Sud and Megha Chaitanya

ST Microelectronics Pvt. Ltd.
Noida, India
Rahul-gva.sud@st.com
megha.chaitanya@st.com

Abstract ƒ Advanced FPGA architectural details for the

This paper discusses how GOSPL (Generalized
Open Source Programmable Logic), the world’s first
and only complete, commercially viable
hardware/software electronics platform is a dramatic
and major step forward in Semiconductor &
Electronic Design Automation Education/ Research
worldwide. Never before in the history of the world,
the work of 300 people over 5 years representing over
one million lines of EDA software code and
correspondingly programmable system on chip
Semiconductor IP Architecture have been made
available to the global University system. It allows
global education, research, innovation and
entrepreneurialism for universities to play
commercially viable EDA and VLSI IP game.
supported device, to understand the architecture
and to work on new architectural innovations
and enhancements.
ƒ Software User Manual, Coding Guidelines,
Design Documents etc.
ƒ Device Soft Model: Functional representation of
device.
2. GOSPL as a learning platform
The self-teaching capability of GOSPL provides a
learning opportunity based upon the analysis of
community projects and the GOSPL framework
encompass three complementary aspects namely
Learning, Experimentation & development and
Cooperation.

1. Introduction to GOSPL Platform

Software and hardware are two integral parts of a

GOSPL
FPGA.GOSPL platform offers both components of Platform Design
programmable logic and allows innovators to
experiment/enhance both software and hardware S/W Platform
together, which can lead to much higher degree of Synthesis
GOSPL Device
optimizations. Architecture Placer Configuration Bit
GOSPL platform is available via a globally Generator
Routing (Executable)
accessible web portal. The portal is envisaged to
Architecture Timing
become a global hub that will become single point to Capture Analysis
access all the important components of a SoC design
GUI
by the widespread community of users/ developers
from university as well as industry. The GOSPL Device Model
Platform comprises of the following components: (Executable)
ƒ Complete Source Code for FPGA Software
Tool Suite: Placer, Router, Synthesis and
Timing Analyzer and GUI. Programmable
ƒ Configuration bit generator in the executable Device

format that can link with the FPGA device

Figure 1. GOSPL Platform

Proceedings of the 2005 IEEE International Conference on Microelectronic Systems Education (MSE’05)
0-7695-2374-9/05 $20.00 © 2005 IEEE
 2.1.GOSPL Software as an EDA Learning
Platform
GOSPL provides a Complete FPGA
implementation toolset (Synthesis, Placement, Routing
and Timing Analysis) comprising close to one million
lines of fully functional C++ code with modular
framework and state of the art algorithms along with
an innovative FPGA device architecture.
With GOSPL, software developer has to deal with
different aspects of handling very large NP hard
problems, which is the most challenging part of any
EDA development.
2.2. GOSPL Architecture as an FPGA
learning Platform
The GOSPL architecture is symmetrical in nature
and is made up by replication of basic tiles. A tile
contains a logic block and associated routing (switch
box, connection box and IN mux).
Further research can be done on the combination of
different type of LUTs and cluster size with reduced
routing area and algorithms for the same. New
arithmetic techniques with reduced area and better
performance can be evaluated by GOSPL community.
2.3. GOSPL as an IP Integrator
GOSPL offers the user with a versatile
programmable fabric to port the soft IPs. This
programmable fabric can be easily integrated with a
generic bus interface which in turn can be used to
integrate the hard IPs which is compatible to this
generic bus interface. This novel approach will allow
the platform user to:
ƒ Initiate IP Development utilizing the strength of
the GOSPL community
ƒ Share developed IPs and invite improvements
from the GOSPL community
ƒ Build applications around GOSPL
programmable solution.
ƒ Innovate or suggest improvements in embedded
IP by just following the architecture guidelines
3. Courseware around GOSPL
Few of the renowned universities across the globe
have inducted GOSPL into their curriculum and their
courseware has been designed in synchronization with
GOSPL in consultation with the GOSPL community.
Beside this GOSPL has a rich knowledge resource in
form of GOSPL Knowledge Publications which
Proceedings of the 2005 IEEE International Conference on Microelectronic Systems Education (MSE’05)
0-7695-2374-9/05 $20.00 © 2005 IEEE
include various books and e-learning courses. The
objectives of Book Building/ e-Learning Courses is to
share knowledge, experience & analysis on the scantily
addressed topics so far and help proliferate the
programmable logic technology.
4. Licensing and Access details to GOSPL
The GOSPL source code access is web based, i.e
through the community portal. The source code for the
GOSPL platform is governed by a license on lines of
Open Source. After signing the license agreement, the
organization /individual is assigned the login &
password to the community portal.
Upon signing the license agreement, licensee
can start contributing to the existing projects or can
initiate his own project. Depending upon licensee’s
expertise and level of involvement, the licensee
assumes one of the several defined roles in GOSPL
projects.
5. Conclusion
GOSPL is a methodology to try and teach CAD related
courses to Microelectronic Community. The platform
gives academicians an insight to whole FPGA from
each perspective including software and architecture. It
will also give the opportunity to students to develop
specialized IPs.
6. Acknowledgements
The authors would like to thank 300 people who have
created this technology over 5 year’s effort.
Special thanks to the following people, who made
substantial and valuable contributions to this paper.
Prof.Narasimha B. Bhat, Manipal Dot Net Pvt. Ltd.
Mr Rajiv Kumar, ST Microelectronics
Ms Nidhi Chandra, ST Microelectronics
Mr Mayank Jain , ST Microelectronics
Ms Tulika Gupta , ST Microelectronics
Mr Parvesh Swami, ST Microelectronics
Mr Kailash Digari, ST Microelectronics
Mr Danish Hasan Syed, ST Microelectronics
Mr Md. Bader Alam, ST Microelectronics
Mr Nimit Endlay, ST Microelectronics
7. References
[1] www.gospl.org