Pci Express Gen4 Retimer Supplemental Features PDF

PCI Express* (PCIe*) 4.
0 Retimer
Supplemental Features and Standard
BGA Footprint
Revision 004
June 2018
Document Number: 336467-004US

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2 PCI Express* (PCIe*) 4.0 Retimer Supplemental Features and Standard BGA Footprint
June 2018
Contents
1 Introduction .............................................................................................................. 6
1.1 Overview ........................................................................................................... 6
1.2 Terminology ....................................................................................................... 8
1.3 Specification References....................................................................................... 8
1.4 Retimer Supplemental Features Beyond PCIe 4.0 Specification .................................. 9
1.4.1 Link Subdivision ....................................................................................... 9
2 Mechanical Specification.......................................................................................... 10
2.1 Overview ......................................................................................................... 10
3 Signal Description ................................................................................................... 11
3.1 x16 Retimer Interface Signals ............................................................................. 12
3.1.1 Signal Descriptions ................................................................................. 17
3.2 x16 Retimer Ballmap (Package Side).................................................................... 18
3.3 x16 Retimer Ballmap (Platform Side) ................................................................... 19
3.4 x16 Retimer, Physical Ballmap (Package Side)....................................................... 20
3.5 x16 Retimer Platform Side Land Pattern ............................................................... 21
3.6 x8 Retimer Interface Signals ............................................................................... 21
3.7 x8 Retimer Ballmap (Package Side) ..................................................................... 25
3.8 X8 Retimer Ballmap (Platform Side) ..................................................................... 26
3.9 x8 Retimer, Physical Ballmap (Package Side) ........................................................ 27
3.10 x8 Retimer Platform Side Land Pattern ................................................................. 28
3.11 x4 Retimer Interface Signals ............................................................................... 28
3.12 x4 Retimer Ballmap (Package Side) ..................................................................... 31
3.13 x4 Retimer Ballmap (Platform Side) ..................................................................... 32
3.14 x4 Retimer, Physical Ballmap (Package Side) ........................................................ 33
3.15 X4 Retimer Platform Side Land Pattern................................................................. 34
4 Electrical Characteristics ......................................................................................... 35
4.1 Absolute Maximum Ratings ................................................................................. 35
4.2 Power Consumption ........................................................................................... 35
4.3 Power Supply Decoupling ................................................................................... 36
4.4 Retimer Latency ................................................................................................ 36
4.5 Package Thermal Considerations ......................................................................... 36
5 SMBus and EEPROM ................................................................................................. 37
6 BGA Footprint Register Configuration ...................................................................... 38
6.1 SMBus Address Range........................................................................................ 38
6.2 SMBus Command Formats .................................................................................. 38
6.3 SMBus Block Read/Write Examples ...................................................................... 39
6.3.1 Read Vendor ID (Implemented Using Block Read with Repeat START) ........... 40
6.3.2 Write 16G Preset (P7) for Downstream Pseudo Port .................................... 40
6.3.3 Enable SRIS (Implemented Using Block Write with Repeat START)................ 40
6.4 Global Parameter Register 0 ............................................................................... 41
6.5 Global Parameter Register 1 ............................................................................... 44
6.6 Physical Pseudo Port 0 Parameter Register 0 ......................................................... 44
6.12 Register Offsets for Different Link Subdivision (Bifurcation) ..................................... 52
PCI Express* (PCIe*) 4.0 Retimer Supplemental Features and Standard BGA Footprint 3
June 2018
Figures
1-1 Platform Configuration with an Add-in Card and Retimer on Mother Board .................. 6
1-2 Platform Configuration with an Add-in Card and Riser, Retimer on Riser ..................... 7
1-3 Platform Configuration with a Riser and Cable, Retimer is on Riser ............................ 7
1-4 Platform Configuration with a Backplane, Retimer on Both Mother Boards................... 7
2-1 Retimer Form Factors .........................................................................................10
3-1 x16 Retimer Block Diagram .................................................................................11
3-2 x16 Retimer, Package Side Pin Arrangement (Top View) .........................................18
3-3 x16 Retimer, Platform side Pin Arrangement (Top View)..........................................19
3-4 x16 Retimer, Physical Ballmap on Package (Top View) ............................................20
3-5 x16 Retimer, Platform Side Land Pattern with Spacing Details (Top View)..................21
3-6 x8 Retimer, Package-Side Pin Arrangement (Top View) ...........................................25
3-7 x8 Retimer, Platform-Side Pin Arrangement (Top View)...........................................26
3-8 x8 Retimer, Physical Ballmap on Package (Top View) ..............................................27
3-9 x8 Retimer, Platform-Side Land Pattern with Spacing Details (Top View) ...................28
3-10 x4 Retimer, Package-Side Pin Arrangement (Top View) ...........................................31
3-11 x4 Retimer, Platform-Side Land Pattern (Top View) ................................................32
3-12 x4 Retimer, Physical Ballmap on Package (Top View) ..............................................33
3-13 x4 Retimer, Platform-Side Land Pattern with Spacing Details (Top View) ...................34
6-1 Slave SMBus Command Code Format ...................................................................38
Tables
1-1 Abbreviations ..................................................................................................... 8
1-2 Retimer Feature Comparison ................................................................................ 9
3-1 x16 Retimer Signal Descriptions ..........................................................................12
3-2 x8 Retimer Signal Descriptions ............................................................................21
3-3 x4 Retimer Signal Descriptions ............................................................................28
4-1 Absolute Maximum Voltage Ratings ......................................................................35
4-2 Recommended Absolute Maximum Power Ratings ..................................................35
6-1 SMBus Address bits Mapping ...............................................................................38
6-2 Slave SMBus Command Code Fields .....................................................................39
6-3 START and END Bit Usage for Command Code .......................................................39
6-4 Global Parameter Register 0 Description ...............................................................42
6-5 Global Parameter Register 1 Description ...............................................................44
6-6 Physical Pseudo Port 0 Parameter Register 0 Description .........................................45
6-7 Physical Pseudo Port 0 Parameter Register 1 .........................................................46
6-12 Register Offsets.................................................................................................52
4 PCI Express* (PCIe*) 4.0 Retimer Supplemental Features and Standard BGA Footprint
June 2018
Revision History
Document Revision
Description Date
Number Number
336467 001 • Initial Release November 2017
• Updated the register configuration section to define 32-bit registers

instead of 8-bit registers.
• Updated proposed register offset map to include vendor defined registers,
reserved registers, and 16-bit addressing.
• Added SMBus Command Code definition and examples.
• Made REFCLK_OUT a required feature.
336467 002 February 2018
• Changed names for the SMB_ADDR pins from (0,1,2) to (1,2,3).
• Updated the specification reference list to include the PCIe* Base
Specification Rev 4.0, Ver 1.0.
• Updated support for EEPROM configuration load to Optional.
• Added Link Subdivision details.
• Added frequency requirements for SMBus implementation.
336467 003 • Correct PCI Express naming. March 2018
• X16 Retimer Interface signals, changed pin FJ3 description to “data”

• X16 Retimer Interface signals, changed pin FF5 description to “clock”
• X8 Retimer Interface signals, changed pin AP11 to “EE_CLK”
• X8 Retimer Interface signals, changed pin AP13 to “EE_DAT”
• X8 Retimer Interface signals, removed VD_12 signal from miscellaneous
section
• X8 Retimer Interface signals, Receiver differential pair, B channel, Lane 3,
“p” pin changed to “U2”
• X8 Retimer Interface signals, corrected signal name to
“SMB_ADDR_3/VD_12”
336467 004 • X4 Retimer Interface signals, changed pin U8 description to “data”, June 2018
• X4 Retimer Interface signals, changed pin N8 description to “clock”
• X4 Retimer Interface signals, updated pin A5 to VD_5
• X4 Retimer Interface signals, updated pin U8 to EE_DAT/VD_7
• X4 Retimer Interface signals, updated pin N8 to EE_CLK/VD_8
• X4 Retimer Interface signals, updated pin C8 to VD_9
• X4 Retimer Interface signals, updated pin W9 to SMB_ADDR_3/VD_10
• X4 Retimer Interface signals, updated pin A10 to VD_6
• Renamed a few sections between 3.2 and 3.15 to maintain naming
consistency
PCI Express* (PCIe*) 4.0 Retimer Supplemental Features and Standard BGA Footprint 5
June 2018
1 Introduction
1.1 Overview
PCI Express* (PCIe*) 4.0 capable retimers extend the channel reach on a platform to
beyond what is possible otherwise.
With PCI Express 4.0 (16 GT/s), data rate has increased by 2x compared to previous
generation (8 GT/s), resulting in shorter channel reach. Common use cases include
channels expanding over system boards, backplanes, cables, risers, and add-in cards.
Such long channels can have loss that far exceeds the spec loss target of -28 dB at 8
GHz. Retimer is now part of the PCI Express 4.0 Base Specification. PCI-SIG* is
expected to implement compliance program for testing retimers.
It is expected that significant number of platforms using PCI Express 4.0 will require
retimers. Multiple sources of retimers will make adoption of PCIe 4.0 technology easier.
Common footprint simplifies the platform design process. Pinout is optimized for
16 GT/s signal integrity and thermal challenges.
Figure 1-1 to Figure 1-4 show few example configurations involving riser, mother board
and add-in card. Various other configurations are possible.
Figure 1-1. Platform Configuration with an Add-in Card and Retimer on Mother Board
6 PCIe Express* (PCIe*) 4.0 Retimer Supplemental Features and Standard BGA Footprint
June 2018
Figure 1-2. Platform Configuration with an Add-in Card and Riser, Retimer on Riser
Figure 1-3. Platform Configuration with a Riser and Cable, Retimer is on Riser
Figure 1-4. Platform Configuration with a Backplane, Retimer on Both Mother Boards
PCIe Express* (PCIe*) 4.0 Retimer Supplemental Features and Standard BGA Footprint 7
June 2018
1.2 Terminology
The “#” symbol at the end of a signal name indicates that the active or asserted state
occurs when the signal is at a low voltage level. When “#” is not present after the
signal name, the signal is asserted when the signal is at a high voltage level.
The following notations are used to describe the various signal types.
Table 1-1. Abbreviations

Term Description
I Input
O Output
I/O Bi-Directional
PU Pull-up
PWR Power
GND Ground
Host This term is synonymous with platform or system
NC No Connect
VD Vendor Defined
SSC Spread Spectrum Clocking
SRIS Separate Reference Clock Independent SSC
RX PCIe Receiver
TX PCIe Transmitter
N/A Not Applicable
1.3 Specification References

This specification requires references to other specifications or documents that will
form the basis for some of the requirements stated herein.
• PCI Express Card Electromechanical (CEM) Specification, Revision 4.0, Version 0.5,
December 18, 2015
• PCI Express Base Specification, Revision 4.0, Version 1.0, October 5, 2017
• System Management Bus (SMBus) Specification, Version 2.0, August 3, 2000
• JTAG Specification (IEEE* 1149.1)
• I2C* BUS Specifications, Version 2.1, January 2000
June 2018
1.4 Retimer Supplemental Features Beyond PCIe 4.0
Specification
Table 1-2. Retimer Feature Comparison

PCIe 4.0 for Retimers Supplemental
PCIe 4.0 Base Specification
Feature Features and Standard BGA Footprint
for Retimers
Specification
SRIS Optional Required
Slave Loopback Optional Required
Receiver Lane Margining (Voltage) Optional Required
Not defined explicitly but can be Required

Link Subdivision(1) (Bifurcation)
supported
L1PM Substates(2) Optional Required
SMBus Programmable Configurations N/A Required
Support for EEPROM load configuration N/A Optional
Retimer Common (size, pinout) Footprint N/A Required
Reference Clock Out N/A Required
Notes:
1. Link subdivision should be implemented such that no power reset is required.
2. L1PM Substate support for retimers as defined in Section 4.3.10 in the PCIe Base Specification.
1.4.1 Link Subdivision

Link Subdivision (also known as bifurcation) is dividing a PCIe Link into a certain
number of independent links. Each of the sub divided links behave as an independent
PCIe link and is required is follow the PCIe Link requirements. For example, each of
these subdivided links should support defaulting to x1 Link width if the link cannot be
trained at the required link width.
The host updates the Global Parameter register in the retimer with required link
subdivision using SMBus commands. Refer to Section 6.2 and Section 6.4.
A host is required to issue a warm reset to the retimer to retrain the link with updated
link subdivision settings.
June 2018
2 Mechanical Specification
2.1 Overview
Three different retimer package sizes are specified.
• x4: Supports 4 lanes in upstream direction and 4 lanes in downstream direction
The following figure shows the overall package dimensions for the three retimer form
factors.
Note: All the dimensions are in mm and the tolerance is ±0.15 mm.
Figure 2-1. Retimer Form Factors
June 2018
3 Signal Description
This chapter provides a detailed description of retimer signals. The signal descriptions
are arranged in functional groups according to their associated interface.
Signal directions in Table 3-1, “x16 Retimer Signal Descriptions”, Table 3-2, “x8
Retimer Signal Descriptions” and Table 3-3, “x4 Retimer Signal Descriptions” are from
retimer perspective. That is, “O” indicates output from the retimer device and “I”
indicates input to the retimer device.
Signals labeled “VD” are Vendor Defined. It is required that VD balls carry signals that
are not critical to retimer basic functionality and are used for providing enhanced or
debug features.
Common footprint for following link widths are defined for the PCIe 16 GT/s retimers:
1. x16 (link with 16 physical lanes)
The following figure shows the x16 retimer block diagram. Channel A and Channel B
are ports that can be configured to be upstream or downstream.
Figure 3-1. x16 Retimer Block Diagram
June 2018
3.1 x16 Retimer Interface Signals
The following table lists pin numbers and functions for each of the pins in the x16
pinout, along with voltage level wherever applicable.
Table 3-1. x16 Retimer Signal Descriptions (Sheet 1 of 5)

Signal
Pin# Signal Name Signal Description Voltage Level
Direction
High Speed Differential I/O
M26 A_PETp0 O
Transmitter differential pair, A Channels, Lane 0
P29 A_PETn0 O
W26 A_PETp1 O
AA29 A_PETn1 O
AF26 A_PETp2 O
AH29 A_PETn2 O
AN26 A_PETp3 O
AR29 A_PETn3 O
AY26 A_PETp4 O
BB29 A_PETn4 O
BG26 A_PETp5 O
BJ29 A_PETn5 O
BP26 A_PETp6 O
BT29 A_PETn6 O
CA26 A_PETp7 O
CC29 A_PETn7 O
CH26 A_PETp8 O
CK29 A_PETn8 O
CR26 A_PETp9 O
CU29 A_PETn9 O
DB26 A_PETp10 O
DD29 A_PETn10 O
DJ26 A_PETp11 O
DL29 A_PETn11 O
DT26 A_PETp12 O
DV29 A_PETn12 O
EC26 A_PETp13 O
EE29 A_PETn13 O
EK26 A_PETp14 O
EM29 A_PETn14 O
EU26 A_PETp15 O
EW29 A_PETn15 O
N34 B_PERp0 I
Receiver differential pair, B Channels, Lane 0
R35 B_PERn0 I
Y34 B_PERp1 I
AB35 B_PERn1 I
June 2018
Signal
Direction
AG34 B_PERp2 I
AJ35 B_PERn2 I
AP34 B_PERp3 I
AT35 B_PERn3 I
BA34 B_PERp4 I
BC35 B_PERn4 I
BH34 B_PERp5 I
BK35 B_PERn5 I
BR34 B_PERp6 I
BU35 B_PERn6 I
CB34 B_PERp7 I
CD35 B_PERn7 I
CJ34 B_PERp8 I
CL35 B_PERn8 I
CT34 B_PERp9 I
CV35 B_PERn9 I
DC34 B_PERp10 I
DE35 B_PERn10 I
DK34 B_PERp11 I
DM35 B_PERn11 I
DU34 B_PERp12 I
DW35 B_PERn12 I
ED34 B_PERp13 I
EF35 B_PERn13 I
EL34 B_PERp14 I
EN35 B_PERn14 I
EV34 B_PERp15 I
EY35 B_PERn15 I
R1 A_PERp0 I
Receiver differential pair, A Channels, Lane 0
N2 A_PERn0 I
AB1 A_PERp1 I
Y2 A_PERn1 I
AJ1 A_PERp2 I
AG2 A_PERn2 I
AT1 A_PERp3 I
AP2 A_PERn3 I
BC1 A_PERp4 I
BA2 A_PERn4 I
BK1 A_PERp5 I
BH2 A_PERn5 I
June 2018
Signal
Direction
BU1 A_PERp6 I
BR2 A_PERn6 I
CD1 A_PERp7 I
CB2 A_PERn7 I
CL1 A_PERp8 I
CJ2 A_PERn8 I
CV1 A_PERp9 I
CT2 A_PERn9 I
DE1 A_PERp10 I
DC2 A_PERn10 I
DM1 A_PERp11 I
DK2 A_PERn11 I
DW1 A_PERp12 I
DU12 A_PERn12 I
EF1 A_PERp13 I
ED2 A_PERn13 I
EN1 A_PERp14 I
EL2 A_PERn14 I
EY1 A_PERp15 I
EV2 A_PERn15 I
M7 B_PETp0 O
Transmitter differential pair, B Channels, Lane 0
P10 B_PETn0 O
W7 B_PETp1 O
AA10 B_PETn1 O
AF7 B_PETp2 O
AH10 B_PETn2 O
AN7 B_PETp3 O
AR10 B_PETn3 O
AY7 B_PETp4 O
BB10 B_PETn4 O
BG7 B_PETp5 O
BJ10 B_PETn5 O
BP7 B_PETp6 O
BT10 B_PETn6 O
CA7 B_PETp7 O
CC10 B_PETn7 O
CH7 B_PETp8 O
CK10 B_PETn8 O
CR7 B_PETp9 O
CU10 B_PETn9 O
June 2018
Signal
Direction
DB7 B_PETp10 O
DD10 B_PETn10 O
DJ7 B_PETp11 O
DL10 B_PETn11 O
DT7 B_PETp12 O
DV10 B_PETn12 O
EC7 B_PETp13 O
EE10 B_PETn13 O
EK7 B_PETp14 O
EM10 B_PETn14 O
EU7 B_PETp15 O
EW10 B_PETn15 O
Reference Clock
FJ16 REFCLK+ I
100 MHz. Reference Clock (Differential Pair) to be

used in Common Clock configuration, as defined
FF18 REFCLK- I by the PCIe Base Specification
100 MHz. This pin is used for driving

B16 REFCLK_Out+ (2) O
REFCLK_out+

E18 REFCLK_Out1 (2) O
REFCLK_out -
PCI Express Auxiliary Signals
Fundamental Reset; Active

F2 PERST# I 1.8V (3.3V tolerant)
Low
G35 CLKREQ# I Used by L1PM Substates; Active Low 1.8V (3.3V tolerant)
JTAG
B6 JTAG_TDI I JTAG Test Data In 1.8V (3.3V tolerant)
JTAG Test Data Out; Open drain; Require pull up

on the platform; Pull up voltage must be selected
B9 JATG_TDO O
based on the I/O voltage selected for other JTAG
signals
B12 JTAG_TMS I JTAG Test Mode Select 1.8V (3.3V tolerant)
B3 JTAG_TCK I JTAG Clock 1.8V (3.3V tolerant)
E8 JTAG_TRST# I JTAG Reset; Active Low 1.8V (3.3V tolerant)
June 2018
Signal
Direction
System Management Bus (SMBus)
B31 SMBCLK I/O SMBus Clock Input / Open Drain Clock Output 1.8V (3.3V tolerant)
SMBus Data Input / Open

B28 SMBDAT I/O 1.8V (3.3V tolerant)
Drain Output
F34 SMB_ADDR_1 I SMBus Address Bit1 1.8V (3.3V tolerant)
B23 SMB_ADDR_2 I SMBus Address Bit2 1.8V (3.3V tolerant)
SMB_ADDR_3/
B25 I SMBus Address Bit3 or Vendor Defined 1.8V (3.3V tolerant)
VD_16(1)
EEPROM Configuration Interface
FJ3 EE_DAT/VD_7(1) I/O EEPROM Interface Data or Vendor Defined 1.8V (3.3V tolerant)
FF5 EE_CLK/VD_8(1) I/O EEPROM Interface Clock or Vendor Defined 1.8V (3.3V tolerant)
Miscellaneous
FJ23 VD_1(1) TBD Vendor Defined Signal
FF24 VD_2(1) TBD Vendor Defined Signal
G1 VD_15(1) TBD Vendor Defined Signal
E11 RX_DET_BYP I Receiver Detection Bypass
Power
6 pins PWR_1 Power Rail 1 1.8V or 3.3V
24 pins PWR_2 Power Rail 2 1.1V or 1.0V or 0.9V or 0.8V
152pins GND 0V
Notes:
1. It is safe to route high speed Vendor Defined (VD) signals at these locations. Care must be taken to provide enough GND
isolation. Retimer vendors are recommended to do a thorough signal integrity analysis when using any of the VD pins.
2. REFCLK Out is compliant with REFCLK definition in the PCIe Base Specification.
June 2018
3.1.1 Signal Descriptions
3.1.1.1 SMBus Interface
SMBCLK, SMBDAT and three address pins (SMB_ADDR_1, SMB_ADDR_2,
SMB_ADDR_3) are assigned in the ballmap. Three address bits are required to address
retimers on the SMBus in a platform configuration. Retimer vendors are allowed to take
care of SMBus address needs on the platform by using only two address pins, if they
can take care of additional addresses needed by the platform in a proprietary way. The
retimer vendors can use the third address bit for Vendor Defined purposes in that case.
Address pin SMB_ADDR_3 can be used for Vendor Defined signal.
SMBus implementation is required to support 100 kHz and be 400 kHz compatible.
3.1.1.2 EEPROM Interface

EECLK and EEDAT signals are defined to load initial configuration from an external
EEPROM. No specific interface is mentioned, giving retimer vendors freedom to use the
interface of their choice. An example of the interface that can be used is I2C.
When this dedicated interface is not used for EEPROM load, and some other means are
used to load EEPROM configuration, these pin can be used as Vendor Defined.
3.1.1.3 Miscellaneous Signals
3.1.1.3.1 RX_DET_BYP (PCIe_BYPASS_MODE)
This signal is asserted to bypass the receiver detection process to expedite the link
training. In this mode, the retimer does not do any active determination of its receiver
impedance. It rather assumes that the receiver is present on the other end of the link.
This feature can be used for soldered-down devices. The same signal when asserted,
also serves to bypass the PCIe mode.
3.1.1.3.2 REFCLK_Out+/REFCLK_Out-
This is the 100 MHz reference clock as defined by the PCIe Base Specification. Retimer
devices are required to provide this clock output to ease clock routing complexities on
the platform.
3.1.1.3.3 PERST#
Fundamental Reset signal as defined by the PCIe Base Specification.
3.1.1.3.4 CLKREQ#
This signal is used to support L1PM Substates. Refer to the PCIe Base Specification for
more details on L1PM Substate support for retimers.
June 2018
3.2 x16 Retimer Ballmap (Package Side)
The following figure shows the ball arrangement from the retimer package side. Note
that this figure is for reference only, for actual pin number and spacing details, refer to
Figure 3-5, “x16 Retimer, Platform Side Land Pattern with Spacing Details (Top View)”
on page 21.
Figure 3-2. x16 Retimer, Package Side Pin Arrangement (Top View)
CP CN CM CL CK CJ CH CG CF CE CD CC CB CA BY BW BV BU BT BR BP BN BM BL BK BJ BH BG BF BE BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER
1 GND
p15
GND
p14
GND
p13
GND
p12
GND
p11
GND
p10
GND
p9
GND
p8
GND
p7
GND
p6
GND
p5
GND
p4
GND
p3
GND
p2
GND
p1
GND
p0
GND VD _15 1
NC NC NC
A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER A_PER
2 GND
n15
GND
n14
GND
n13
GND
n12
GND
n11
GND
n10
GND
n9
GND
n8
GND
n7
GND
n6
GND
n5
GND
n4
GND
n3
GND
n2
GND
n1
GND
n0
GND PERST# 2
NC NC NC
EE_DAT JTAG_T
3 /VD_7
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
CK 3
EE_CLK/
4 VD_8 4
B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp JTAG_T
5 VD_3 GND
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DI 5
JTAG_T
6 VD_4
RST# 6
B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn JTAG_T
7 VD_5 GND
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DO
7
RX_DET
8 VD_6
_B YP 8
JTAG_T
9 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
MS 9
10 GND GND 10
REFCLK REFCLK
11 +
GND
_Out+ 11
PWR_2 PWR_2 PWR_2 PWR_2 PWR_2 PWR_2 PWR_1 PWR_1 PWR_1 PWR_2 PWR_2 PWR_2 PWR_2 PWR_2 PWR_2
REFCLK
12 REFCLK-
_Out- 12
13 GND GND GND GND 13

14 GND 14
SM B_A
15 VD_1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
DDR _2 15
16 VD_2 16
A_PETp A_PETp A_PETp A_PETp A_PETp A_PETp A_PETp A_PETp A_PETp A_PETp A_PETp A_PETp A_PETp A_PETp A_PETp A_PETp SM B_A
17 VD_9 GND
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDR_3/ 17
VD_16
18 VD_10 GND 18
A_PETn A_PETn A_PETn A_PETn A_PETn A_PETn A_PETn A_PETn A_PETn A_PETn A_PETn A_PETn A_PETn A_PETn A_PETn A_PETn
19 VD_11 GND
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBDAT 19
20 VD_12 GND 20
21 VD_13 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SMBCLK 21
22 VD_14 GND 22
B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp SM B_A
23 GND
15
GND
14
GND
13
GND
12
GND
11
GND
10
GND
9
GND
8
GND
7
GND
6
GND
5
GND
4
GND
3
GND
2
GND
1
GND
0
GND
DDR _1 23
NC NC NC
B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn CLKREQ
24 GND
15
GND
14
GND
13
GND
12
GND
11
GND
10
GND
9
GND
8
GND
7
GND
6
GND
5
GND
4
GND
3
GND
2
GND
1
GND
0
GND
# 24
NC NC NC
Note: Refer to Figure 3-5, “x16 Retimer, Platform Side Land Pattern with Spacing Details (Top View)” on page 21 for pitch and
spacing details.
Legend
PWR_1
PWR_2
GND
Control and VD Signals
Differential TX
Differential RX
No Balls
NC
June 2018
3.3 x16 Retimer Ballmap (Platform Side)
The following figure shows the platform side pin arrangement with PCB vias. The TX
and RX balls here have been swapped when compared to package side ballmap
(Figure 3-2). That is, “TX lane x” in package side ballmap gets mapped to “RX lane x”
in the land pattern.
Note that this figure is for reference only; for actual pin number and spacing details,
refer to Figure 3-5, “x16 Retimer, Platform Side Land Pattern with Spacing Details (Top
View)” on page 21.
Figure 3-3. x16 Retimer, Platform side Pin Arrangement (Top View)
A_PETp A_PETp A _PETp A_PETp A_PETp A _PETp A_PETp A_PETp A _PETp A_PETp A_PETp A _PETp A_PETp A_PETp A_PETp A_PETp
1 GND
15
GND
14
GND
13
GND
12
GND
11
GND
10
GND
9
GND
8
GND
7
GND
6
GND
5
GND
4
GND
3
GND
2
GND
1
GND
0
GND VD_15 1
NC NC NC
A_PETn A_PETn A_PETn A_PETn A _PETn A_PETn A_PETn A _PETn A_PETn A_PETn A _PETn A_PETn A_PETn A _PETn A_PETn A_PETn
2 GND
15
GND
14
GND
13
GND
12
GND
11
GND
10
GND
9
GND
8
GND
7
GND
6
GND
5
GND
4
GND
3
GND
2
GND
1
GND
0
GND PERST# 2
NC NC NC
EE_DAT JTAG_T
3 /VD_7
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
CK 3
EE_CLK/
4 VD_8 4
B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp B_PERp JTAG_T
5 VD_3 GND
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DI 5
JTAG_T
6 VD_4
RST# 6
B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn B_PERn JTAG_T
7 VD_5 GND
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DO 7
RX_DET
8 VD_6
_BYP 8
JTAG_T
9 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
MS 9
10 GND GND 10
REFCLK REFCLK
11 +
GND
_Out+ 11
REFCLK
12 REFCLK-
_Out- 12
13 GND GND GND GND 13

14 GND 14
SMB_A
15 VD_1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
DD R_2 15
16 VD_2 16
A_PERp A_PERp A_PERp A_PERp A_PERp A_PERp A_PERp A_PERp A_PERp A_PERp A_PERp A_PERp A_PERp A_PERp A_PERp A_PERp SMB_A
17 VD_9 GND
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDR_3/ 17
VD_16
18 VD_10 GND 18
A_PERn A_PERn A_PERn A_PERn A_PERn A_PERn A_PERn A_PERn A_PERn A_PERn A_PERn A_PERn A_PERn A_PERn A_PERn A_PERn
19 VD_11 GND
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBDAT 19
20 VD_12 GND 20
21 VD_13 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SMBCLK 21
22 VD_14 GND 22
B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp B_PETp SMB_A
23 GND
15
GND
14
GND
13
GND
12
GND
11
GND
10
GND
9
GND
8
GND
7
GND
6
GND
5
GND
4
GND
3
GND
2
GND
1
GND
0
GND
DDR_1 23
NC NC NC
B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn B_PETn CLKREQ
24 GND
15
GND
14
GND
13
GND
12
GND
11
GND
10
GND
9
GND
8
GND
7
GND
6
GND
5
GND
4
GND
3
GND
2
GND
1
GND
0
GND
# 24
NC NC NC
Legend
RX Via
PWR_1 Via
PWR_2 Via
GND Via
Control Signal Via
June 2018
3.4 x16 Retimer, Physical Ballmap (Package Side)
The following figure shows the top view of x16 retimer package-side ball arrangement
with pin numbers.
Figure 3-4. x16 Retimer, Physical Ballmap on Package (Top View)
June 2018
3.5 x16 Retimer Platform Side Land Pattern
The following figure shows top view of the platform side mechanical outline drawing for
x16 retimer.
Dimension tolerances for ball diameter are ±0.05 mm.
Figure 3-5. x16 Retimer, Platform Side Land Pattern with Spacing Details (Top View)
Note: All dimensions are in mm and all distances are center to center.

Signal
Direction
High Speed Differential I/Os
B9 A_PETp0 O
A10 A_PETn0 O
C6 A_PETp1 O
D7 A_PETn1 O
B3 A_PETp2 O
A4 A_PETn2 O
E2 A_PETp3 O
D1 A_PETn3 O
AB1 A_PETp4 O
AA2 A_PETn4 O
June 2018
Signal
Direction
AE4 A_PETp5 O
AD3 A_PETn5 O
AH1 A_PETp6 O
AG2 A_PETn6 O
AL4 A_PETp7 O
AK3 A_PETn7 O
B15 A_PERp0 I
A14 A_PERn0 I
C18 A_PERp1 I
D17 A_PERn1 I
B21 A_PERp2 I
A20 A_PERn2 I
E22 A_PERp3 I
D23 A_PERn3 I
AB23 A_PERp4 I
AA22 A_PERn4 I
AE20 A_PERp5 I
AD21 A_PERn5 I
AH23 A_PERp6 I
AG22 A_PERn6 I
AL20 A_PERp7 I
AK21 A_PERn7 I
H21 B_PETp0 O
G20 B_PETn0 O
L22 B_PETp1 O
K23 B_PETn1 O
P21 B_PETp2 O
N20 B_PETn2 O
U22 B_PETp3 O
T23 B_PETn3 O
AP23 B_PETp4 O
AN22 B_PETn4 O
AU20 B_PETp5 O
Transmitter differential pair B Channels, Lane 5
AT21 B_PETn5 O
AP17 B_PETp6 O
AR18 B_PETn6 O
AU14 B_PETp7 O
AT15 B_PETn7 O
H3 B_PERp0 I
G4 B_PERn0 I
June 2018
Signal
Direction
L2 B_PERp1 I
K1 B_PERn1 I
P3 B_PERp2 I
N4 B_PERn2 I
U2 B_PERp3 I
T1 B_PERn3 I
AP1 B_PERp4 I
AN2 B_PERn4 I
AU4 B_PERp5 I
AT3 B_PERn5 I
AP7 B_PERp6 I
AR6 B_PERn6 I
AU10 B_PERp7 I
AT9 B_PERn7 I
Reference Clock
Y5 REFCLK+ I 100 MHz. Reference Clock (Differential Pair) to

be used in Common Clock configuration, as
V5 REFCLK- I defined by the PCIe Base Specification

Y19 REFCLK_Out+ (2) O
REFCLK_out+.

V19 REFCLK_Out1 (2) O
REFCLK_out -.
Y1 PERST# I Fundamental Reset; Active Low 1.8V (3.3V tolerant)
B11 CLKREQ# I Used by L1PM Substates; Active Low 1.8V (3.3V tolerant)
JTAG
AC18 JTAG_TDI I JTAG Test Data In 1.8V (3.3V tolerant)
JTAG Test Data Out; Open drain; Require pull

up on the platform; Pull up voltage must be
L18 JATG_TDO O selected based on the I/O voltage
selected for other JTAG signals
E16 JTAG_TMS I JTAG Test Mode Select 1.8V (3.3V tolerant)
AG18 JTAG_TCK I JTAG Clock 1.8V (3.3V tolerant)
R18 JTAG_TRST# I JTAG Reset; Active Low 1.8V (3.3V tolerant)
AC6 SMBCLK I/O SMBus Clock Input / Open Drain Clock Output 1.8V (3.3V tolerant)
AG6 SMBDAT I/O SMBus Data Input / Open Drain Output 1.8V (3.3V tolerant)
R6 SMB_ADDR_1 I SMBus Address Bit 1 1.8V (3.3V tolerant)
L6 SMB_ADDR_2 I SMBus Address Bit 2 1.8V (3.3V tolerant)
V23 SMB_ADDR_3/ VD_12 I SMBus Address Bit 3or Vendor Defined 1.8V (3.3V tolerant)
AP11 EE_CLK/VD_5(1) I/O EEPROM Interface Clock or Vendor Defined 1.8V (3.3V tolerant)
AP13 EE_DAT/VD_6(1) I/O EEPROM Interface Data or Vendor Defined 1.8V (3.3V tolerant)
June 2018
Signal
Direction
Miscellaneous
AT1 VD_1 TBD Vendor Defined Signal
W2 VD_2 TBD Vendor Defined Signal
B1 VD_3 TBD Vendor Defined Signal
AU12 VD_4 TBD Vendor Defined Signal
D11 VD_7(1) TBD Vendor Defined Signal
D13 VD_8(1) TBD Vendor Defined Signal
A12 VD_9 TBD Vendor Defined Signal
AT23 VD_11 TBD Vendor Defined Signal
B23 VD_13 TBD Vendor Defined Signal
AT13 RX_DET_BYP I Receiver Detection Bypass
Power
Power
16 pins PWR_1 1.8V or 3.3V
Rail 1
Power
48 pins PWR_2 1.1V or 1.0V or 0.9V or 0.8V
Rail 2
175pins GND 0V
Notes:
1. It is safe to route high speed Vendor Defined signals at these locations. Rest VD pins are recommended to be used for static/
quasi static (low slew rate) signals. Routing high frequency signals on these may impose crosstalk on high-speed signals.
Retimer vendors are recommended to do a thorough signal integrity analysis when using any of the VD pins.

Refer to Section 3.1.1.1, “SMBus Interface” on page 17.

Refer to Section 3.1.1.2, “EEPROM Interface” on page 17

Refer to Section 3.1.1.3, “Miscellaneous Signals” on page 17.
June 2018
Figure 3-6. x8 Retimer, Package-Side Pin Arrangement (Top View)
AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
B_P ERp A _P ETp A _P ETp B_P ERn B _PERn A_PETn
1 VD_1
4
GND
6
GND
4
P ERST# GND
3
GND
1
GND
3
VD_3 1
B_P ERn A _P ETn A_P ETn B _PERp B_P ERp A _PETp
2 GND GND
4
GND
6
GND
4
VD_2
3
GND
1
GND
3
GND GND 2
B _PERn A_PETn A _PETn B _P ERp B _PERp A_PETp

3 5
GND
7
GND GND
5
GND GND GND GND
2
GND GND
0
GND
2 3
B _P ERp A _P ETp A _P ETp B _P ERn B_P ERn A _P ETn

4 5
GND GND
7
GND
5
GND GND
2
GND
0
GND GND
2 4
REFCLK
5 GND GND GND GND GND GND GND GND
+
REFCLK- GND GND GND GND GND GND GND GND 5
B _PERn SM B DA SM B CL SM B _A SM B _A A_P ETp

6 6
GND
T K
GND
DDR_1 DDR_2
GND
1 6
B_P ERp A_PETn
7 6
PWR_2 P WR_2 GND GND P WR_2 PWR_2 GND GND P WR_2 PWR_2 GND GND P WR_2 PWR_2
1 7
8 GND GND GND GND GND GND GND GND GND GND GND GND 8
B _PERn A_PETp
9 7
GND PWR_2 P WR_2 GND GND P WR_2 PWR_2 GND GND P WR_2 PWR_2 GND GND P WR_2 PWR_2 GND
0 9
B _P ERp A _P ETn
10 7
GND PWR_2 PWR_1 PWR_2 P WR_2 P WR_2 PWR_1 P WR_2 GND
0 10
EE_CLK/ CLKREQ
11 GND
VD_5
GND GND PWR_1 PWR_1 GND GND P WR_2 P WR_2 GND GND P WR_1 PWR_1 GND GND VD_7
# 11
12 VD_4 GND PWR_1 P WR_1 P WR_2 P WR_2 PWR_1 P WR_1 GND VD_9 12
RX_DET EE_DAT
13 _B YP /VD_6
GND GND PWR_1 PWR_1 GND GND P WR_2 P WR_2 GND GND P WR_1 PWR_1 GND GND VD_8 GND 13
B _P ETp A _PERn
14 7
GND PWR_2 PWR_1 PWR_2 P WR_2 P WR_2 PWR_1 P WR_2 GND
0 14
B _P ETn A _PERp
15 7
0 15
JTA G_T
16 GND GND GND GND GND GND GND GND GND
MS
GND GND 16
B _P ETp A _PERn
17 6
1 17
B _P ETn JTAG_T JTA G_T JTAG_T JTA G_T A _P ERp

18 6
GND
CK DI
GND
RST# DO
GND
1 18
REFCLK REFCLK
_OUT+ _OUT-
GND GND GND GND GND GND GND GND 19
B _P ETp A _P ERp A_P ERp B_P ETn B _P ETn A _PERn

20 5
GND GND
7
GND
5
GND GND
2
GND
0
GND GND
2 20
B _P ETn A _PERn A_P ERn B _PETp B _P ETp A _PERp

21 5
GND
7
GND GND
5
GND GND GND GND
2
GND GND
0
GND
2 21
B _PETn A _PERn A _P ERn B _PETp B_P ETp A _P ERp

22 GND GND
4
GND
6
GND
4
VD_10
3
GND
1
GND
3
GND GND 22
SM B_A
B _P ETp A _PERp A _P ERp B _P ETn B _P ETn A _PERn
23 VD_11
4
GND
6
GND
4
GND DDR_3/
3
GND
1
GND
3
VD_13 23
VD_12
Legend
PWR_1
PWR_2
GND
Control Signals
Differential TX
Differential RX
No Balls
June 2018
3.8 X8 Retimer Ballmap (Platform Side)
The following figure shows the platform side land pattern. The TX and RX balls have
been swapped when compared to package side ballmap, i.e., “TX lane x” in package
side ballmap gets mapped to “RX lane x” in the land pattern.
Figure 3-7. x8 Retimer, Platform-Side Pin Arrangement (Top View)
B _PETp A _P ERp A _P ERp B _P ETn B _P ETn A _P ERn
1 VD_1
4
GND
6
GND
4
P ERST# GND
3
GND
1
GND
3
VD_3 1
B _PETn A _PERn A _P ERn B _P ETp B_P ETp A _P ERp

2 GND GND
4
GND
6
GND
4
VD_2
3
GND
1
GND
3
GND GND 2
B _P ETn A _P ERn A_P ERn B _PETp B _P ETp A _P ERp
3 5
GND
7
GND GND
5
GND GND GND GND
2
GND GND
0
GND
2 3
B _P ETp A _P ERp A_PERp B_P ETn B_P ETn A _PERn

4 5
GND GND
7
GND
5
GND GND
2
GND
0
GND GND
2 4
REFCLK
+
REFCLK- GND GND GND GND GND GND GND GND 5
B _P ETn SM BDA SM B CL SM B _A SM B_A A _P ERp

6 6
GND
T K
GND
DDR_1 DDR_2
GND
1 6
B _PETp A _P ERn
7 6
1 7
8 GND GND GND GND GND GND GND GND GND GND GND GND 8
B _P ETn A _P ERp
9 7
0 9
B _P ETp A _PERn
10 7
GND PWR_2 PWR_1 PWR_2 P WR_2 P WR_2 PWR_1 PWR_2 GND
0 10
EE_CLK/ CLKREQ
11 GND
VD_5
GND GND PWR_1 P WR_1 GND GND P WR_2 P WR_2 GND GND P WR_1 PWR_1 GND GND VD_7
# 11
12 VD_4 GND PWR_1 P WR_1 P WR_2 P WR_2 P WR_1 P WR_1 GND VD_9 12
RX_DET EE_DA T
13 _B YP /VD_6
GND GND PWR_1 P WR_1 GND GND P WR_2 P WR_2 GND GND P WR_1 PWR_1 GND GND VD_8 GND 13
B _P ERp A _P ETn
14 7
GND PWR_2 PWR_1 PWR_2 P WR_2 P WR_2 PWR_1 PWR_2 GND
0 14
B _PERn A_PETp
15 7
0 15
JTA G_T
16 GND GND GND GND GND GND GND GND GND
MS
GND GND 16
B_PERp A_P ETn
17 6
1 17
B _PERn JTAG_T JTA G_T JTA G_T JTA G_T A_P ETp
18 6
GND
CK DI
GND
RST# DO
GND
1 18
REFCLK REFCLK
_OUT+ _OUT-
GND GND GND GND GND GND GND GND 19
B _P ERp A _P ETp A _P ETp B _P ERn B_P ERn A _P ETn

20 5
GND GND
7
GND
5
GND GND
2
GND
0
GND GND
2 20
B _PERn A_P ETn A _PETn B_P ERp B _PERp A_PETp

21 5
GND
7
GND GND
5
GND GND GND GND
2
GND GND
0
GND
2 21
B_P ERn A _P ETn A_P ETn B _PERp B _P ERp A _PETp

22 GND GND
4
GND
6
GND
4
VD_10
3
GND
1
GND
3
GND GND 22
SM B_A
B_PERp A _P ETp A _P ETp B_P ERn B _PERn A_P ETn
23 VD_11
4
GND
6
GND
4
GND DDR_3/
3
GND
1
GND
3
VD_13 23
VD_12
Legend
PWR_1 Via
PWR_2 Via
GND Via
Control Signal Via
June 2018
June 2018
3.10 x8 Retimer Platform Side Land Pattern
Figure 3-9. x8 Retimer, Platform-Side Land Pattern with Spacing Details (Top View)
Signal
Direction
High Speed Differential I/Os
A3 A_PETp0 O
A4 A_PETn0 O
C1 A_PETp1 O
B1 A_PETn1 O
F1 A_PETp2 O
E1 A_PETn2 O
June 2018
Signal
Direction
J1 A_PETp3 O
H1 A_PETn3 O
A8 A_PERp0 I
A7 A_PERn0 I
C10 A_PERp1 I
B10 A_PERn1 I
F10 A_PERp2 I
E10 A_PERn2 I
J10 A_PERp3 I
H10 A_PERn3 I
M10 B_PETp0 O
l10 B_PETn0 O
R10 B_PETp1 O
P10 B_PETn1 O
V10 B_PETp2 O
U10 B_PETn2 O
W7 B_PETp3 O
W8 B_PETn3 O
M1 B_PERp0 I
L1 B_PERn0 I
R1 B_PERp1 I
P1 B_PERn1 I
V1 B_PERp2 I
U1 B_PERn2 I
W4 B_PERp3 I
W3 B_PERn3 I
Reference Clock
C5 REFCLK+ I 100 MHz. Reference Clock (Differential Pair) to

be used in Common Clock configuration, as
C6 REFCLK- I defined by the PCIe Base Specification

U5 REFCLK_Out+ (2) O
REFCLK_out+.
100Mhz. This pin is used for driving

U6 REFCLK_Out- (2) O
REFCLK_out-.
A2 PERST# I Fundamental Reset; Active Low 1.8V (3.3V tolerant)
A9 CLKREQ# I Used by L1PM Substates; Active Low 1.8V (3.3V tolerant)
JTAG
U3 JTAG_TDI I JTAG Test Data In 1.8V (3.3V tolerant)
JTAG Test Data Out; Open drain; Require pull

up on the platform; Pull up voltage must be
C3 JATG_TDO O
selected based on the I/O voltage selected for
other JTAG signals
June 2018
Signal
Direction
N3 JTAG_TMS I JTAG Test Mode Select 1.8V (3.3V tolerant)
K3 JTAG_TCK I JTAG Clock 1.8V (3.3V tolerant)
G3 JTAG_TRST# I JTAG Reset; Active Low 1.8V (3.3V tolerant)
G8 SMBCLK I/O SMBus Clock Input / Open Drain Clock Output 1.8V (3.3V tolerant)
K8 SMBDAT I/O SMBus Data Input / Open Drain Output 1.8V (3.3V tolerant)
W5 SMB_ADDR_1 I SMBus Address Bit 1 1.8V (3.3V tolerant)
W6 SMB_ADDR_2 I SMBus Address Bit 2 1.8V (3.3V tolerant)
SMB_ADDR_3/
W9 I SMBus Address Bit 3 or Vendor Defined 1.8V (3.3V tolerant)
VD_10
U8 EE_DAT/VD_7(1) I/O EEPROM Interface Data or Vendor Defined 1.8V (3.3V tolerant)
N8 EE_CLK/VD_8(1) I/O EEPROM Interface Clock or Vendor Defined 1.8V (3.3V tolerant)
Miscellaneous
C8 VD_9 TBD Vendor Defined Signal
A6 RX_DET_BYP I Receiver Detection Bypass
Power
5 pins PWR_1 Power Rail 1 3.3V or 1.8V
29 pins PWR_2 Power Rail 2 1.1V or 1.0V or 0.9V or 0.8V
54 pins GND 0V
Notes:
1. It is safe to route high speed Vendor Defined signals at these locations. Rest VD pins are recommended to be used for static/
quasi static (low slew rate) signals. Routing high frequency signals on these may impose crosstalk on high-speed signals.
Retimer vendors are recommended to do a thorough signal integrity analysis when using any of the VD pins.
June 2018
Refer to Section 3.1.1.1, “SMBus Interface” on page 17.

Refer to Section 3.1.1.2, “EEPROM Interface” on page 17

Refer to Section 3.1.1.3, “Miscellaneous Signals” on page 17.
Figure 3-10. x4 Retimer, Package-Side Pin Arrangement (Top View)
W V U T R P N M L K J H G F E D C B A
B _P ERp B _P ERn B _P ERp B _P ERn B _P ERp B _P ERn A _P ETp A _P ETn A _P ETp A _P ETn A _P ETp A _P ETn
1 VD_1
2 2
GND
1 1
GND
0 0
GND
3 3
GND
2 2
GND
1 1
VD_4 1
2 VD_2 GND GND GND GND GND GND GND GND GND GND P ERST# 2
B _P ERn JTA G_T JTA G_T JTA G_T JTA G_T JTA G_T A _P ETp
3 3
GND
DI
P WR_2 P WR_2 P WR_2
MS
P WR_2 P WR_2
CK
P WR_2 P WR_2
RST#
DO
GND
0 3
B _P ERp A _P ETn
4 3
GND P WR_2 P WR_2 P WR_2 P WR_2 P WR_2 P WR_2 P WR_2 GND
0 4
SM B_A REFCLK REFCLK
5 DDR_1
GND
_OUT+
GND GND GND GND GND GND
+
GND VD_5 5
SM B_A REFCLK RX_DET
6 DDR_2
GND
_OUT-
GND GND GND GND GND GND REFCLK- GND
_B YP 6
B _P ETp A _P ERn
7 3
0 7
B _P ETn EE_DA T EE_CLK/ SM BDA SM BCL A _P ERp
8 3
GND
/VD_7
VD_8
P WR_1 P WR_1
T
P WR_1 P WR_1
K
P WR_2 P WR_2 P WR_2 VD_9 GND
0 8
SM B_A
CLKREQ
9 DDR_3/ GND GND GND GND GND GND GND GND GND GND
# 9
VD_10
B _P ETp B _P ETn B _P ETp B _P ETn B _P ETp B _P ETn A _P ERp A _P ERn A _P ERp A _P ERn A _P ERp A _P ERn
10 VD_3
2 2
GND
1 1
GND
0 0
GND
3 3
GND
2 2
GND
1 1
VD_6 10
Legend
PWR_1
PWR_2
GND
Control Signals
Differential TX
Differential RX
No Balls
June 2018
3.13 x4 Retimer Ballmap (Platform Side)
The following figure shows the platform side land pattern. The TX and RX balls have
been swapped when compared to package side ballmap, i.e., “TX lane x” in package
side ballmap gets mapped to “RX lane x” in the land pattern.
Figure 3-11. x4 Retimer, Platform-Side Land Pattern (Top View)
B _P ETp B _P ETn B _P ETp B _P ETn B _P ETp B _P ETn A _P ERp A _P ERn A _P ERp A _P ERn A _P ERp A _P ERn
1 VD_1
2 2
GND
1 1
GND
0 0
GND
3 3
GND
2 2
GND
1 1
VD_4 1
2 VD_2 GND GND GND GND GND GND GND GND GND GND P ERST# 2
B _P ETn JTA G_T JTA G_T JTA G_T JTA G_T JTA G_T A _P ERp
3 3
GND
DI
MS
P WR_2 P WR_2
CK
P WR_2 P WR_2
RST#
DO
GND
0 3
B _P ETp A _P ERn
4 3
0 4
SM B_A REFCLK REFCLK
5 DDR_1
GND
_OUT+
GND GND GND GND GND GND
+
GND VD_5 5
SM B_A REFCLK RX_DET
6 DDR_2
GND
_OUT-
GND GND GND GND GND GND REFCLK- GND
_B YP 6
B _P ERp A _P ETn
7 3
0 7
B _P ERn EE_DA T EE_CLK/ SM BDA SM BCL A _P ETp
8 3
GND
/VD_7
VD_8
P WR_1 P WR_1
T
P WR_1 P WR_1
K
P WR_2 P WR_2 P WR_2 VD_9 GND
0 8
SM B_A
CLKREQ
9 DDR_3/ GND GND GND GND GND GND GND GND GND GND
# 9
VD_10
B _P ERp B _P ERn B _P ERp B _P ERn B _P ERp B _P ERn A _P ETp A _P ETn A _P ETp A _P ETn A _P ETp A _P ETn
10 VD_3
2 2
GND
1 1
GND
0 0
GND
3 3
GND
2 2
GND
1 1
VD_6 10
Legend
PWR_1 Via
PWR_2 Via
GND Via
Control Signal Via
June 2018
June 2018
3.15 X4 Retimer Platform Side Land Pattern
Figure 3-13. x4 Retimer, Platform-Side Land Pattern with Spacing Details (Top View)
June 2018
4 Electrical Characteristics
Two power supplies are supported, PWR_1 and PWR_2.
PWR_1 supports 3.3V or 1.8V. PWR_2 supports one of (0.8V, 0.9V, 1.0V, 1.1V). Actual
voltage is to be decided between retimer vendor and the system vendor.
PWR_1 rail is intended for control signals and sideband signals, whereas PWR_2 is
intended for high-speed signaling.
Table 4-2 lists power distribution for the two rails (PWR_1 and PWR_2) for x4, x8 and
x16 configurations.
4.1 Absolute Maximum Ratings

The following table lists the absolute maximum supply voltage ratings.
Table 4-1. Absolute Maximum Voltage Ratings
Symbol Parameter Min. Max. Units Notes
3.3V 3.3V Supply Voltage 2.8 3.6 V 1
Note:
1. No specific power-on and power-off sequence is required for various supply voltage rails.
4.2 Power Consumption

The following table lists power consumption values under maximum operating
conditions. Maximum power is consumed while all the lanes are operating at 16 GT/s
with full swing on the transmitter. Refer to Section 4.5 for details of thermal
requirements.
Table 4-2. Recommended Absolute Maximum Power Ratings

Power_1 Power_2 Unit
x16 1.7 6.8 W
x8 0.85 3.4 W
x4 0.425 1.7 W
June 2018
4.3 Power Supply Decoupling
Due to the low level signaling of the PCI Express interface, it is recommended that
sufficient decoupling of all power supplies be provided. This is recommended to ensure
that power supply noise does not interfere with the recovery of data from a remote
upstream PCI Express device. Some basic guidelines to help ensure a quiet power
supply are provided below.
Note: The following are guidelines only. It is the responsibility of the retimer designer and the
platform designer to properly test the design to ensure that retimer circuitry does not
create excessive noise on power supply or ground signals at the retimer package balls.
• For PWR_1 rail, a bulk decoupling capacitor of value 1x470 uF (aluminum) and
1x22 uF (0805) is recommended near VR on the platform.
• For PWR_1 rail, 1x10 uF (0603) capacitor is recommended at top cavity on
the platform.
• For PWR_1 rail, 1x10 uF (0603) capacitor is recommended at bottom cavity on
the platform.
• For PWR_2 rail, a bulk decoupling capacitor of value 1x470 uF (aluminum) and
1x22 uF (0805) is recommended near VR on the platform.
• For PWR_2 rail, 2x10 uF (0603) capacitors and 1x10 uF (0805) capacitor is
recommended at the top cavity on the platform.
• For PWR_2 rail, 1x22 uF (0805) capacitor is recommended at the bottom cavity on
the platform.
• It is recommended that the retimer vendor incorporate the decoupling caps in the
package or in the die as needed to minimize noise at the package balls.
4.4 Retimer Latency

The maximum latency (refer to the base specification) specification for PCIe 4.0
retimers is 64 ns to 91 ns depending on clocking architecture and maximum payload
size. Some applications may need significantly lower latency (less than 10 ns). OEMs
are recommended to work with retimer vendors for this low latency use case.
4.5 Package Thermal Considerations
Parameter Description Value Units
TJ(max) Junction temperature 125 °C
TA(max) Ambient temperature 85 °C
Detailed thermal analysis including heat sink requirements are outside the scope of this
specification. The retimers will be used in a variety of chassis types/Platforms. It is up
to the retimer vendor and the OEM to figure out thermal/heatsink requirements based
on the chassis type and specific location on the chassis for the retimer.
June 2018
5 SMBus and EEPROM
It is recommended that each retimer have a dedicated EEPROM behind it from where
the retimer loads its configuration data upon power up. A dedicated EEPROM interface
allows retimer to use fixed address to access the EEPROM.
It is recommended that the retimer load the configuration through EEPROM. Once the
EEPROM configuration is loaded, if any additional configuration changes are needed, it
is done using SMBus interface from the platform side.
If the retimer is located on a CEM riser card, it is not possible for platform to program
the retimer using SMBus interface as the platform does not know the retimer address.
In that case, the retimer (located on CEM riser card) is required to have a dedicated
EEPROM associated with it. It should be noted that, once the retimer loads
configuration from this EEPROM, it cannot be changed using SMBus commands from
the platform.
Retimer pinout supports 3 SMBus address pins allowing up to 8 addressable devices on

the bus. If more than 8 devices (and hence addresses) are needed, some kind of
SMBus multiplexing is to be used on the platform side. Details of how SMBus
multiplexing and addressing is done on the platform is left to be implementation
specific.
It is recommended to minimize the configurations through SMBus in applications where

boot time is to be minimized.
June 2018
6 BGA Footprint Register
Configuration
6.1 SMBus Address Range

Retimer SMBus address will be chosen from the range 20h to 27h.
The following tables hows the bit level mapping for the SMBus address byte.
Table 6-1. SMBus Address bits Mapping

Address Bit Address Bit Value
1 SMB_ADDR_1
2 SMB_ADDR_2
3 SMB_ADDR_3
4 0
5 1
6 0
7 0
6.2 SMBus Command Formats

The SMBus interface responds to following SMBus commands.
Refer to the SMBus specification for a detailed description of these commands.
Block Write/Read with PEC.
The following figure defines the command code associated with retimer SMBus
transactions.
Figure 6-1. Slave SMBus Command Code Format
June 2018
Table 6-2. Slave SMBus Command Code Fields
Bit Field Name Description
0 END End of transaction indicator. Setting both START

and END signifies a single transaction sequence.
0 = Current transaction is not the last read or
write sequence.
1 = Current transaction is the last read or write
sequence.
Refer to Table 6-3 for usage of this bit.
1 START Start of transaction indicator. Setting both START

and END signifies a single transaction sequence.
0 = Current transaction is not the first of a read
or write sequence.
1 = Current transaction is the first of a read or
write sequence. Refer to Table 6-3 for usage
of this bit.
4:2 FUNCTION This field encodes the type of SMBus operation.

000 - Retimer register read operation
001 - Retimer register write operation
010 - Vendor defined
6:5 RSVD This field is Reserved.
7 PEC This bit controls whether packet error checking is

enabled for the current SMBus transaction.
0 = Packet error checking disabled for the
current SMBus transaction.
1 = Packet error checking enabled for the
current SMBus transaction.
START (Bit Field 1) and END (Bit Field 0) is used to indicate if the SMBus command
spans across multiple transactions.
Table 6-3. START and END Bit Usage for Command Code
START Bit Value END Bit Value Description
1 0 This is the first transaction in a command that

0 1 This is the last transaction in a command that

1 1 The SMBus command is implemented using a

single transaction.
0 0 Reserved
6.3 SMBus Block Read/Write Examples

All read and write accesses to the registers should be 32 bits as shown in the examples
below.
Non- shaded items in the examples are driven by SMBus host and shaded items are
driven by SMBus Slave implementation on the retimer.
June 2018
6.3.1 Read Vendor ID (Implemented Using Block Read with
Repeat START)
6.3.2 Write 16G Preset (P7) for Downstream Pseudo Port
6.3.3 Enable SRIS (Implemented Using Block Write with Repeat

START)
If the retimer sends NACK for any of the commands because it is not ready to write or
read the data from specified offset location, the entire command needs to be repeated.
If the retimer supports the optional auto-increment feature, it can indicate the support
by using a bit in the Global Parameter Register 0.
June 2018
6.4 Global Parameter Register 0
June 2018
Table 6-4. Global Parameter Register 0 Description
Bit Location Register Description Attributes
Profile#
This field indicates which retimer common footprint
specification revision the retimer is implementing.
2:0 RO
000: Rev 0.5
001: Rev 0.7+ (indicating this version of specification)
010:111 Reserved for future versions
6:3 Rsvd RO
Port Link Subdivision (Bifurcation)

000000: x16
000001: x8
000010: x4
000011: x8x8
000100: x8x4x4
000101: x4x4x8
000110: x4x4x4x4
000111: x2x2x2x2x2x2x2x2
001000: x8x4x2x2
001001: x8x2x2x4
001010: x2x2x4x8
001011: x4x2x2x8
001100: x2x2x2x2x8
001101: x8x2x2x2x2
001110: x2x2x4x4x4
001111: x4x2x2x4x4
12:7 010000: x4x4x2x2x4 RW
010001: x4x4x4x2x2
010010: x2x2x2x2x4x4
010011: x2x2x4x4x2x2
010100: x4x2x2x2x2x4
010101: x2x2x4x4x2x2
010110: x4x2x2x4x2x2
010111: x4x4x2x2x2x2
011000: x2x2x2x2x2x2x4
011001: x2x2x2x2x4x2x2
011010: x2x2x4x2x2x2x2
011011: x4x2x2x2x2x2x2
011100: x4x4
011101: x2x2x4
011110: x4x2x2
011111: x2x2x2x2
100000: x2x2
100001:111111:Rsvd
EEPROM Data Valid

00: No EEPROM
14:13 01: EEPROM Present and Data Valid
01: EEPROM Present and Data Not Valid
11: Controller Busy*
AutoIncrement Feature Support

15 1: Supported
0: Not Supported
20:16 Rsvd RO
June 2018
EEPROM Data Valid Request Timeout

000: No delay
001: 10ms(Def)
010: 20ms
23:21 011: 30ms RO
100: 40ms
101: 50ms
110: 60ms
111: 70ms
Max Data Rate

000: Rsvd
001: 2.5 G (Def)
010: 5.0 G
26:24 011: 8.0 G RW
100: 16 G
101: Rsvd
110: Rsvd
111: Rsvd
SRIS Enable
27 0 = Common Clock (Def) RW
1 = SRIS
SRIS Link Payload Size (valid when Bit3=1)

000: 128
001: 256
010: 512
30:28 011: 1024 RW
100: 2048
101: 4096 (Def)
110: Rsvd
111: Rsvd
Port Orientation Method

31 0 = Static RW
1 = Dynamic (Def)
Note: *: If the BIOS reads this value, then the retimer controller is busy calculating the
validity of the EEPROM data. The BIOS should retry after a timeout value specified in
Global Parameter Register 0 (Bits [23:21], EEPROM Data Valid Request Timeout).
June 2018
6.5 Global Parameter Register 1

7:0 Device Revision # RO
15:8 Device ID RO
31:16 Vendor ID RO
Vendor ID field identifies manufacturer of the device. This field contains the PCI-SIG*
assigned vendor ID.
Device ID field value is chosen by the vendor.
Device Revision# value is chosen by retimer vendor. This value can be viewed as
extension of the Device ID field.
6.6 Physical Pseudo Port 0 Parameter Register 0
June 2018
Table 6-6. Physical Pseudo Port 0 Parameter Register 0 Description
Downstream Pseudo Port 0 16GT Tx Preset

0000: P0
0001: P1
0010: P2
0011: P3
0100: P4
3:0 0101: P5 RW
0110: P6
0111: P7 (Def)
1000: P8
1001: P9
1010: P10
1011 to 1111: Rsvd
Downstream Pseudo Port 0 16GT Tx Requested

Preset
0000: P0
0001: P1
0010: P2
0011: P3
0100: P4
7:4 RW
0101: P5
0110: P6
0111: P7 (Def)
1000: P8
1001: P9
1010: P10
1011 to 1111: Rsvd
16G Post-Cursor Coefficient Pseudo port 0 Coefficient 1 to

13:8 RW
Coefficient 64
15:14 Reserved RO
16G Cursor Coefficient Pseudo port 0 Coefficient 1 to

21:16 RW
Coefficient 64
23:22 Reserved R0
16G Pre-Cursor Coefficient Pseudo port 0 Coefficient 1 to

29:24 RW
Coefficient 64
31:30 Reserved R0
June 2018
Table 6-7. Physical Pseudo Port 0 Parameter Register 1

Downstream Pseudo Port 0, 8 GT/s TX Preset

0000: P0
0001: P1
0010: P2
0011: P3
0100: P4
3:0 0101: P5 RW
0110: P6
0111: P7 (Def)
1000: P8
1001: P9
1010: P10
1011 to 1111: Rsvd
Downstream Pseudo Port 08GT Requested TX Preset

0000: P0
0001: P1
0010: P2
0011: P3
0100: P4
7:4 0101: P5 RW
0110: P6
0111: P7 (Def)
1000: P8
1001: P9
1010: P10
1011 to 1111: Rsvd

13:8 RW
Coefficient 64
15:14 Reserved RO

21:16 RW
Coefficient 64
June 2018
23:22 Reserved RO

29:24 RW
Coefficient 64
31:30 Reserved RO

7:0 Reserved RO
Port 0 Orientation (valid when Port Orientation Method in

Global Parameter Register = 0)
8 RO
0 = Upstream (Def)
1 = Downstream
Selectable De-emphasis Port 0

9 0 = -3.5 dB (Def) RW
1 = -6.0 dB
RX Impedance Control Port 0

00: Static- On
11:10 01: Static- Off RO
10: Dynamic (Def)
11: Rsvd
Port 2TX Compliance Disable

12 1 = Disable RW
0 = Enable (Def)
Pseudo Port 2 Slave Loopback

13 1 = Enable RW
0 = Disable (Def)
31:14 Reserved RO
June 2018

Downstream Pseudo Port 1 16GT Tx Preset

0000: P0
0001: P1
0010: P2
0011: P3
0100: P4
3:0 0101: P5 RW
0110: P6
0111: P7 (Def)
1000: P8
1001: P9
1010: P10
1011 to 1111: Rsvd
Downstream Pseudo Port 1 16GT Requested Tx

Preset
0000: P0
0001: P1
0010: P2
0011: P3
0100: P4
7:4 RW
0101: P5
0110: P6
0111: P7 (Def)
1000: P8
1001: P9
1010: P10
1011 to 1111: Rsvd

13:8 RW
Coefficient 64
15:14 Reserved RO

21:16 RW
Coefficient 64
June 2018
23:22 Reserved RO

29:24 RW
Coefficient 64
31:30 Reserved RO
June 2018
Downstream Pseudo Port 1, 8 GT/s TX Preset

0000: P0
0001: P1
0010: P2
0011: P3
0100: P4
3:0 0101: P5 RW
0110: P6
0111: P7 (Def)
1000: P8
1001: P9
1010: P10
1011 to 1111: Rsvd
Downstream Pseudo Port 1 8GT Requested TX Preset

0000: P0
0001: P1
0010: P2
0011: P3
0100: P4
7:4 0101: P5 RW
0110: P6
0111: P7 (Def)
1000: P8
1001: P9
1010: P10
1011 to 1111: Rsvd

13:8 RW
Coefficient 64
15:14 Reserved RO

21:16 RW
Coefficient 64
23:22 Reserved R0

29:24 RW
Coefficient 64
31:30 Reserved R0
June 2018

7:0 Reserved RO
Port 1 Orientation (valid when Port Orientation Method in

Global Parameter Register = 0)
8 RO
0 = Upstream (Def)
1 = Downstream
Selectable De-emphasis Port 0 (Valid when Port 0

orientation =1 and Link Data Rate =5G)
9 RW
0 = -3.5 dB (Def)
1 = -6.0 dB
RX Impedance Control Port 1

00: Static- On
11:10 01: Static- Off RO
10: Dynamic (Def)
11: Rsvd
Port 1 TX Compliance Disable

12 1 = Disable RW
0 = Enable (Def)
Pseudo Port 1 Slave Loopback

13 1 = Enable RW
0 = Disable (Def)
31:14 Reserved RO
June 2018
6.12 Register Offsets for Different Link Subdivision
(Bifurcation)
The following table shows the offsets for various registers.
Table 6-12. Register Offsets
Offset
Global Parameter Register 0 0x0000
Global Parameter register 0 0x0004
Rsvd 0x0008
Rsvd 0x000C
Physical Pseudo Port 0 Parameter register 2 0x0010
Physical Pseudo Port 0 Parameter Register 0 Lane 0 0x0014
Physical Pseudo Port 0 Parameter register 1 Lane 0 0x0018
Physical Pseudo Port 0 Parameter register 0 Lane 1 0x001C
Rsvd 0x0094
Rsvd 0x0098
Rsvd 0x009C
Rsvd 0x00A0
Rsvd 0x00A4
Rsvd 0x00A8
June 2018
Table 6-12. Register Offsets
Physical Pseudo Port 1 Parameter register 2 0x00AC
Physical Pseudo Port 1 Parameter register 0 Lane 0 0x00B0
Physical Pseudo Port 1 Parameter register 1 Lane 0 0x00B4
Physical Pseudo port 1 Parameter register 0 Lane 1 0x00B8
Physical Pseudo port 1 Parameter register 1 Lane 1 0x00BC
Physical Pseudo port 1 Parameter register 0 Lane 2 0x00C0
Physical Pseudo port 1 Parameter register 1 Lane 3 0x00CC
Physical Pseudo port 1 Parameter register 0 Lane 4 0x00D0
Physical Pseudo port 1 Parameter register 1 Lane 5 0x00DC
Physical Pseudo port 1 Parameter register 0 Lane 6 0x00E0
Physical Pseudo port 1 Parameter register 1 Lane 7 0x00EC
Physical Pseudo port 1 Parameter register 0 Lane 8 0x00F0
Physical Pseudo port 1 Parameter register 1 Lane 9 0x00FC
Physical Pseudo port 1 Parameter register 0 Lane 10 0x00100
Physical Pseudo port 1 Parameter register 1 Lane 11 0x010C
Rsvd 0x0130
Rsvd 0x0134
Rsvd 0x0138
Rsvd 0x013C
Rsvd 0x0140
Rsvd 0x0144
Rsvd 0x0148
Rsvd 0x014C
Rsvd 0x0150
Rsvd 0x0154
Rsvd 0x0158
Rsvd 0x015C
Rsvd 0x0160
Rsvd 0x0164
Vendor Defined 0x0168
Offsets from 0x0168 onwards can be used for vendor defined purposes.
June 2018

Pci Express Gen4 Retimer Supplemental Features PDF

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PCI Express* (PCIe*) 4.

Document Number: 336467-004US

activation. Learn more at intel.com, or from the OEM or retailer.

336467 001 • Initial Release November 2017

• Updated the register configuration section to define 32-bit registers

336467 003 • Correct PCI Express naming. March 2018

• X16 Retimer Interface signals, changed pin FJ3 description to “data”

Table 1-1. Abbreviations

Host This term is synonymous with platform or system

SSC Spread Spectrum Clocking

SRIS Separate Reference Clock Independent SSC

N/A Not Applicable

1.3 Specification References

Table 1-2. Retimer Feature Comparison

SRIS Optional Required

Slave Loopback Optional Required

Receiver Lane Margining (Voltage) Optional Required

Not defined explicitly but can be Required

L1PM Substates(2) Optional Required

SMBus Programmable Configurations N/A Required

Support for EEPROM load configuration N/A Optional

Retimer Common (size, pinout) Footprint N/A Required

Reference Clock Out N/A Required

1.4.1 Link Subdivision

Figure 2-1. Retimer Form Factors

Figure 3-1. x16 Retimer Block Diagram

Table 3-1. x16 Retimer Signal Descriptions (Sheet 1 of 5)

High Speed Differential I/O

100 MHz. Reference Clock (Differential Pair) to be

100 MHz. This pin is used for driving

100 MHz. This pin is used for driving

PCI Express Auxiliary Signals

Fundamental Reset; Active

B6 JTAG_TDI I JTAG Test Data In 1.8V (3.3V tolerant)

JTAG Test Data Out; Open drain; Require pull up

B12 JTAG_TMS I JTAG Test Mode Select 1.8V (3.3V tolerant)

B3 JTAG_TCK I JTAG Clock 1.8V (3.3V tolerant)

E8 JTAG_TRST# I JTAG Reset; Active Low 1.8V (3.3V tolerant)

System Management Bus (SMBus)

SMBus Data Input / Open

F34 SMB_ADDR_1 I SMBus Address Bit1 1.8V (3.3V tolerant)

B23 SMB_ADDR_2 I SMBus Address Bit2 1.8V (3.3V tolerant)

EEPROM Configuration Interface

FJ23 VD_1(1) TBD Vendor Defined Signal

FF24 VD_2(1) TBD Vendor Defined Signal

FJ6 VD_3(1) TBD Vendor Defined Signal

FF8 VD_4(1) TBD Vendor Defined Signal

FJ9 VD_5(1) TBD Vendor Defined Signal

FF11 VD_6(1) TBD Vendor Defined Signal

FJ25 VD_9(1) TBD Vendor Defined Signal

FF27 VD_10(1) TBD Vendor Defined Signal

FJ28 VD_11(1) TBD Vendor Defined Signal

FF30 VD_12(1) TBD Vendor Defined Signal

FJ31 VD_13(1) TBD Vendor Defined Signal

FF33 VD_14(1) TBD Vendor Defined Signal

G1 VD_15(1) TBD Vendor Defined Signal

E11 RX_DET_BYP I Receiver Detection Bypass

6 pins PWR_1 Power Rail 1 1.8V or 3.3V

24 pins PWR_2 Power Rail 2 1.1V or 1.0V or 0.9V or 0.8V

Address pin SMB_ADDR_3 can be used for Vendor Defined signal.

3.1.1.2 EEPROM Interface

3.1.1.3 Miscellaneous Signals

3.1.1.3.1 RX_DET_BYP (PCIe_BYPASS_MODE)