Assignment

6562-VLSI Techniques
All students of Third year Second shift are hereby informed to solve and submit this
assignment after 31/03/2020. (The marks of this will be added to VLSI term work.)
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1. Write answers of following two mark questions.
a) Define Entity. Write its syntax.
b) Define architecture. Write its syntax.
c) State use of package in VHDL.
d) State difference between stimulus only and full test bench.
e) Define Moore machine.
f) Write excitation table for D & T flip-flop.
g) State difference between PLA and PAL.
h) List various IC integration levels.
i) Define Threshold voltage and pinch-off voltage in MOSFET.
j) What is Hot electron effect?
k) Draw construction and symbol of P-channel MOSFET.
l) Define Low and High Noise Margin.
m) Draw voltage transfer characteristics of CMOS inverter.
n) Define process. Write its syntax.

2. Write answers of following four mark questions

a) Explain various data types in VHDL.
b) Write VHDL code for 8:3 encoder using behavioral modeling style.
c) Compare CPLD and FPGA.
d) Explain steps involved in N-well IC fabrication.
e) State advantage of structural modeling style. Explain structural modeling style with one
example.
f) Write VHDL test bench for 3 input NAND gate.
g) Draw state diagram and design FSM using JK flip-flop for sequence 101.
h) Draw and explain resistive load inverter.
i) Write VHDL code for full adder using dataflow modeling.
j) Draw and explain VLSI design flow.
k) Draw and explain operation of CMOS NAND gate.
l) Write VHDL code of 8:1 multiplexer.
m) Draw and explain PAL macro-cell.
n) Explain constant voltage scaling technique.
o) Implement following equation using CMOS logic .
p) Write VHDL code for D-flip-flop.
q) Draw and explain general architecture of CPLD.
r) Draw and explain operation of EX-OR gate using transmission gate.
s) Write VHDL code for state diagram shown in fig 6.d

Fig. 6.d