RS Latches

William Shoaff

wds@cs.fit.edu

http://www.cs.wds.edu/~wds/classes/comp-org/Logic/sequential/

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 Cross-coupled NOR gates

• Input to leftmost gate is S = 0, Q = 0;

output is Q̄ = S + Q = 1

• Input to rightmost gate is Q̄ = 1, R = 0;

output is Q = Q̄ + R = 0

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 The Set Switch

• Now set the S switch

 The Set Switch

• Now set the S switch

• This sets Q̄ off, setting Q and the light on

 The Set Switch

• Now set the S switch

• This sets Q̄ off, setting Q and the light on

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 The Set Switch

• Now consider what happens when S is turned off

 The Set Switch

• Now consider what happens when S is turned off

• The output Q̄ remains on and the light remains on

 The Set Switch

• Now consider what happens when S is turned off

• The output Q̄ remains on and the light remains on

• Now the switch at S has no effect on the circuit

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 The Reset Switch

• The circuit can be reset by flipping the R switch on

 The Reset Switch

• The circuit can be reset by flipping the R switch on

• The light goes off

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 The Reset Switch

• And setting R = 0 keeps the light off

• Now the switch at R has no effect on the circuit

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 Latches and Flip-Flops

• The circuit has two stable states

 Latches and Flip-Flops

• The circuit has two stable states

• Such a circuit is called a flip-flop or latches

 Latches and Flip-Flops

• The circuit has two stable states

• Such a circuit is called a flip-flop or latches

• Latches and flip-flops store information

 Latches and Flip-Flops

• The circuit has two stable states

• Such a circuit is called a flip-flop or latches

• Latches and flip-flops store information

• Latches change output on changes to input

 Latches and Flip-Flops

• The circuit has two stable states

• Such a circuit is called a flip-flop or latches

• Latches and flip-flops store information

• Latches change output on changes to input

• Flip-flop change output only when the clock changes

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 RS Latches

• RS latches are generally drawn as shown below

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 Finite State Diagram for RS Latch

• Here’s how the RS latch works for stable transitions

Input Output
S R Q Q̄
1 0 1 0
0 1 0 1
0 0 Q Q̄
1 1 unstable

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 Finite State Diagram for RS Latch

• If S = 1, R = 1 from state Q = 0, Q̄ = 1, unstable

state Q = 0, Q̄ = 0 is entered

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Finite State Diagram for RS Latch

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 Finite State Diagram for RS Latch

• If S = 1, R = 1 from state Q = 0, Q̄ = 1, unstable

state Q = 0, Q̄ = 0 is entered

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• We want the output Q and Q̄ to be complements

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 Unstable Input/Race Conditions

• If R and S simultaneous return 0, the circuit will os-

cillate between two unstable states in a race condition
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 State, Clock, Setup and Hold Times

• The current state of a circuit is the collection of feed-

back signals (Q and Q̄ for the RS latch)
 State, Clock, Setup and Hold Times

• The current state of a circuit is the collection of feed-

back signals (Q and Q̄ for the RS latch)

• A clock (periodic external event) determines when the

current state changes to a new state
 State, Clock, Setup and Hold Times

• The current state of a circuit is the collection of feed-

back signals (Q and Q̄ for the RS latch)

• A clock (periodic external event) determines when the

current state changes to a new state

• The new state is determined by the current state and

the inputs
 State, Clock, Setup and Hold Times

• The current state of a circuit is the collection of feed-

back signals (Q and Q̄ for the RS latch)

• A clock (periodic external event) determines when the

current state changes to a new state

• The new state is determined by the current state and

the inputs

• Clocking event: low-to-high or high-to-low change

 State, Clock, Setup and Hold Times

• The current state of a circuit is the collection of feed-

back signals (Q and Q̄ for the RS latch)

• A clock (periodic external event) determines when the

current state changes to a new state

• The new state is determined by the current state and

the inputs

• Clocking event: low-to-high or high-to-low change

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• The setup time is the minimal time the input must
be stable before a clock event
• The setup time is the minimal time the input must
be stable before a clock event

• The hold time is the minimal time the input must be

stable after a clock event

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 Timing for the RS Latch

S(t) R(t) Q(t) Q(t + 4t) Comment

0 0 0 0 Hold
0 0 1 1
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 X Not Allowed
1 1 1 X
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• The characteristic equation (recursion) is:

Q(t + 4t) = S(t) + R̄(t)Q(t)

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 Avoiding Unstable States and Race
Conditions

• What’s really wanted is a circuit that allows us to flip

from 0 to 1, or hold a value indefinitely
Input Output
Data Enable Q
0 1 0
1 1 1
X 0 Q
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 Level Triggered D Type Latch

• Make certain: If S = 1 then R = 0 and if R = 1 then

S=0

• When E = 0 the value of D does not change the

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 output

• When E = 1 the value of Q changes to D

D(t) E(t) Q(t) Q(t + 4t) Comment
0 0 0 0 Hold
0 0 1 1
1 0 0 0
1 0 1 1
1 1 1 1 Set
1 1 0 1
0 1 1 0 Reset
0 1 0 0
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• The characteristic equation (recursion) is:

Q(t + 4t) = D(t)E(t) + Ē(t)Q(t)

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