Chapter 7 – The CPU and Memory

 
·         This chapter covers the following main topics:
o        The components of the CPU
o        The concept of Registers
o        The memory unit and its operations
o        The fetch-execute instruction cycle
o        Instruction format
o        Classification of instructions

Introduction
·         This chapter and the next few chapters extents the Little Man Computer model to discuss the real
computer hardware architecture
·         This chapter covers, in particular, both the Central Processing Unit (CPU) and Memory
·         CPUs varies in their capabilities, complexity, and even applications
·         The CPU model covered in this chapter is not based on any particular model
·         Memory is separated both physically and functionally from the CPU
·         The CPU and memory are very closely associated
o        Every instruction the CPU executes requires at least one, and possibly more, memory
access

The Components of the CPU

·         Figure 7.1 page 166 shows a simplified system block diagram of a typical general-purpose CPU
and memory structures
·         A simplified internal structure of a typical CPU can be viewed as consisting of 3 main
components
o        Arithmetic/logic unit (ALU)
§         Responsible for logical and arithmetic calculations
o        Control unit (CU)
§         Responsible for managing and controlling the instruction execution
o        I/O interface
§         Responsible for managing I/O operations
§         Defines an interface between the CPU and the various I/O devices
·         Figure 7.2 in page 167 shows the relationship between the LMC model and a real computer model
·         This diagram shows that the 2 models are conceptually very similar
 o        Little Man                     correspond to the CU function in the real computer
o        Calculator                     correspond to the ALU function in the real computer
o        Mailbox                          correspond to the memory function in the real computer
o        Program counter         correspond to the PC register function in the real computer
o        I/O baskets                   correspond to the I/O interface function in the real computer
 
The Concept of Registers
·         Register is a hardware component which provides temporary data storage capability within the
CPU
·         Registers storage is required during instruction execution
·         Registers provide very limited storage capability (typical register size: 16, 32, 64, 128 bits)
·         Therefore, a register is typically used to store a single data unit (e.g. memory address, integer
number)
·         Register access is extremely fast (fastest storage device) as it sets at the top of the storage
hierarchy
·         Registers are accessed directly by the Control Unit (i.e. not addressed as a memory location)
·         Modern CPUs would typically have few 100’s of registers
·         Registers are referred to by their names where each has a unique name
·         Different CPUs usually vary in their
o        Number of registers
o        Size of each register
o        The purpose of each register
o        Registers naming convention
·         Each register has a particular and predefined purpose such as:
o        Hold data being processes
o        Hold instruction to be executed
o        Hold memory or I/O address to be accessed
o        Hold status data for tracking computer and execution statuses
o        Hold numbers in different numerical formats (unsigned integer, signed integer, floating
point)
 
·         The following are typical operations that can be performed on registers
o        Load it with data from another location (mostly from other registers or memory)
o        Add or subtract data from other location and store result in the register
o        Shift or rotate content left or right by one or more bits
o        Clear register by setting its content to zero
o        Increment or decrement content
o        Bit inversion
 
·         Registers can be classified into 3 main categories:
o        General-purpose or accumulator or user-visible registers
§         Are used to hold general-purpose data (e.g. integer number)
§         Can be directly referenced by application programs
o        Privileged registers
 §         Can only be accessed by the operating system
§         Used in the implementation of operating system services (e.g. memory management)
o        CPU internal usage registers
§         Can only be accessed by the CPU
§         Used to during instruction execution (e.g. hold instruction being executed)
 
·         The control unit uses several registers for its internal use:
o        Program counter register (PC) holds the memory address of the instruction to be
executed
o        Instruction register (IR) holds the actual instruction being executed
o        Memory address register (MAR) holds a memory address to be accessed
o        Memory data register (MDR) holds the data that has been retrieved from memory (in
case of read) or to be stored into memory (in case of write)
o        Status register (SR) holds 1-bit flags for keeping track of special condition during
instruction execution (e.g. carry, overflow, power failure, internal error, etc.)
 
·         See Figure 7.3 in page 153 for registers available in the IBM zSeries computers

The Memory Unit

·         Memory is responsible for temporarily holding instructions and data during program execution
·         Data and instructions in memory are immediately available to the CPU
·         Memory is connected to the CPU through special system bus
·         Memory consists of linear storage cells
·         Each cell is capable of storing a single data unit
·         In most modern computers, the cell size is 1 byte (i.e. smallest addressable data unit)
·         Memory cells are usually grouped to store large data unit (e.g. integer number)
·         A memory cell is referenced by its address
·         Each address is a unique unsigned integer number, starting at address 0
·         All memory cells are identical in their purpose (e.g. store general purpose data)
 
The Operation of Memory
·         The MAR and MDR registers acts as an interface between the CPU and memory
·         MAR
o        Holds the address in memory which to be open for data access
o        Connected to address decoder that resolves the memory address to be accessed
·         Address decoder
o        Interpret the address passed from MAR to identify the address to be accessed
o        Activate the appropriate address line in memory for access
·         MDR
o        MDR is data holding register during memory access
o        Store the content of memory that is currently addressed by MAR in case of read
o        Store the data to be stored into memory in case of write
 o        The word size that can be retrieved or stored into memory in a single operation is
determined by the size of MDR
 
·         There are 3 control lines that controls memory access, see Figures 7.4 - 7.7 in pages 154 - 157
o        Address line
§         There is 1 address line for every memory cell
§         An address line for a particular cell is turned only when addressing data within
that cell
o        Read/write line
§         Determines whether the memory access is a read or a write operation
§         Turned on in case of read and off in case of write
o        Activation line
§         Used to control the memory access operation
§         Turned on to start a memory access operation (i.e. read or write)
 
·         See Figure 7.6 in page 172 to see how memory access is done
 
·         The following are the steps taken to load data from a particular memory location (read
operation)
1.        CPU copies the address of memory to be accessed into MAR
2.        CPU sets the Read/Write switch on to indicate a read operation
3.        CPU sets Activation line on to start the data transfer
4.        Data transfer takes place retrieving data from the specified memory location and store it
into the MDR register
5.        Data is copied from the MDR into another register depending on the type of read data
 
·         The following are the steps taken to store data into a particular memory location (write
operation)
1.        CPU copies the address of memory to be accessed into MAR
2.        CPU copies data into MDR
3.        CPU sets the Read/Write switch off to indicate a write operation
4.        CPU sets Activation line on to start the data transfer
5.        Data transfer takes place to store data into the specified memory location
 
·         Only one memory location is addressed at any given time to prevent conflict
 
Memory Capacity
·         The size of the MAR register is the main determining factors of the addressable physical memory
o        Memory Capacity = 2n where n is the MAR size in bits
·         In today’s computer a typical MAR is at least 32-bits which allows 4GB of memory addressing
·         Many modern CPUs supports 64-bits which allows 264 = 16 x 1018 bytes of memory addressing
·         In these computers the actual limiting factor for memory capacity would be
o        Physical space for fitting large number of memory chips
o        Time requirement for decoding and accessing such a huge memory
 
Memory Implementations
·         The most popular types of memory in use by computers are
o        Magnetic core memory
o        Static RAM
o        Dynamic RAM
o        Read Only Memory (ROM)
 
Magnetic Core Memory
·         Magnetic core memory is an old technology supporting non-volatile storage (i.e. data is
maintained after power is turned off)
·         Magnetic core memory is expensive and slow and has been mostly replaced by RAM
·         Few special purpose computers still uses this type of memory where non-volatile storage is
required
 
RAM
·         Most current computers uses either static or dynamic RAM
·         Both static and dynamic RAM are volatile and writeable (i.e. data is lost when power is turned
off)
·         Dynamic RAM advantages over Static RAM:
o        Less Expensive
o        Requires less power
o        Can be made smaller (i.e. can be made to fit more memory in a single chip)
·         Static RAM advantages over Dynamic RAM
o        Does not need periodic refreshing
o        Faster access time (Static memory is what cache memory is made of)
 
·         Dynamic RAM is more popular than static RAM
·         The size of memory in a single dynamic RAM chip has increased significantly in the last few
years (from fewer than 64KB to over 64 MB)
 
ROM
·         Supports non-volatile storage
·         Read only (i.e. data never changes)
·         Mostly used to store system programs and data used at computer starts up (i.e. boot time)
·         Modern ROM is made so it can be erased and reprogrammed in the factory
·         However within the computer ROM is still read only
 
EEPROM and Flash ROM
·         Recent memory innovation supporting non-volatile and writeable memory
·         Typically slower than ROM
 
The Fetch-Execute Instruction Cycle

·         The fetch-execute cycle in a real computer works very similar to the one for LMC
·         The fetch-execute instruction cycle is a 2 phase process
1.        Fetch phase                   fetch an instruction from memory for execution
2.        Execute phase               execute the instruction
·         The fetch phase is consistent and follow the same steps for all types of instructions
·         The fetch phase consists of the following steps:
1.        Copy content of PC to MAR – this result in transferring the instruction located at the
specified address to the MDR register
2.        Copy content of MDR into IR
3.        Decode the instruction
 
·         The execution phase varies between the different instructions
·         The LOAD instruction execution steps
1. Copy address specified in the instruction to MAR
2. Copy content of MDR register into a general-purpose register
3. Increment the PC register                  
 
·         A special notation is used to describe the fetch-and-execute phase steps for instruction execution
REGa → REGb                              transfer data from one register to another
REG[address] → REGb               transfer the address part of the register content to another register
REGa + REGb → REGc                add content of two registers and store result into a third register
REGa + const → REGb                add content of register to constant and store result into a third
register
 
Examples
·         The LMC STORE instruction fetch-execute steps
1.        PC → MAR
2.        MDR → IR
3.        IR[address] → MAR
4.        A → MDR
5.        PC + 1 → PC
 
·         The LMC ADD instruction fetch-execute steps
1.        PC → MAR
2.        MDR → IR
3.        IR[address] → MAR
4.        A + MDR → A
5.        PC + 1 → PC
 
·         The LMC BR instruction fetch-execute steps
1.        PC → MAR
2.        MDR → IR
 3.        IR[address] → PC

Buses

·         A bus is the physical interface to interconnect the different components within the computer
system
·         This topic will be covered in more details in chapter 8

Instruction Word Formats

·         The instruction set format in a typical real CPU is similar to the one supported by the LMC
·         The instruction word format is divided into 2 parts
o        Op code
o        Address fields
·         See Figure 7.14 in page 184 for an example 32-bit instruction format
·         The address field may refer to register address, memory address or constant data
·         Two types of addresses are defined
o        Source address
o        Destination address
·         The source and destination addresses are also called operands
·         The address may be expressed
o        Explicitly as an address field in the instruction word
o        Implicitly as part of the definition of the instruction (i.e. no address field is necessary)
·         On some computers one or more of the addresses may be implicit
·         In modern computers most address references are explicit
·         Instructions with 1 address field are called unary instruction
·         Instructions with 2 address fields are called binary instruction
·         Instructions with 3 address fields are called ternary instruction
·         The source(s) and destination addresses may be the same or may be different
·         Example of instruction with the same source and destination is a complement of a register content
·         The ADD instruction in LMC uses the accumulator register as both source for one of the numbers
and as the destination for the result
·         The MOVE instruction obviously uses different source and destination addresses

Instruction Word Requirements and Constrains

·         The word size of instructions depends on

o        The CPU design of the instruction set
o        The usage of the address fields
·         2 techniques are in common use for instruction word size design
 o        Fixed length                  instruction size is the same for all instructions in the instruction
set
o        Variable length            instruction size may vary between instructions within the
instruction set
·         In IBM S/390 systems most instructions are 32-bits long but few are 16-bits or 48-bits long
·         x86 uses 8-bits and 16-bits long instructions and some Pentium instructions can be as long as 88-
bits
·         Figure 7.15 in page 172 shows the IBM mainframe and the SPARC RISC instruction formats
o        The IBM instruction set defines variable word size (16-bits to 48-bits)
o        The SPARC RISC defines fixed word size of 32-bits
 
Advantages of Fixed Length Instruction design
·         Simple to design
·         Simplifies the fetch operation
·         It is easy to locate any instruction since every instruction takes the same amount of space in
memory
·         The program counter adjustment is simple (i.e. incremented by instruction word size - fixed)
·         The Skip and Jump instructions (involves adjusting the program counter) are also simple
 
Advantages of Variable Length Instruction design
·         Efficient use of memory since each instruction is only as long as it needs to be. Typically
designed so that most frequently used instructions have the shortest word size
·         The use of different lengths within the instruction set is used to provide flexibility
o        The ability to address large address space
o        Expand of instruction set to support complex instructions that specifies 2 or more address
fields (e.g. instruction that add data from two memory location and put result in a third
memory location)
 
·         Many new CPU designs uses the fixed length instructions exclusively due to its simplicity

Classification of Instructions

·         Most instructions manipulate data

·         Very few do not operate on data like
o        Flow control instructions (e.g. jump)
o        Control and administration instructions  (e.g. halt)
o        No operation instruction (allows programs to create time delays)
·         Most modern computers also provides instructions for the operating system
·         These instructions are known as privileged instructions
·         Computer manufacturers usually group instructions into categories
·         Within a category instructions usually have
o        Similar instruction format
o        Support similar addressing modes
·         Figure 7.16 in page 174 shows the instruction set for the Motorola 68000 CPU
·         The Motorola 68000 CPU divides its instruction set into 8 categories:
1.        Data Movement instructions
2.        Integer Arithmetic instructions
3.        Boolean Logic instructions
4.        Shift and Rotate instructions
5.        Bit Manipulation instructions
6.        Bit Field instructions
7.        Binary Coded Decimal instructions
8.        Program Flow instructions
9.        Privileged instructions
10.     Exception handling instructions
11.     Floating point arithmetic instructions
Note: the Privileged, Exception handling, and the floating point arithmetic instructions are not
listed
 
Data Movement Instructions
·         The data movement category typically include instructions to
o        Move data from memory to general registers
o        Move data from general registers to memory
o        Move data between general registers
o        In some computers move data directly between memory locations
·         Variations of these instructions are used to handle different data sizes (e.g. LOAD byte, LOAD
half-word, LOAD word, and LOAD double-word)
 
Arithmetic Instructions
·         Every CPU instruction set include instructions to perform integer addition and subtraction
arithmetic
·         With the exception of very few special-purpose CPUs, integer multiplication and division
arithmetic are also supported
·         Many instruction sets provides integer arithmetic for different data size (e.g. byte, half-word,
word, double-word)
·         Many instruction sets provides integer arithmetic in different addressing modes (i.e. memory and
register combinations)
·         Most modern CPUs also provide floating point arithmetic capabilities
·         In some cases a separate match coprocessor is needed to enable the floating point capabilities
(e.g. 80386 and later brands)
·         This capability significantly enhances the performance of programs that uses extensive floating
point operations (e.g. CAD/CAM programs)
·         Floating point instructions usually operate on a separate set of registers with 64-bits or 128-bits
word size
·         Modern instruction sets also include instructions to convert between integer and floating point
·         Most modern instruction sets also provide instructions to perform BCD arithmetic
 
Boolean Logic Instructions
·         Most modern instruction sets provide instructions for performing Boolean algebra logic
operations
·         Commonly include NOT, AND, XOR, OR instructions
 
Single Operand Manipulation Instructions
·         Most instruction sets also provide convenient single operand instructions (e.g. negate, increment,
decrement a value, setting register to zero, etc.)
·         Most of these instruction operate on registers but some can also operate on memory
 
Bit Manipulation Instructions
·         Most instruction sets provide instructions for setting, resetting, and testing individual bits in a data
word
·         Some instruction sets also provide instructions to operate on multiple bits at once
 
Shift and Rotate Instructions
·         Most instruction sets provide instructions for shifting and rotating data words
·         Shifting is the process of moving data to left or right one or more bits
·         2 different kinds of shifting are usually provided, see Figure 7.17 in page 177
o        Logical shift
o        Arithmetic shift
·         Rotating takes the bits as they exists and rotate them into the other end
·         Some instruction sets include carry and overflow bit as part of rotate and shifting instructions
 
Program Control Instructions
·         Program control instructions control the flow of the program execution
·         Program control instructions include
o        Jump conditionally (e.g. branch on zero, nonzero, negative, positive, carry, overflow, etc.)
o        Jump unconditionally
o        Subroutine call sometimes know as jump subroutine and return, see Figure 7.18 in page 179
§         Used to implement subroutines, procedures, and function calls
§         A returning address (next instruction after call) must be saved (typically save on the
stack)
§         A jump to the subroutine address is done after the save
§         The return instruction reload the saved return address and jump back
 
Stack Instructions
·         Stack constitute one of the most important data storage structures in programming
·         Stack is implemented as last-in-first-out LIFO structure
·         The stack pointer register is used to keep track of the top of the stack
·         Two operations are typical in the stack, see figure 7.19 in page 194
o        Push               add a data element to the top of the stack
o        Pop                 remove a data element from the top of the stack
·         Subroutine call typically use stack to save the returning address
·         The stack allows for nested subroutine calls (returning is done in a reversing order), see Figure
7.21 in page 181
 
Multiple Data Instructions
·         Specialized instructions to speed up and simplify multimedia processing
·         Multimedia operations are characterized by simple instructions applied identically to every piece
of the data in a set (e.g. move an image, scale an image)
·         Multiple data instructions perform a single operation on multiple pieces of data concurrently
·         Also called Single Instruction, Multiple Data (SIMD)
·         Intel Pentium MMX support SIMD instructions
·         Figure 7.23 in page 182, shows 4-wide SIMD add instruction
 
Other Instructions
·         This category of instructions include I/O and machine control instructions
·         These instructions, in most systems, are privileged instructions
·         These instructions are used by the operating system to implement important operating system
services (e.g. I/O device drivers, memory management, etc.)