ARM Processor Study Notes

1 Explain the features of CISC Machine.

i CISC stands for Complex Instruction Set Computer

ii Instructions of CISC are of variable length.
iii Due to of variable length of instructions in CISC pipelining can’t be implementation in
efficient manner.
iv Different instructions take different number of clocks for execution.
v Numbers of instructions are more in CISC.
vi Hardware architecture of CISC is complex whereas compiler software is simple.

vii CISC machines have very few general purpose registers.

viii In CISC processors data processing instructions can process data which are even in
memory also.
Example: ADD AL, [SI].
In this example the data stored in AL register is added with the data stored in
memory whose address is specified by SI register.
ix Example of CISC is 8086 microprocessor.

2 Explain the features of RISC Machine.

i RISC stands for Reduced Instruction Set Computer

ii Instructions of RISC are powerful and of same length.
iii Due to of same length of instructions in RISC pipelining can be implementation in
efficient manner.
iv All instructions of RISC executes in single clock.
v Numbers of instructions are less in RISC.
vi Hardware architecture of RISC is simple whereas compiler software is complex.

vii RISC machines have large number of general purpose registers.

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viii In RISC processors data processing instructions can process data which are stored in
internal registers. It can’t process data which is in memory. To achieve this concept
RISC has Load-Store architecture.
ix Example of RISC is ARM processor.

3 Explain about the register file of ARM processor.

(i) ARM processor has thirty seven 32 bit registers.

(ii) All the thirty seven registers are not visible simultaneously.

(iii) Depending upon the mode of operation the registers are visible.

(iv)In System Mode / User Mode programmer uses sixteen registers from R0 to R15.

(v) In Fast Interrupt Request (FIQ) Mode out of sixteen visible registers nine registers R0 to R7
and R15 are same as user mode registers. Seven registers R8 to R14 are new for FIQ mode (in
figure they are denoted as R8_fiq to R14_fiq.

(vi) In Supervisor Mode out of sixteen visible registers fourteen registers R0 to R12 and R15 are
same as user mode registers. Two registers R13 and R14 are new for supervisor mode (in figure
they are denoted as R13_svc and R14_svc.

(vii) In Abort Mode out of sixteen visible registers fourteen registers R0 to R12 and R15 are same
as user mode registers. Two registers R13 and R14 are new for abort mode (in figure they are
denoted as R13_abt and R14_abt.

(viii) In Interrupt Request (IRQ) Mode out of sixteen visible registers fourteen registers R0 to R12
and R15 are same as user mode registers. Two registers R13 and R14 are new for supervisor
mode (in figure they are denoted as R13_irq and R14_irq.

(ix) In Undefined Mode out of sixteen visible registers fourteen registers R0 to R12 and R15 are
same as user mode registers. Two registers R13 and R14 are new for undefined mode (in figure
they are denoted as R13_und and R14_und.

(x) There is one Current Program Status Register (CPSR) which is available for all modes.

(xi) There are five Saved Program Status Register (SPSR) one each for System Mode / User
Mode, Fast Interrupt Request (FIQ) Mode, Supervisor Mode, Abort Mode, Interrupt Request
(IRQ) and Undefined Mode denoted as SPSR_fiq, SPSR_svc, SPSR_abt, SPSR_irq and SPSR_und.

Special Function of R13, R14 and R15 registers

(i) R13 register can be used as stack pointer for the implementation of stack.

(ii) R14 is also called as link register (LR) and it is used to store the return address from interrupt
service routine during interrupt operations.

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 ARM Processor Study Notes
(iii) R15 acts as program counter to point next memory location from where processor will fetch
the next instruction.

Fig. : Register File of ARM processor

4 Explain the purpose of Current Program Status Register (CPSR).

Current Program Status Register (CPSR) is a 32 bit register. It is used as status register to reflect
the result of any arithmetic operation and it is also used as machine control flags to select the
mode of operation of ARM processor.

Status Flags:
Bit No. 31: It is used to indicate whether the result of an operation is +ve or –ve. It is denoted by
N.
If N=0 then it indicate the result is +ve.
If N=1 then it indicate the result is -ve.

Bit No. 30: It is used to indicate whether the result of an operation is zero. It is denoted by Z.

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If Z=0 then the result is non zero.
If Z=1 then the result is zero.

Bit No. 29: It is used to indicate whether a carry is generated after an operation on unsigned
numbers. It is denoted by C.
If C=0 then carry is not generated.
If C=1 then carry is generated.

Bit No. 28: It is used to during operation on signed numbers. It is denoted by V.

If V=0 then result of signed number is valid.
If V=0 then result of signed number is valid.

Machine Control Flags:

Bit No. 7: It is used to enable or disable Interrupt Request (IRQ). It is denoted by I.
If I=0 then it enable the Interrupt Request (IRQ).
If I=1 then it disable the Interrupt Request (IRQ).

Bit No. 6: It is used to enable or disable Fast Interrupt Request (FIQ). It is denoted by F.
If F=0 then it enable the Fast Interrupt Request (FIQ).
If F=1 then it disable the Fast Interrupt Request (FIQ).

Bit No. 5: ARM processor can execute ARM instruction sets which are 32 bit instructions and
Thumb instruction sets which are 16 bit instructions. To select ARM instruction sets execution
mode or Thumb instruction sets execution mode Bit No. 5 of CPSR is used and this bit is denoted
by T.
If T=0 then ARM instruction sets execution mode is selected.
If T=1 then Thumb instruction sets execution mode is selected.

Bit No. 4, Bit No. 3, Bit No. 2, Bit No. 1 and Bit No. 0: These are mode selection bits. ARM
processors have seven mode and they can be selected by using Bit No. 4 – Bit No. 0 of CPSR.

Fig. : Various fields of Current Program Status Register (CPSR)

5 Explain various modes of ARM processor.

(i) Undefined Mode: When processor can’t decode an instruction then it goes to undefined

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mode.

(ii) Supervisor Mode: When processor executes a software instruction (SWI) or it is reset then it
goes to supervisor mode.

(iii) Fast Interrupt Request (FIQ) Mode: If a processor is interrupted using FIQ pin and
corresponding FIQ bit of CPSR register is set then processor goes in Fast Interrupt Request (FIQ)
Mode.

(iv) Interrupt Request (IRQ) Mode: If a processor is interrupted using IRQ pin and corresponding
IRQ bit of CPSR register is set then processor goes in Interrupt Request (IRQ) Mode.

(v) Abort Mode: If a processor is trying to fetch instruction from a program memory without the
access permission or when a processor is trying to fetch data from a data memory without access
permission then processor goes to Abort Mode.

6 Explain the features of ARM processor.

(i) ARM processor is based on RISC architecture.

(ii) ARM processor has Harvard architecture.

(iii) It can execute 32 bit ARM instruction sets or 16 bit Thumb instruction sets.

(iv) Instructions of ARM processors are of same length.

(v) Instructions of ARM processors executes in 1 clock cycle.

(vi) Due to of same length of instructions in pipelining can be implementation in efficient manner
in ARM processors.

(vii) ARM processors have large number of general purpose registers.

(viii) ARM processors have MAC (Multiply and Accumulate) unit for DSP applications.

(ix) ARM processors have Load-Store architecture.

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