6 5 4 3 2 1

REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

R123
WCSS_XO 1 2
[24]

2
0R C110
U100-A

R110
U101

1M
n.m
Place R107 close to MSM8974
within 5mm. Keep SDC1 and SDC2 trace lengths
CONTROL

1
VREG_S3A_1P8 less than 50mm and length matching within 1mm.
B28 WCN_XO For eMMC 5.0
[1,11] XO_OUT_D0 Y44 CXO
[11] XO_OUT_D0_EN W45 CXO_EN SDC1_CLK AM50 R107 24R
SDC1_CLK [27] PoP package

2
W47 AK46
MODE PIN [11] SLEEP_CLK SLEEP_CLK SDC1_CMD
AL47
SDC1_CMD [27]
No Pin on PCB

R102

n.m
SDC1_DATA_0 SDC1_DATA_0 [27]
SDC1_DATA_1 AM48 SDC1_DATA_1 [27]
00 = Native mode V44 AL49 SDC1_DATA_2 [27]
[11,15] MSM_RESIN_N RESIN_N SDC1_DATA_2
11 = Boundary Scan-(BSCAN) mode AA45 AK48

1
[20,27] MSM_RESOUT_N RESOUT_N SDC1_DATA_3 SDC1_DATA_3 [27]
SDC1_DATA_4 AM46 SDC1_DATA_4 [27]
[35] MODE F34 MODE_0 SDC1_DATA_5 AR49
R101 1 2 0R SDC1_DATA_5 [27]
G35 MODE_1 SDC1_DATA_6 AJ47
SDC1_DATA_6 [27]
Note: R102 is only needed for BSCAN mode. SDC1_DATA_7 AG47 SDC1_DATA_7 [27]
If BSCAN is not used, leave MODE_0 and Y46
[11] MSM_PS_HOLD PS_HOLD
C MODE_1 floating since both pins are default pull T48 R108 1 2 32.4R SDC2_CLK [30] C
SDC2_CLK
[35] JTAG_SRST_N AM44 SRST_N SDC2_CMD U45 SDC2_CMD [30]
down. AG45 T50
[35] JTAG_TCK TCK SDC2_DATA_0 SDC2_DATA_0 [30] K3QF2F200B-XGCE
[35] JTAG_TDI AL45 TDI SDC2_DATA_1 V46 SDC2_DATA_1 [30]
[35] JTAG_TDO AP46 TDO SDC2_DATA_2 P46 SDC2_DATA_2 [30]
[35] JTAG_TMS AK44 TMS SDC2_DATA_3 R47 SDC2_DATA_3 [30]
[35] JTAG_TRST_N AJ45 TRST_N
VREF_LPDDR3_DQ
USB_HS1_DM G3 USB1_HS_DM_CPU [35]
B34 EBI0_VREF_DQ USB_HS1_DP F4 USB1_HS_DP_CPU [35]
AU1 EBI1_VREF_DQ USB_HS1_ID E7 Rev.H NC
USB1_PHY_VBUS
BJ29 EBI0_VREF_CA2
AG49 EBI1_VREF_CA2 USB_HS1_SYSCLK E5 XO_OUT_D0 [1,11]
USB_HS1_VBUS D6
VREF_LPDDR3_CA
F40 EBI0_VREF_D0
F28 EBI0_VREF_D1
6.3VC103 N47 G7
100NF EBI0_VREF_D2 USB_SS_RX0_M USB1_SS_RX0M [35]
H14 EBI0_VREF_D3 USB_SS_RX0_P H6 USB1_SS_RX0P [35]
BD40 EBI0_VREF_CA1 USB_SS_TX0_M J7 USB1_SS_TX0M [35]
USB_SS_TX0_P K6 USB1_SS_TX0P [35]
USB_SS_CLK_M K2
DIFFCLK_M [11]
AF8 EBI1_VREF_D0 USB_SS_CLK_P J3
6.3V C104 BG9 DIFFCLK_P [11]
100NF EBI1_VREF_D1
M6 EBI1_VREF_D2
R117 & R118 reservered for disable USB3.0

2
BD16 EBI1_VREF_D3 USB_HS2_DM N7
AT44 EBI1_VREF_CA1 USB_HS2_DP P6 R117
R118
USB_HS2_ID R7 n.m
n.m
BJ37

1
EBI0_CAL
AN49 EBI1_CAL USB_HS2_VBUS N1
USB_HS2_SYSCLOCK M4

BJ31 EBI0_ZQ
BE49 EBI1_ZQ PMIC_SPMI_CLK W49 PMIC_SPMI_CLK [11,15]

2
V48
2

2
PMIC_SPMI_DATA PMIC_SPMI_DATA [11,15]

2
R103 R104
R105 R106
240R 240R 240R AN45 E9
240R DNC1 HSIC_CAL
AP44 DNC2 USB_HS1_REXT E3
1

1
H2 C109 C108
USB_SS_REXT

1
USB_HS2_REXT P2 n.m
n.m

2
R122 R124 BK22 DNC3
1M 1M BH22 DNC4
WLAN_REXT B24 HSIC Interface is not used

1
E29 DNC5 Connect HSIC_CAL to GND following Qualcomm's suggestion
G29 DNC6 R109 R111 R112
B 6.81K 200 Remove R113 at EVT if no issue found B
MSM8974 200

MSM_THERM [11]

Place near MSM

R116
N.M

R116 N.M

A A

COMPANY:
Lenovo

HF Pb

1
1

1
TITLE:
S1 S2 S3
LPDDR3_CHANNEL0
HALOGEN-FREE LEAD-FREE STATIC-FREE
DRAWN: DATED:
Gul 2013/12/21

CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>

QUALITY CONTROL: DATED:

<Code> D Rev.0.2
<QC By> <QC Date> 01_MSM8974-CONTROT

RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 1OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

U100-D
MSM8974 NOTE 1
VREG_S3A_1P8
GPIO1 DEFAULT BOOT DEVICE = eMMC
[33]SMART_PA_RST BH12 GPIO_0 GPIO_37 A19 WCSS_WLAN_DATA_1 WCSS_WLAN_DATA_1 [24]
BF14 * F18 BOOT_CONFIG[4:1] = 0b¡¯0000

BLSP1
[35] REDRIVER_EN GPIO_1 * GPIO_38 WCSS_WLAN_DATA_0 [24]
[2,33] SMART_PA_SDA BF12 GPIO_2 GPIO_39 F20 WCSS_WLAN_SET WCSS_WLAN_SET [24] U100-E Note: Install R216 to disable
[2,33] SMART_PA_SCL BG13 GPIO_3 GPIO_40 E17 WCSS_WLAN_CLK [24] MSM8974 R216 the watchdog.
[35] MSM_DEBUG_TX C29 GPIO_4 GPIO_41 D18 WCSS_FM_SSBI n.m
WCSS_FM_SSBI [24]
GPIO2

BLSP2
D30 C19 TP221

BLSP7
[35] MSM_DEBUG_RX GPIO_5 * * GPIO_42 FM_DATA [24] TP_0.3 L47
C31 GPIO_6 GPIO_43 B18 BT_CTL BT_CTL [35] FP_IQR GPIO_74 GPIO_110 BK18
[2,31] TS_I2C_SDA
E31 C21 [24] L49 * BH18
[2,31] TS_I2C_SCL GPIO_7 * GPIO_44 BT_DATA [24] GPIO_75 * GPIO_111
BG11 GPIO_8 GPIO_45 D16 M48 GPIO_76 GPIO_112 BF20
BE13 B14 M46 BG19

BLSP3

BLSP8
GPIO_9 * * GPIO_46 SMART_PA_INT [33] GPIO_77 * GPIO_113
[2,29] SENSORS2_I2C_SDA BH10 GPIO_10 GPIO_47 A15 TYPEC_CC_SDA [2,35] M50 GPIO_78 GPIO_114 AW47
BE11 GPIO_11 GPIO_48 C17 TYPEC_CC_SCL [2,35] [29] COMPASS_DRDY N45 GPIO_79 GPIO_115 AV48
[2,29] SENSORS2_I2C_SCL
AL3 AA49 [30,35] R49 * AY46
[31] DISP_TE GPIO_12 GPIO_49 UIM2_DATA [29] HALL_INT1_N GPIO_80 * GPIO_116 TX_GTR_THRES [11,33]
AJ3 AC49 UIM2_CLK UIM2_CLK [30,35] A31 AY48 Note1

BLSP10 BLSP9
[31] DISP_HSYNC GPIO_13 * GPIO_50 [31] LCD_ID2 GPIO_81 GPIO_117

BLSP11
LGD_DCDC_ENN AG3 GPIO_14 GPIO_51 AE47 UIM2_RST [30,35] [31] TS_INT_N D32 GPIO_82 GPIO_118 BE17 MAIN_ANT_DET0
[31]
C7 AH50 UIM_DETECT F32 * BF18
[32] CAM0_MCLK0 GPIO_15 GPIO_52 [2,30] [2,28] GASGAUGE_I2C_SDA GPIO_83 GPIO_119 (1X_MRD_SEL/BCX_SW_SEL0)
[31] LGD_DCDC_ENP A7 GPIO_16 GPIO_53 B22 TYPEC_USB1_SW TYPEC_USB1_SW [35] [2,28] GASGAUGE_I2C_SCL E33 GPIO_84 GPIO_120 BA47 (PRX_SW_SEL0/RF_SW_SEL4) GRFC_16 [35]
[32] CAM1_MCLK2 B8 GPIO_17 GPIO_54 D22 IMAGER_1V1_EN IMAGER_1V1_EN [32] [31] LCD_ID C41 GPIO_85 GPIO_121 BA45 [35]
* (PRX_SW_SEL1/RF_SW_SEL3) GRFC_17

BLSP12
CAM1_RST_N C11 GPIO_18 GPIO_55 C23 AUDIO_R_CMD_SW [35] [28] FUEL_INT_N D42 GPIO_86 GPIO_122 BB48
[32]
F12 * A23 VER_GPIO0 [11] E47 * BH46
(DRX_SW_SEL2)
[2,32] CAM0_I2C_SDA0 GPIO_19 GPIO_56 [2,29] SENSORS1_I2C_SDA GPIO_87 GPIO_123
E11 C33 AUDIO_MIC_CMD_SW H44 BF16

BLSP4
[2,32] CAM0_I2C_SCL0 GPIO_20 * GPIO_57 [35] [2,29] SENSORS1_I2C_SCL GPIO_88 GPIO_124
[2,32] CAM1_I2C_SDA1 G15 GPIO_21 GPIO_58 C35 MI2S_4_BCLK MI2S_4_BCLK [33] [35] ANC_AUDIO_CMD F26 GPIO_89 GPIO_125 BG15 CH1_GSM_TX_PHASE_D1 (GPIO126)
[2,32] CAM1_I2C_SCL1 D10 GPIO_22 GPIO_59 D34 MI2S_4_WS MI2S_4_WS [33] CAM0_RST_N C27 GPIO_90 GPIO_126 BD18
E13 * E35 [32] SDC4_CMD D24 BH14
CH1_GSM_TX_PHASE_D0 (GPIO127)
[35] FP_SPI_MOSI GPIO_23 GPIO_60 MI2S_4_DIN [33] [32] CAM_1_PWDN GPIO_91 GPIO_127
B10 D36 D26 BK10

BLSP5
[35] FP_SPI_MISO GPIO_24 * * GPIO_61 MI2S_4_DOUT [33] [11] VER_GPIO1 GPIO_92 * GPIO_128 EXT_GPS_LNA_EN [19]
D12 D38 SDC4_CLK E27 BJ11
[35] FP_SPI_CS GPIO_25 * GPIO_62 SD_CARD_DET_N [30] [33] CODEC_INT2 GPIO_93 * GPIO_129
[35] D14 GPIO_26 GPIO_63 D40 CODEC_RESET_N CODEC_RESET_N [33] [31] A27 GPIO_94 GPIO_130 BB46
FP_SPI_CLK TS_RESET_N
A11 GPIO_27 GPIO_64 D48 C25 GPIO_95 GPIO_131 BD46
[11] FLASH_LED_NOW
E15 * * G47 TP222 TP_0.3 HOME_KEY D28 * BC47

BLSP6
GPIO_28 * * GPIO_65 N.M [35] GPIO_96 GPIO_132
F16 GPIO_29 GPIO_66 F48 GYRO_DRDY_INT [29] [30] UIM1_DATA AB46 GPIO_97 GPIO_133 BH16 WTR0_SSBI1_TX_GPS [22]
G17 * H46 AC45 BG17
[32,35] FP_PER_EN GPIO_30 * GPIO_67 COMPASS_INT [29] [30] UIM1_CLK GPIO_98 GPIO_134 WTR0_SSBI2_PRX_DRX [22]
AN3 GPIO_31 GPIO_68 H48 PROXI_INT_N [30] UIM1_RST Y50 GPIO_99 GPIO_135 BJ15
[35] USB2_SW_EN2
AM4 * G49
[29]
Y48 BK14
[35] USB2_SW_EN1 GPIO_32 GPIO_69 CHG_STAT [28] [2,30] UIM_DETECT GPIO_100 GPIO_136
[35] AM2 GPIO_33 GPIO_70 J45 SLIMBUS_CLK [33] AA47 GPIO_101 GPIO_137 BD20
FP_RESET [11] BATT_REM_ALARM TP_0.3 TP209 CH0_GSM_TX_PHASE_D1 (GPIO138)
[35] TYPEC_CC_EN AP4 GPIO_34 GPIO_71 K46 AF2 GPIO_102 GPIO_138 BJ19 WTR0_GSM_TX_PHASE_D[1] [22]
[24] D20 * * L45
SLIMBUS_DATA [33] N.M
AR47 * BE19
CH0_GSM_TX_PHASE_D0 (GPIO139)
WCSS_BT_SSBI GPIO_35 * * GPIO_72 CODEC_INT1 [33] [35] FORCE_USB_BOOT GPIO_103 GPIO_139 WTR0_GSM_TX_PHASE_D[0] [22]
G19 GPIO_36 GPIO_73 K48 TYPEC_CC_INT1 [35] AR45 GPIO_104 GPIO_140 BC45
[24] WCSS_WLAN_DATA_2 * AT48 BE47
RFFE1_CLK [16,17,19,23]
GPIO_105 GPIO_141 RFFE1_DATA [16,17,19,23]
AT46 GPIO_106 GPIO_142 BG47
AU47 GPIO_107 GPIO_143 BF46
C AU45 F10 C
AV46
GPIO_108 * GPIO_144
C9
CHG_INT_N [28]
GPIO_109 GPIO_145

Plug USB calbe in , and then press VOL_UP_N

to enter force USB boot mode

Handling Unused MSM pins ----From 80_NA437_5B

Note: Using GPIO_54/55/56/91 at frequencies greater than 100KHz or
GPIO_53/92 greater than 10MHz may degrade WLAN Tx EVM and
spectral emission mask performance ONLY when used concurrently with WCN.

B B

I2C Pull-up Resistors VREG_LVS2_1P8 VREG_S3A_1P8

VREG_LVS2_1P8
VREG_LVS1_1P8

R215
R219

2.2K

2.2K
R206

2.2K

2.2K
R205
R204

2.2K
R202

R201

2.2K
2.2K

R203
[2,33] SMART_PA_SCL

2.2K
[2,32] CAM1_I2C_SCL1
[2,31] TS_I2C_SCL
[2,32] CAM0_I2C_SCL0 [2,32] CAM1_I2C_SDA1 SMART_PA_SDA
[2,31] TS_I2C_SDA [2,33]

[2,32] CAM0_I2C_SDA0

VREG_S3A_1P8

VREG_LVS1_1P8
VREG_S3A_1P8 VREG_LVS1_1P8
R207

R211

2.2K
2.2K

R220
R221

2.2K
R208

2.2K
R212

2.2K
2.2K

R213

2.2K
R214

2.2K

[2,29] SENSORS2_I2C_SDA [2,35] TYPEC_CC_SDA

[2,28] GASGAUGE_I2C_SDA
A [2,29] SENSORS1_I2C_SCL A
[2,29] SENSORS2_I2C_SCL [2,35] TYPEC_CC_SCL
[2,28] GASGAUGE_I2C_SCL [2,29] SENSORS1_I2C_SDA COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 02_MSM8974-GPIO Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:2 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

$$$30250

[19]

C U100-B C
HDMI_EDP
[32] MIPI_CSI0_LANE0_M W3 MIPI_CSI0_LN0_N MIPI_DSI0_CLK_N BH8 MIPI_DSI0_CLK_M [31]
[32] MIPI_CSI0_LANE0_P Y4 MIPI_CSI0_LN0_P MIPI_DSI0_CLK_P BG7 MIPI_DSI0_CLK_P [31]
[32] V2 BE9 MIPI_DSI0_LANE0_M [31]
MIPI_CSI0_CLK_M MIPI_CSI0_LN1_N MIPI_DSI0_LN0_N
MIPI_DSI0_LANE0_P [31]
REAR CAMERA [32] MIPI_CSI0_CLK_P
V4
V6
MIPI_CSI0_LN1_P
MIPI_CSI0_LN2_N
MIPI_DSI0_LN0_P
MIPI_DSI0_LN1_N
BF8
BJ7 MIPI_DSI0_LANE1_M [31]
[32] MIPI_CSI0_LANE1_M MIPI_DSI0_LANE1_P [31]
[32] MIPI_CSI0_LANE1_P W5 MIPI_CSI0_LN2_P MIPI_DSI0_LN1_P BH6
[32] MIPI_CSI0_LANE2_M T6 MIPI_CSI0_LN3_N MIPI_DSI0_LN2_N BH4 MIPI_DSI0_LANE2_M [31]
[32] MIPI_CSI0_LANE2_P
U5
U1
MIPI_CSI0_LN3_P MIPI_DSI0_LN2_P BG5
BF6
MIPI_DSI0_LANE2_P
MIPI_DSI0_LANE3_M
[31]
[31]
DISPLAY
[32] MIPI_CSI0_LANE3_M MIPI_CSI0_LN4_N MIPI_DSI0_LN3_N
U3 MIPI_CSI0_LN4_P MIPI_DSI0_LN3_P BE5 MIPI_DSI0_LANE3_P [31]
[32] MIPI_CSI0_LANE3_P

AB6 MIPI_CSI1_LN0_N MIPI_DSI1_CLK_N BA5

AC5 MIPI_CSI1_LN0_P MIPI_DSI1_CLK_P AY6
AB2 MIPI_CSI1_LN1_N MIPI_DSI1_LN0_N BD6
AB4 MIPI_CSI1_LN1_P MIPI_DSI1_LN0_P BC7
AA1 MIPI_CSI1_LN2_N MIPI_DSI1_LN1_N BB6
AA3 MIPI_CSI1_LN2_P MIPI_DSI1_LN1_P BA7
AA5 MIPI_CSI1_LN3_N MIPI_DSI1_LN2_N BB2
AA7 MIPI_CSI1_LN3_P MIPI_DSI1_LN2_P BA3
W7 MIPI_CSI1_LN4_N MIPI_DSI1_LN3_N AY4
Y6 MIPI_CSI1_LN4_P MIPI_DSI1_LN3_P AW3

[32] MIPI_CSI2_LANE0_M AC3 AT4

MIPI_CSI2_LN0_N EDP_AUX_N
[32] MIPI_CSI2_LANE0_P AD4 AR3
MIPI_CSI2_LN0_P EDP_AUX_P
FRONT CAMERA [32] MIPI_CSI2_CLK_M
[32] MIPI_CSI2_CLK_P
AC7
AD6
MIPI_CSI2_LN1_N EDP_LN0_N AR5
AP6
MIPI_CSI2_LN1_P EDP_LN0_P
[32] MIPI_CSI2_LANE1_M AE1 MIPI_CSI2_LN2_N EDP_LN1_N AT6
AE3 MIPI_CSI2_LN2_P EDP_LN1_P AR7
[32] MIPI_CSI2_LANE1_P AE5 AU7
MIPI_CSI2_LN3_N EDP_LN2_N
AE7 MIPI_CSI2_LN3_P EDP_LN2_P AU5
AF6 MIPI_CSI2_LN4_N EDP_LN3_N AW5
AG5 MIPI_CSI2_LN4_P EDP_LN3_P AV6
EDP_TPA AT8

AH6 HDMI_TCLK_M
AJ5 HDMI_TCLK_P EDP_REXT AP2
AJ7 HDMI_TX0_M
AK6 HDMI_TX0_P
AL5 HDMI_TX1_M
AL7 HDMI_TX1_P
AM6 HDMI_TX2_M
AN5 HDMI_TX2_P
AJ1 HDMI_REXT
B B
MSM8974

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 03_MSM8974-MII&HDMI Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:3 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

VREG_L14_1P8

R401 R402 R403

NOTE CSFB NA/EU 0ohm 0ohm DNP
U100-C C402 SVLTE, CA DNP DNP 0ohm
n.m
RF_INTF
BH26 BD22 at EVT GND unused WTR1 IQ signals
[22] WTR0_BB_PRX_IM BBRX_IM_CH0 TX_DAC0_IM WTR0_BB_TX_IM [22] with 0ohm. Remove resistors
[22] WTR0_BB_PRX_IP BK26 BBRX_IP_CH0 TX_DAC0_IP BE23 WTR0_BB_TX_IP [22]
[22] WTR0_BB_PRX_QM BG27 BBRX_QM_CH0 TX_DAC0_QM BE21 WTR0_BB_TX_QM [22]
[22] WTR0_BB_PRX_QP BJ27 BBRX_QP_CH0 TX_DAC0_QP BF22 WTR0_BB_TX_QP [22]
TX_DAC0_IREF BF24 WTR0_BB_TX_IDAC [22]
[22] WTR0_BB_DRX_IM BG29 BBRX_IM_CH1 TX_DAC0_VREF BE25
TXDAC0_VREF [11]
[22] WTR0_BB_DRX_IP BH28 BBRX_IP_CH1
C [22] WTR0_BB_DRX_QM BH30 BBRX_QM_CH1 TX_DAC1_IM BF36 C
[22] WTR0_BB_DRX_QP BK30 BBRX_QP_CH1 TX_DAC1_IP BE35 C404
TX_DAC1_QM BE31 n.m
BK38 BBRX_IM_CH2 TX_DAC1_QP BF32
BH38 BBRX_IP_CH2 TX_DAC1_IREF BG35
BG39 BBRX_QM_CH2 TX_DAC1_VREF BF34
BJ39 BBRX_QP_CH2
BG41 BBRX_IM_CH3 ET_DAC_M BH32
BH40 BBRX_IP_CH3 ET_DAC_P BG33
BJ43 BBRX_QM_CH3
BH42 BBRX_QP_CH3
BC33 WTR0_GPS_BB_IP [22]
GNSS_BB_IP
[24] WLAN_IM G25 BC35 WTR0_GPS_BB_IM [22]
WLAN_BB_IM GNSS_BB_IM
[24] WLAN_IP E25 BC29 WTR0_GPS_BB_QP [22]
WLAN_BB_IP GNSS_BB_QP
[24] WLAN_QM F24 BC31 WTR0_GPS_BB_QM [22]
WLAN_BB_QM GNSS_BB_QM
E23 WLAN_BB_QP
[24] WLAN_QP

MSM8974

NC pins referenece 80_NA437_5B

Rev.E Note:
For CSFB - Unused BBRX_I/Q_CH2/3 pins can be left floating.
Refer to 80-NA437-22/5B MSM8x74 Digital Baseband Training Slides/Design Guidelines:
Handling unused MSM pins page for terminating unused I/Q pins.
TXDAC1_IREF pin must be connected to VREG_L14_1P8.
Unused TXDAC1_VREF pin must be connected to GND
Unused TXDAC1_I/Q pins must be connected to GND

B B

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 04_MSM8974_RF_INTERFACE Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:4 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

VREG_L12_1P8

2
R502

0R
1
C501 NOTE: VDD_QFPROM_PRG needs to be at typical 1.9V
VREG_S3A_1P8
U100-F when blowing fuses. VREG_L12 regulator will be set
1uF to 1.9V for the fuse blow duration only.
PWR VREG_S2B_0P9_ISO For other use cases, it will be set to 1.8V typical.
AD50 VDD_DDR_CORE_1P8 VDD_QFPROM_PRG F36 Please make sure any 3rd party IC powered by VREG_L12
BF2 VDD_DDR_CORE_1P8 Star Route SDC_UIM_VBIAS can tolerate a max VDD of 1.98V.
BJ25 VDD_DDR_CORE_1P8 VDD_SDC_CDC AP48
VREG_L1_1P2 D2 VDD_DDR_CORE_1P8 VDD_SDC_CDC U47
D50 The Resistor between VREG_S2B_0P9 and
VDD_DDR_CORE_1P8 VREG_S2B_0P9_ISO is removed to P09
VREF_SDC R45
AD2 VDD_DDR_CORE_1P2
AE49 VDD_DDR_CORE_1P2 VDD_PLL1 AE35
AV2 VDD_DDR_CORE_1P2 VDD_PLL1 N23 C502 VREG_L12_1P8
C B4 VDD_DDR_CORE_1P2 VDD_PLL1 AE43
100NF
C
B26 VDD_DDR_CORE_1P2 VDD_PLL1 AG15
VREG_KRAIT_0P9 BG25 VDD_DDR_CORE_1P2 VDD_PLL1 AF46
BH48 VDD_DDR_CORE_1P2 VDD_PLL1 AR29 200mA
NOTE: Place R501 close to MSM BK4 VDD_DDR_CORE_1P2 VDD_PLL1 AU29
(AW29) (AE45) (G43)
(H20, J23)
C37 VDD_DDR_CORE_1P2 (AA23, AC31)
E49 VDD_DDR_CORE_1P2 C504 C505 C506 C507
VDD_PLL2 H20
[15] VSENSE_KRAIT_0P9 R5012 1 0R AC25 AW29
VDD_KRAIT VDD_PLL2 1uF 1uF 1uF 1uF
AC27 VDD_KRAIT
AC29 VDD_KRAIT VDD_PLL2 AE45 VREG_L11_1P25
C513 AC37 G43
VDD_KRAIT VDD_PLL2
n.m AC39 VDD_KRAIT VDD_PLL2 AA23
AC41 VDD_KRAIT VDD_PLL2 J23
J25 VDD_KRAIT VDD_PLL2 AC31
J27 VDD_KRAIT 12mA
J29 E21 R505 2 1 0R VREG_L14_1P8
VDD_KRAIT VDD_WLAN
J37
J39
VDD_KRAIT
BD26
40mA
VDD_KRAIT VDD_A2
J41 VDD_KRAIT VREG_L4_1P3
N25 VDD_KRAIT VDD_A2 BE39
N27 VDD_KRAIT
N29 BF28 R508 2 1 0R
VDD_KRAIT VDD_A1 6mA
N37 VDD_KRAIT
N39 VDD_KRAIT VDD_A1 BD38
N41 VDD_KRAIT VREG_L12_1P8
U25 VDD_KRAIT VDD_A1 BC37 Note:R503/R505/R508/R510 is jumper for current
U27 VDD_KRAIT
VREG_S4B_0P9 U29 AB8 measurement, would be deleted at product board.
VDD_KRAIT VDD_MIPI_CSI (AB8)
U37 VDD_KRAIT (AY8, BF6)
U39 VDD_KRAIT C510 C511 (BG3)
U41 VDD_KRAIT
BD8 VREG_L12_1P8
VDD_PLL2 1uF 1uF
AG17 VDD_GFX VDD_PLL2 AY8
AG19 VDD_GFX (AT2, AW7)
AG21 AW7 R512 n.m C508 1uF
VDD_GFX VDD_EDP
AL15 VDD_GFX VDD_PLL2 AT2
(AH4, AK4) 1uF
AL17 AK4 R511 n.m C509
VDD_GFX VDD_HDMI
AL23 VDD_GFX VDD_PLL2 AH4 VREG_L14_1P8
AL25 VDD_GFX
AR15
1 0R 40mA
VDD_GFX R510
AR17 BF26 R513 2
VDD_GFX VDD_A2
AR19 VDD_GFX VDD_A2 BE33
AR23 VDD_GFX 0R C512
AR25 VDD_GFX
AW15 VDD_GFX GND BA31 1uF
AW17 VDD_GFX
AW19 VDD_GFX VDD_MIPI_DSI_0P4 BB4
AW23 VDD_GFX
AW25 BD2 L501 2.2uH
VDD_GFX MIPI_DSI_LDO
B BB18 VDD_GFX B
BB20 VDD_GFX
C515 C503
MSM8974
2.2UF
47PF

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 05_MSM897_PWR Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:5 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

VREG_S3B_1P15
VREG_S1B_0P95
U100-G

PWR1
AA31 VDD_MEM VDD_MODEM AG37
For tatally disable USB port2, AC15 VDD_MEM VDD_MODEM AG39
AC17 AG41
Pin R3 & P4 must connect to GND AG35
VDD_MEM VDD_MODEM
AL39
VDD_MEM VDD_MODEM
VREG_S1B_0P95_ISO T4 need connect to power supply AL19 VDD_MEM VDD_MODEM AL41
AL21 AR31
VREG_S1B_0P95 Ref P01- Terminating Unused USB pins AL27
VDD_MEM VDD_MODEM
AR33
Note:R601 is jumper for current measurement, VDD_MEM VDD_MODEM
U100-H AL29 VDD_MEM VDD_MODEM AR39
would be deleted at product board.
VREG_L24_3P075 AL37 VDD_MEM VDD_MODEM AR41
PWR2 AN15 VDD_MEM VDD_MODEM AW31
AN37 AW33
R604 0R BF38 J1 R601 2 1 0R 12mA VREG_L6_1P8 AR21
VDD_MEM VDD_MODEM
AW35
VDD_EBI0_CDC VDD_USB_3P3 VDD_MEM VDD_MODEM
F42 VDD_EBI0_CDC VDD_USB_3P3 R3 AR35 VDD_MEM VDD_MODEM AW37
B30 VREG_S2B_0P9 AR37 AW39
W43
VDD_EBI0_CDC
F2 R602 2 1 0R 40mA AU17
VDD_MEM VDD_MODEM
Star Route D8
VDD_EBI0_CDC VDD_USB_1P8
P4 AU37
VDD_MEM
VDD_EBI0_CDC VDD_USB_1P8 VDD_MEM
VDD_USB_1P8 K4 AW13 VDD_MEM
AR43 VDD_EBI1_CDC <500mA AW21 VDD_MEM VDD_ALWAYS_ON AD48 N.M TP601
AM8 L7 VREG_S2B_0P9_USB R603 2 1 0R BA13 SDC_UIM_VBIAS
VDD_EBI1_CDC USB_SS_VPTX VDD_MEM TP_0.3
BF10 VDD_EBI1_CDC VDD_USB_CORE F6 BA35 VDD_MEM
L9 VDD_EBI1_CDC VDD_USB_CORE T4 VREG_L2_1P2 BA37 VDD_MEM
BC19 J5 C603 BA39 AB48
VDD_EBI1_CDC VDD_USB_CORE VREG_L12_1P8 VDD_MEM VREF_UIM
C C604 BA41 VDD_MEM
C
BB44 VDD_EBI0_PLL VDD_MIPI_DSI_1P2 BF4 1uF H34 VDD_MEM VREG_S1B_0P95_ISO
G37 VDD_EBI0_PLL VDD_MIPI_DSI_1P8 BG3 1uF L17 VDD_MEM
F30 VDD_EBI0_PLL L19 VDD_MEM
T44 VDD_EBI0_PLL GND H4 L35 VDD_MEM VDD_MEM BD28
F14 VDD_EBI0_PLL GND G5 R17 VDD_MEM
GND R5 R19 VDD_MEM
AN43 VDD_EBI1_PLL R31 VDD_MEM C602
AH8 VDD_EBI1_PLL Note:R602 is jumper for current measurement, R33 VDD_MEM 100NF
BC11 VDD_EBI1_PLL W11 VDD_MEM
J9 would be deleted at product board. W13
VDD_EBI1_PLL VDD_MEM
BD14 VDD_EBI1_PLL W19 VDD_MEM
W21 VREG_OTG
VDD_MEM
MSM8974 W31 VDD_MEM

MSM8974

B B

VREG_S1B_0P95_ISO
VREG_S1B_0P95
(BC11, BF8)

(VDD_MEM) (VDD_EBI) (BD14)

(F42) (B30, F30) (T44, W43) (AR43, AN43) (AM8) (BC19) (F14)
(J9, L9)

C629
(BB44, BF38)

C624
(D8)

C623

C626
C622

C625

C627

C628
1uF C620
(BD28)

C621

1uF
C618
C616

C619
C606

C617
C605

C608

C609

C610

1uF C612
C607

C611

C614

1uF C615
C613

1uF
1uF

1uF
1uF
1uF

1uF

1uF
1uF
1uF

1uF

1uF

1uF

1uF

1uF

1uF
1uF

1uF
1uF

1uF

1uF
1uF

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 06_MSM8974_PWR1&2 Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:6 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

U100-M

NC
A35 NC1 NC55 BG23
A39 NC2 NC56 BG31
A43 NC3 NC57 BG37
VREG_S2B_0P9 A47 BG43
U100-I VREG_L1_1P2 NC4 NC58
AA43 NC5 NC59 BG45
PWR3 342mA AB42 NC6 NC60 BG49
AB44 VDD_CORE VDD_P1 AG7 AC43 NC7 NC61 BH2
AC11 VDD_CORE VDD_P1 AH2 AD8 NC8 NC62 BH20
AC13 VDD_CORE VDD_P1 AJ49 AD42 NC9 NC63 BH24
AC19 VDD_CORE VDD_P1 AN47 AF4 NC10 NC64 BH36
AC21 VDD_CORE VDD_P1 AV44 AH42 NC11 NC65 BH44
AE27 VDD_CORE VDD_P1 B6 AJ43 NC12 NC66 BH50
AG11 VDD_CORE VDD_P1 B16 AK2 NC13 NC67 BJ9
AG13 VDD_CORE VDD_P1 B38 AK42 NC14 NC68 BJ13
AG23 VDD_CORE VDD_P1 BA1 AL43 NC15 NC69 BJ23
AG25 VDD_CORE VDD_P1 BD10 AP8 NC16 NC70 BK6
C AG27 VDD_CORE VDD_P1 BD48 AR11 NC17 NC71 BK34 C
AG29 VDD_CORE VDD_P1 BE15 AR13 NC18 NC72 BK42
AG31 VDD_CORE VDD_P1 BF40 [27] SDC1_RCLK AT50 NC19 NC73 BK46
AG33 VDD_CORE VDD_P1 BJ5 AU49 NC20 NC74 C3
AH44 VDD_CORE VDD_P1 BJ17 AW41 NC21 NC75 C5
AL11 VDD_CORE VDD_P1 BJ35 AW43 NC22 NC76 C39
AL13 VDD_CORE VDD_P1 BJ45 AW49 NC23 NC77 C43
AL31 VDD_CORE VDD_P1 BJ47 VREG_L13_2P95 AY50 NC24 NC78 C45
AL33 VDD_CORE VDD_P1 BK32 B12 NC25 NC79 C47
AL35 VDD_CORE VDD_P1 E1 B32 NC26 NC80 C49
AU11 VDD_CORE VDD_P1 G11 B36 NC27 NC81 D4
AV42 VDD_CORE VDD_P1 G27 B40 NC28 NC82 D44
AW11 VDD_CORE VDD_P1 G41 B42 NC29 NC83 D46
BC21 VDD_CORE VDD_P1 J49 B44 NC30 NC84 E37

2
BC41 VDD_CORE VDD_P1 K8 B46 NC31 NC85 E39
BD36 L3 B48 E41

R711
VDD_CORE VDD_P1 NC32 NC86

0R
H12 VDD_CORE VDD_P1 P44 BA33 NC33 NC87 E43
H16 VDD_CORE VDD_P1 T2 BA43 NC34 NC88 E45
H18 U49 BA49 F8

1
VDD_CORE VDD_P1 NC35 NC89
K44 VDD_CORE VREG_S3A_1P8 BB22 NC36 NC90 F44
L11 VDD_CORE VDD_P2 T46 BC1 NC37 NC91 F46
L13 VDD_CORE BC3 NC38 NC92 H50
L15 VDD_CORE VDD_P3 AH46 BC5 NC39 NC93 J47
L31 VDD_CORE VDD_P3 AK8 BC9 NC40 NC94 L5
L33 AY44 75mA BC17 L43
VDD_CORE VDD_P3 NC41 NC95
R11 VDD_CORE VDD_P3 BC15 BC23 NC42 NC96 M2
R13 VDD_CORE VDD_P3 BC39 BC43 NC43 NC97 M8
R15 VDD_CORE VDD_P3 BG21 BC49 NC44 NC98 M44
R21 VDD_CORE VDD_P3 E19 BD30 NC45 NC99 N3
R23 VDD_CORE VDD_P3 G9 BD32 NC46 NC100 N43
R25 VDD_CORE VDD_P3 G23 BD34 NC47 NC101 N49
R35 VDD_CORE VDD_P3 G31 VREG_S3A_1P8 BD44 NC48 NC102 P8
W15 VDD_CORE VDD_P3 G39 VREG_L9_UIM1 BD50 NC49 NC103 T8
W17 VDD_CORE VDD_P3 G45 BE3 NC50 NC104 U7
W23 VDD_CORE VDD_P3 N5 BE27 NC51 NC105 V8
W33 VDD_CORE VDD_P3 P48 VREG_L10_UIM2 BE43 NC52 NC106 W37
W35 VDD_CORE BE45 NC53 NC107 Y2
W39 VDD_CORE VDD_P4 C15 BF44 NC54
W41 VDD_CORE VREG_L1_1P2
VDD_P5 AC47 MSM8974
VREG_S3A_1P8
VDD_P6 AF48

AH48 VDDPX_7 R706 n.m

VDD_P7
R707 2 1 0R
MSM8974

B B

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 07_MSM8974_PWR3&NC Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:7 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

U100-J
U100-K
VSS U100-L
A1 GND GND AJ33 VSS VSS2
A3 GND GND AJ35 BA19 GND GND J19
BC27 GND GND L21
A5 GND GND AJ37 BA21 GND GND J31
BB38 GND GND J21
A9 GND GND AJ39 BA23 GND GND J33
AD46 GND GND BA29
A13 GND GND AJ41 BA25 GND GND J35
AD44 GND GND AW27
A17 GND GND AK50 BA27 GND GND K42
J43 GND GND BC25
A21 GND GND AL1 BB8 GND GND K50
H42 GND GND BF30
A25 GND GND AN1 BB14 GND GND L1
AE23 GND GND BE37
A29 GND GND AN9 BB26 GND GND L25
AC23 GND GND BF42
A33 GND GND AN11 BB28 GND GND L27
H24 GND GND AV4
A37 GND GND AN13 BB30 GND GND L37
G21 GND GND AR1
A41 GND GND AN17 BB36 GND GND L41
AC35 GND GND BB24
A45 GND GND AN19 BB40 GND GND M42
AC33 GND GND BB32
A49 GND GND AN21 BB42 GND GND N9
AE31 GND GND AN7
AA9 GND GND AN23 BB50 GND GND N11
AE33 GND GND AL9
AA11 GND GND AN25 BD4 GND GND N13
N21 GND GND Y8
AA13 GND GND AN31 BE1 GND GND N15
L23 GND GND AY2
C AA15 GND GND AN33 BE7 GND GND N17 C
GND BG1
AA17 GND GND AN35 BE29 GND GND N19
AF44 GND GND BB10
AA19 GND GND AN39 BF48 GND GND N31
GND BA9
AA21 GND GND AP42 BF50 GND GND N33
AE41 GND GND BE41
AA25 GND GND AP50 BH34 GND GND N35
GND BD42
AA27 GND GND AR9 BJ1 GND GND P42
AJ17 GND GND F38
AA33 GND GND AT42 BJ3 GND GND P50
GND H38
AA35 GND GND AU3 BJ21 GND GND R1
AE17 GND GND H28
AA37 GND GND AU9 BJ33 GND GND R9
GND H30
AA41 GND GND AU13 BJ41 GND GND R27
AJ13 GND GND R43
AB50 GND GND AU15 BJ49 GND GND R29
GND U43
AC1 GND GND AU19 BK2 GND GND R37
AE13 GND GND G13
AC9 GND GND AU21 BK8 GND GND R39
GND J15
AE9 GND GND AU23 BK12 GND GND R41
AF42 GND GND AN41
AE11 GND GND AU25 BK16 GND GND T42
GND AM42
AE15 GND GND AU31 BK20 GND GND U9
AG43 GND GND AG9
AE19 GND GND AU33 BK24 GND GND U11
GND AJ9
AE21 GND GND AU35 BK28 GND GND U13
AN29 GND GND BD12
AE25 GND GND AU39 BK36 GND GND U15
AN27 GND GND BB12
AE29 GND GND AU41 BK40 GND GND U17
AU27 GND GND H8
AE37 GND GND AU43 BK44 GND GND U19
AR27 GND GND H10
AE39 GND GND AV8 BK48 GND GND U21
GND BB16
AF50 GND GND AV50 BK50 GND GND U23
GND BC13
AG1 GND GND AW1 C1 GND GND U31
GND BD24
AJ11 GND GND AW9 C13 GND GND U33
GND BB34
AJ15 GND GND AW45 F50 GND GND U35
GND F22
AJ19 GND GND AY42 G1 GND GND V42
GND H22
AJ21 GND GND B2 G33 GND GND V50
AJ23 GND GND B20 H26 GND GND W1
AJ25 B50 H32 W9 MSM8974
GND GND GND GND
AJ27 GND GND BA11 H36 GND GND W25
AJ29 GND GND BA15 H40 GND GND W27
AJ31 GND GND BA17 J11 GND GND W29
J13 GND GND Y42
MSM8974 J17 GND

MSM8974

B B

SH1 SH8 SH9 SH10

SH7
SH2
1 1 1 1
1
1
SHA-CPU-K9 SHA-POWER-K9 SHA-BB-K9 SHA-RF-K9
SHA-CAM-K9
SHA-WIFI-K9

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 08_MSM8974_GROUND Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:8 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

VREG_S2B_0P9

The capacitors of VDD_MEM & VDD_EBI MSM8974 BYPASS CAPACITORS (VDD_CORE)

are moved to P06. The Ref-Des is reach maximum. PLACE CLOSE TO MSM

C985
C979

C984
1uF C983
1uF C980

C982
1uF C978

1uF C981
1uF

1uF
1uF

1uF
VREG_S3B_1P15 VREG_S4B_0P9 VREG_S2B_0P9
VREG_S2B_0P9_ISO

D (VDD_MODEM) (VDD_SDC_CDC,VDD_PLL1) D
(VDD_GFX) R901 0R (AE35, AG15)
(N23)
(AP48, AE43) (U47)
(AF46) (AR29, AU29)

C986

C989
C987
C927

C928
C926

C929

C930

C988
C931

C932

C933

1uF
1uF

1uF
1uF
1uF
1uF

1uF
1uF

1uF

1uF
1uF
1uF
VREG_L13_2P95
(VDD_P2)
VREG_L9_UIM1

C925
VREG_S3A_1P8
(VDD_P5)

C913

1uF
(VDD_P3)

1uF
C909
C902

C903

C906
VREG_L1_1P2

C901

C911
C907

C908

C912
C905

C910
C904

1uF
1uF

1uF
1uF
1uF

1uF
1uF

1uF

1uF

1uF
1uF

1uF
(VDD_P1, VDD_DDR_CORE_1P2)
VREG_L24_3P075

C943
C941

C942
C940
C936
C934

C939
C935

C938
C937

(J1, R3)

1uF
1uF
1uF

1uF
1uF

1uF

1uF
1uF

1uF

1uF

C993
VREG_L14_1P8

1uF
(BE39)

C924
C923
(BD26, BF26)

VREG_S3A_1P8

1uF

1uF
C949

C953
C948

C952
C945
C944

C950

(VDD_DDR_CORE_1P8)
C946

C951
C947

C915

C917
C914

C916
C C
1uF

1uF

1uF

1uF
1uF
1uF

1uF
1uF

1uF
1uF

VREG_L2_1P2

1uF
1uF
1uF

1uF
(BF4)

C922
1uF
VREG_L6_1P8
VREG_L4_1P3

(BD38, BC37)
VREG_KRAIT_0P9

C919
(K4)

C920
(BF28) (F2) (P4)

C992
C990

C991
(VDD_APCC)

1uF

1uF

1uF
1uF

1uF
C969
C968
C962

C965

C967
C966
C963

C964
1uF
1uF

1uF

1uF
1uF
C955 1uF

1uF
1uF
C956
C954

C960
C958
C957

C959

C961

1uF

1uF
1uF

1uF
1uF

1uF

1uF

1uF

VREG_L10_UIM2 VREG_L11_1P25

(VDD_P6) (VDDA_WLAN)

C921
C918

1uF
1uF

B B

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 09_MSM8974_BYPASS Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:9 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

C C

USB1_PHY_VBUS R1004 R1005 are working with Lenovo standard battery

PM8941_VREF_BAT_THM which bond inner
TP1001
TP_0.3
U1001-B
N.M
PM8941

R1003

R1006
100K

100K
1%

1%
USB1_VBUS
CHARGING BAT_ID is not conneted from battery to PMIC
139 OTG_IN VREF_BAT 218
211 R1004 100K
BAT_THERM 1%
226 PHY_VBUS BAT_ID 227 BATT_ID [28]
172 USB_IN VPH_PWR
173 63 PM8941_VCOIN C1005 1uF
USB_IN VCOIN

R1007
181

n.m
USB_IN

R1001
C1006

47K
C1010 R1002 2 0R 100NF

6.3V
1 220 DC_IN VPRE_CAP 187PM8941_VPRE_BYP
1uF 221 C1007
DC_IN 470NF
229 DC_IN K7 USE 10V
0R VREG_BMS 169
R1005 2 1 212 177 VBATT_SENSE_M
DC_IN_OVP_CTRL BMS_CSM VBATT_SENSE_P
228 DC_IN_OVP_SNS BMS_CSP 193 VPH_PWR
VCHG
C1012 n.m 171 OVP_CP_DRV C1009
189 201 n.m
OVP_OUT VREG_SMBC
205 OVP_OUT VSW_SMBC 208 VPH_PWR
224 L1001 1uH
VSW_SMBC

16V
C1013 100NF 209 TFM201610GHM-1R0MTAA
VDRV_P R1006 can be removed for ES3 and later samples.
217 VCHG_SNS VPH_PWR 198
C1001 C1002 200 206 Might it happens at DVT ?
VCHG VPH_PWR
216 VCHG VPH_PWR 207 Rev.E
4.7UF 4.7UF 199 C1008
GND_CHG_HP NOTE: A 5K ohm resistor is required in parallel with C3789
215 GND_CHG_HP
C1003 n.m 22uF
182 BATFET_CP_DRV
GND 219
[28] VBATT_SENSE 210 VBAT_SNS GND 185 It is recommended to connect
214 VBAT GND 225 pin 185 of PM8941 to GND as a workaround for issue 3 as mentioned in
222 VBAT
directly using a dedicated via. PM8941 DRG (80-NA555-4)
2

223 VBAT
C1011
R1009

B C1004 B
n.m

6.3V
6.3V 22uF
100NF
1

VPH_PWR

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 10_PM8941_CHARGING Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:10 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

R1107 10K
[1] MSM_PS_HOLD

C1107 n.m
TP1103
U1001-A TP1104
[35] JTAG_PS_HOLD PM8941 TP_0.3 TP_0.3
[28,30] PHONE_ON_N MPP_AMUX_CLKS
U1001-C [28,35] PM8941_CBLPWR_N
197
155
PS_HOLD PON_RESET_N 164
204
MSM_RESIN_N [1,15]
R1109 KYPD_PWR_N PON_OUT PON_OUT [15]
GPIO R1108 1
n.m
2 0R
180 CBL_PWR_N
39 GPIO_01 GPIO_19 43 DISP_RESET_N [31] 196 PON_1 GND 175
53 GPIO_02 GPIO_20 36 AUDIOJK_SWITCH_EN [34] 163 RESIN_N OPT_1 191 PM8941_OPTION_1 [11]
[30] VOL_DN_N [30] PM_RESIN_N TP_0.3
62 GPIO_03 GPIO_21 25 TP1111 OPT_2 202
BOOST_BYP_BYP [13,14]
55 GPIO_04 GPIO_22 59 [1,15] PMIC_SPMI_CLK 131 SPMI_CLK OPT_3 114
[30] VOL_UP_N 61 GPIO_05 GPIO_23 34 147 SPMI_DATA OPT_4 129 VREF_LPDDR3_CA
[1,15] PMIC_SPMI_DATA
71 GPIO_06 GPIO_24 105 1uF
77 51 TP1112 TP_0.3 85 PM8941_AVDD_BYP
GPIO_07 GPIO_25 VREG_L8_1P8 VDD_INT_BYP
94 GPIO_08 GPIO_26 67 LCD_BL_PWM [31] PM8941_REF_BYP100NF

6.3V
76 184 152 C1104
GPIO_09 GPIO_27 FLASH_LED_NOW [2] REF_BYP
[28] CHG_EN 86 194 168 C1103
GPIO_10 GPIO_28 TX_GTR_THRES [2,33] R1111 REF_GND VREF_LPDDR3_DQ
[28] CHG_OTG 93 159 150K PM8941_AMUX_PU1 186
GPIO_11 GPIO_29 AMUX_PU1
[28] CHG_PSEL 110 90 R1110 100K PM8941_AMUX_PU2 195 188 SDC_UIM_VBIAS
GPIO_12 GPIO_30 AMUX_PU2 VREF_DDR3_CA
[31] LCD_BL_EN 157 GPIO_13 GPIO_31 143 BATT_REM_ALARM [2]
102 GPIO_14 GPIO_32 166 PM8941_HW_ID 162 AMUX_HW_ID VREF_DDR3_DQ 213
[33] DIVCLK1_CODEC 109 GPIO_15 GPIO_33 106 [35] USB1_HS_ID 179 AMUX_USB_ID
149 GPIO_16 GPIO_34 128 MPP_01 123
165 GPIO_17 GPIO_35 137 XO_OUT_A2_EN [1] MSM_THERM 170 AMUX_1 MPP_02 156
117 146 [27] EMMC_THERM 138 148

30.9K
TXDAC0_VREF [4]

R1112
GPIO_18 GPIO_36 AMUX_2 MPP_03
[16] PA_THERM0 154 AMUX_3 MPP_04 132
178 121
PM8941 [11] QUIET_THERM 203
AMUX_4
AMUX_5
MPP_05
MPP_06 145
VER_ADC0 [11]
VER_ADC1 [11]
MPP_07 136
PM8941_XO_THERM 46 153
VREF_XO MPP_08
NOTE: Placeholder R2677 is required until Qualcomm has 37 XO_THERM
45 GND_XOADC VREG_XO 20 VREG_XO
C validated use of AMUX_PU2 for measuring XO 12 VREG_RF_CLK C
C1101 C1102 VREG_RF_CLK C1106 C1105
temperature. R1113
100NF 91
GND
X1102 n.m 1NF GND 99 1uF 1uF

XO_OUT_A0 69
84 XO_OUT_A0 [22]
2 XTAL_19M2_IN XO_OUT_A1
GND 1 XTAL_19M2_OUT
11 XTAL_19M_IN XO_OUT_A2 60
HOT 3 XTAL_19M_OUT
XO_OUT_DIFF_N 52 DIFFCLK_M [1]
XO_OUT_DIFF_P 68
DIFFCLK_P [1]
3 4
HOT SENSOR XO_OUT_D0_EN
XO_OUT_D0
44
75 R1118 2 1 0R
XO_OUT_D0_EN
XO_OUT_D0 [1]
[1]

R1114 XO_OUT_D1 83
n.m
70 XTAL_32K_IN SLEEP_CLK 30 SLEEP_CLK [1]
54 XTAL_32K_OUT
CT2016DB19200C0FLHA1
TP_0.3 TP1107
TP_0.3 TP1109

Rev. E
Note 1: USB_HSx_SYSCLK from PMIC X0_OUT_D0 is
branched to CXO and USB on the MSM side:
a) Make this a 50 ohm trace.
b) Match branch length. Even 5mm of delta can cause SI
VREG_S3A_1P8 problems.
c) Keep branches as short as possible.
B d) If routing guidellines above cannot be met, add a buffer B
for the USB branch right at at the split.

VPH_PWR
2

2
R1101

R1116
n.m

n.m

R1117

R1120
n.m

n.m
PLACE IN THERMALLY QUIET AREA
2

1
R1105

1
NCP15WF104F03RC

[2] VER_GPIO0
0R

QUIET_THERM [11] [2] VER_GPIO1

1

PM8941_OPTION_1 [11] [11] VER_ADC0

R1106

[11] VER_ADC1
2
2

2
R1103

R1121
n.m

n.m
R1102

R1115

R1119
n.m

n.m

n.m

1
1

RF VERSION INDICATION
HWID VER_GPIO0 VER_GPIO1VER_ADC0VER_ADC1 DESCRIPTION
01 0 0 DSDA_3G
03 0 1 CMCC SE_LTE

04 1 0 CT_SV-LTE
05 0 1
A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 11_PM8941_AMUX_CLK_GPIO Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:11 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

VREG_S1A_1P3

L1202 TFM252010GHM 2.2UH 20% 2.9A 0.070OHM ROHS

VPH_PWR
U1001-D Feedback, signal trace route back from C1208

1125mA C1208

VREG1 4V
47UF
VREG_S2A_2P15
14 VDD_S1 VREG_S1 23
15 7 1225mA from BAT (max) L1202 2.2uH 1.3v 2000mA for device
GND_S1 VSW_S1 VREG_S3A_1P8
C Feedback, signal trace route back from C1209 C
VREG_S2 33
C1205 2 VDD_S2
C1204 17 1 VSW_S2A 930mA from BAT (max) L1203 2.2uH C1209
GND_S2 VSW_S2
9 2.15v 1000mA for device 4V
VSW_S2
22UF 22UF 47UF
VREG_S3 87 Feedback, signal trace route back from C1210 1.8v 2000mA for device
64 VDD_S3 VREG_LVS1_1P8 VREG_LVS2_1P8
L1204 1 2 2.2uH C1210
95 GND_S3 VSW_S3 79 1560mA from BAT (max)
300mA 4V
C1201 C1202 C12033 300mA R1205 0R
VOUT_LVS1 140 47UF
VOUT_LVS2 111 300mA
2.2UF 2.2UF 2.2UF VOUT_LVS3 124

VREG_5V_SNS 47
VREG_OTG
16 VSW_5V VREG_5V 8
32 VSW_5V VREG_5V 24
VPH_PWR 48 VREG_HDMI
GND_5V
133 VIN_5VS VOUT_5VS_OTG 141 500mA

VOUT_5VS_HDMI 125

VREG_FAULT 192

PM8941

B B

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 12_PM8941_SMPS Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:12 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

6.3V C1301
100NF
U1001-E
VREG_S2A_2P15

VREG2
VREG_S1A_1P3 40 VDD_L1_3 VREG_L1 31 1200mA VREG_L1_1P2
118 103 300mA
VREG_S3A_1P8 VDD_L2_LVS1_2_3 VREG_L2 300mA VREG_L2_1P2
L1302 1 2 GZ1005U601TF
VREG_L3 56 VREG_L3_1P2
21 VDD_L4_11 VREG_L4 5 1200mA VREG_L4_1P3
4 VDD_L5_7
19 35 150mA VREG_L6_1P8
VREG_S2A_2P15 VDD_L6_12_14_15 VREG_L6
22 38 50mA VREG_L8_1P8
VPH_PWR VDD_L8_16_18_19 VREG_L8
135 113 150mA VREG_L9_UIM1
VREG_BOOST_BYPASS VDD_L9_10_17_22 VREG_L9
VREG_L10 144 150mA VREG_L10_UIM2
VREG_L11 28 1200mA VREG_L11_1P25
26 300mA
VREG_L12 VREG_L12_1P8
58 42 150mA VREG_L13_2P95
VREG_BOOST_BYPASS VDD_L13_20_23_24 VREG_L13 150mA
VREG_L14 27 VREG_L14_1P8
10 600mA
VREG_L15 VREG_L15_2P05
29 150mA
VREG_L16 300mA VREG_L16_2P7
VREG_L17 151
300mA VREG_L17_2P85
VREG_L18 6 VREG_L18_2P85
98 13 600mA
VREG_BOOST_BYPASS VDD_L21 VREG_L19 VREG_L19_2P9
74 600mA
VREG_L20 VREG_L20_2P95
89 600mA
VREG_L21 300mA VREG_L21_2P95
Note : Voltage label is horizontal in this page VREG_L22 120
VREG_L22_3P0
VREG_L23 18 300mA
VREG_L23_2P85
VREG_L24 82 50mA
C VREG_L24_3P075 C
PM8941 1 2
TP_AVDD_3P3

R1303
0R
C1320

C1309

C1323
C1313

C1315

C1311
C1314

C1308

C1318
C1303

C1317

C1306

C1312
C1310

C1316
C1302

C1307

C1322

C1319
C1321

C1305
C1304

1uF
1uF

4.7UF
1uF

4.7UF
1uF

4.7UF
1uF

1uF

1uF
4.7UF

1uF
4.7UF
1uF

1uF
4.7UF
1uF

1uF
1uF

1uF
4.7UF

1uF
VPH_PWR

B B
U1301 VREG_BOOST_BYPASS
ISL91107IIQZ-T
L1301 1uH
A1 PVIN LX1 B1
C1324 A2 B2
PVIN LX1 TFM201610GHM-1R0MTAA
22UF
R2116 C1328
D1

1K
LX2 U1302
LX2 D2 VREG_BOOST_BYPASS TPS22913B
A3 VIN 100NF

C3 MODE VOUT E1
VOUT E2
A2 A1
VIN VOUT
C1326 C1327 VDD_WL_2GPA_3P3
BOOST_BYP_BYP R1311 1 2 0R B3 E3
[11,14] EN FB B2 B1 C1329
22UF [13] VREG_L19_2P9 ON GND

PGND
PGND
22UF

GND
100NF
D3

C1
C2
R1315
n.m

R1302 1 2 n.m

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 13_PM8941_LDOS Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:13 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

U1001-F
PM8941
LED
VREG_S3A_1P8 161 VDD_MSM_IO VREG_WLED 97
VSW_WLED 126
GND_WLED_SMPS 134
VPH_PWR 96 VDD_WLED
112 GND WLED_SNK1 127
WLED_SNK2 119
Pull down CABC pin with 104
10K if not used WLED_SNK3

DISP_PWM_OUT 150 WLED_CABC GPLED_SRC1 66 GPLED_SRC1 [35]

CABC GPLED_SRC2 81
GPLED_SRC2 [35]
GPLED_SRC3 73
GPLED_SRC4 88
57

R1401
VDD_GPLED

10K
GPLED_SNK1 80 GPLED_SNK1 [35]
GPLED_SNK2 41 GPLED_SNK2 [35]
GPLED_SNK3 65
GPLED_SNK4 49
Rev.E Qualcomm REF design NC GPLED SNK1-4
GND 50
VCHG 183 176 [34]
VDD_RGB RGB_BLU BLUE_LED_DRV
VREG_BOOST_BYPASS 167
RGB_GRN GREEN_LED_DRV [34]
RGB_RED 160 RED_LED_DRV [34]
174 VDD_FLASH
142 VDD_TORCH FLASH_DRV_1 158 FLASH_DRV1 [32]
FLASH_DRV_2 190 FLASH_DRV2 [32]

VIB_DRV_N 72 VIB_DRV_N [35]

C GND 78 C
Connected FLASH_DRV_2 to FLASH_DRV_1
as only one Flash is used.

Note: During large battery current transients, the battery voltage seen by the PMIC
can dip below 2.7V. The current that S2A regulator can supply at such voltages
is less than its rated current of 1A. Bhelper LDO aids S2A to provide current
to the load in this scenario.
The alternate parts for Bhelper LDO:
On Semi part NCP706 which is pending on validation.

RGB LED

B B

U1401 U1001-G
2.1V PM8941
VDD 7
VPH_PWR
[11,13] BOOST_BYP_BYP 6 CE VDD 8 PWR_GND
92 GND GND 100
TP1401 1 101 GND GND 115
VOUT
2 107 GND
TP_0.3 VOUT
3 4 108 GND
VPH_PWR LCON VFB VREG_S2A_2P15
116 GND
5 C1404 122 GND
GND C1405
9 130 GND
EPAD_GND
4.7UF 2.2UF

On Semi part NCP706MX21TAG

Rev. M

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 14_PM8941_LED&GROUND Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:14 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

VREG_S1B_0P95

VPH_PWR

U1501-B
Feedback, signal trace route back from C1515
C1514 VREG_S2B_0P9
53 VDD_S1 VREG VREG_S1 42 C1515
780mA from BAT (max) 0.95v 1900mA for device
C1506 2.2UF 35 44 L1501 0.47uH 47UF 47UF
GND_S1 VSW_S1

C1503

C1504

C1505
Feedback, signal trace route back from C1516
8 6 R1501 1 2 0R
VDD_S2 VREG_S2
9 VDD_S2
C1507 2.2UF 7 C1525 n.m
VSW_S2 1200mA from BAT (max) VREG_S3B_1P15

22UF
18 16

22UF
22UF
0.9v 3000mA for device
GND_S2 VSW_S2 0.47uH
25 GND_S2 VSW_S2 17 L1502
Feedback, signal trace route back from C1517 C1516 C1523
80 60 47UF 47UF NOTE2
2.2UF VDD_S3 VREG_S3
C1508 500mA from BAT (max) 1.15v 1000mA for device VREG_S4B_0P9
62 71 L1504 2.2uH
GND_S3 VSW_S3 C1517
BOM_IGNORE property of C1503-C1505 is 97 95 R1502 1 2 0R
Feedback, signal trace route back from C1518
47UF
VDD_S4 VREG_S4
determined by placement C1509 2.2UF
98 VDD_S4
87
1200mA from BAT (max)
C1526 n.m
VSW_S4
79 GND_S4 VSW_S4 88 C1518 C1524
89 96 L1503 0.47uH 0.9v 3000mA for device
GND_S4 VSW_S4 VREG_KRAIT_0P9
47UF 47UF
C 1 4 differencial-line with REMOTE_GND_SNS, route back under MSM8974 C
2
VDD_S5 VREG_S5 VSENSE_KRAIT_0P9 [5] NOTE2
VDD_S5 1200mA from BAT (max) L1505
C1510 2.2UF 3 0.9v 3000mA for device
VSW_S5
10 GND_S5 VSW_S5 11 0.24uH
20 GND_S5 VSW_S5 12

19 5 C1519 C1520 C1521 C1522

VDD_S6 VREG_S6 L1506 0.9v 3000mA for device
C1511 2.2UF 36 27 1200mA from BAT (max) 22UF 22UF 22UF 22UF
GND_S6 VSW_S6
37 GND_S6 VSW_S6 28 0.24uH
72 VDD_S7 VREG_S7 94
C1512 2.2UF 0.9v 3000mA for device
L1507
54 GND_S7 VSW_S7 63 1200mA from BAT (max)
55 GND_S7 VSW_S7 64 0.24uH
90 VDD_S8 VREG_S8 93
C1513 2.2UF 91 1200mA from BAT (max) L1508 0.9v 3000mA for device
VDD_S8
VSW_S8 82
73 GND_S8 VSW_S8 83 0.24uH
81 GND_S8 VSW_S8 92

47 REMOTE_GND_SNS

PM8841
differencial-line with VSENSE_KRAIT_0P9, route back under MSM8974

NOTE 1: CONNECT REMOTE_GND_SNS GROUND TO MSM GROUND WITH SINGLE TRACE

NOTE 2: PLACE S2B, S4B, S5B, S6B, S7B, S8B OUTPUT CAPACITORS CLOSE TO MSM

VPH_PWR

U1501-A
B B
CONTROL VDD_PON 50

[11,15] PON_OUT 68 PS_HOLD GND 45

GND 46
[1,11] MSM_RESIN_N 69 RESIN_N
41 C1502
VDD_INT_BYP
26 1uF
GND
SPMI_CLK 77 PMIC_SPMI_CLK [1,11]
59 XO_IN SPMI_DATA 76 PMIC_SPMI_DATA [1,11]

VREG_S3A_1P8 33 MPP01
34 MPP02 PON_1 61 PON_OUT [11,15]
78 MPP03
86 MPP04
OPT_1 52
32 VDD_MSM_IO OPT_2 51

49 GND
58 GND NC1 43
NC2 70

31 REF_BYP GND 30
24 REF_GND GND 38
GND 39
C1501 40
100NF GND
13 GND GND 48
14 GND GND 56
15 GND GND 57
21 GND GND 65
22 GND GND 66
23 GND GND 67
29 GND GND 74
GND 75
GND 84
GND 85

PM8841

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 15_PM8841_CONTROL&VREG Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:15 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

VPH_PWR
VPA_APT

VPH_PWR
D D

VDD_1P8

C1606 C1602 C1603 C1604

C1605
2.2UF
22PF 10NF 22uF 22PF
100PF
C1607 33PF C1608
33PF C1650
U1601
[22] WTR0_TX_MB3 SKY77633

11 VBATT VIO 6
C1609 26 8 RFFE1_CLK [2,16,17,19,23]
VCC_GSM SCLK
28 VCC1 SDATA 9 RFFE1_DATA [2,16,17,19,23]
n.m 27 VCC2

SKY77633
C1613 33PF 1 35
C1616 RFIN_B1_B2 RFOUT_B1 B1_PASM_TX [17]
33PF 34
RFOUT_B3 B3_PA_OUT [18]
[22] 2 RFIN_B3_B4 RFOUT_B4 33 TD_PA_OUT
WTR0_TX_MB4 [18]
RFOUT_B2 32 B2_PASM_TX [17]
C1620 3 RFIN_B20_B26
RFOUT_B5_B26 31 B5_PASM_TX [17]
n.m 4 RFIN_B5_B8 RFOUT_B8 29
B8_PASM_TX [17]
RFOUT_B20 30 B20_PA_OUT [18]

13 RFIN_GSM_HB RFOUT_GSM_HB 24 GSM_HB_PAOUT [17]

RFOUT_GSM_LB 22 GSM_LB_PAOUT [17]
14 RFIN_GSM_LB
33PF 33PF
C1610 C1611
20 GND GND 21
[22] WTR0_TX_LB3 19 GND GND 23
18 GND GND 25
17 GND GND 36
16 GND GND 37
15 GND GND 38
C1612 12 39
GND GND
10 GND GND 40
C n.m 7 GND GND 41 C
5 GND GND 42
EP_GND 43
33PF 33PF
C1614 C1651
[22] WTR0_TX_LB1

C1615

n.m

33PF 33PF
C1617 C1618
[22] WTR0_TX_MB2

C1619

n.m

33PF

NCP03WF104F05RL
33PF
C1621 C1653 PLACE NEAR B7 PA
PA_THERM0 [11]
[22] WTR0_TX_LB2

R1601
C1622

n.m

B B
VPH_PWR

VPA_APT
VDD_1P8

R1602
U1602
3R3

C1627 C1628 C1629 18 C1624

2.2UF VCC2 23 R1603
100PF 100NF 20 VCC1 RFIN_2_5_GHZ WTR0_TX_HB1 [22]
21 VBATT 33PF
2.2nH

C1626
1.2PF
B41_TX 9 B41_PA_OUT [18]
24 VIO B38_TX 10
2 SCLK B40_TX 12 B40_PA_OUT [18]
[2,16,17,19,23] RFFE1_CLK
1 SDATA B7_TX 14 B7_PA_OUT [18]
[2,16,17,19,23] RFFE1_DATA
C1638 C1639 C1630
33PF C1632 C1633
100NF 33PF 1.2nH
33PF
16 NC1 B38/41_RX 6 WTR0_PRX_HB2 [22]
22 NC2 B40_RX 7

R1604
1.2nH
13 GND GND 3
15 GND GND 4
17 5 C1634
GND GND 33PF
19 GND GND 8
25 GND GND 11

SKY77814 33PF
C1636 C1637
1nH
WTR0_PRX_HB1 [22]

A A
R1605
3nH COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 16_RF_SKY77633+SKY77814 Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:16 OF 36
 6 5 4 3 2 1

REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

B1_PASM_TX [16]

C1701

22PF
L1701

L1702
n.m

n.m
C1703
WTR0_PRX_HMB4 [22]
1.2nH

C1702

33PF
C1750
2.4nH

B2_PASM_TX [16]

22PF
C1706
L1703

L1704
9.1nH
n.m
C1711

VREG_L16_2P7
WTR0_PRX_MB3 [22]

VDD_1P8
3nH

C1710

33PF
[2,16,19,23] C1751
RFFE1_CLK
n.m

B5_PASM_TX [16]
[2,16,19,23] RFFE1_DATA

C1712
2.7nH
C C

L1705

L1706
n.m

n.m
100NF 100PF 100PF C1708 100PF

C1713 C1714 C1704 100PF

C1705
U1702
1 SCLK TRX1 3 B7_PASM_TRX [18]
34 VIO C1717

33PF
35 SDATA TRX2 13 B40_PASM_TRX [18] WTR0_PRX_LB3 [22]
33 VDD
U1701 8.2nH

C1716
TRX3 14 B41_PASM_TRX [18]
HHM22106B1
16 TD_PASM_RX [18] C1753
1 3 TRX4
[26] PRIMARY_ANT OUTPUT IN 29 ANT n.m
TRX5 17 B3_PASM_TRX [18] B8_PASM_TX [16]
C1719

1.0nH
C1720
1.8nH

4 HHM22106B1 6

C1718
19

1.0nH
CPOUTPUT 50_OHM B1_TX
L1709

GND

GND
82nH

L1710

L1711

L1707

L1708
2.7PF

10nH
n.m

n.m
B1_RX 4
R1704
2

51R
B2_TX 20

B2_RX 7

B5_TX 21 C1723
[22] WTR0_TX_PDET_CPL WTR0_PRX_LB2 [22]
B5_RX 12
22nH

C1722
40

33PF
GND
39 GND B8_TX 22
38 C1754
GND
37 GND B8_RX 15
36 n.m
GND
32 GND GSM_HB_RX 6
31 GND
30 GND GSM_HB_TX 23 GSM_HB_PAOUT [16]
28 GND

C1724
18 24

22PF
GND GSM_LB_TX
11 GND

L1712

L1713
n.m

n.m
10 GND TRX6 25
9 GND
8 GND TRX7 26 TD_PASM_TX [18]
5 GND
2 GND TRX8 27 B20_PASM_TRX [18]
LMSW54GM-F96TEMP
LMSW54GM-F96TEMP
GSM_LB_PAOUT [16]

C1726

22PF
B B

L1714

L1715
n.m

n.m
A A

COMPANY:
Lenovo

TITLE:

LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21

CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>

QUALITY CONTROL: DATED:

<Code> D Rev.0.2
<QC By> <QC Date> 17_RF_ASM

RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 17
OF 36
 6 5 4 3 2 1

REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

TDS TX&RX B3 TRX

22PF
C1876

[16] B3_PA_OUT

C1821 C1820

22PF U1808 22PF

C1871 C1872 n.m n.m

GND2
GND1
3 OUT/IN IN/OUT 1 TD_PA_OUT [16]
[17] TD_PASM_TX

C1870 C1875

4
2
DEA162025LT-5046E1 C1873 C1874 U1802 3.9PF
SAYEY1G74BA0B0A C1808
n.m n.m 33PF
n.m n.m C1811 C1803 3 TX ANT 6 [17]
B3_PASM_TRX
1 RX
[22] WTR0_PRX_MB2

GND
GND
GND
GND
GND

C1804
6.8nH C1812

2.7nH
C1859
n.m 1.5PF

2
4
5
7
8
22PF U1805 22PF
C1829 C1801
C1832
1 6
[17] TD_PASM_RX UNBAL UNBAL WTR0_PRX_MB1 [22]
2.0nH
C1802

C1880

4.3NH
C1866
n.m 1.8nH
2 SAWFD1G90KZ0F0A 7
GND GND
3 8
GND GND
4 9
GND GND
C 5
GND GND
10
B20 TRX C

SAWFD1G90KZ0F0A 22PF
U1804 22PF
C1837 SAYEY806MBA0F0A C1806
[16] B20_PA_OUT 3 TX ANT 6 [17]
B20_PASM_TRX
1 RX

GND
GND
GND
GND
GND
C1840 C1839 C1828 C1807

n.m n.m 6.8nH n.m

2
4
5
7
8
33PF
L1801 C1805
[22] WTR0_PRX_LB1
18nH
C1856

TDD TRX n.m

1nH U1801
C1886 2.4nH
2

C1844
4
G

[17] B41_PASM_TRX OUT

IN 1 B41_PA_OUT [16]
3 G
B7 TRX
G

C1849
5

C1883
L1803
4.7nH

n.m

1.0pF 2.2nH C1841

SAFEA2G60MA0F0A U1806 1nH
C1846
SAYEY2G53BA0F0A
[16] B7_PA_OUT 3 TX ANT 6 B7_PASM_TRX [17]
1 RX

GND
GND
GND
GND
GND
C1848 C1847 C1842 C1843

0.5PF n.m 3nH 6.8nH

2
4
5
7
8
B B

SAFEA2G35MF0F0A 33PF
1.5nH U1807 C1852
C1855 C1853
4 [22] WTR0_PRX_HB3
[17] B40_PASM_TRX ANT 2.7nH
22PF
5 C1854 C1860
GND3
L1805
5.6nH

1 n.m
3 PA B40_PA_OUT [16]
GND2
2 C1857
GND1
C1858
4.7nH

n.m
SAFEA2G35MF0F0A

A A

COMPANY:
Lenovo

TITLE:

LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21

CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>

QUALITY CONTROL: DATED:

<Code> D Rev.0.2
<QC By> <QC Date> 18_RF_PRX

RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 18
OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D
DRX 1
U1910

IN OUT
RX FILTER B40
4
C1942
WTR0_DRX_HB1 [22]
D

C1939

C1940

2.2nH
3nH
C1941
2 GND n.m
10nH 3 GND
5 GND
SAFFB2G35AA0F0A

U1908
1 IN OUT 4 WTR0_DRX_HB3 [22]
RX FILTER B7

C1929
3.3nH

C1930

22PF
C1931 C1932
2 GND
6.8nH 3 GND n.m
5 GND
SAFFB2G65AA0F0A
SAFFB2G65AA0F0A

U1903
1 IN OUT 4 WTR0_DRX_HB2 [22]

C1911

C1912
SAFFB2G60AA0F0A

2.4nH
12PF

C1914

0.5pF
2 GND

C1913

2.7nH
3 GND
5 GND

SAFFB2G60AA0F0A
RF4 7
6

4
RF5

RF6

GND

15
GND 3
SCLK RFFE1_CLK [2,16,17,23]
8 GND 2
SDATA RFFE1_DATA [2,16,17,23] VDD_1P8
[19] DIV_ANT 9 RF1656
ANT 1
10 VIO
RF1 C1916
U1904
VDD
RF2

RF3

33PF U1911
ID

L1906
1 4
11

12

13

14

VREG_L16_2P7 [19] B20_DRX_ASMIN IN OUT WTR0_DRX_LB2 [22]

C RX FILTER B20 C1943 22nH C
C1918
C1925 2 2.2PF
U1909 GND1
SAFFB2G14AA0F0A n.m 3 GND2
33PF 5 GND3
SAFFB806MAA0F0A
1 4
PORT1 PORT2 WTR0_DRX_HMB4 [22]
C1937
C1935

C1936
22PF
22PF
C1938
n.m 2 GND
3nH
U1901 5
3 GND
SAFFB1G84AB0F0A GND

1 UNBAL1 UNBAL2 4 WTR0_DRX_MB3 [22]

C1915
3.3nH
C1906

C1910
C1909 2 2.2nH
GND1 n.m
n.m
3 GND2 GND3 5

SAFFB1G84AB0F0A

C1904
C1905

3nH

0.5PF
IN

C1917
2 5
GND GND
n.m
SAFFB1G90KA0F0A
3 4
GND OUT WTR0_DRX_MB1 [22]
C1908
C1907

22PF

B20_DRX_ASMIN [19] U1902

SAFFB1G90KA0F0A n.m

B B

GPS U1913
B8636

BEIDOU/GPS/GLONASS_OUT 4
VREG_L16_2P7

L1907 39nH R1902

EXT_GPS_LNA_EN [2]
0R
[26] DIV_HMB_ANT 1 ANT_INPUT
C1944 C1945
CELL_OUTPUT 9
DIV_ANT [19]
27PF 27PF
GND
GND
GND
GND
GND
GND
GND

B8636
2
3
5
6
7
8
10

U1912
U1914 L1902 10nH
BGU8009 WTR0_GPS_RF_M [22]

6
SAFFB1G56FA0FT1
2

C1901
VCC

ENABLE

18PF
L1920

9.1nH

3 C1903
OUT1
4
1

R1904 OUT2 1PF

L1908 5.6nH 5 3 1
RFIN BGU8009 RFOUT IN
0R 2
C1946

18PF

C1949 GND_RF C1951 GND1 L1901 10nH

5 WTR0_GPS_RF_P [22]
GND2
GND

C1902

18PF
n.m n.m

SAFFB1G56FA0FT1
1

4
L1910

n.m

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 19_RF_DRX&GPS Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:19 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

WTR POWER DISTRIBUTION 1.8V & 2.0V WTR POWER DISTRIBUTION 1.225V

D D

Indicates star connections

VREG_L15_2P05

VREG_L4_1P3
L2001
Pin 54
VDD_RF2_D_BB [20,21]
0R L2002
4.7UF 0R
Pin 129 PIN 25
C2001 VDD_RF2_D_BB [20,21] 22uF VDD_RF1_P_HB_LO [20,21]
C2004
100PF C2002
C2003
100NF
L2003
PIN 79
[21] VDD_RF1_P_PLL
Pin 98 [20,21] PIN 78 22nH
VDD_RF2_D_BB [20,21] VDD_RF1_P_HB_LO
Pin 126 PIN 48 PIN 31
VDD_RF2_D_BB [20,21] [20,21] VDD_RF1_P_HB_LO VDD_RF1_P_HB_LO [20,21]
100PF [20,21] VDD_RF1_P_HB_LO PIN 90 PIN 72
VDD_RF1_P_HB_LO [20,21]
C2005 100NF 100NF PIN 38
100NF
100NF VDD_RF1_P_HB_LO [20,21]
C2006 C2010
C2007 C2008 C2009
C 100NF
C
Pin 80
VDD_RF2_D_BB [20,21]
Pin 62
VDD_RF2_D_BB [20,21]
L2004 PIN 14
Pin 157 PIN 137
VDD_RF2_D_BB [20,21] [21] VDD_RF1_T_DA VDD_RF1_P_HB_LO [20,21]
8.2nH C2014
C2011 C2012 C2013
PIN 149 100NF
100NF [20,21] VDD_RF1_P_HB_LO
100NF 100NF

[20,21] VDD_RF1_P_HB_LO PIN 115

PIN 11
VDD_RF1_P_HB_LO [20,21]
C2015 100NF
PIN 22
Pin 114 VDD_RF1_P_HB_LO [20,21]
VDD_RF2_D_BB [20,21] 100NF C2016
PIN 57
VDD_RF1_P_HB_LO [20,21]
Pin 147 C2017
VDD_RF2_D_BB [20,21]
C2018 PIN 135 100PF
[20,21] VDD_RF1_P_HB_LO
100NF PIN 136
[20,21] VDD_RF1_P_HB_LO
PIN 34
C2019 C2020 VDD_RF1_P_HB_LO [20,21]

Pin 116 100PF PIN 52

VDD_RF2_D_BB [20,21] 100NF VDD_RF1_P_HB_LO [20,21]
C2021
4.7NF 100NF PIN 59
VDD_RF1_P_HB_LO [20,21]
C2022

Pin 100 PIN 93

VREG0_1P8 VDD_RF2_D_BB [20,21] VDD_RF1_P_HB_LO [20,21]
C2023
Indicates star connections 100NF

PIN 74
VDD_RF1_P_HB_LO [20,21]

R2001 Pin 103

VDD_DIO [21]
0R
C2024
B 1uF B

1.8V load switch

VREG_S3A_1P8
VREG_S3A_1P8_RF
U2001 TPS22913B

TPS22913B
A2 A1
VIN VOUT

R2002
B2 B1
[1,27] MSM_RESOUT_N ON GND
0R

VREG0_1P8
VREG_S3A_1P8_RF

R2003

0R VDD_1P8

R2004

0R

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 20_RF_WTR1625_POWER Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:20 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

U2201-D
PWR
[20,21] 90 129 U2201-E
VDD_RF1_P_HB_LO VDD_RF1_P_VCO VDD_RF2_T_DA VDD_RF2_D_BB [20,21]
GND
[20,21] VDD_RF2_D_BB 80 VDD_RF2_P_VCO VDD_RF1_T_DA 137 VDD_RF1_T_DA [20]
89 GND_3 GND_48 111
[20,21] VDD_RF1_P_HB_LO 25 VDD_RF1_P_HB_LO VDD_RF1_T_UPC 136 VDD_RF1_P_HB_LO [20,21] 56 GND_4 GND_28 101
83 GND_5
[20,21] VDD_RF1_P_HB_LO 72 VDD_RF1_P_LB VDD_RF1_T_LO 135 VDD_RF1_P_HB_LO [20,21] 82 GND_6 GND_29 110
58 145
C [20,21] 34 126 35
GND_7 GND_30
144
C
VDD_RF1_P_HB_LO VDD_RF1_P_HMB VDD_RF2_T_BB VDD_RF2_D_BB [20,21] GND_8 GND_31
8 GND_9 GND_32 143
[20,21] VDD_RF1_P_HB_LO 57 VDD_RF1_P_HMB_LO 26 GND_10 GND_33 128
64 GND_11 GND_34 120
[20] VDD_RF1_P_PLL 79 VDD_RF1_P_PLL 42 GND_12 GND_35 119
VDD_RF2_FBRX 116 VDD_RF2_D_BB [20,21] 41 GND_13
[20,21] VDD_RF2_D_BB 98 VDD_RF2_P_BB 81 GND_14
VDD_RF2_T_VCO 157 [20,21] 21 GND_15 GND_36 106
VDD_RF2_D_BB
[20,21] VDD_RF2_D_BB 100 VDD_RF2_P_PRX GND_37 150
VDD_RF1_T_VCO 149 VDD_RF1_P_HB_LO [20,21] 6 GND_16 GND_38 134
24 GND_17 GND_39 159
VDD_RF1_T_SYN 115 [20,21] 39 GND_18 GND_40 142
14 VDD_RF1_P_HB_LO 10 125
[20,21] VDD_RF1_P_HB_LO VDD_RF1_D_LB_LO GND_19 GND_41
VDD_RF2_T_PLL 114 3 GND_20 GND_42 124
VDD_RF2_D_BB [20,21]
[20,21] VDD_RF1_P_HB_LO 38 VDD_RF1_D_LOM 23 GND_21 GND_43 148
46 GND_22
[20,21] VDD_RF1_P_HB_LO 31 VDD_RF1_D_LB 49 GND_23 GND_44 158
69 GND_24 GND_45 133
[20,21] VDD_RF1_P_HB_LO 22 VDD_RF1_D_HB VDD_RF1_G_LNA 52 VDD_RF1_P_HB_LO [20,21] GND_46 112

[20,21] VDD_RF1_P_HB_LO 11 VDD_RF1_D_MB VDD_RF1_G_VCO 74 [20,21] 88 GND_26

VDD_RF1_P_HB_LO
70 GND_27 GND_47 132
[20,21] VDD_RF2_D_BB 54 VDD_RF2_D_BB VDD_RF1_G_PLL 93 VDD_RF1_P_HB_LO [20,21]
63 GND_54
VDD_RF1_G_BB 59 VDD_RF1_P_HB_LO [20,21] GND_55 45
40 GND_49
GND_8 113 47 GND_50 GND_56 66
GND_57 84
[20,21] VDD_RF1_P_HB_LO 48 VDD_RF1_S_VCO 87 GND_51
77 GND_52 GND_58 75
[20,21] VDD_RF2_D_BB 62 VDD_RF2_S_VCO VDD_RF2_XO 147 VDD_RF2_D_BB [20,21]
96 GND_53 GND_59 164
[20,21] VDD_RF1_P_HB_LO 78 VDD_RF1_S_PLL VDD_DIO 103 VDD_DIO [20]

WTR1625L
WTR1625L

B B

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 21_RF_WTR1625_VDD&GND Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:21 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

WTR1625 TX & GND PINS

U2201-A
PRX
PRX_B20/17 102 U2201-B
[18] WTR0_PRX_LB1 PRX_LB1_IN
99 WTR0_BB_PRX_IP [4] DRX_GPS
PRX_B8/GSM900 PRX_BB_IP
[17] WTR0_PRX_LB2 92 PRX_LB2_IN PRX_BB_IM 108 WTR0_BB_PRX_IM [4] 5 DRX_LB1_IN
PRX_BB_QP 107 WTR0_BB_PRX_QP DRX_B20 DRX_BB_IP 76 WTR0_BB_DRX_IP [4]
PRX_B5/BC0_GSM850 [4]
[17] WTR0_PRX_LB3 73 PRX_LB3_IN PRX_BB_QM 97 [19] WTR0_DRX_LB2 15 DRX_LB2_IN DRX_BB_IM 86 WTR0_BB_DRX_IM [4]
WTR0_BB_PRX_QM [4]
DRX_BB_QP 61 WTR0_BB_DRX_QP [4]
65 PRX_LB4_IN 16 DRX_LB3_IN DRX_BB_QM 68
WTR0_BB_DRX_QM [4]
7 DRX_LB4_IN

32 DRX_LB_CA_OUT
C 91 PRX_LB_CA_OUT
C
29 DRX_MB_CA_IN
50 PRX_MB_CA_IN
DRX_B39
[19] WTR0_DRX_MB1 28 DRX_MB1_IN
20 DRX_MB2_IN
[18] PRX_B4 /B34/B39 51
WTR0_PRX_MB1 PRX_MB1_IN DRX_B2/B3
[19] WTR0_DRX_MB3 1 DRX_MB3_IN
PRX_B3/GSM1800 43
[18] WTR0_PRX_MB2 PRX_MB2_IN DRX_B1/B4 2
PRX_B2/BC1/GSM1900 [19] WTR0_DRX_HMB4 DRX_HMB4_IN
[17] WTR0_PRX_MB3 27 PRX_MB3_IN
PRX_B1 [19] DRX_B40
[17] WTR0_PRX_HMB4 19 PRX_HMB4_IN WTR0_DRX_HB1 4 DRX_HB1_IN
[19] DRX_B38/B41 12
WTR0_DRX_HB2 DRX_HB2_IN
WTR0_PRX_HB1 PRX_B40 9 [19] WTR0_DRX_HB3 DRX_B7 13 60
[16] PRX_HB1_IN DRX_HB3_IN GNSS_BB_IP WTR0_GPS_BB_IP [4]
GNSS_BB_IM 53 WTR0_GPS_BB_IM [4]
WTR0_PRX_HB2 PRX_B38/41 17 30 67
[16] PRX_HB2_IN DRX_HB_CA_OUT GNSS_BB_QP WTR0_GPS_BB_QP [4]
GNSS_BB_QM 85 WTR0_GPS_BB_QM
PRX_B7 [4]
[18] WTR0_PRX_HB3 18 PRX_HB3_IN [19] WTR0_GPS_RF_P 36 GNSS_INP

[19] WTR0_GPS_RF_M 44 GNSS_INM DNC 37

33 PRX_HB_CA_OUT
WTR1625L

WTR1625L

U2201-C
TX

[4] 151 162 TX_BCO/B5/B8 [16]

WTR0_BB_TX_IP TX_BB_IP TX_LB1_OUT WTR0_TX_LB1
160 153 TX_GSM850/900 WTR0_TX_LB2[16]
[4] WTR0_BB_TX_IM TX_BB_IM TX_LB2_OUT
152 163 TX_B20/B17
[4] WTR0_BB_TX_QP TX_BB_QP TX_LB3_OUT WTR0_TX_LB3
[16]
[4] WTR0_BB_TX_QM 161 TX_BB_QM TX_LB4_OUT 154
[4] WTR0_BB_TX_IDAC 127 DAC_REF

B B
[2] WTR0_GSM_TX_PHASE_D[0] 123 GP_DATA0 TX_MB1_OUT 146
104 138 TX_GSM1800/1900 WTR0_TX_MB2 [16]
[2] WTR0_GSM_TX_PHASE_D[1] GP_DATA1 TX_MB2_OUT TX_BC1/B1/B2
141 GP_DATA2 TX_MB3_OUT 139 WTR0_TX_MB3 [16]
155 TX_B3/B4/B34/B39
TX_MB4_OUT WTR0_TX_MB4[16]
94 GND_1
130 TX_B7
TX_HB1_OUT WTR0_TX_HB1[16]
R2201
71 RTUNE
4.75K TX_HB2_OUT 121

140 GND_2
55 GND_3
118 GND_4
ADC_IN 109
3dB atten 22PF
WTR0_SSBI1_TX_GPS
[2] 105 SSBI_TX_GNSS C2201
R2202
[2] 95 SSBI_PRX_DRX PDET_RFFB 117 WTR0_TX_PDET_CPL [17]
WTR0_SSBI2_PRX_DRX
18R
5%
R2203

R2204

1NF
300R

300R

C2202 156 5% 5%
GND_5
R2205
[11] XO_OUT_A0 131 XO_IN
0R GND_6 122
WTR1625L
C2203

n.m

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 22_RF_WTR1625_TX&RX Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:22 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

VPH_PWR

VDD_1P8

U2301 C2301

14 15 10uF
BYP_BATT VDD_BATT
10 16
BYP_LOAD VDD_BATT

28 5
VDD_BUCK VDD_GP

C2302
10uF 27 17
GND_BUCK VDD_1P8
C C
VPA_APT
7 23 L2301 1.5uH
NC VSW_BUCK
2
NC
4
AMP_OUT
R2302
26
[2,16,17,19] RFFE1_DATA SDATA
0R 11 C2303
C_BUCK
R2303
[2,16,17,19] 21 12 4.7UF
RFFE1_CLK SCLK C_BUCK
0R
8
13 C_SW_BUCK
MPP1 9
C_SW_BUCK

20
VSW_BOOST 6
C_GSM
VPH_PWR
19
USID_LSB 18
PA_VBATT

22
GND 25
VOUT_BOOST

24
GND_BOOST 1
GND VPH_PWR
C2304
3
GND
22UF
QFE1101

B B

A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 23_RF_QFE1100 Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:23 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

WIFI/BT TRX
VPH_PWR
2PF U2401 TFSC06054125-2113A1
FM_RX L2401
L2402 n.m
C2405 U2402 [24] FM_RX FM_RX_ANT [34]
C2406 C2407 C2408 0R n.m
6 HFP R2401
22uF 1uF 2 3 4 C2401
L2406 CP OUT IN WIFI_ANT1 [26]

L2403
C2409

n.m
100PF 0R n.m
[24] 4 LFP GND 1 R2404
WL_EXTPA_CTRL0
n.m GND 3 2 50_OHM CPLD 1
5 C2402
[24] WL_EXTPA_CTRL1 GND 49.9R
100PF 100PF
U2404 DPX165950DT-8126A1 n.m
TFSC06054125-2113A1
7 2
D
C2410 C2415
13
PA_EN VCC2
3
RB886CST2RA R2405
D
SW_CTL VCC1
12 LNA_EN PDET_IN_WL [24]
C2413 9
VBAT 1K
2.7PF
[24] WL_5GHZ_TX 5 TX D2401 1NF
18PF C2411

R2406
15

R2403
C2414 ANT

n.m
11 RX C2412

n.m
4 GND NC 1
6 GND GND 14
8 GND GND 16
2.7PF 10 17
C2416 GND THERM_PAD
RFFM8506
[24] WL_RFIO_5G

C2442 5pF

n.m
L2405
U2403 C2404

4
SAFEA2G45MB0F0A

GND

RF2
R2402 3nH
L2404 15PF 1
[24] WL_BT_RFIO_2P4G RF1
8.2pF

GND

GND
C2403

3
10nH SAFEA2G45MB0F0A

VREG_L11_1P25
Pin 9
VDD_BT_RF_1P3 [24]

3680 power supply VREG_S3A_1P8 VSMPS_1P8

VDD_WLAN_1P3 R2407

0R
C2418 C2417
Pin 78
VDD_BT_RF_1P3 [24]

R2408 100PF
C VDD_IO_1P8 [24] 100PF
0R
470NF
Pin 40 Pin 6
C2419 VDD_BT_RF_1P3 [24]
10NF C2421 C
C2420
VREG_L6_1P8 VLDO_1P8 100PF
R2409
VDD_XO_1P8 [24]
0R
Pin 59
470NF VDD_BT_RF_1P3 [24]
C2422 4.7UF
100PF
C2423 C2424

VDD_MODEM_1P2 [24]
L2407 pin 50
VDD_WL_LO_1P3 [24]
4.7UF BLM03HG102SN1 22uF
C2427 100PF
C2425
C2426
10NF C2428
BLM03AX241SN1B

pin 3
VDD_BT_RF_1P3 [24]
pin 11 C2430
[13,24] VDD_WL_2GPA_3P3 VDD_WL_2GPA_3P3 [13,24] 22uF
C2429 10NF
pin 73
VDD_WL_2GPA_3P3 [13,24]
22uF 100NF 22uF 10NF
C2432 C2433 pin 17
C2431 VDD_BT_RF_1P3 [24]
C2434
C2435
10NF
R2411 pin 4
VDD_BT_TXRF_3P3 [24]
0R C2436
n.m Pin 69,74,75
VDD_BT_RF_1P3 [24]
C2437 C2438
10NF
10NF

B B
Pin 54
VDD_BT_RF_1P3 [24]

C2439

10NF

Note: As no short bar add in this design so that no alias can be

used. All 1.3v voltage named as VDD_BT_RF_1P3. Refer

WCN3680
U2405-B
PWR_GND
U2405-A
CONTROL [24] VDD_IO_1P8 35 76
VDD_IO_1P8 GND_1
[24] VDD_XO_1P8 26 VDD_XO_1P8 GND_2 42
48MHZ 8 GND VDD_WL_LO_1P3 32 VDD_WL_LO_1P3 [24] [24] VDD_MODEM_1P2 30 VDD_DIG_1P2 GND_3 67
GND_4 55
31 XO_IN WL_PDET_IN 16 PDET_IN_WL [24] [24] VDD_BT_RF_1P3 74 VDD_FM_RXFE_1P3 GND_6 62
Y2401 43 XO_OUT WL_RF_DA_OUT 47 WL_5GHZ_TX 54 VDD_FM_RXBB_1P3 GND_7 15
C2440 72 [24] 69 13
WL_RFIO_5G WL_RFIO_5G [24] VDD_FM_PLL_1P3 GND_8
1 IN OUT 3 75 VDD_FM_VCO_1P3 GND_9 2
9.1PF FM_RX 61 FM_HS_RX WL_BB_IP 58 WLAN_IP GND_10 20
2 4 [24] 64 [4] 4 10
GND GND 12PF WL_BB_IN WLAN_IM [4] [24] VDD_BT_TXRF_3P3 VDD_BT_TXRF_3P3 GND_11
[2] WCSS_FM_SSBI 48 FM_SSBI WL_BB_QP 51 WLAN_QP 3 VDD_BT_RXRF_1P3 GND_12 1
C2441 41 57 [4] 14 18
[2] FM_DATA FM_DATA WL_BB_QN WLAN_QM [4] [24] VDD_BT_RF_1P3 VDD_BT_BB_1P3 GND_13
CX2016DB48000C0FLHA1 17 VDD_BT_PLL_1P3 GND_14 39
NC_3 28 [24] VDD_BT_RF_1P3 7 VDD_BT_VCO_1P3 GND_15 37
WL_BT_RFIO_2P4G 5 GND_16 44
WL_BT_RFIO_2P4G [24]
[2] BT_CTL 19 BT_CTL [24] VDD_BT_RF_1P3 25 VDD_BT_FM_DIG_1P3 GND_17 38
CLK_OUT 36 WCSS_XO [1] GND_18 79
[2] WCSS_BT_SSBI 24 BT_SSBI [24] VDD_BT_RF_1P3 45 VDD_WL_BB_1P3 GND_19 21
[2] BT_DATA 29 BT_DATA [24] VDD_BT_RF_1P3 6 VDD_WL_2GPA_1P3 GND_20 65
50 VDD_WL_PLL_1P3 GND_21 22
[24] VDD_WL_LO_1P3
WL_CMD_SET 63 WCSS_WLAN_SET [2] 40 VDD_WL_UPC_1P3 GND_22 66
56 WL_EXTPA_CTRL4 WL_CMD_CLK 33 WCSS_WLAN_CLK [2] GND_23 23
68 WL_EXTPA_CTRL3 [24] VDD_BT_RF_1P3 9 VDD_WL_2GLNA_1P3 GND_24 12
A 49 WL_EXTPA_CTRL2 WL_CMD_DATA2 77 WCSS_WLAN_DATA_2 [2] 78 VDD_WL_5GLNA_1P3 GND_25 53 A
[24] WL_EXTPA_CTRL1 34 WL_EXTPA_CTRL1 WL_CMD_DATA1 70 WCSS_WLAN_DATA_1 [2] GND_26 60
[24] WL_EXTPA_CTRL0
52 WL_EXTPA_CTRL0 WL_CMD_DATA0 71 WCSS_WLAN_DATA_0 [2] [24] VDD_BT_RF_1P3 59 VDD_WL_5GPA_1P3 GND_27 46 COMPANY:
GND_28 27 Lenovo
[13,24] VDD_WL_2GPA_3P3 11 VDD_WL_2GPA_3P3
WCN3680B [13,24] VDD_WL_2GPA_3P3 73 VDD_WL_5GPA_3P3
WCN3680B
TITLE:
WCN3680B
WCN3680B LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 24_RF_WIFI&BT Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:24 OF 36
 6 5 4 3 2 1

REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

C C

B B

A A

COMPANY:
Lenovo

TITLE:

LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21

CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>

QUALITY CONTROL: DATED:

<Code> D Rev.0.2
<QC By> <QC Date> 25_RF_NC

RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 25
OF 36
 6 5 4 3 2 1

REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

JP2601
MM8030-2610

1 RX/TX
INT
3 G

4 G
J2601

2
MM8030-2610

GND2

C2612

39PF
MAIN ANT GND3 CONTACT PRIMARY_ANT [17]

GND1
C2601 C2610

818000500 n.m n.m

DRX ANT JP2602

MM8030-2610

1 RX/TX
C C

INT
1

3 G

4 G
ANT3506 ANT2603

2
MM8030-2610
PIN_ANT_818001475 PIN_ANT_818001475
818001475
2

R2603 R2610 0R
L2603

1 2 [19]
DIV_HMB_ANT
0

3.3nH C2604
1

C2605
C2606

L2601

n.m
n.m
n.m

JP2603

MM8030-2610

1 RX/TX
INT
1

3 G

4 G
ANT2604 ANT2605

2
PIN_ANT_818001475
PIN_ANT_818001475

WIFI ANT 818001475 818001475

C2609 1nH R2604

WIFI_ANT1 [24]
0R
C2607 C2608
B B
8.2nH
n.m

A A

COMPANY:
Lenovo

TITLE:

LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21

CHECKED: DATED:
CODE: SIZE: DRAWING NO: REV:
<Checked By> <Checked Date>

QUALITY CONTROL: DATED:

<Code> D Rev.0.2
<QC By> <QC Date> 26_RF_ANT

RELEASED: DATED:
<Released By> <Release Date> SCALE: <Scale> SHEET: 26
OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

U2701-B
FLASH MEMORY
NC71 J13
NC72 J14
NC73 K1 VREG_S3A_1P8
NC74 K2 VCC_EMMC
NC75 K3
NC76 K12
K13 R2701 1 2 0R
NC77
NC78 K14
A1 NC9 NC79 L1
A2 NC10 NC80 L2
A8 NC11 NC81 L3 VCC_EMMC
A9 NC12 NC82 L12
A10 NC13 NC83 L13
A11 NC14 NC84 L14 U2701-A
A12 NC15 NC85 M1
A13 M2 Removed the DNIed pull-ups on SDC1_DATA(x) FLASH MEMORY
NC16 NC86
A14 NC17 NC87 M3 VCCQ C6
VCC_EMMC C2701 C2702 VREG_L20_2P95
B1 NC18 NC88 M7 VCCQ M4
B7 M8 N4 2.2UF 100NF
NC19 NC89 VCCQ
B8 NC20 NC90 M9 VCCQ P3
B9 NC21 NC91 M10 VCCQ P5
B10 NC22 NC92 M11 R2703
B11 M12 E6 1 2

R2702
NC23 NC93 VCC

10K
B12 NC24 NC94 M13 VCC F5 0R
C B13 NC25 NC95 M14 VCC J10 C
B14 N1 [1,20] MSM_RESOUT_N R27041 2 0R K5 K9 C12704 C2703
NC26 NC96 RST_N VCC
C1 NC27 NC97 N3 [1] SDC1_CMD M5 CMD
C3 NC28 NC98 N6 M6 CLK VDDI C2 100NF
[1] SDC1_CLK 2.2UF
C7 NC29 NC99 N7
C8 NC30 NC100 N8 VSS C4
C9 NC31 NC101 N9 [1] SDC1_DATA_7 B6 D7 VSS E7
C10 N10 B5 G5 C2706 C2704
NC32 NC102 [1] SDC1_DATA_6 D6 VSS
C11 NC33 NC103 N11 [1] SDC1_DATA_5 B4 D5 VSS H10
C12 N12 SDC1_DATA_4 B3 K8 1uF n.m
NC34 NC104 [1] D4 VSS
C13 NC35 NC105 N13 SDC1_DATA_3 B2 D3 VSS N2
[1]
C14 NC36 NC106 N14 SDC1_DATA_2 A5 D2 VSS N5
D1 P1 [1] A4 P4
NC37 NC107 [1] SDC1_DATA_1 D1 VSS
D2 NC38 NC108 P2 SDC1_DATA_0 A3 D0 VSS P6
D3 P8 [1]
NC39 NC109
D4 NC40 NC110 P9 TP_0.3
D12 NC41 NC111 P11 <Value>
D13 NC42 NC112 P12
D14 P13 TP2701
NC43 NC113
E1 NC44 NC114 P14
E2 NC45
E3 NC46
E12 NC47
E13 NC48
E14 NC49
F1 NC50
F2 NC51
F3 NC52
F12 NC53
F13 NC54 RFU1 A6
F14 NC55 RFU2 A7
G1 NC56 RFU3 C5 For eMMC 5.0
G2 NC57 RFU4 E5
G12 NC58 RFU5 E8 EMMC_THERM [11]
G13 NC59 RFU6 E9
G14 NC60 RFU7 E10
H1 NC61 RFU8 F10
H2 G3 Place near U2701
NC62 RFU9
H3 NC63 RFU10 G10
H12 H5

R2705
NC64 RFU11 SDC1_RCLK [7]

n.m
H13 NC65 RFU12 J5
H14 NC66 RFU13 K6
J1 NC67 RFU14 K7
J2 NC68 RFU15 K10 R2706
J3 NC69 RFU16 P7 n.m
J12 NC70 RFU17 P10

<Value>

B B

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 27_EMMC Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:27 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

VCC_FUEL

VBATT

VPH_PWR

R2801

R2802
2.2K

2.2K
VCC_FUEL
VPH_PWR 6.3V 100NF
FUEL_I2C_SDA [28]
C2802 C2801
100NF VREG_S3A_1P8 FUEL_I2C_CLK [28]

D C2803 D

R2803
U2801

4.7K
R2804
1.8M
E1 E2

R2805
REGIN BAT

10K
1uF D1 D2
VCC CE

[2,28] GASGAUGE_I2C_SDA B3 SDA SOC_INT A2 FUEL_INT_N [2]

[2,28] GASGAUGE_I2C_SCL A3 SCL GND_SENSE_G [28]
B2 R28061 2 0R
BAT_GD FUEL_I2C_CLK [28]
R2807 18.2k E3 BI/TOUT
[28] BATT_THERM R2811 R28081 0R
1K D3 C3 2
TS BAT_LOW FUEL_I2C_SDA [28]
C2 B1 C2805
VSS_1 SRN 100NF
C1 VSS_2 SRP A1
C2806 BQ27530
33PF C2807 BQ27530 GND_SENSE_B [28]
100NF
differential trace, Shilding with GND
need to shield with Ground.
Route in differential pair and

Fuel Gauge
USB1_VBUS

VREG_S3A_1P8

C C

C2808
4.7UF VPH_PWR

2
R2826
L2801
U2802

10K

D2804

uClamp0571P
R2813 1 2 n.m
[2,28] GASGAUGE_I2C_SDA 1.2uH
1 VBUS SW 20

1
[2,28] R2825 1 2 n.m 24 VBUS SW 19
GASGAUGE_I2C_SCL C2810
C2809 4.7UF 23 PMID 47NF +V_CH_REGN C2811
BTST 21 22UF

CHRG_AGND
[28] FUEL_I2C_CLK 5 SCL
[28] FUEL_I2C_SDA 6 SDA
REGN 22
C2812
[2] CHG_INT_N 7 INT 1uF
VBATT
SYS 16
8 OTG/IUSB SYS 15
[11] CHG_OTG

[11] CHG_EN 9 CE
BAT 14
10 ILIM BAT 13 ¼æÈÝbq25892RTWR
[11] CHG_PSEL R28211 2 n.m PHONE_ON_N [11,30]

+V_CH_REGN C2813
2 PSEL TS1 11 R28171 2 0R 2.2UF
[2] CHG_STAT TS2 12
3 /PG
2 0R

2
R28241

R2814
4 STAT

8.2K
R2816

R2818
100K

100K
R2815

1
100K

2
25 GND PGND 18

R2819

R2920
PGND 17

220R

4.7K
1%

1%

16.2K

R2820
BQ24292I

RT2801

1%
47k*24.9/(47+24.9)=16.2k

N.M
VPH_PWR

R2921
CHRG_AGND
0R

B Slave address B

Charger=0x6B
CHRG_AGND

Charger

R2810 0R
[28] GND_SENSE_G
R2809 Change R2809 to Special res
0.01R
differential trace, Shilding with GND
R2812 0R
[28] GND_SENSE_B

JP2801
differential trace, Shilding with GND Near battery CON
R2822 0R VBAT_GND
[10] VBATT_SENSE
1
A
8
VBATT A
R2823 0R 2
A [10] BATT_ID B A
PM8941_CBLPWR_N R2837 1K 3
[11,35]
B COMPANY:
6 Lenovo
[28] BATT_THERM C
7
C
4 TITLE:
D2802

D2803
D2801

D
C2804 C2814 C2815 5 LPDDR3_CHANNEL0
D
DRAWN: DATED:
22UF 10PF
68pf Gul 2013/12/21
SD-505006-001
BATTERY CONN
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
GND

GND

GND

VBAT_GND <Checked By>

QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 28_CHARGING Rev.0.2

Battery Connector RELEASED: DATED:

<Released By> <Release Date> SCALE:<Scale> SHEET:28 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

VREG_LVS1_1P8

U2901 BMC156

[2,29] SENSORS1_I2C_SCL 12 SCK/SCL R2902

3 1 2
VDDIO
2 SDI/SDA 0R VREG_L18_2P85
[2,29] SENSORS1_I2C_SDA
PS 11 VREG_BOOST_BYPASS
5 DRDY VREG_L18_2P85
[2] COMPASS_DRDY
CSB 10
R2903
7 1 2
VDD
6 INT2 0R
[2] COMPASS_INT
VREG_LVS1_1P8

GND0

GND1

GND2
SDO
C2901

2
C2902
C2906

R2909
1

0R
100NF 100NF
100NF

1
U2902

R2901

10K
PS=0 SPI mode£»PS=1 I2C mode
1 4
SPI mode: CSB low,communication start,CSB high,communication stop VDD LEDA

C2907

C2908
5
I2C mode£º CSB SDO A-Sensor I2C adrress E-Compass I2C Address 2 LEDK
HIGH HIGH 0X11 0X13 [2] SENSORS2_I2C_SCL SCL 6
HIGH LOW 0X10(use) 0X12(use) LDR

100NF
8

1uF
[2] SENSORS2_I2C_SDA SDA
7 3
[2] PROXI_INT_N INT GND
AP3426M

D2901
n.m
D2902

D2903
n.m

n.m
GND
GND

GND
C C
E-compass+Acc

P-Sensor

VREG_LVS1_1P8

B VREG_LVS1_1P8
VREG_L18_2P85 B
R2908
R2910

C2911
U2904 100NF
BMG160 U2903
4
VDD 5
0R

R2905
0R

5 1 2 1
CSB [2] HALL_INT1_N OUT 3
VDDIO 10 0R NC
7 2
[2,29] SENSORS1_I2C_SCL SCK/SCL GND
C2912
[2,29] SENSORS1_I2C_SDA 9 SDI/SDA PS 6
27PF
BU52031NVX-TR
[2] GYRO_DRDY_INT 4 INT1
VDD 2
12 INT2
GNDIO

8
GND

SDO
NC

C2909
PS=0 SPI mode£»PS=1 I2C mode C2910
1

11

100NF
SPI mode: CSB low,communication start,CSB high,communication stop 100NF

I2C mode£º CSB SDO I2C adrress

Float High 0X69
Float GND 0X68(use)

Gyroscope sensor

Hall Sensor

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 29_SESORS Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:29 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

VREG_L9_UIM1

R3004
VREG_L9_UIM1

10K
VREG_S3A_1P8

UIM1_DATA [2]

C3003

C3004
2
R3020

10K

C3018
D3003

n.m
33PF

D3007
1uF

n.m
1
[35] UIM_DETECT_TP

A10
A11
A12
A13
A8

A9
JP3002

n.m
R3017 R3018
1 2 1 2

SW

GND
GND
GND
GND
GND
[2] UIM_DETECT
1K 1K A3 A7
[2] UIM1_CLK CLK1 I/O1

[2] UIM1_RST A2 SIM1 A6

RST1 VPP1
A1 A5
VCC1 GND

VREG_L10_UIM2
VREG_L10_UIM2

B3 B7
[2,35]UIM2_CLK CLK2 SIM2 I/O2

R3003

10K
B2 B6
[2,35] UIM2_RST RST2 VPP2
B1 B5
VCC2 GND

B9 GND
GND

B11 GND
GND
C3016

C3017
C-2288104-TEMP UIM2_DATA [2,35]

B8

B10
D3006

n.m
1uF
33PF
C3015

C3024
C3013
C3005

D3008

n.m
C3002

D3005
D3004
D3002

n.m
n.m
n.m
D3009

n.m

D3001

n.m

n.m

n.m
n.m
n.m
n.m
C C

GND
SIM CARD

PWR_KEY[35]

L3003
[11,28] PHONE_ON_N
68nH
B B
PESD5V0S1BSF

VREG_L21_2P95
D3512

JP3001
GND

2
2

R3016

0R
JP3004
VOLUME UP 3
504528-0892
L3001

1
[11] R3010 240R 4
VOL_UP_N
68nH 5
[1] SDC2_DATA_2 DAT2 GND
PESD5V0S1BSF

6 [1] SDC2_DATA_3 CD/DAT3 GND

D3511

7
8

AYF530635 [1] SDC2_CMD CMD GND

VDD GND
GND

[1] SDC2_CLK CLK GND

R3014 VSS GND

VREG_S3A_1P8
[35] 100K [1] SDC2_DATA_0 DAT0 GND
[11] R3012 n.m VOL_DN
VOL_DN_N
[1] SDC2_DATA_1 DAT1 GND
R3015
L3002 [2] SD_CARD_DET_N DET GND
R3013 240R
[11] PM_RESIN_N 1K
68nH

D3011

D3012

D3015
D3014
D3013
PESD5V0S1BSF

VOLUME DOWN

D3017
D3016
D3510

D3018
C3022
C3021
GND

1uF
33PF
n.m
n.m

n.m

n.m
n.m

n.m

GND
n.m

n.m
A A
COMPANY:
Lenovo

SD CARD TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21

VOLUME&PWR KEYBAD CHECKED:

<Checked By>
DATED: CODE: SIZE: DRAWING NO: REV:

QUALITY CONTROL: DATED:

<QC By> <QC Date> <Code> D 30_SIM&SD_CARD/KEYBAD Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:30 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

VREG_L12_1P8

D D

BLM15HG601SN1
R3104
C3106 C3107
6.3V
100NF
33PF
JP3101

1 RESET TE 40
[31] NRES TE [31]
2 GND LEDPWM 39
DISP_PWM_OUT_NS [31]
3 VSP GND 38
LGD_VOUT_P
4 VSN D2P 37 E3104 4 3
LGD_VOUT_N MIPI_DSI0_LANE2_P [3]
C3109 C3108 5 GND D2N 36 1 2
MIPI_DSI0_LANE2_M [3]
ACFT4A2G900E
100NF 100NF 6 IOVCC GND 35
C3121 C3122
7 NC £¨MTP£© D1P 34 E3103 4 3
56PF 56PF MIPI_DSI0_LANE1_P [3]
8 LED_A D1N 33 1 2
[31] LED_A1 MIPI_DSI0_LANE1_M [3]
ACFT4A2G900E
9 LED_C1 GND 32
[31] LED_K1
10 LED_C2 CLKP 31 E3105 4 3
[31] LED_K2 MIPI_DSI0_CLK_P [3]
11 NC CLKN 30 1 2
MIPI_DSI0_CLK_M [3]
ACFT4A2G900E
12 NC GND 29

R3120 1 2 1K 13 GND D0P 28 E3106 4 3

[2] TS_INT_N MIPI_DSI0_LANE0_P [3]
R3119 1 2 33R 14 I2C_SCL D0N 27 1 2
[2,31] TS_I2C_SCL MIPI_DSI0_LANE0_M [3]
ACFT4A2G900E
R3118 1 2 33R 15 I2C_SDA GND 26
[2,31] TS_I2C_SDA
R3117 1 2 1K 16 MCU_RESET D3P 25 E3102 4 3
[2] TS_RESET_N MIPI_DSI0_LANE3_P
[3]
C 17 GND D3N 24 1 2
MIPI_DSI0_LANE3_M [3]
C
ACFT4A2G900E
18 EVDD GND 23
TP_AVDD_3P3
R3101 1 2 0R 19 T_AVDD LCD_ID122 R3105 1K
VREG_LVS1_1P8 LCD_ID [2]
20 GND LCD_ID221 R3123 1K
LCD_ID2 [2]
C3103 C3105
6.3V
100NF AXE540124

41

42

43

44
100NF

VPH_PWR

R3107
R3106 L3102 10uH
D3101 BLM15HG601SN1B
0R
LED_A1 [31]
LVS303010-100M-N
PMEG4015EPK C3111
C3112
C3113 U3101 56PF
22uF 100NF TPS61163A C3110

C3
B 1uF B

SW
C2 VIN

[11] LCD_BL_EN C1 EN
R3109 n.m B1
[11] LCD_BL_PWM PWM
A3 R3108 1 2 BLM03HD601SN1 LED_K1 [31]
VPH_PWR IFB1
B2 COMP
R3111 1K R3110 1 2 BLM03HD601SN1

R3113
A2 [31]

100K
LED_K2

R3112
[31] DISP_PWM_OUT_NS IFB2

100K
A1

GND
ISET
C3115
330nF

B3

R3114
61.9K
C3114
1 1 2 2

10V
L3103

2.2uH

4.7UF
U3102
C1

ISL98608II55Z-T
LGD_VOUT_N
VIN

A2 LXP SCL C3 TS_I2C_SCL [2,31]

LGD_VOUT_P
10V

C3116 4.7UF A4 C2
VBSTCP SDA TS_I2C_SDA [2,31]
A3 VBST
ENP D1 LGD_DCDC_ENP [2]
R3115 1K
C3117 4.7UF [11] DISP_RESET_N NRES [31]
10V

B4 CP ENN B2 LGD_DCDC_ENN [2] R3116 1 2 1K

[2] DISP_TE TE [31]
R3125 D4 CN
1 2

D3 R3122 1 2n.m
VN [2] DISP_HSYNC HSYNC
R3124 D2 VSUB
PGNDCP

C3118
1 2
Back Light driver
AGND

PGND

33PF
C3119

C3120

B3 VP
LCD HSYNC?
B1

A1
C4

10V 10V
ISL98608II55Z-T
4.7UF

4.7UF

A LCD&TP CONNECTOR A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 31_LCD Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:31 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

VREG_L17_2P85

L3201 BLM15HG601SN1B

JP3202 VDD_AF_2V8
D AVDD_FCAM_2P7V C32011 D
DOVDD_FCAM_1P8V 34 1 2.2UF
[32] CAM0_RST_N_CON RESET_N AVCC_OIS_GND
VREG_L3_1P2 33 DGND 2
AVCC_OIS(2.8V)
E3202 ACFT4A2G900E
1 2 32 3 L3205 BLM15HG601SN1B

L3204
AF_GND

L3203
[3] MIPI_CSI0_LANE0_M DATA0_N
4 3 31 4
[3] MIPI_CSI0_LANE0_P DATA0_P AF_GND C3203

L3202
C3202
30 5 100PF
JP3201 DGND VDDAF(2.8V) 2.2UF
E3204 ACFT4A2G900E
28 DGND 1 1 2 29 6
GND [3] MIPI_CSI0_LANE1_M DATA1_N VDDAF(2.8V)
27 MDN2 2 1 2 4 3 28 SCL 7
GND MIPI_CSI2_LANE1_M [3] [3] MIPI_CSI0_LANE1_P DATA1_P CAM0_I2C_SCL0_CON [32]
26 MDP2 3 4 3 27 DGND 8
GND MIPI_CSI2_LANE1_P [3] SDA CAM0_I2C_SDA0_CON [32]
E3201 ACFT4A2G900E E3206
25 DGND 4 1 2 ACFT4A2G900E 26 VREG_L17_2P85
GND [3] MIPI_CSI0_CLK_M CLK_N DGND 9

BLM15AG121SN1

BLM15AG121SN1
24 5 1 ACFT4A2G900E
2 4 3 25
DVDD1.2V MCN MIPI_CSI2_CLK_M [3] CLK_P MCLK 10 CAM0_MCLK0_CON [32]
MIPI_CSI0_CLK_P

BLM15AG121SN1
[3]
23 DOVDD1.8V MCP 6 4 3 24 DGND 11 CAMERA_DVDD
MIPI_CSI2_CLK_P [3] DGND
E3203 E3207 R3201
22 DGND DGND 7 1 2 ACFT4A2G900E 23 12
[3] MIPI_CSI0_LANE2_M DATA2_N VDD_OIS(2.8V)
ACFT4A2G900E R3203 BLM15HG601SN1
21 SIO_D MDN1 8 1 2 4 3 22 VDIG(1.0V) 13 1 2
[32] FRONT_CAM_I2C_SDA MIPI_CSI2_LANE0_M [3] [3] MIPI_CSI0_LANE2_P DATA2_P
20 0R VREG_LVS2_1P8
[32] SIO_C MDP1 9 4 3
MIPI_CSI2_LANE0_P
21 DGND EVDD(1.8V) 14 C3205
FRONT_CAM_I2C_SCL [3]
E3205 E3208
19 DGND DGND 10 1 2 ACFT4A2G900E 20 15 L3206 BLM15HG601SN1B 2.2UF
[3] MIPI_CSI0_LANE3_M DATA3_N VDDIO(1.8V)
R3202 VREG_L17_2P85
CAM_1_PWDN 1 2 18 XSHUTDN XCLK1 11 4 3 19 16
[2] CAM1_MCLK2_CON [32] [3] MIPI_CSI0_LANE3_P DATA3_P AGND
0R 17
[32] WEBCAM_RESET_N_CON SYNC DGND 12 18
DGND VANA_2V8(2.8V)
17 L3208 BLM15AG121SN1 C3210
C3204
16 DGND FSIN 13 2.2UF
n.m
C3206 15 AVDD2.8V DGND 14 C3211

38

37

35

36
AXE534124_CW
n.m C3209
2.2UF
C3208 C3207 AXE524124-CCW
470NF 470NF
470NF

Rear Camera
VDD_AF_2V8
U3202

C 13M Main Camera Connector NCP114AMX280TCG

C
[2,35] FP_PER_EN 3
EN

1
4 OUT
VREG_BOOST_BYPASS IN C3217

EPAD
GND
C3216 100NF

5
100NF

R3214 1 2 33R CAM0_MCLK0 [2]

[32] CAM0_MCLK0_CON
R3215 1 2 1K CAM0_RST_N
[32] CAM0_RST_N_CON [2]

CAM0_I2C_SDA0_CON R3216 1 2 33R CAM0_I2C_SDA0 [2]

[32]
R3217 1 2 33R
[32] CAM0_I2C_SCL0_CON CAM0_I2C_SCL0 [2]
[32] R3210 1 2 n.m VREG_LVS2_1P8
WEBCAM_RESET_N_CON CAM1_RST_N [2] DOVDD_FCAM_1P8V
R3211 1 2 33R
[32] FRONT_CAM_I2C_SCL CAM1_I2C_SCL1 [2] 0R
R3204 1 2
[32] R3212 1 2 33R CAM1_I2C_SDA1 [2]
FRONT_CAM_I2C_SDA VREG_L17_2P85 AVDD_FCAM_2P7V
R3213 1 2 33R CAM1_MCLK2
[32] CAM1_MCLK2_CON [2]
R3205 1 2 0R

VREG_S1A_1P3
VPH_PWR

CAMERA_DVDD
B B
C3215 C3213
[14] FLASH_DRV2
1uF 1uF
[14] FLASH_DRV1
U3201 C3214 Flash LED 1A cool-white warm-white

R3221

D3201

D3202
n.m
2.2UF

LXCL-EY17-0005

LXCL-EA07-0001
4 1
BAIS OUT
6
IN

P-GND
[2] IMAGER_1V1_EN 3 2
EN ADJ

7 GND
R3206
NCP133

5
100K

R3222

n.m
FRONT CAMERA REAR CAMERA & FLASH

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 32_CAMERA Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:32 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

Note: This Pi filter is added for WCN FM Performance

D L3301 10R CDC_HPH_L [34,35]
D

CDC_HPH_REF [34]

C2232 L2307 placed close to WCD pin!! L3302 10R

CDC_HPH_R [34,35]

U3302-A C3301
WCD9320 100NF

[35] MAIN_MIC_INP 79 MIC1_INP ANALOG HPH_LP 77

[35] MAIN_MIC_INM 74 MIC1_INM HPH_REF 65
HPH_RM 82
Headset
[34,35] CDC_IN2_P 50 MIC2_INP
[34,35] CDC_IN2_M 68 MIC2_INM
EAROP 76 CDC_EAR_P [34]
[34] NOISE_MIC_INP 43 MIC3_INP EAROM 81 CDC_EAR_M
57 [34]
[34] NOISE_MIC_INM MIC3_INM
80 R3311 1 2 0R
LINE_OUT1 VREG_S3A_1P8
[34] REC_ANC_MIC_INP 62 MIC4_INP LINE_OUT2 69
[34] REC_ANC_MIC_INM 56 MIC4_INM LINE_OUT3 75
VREG_S3A_1P8 VREG_L1_1P2 70 C3302
LINE_OUT4 VREG_S2A_2P15
U3302-B C3335 C3334 19
N.M MIC5_INP
TP3301
WCD9320 n.m n.m
26 MIC5_INM VDD_RX 64 1uF

DIGITAL 38 MIC6_INP
6 GND VDD_IO 24 32 MIC6_INM GND 58
[2] 46 RESET_N
CODEC_RESET_N
40 MODE1 RX_I2S_WS 34 C3303 [34] MBHC_HSDET 31 MBHC_HSDET
48 MODE0 RX_I2S_SCK 10 VDD_BUCK 60
n.m 73 54 L3304 MPZ1608S102AT
[35] MIC_BIAS1 MIC_BIAS1 BUCK_VSW
[2] SLIMBUS_DATA 12 SLIMBUS_DATA TX_I2S_WS 41 61 MIC_BIAS2 BUCK_VOUT1 71
[34] MIC_BIAS2 C3304
18 SLIMBUS_CLK TX_I2S_SCK 5 [34] MIC_BIAS3 25 MIC_BIAS3 BUCK_VOUT2 59
[2] SLIMBUS_CLK 4.7UF
22 I2C_SCL 37 MIC_BIAS4
[2] [34] MIC_BIAS4
INTR1 16 CODEC_INT1 C3305
36 33 R3301 1 2 0R C3307 100NF 63 66
DMIC0_CLK INTR2 CODEC_INT2 [2] MICB_CFILT1 GND_BUCK

6.3V
42 C3306 100NF 67 84 2.2UF
DMIC0_DATA Note: R2101 is only for debug. MICB_CFILT2 GND_BUCK
11 29 C3308 100NF 13 B
DMIC1_CLK VDD_DIG1 MICB_CFILT3
17 DMIC1_DATA VDD_DIG2 47
23 VREG_S3A_1P8 L3306 0R 55 72 C3309 1uF
DMIC2_CLK VDD_TX NCP_C1P
30 35 VREG_L1_1P2 L3307 0R 20 78
DMIC2_DATA GND C3315 VDD_TXADC NCP_C1M
VPH_PWR 44 VDD_VBAT
Rev. E Note: It is critical to use part
28 100NF 51 83 CDC_NCP_VNEG C3310 1uF
[2,11] TX_GTR_THRES RF_PA_ON
C3311 C3312 C3313 C3314
LDO_HI_CAP NCP_VNEG identical to E36 as summarized in parts
WCD9320 list.Do not change unless consulted with
1uF 1uF 1uF 39
100NF CCOMP Qualcomm.
SPKR_VSNSP 14 Note: Place components close to the CODEC pins
Note: RF_PA_ON connection to MSM GPIO C3316
52 GND_CCOMP SPKR_DRVP 8 Pi filter place holders for EMI filtering
C SPKR_DRVM 9
especially recommended when the codec
C
1uF 21
TX_GTR_THRES pin for VBAT Monitoring 49
SPKR_VSNSM is placed away from the transducers.
GND
Feature.Connect RF_PA_ON to GND if not planning 27 GND
53 3 VPH_PWR
on enabling VBAT Monitoring Feature. GND VDD_SPKDR1
VDD_SPKDR2 15
LOUD SPEAKER
GND_SPKDRV 2
[11] DIVCLK1_CODEC 45 MCLK GND_SPKDRV 4
A
GND_SPKDRV 7
GND_SPKDRV 1
C3317 WCD9320 Rev.J Note: R2222 and R2223
placeholders added
n.m for speaker protection feature
!!!DNP R2212 and install R2213 with CS WCD9320
performance; in long traces due
to amplifier ringing replace 0
ohms with 15K.

Rev.J Note: GND island for

Speaker driver, (GND_SPKDRV)
is to isolate speaker driver
Rev. E Note: SPKR_VSNSP and SPKR_VSNSM must be noise from other
connected directly circuits.Refer to 80-NA556-5
at the speaker transducers for WCD9320 feedback for details.
(I/V sense) speaker protection feature.
4 Connect SPKR_VSNSP and SPKR_VSNSM to GND if not3 2

WCD9320

VPH_PWR
B B

VREG_S3A_1P8

C3318
10uF

TFM201610GHM-1R0MTAA
L3309
C3319
C3324 C3320 C3321 C3322 C3323
100NF
TP3302

TP3305
TP3303

100NF
TP3304

10uF 10uF 10uF 10uF

1uH
U3303
G3

G2

A7
B7
C7
TFA9890AUK
VDDD

VBAT

VDDP_1
VDDP_2
VDDP_3
[2] SMART_PA_SDA F1 SDA VBST_1 E7
[2] SMART_PA_SCL G1 SCL VBST_2 F7
VBST_3 G7
[2] MI2S_4_DOUT A2 DATAI1
MI2S_4_WS A1 WS1 INB_1 E6
[2]
B1 BCK1 INB_2 F6
[2] MI2S_4_BCLK
[2] A3 DATAO INB_3 G6 100R
MI2S_4_DIN
R3308 R3304
[2] SMART_PA_RST 1 2 B4 RST NC1 D6
[2] SMART_PA_INT 0R A4 INT NC2 D7 SMART_PA_OUTA R3305 BLM18EG221SN1 SPKR_DRVP
C1 C6 [35]
DATAI2 OUTA
R3306 BLM18EG221SN1
D1 WS2 OUTB A6 SMART_PA_OUTB SPKR_DRVM
C3327

E1 [35]
BCK2 100R
B3 E4 R3307
DATAI3 TEST7
TEST6 D4
TEST5 C4
C3 C3325
C3326
n.m

TEST4
GNDB_3
GNDB_2
GNDB_1

GNDD_9
GNDD_8
GNDD_7
GNDD_6
GNDD_5
GNDD_4
GNDD_3
GNDD_2
GNDD_1
GNDP_2
GNDP_1

TEST3 D3 33PF
33PF
ADS2
ADS1

TEST2 E3
F3
F2
G5
F5
E5
B6
B5
G4
F4
E2
D5
D2
C5
C2
B2
A5

A A

AUDIO PA COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 33_AUDIO_CODEC Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:33 OF 36
 HPH_REF should be routed between HPH_L
and HPH_R, and then connected to headset
ground.

C3416 n.m
[24] FM_RX_ANT

2
n.m
B3402 C3417 JP3402

L3412

n.m
VREG_BOOST_BYPASS
BLM03HG102SN1
C3401

1
1
100NF
VREG_S3A_1P8 2
[34] SNS_CON1
[33] MIC_BIAS2 3
[34] SNS_CON2
U3401 4

C1
R3406 R3402 L3404 BLM15BD182SN1D 5
1%
R3405

VDD
2.2K [33,35] CDC_HPH_L
0R

A2 A1 133K
[33] CDC_HPH_REF SENSE SNS1 A3 L3403
SNS2 [33,35] CDC_HPH_R BLM15BD182SN1D 6
C3 B1 R3403 100K L3405 BLM15BD182SN1D 7
[33,35] CDC_IN2_P MIC CON1 B3 SNS_CON1 [34] [33] MBHC_HSDET
CON2 SNS_CON2 [34] R1402 1 8
2 0R
B2 [14] BLUE_LED_DRV
[11] AUDIOJK_SWITCH_EN SEL

GND
GND CLOSE TO HSJ!!! [14] RED_LED_DRV
R1403 1 2 0R 9
10

PESD5V0S1BSF
R1404 1 2 0R

PESD5V0S1BSF
PESD5V0S1BSF
C3407 NCX8200 [14] GREEN_LED_DRV

C2

PESD5V0S1BSF
PESD5V0S1BSF
R3409 n.m
[33,35] CDC_IN2_M 1NF

R3404

100K

GND
GND
GND

GND

GND
C3403

C3404

11
12
AYF531035

1NF
HPH path THD+N.

1NF
NOTE Backup option for insertion and removal detection.
Note: R2305 should be 20K +/-5%. OEM

GND

GND
D3401
D3408
D3406
D3412

D3407
must install this component as shown
and not change the value as it will
negatively impact MBHC operation and
Primary option is using WCD9320 MBHC_HSDET for
mechanical insertion/removal detection.

Note: For MBHC operation, it is Required to implement

MICBIAS2 as shown in this reference schematic. Do not add
large capacitance to the micbias2 trace. The trace must be
limited to less than 270pF.
MIC A: Front TOP

MIC B: Rear TOP

MIC_BIAS4 [33]

MIC3401
AM0502B-NEA383-M02
5
6

C3408
NPTH
VDD

100NF
1 R3410 1 2 0R
OUTPUT REC_ANC_MIC_INP [33]
GND
GND
GND
3
4

REC_ANC_MIC_INM [33]
R3411
0R

R34181 2 0R JP3401
PESD5V0S1BSF

PESD5V0S1BSF

[33] CDC_EAR_P
C3412 1
D3410

D3411

+
47PF
R34191 2 0R 2
[33] CDC_EAR_M -
GND

GND

CDC_EAR_N_CON

C3413

C3414

R3415

PESD5V0S1BSF
PESD5V0S1BSF
R3414
SDRP0612K-J-03-02-F1

D3416

D3417
47PF

47PF

150K

150K
MIC_BIAS3 [33]

GND

GND
C3415
100NF
MIC3402
6
VDD

4 R3416 1 2 0R
OUTPUT NOISE_MIC_INP [33]
GND
GND
GND
GND
3
1
2

NOISE_MIC_INM [33]
R34172 1 0R Receiver
PESD5V0S1BSF

PESD5V0S1BSF
D3418

D3419
GND

GND

MIC
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

64

63

62

61
30 31

GND

GND

GND

GND
29 32

28 33
[2] GRFC_17 GPLED_SRC1 [14]
27 34
GPLED_SNK1 [14]
26 35
USB1_SS_RX0M GRFC_16 [2]
D [1] D
25 36
[1] USB1_SS_RX0P
24 37
USB1_HS_DP_RXD [35]
23 38
[1] USB1_SS_TX0M USB1_HS_DM_TXD [35]
22 39
[1] USB1_SS_TX0P
21 40 [2]
TYPEC_CC_SCL
20 41 TYPEC_CC_SDA [2]
[35] CDC_IN2_TYPEC_MIC_P

[35] CDC_IN2_TYPEC_MIC_M 19 42
VREG_S3A_1P8
18 43 VPH_PWR VPH_PWR

[11,35] 17 44
USB1_HS_ID FP_SPI_MOSI [2] USB1_VBUS

100NF
16 45
[2] TYPEC_CC_EN FP_SPI_CS [2]
15 46
[2] TYPEC_CC_INT1 FP_IQR [2] U3501

C3501
14 47 FP_3.3V
[2] FP_SPI_MISO R3512
13 48 5 3
[2] FP_SPI_CLK
[2,35] MSM_DEBUG_TX DN VCC 180K
5*100/280=1.78
12 49 [33] 1
[2] FP_RESET MIC_BIAS1 [2,35] MSM_DEBUG_RX DP
11 50 8 USB1_HS_DM_TXD [35]
[2] TYPEC_USB1_SW MAIN_MIC_INM [33] E3501 1 D-
[1,35] USB1_HS_DM_CPU 2 4
10 51 HDN
[14] VIB_DRV_N MAIN_MIC_INP [33] 3 4 2 10
[1,35] USB1_HS_DP_CPU HDP D+ USB1_HS_DP_RXD [35]
TP_1.0 TP3502 9 52
VBATT [14] GPLED_SRC2 ACFT4A2G900E
TP_1.0 TP3503 8 53 GPLED_SNK2 [14]
6 11 R3513 n.m USB2_SW_EN1 [2]
7 54 [35] CDC_HPH_TYPEC_L AUDN IN1 7
[2] HOME_KEY REDRIVER_EN [2] IN2 USB2_SW_EN2
12 [2]
[35] CDC_HPH_TYPEC_R AUDP
TP_1.0 TP3504 6 55 9
GND
TP_1.0 TP3505 5 56
[33] SPKR_DRVP SPKR_DRVM [33]
NCN1188MUTAG

C3533

C3524
4 57

C3523
C3540
C3517

C3522

C3519
C3521

C3503

C3507
C3514

C3518

C3520

C3504

C3506

C3529

C3508

C3543
R3505

C3525

C3535

C3534

C3502
C3515

C3505
100NF C3532

100NF C3541

100NF C3538
R3511
Factory test point for PowerOn n.m
TP_1.0 3 58 100K
[30] PWR_KEY TP3511

n.m

n.m

n.m

n.m

n.m

n.m
n.m
22uF
2 59

n.m

n.m

n.m

n.m

n.m

n.m

n.m

n.m
n.m

n.m

n.m
n.m

n.m

n.m
n.m

n.m
[11,28]PM8941_CBLPWR_N TP_1.0 TP3506
1 60

C [30] VOL_DN
TP_1.0 TP3507

AXE560124-CCW IN1 IN2 Fucntion

JP3502 LOW LOW Hi-Z
LOW HIGH UART
Factory test point for Force USB Boot Mode USB1_VBUS HIGH LOW Audio
HIGH HIGH USB

D3501
C3537

C3536
Factory test point for SIM1
H3501
TP_1.0 TP3509 25V
[2,30] UIM2_RST
YSMTSO-46168-ET

100NF
4.7UF
TP_1.0 TP3510
[2,30] UIM2_CLK
TP_1.0 TP3512
[2,30] UIM2_DATA
TP_1.0 TP3514
VREG_L10_UIM2
UIM_DETECT_TP TP_1.0 TP3515
[30]
ANT3504

1
PIN_ANT_818001102
ANT3502 ANT3512 ANT2601
PIN_ANT_818001102_NM PIN_ANT_818001104 PIN_ANT_818001475

1
ANT3513
PIN_ANT_818001102_NM

[33,34] CDC_HPH_L CDC_IN2_M [33,34]

R3522 1R R3523 0R
[35] CDC_HPH_TYPEC_L CDC_IN2_TYPEC_MIC_M [35]

1
FP_3.3V ANT3508 ANT3509 ANT3510 ANT3511
Factory test point for USB ANT3514

C3544
TP_1.0 PIN_ANT_818001475 PIN_ANT_818001475 PIN_ANT_818001475
PIN_ANT_818001475
USB1_VBUS TP3528 PIN_ANT_818001102
[1,35] TP_1.0 TP3529
USB1_HS_DM_CPU TP_1.0
[1,35] USB1_HS_DP_CPU TP3530
TP_1.0 TP3531

100NF
[11,35] USB1_HS_ID

R3501 1K UART_RX
TP_1.0 U3503
B [2,35] MSM_DEBUG_RX TP3532
9 1 B
R3502 1K UART_TXTP_1.0 VDD NO1
[2,35] MSM_DEBUG_TX TP3533
8
COM1 CDC_IN2_TYPEC_MIC_P [35]
3
NO2
10
NC1 CDC_IN2_P [33,34]
[35] 5
CDC_HPH_TYPEC_R COM2
7
2 IN1
[33,34] CDC_HPH_R NC2
6
[2] AUDIO_R_CMD_SW IN2 GND
4
PI3A268CZME
TP3539 [2] AUDIO_MIC_CMD_SW
JTAG_TRST_N TP_0.3
[1]
TP3540

100K
TP_0.3

100K
[1] JTAG_TDI
TP_0.3 TP3541
[1] JTAG_TMS
TP_0.3 TP3545
[1] JTAG_TCK
TP_0.3 TP3546
[1] JTAG_TDO

R3524

R3525
R3521 0R
TP3547 [2] ANC_AUDIO_CMD
[1] JTAG_SRST_N TP_0.3

[1] TP_0.3 TP3549

MODE

JTAG_PS_HOLD TP_0.3
[11] TP3548

Debug pin

·Åµ½±³ÃæÈ¥µôºó¸Ç¿ÉÒԵ㴥µÄλÖã¡
TP_1.0 VREG_BOOST_BYPASS
VREG_S3A_1P8 TP3537

TP_1.0 FP_3.3V
[2] FORCE_USB_BOOT TP3538
R3508 1 0R
2
2
R3509

0R

U3502
Shielding clip
1

A2 A1
A VIN VOUT A
C3531 B2 B1 COMPANY:
ON GND Lenovo
100NF
C3530
100NF
TPS22913B_NM TITLE:
[2,32] FP_PER_EN
LPDDR3_CHANNEL0
DRAWN: DATED:
2
R3510

100K

Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
1

<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D 35_TEST/POINT/SHIELD/CNN Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:35 OF 36
 6 5 4 3 2 1
REVISION RECORD
LTR ECO NO: APPROVED: DATE:

D D

C C

B B

A A
COMPANY:
Lenovo

TITLE:
LPDDR3_CHANNEL0
DRAWN: DATED:
Gul 2013/12/21
CHECKED: DATED: CODE: SIZE: DRAWING NO: REV:
<Checked By>
QUALITY CONTROL: DATED:
<QC By> <QC Date> <Code> D <undefined> Rev.0.2

RELEASED: DATED:
<Released By> <Release Date> SCALE:<Scale> SHEET:36 OF 36