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Mechanical Data
High density cell design for low RDS(ON)
Voltage controlled small signal switching.
Rugged and reliabale.
High saturation current capability.
High-speed switching.CMOS logic compatible.
CMOS logic compatible input.
Not thermal runaway.
No secondary breakdown.
Marking Code: S72
P Value UNIT
NOTES:
1.Pulse Test: Pulse Width <300 us, Duty Cycle <2.0%.
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2N7002
N-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR
DYNAMIC CHARACTERISTICS
Input Capacitance CISS ─ ─
Output Capacitance COSS VDS=25V, VGS=0V, F=1.0MHz ─ ─
Reverse Transfer Capacitance CRSS ─ ─
Turn-On Time TON
VDD=30V,RL=25Ω , ID=500mA ─ ─
VGS=10V, RGEN=25Ω
Turn-Off Time TOFF ─ ─
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2N7002
N-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR
2.0 1.0
•-
V
1.8 TA =25 °C DS =10V
• °C
25
ID ,DRAIN CURRENT (AMPS)
0.4 5V -
0.2
0.2 4V
3V
0 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
V V
DS ,DRAIN SOURCE VOLTAGE (VOLTS) GS ,GATE SOURCE VOLTAGE (VOLTS)
2.4 1.2
2.2 V
1.15
•
V V
GS =10V DS = GS
2.0 1.1
ID• -=200mA
• ID =1.0mA
1.8 -
1.10
1.6 1.0
(NORMALIZED)
1.4 0.95
1.2 0.9•
1.0 0.85
0.8 0.8•
0.6 0.75
0.4 0.7•
-60 -20 +20 +60 +100 +140 -60 -20 +20 +60 +100 +140
r
T,TEMPERAURE(°C ) T,TEMPERAURE(°C )
Fig.3 Temperature versus Static Fig.4 Drain¡VSource On¡VResistance
Drain-Source On-Resistance Temperature versus Gate Threshold Voltage
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