Technical Paper

ANSYS RedHawk

System-Aware SoC Power, Noise and Reliability Sign-off Platform

The global IC market is driven by shrinking time-to-market demands. To meet these chal-
lenging market forces and stringent foundry requirements, ANSYS® RedHawk™ offers a
silicon-proven power noise and reliability simulation platform that delivers low-power, high-
performance system-on-chip (SoC) ICs. RedHawk provides the full-chip capacity, efficient
turnaround, silicon-validated accuracy and sign-off coverage required for IC delivery, especial-
ly for power-efficient mobile, networking, consumer and automotive electronics applications.
As the industry-standard sign-off solution, RedHawk is an integral part of every foundry’s
reference flow, including sub-20 nm FinFET-based process nodes.

With increasing current density and shrinking noise margin at advanced process technologies,
it is critically important to accurately model and simulate the chip’s true performance. ANSYS
RedHawk Platform considers the impact of package/PCB noise on IC power. It also enables
an IC-aware power noise analysis and sign-off for package, PCB and system to ensure that the
tightest noise margin is met without wasted resources (over-design) or failure risks (under-
design). It delivers the required sign-off accuracy for chip–package power noise and reliability.

Key Capabilities
• SPICE-accurate transient simulation results at SoC level using dynamic
power models
• Simulation of 100 M+ instances with 2 B+ node designs while maintain-
ing flat sign-off accuracy
• Fast turn-around using advanced extraction and simulation engines
leveraging state-of-art multi-CPU computing and distributed machine
processing
• Out-of-box VectorLess™ algorithm for quick hot-spot identification and
high sign-off coverage
• Advanced logic simulation engine for complete RTL-to-GDS signoff
• Integrated root cause identification and debugging using RHE and
easy-to-use GUI
• Versatile environment for power grid prototyping and design optimization
• Native chip–package co-analysis by seamlessly merging full distributed
package parasitic network with on-die power delivery network (PDN)
• Impact of dynamic voltage drop on timing for clock network and critical
path
• Chip model (CPM, CTM) creation for system PI, EMI and thermal analyses
• Support for advanced device architectures including sub-20 nm FinFETs
• Foundry-certified power/signal EM and SoC ESD signoff for all leading
process technologies

1
 ANSYS RedHawk

Figure 1. Expected packaging technologies over the next five years

ANSYS RedHawk Platform

ANSYS RedHawk’s scalable architecture and advanced modeling technolo-
gies deliver full-chip capacity with sign-off accuracy. These capabilities
are required as designs become increasingly complex at smaller technol-
ogy nodes; they also ensure compliance with foundry requirements. As the
sign-off solution of choice for design teams around the world, RedHawk
provides an integrated environment for design needs including IP valida-
tion in an SoC context, comprehensive RTL-to-GDS power sign-off meth-
odology, chip-aware package/PCB design, and package/PCB-aware chip
signoff. Thermal feedback and integrated package layout analysis add to
the software’s value.

High Capacity and Performance

RedHawk delivers the capacity required for full-chip simulation without
compromising sign-off accuracy for dynamic voltage drop (DvD), electro-
migration (EM) and electrostatic discharge (ESD) analyses. The combina-
tion of re-architected database, several new engines and enhanced solvers
enable simulation of multi-billion nodes and RLC network matrices along
with fully distributed and cross-coupled package models. By optimizing
modeling and simulation of components necessary for sign-off accuracy,
RedHawk significantly improves performance both in terms of total turn-
around time and memory footprint — while generating results that are
silicon validated on sub-20 nm technology designs. Additional technologies
have been incorporated to meet the increasing number and complexity of
EM rule-checks.

For ultra-large designs, especially those fabricated using FinFET technolo-

gies, ANSYS RedHawk leverages distributed machine processing (DMP)
capabilities in which simulation is distributed across multiple machines
in a private cluster. This feature enables simulating 100 M+ instances or
2 B+ node designs while maintaining flat simulation sign-off accuracy.
DMP’s proprietary architecture allows each distributed portion of the de-
sign to be simulated within the context of the entire chip, including
package and PCB elements.

2
 ANSYS RedHawk

Silicon-Validated Sign-off Accuracy

ANSYS RedHawk is FinFET ready with sign-off certification from industry-
leading foundries for IR/DvD, EM and ESD integrity.

Figure 2. Accuracy: SPICE vs. APL
The software uses Apache Power Library (APL) and Custom Macro Model
(CMM) to incorporate device-level RC parasitics and switching current
waveforms for full-chip transient simulation at pico-second resolution.
These models are enhanced to meet evolving accuracy and coverage needs
for today’s complex designs. Additionally, RedHawk simultaneously simu-
lates all the power and ground domains present in today’s SoC to accurate-
ly predict the current drawn and voltage seen at every cell in a design.
For sub-20 nm FinFET-based designs, RedHawk expands its modeling,
extraction and analysis capabilities to support special metal layers and
complex via structures/shapes as well as dummy devices, vertical resis-
tance and double patterning. These capabilities help to ensure that SoCs
designed for the latest process technology nodes meet advanced IR/DvD
sign-off requirements. Figure 2 compares transistor-level SPICE simulation
of a waveform to a corresponding ANSYS RedHawk simulation using APL
models.

Accurate signoff of today’s low-power, high-performance SoCs requires

inclusion of detailed IP model and package/PCB parasitics. RedHawk
provides flexibility in bringing in models of various IPs based on detailed
simulation using ANSYS Totem™. It also accurately analyzes the effect of
package and PCB parasitics on dynamic voltage drop with RedHawk-CPA,
an integrated chip–package co-analysis feature. RedHawk-CPA maps a
package design to its corresponding die layout through pin-to-pin physical
connectivity. This enables a seamless merging of a fully distributed pack-
age parasitic network with on-die power delivery network.

Advanced Reliability Sign-off

As designs move to 20 nm and below, EM and ESD issues become even
more critical. RedHawk provides full support for power/ground and signal
line EM analyses, accurately analyzing EM violations while minimizing false
positives. Its proprietary current-flow-aware extraction techniques help to
create and simulate RLC network in a manner that provides sign-off quality
results for every wire and via in the design. ANSYS PathFinder™, which is
part of the RedHawk platform, supports SoC-level ESD integrity analysis by
providing connectivity and interconnect failure checks for all current flow
pathways (wires and vias) from an ESD event (HBM or CDM).

With FinFET-based designs, local heating is a major challenge, further exac-

erbating EM and ESD issues. The ANSYS comprehensive chip–package–sys-
tem thermal analysis flow takes in chip data along with package and system
(environment information) to generate accurate on-chip thermal profiles.
RedHawk enables thermal-aware EM and ESD analysis by incorporating
these thermal profiles.

3
 ANSYS RedHawk

Greater Coverage for Power Noise Closure

Identifying design hotspots in the absence of input vectors is critical for
better coverage of power integrity and reliability issues. ANSYS RedHawk
supports a VectorLess dynamic simulation engine that automatically
generates switching scenarios with or without user-specified constraints
for full-chip verification coverage. Additional VectorLess modes supported
by RedHawk include PowerTransient™, FrequencyAware™ and VectorLess
scan.

RedHawk also supports a variety of simulation engines to enable RTL to

GDS power noise closure. VectorLess RTL VCD and gate-level VCD engines
can be simultaneously invoked on a design, allowing mixed-mode opera-
tion to simulate every block with whatever input vector data is available for
each block. For example, if one block has gate-level VCD and another has
RTL vectors, then RedHawk uses the net activity from these vectors for the
respective blocks and uses the VectorLess engine for rest of the design to
generate the switching scenario.

Figure 3. Product ecosystem Power of Extended Ecosystem

The ANSYS power noise and reliability ecosystem extends beyond RedHawk
and other IC simulation platforms to include a suite of the most production-
proven system simulation tools: ANSYS SIwave™ for signal integrity,
ANSYS Icepak® for thermal integrity, and ANSYS HFSS™ for EMI and high-
frequency analysis.

Summary
Dynamic power, power/signal integrity and reliability from EMI and ESD
issues will become more challenging as process technologies advance.
ANSYS RedHawk pioneered full-chip package-aware dynamic power noise
analysis and signoff. Now with thousands of silicon implementations and
added EM, ESD, package and system-level reliability capabilities, it is the
preferred sign-off solution for foundries and designers to address power-
integrity, signal-integrity and reliability issues.

ANSYS, Inc. ANSYS, Inc. is one of the world’s leading engineering simulation software provid-
Southpointe ers. Its technology has enabled customers to predict with accuracy that their prod-
275 Technology Drive uct designs will thrive in the real world. The company offers a common platform of
Canonsburg, PA 15317 fully integrated multiphysics software tools designed to optimize product develop-
U.S.A. ment processes for a wide range of industries, including aerospace, automotive,
724.746.3304 civil engineering, consumer products, chemical process, electronics, environ-
ansysinfo@ansys.com mental, healthcare, marine, power, sports and others. Applied to design concept,
final-stage testing, validation and trouble-shooting existing designs, software from
ANSYS can significantly speed design and development times, reduce costs, and
provide insight and understanding into product and process performance.
© 2014 ANSYS, Inc. All Rights Reserved. Visit www.ansys.com for more information.

Any and all ANSYS, Inc. brand, product, service and feature names, logos and slo-
gans are registered trademarks or trademarks of ANSYS, Inc. or its subsidiaries in
the United States or other countries. All other brand, product, service and feature
names or trademarks are the property of their respective owners.