IP

1) What is IP Addressing?
• When Internet addresses were standardized (early
Using typical example IP addresses give network 1980s), the Internet address space was divided up into
classes:
ID and host ID s for Class A, Class B and Class
– Class A: Network prefix is 8 bits long
C IP addresses. – Class B: Network prefix is 16 bits long
– Class C: Network prefix is 24 bits long
➢ An IP address is a unique global address for a network – Each IP address contained a key which
interface identifies the class:
➢ An IP address: – Class A: IP address starts with “0”
– Class B: IP address starts with “10”
- is a 32 bit long identifier – Class C: IP address starts with “110”
- encodes a network number (network bit # 0 1 7 8 31
prefix) and a host number Class A 0
•
Network Prefix Host Number
IP addresses are written in a so-called dotted decimal 8 bits 24 bits

notation bit # 0 1 2 15 16 31

• Each byte is identified by a decimal number in the Class B 10 network id host

range [0..255]: Network Prefix Host Number
16 bits 16 bits

bit # 0 1 2 3 23 24 31

Class C 110 network id host

Network Prefix Host Number

24 bits 8 bits

•
The network prefix identifies a network and the host
number identifies a specific host (actually, interface on
the network).

2)Draw TCP/IP protocol stack. What are

• The network prefix used to be implicitly defined
(class-based addressing, A,B,C,D…)
• The network prefix now is flexible and is indicated by
a prefix/netmask (classless).
• Example: argon.cs.virginia.edu
• IP address is 128.143.137.144
• Is that enough info to route datagram??? -> No, need
netmask or prefix at every IP device (host and router)
• Using Prefix notation IP address is:
128.143.137.144/16
• Network prefix is 16 bits long
• Network mask is: 255.255.0.0 or hex format: ffff0000
• -----> Network id (IP address AND Netmask) is:
128.143.0.0
• -----> Host number (IP address AND inverse of
Netmask) is: 137.144
the functions of each layer? Compare it
with standard ISO OSI network model.
Both are based on the concept of a stack of
independent protocols. Also, the functionality of the layers
is roughly similar. For example, in both models the layers
up through and including the transport layer are there to
provide an end-to-end, network- independent transport
service to processes wishing to communicate. These layers
form the transport provider. Again in both models, the
layers above transport are application-oriented users of the
transport service.
Following are some similarities between OSI Reference
Model and TCP/IP Reference Model.
• Both have layered architecture.
• Layers provide similar functionalities.
• Both are protocol stack.
• Both are reference models.

TCP/IP PROTOCOL STACK

Application Layer
The application layer is provided by the program that uses
TCP/IP for communication. An application is a user process
cooperating with another process on the same or a different
host. The interface between the application and transport
layers is defined by port numbers and sockets

Transport Layer
• The transport layer provides the end-to-end data
transfer. Multiple applications can be supported
simultaneously. The transport layer is responsible for
providing a reliable exchange of information.
• The main transport layer protocol is TCP
• Another transport layer protocol is User Datagram
Protocol (UDP)which provides a connectionless
service in comparison to TCP, which provides a
connection-oriented service.
Internetwork Layer
 • The internetwork layer, also called the internet layer
or the network layer, provides the “virtual network”
image of an internet (that is, this layer shields the
higher levels from the physical network architecture
below it).
• Internet Protocol (IP) is the most important protocol
in this layer.
• It is a connectionless protocol that doesn't assume
reliability from the lower layers.
• IP does not provide reliability, flow control or error
recovery.
• IP provides this routing function.
Network Interface Layer
• The network interface layer, also called the link layer
Some implications of this algorithm are:
or the data-link layer, is the interface to the actual
network hardware. ➢ It is a change to the general IP algorithm.
• This interface may or may not provide reliable ➢ Therefore, to be able to operate this way, the
delivery, and may be packet or stream oriented. particular gateway must contain the new algorithm. Some
• In fact, TCP/IP does not specify any protocol here, but implementations may still use the general algorithm, and
can use almost any network interface available, which will not function within a subnetted network, although they
illustrates the flexibility of the IP layer. can still communicate with hosts in other networks that are
3)Develop IP routing algorithm with subnet mask subnetted.
and illustrate it with example ➢ As IP routing is used in all of the hosts (and not just
➢ IP uses a unique algorithm to route an IP the routers), all of the hosts in the subnet must have:
datagram, called the IP routing algorithm. To 1. An IP routing algorithm that supports subnetting.
send an IP datagram on the network, the 2. The same subnet mask (unless subnets are formed within
general IP routing algorithm has the following the subnet).
form ➢ If the IP implementation on any of the hosts does
not support subnetting, that host will be able to
communicate with any host in its own subnet but not with
any machine on another subnet within the same network.
➢ This is because the host sees only one IP network
and its routing cannot differentiate between an IP datagram
directed to a host on the local subnet and a datagram that
should be sent via a router to a different subnet.

➢
To be able to differentiate between subnets, the IP routing
algorithm changes and has the following form:
 • The number of network numbers in use. The Class
C figures are somewhat inaccurate, because the
figures do not include many class C networks in
Europe, which were allocated to RIPE and
subsequently assigned but which are still recorded
as allocated.
• Allocated
• This includes all of the assigned networks and
additionally, those networks that have either been
reserved by IANA (for example, the 63 class A
networks are all reserved by IANA) or have been
allocated to regional registries by IANA and will
subsequently be assigned by those registries.
• There are relatively few networks that would need
as many as 65,534 host addresses, but very few for
which 254 hosts would be an adequate limit. In
➢ summary, although the Class A, Class B and Class
C divisions of the IP address are logical and easy-
to-use (because they occur on byte boundaries),
with hindsight they are not the most practical
because Class C networks are too small to be
useful for most organizations while Class B
networks are too large to be densely populated by
any but the largest organizations.
• Since 1990, the number of assigned Class B
networks has been increasing at a much lower rate
than the total number of assigned networks and the
anticipated exhaustion of the Class B network
numbers has not yet occurred. The reason for this
is that the policies of the InterNIC on network
number allocation were changed in late 1990 to
preserve the existing address space, in particular to
avert the exhaustion of the Class B address space.
• The new policies can be summarized as follows.
➢ The upper half of the Class A address
space (network numbers 64 to 127) is
reserved indefinitely to allow for the
possibility of using it for transition to a new
• numbering scheme. Class B networks are
only assigned to organizations that can clearly
demonstrate a need for them. The same is, of
4)What is The IP Address Exhaustion course, true for Class A networks. The
Problem? What are the solutions for it? requirements for Class B networks are that
the requesting organization:
• The number of networks on the Internet has been ➢ – Has a subnetting plan that documents more
approximately doubling annually for a number of than 32 subnets within its organizational
years. network
• However, the usage of the Class A, B and C ➢ – Has more than 4096 hosts Any requirements
networks differs greatly. for a Class A network would be handled on an
• The terms assigned and allocated in this context individual case basis.
have the following meanings: ➢ Organizations that do not fulfill the
• requirements for a Class B network are
• assigned a consecutively numbered block of
• Assigned Class C network numbers.
 ➢ The lower half of the Class C address space • An exception to the rule constitutes the Asynchronous
(network numbers 192.0.0 through Transfer Mode (ATM) technology where ARP cannot be
207.255.255) is divided into eight blocks, implemented in the physical layer as described previously.
which are allocated to regional authorities • Therefore, an ARP server is used with which every
as follows: host has to register upon initialization in order to be able
192.0.0 - 193.255.255 Multi-regional to resolve IP addresses to hardware addresses . ARP was
194.0.0 - 195.255.255 Europe designed to be used on networks that support hardware
196.0.0 - 197.255.255 Others broadcast.
198.0.0 - 199.255.255 North America
200.0.0 - 201.255.255 Central and South America
202.0.0 - 203.255.255 Pacific Rim
204.0.0 - 205.255.255 Others
206.0.0 - 207.255.255 Others
5)What is Address Resolution Protocol (ARP)?

• The ARP protocol is a network-specific standard

protocol.
• The address resolution protocol is responsible for
converting the higher level protocol addresses
(IPaddresses) to physical network addresses.
• The term address resolution refers to the process of
finding an address of a computer in a network.
• On a single physical network, individual hosts are
known on the network by their physical hardware address.
• Higher level protocols address destination hosts in the
form of a symbolic address (IP address in this case).
• When such a protocol wants to send a datagram to
destination IP address w.x.y.z, the device driver does not
understand this address.
• Therefore, a module (ARP) is provided that will
translate the IP address to the physical address of the
destination host.

• It uses a lookup table (sometimes referred to as the

ARP cache) to perform this translation. When the address
is not found in the ARP cache, a broadcast is sent out on
the network, with a special format called the ARP request.

• If one of the machines on the network recognizes its

own IP address in the request, it will send an ARP reply
back to the requesting host.

• The reply will contain the physical hardware address

of the host and source route information (if the packet has
crossed bridges on its path).

• Both this address and the source route information are

stored in the ARP cache of the requesting host.

• All subsequent datagrams to this destination IP

address can now be translated to a physical address, which
is used by the device driver to send out the datagram on
the network.

CAN
4)What is the minimum and maximum size of the CAN frame are used for soft synchronization of the
of a CAN frame?
• In addition, CAN specification version 2.0B defines two more than a specific amount indicated within the CAN
different formats that differ in the length of the identifier specification.
field: standard frames with an 11-bit identifier and
extended frames with 29-bit identifier.
• CAN standard data frames contain from 44 to 108 bits and
CAN extended data frames contain 64 to 128 bits.
Furthermore, up to 23 stuff bits can be inserted in a
standard data frame, and up to 28 stuff bits in an extended
data frame, depending on the data-stream coding. The
overall maximum data frame length is then 131 bits for a
standard frame and 156 bits for an extended frame
5)How synchronization is achieved in CAN
signaling?
1. CAN signaling is bit synchronized across the entire
network during the Sync portion which is the time
required for each node to synchronize with the leading
edge of a recessive to dominant edge transition.
2. The Signal Propagation is the time for the bit signal
to propagate throughout the network.
3. Longer networks result in longer Signal Propagation
delays which require longer bits resulting in slower
data rates.
4. The Phase 1 portion delays sampling so that the bit
signal can settle to a stable value
Bit Synchronization
There is no separate clock signal on the CAN bus to
synchronize the node the CAN frame itself is used for
synchronization of the clocks on all the nodes. To a effectively
achieve this CAN frames have NRZ-5 coding. If there are five
bits at the same level in the CAN frame a sixth bit of the
opposite level is stuffed by the transmitter. This extra stuffed
bit is removed by the receiver node before processing the
CAN frame. There is hard synchronization and soft
synchronization of node clocks using the CAN frame while
all nodes have clocks running at the same baud rate. When the
transmitting node sends a CAN frame all the clocks of the
receiving nodes are synchronized to the transmitter clock at
the falling edge of the “Start of Frame” (SOF) bit. This is the
hard synchronization of the clocks. Subsequent falling edges
nodes. The difference between the hard synchronization and
soft synchronization is that the sampling clock cannot shift by
CAN Synchronization Via Bit Stuffing
• CAN nodes use Recessive to Dominant edges to
maintain bit synchronization.
• Bit Stuffing ensures sufficient Recessive to Dominant
edges to maintain bit synchronization
• A stuff Bit inserted after 5 consecutive bits at the same
state
• A Stuff Bit is the inverse of previous bits and is
discarded by the receiver
6)Why CAN bus is highly immune to noise?
10)How differential signaling in CAN
reduces the interference?
Noisetolerance
• Information is carried on the bus as a voltage
difference between the two lines.
• If both lines are at the same voltage, the signal is a
recessive bit.
• If the CAN_H line is higher than the CAN_L line by
0.9V, the signal line is a dominant bit.
• There's no independent ground reference point for
these two lines. The bus is therefore immune to any
ground noise, which in a vehicle can be considerable.
• The signals on the two CAN lines will both be subject
to the same electromagnetic influences, and so the
difference in voltages between the two lines will not
vary.
• Because of this, the bus is also immune to
electromagnetic interference. the differential signaling
inherent in CAN helps to filter out noise.
• in the recessive state both the CANH and CANL bus
pins are biased to the same level: ~2.5V. During the
dominant state, the CANH bus pin is biased to a higher
voltage potential (~3.5V) and the CANL bus pin is
biased to a lower voltage potential (~1.5V). By
subtracting the voltage potential of the two bus pins,
you can determine the logical state of the bus using
Equation 1. When the Vdiff value on the bus is less than
0.5V, the bus is considered to be in a recessive state.
Alternately, Vdiff values greater than 0.9V indicate that
the bus is in a dominant state. Lastly, for Vdiff values
between 0.5V and 0.9V, the bus state is undefined.
Since the difference between the two signals is used to
define the state of the bus, this signaling type is known
as differential signaling
7)Draw CAN data frame format. How
multiple devices are connected to the CAN
bus? What is the arbitration mechanism?
➢ SOF -The single dominant start of frame (SOF) bit
marks the start of a message, and is used to
synchronize the nodes on a bus after being idle.
➢ Identifier- The Standard CAN 11-bit identifier
establishes the priority of the message. The lower the
binary value, the higher its priority.
➢ RTR–The single remote transmission request (RTR)
bit is dominant when information is required from
another node. All nodes receive the request, but the
identifier determines the specified node. The
responding data is also received by all nodes and used
by any node interested.
➢ IDE–A dominant single identifier extension (IDE) bit
means that a standard CAN identifier with no
extension is being transmitted.
➢ r0–Reserved bit (for possible use by future standard
amendment).
➢ DLC–The 4-bit data length code (DLC) contains the
number of bytes of data being transmitted. move a
correctly received frame to its proper position in a
message buffer area.
➢ Data–Up to 64 bits of application data may be
transmitted.
➢ CRC–The 16-bit (15 bits plus delimiter) cyclic
redundancy check (CRC) contains the checksum
(number of bits transmitted) of the preceding
application data for error detection.
➢ ACK–Every node receiving an accurate message
overwrites this recessive bit in the original message
with a dominate bit, indicating an error-free message
has been sent. Should a receiving node detect an error
and leave this bit recessive, it discards the message and
the sending node repeats the message after
rearbitration. In this way, each node acknowledges
(ACK) the integrity of its data. ACK is 2 bits, one is
the acknowledgment bit and the second is a delimiter.
➢ EOF–This end-of-frame (EOF), 7-bit field marks the
end of a CAN frame (message) and disables bit-
stuffing, indicating a stuffing error when dominant.
When 5 bits of the same logic level occur in succession
during normal operation, a bit of the opposite logic
level is stuffed into the data.
 ➢ IFS–This 7-bit interframe space (IFS) contains the
time required by the controller to move a correctly
received frame to its proper position in a message
buffer area.
CAN Logic & Arbitration
1. CAN 2.0A messages begin with an 11-bit message ID
which identifies the message type and also establishes
the message priority.
2. As with many computer interfaces, the CAN
transceivers invert the microcontroller signal. Thus,
the dominant bus state occurs when a logic “0” is
transmitted and the recessive state occurs when a logic
“1” is transmitted.
3. CAN uses the message ID to perform bus access
arbitration between nodes.
4. Each node waits for an idle bus state then begins to
transmit its message ID.
5. Each node also listens to the bus to see if the bus state
match its transmission.
6. If a node detects a dominant bus state while
transmitting a recessive message ID bit (logic “1”), it
drops out of the current arbitration round and will try
again the next time the bus is idle
7-bit CANopen Node ID Arbitration Example
KEY ADVANTAGES OF CAN BUS ARBITRATION
1. Fast & deterministic.
2. Highest priority message gets immediate access once
the bus is available.
3. Arbitration is essential “free” since message ID
encodes message priority.
4. Unlike Carrier Sense Multiple Access with Collision
Detect (CSMA/CD) arbitration propagation delays
never cause message collisions
8)What are the important features of CAN
network? What are the advantages of CAN
network?
Advantages of CAN
1. Low cost network infrastructure which is often built
into microcontrollers.
2. Large market segment with broad availability of
hardware, software and systems engineering tools.
3. Light weight, low latency, highly deterministic design
specifically for real-time embedded applications.
4. Reliable with strong error detection, fault tolerant
versions available.
5. Flexible and highly configurable with various higher
level application protocols.
6. Foundation for next generation technology controller
area networks.
Features of CAN
• Multi-master/broadcast
• Maximum signaling rate of 1Mbps
• Absence of node addressing
– Message ID : contents, priority
• CSMA/CD with AMP (Carrier Sense Multiple Access
with Collision Detection and Arbitration on Message
Priority).
• Asynchronous Serial Bus
• Simple 2-wire differential bus
• Unlike a traditional network such as USB or Ethernet,
CAN does not send large blocks of data point-to-point
from node A to node B. In a CAN network, many short
messages like temperature or RPM are broadcast to the
entire network, which provides for data consistency in
every node of the system.
• Prioritization of messages
• Guarantee of latency times
• Multimaster
• Configuration flexibility
• Multicast reception with time synchronization
• Error detection and signaling
• Automatic retransmission of corrupted messages
2)Give an example of an industrial • The logic ‘1’ in RS232 is described as being in the
communication interface commonly used in voltage range of -15V to -3V and logic ‘0’ is described
embedded systems. What are special features available in as the voltage range of +3V to +15V i.e. low level
that interface? voltage is logic ‘1’ and high level voltage is logic ‘0’.
• Typically, the logic ‘1’ in RS232 will be -12V and
logic ‘0’ will be +12V.
• RS-232 defines the connection between data terminal
• The maximum slew rate in RS232 is limited to
equipment (DTE) and data circuit-terminating
30V/µs. Also, a maximum bit rate of 20 Kbps is also
equipment (DCE).
defined.
• Data terminal equipment is any end user device, such
as a computer, that can be used to send data over a
network. • These limitations of the standard help in reducing
• Data circuit-terminating equipment is a device that the cross – talk with adjacent signals.
provides the interface between the DTE and the
network, and is often a modem or terminal adapter.
9)Draw the CAN protocol stack and explain
• An RS-232-compatible interface was commonly used
for computer serial communication (COM) ports,
the functions of each layer in the protocol
which were originally intended for connecting the
computer to a modem.
• While the original RS232 standard specified 25-pin
connections, many of the pins were not used in
practice, and a 9-pin connection was implemented on
most computers.

• When Modem (DCE) is ready to receive, it will send

a DCE ready signal.
• When the computer (DTE) is ready to send the data,
it sends a Ready to Send (RTS) signal.
• The Modem (DCE) then sends a Clear to Send (CTS)
signal to indicate that data can be sent by computer
(DTE).
• Finally, the Computer (DTE) sends data on Transmit
Data (TD) line to the Modem (DCE).
 ➢

12)Find out reasons why CAN bus is used in

industrial networking.
➢ The Controller Area Network (CAN bus) is
the nervous system, enabling communication
between all parts of the body.
➢ Similarly, ‘nodes’ - or electronic control units (ECU)
- are connected via the CAN bus, which acts as a
central networking system.
➢ The CAN bus protocol allows ECUs to communicate
with each other without complex dedicated wiring in
between.
➢ To allow any ECU to communicate with the entire
system without causing an overload to the controller
computer.
➢ Low cost: ECUs communicate via a single CAN
interface, i.e. not direct analogue signal
lines, reducing errors, weight, costs
➢ Centralized: The CAN bus system allows for
central error diagnosis and configuration across all
ECUs
➢ Robust: The system is robust towards failure of
subsystems and electromagnetic interference,
making it ideal for e.g. vehicles
➢ Efficient: CAN messages are prioritized via IDs so
that the highest priority IDs are non-interrupted
(key in e.g. vehicles)
➢ Flexible: Each ECU contains a chip for receiving all
transmitted messages, decide relevance and act
accordingly - this allows easy modification and
inclusion of additional nodes
 receives it. The MISO line remains inactive.
SPI
1. How multiple devices are connected in
SPI bus? Differentiate master and slave
modes in SPI. Explain the daisy
chaining of devices on SPI bus.
In SPI, a master can communicate with a single
or multiple slaves. For applications using
multiple slaves, the following configurations are
possible:
Independent slaves. This is a most common
configuration of the SPI bus. The MOSI, MISO
and SCK lines of all slaves are interconnected.
The SS line of every slave device is connected to Daisy-chain slaves: the first slave output is connected to the
second slave input, etc. The SPI port of each slave is
a separate pin of SPI master device.
designed to send out during the second group of clock pulses
an exact copy of the data it received during the first group of
clock pulses.

Independent slave configuration with

decoder/demultiplexer. The SS lines are used to send
an n-bit value, which is the number of the selected slave.
Here, the master can communicate with m=2n slaves.

Master Mode
• The SPI operates in master mode when the MSTR bit
is set.
• Only a master SPI module can initiate transmissions.
• A transmission begins by writing to the master SPI
Data Register.
• If the shift register is empty, the byte immediately
transfers to the shift register.
• The byte begins shifting out on the MOSI pin under
the control of the serial clock.
• S-clock
Half-duplex write configuration. The master
• The SPR2, SPR1, and SPR0 baud rate selection bits in
transmits data on the MOSI line and the slave conjunction with the SPPR2, SPPR1, and SPPR0 baud
rate preselection bits in the SPI Baud Rate register
 control the baud rate generator and determine the
speed of the transmission.
• The SCK pin is SPI clock output. Through the SCK
pin, the baud rate generator of the master controls the
shift register of the slave peripheral.
• MOSI, MISO pin
In master mode, the function of the serial data output pin
(MOSI) and the serial data input pin (MISO) is determined
by the SPC0 and BIDIROE control bits.
• SS pin
If MODFEN and SSOE bit are set, the SS pin is configured
as slave select output. The SS output becomes low during
each transmission and is high when the SPI is in idle state.
• If MODFEN is set and SSOE is cleared, the SS pin is
configured as input for detecting mode fault error.
• If the SS input becomes low this indicates a mode fault
error where another master tries to drive the MOSI and SCK
lines.
• In this case, SPI immediately switches to slave mode,
by clearing the MSTR bit and also disables the slave output
buffer MISO (or SISO in bidirectional mode).
• So the result is that all outputs are disabled and SCK,
MOSI and MISO are inputs.
• If a transmission is in progress when the mode fault
occurs, the transmission is aborted and the SPI is forced into
idle state.
• This mode fault error also sets the mode fault (MODF)
flag in the SPI Status Register (SPISR).
• If the SPI interrupt enable bit (SPIE) is set when the
MODF flag gets set, then an SPI interrupt sequence is also
requested.
• When a write to the SPI Data Register in the master
occurs, there is a half SCK-cycle delay.
• After the delay, SCK is started within the master. The
rest of the transfer operation differs slightly, depending on
the clock format specified by the SPI clock phase bit, CPHA,
in SPI Control Register 1
A change of the bits CPOL, CPHA, SSOE, LSBFE,
MODFEN, SPC0, BIDIROE with SPC0 set, SPPR2-SPPR0
and SPR2-SPR0 in master mode will abort a transmission in
progress and force the SPI into idle state. The remote slave
cannot detect this, therefore the master has to ensure that the
remote slave is set back to idle state.
Slave Mode
The SPI operates in slave mode when the MSTR bit in SPI
Control Register1 is clear.
• SCK clock
In slave mode, SCK is the SPI clock input from the master.
• MISO, MOSI pin
In slave mode, the function of the serial data output pin
(MISO) and serial data input pin (MOSI) is
determined by the SPC0 bit and BIDIROE bit in SPI Control
Register 2.
• SS pin
The SS pin is the slave select input. Before a data
transmission occurs, the SS pin of the slave SPI must
be low. SS must remain low until the transmission is
complete. If SS goes high, the SPI is forced into idle
state.
• The SS input also controls the serial data output pin, if SS
is high (not selected), the serial data output pin is high
impedance, and, if SS is low the first bit in the SPI Data
Register is driven out of the serial data output pin.
• Also, if the slave is not selected (SS is high), then the SCK
input is ignored and no internal shifting of the SPI shift
register takes place.
• Although the SPI is capable of duplex operation, some SPI
peripherals are capable of only receiving SPI data in a
slave mode. For these simpler devices, there is no serial
data out pin.
NOTE: When peripherals with duplex capability are used,
take care not to simultaneously
enable two receivers whose serial outputs drive the same
system slave’s serial data
output line.
• As long as no more than one slave device drives the
system slave’s serial data output line, it is possible for
several slaves to receive the same transmission from a
master, although the master would not receive return
information from all of the receiving slaves.
• If the CPHA bit in SPI Control Register 1 is clear, odd
numbered edges on the SCK input cause the data at the
serial data input pin to be latched. Even numbered edges
cause the value previously latched from the serial data
input pin to shift into the LSB or MSB of the SPI shift
register, depending on the LSBFE bit.
• If the CPHA bit is set, even numbered edges on the SCK
input cause the data at the serial data input pin to be
latched. Odd numbered edges cause the value previously
latched from the serial data input pin to shift into the LSB
or MSB of the SPI shift register, depending on the LSBFE
bit.
• When CPHA is set, the first edge is used to get the first
data bit onto the serial data output pin. When CPHA is
clear and the SS input is low (slave selected), the first bit
of the SPI data is driven out of the serial data output pin.
After the eighth shift, the transfer is considered complete
and the received data is transferred into the SPI Data
Register. To indicate transfer is complete, the SPIF flag in
the SPI Status Register is set.
NOTE: A change of the bits CPOL, CPHA, SSOE, LSBFE,
MODFEN, SPC0 and BIDIROE
with SPC0 set in slave mode will corrupt a transmission in
progress and has to be
avoided.
2. How the transmission formats changes with
the value of clock phase in SPI? Explain with
neat sketch.
• During an SPI transmission, data is transmitted
(shifted out serially) and received (shifted in serially)
simultaneously.
• The serial clock (SCK) synchronizes shifting and
sampling of the information on the two serial data lines.
• A slave select line allows selection of an individual
slave SPI device, slave devices that are not selected do not
interfere with SPI bus activities.
• Optionally, on a master SPI device, the slave select
line can be used to indicate multiple-master bus
contention.
• bit.
1) Clock Phase and Polarity Controls
• Using two bits in the SPI Control Register1, software
selects one of four combinations of serial clock phase and
polarity.
• The CPOL clock polarity control bit specifies an
active high or low clock and has no significant effect on
the transmission format.
• The CPHA clock phase control bit selects one of two
fundamentally different transmission formats. Clock phase
and polarity should be identical for the master SPI device
and the communicating slave device.
• In some cases, the phase and polarity are changed
between transmissions to allow a master device to
communicate with peripheral slaves having different
requirements.
2 CPHA = 0 Transfer Format
• The first edge on the SCK line is used to clock the first
data bit of the slave into the master and the first data bit of
the master into the slave.
• In some peripherals, the first bit of the slave’s data is
available at the slave’s data out pin as soon as the slave is
selected.
• In this format, the first SCK edge is issued a half cycle
after SS has become low.
• A half SCK cycle later, the second edge appears on the
SCK line.
• When this second edge occurs, the value previously
latched from the serial data input pin is shifted into the
LSB or MSB of the shift register, depending on LSBFE
• After this second edge, the next bit of the SPI master
data is transmitted out of the serial data output pin of the
master to the serial input pin on the slave.
• This process continues for a total of 16 edges on the
SCK line, with data being latched on odd numbered edges
and shifted on even numbered edges.
• Data reception is double buffered. Data is shifted
serially into the SPI shift register during the transfer and
is transferred to the parallel SPI Data Register after the last
bit is shifted in.
• After the 16th (last) SCK edge:
• Data that was previously in the master
SPI Data Register should now be in the
slave data register and the data that was in
the slave data register should be in the
master.
• The SPIF flag in the SPI Status Register
is set indicating that the transfer is
complete
In slave mode, if the SS line is not deasserted between the
successive transmissions then the content of the SPI Data
Register is not transmitted, instead the last received byte is
transmitted. If the SS line is deasserted for at least minimum
idle time ( half SCK cycle) between successive
transmissions then the content of the SPI Data Register is
transmitted. In master mode, with slave select output
 enabled the SS line is always deasserted and reasserted
between successive transfers for at least minimum idle time.
3 CPHA = 1 Transfer Format
• Some peripherals require the first SCK edge before the
first data bit becomes available at the data out pin, the
second edge clocks data into the system.
• In this format, the first SCK edge is issued by setting
the CPHA bit at the beginning of the 8-cycle transfer
operation.
• The first edge of SCK occurs immediately after the
half SCK clock cycle synchronization delay.
• This first edge commands the slave to transfer its first
data bit to the serial data input pin of the master.
• A half SCK cycle later, the second edge appears on the
SCK pin.
• This is the latching edge for both the master and slave.
• When the third edge occurs, the value previously
latched from the serial data input pin is shifted into the
LSB or MSB of the SPI shift register, depending on
LSBFE bit.
• After this edge, the next bit of the master data is ➢ The SS line can remain active low between successive
coupled out of the serial data output pin of the master transfers (can be tied low at all times). This format is
to the serial input pin on the slave. sometimes preferred in systems having a single fixed
master and a single slave that drive the MISO data
• This process continues for a total of 16 edges on the
line.
SCK line with data being latched on even numbered
➢ Back to Back transfers in master mode
edges and shifting taking place on odd numbered
➢ In master mode, if a transmission has completed and a
edges.
new data byte is available in the SPI Data Register,
• Data reception is double buffered, data is serially
this byte is send out immediately without a trailing and
shifted into the SPI shift register during the transfer
minimum idle time.
and is transferred to the parallel SPI Data Register
➢ The SPI interrupt request flag (SPIF) is common to
after the last bit is shifted in.
both the master and slave modes. SPIF gets set one
• After the 16th SCK edge: half SCK cycle after the last SCK edge.
o Data that was previously in the SPI Data
Register of the master is now in the data
register of the slave, and data that was in the
3. How SPI differs from other
data register of the slave is in the master. communication protocols? What are
o The SPIF flag bit in SPISR is set indicating the special applications of SPI?
that the transfer is complete
Figure 4-3 shows two clocking variations for CPHA = 1. The
diagram may be interpreted as a master or slave timing diagram
since the SCK, MISO, and MOSI pins are connected directly
between the master and the slave. The MISO signal is the output
from the slave, and the MOSI signal is the output from the master.
The SS line is the slave select input to the slave. The SS pin of the
master must be either high or reconfigured as a general-purpose
output not affecting the SPI.
 • If SPISWAI is set, SPI clock generation ceases and
the SPI module enters a power conservation state when the
CPU is in wait mode.
• If SPISWAI is set and the SPI is configured for
master, any transmission and reception in progress stops at
wait mode entry. The transmission and reception resumes
when the SPI exits wait mode.
• If SPISWAI is set and the SPI is configured as a slave,
any transmission and reception in progress continues if the
SCK continues to be driven from the master. This keeps the
slave synchronized to the master and the SCK.
APPLICATIONS • If the master transmits several bytes while the slave is
➢ The full-duplex capability makes SPI very simple and in wait mode, the slave will continue to send out bytes
efficient for single master/single slave applications consistent with the operation mode at the start of wait mode
➢ digital audio, digital signal processing. (i.e. If the slave is
currently sending its SPIDR to the master, it will continue to
➢ SPI is used to talk to a variety of peripherals, such as
send the same byte. Else if the slave is currently sending the
➢ Sensors: temperature, pressure, ADC, last received byte from the master, it will continue to send
touchscreens, video game controllers each previous master byte)
➢ Control devices: audio codecs, digital SPI in Stop Mode
potentiometers, DAC • Stop mode is dependent on the system. The SPI
➢ Camera lenses: Canon EF lens mount enters stop mode when the module clock is disabled
➢ Communications: Ethernet, USB, USAR (held high or low).
T, CAN, IEEE 802.15.4, IEEE 802.11, • If the SPI is in master mode and exchanging data
handheld video games when the CPU enters stop mode, the transmission is
frozen until the CPU exits stop mode. After stop, data
➢ Memory: flash and EEPROM
to and from the external SPI is exchanged correctly.
➢ Real-time clocks
• In slave mode, the SPI will stay synchronized with
➢ LCD, sometimes even for managing
the master.
image data
• The stop mode is not dependent on the SPISWAI bit.
➢ It is used in audio or video codec’s,
digital potentiometers. Reset
➢ It is used in flash and EEPROM The reset values of registers and signals are described in the
memories. Memory Map and Registers section which details the
➢ It is used as canon EF lens mount in registers and their bit-fields.
camera. • If a data transmission occurs in slave mode after reset
➢ without a write to SPIDR, it will transmit garbage, or the
byte last received from the master before the reset.
• Reading from the SPIDR after reset will always read a byte
4. What are the low power mode options in of zeros.
SPI? Interrupts
• The SPI only originates interrupt requests when SPI is
SPI in Run Mode enabled (SPE bit in SPICR1 set).
• In run mode with the SPI system enable (SPE) bit in • The following is a description of how the SPI makes a
the SPI control register clear, the SPI system is in a low- request and how the MCU should acknowledge that
power, disabled state. request.
• SPI registers can still be accessed, but clocks to the • The interrupt vector offset and interrupt priority are
core of this module are disabled. chip dependent.
SPI in Wait Mode • The interrupt flags MODF, SPIF and SPTEF are
• SPI operation in wait mode depends upon the state of logically ORed to generate an interrupt request.
the SPISWAI bit in SPI Control Register 2. 1 MODF
• If SPISWAI is clear, the SPI operates normally when • MODF occurs when the master detects an error on the
the CPU is in wait mode SS pin. The master SPI must be configured for the MODF
 feature. Once MODF is set, the current transfer is aborted and
the following bit is changed:
• MSTR=0, The master bit in SPICR1 resets.
• The MODF interrupt is reflected in the status register
MODF flag. Clearing the flag will also clear the interrupt.
• This interrupt will stay active while the MODF flag is
set.
• MODF has an automatic clearing process
2 SPIF
• SPIF occurs when new data has been received and
copied to the SPI Data Register.
• Once SPIF is set, it does not clear until it is serviced.
• SPIF has an automatic clearing process
• In the event that the SPIF is not serviced before the
end of the next transfer (i.e. SPIF remains active throughout
another transfer), the latter transfers will be ignored and no
new data will be copied into the SPIDR.
3 SPTEF
SPTEF occurs when the SPI Data Register is ready to accept
new dataOnce SPTEF is set, it does not clear until it is
serviced. SPTEF has an automatic clearing process
5. What are the modes of operations of
SPI? What happens when mode fault
occurs in SPI?
Run Mode
• This is the basic mode of operation.
Wait Mode
• SPI operation in wait mode is a configurable low power
mode, controlled by the SPISWAI bit located in the
SPICR2 register.
• In wait mode, if the SPISWAI bit is clear, the SPI
operates like in Run Mode.
• If the SPISWAI bit is set, the SPI goes into a power
conservative state, with the SPI clock generation turned
off.
• If the SPI is configured as a master, any transmission in
progress stops, but is resumed after CPU goes into Run
Mode.
• If the SPI is configured as a slave, reception and
transmission of a byte continues, so that the slave stays
synchronized to the master.
Stop Mode
• The SPI is inactive in stop mode for reduced power
consumption. If the SPI is configured as a master, any
transmission in progress stops, but is resumed after
CPU goes into Run Mode.
• If the SPI is configured as a slave, reception and
transmission of a byte continues, so that the slave stays
synchronized to the master.
MODE FAULT ERROR
• If the SS input becomes low while the SPI is
configured as a master, it indicates a system error
where more than one master may be trying to drive the
MOSI and SCK lines simultaneously.
• This condition is not permitted in normal operation,
the MODF bit in the SPI Status Register is set
automatically provided the MODFEN bit is set.
• In the special case where the SPI is in master mode
and MODFEN bit is cleared, the SS pin is not used by
the SPI.
• In this special case, the mode fault error function is
inhibited and MODF remains cleared.
• In case the SPI system is configured as a slave, the SS
pin is a dedicated input pin. Mode fault error doesn’t
occur in slave mode.
• If a mode fault error occurs the SPI is switched to slave
mode, with the exception that the slave output buffer
is disabled.
• So SCK, MISO and MOSI pins are forced to be high
impedance inputs to avoid any possibility of conflict
with another output driver.
• A transmission in progress is aborted and the SPI is
forced into idle state.
• If the mode fault error occurs in the bidirectional
mode for a SPI system configured in master mode,
output enable of the MOMI (MOSI in bidirectional
mode) is cleared if it was set.
• No mode fault error occurs in the bidirectional mode
for SPI system configured in slave mode.
• The mode fault flag is cleared automatically by a read
of the SPI Status Register (withMODFset) followed
by a write to SPI Control Register 1.
• If the mode fault flag is cleared, the SPI becomes a
normal master or slave again.
MODF — Mode Fault Flag
This bit is set if the SS input becomes low while the SPI is
configured as a master and mode fault detection is enabled,
MODFEN bit of SPICR2 register is set. The flag is cleared
automatically by a read of the SPI Status Register (with
MODF set) followed by a write to the SPI Control Register 1.
1 = Mode fault has occurred.
0 = Mode fault has not occurred.
6. How baud rate is set in SPI? Explain
baud rate register? Show the
configuration for the maximum baud
rate in SPI.
➢ Baud rate generation consists of a series of divider
stages.
➢ Six bits in the SPI Baud Rate register (SPPR2, SPPR1,
SPPR0, SPR2, SPR1, and SPR0) determine the divisor to
the SPI module clock which results in the SPI baud rate.
➢ The SPI clock rate is determined by the product of the
value in the baud rate preselection bits (SPPR2–SPPR0)
and the value in the baud rate selection bits (SPR2–SPR0).
➢ The module clock divisor equation is shown .

➢ When all bits are clear (the default condition), the SPI
module clock is divided by 2.
➢ When the selection bits (SPR2–SPR0) are 001 and the
preselection bits (SPPR2–SPPR0) are 000, the module
clock divisor becomes 4.
➢ When the selection bits are 010, the module clock
divisor becomes 8 etc.
➢ When the preselection bits are 001, the divisor
determined by the selection bits is multiplied by 2.
➢ When the preselection bits are 010, the divisor is
multiplied by 3, etc. See
➢ The two sets of selects allows the clock to be divided
by a non-power of two to achieve other baud rates such as
divide by 6, divide by 10, etc.
➢ The baud rate generator is activated only when the
SPI is in the master mode and a serial transfer is taking
place. In the other cases, the divider is disabled to decrease
IDD current.
 ZIGBEE
1) What is the addressing mechanism in ZigBee?
➢ Each device in a network needs a unique address.
IEEE 802.15.4 uses two methods of addressing:
➢ 16-bit short addressing
➢ 64-bit extended addressing
➢ A network can choose to use either 16-bit or 64-bit
addressing.
➢ short address allows communication within a single
network.
➢ Using short addressing mechanism allows for a reduction
in length of messages & saves on required memory space that
is allocated for storing addresses.
➢ combination of a unique PAN identifier & a short address
can be used for communication between independent
networks.
➢ Availability of 64-bit addressing means that maximum
number of devices in a network can be 2 64 , or approximately
1.8* 10 .19
➢ Therefore, an IEEE 802.15.4 wireless network has
practically no limit on number of devices that can join
network.
➢ Network (NWK) layer of ZigBee protocol assigns a 16-
bit NWK address in addition to IEEE address.
➢ A simple lookup table is used to map each 64-bit IEEE
address to a unique NWK address.
➢ NWK layer transactions require use of NWK address.
➢ Each radio in a network can have a single IEEE address and
a single NWK address.
➢ But there can be up to 240 devices connected to a single
radio. Each one of these devices is distinguished by a number
between 1 & 240 known as the endpoint address.
ZIGBEE Addressing
• Addressing is the way in which a message gets from The MAC address,
one place to another in a network.
• ZigBee addressing takes into account all the information
shown in Table 4.3.
•
• both ZCs and ZRs are full-function devices and a ZED
is a reduced-function device
• ZigBee Coordinator (ZC)- Use a ZigBee Coordinator
to form a network.
• If network is secure, ZC must be present to add nodes
to network. Otherwise, once network starts, it's just a
router.
• it contains the Trust Center. Only the Trust Center can
decide whether to allow a node on a ZigBee network,
or to deny it access.
• ZigBee Router(ZR)- to enhance mesh in network.
ZigBee Routers can extend range of network and
increase its reliability.
• ZigBee End-Device (ZED)- if the node must be
battery-operated and sleep during network inactivity.
A ZED may be RxOnIde or not. When RxOnIdle is
false, ZEDs may sleep for long periods of time.
The Network Address
• The network address, also called NwkAddr, short
address, or node address, is a 16-bit number used to
uniquely identify a particular node on a ZigBee
network.
• The ZigBee Coordinator is always NwkAddr 0x0000.
• Yes, two ZigBee coordinators can exist on the same
channel with NwkAddr 0x0000, because they are on
different PAN IDs.
• also called IEEE address, long address, or extended
address, is a 64bit number
• uniquely identifies this board from all other ZigBee
boards in the world.
• The top 24 bits of this address consist of the
Organizational Unique Identifier (OUI).
• The lower 40 bits are managed by the OEM producing
the boards.
• The 64-bit MAC addresses have no direct relationship
to the 16-bit NwkAddr. If a node leaves one ZigBee
network and joins another, its MAC address will
remain the same, but the NwkAddr will likely change.
 2) How ZigBee gateway and ZigBee metaphor are
formed?
ZigBee gateway
• provides interface between a ZigBee network and
another network using a different standard.
• For eg, if ZigBee wireless networking is used to
gather patient information locally inside a room,
information might need to be transmitted over Internet to
a monitoring station.
• In this case, ZigBee gateway implements both ZigBee
protocol and Internet protocol to be able to translate
ZigBee packets to Internet protocol packet format, and
vice versa.
Zigbee metaphor
• One of the key characteristics of the ZigBee standard
is its mesh networking capability.
• In a large distributed mesh network, a message is
relayed from one device to another until it reaches its
faraway destination. Similarly, when a group of honey ZigBee Networking Topologies
bees, distributed in a large field, want to communicate a
message all the way back to their hive, they use message
relaying.
• Each bee performs a specific zigzag dance, which is
repeated by the next bee that is slightly closer to the hive.
• This process is repeated until the message gets to the
hive. The name ZigBee was selected as a metaphor for the
way devices on the network find and interact with one
another.
3)Compare ZigBee with Bluetooth based on the
technology and applications?
• Depending on radio class, Bluetooth has a network
range of 1 to 100 meters while Zigbee is up to 70 meters
with a maximum network speed of 1M bit per second
to 250 M bit per second respectively.
• Bluetooth has a protocol stack size of 250 Kilo bytes
and 28K bytes for Zigbee.
• Batteries for blue tooth devices are rechargeable
whereas for Zigbee they are not re chargeable but
longer lasting.
• Zigbee aims at automation whereas Bluetooth aims at
connectivity of mobile devices in close proximity.
• Zigbee uses low data rates, low power consumption on
small packet devices while blue tooth uses higher data
rates, higher power consumption on large packet
devices.
• Zigbee networks support longer range devices and
more in number compared to Bluetooth networks
whose range is small.
• Given Zigbee’s almost instant network join times(30
milliseconds) its more suitable for critical applications
while Bluetooth’s longer join time is detrimental (3
seconds).
•
4)What are the advantages of ZigBee over other
wireless networks? Explain various ZigBee network
topologies.
1. Compare ZigBee with wifi based on the technology
and applications?
1) star topology
• every device in the network can communicate
only with the PAN coordinator.
• A typical scenario in a star network formation
is that an FFD, programmed to be a PAN coordinator,
is activated and starts establishing its network.
• The first thing this PAN coordinator does is
select a unique PAN identifier that is not used by any
other network in its radio sphere of influence —the
region around the device in which its radio can
successfully communicate with other radios.
• In other words, it ensures that the PAN
identifier is not used by any other nearby network.
•
2) peer-to-peer topology
• each device can communicate directly with any other
device if the devices are placed close enough together to
establish a successful communication link.
• Any FFD in a peer-to-peer network can play the role
of the PAN coordinator.
• One way to decide which device will be the PAN
coordinator is to pick the first FFD device that starts
communicating as the PAN coordinator.
• In a peer-to-peer network, all the devices that
participate in relaying the messages are FFDs because
RFDs are not capable of relaying the messages.
• However, an RFD can be part of the network and
communicate only with one particular device (a
coordinator or a router) in the network.
• A peer-to-peer network can take different shapes by
defining restrictions on the devices that can communicate
with each other. If there is no restriction, the peer-to-peer
network is known as a mesh topology . Another form of
peer-to-peer network ZigBee supports is a tree topology.
• method (assuming that transmission does not occur
• for
for TREE: a ZigBee coordinator (PAN coordinator)
establishes the initial network. ZigBee routers form the
branches and relay the messages. ZigBee end devices act
as leaves of the tree and do not participate in message
routing. ZigBee routers can grow the network beyond the
initial network established by the ZigBee coordinator.
Data Transfer from a Coordinator
5) What are the different types of data transfer
mechanism existing in ZigBee?
There are three types of data transfer in IEEE 802.15.4:
● Data transfer to a coordinator from a device
● Data transfer from a coordinator to a device
● Data transfer between two peer devices
All three methods can be used in a peer-to-peer
topology. In a star topology, only the first two are
used, because no direct peer-to-peer communication is
allowed.
Data Transfer to a Coordinator
• In a beacon-enabled network, when a device decides
to transmit data to the coordinator, device
synchronizes its clock on a regular basis and
transmits data to coordinator using CSMA-CA
during a GTS).
• coordinator may acknowledge reception of date
only if it is requested by data transmitter.
• This sequence chart is shown
•
• shows the data transfer sequence in a nonbeacon-
enabled network. In this scenario, the device
transmits the data as soon as the channel is clear.
• The transmission of an acknowledgment by the PAN
coordinator is optional.
• Fig illustrates the data transmission steps to transfer
data from a coordinator to a device in a beacon-
enabled network.
• If the coordinator needs to transmit data to a
particular device, it indicates in its beacon message
that a data message is pending for that device.
•
• The device then sends a data request message to the place, and some designated devices always act as
coordinator indicating that it is active and ready to routers in the network.
receive the data. 7) Give the functional overview of the ZigBee and
• The coordinator acknowledges the receipt of the data IEEE 802.15.4 protocol layers.
request and sends the data to the device. Sending the 1) PHY Layer
acknowledgment by the device is optional. • In ZigBee wireless networking fig below,
• In a nonbeacon-enabled network, coordinator needs
to wait for the device to request the data.
• If the device requests data but there is no data
pending for that device, coordinator sends an
acknowledgment message with a specific format that
indicates there is no data pending for that device.
Alternatively, the coordinator may send a data
message with a zero-length payload.
Peer-to-Peer Data Transfer
• In a peer-to-peer topology, each device can
communicate directly with any other device.
• In many applications, the devices engaged in peer-to-
peer data transmissions and receptions are
synchronized.
•
6) What are the self forming and self healing the lowest protocol layer is the IEEE 802.15.4
characteristics of the ZigBee? Physical layer, or PHY.
• ZigBee network starts its formation as soon as devices • This layer is closest layer to hardware and directly
become active. controls and communicates with the radio transceiver.
• In a mesh network, for eg, the first FFD device that • The PHY layer is responsible for activating the radio
starts communicating can establish itself as the ZigBee that transmits or receives packets.
coordinator, and other devices then join the network • The PHY also selects the channel frequency and
by sending association requests. makes sure the channel is not currently used by any
• Because no additional supervision is required to other devices on another network.
establish a network, ZigBee networks are considered 1.1 PHY Packet General Structure
self-forming networks . • Data and commands are communicated between
• On the other hand, when a mesh network is various devices in the form of packets.
established, there is normally more than one way to • The general structure of a packet is shown in Figure.
relay a message from one device to another. Here first transmitted bit is the LSB of SHR. The
• Naturally, the most optimized way is selected to route MSB of last octet of PHY payload is transmitted
the message. last.
• However, if one of the routers stops functioning due
to exhaustion of its battery or if an obstacle blocks the
message route, the network can select an alternative
route.
• This is an example of the self-healing characteristic of
ZigBee mesh networking. ZigBee is considered an ad
hoc wireless network.
• In an ad hoc wireless network, some of the wireless
nodes are willing to forward data for other devices.
• The route that will carry a message from the source to
the destination is selected dynamically based on the • The PHY packet consists of three components:
network connectivity. • The Synchronization header (SHR)- enables
• If the network condition changes, it might be receiver to synchronize and lock into the bit stream.
necessary to change the routing in the network. • The PHY header (PHR)- contains frame length
• This is in contrast to some other networking information,
technologies in which there is an infrastructure in
 • The PHY payload - is provided by upper layers and ● Beacon frame- used by a coordinator to transmit beacons.
includes data or commands for the recipient device.
• The MAC frame, which is transmitted to other
devices as a PHY payload, has three sections.
• The MAC header (MHR) -contains information
such as addressing and security.
• The MAC payload - has a variable length size
(including zero length) and contains commands or
data.
• The MAC footer (MFR)- contains a 16-bit Frame
Check Sequence (FCS) for data verification.
• The NWK frame has two parts:
• the NWK header (NHR) - has network-level
addressing and control information.
• the NWK payload- is provided by the APS sublayer.
• In the APS sublayer frame
• APS header (AHR)- has application-layer control • MAC header (MHR)
and addressing information.
• auxiliary frame header (auxiliary HDR) -contains • frame control field in MHR contains information defining
mechanism used to add security to frame and
security keys used.
• These security keys are shared among the
corresponding devices and help unlock the
information. The NWK and MAC frames can also
have optional auxiliary headers for additional
security.
• APS payload contains data or commands.
• Message Integrity Code (MIC)- is a security feature
in the APS frame that is used to detect any
unauthorized change in the content of the message.
2) MAC Layer
• The Medium Access Control (MAC) layer provides
interface between PHY layer and NWK layer.
• The MAC is responsible for generating beacons and
synchronizing device to beacons (in a beacon-
enabled network).
• The MAC layer also provides association and
disassociation services.
2.1 MAC Frame Structures
The IEEE 802.15.4 defines four MAC frame structures:
The beacons are used to synchronize clock of all devices
within same network.
● Data frame- used to transmit data
● Acknowledge frame- acknowledge the
successful reception of a frame.
● MAC command frame-commands are transmitted using a
MAC command frame.
THE BEACON FRAME
• The structure is shown.
• entire MAC frame is used as a payload in a PHY packet.
The content of the PHY payload is referred to as the PHY
Service Data Unit (PSDU).
• In the PHY packet, preamble field is used by the receiver
for synchronization.
• The start-of-frame delimiter (SDF) indicates the end of
SHR and start of PHR.
• The frame length specifies the total number of octets in
the PHY payload (PSDU).
• The MAC frame consists of three sections:
• MAC payload
• MAC footer (MFR)
frame type, addressing fields, and other control flags.
• sequence number specifies beacon sequence number
(BSN).
• addressing field provides source and destination addresses.
• auxiliary security header is optional and contains
information required for security processing.
• MAC payload is provided by the NWK layer.
• superframe is a frame bounded by two beacon frames.
• superframe is optionally used in a beacon enabled network
and helps define GTSs.
• GTS field in MAC payload determines whether a GTS is
used to receive or transmit.
• beacon frame is not only used to synchronize devices in a
network but is also used by coordinator to let a specific
device in a network know there is data pending for that
device in coordinator.
• The device, at its discretion, will contact the coordinator and
request that it transmit the data to the device. This is called
indirect transmission.
THE DATA FRAME
• data payload is provided by the NWK layer
• data in MAC payload is referred to as MAC Service 4) The APL Layer
Data Unit (MSDU).
• fields in this frame are similar to the beacon frame
except the superframe, GTS, and pending address
fields are not present in the MAC data frame.
MAC data frame is referred to as MAC Protocol
Data Unit (MPDU) and becomes PHY payload.
THE ACKNOWLEDGMENT FRAME
• simplest MAC frame format and does not carry any
MAC payload.
• acknowledgment frame is sent by one device to
another to confirm successful reception of a packet. •
THE COMMAND FRAME
• The MAC commands such as requesting association
or disassociation with a network are transmitted
using the MAC command frame
• The command type field determines the type of the
command (e.g., association request or data request).
The command payload contains the command itself.
• The entire MAC command frame is placed in the
PHY payload as a PSDU.
3) The NWK Layer
• NWK layer interfaces between the MAC and APL and
is responsible for managing the network formation and
routing.
• Routing is process of selecting path through which
message will be relayed to its destination device.
• ZigBee coordinator and routers are responsible for
discovering and maintaining the routes in the network.
• A ZigBee end device cannot perform route discovery.
• ZigBee coordinator or a router will perform route
discovery on behalf of the end device.
• NWK layer of a ZigBee coordinator is responsible for
establishing a new network and selecting network topology
(tree, star, or mesh).
• ZigBee coordinator also assigns NWK addresses to
the devices in its network.
• The application (APL) layer is highest protocol layer
in the ZigBee wireless network and hosts t application
objects.
• Manufacturers develop application objects to
customize a device for various applications.
• Application objects control and manage the protocol
layers in a ZigBee device. There can be up to 240 application
objects in a single device.
• ZigBee standard offers option to use application
profiles in developing an application.
An application profile is a set of agreements on
application-specific message formats and processing actions.
• The use of an application profile allows further
interoperability between the products developed by different
vendors for a specific application.
• If two vendors use same application profile to develop
their products, product from one vendor will be able to
interact with products manufactured by other vendor as
though both were manufactured by the same vendor.
5) Security
• In a wireless network, the transmitted messages can be
received by any nearby device, including an intruder.
• There are two main security concerns in a wireless
network.
• first one is data confidentiality . The intruder device
can gain sensitive information by simply listening to the
transmitted messages.
• Encrypting messages before transmission will solve
confidentiality problem.
• An encryption algorithm modifies a message using a
string of bits known as the security key, and only the
intended recipient will be able to recover the original
message.
• The IEEE 802.15.4 standard supports use of
Advanced Encryption Standard (AES) to encrypt their
outgoing messages.
• The second concern is that intruder device may
modify and resend one of previous messages even if
messages are encrypted.
 • Including a message integrity code (MIC) with each Three rules govern the piggybacking data transfer.
outgoing frame will allow the recipient to know whether the
message has been changed in transit. This process is known • If station A wants to send both data and an
as data authentication . acknowledgment, it keeps both fields there.
• One of main constraints in implementing security • If station A wants to send just the acknowledgment,
features in a ZigBee wireless network is limited resources. then a separate ACK frame is sent.
• nodes are mainly battery powered and have limited • If station A wants to send just the data, then last
computational power and memory size. acknowledgment field is sent along with data. Station
• ZigBee is targeted for low-cost applications and B simply ignores this duplicate ACK frame upon
hardware in nodes might not be tamper resistant. receiving .
• If an intruder acquires a node from an operating
network that has no tamper resistance, the actual key could Advantages :
be obtained simply from the device memory.
• A tamper-resistant node can erase sensitive • Improves the efficiency
information, including security keys, if tampering is
detected. • better use of available channel bandwidth
9) What is piggy backing in communication?
In all practical situations, the transmission of data needs to be disadvantages
bi-directional. This is called as full-duplex transmission. • Additional complexity.
We can achieve this full duplex transmission i.e. by having • If the data link layer waits too long before transmitting
two separate channels-one for forward data transfer and the the acknowledgement, then retransmission of frame
other for separate transfer i.e. for acknowledgements. would take place.
• The receiver can jam the service if it has nothing to
• A better solution would be to use each channel (forward & send. This can be solved by enabling a counter
reverse) to transmit frames both ways, with both channels (Receiver timeout) when a data frame is received. If
having the same capacity. If A and B are two users. Then the the count ends and there is no data frame to send, the
data frames from A to Bare intermixed with the receiver will send an ACK control frame. The sender
acknowledgements from A to B. also adds a counter (Emitter timeout), if the counter
• One more improvement that can be made is ends without receiving confirmation, the sender
piggybacking. The concept is explained as follows: assumes packet loss, and sends the frame again
• In two-way communication, wherever a frame is
received, receiver waits and does not send control
frame (acknowledgement or ACK) back to sender
immediately.
• The receiver waits until its network layer passes in the
next data packet.
• The delayed acknowledgement is then attached to this
outgoing data frame.
• technique of temporarily delaying acknowledgement
so that it can be hooked with next outgoing data frame
is known as piggybacking.

Working Principle
• In the data frame itself, we incorporate one additional
field for acknowledgment (called ACK).
• Whenever party A wants to send data to party B, it will
send data along with this ACK field.
• Considering sliding window here of size 8 bits, if A
has send frames up to 5 correctly (from B), and wants
to send frames starting from frame 6, it will send
ACK6 with the data.

USB
1) What is the type of encoding used in USB data
transmission? How synchronization is achieved in
the transmission?
➢ The Universal Serial Bus (USB) protocol is designed
to enable communication between many devices by
sharing a data bus.
➢ A USB system consists of one host and many devices
Encoding Scheme
➢ The USB employs NRZI (Non Return to Zero
Inversion) encoding mechanism to encode the data on
the bus. In NRZI encoding, a ‘1’ is represented by no
change in level while a ‘0’ is represented by change in
level. Together with NRZI encoding, bit stiffing and End of Packet
SYNC field is used for synchronization between host
and device
SYNC field
➢ The bit stiffing alone is not enough to take care of the
synchronization between transmitter and receiver. To
keep transmitter and receiver synchronized, SYNC
field is used. In this mechanism, each packet begins
with a SYNC field which enables the receiver to
synchronize the clock
➢ For low/full speed, SYNC field is of 8 bits:
KJKJKJKK. The first k serves as Start of Packet. For
high speed, SYNC field is of 32 bits: fifteen KJ
repetitions, followed by KK. The alternate Ks and Js
provide transitions for synchronizing and the final two
KKs mark the end of SYNC field.
The End of Packet that is SE0 for 2-bit times followed by J
state for 1-bit time marks the end of packet.

2) Why UBS devices and plug-n-play and hot

swappable?
• USB (Universal Serial Bus) refers to any device that
➢ can store data in flash memory with a USB integrated
interface.
Bit stiffing

➢ When long series of zeros are transmitted using NRZI,
it causes a transition in the levels. But when long series
of one’s is transmitted, no transition takes place as per
NRZI encoding scheme. No transition in levels for a
long time can confuse the receiver and makes it
desynchronized.
➢ Bit stiffing is a process in which a zero is inserted in
raw data after every six consecutive ones. The
inserting of zero causes transition in level. The
receiver must recognize the stuffed bits and discard
them after decoding the NRZI data.
➢ In case if no transition takes place in NRZI signal after
six consecutive one’s, then the receiver decides that bit
stiffing has not been done and discards the data
received.
• A Universal Serial Bus (USB) is a common interface
that enables communication between devices and a
host controller such as a personal computer (PC).
• A USB drive is also known as USB Key, USB
stick, USB flash drive and other names.
• USB drives are quite small in size and most weigh less
than 35 gram. Some of the devices that can be
connected using a USB connection include: webcams,
printers, digital camera, external hard drives, mouse,
keyboards, and scanners.
• Flash drives are one of the most popular “Plug and
Play” devices that are commonly used all over the
world. Once the device is plugged into a computer, the
PC OS automatically identifies the required drives for
displaying content and files stored on the drive.

• A USB is intended to enhance plug-and-play and

allow hot swapping. Plug-and-play enables the
operating system (OS) to spontaneously configure and
discover a new peripheral device without having to
➢
 restart the computer. As well, hot swapping allows • However, care should be taken when hot swapping
removal and replacement of a new peripheral without certain devices such as a camera; damage can occur to
having to reboot. the port, camera or other devices if a single pin is
accidently shorted.
• It is designed for easy installation, faster transfer rates,
higher quality cabling and hot swapping. • The goal of Plug and Play is to create a computer
whose hardware and software work together to
• It has conclusively replaced the bulkier and slower automatically configure devices and assign
serial and parallel ports. resources, to allow for hardware changes and
additions without the need for large-scale
• Plug and Play (PnP) is a technology that allows the
resource assignment tweaking. As the name
operating system to detect and configure internal and suggests, the goal is to be able to just plug in a
external peripherals as well as most adapters. new device and immediately be able to use it,
• It has the ability to find and configure hardware without complicated setup maneuvers.
components without having to reset DIP switches and
jumpers.
• When booting a PC, PnP identifies the attached
peripheral devices and regulates the proper internal
settings by configuring the direct memory access
(DMA), interrupt requests (IRQ) and input/output
(I/O) addresses.
• One of the greatest features of the USB is hot
swapping.

• Hot plugging (also called hot swapping) is the ability

to add and remove devices to a computer system while
the computer is running and have the operating
system automatically recognize the change.
• This is useful when a system component fails as it
enables a new device to be installed without system
downtime.
• This feature allows a device to be removed or replaced
without the past prerequisite of rebooting and
interrupting the system.

• Older ports required that a PC be restarted when

adding or removing a new device.

• Rebooting allowed the device to be reconfigured and

prevented electrostatic discharge (ESD), an unwanted
electrical current capable of causing serious damage to
sensitive electronic equipment such as integrated
circuits.

• Hot swapping is fault tolerant, i.e. able to continue

operating despite a hardware failure.

UART
1. How UART is connected to the COM port
and USB port of the PC
2. Why long-distance serial communication
uses negative voltage for signaling. Give
examples
• less susceptible to noise, interference, and
degradation
• still providing a reliable data transmission
• eg: RS232
• RS-232 standard a logic high ('1') is
represented by a negative voltage – anywhere
from -3 to -25V – while a logic low ('0')
transmits a positive voltage that can be
anywhere from +3 to +25V. On most PCs
these signals swing from -13 to +13V.
•
• •
3. Why negative voltage is used in RS232 bus?
• The RS-232 voltage levels are important
because they enable system to be designed to
ensure that data errors are minimise.
• By assigning levels to the mark and Space
conditions, with a band in between it ensures
that data errors are minimised.
• In addition to this the operation of the
handshaking with lines including RST, CTS
and DTR, the operation of the system can be
reliable and only send data when all
equipment is ready.
• The dead area between +3v and -3v is
designed to absorb line noise.
• In RS232 specification low level -3v to-15v
is defined as logic ‘1’ is ON state and referred
as ‘Marking’
• while high level +3v to +15v is defined as
logic ‘0’ as OFF state and known as
‘Spacing’.
• The RS232 standard also limits the
maximum slew rate which reduces the cross-
talk between the two signals.
• Slew rate is defined as the rate of change of
out-put voltage with respect to time.
• The maximum allowable slew rate in RS232
is 30v/micro-seconds which slows down the
rise and fall time and reduces the cross-talk.
4. Differentiate hub, switch, router and
gateway in computer networks.
Router?
• The router forwards data packets along networks.
• Router is mainly a Network Layer device.
• A router is a device like a switch that routes data
packets based on their IP addresses.
• It is connected to at least two networks, commonly
two LANs or WANs or a LAN and its ISP's network.
• Routers are located at gateways, the places where two
or more networks connect.
Routers use headers and forwarding tables to
determine the best path for forwarding the packets,
• they use protocols to communicate with each other
and configure the best route between any two hosts
Switch
• In networks the switch is the device that filters and
forwards packets between LAN segments.
• Switch is data link layer device.
• Switches operate at the data link layer (layer 2) and
sometimes the network layer (layer 3) of the OSI
Reference Model and therefore support any packet
protocol.
• LANs that use switches to join segments are called
switched LANs or, in the case of Ethernet networks,
switched Ethernet LANs.
• keeps a record of the MAC addresses of all the
devices connected to it.
• With this information, a switch can identify which
system is sitting on which port.
• So when a frame is received, it knows exactly which
port to send it to, without significantly increasing
network response times
 • Switch can perform error checking before forwarding • Each specific I/O device may be connected to other
data, that makes it very efficient as it does not forward using specific interfaces, for example, with I/O device
packets that have errors and forward good packets for example, LCD controller, keyboard controller and
selectively to correct port only. print controller.
Hub • Bus communication simplifies the number of
connections and provides a common way (protocol) of
• A hub is a common connection point for devices in a
connecting different or same type of I/O devices
network.
• A hub connects multiple wires coming from different
branches,
• for example, the connector in star topology which
connects different stations.
• Hubs cannot filter data, so data packets are sent to all
connected devices.
• Hubs connect segments of a LAN.
• It contains multiple ports so when a packet arrives at
one port, it is copied to the other ports so that all
segments of the LAN can see all packets.
Gateway
• A gateway, as the name suggests, is a passage to
connect two networks together that may work
upon different networking models.
• They basically works as the messenger agents that
take data from one system, interpret it, and transfer IO Bus
it to another system. • I/O devices communicate with the processor through
• Gateways are also called protocol converters and an I/O bus, which is separate from the memory bus
can operate at any network layer. that the processor uses to communicate with the
• Gateways are generally more complex than memory system.
switch or router. • A bus has a fixed bandwidth that must be shared by
all of the devices on the bus.
5. How embedded network is different from Embedded systems Networking
computer network? • Embedded systems connected internally on same IC
• A computer network is a set of connected or systems at very short, short and long distances can
computers. Computers on a network are be networked using a type of the I/O buses- CAN, I
called nodes. 2C, USB, PCI, …
• The connection between computers can be serial bus
done via cabling, most commonly the • A serial bus has very few lines and the number of lines
Ethernet cable, or wirelessly through radio as per the protocol
waves. • A wide range of I/O devices without having to implement
• Connected computers can share resources, a specific interface for each I/O device.
like access to the Internet, printers, file Parallel bus
servers, and others.
• Using a parallel I/O bus allows a computer or
• Embedded networks are private electricity
controller or embedded system to interface with
networks that supply homes or businesses
number of internal systems at very short distances
within a specific area. They are common in
without having to implement a specific interface for
apartment buildings, shopping centres,
each I/O device
caravan parks and retirement villages.
6. What are the important features of the
communication buses used in embedded
networks?
• Bus Communication for networking Bus
Communication for networking
 determined by the one with the shortest clock HIGH
period.
I2C
1)How the clock synchronization and
arbitration is done in multimaster
configuration of I2C bus
• Two masters can begin transmitting on a free bus at
the same time and there must be a method for deciding
which takes control of the bus and complete its
transmission.
• This is done by clock synchronization and arbitration.
• In single master systems, clock synchronization and
arbitration are not needed.
clock synchronization
➢ performed using the wired-AND connection
of I2C interfaces to the SCL line.
➢ This means that a HIGH to LOW transition
on the SCL line causes the masters concerned
to start counting off their LOW period and,
once a master clock has gone LOW, it holds
the SCL line in that state until the clock
HIGH state is reached.
➢
➢ However, if another clock is still within its LOW
period, the LOW to HIGH transition of this clock may not
change the state of the SCL line.
➢ The SCL line is therefore held LOW by the master
with the longest LOW period.
➢ Masters with shorter LOW periods enter a HIGH wait-
state during this time.
➢ When all masters concerned have counted off their
LOW period, the clock line is released and goes HIGH.
➢ There is then no difference between the master clocks
and the state of the SCL line, and all the masters start
counting their HIGH periods.
➢ The first master to complete its HIGH period pulls the
SCL line LOW again.
➢ In this way, a synchronized SCL clock is generated
with its LOW period determined by the master with the
longest clock LOW period, and its HIGH period
➢
Arbitration
➢ Arbitration, like synchronization, refers to a
portion of the protocol required only if more than one
master is used in the system.
➢ Slaves are not involved in the arbitration
procedure. A master may start a transfer only if the bus
is free.
➢ Two masters may generate a START
condition within the minimum hold time (tHD;STA)
of the START condition which results in a valid
START condition on the bus.
➢ Arbitration is then required to determine which
master will complete its transmission. Arbitration
proceeds bit by bit.
➢ During every bit, while SCL is HIGH, each
master checks to see if the SDA level matches what it
has sent.
➢ This process may take many bits.
➢ Two masters can actually complete an entire
transaction without error, as long as the transmissions
are identical.
➢ The first time a master tries to send a HIGH,
but detects that the SDA level is LOW, the master
knows that it has lost the arbitration and turns off its
SDA output driver.
➢ The other master goes on to complete its
transaction.
➢ No information is lost during the arbitration
process.
➢ A master that loses the arbitration can generate
clock pulses until the end of the byte in which it loses
the arbitration and must restart its transaction when the
bus is free.
➢ If a master also incorporates a slave function
and it loses arbitration during the addressing stage, it
is possible that the winning master is trying to address
it.
➢ The losing master must therefore switch over
immediately to its slave mode.
 ➢ the following combinations result in an
undefined condition:
• Master 1 sends a repeated START condition
and master 2 sends a data bit.
• Master 1 sends a STOP condition and
master 2 sends a data bit.
• Master 1 sends a repeated START condition
and master 2 sends a STOP condition.
2)What are the steps to be done to write
data 0xFF to the slave (slave address 0x66)
using i2c protocol? Explain using timing
diagram.
Suppose a master wants to send data to a slave:
• Master-transmitter sends a START condition and
addresses the slave-receiver
• Master-transmitter sends data to slave-receiver
• Master-transmitter terminates the transfer with a
STOP condition
To write on the I 2C bus, the master will send a start
condition on the bus with the slave's address, as well as the
last bit (the R/W bit) set to 0, which signifies a write. After
the slave sends the acknowledge bit, the master will then
send the register address of the register it wishes to write to.
The slave will acknowledge again, letting the master know
it is ready. After this, the master will start sending the
register data to the slave, until the master has sent all the
data it needs to (sometimes this is only a single byte), and
the master will terminate the transmission with a STOP
condition.
3)How the one byte of data is read from the
slave device in I2C interfacing?
• Reading from a slave is very similar to writing, but
with some extra steps.
• In order to read from a slave, the master must first
instruct the slave which register it wishes to read from.
• This is done by the master starting off the
transmission in a similar fashion as the write, by sending
the address with the R/W bit equal to 0 (signifying a
write), followed by the register address it wishes to read
from.
• Once the slave acknowledges this register address, the
master will send a START condition again, followed by
the slave address with the R/W bit set to 1 (signifying a
read).
• This time, the slave will acknowledge the read request,
and the master releases the SDA bus, but will continue
supplying the clock to the slave.
• During this part of the transaction, the master will
become the master-receiver, and the slave will become the
slave-transmitter.
• The master will continue sending out the clock pulses,
but will release the SDA line, so that the slave can transmit
data.
• At the end of every byte of data, the master will send
an ACK to the slave, letting the slave know that it is ready
for more data.
• Once the master has received the number of bytes it is
expecting, it will send a NACK, signaling to the slave to
halt communications and release the bus.
• The master will follow this up with a STOP condition.
 ➢ As Standard-mode devices, however, are not upward
compatible; they should not be incorporated in a Fast-
mode I2C-bus system as they cannot follow the higher
transfer rate and unpredictable states would occur.
➢ The Fast-mode I2C-bus specification has the
following additional features compared with the
Standard-mode:
• The maximum bit rate is increased to 400
kbit/s. Standard-mode (Sm), with a bit rate up
to 100 kbit/s
• Timing of the serial data (SDA) and serial
clock (SCL) signals has been adapted.There is
• no need for compatibility with other bus
4)What is the default signal voltage level systems such as CBUS because they cannot
on I2C? Why? How bulk data is operate at the increased bit rate.
transmitted on I2C bus • The inputs of Fast-mode devices incorporate
• Due to the open drain structure of the bus, spike suppression and a Schmitt trigger at the
voltage level in the bus is fixed by the voltage SDA and SCL inputs.
connected to the pull-up resistor. • The output buffers of Fast-mode devices
• If different voltage levels are required (e.g., incorporate slope control of the falling edges
master core at 1.8 V, legacy I2C bus at 5 V of the SDA and SCL signals.
and new devices at 3.3 V), voltage level • If the power supply to a Fast-mode device is
translators need to be used switched off, the SDA and SCL I/O pins must
be floating so that they do not obstruct the bus
lines.

6)How a transmission start and stop

conditions are indicated in I2C bus?

•
Data on the I2C bus is transferred in 8-bit packets
(bytes). There is no limitation on the number of
bytes, however, each byte must be followed by an
Acknowledge bit. This bit signals whether the device
is ready to proceed with the next byte. For all data
bits including the Acknowledge bit, the master must
generate clock pulses. If the slave device does not
acknowledges transfer this means that there is no
more data or the device is not ready for the transfer The master always generates START and STOP
yet. The master device must either generate Stop or conditions. The bus is considered to be busy after the
Repeated Start condition. START condition. The bus is considered to be free
again a certain time after the STOP condition. The
5)What are the differences between bus stays busy if a repeated START (Sr) is generated
standard mode and fast mode of I2C? instead of a STOP condition.
➢ The protocol, format, logic levels and maximum
capacitive load for the SDA and SCL lines are the 7)Explain data read and write operation to
same as the Standard-mode I2C-bus specification. a slave device in I2C interfacing?
➢ Fast-mode devices are downward-compatible and can
communicate with Standard-mode devices in a 0 to
100 kbit/s I2C-bus system.
 8_)What are the means to avoid chaos
when more than one master is trying to get
bus access in I2C?
• The possibility of connecting more than one
microcontroller to the I2C-bus means that
more than one master could try to initiate a
data transfer at the same time.
• To avoid the chaos that might ensue from
such an event, an arbitration procedure has
been developed.
• This procedure relies on the wired-AND
connection of all I2C interfaces to the I2C-
bus. If two or more masters try to put
information onto the bus, the first to produce
a ‘one’ when the other produces a ‘zero’ loses
the arbitration.
• The clock signals during arbitration are a
synchronized combination of the clocks
generated by the masters using the wired-
AND connection to the SCL line
• Arbitration, like synchronization, refers to a
portion of the protocol required only if more
than one master is used in the system.

9)What are the conditions which generate

a NACK status?
1. No receiver is present on the bus with the transmitted
address so there is no device to respond with an
acknowledge.
2. The receiver is unable to receive or transmit because
it is performing some real-time function and is not
ready to start communication with the master.
3. During the transfer, the receiver gets data or
commands that it does not understand.
4. During the transfer, the receiver cannot receive any
more data bytes.
5. A master-receiver must signal the end of the transfer
to the slave transmitter.

ETHERNET
1)Draw frame format for IEEE802.3 LAN
packet format. Calculate maximum and
minimum size of a frame.
802.3 MAC frame
Disadvantages of Ethernet:
◼ Preamble:
◼ 8 bytes with pattern 10101010 used to
synchronize receiver, sender clock rates.
◼ In IEEE 802.3, eighth byte is start of frame
(10101011)
◼ Addresses: 6 bytes (explained latter)
◼ Type (DIX)
◼ Indicates the type of the Network layer
protocol being carried in the payload (data)
field, mostly IP but others may be supported
such as IP (0800), Novell IPX (8137) and
AppleTalk (809B), ARP (0806) )
◼ Allow multiple network layer protocols to be
supported on a single machine (multiplexing)
◼ Its value starts at 0600h (=1536 in decimal)
◼ Length (IEEE 802.3): number of bytes in the data
field.
◼ Maximum 1500 bytes (= 05DCh)
◼ CRC: checked at receiver, if error is detected, the
frame is discarded
◼ CRC-32
◼ Data: carries data encapsulated from the upper-layer
protocols
◼ Pad: Zeros are added to the data field to make the
minimum data length = 46 bytes
2)Why Ethernet is not very popular in
embedded systems even though it’s a
widely used network protocol in computer
systems?
• Ethernet is Local Area Network (LAN) technology.
• It is a system with protocol to connect multiple
systems on the LAN network connection.
• Ethernet offers connectionless communication.
➢ It offers nondeterministic service.
➢ It does not hold good for real-time applications as it
requires deterministic service.
➢ As network cannot set priority for the packets, it is not
suitable for a client-server architecture.
➢ In an interactive application, data is very small and
need quick data transfer. In ethernet, there is a limit of
the minimum size of the frame to 46B. The result of
that, it is not a good choice for interactive
applications.
➢ If you are using it for interactive applications, you
have to feed dummy data to make the frame size
46B which is mandatory.
➢ Not suitable for traffic intensive applications. If the
traffic on the Ethernet increases, the efficiency of the
Ethernet goes down.
➢ It provides connectionless communication over the
network.
➢ After receiving a packet, the receiver doesn’t send
any acknowledge.
➢ If there is any problem in ethernet, it is difficult to
troubleshoot what cable or node in the network
causing an actual problem.