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1 1

LCFC Confidential
NANO G ACL CG521 M/B Schematics Document
2 2

AMD FP4 Carrizo L SOC with DDRIIIL


AMD R16M-M1-30

2016-02-24
3
REV:1.0 3

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/15 Deciphered Date 2013/08/15 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Tuesday, March 08, 2016 Sheet 1 of 50
A B C D E
A B C D E

LCFC confidential
File Name : CG521
AMD R16M-M1-30
S3 Package: 23mmX23mm PCI-Express
Page 18~24 4x Gen2 Memory BUS (DDR3L)
Single Channel B DDR3L-SO-DIMM X1
Page 12
VRAM 256*16 PEG 0~3
1
1.35V DDR3L 1600 MT/s 1

DDR3L*4 2GB 1333MT/s UP TO 8G


Page 14~22

USB Left
HDMI Conn. HDMI x4 Lane Port1 USB 3.0 1x
Page 25 AMD FP4 APU USB 2.0 Port0

USB 2.0 2x
eDP x2 Lane
Carrizo L 15W JUSB1
USB 2.0 Port7
Int. Camera Page 32
USB 3.0 Port3
USB2.0 Port5
USB2.0 1x JUSB2

eDP Conn (Integrated FCH)


Page 23

2 2

SATA HDD SATA Gen3 USB2.0 1x


Page 33 SATA Port0 Cardreader Realtek SD/MMC Conn.
BGA-968 RTS5170 USB2.0 Port2
37mm*29mm USB Board
SATA ODD SATA Gen1
Page 33 SATA Port1

USB 2.0 1x NGFF Card


WLAN&BT
LAN Realtek PCIe 1x Key E
RJ45 Conn. PCIe 1x PCIe Port1
Page 29
RTL8106E Page 31 USB2.0 Port4

3 3
Page 28 PCIe Port2
SPI BUS SPI ROM
HD Audio
Page 4~11 8MB Page 08
TPM
Codec SPK Conn. reserve Page 30
Realtek ALC3248 Page 34
Page 34

EC Thermistor
ITE IT8586E-LQFP Page 30
Page 35

Int. MIC HP&Mic Combo Conn.


Page 34 Page 34 Sub-board ( for 15")

Touch Pad Int.KBD Thermal Sensor ODD Board


4 Page 36 Page 36 NCT7718W 4
Page 30 reserve

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/15 Deciphered Date 2013/08/15 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Tuesday, March 08, 2016 Sheet 2 of 50
A B C D E
A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )


SIGNAL BOARD
+5VS STATE SLP_S3# SLP_S5# +VALW +V +VS Clock Config. BOARD_ID0 BOARD_ID1 BOARD_ID2 Function
+3VS 0: 14'' 0: Dis
S0 (Full ON) HIGH HIGH ON ON ON ON
+1.8VS 1: 15'' 1: UMA
power +1.5VS S1 (Power On Suspend) HIGH HIGH ON ON ON LOW
plane B+ +5VALW
(+20VSB) +1.35V +0.95VS
1 (+VSYSMEM_APU) S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF 1
+3VALW +0.675VS
+3VL (+3VALW_APU)
+APU_CORE S4 (Suspend to Disk) LOW LOW ON OFF OFF OFF
+5VLP +APU_CORE_NB
+1.8VALW S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+APU_GFX
+0.95VALW +VGA_CORE
State
+3VGS USB Port Table for CarrizoL
+0.775VALW
+1.8VGS
+1.35VGS
USB 2.0 USB 3.0 Port Port device
+0.95VGS 0 RIGHT USB (2.0) BOM Structure Table
1 N/A BOM Structure BTO Item
EHCI0
2 Card Reader @ Not stuff
S0 O O O O 3 Touch screen ME@ Connector
4 Blue Tooth 14@ For 14" part
EHCI1
S3
O O O X 5 Camera 15@ For 15" part
0 6 LEFT USB (3.0) EMC@ EMC Part
xHCI
S5 S4/AC
1 7 LEFT USB (3.0) EMC_NS@ EMC reserve Part
2 O O X X EMC_PX@ EMC GPU part 2

USB Port Table for Carrizo EMC_CZ@ EMC Carrizo APU part
S5 S4/ Battery only EMC_15@ EMC 15 part
O X X X USB 2.0 USB 3.0 Port Port device
RF_NS@ RF reserve Part

S5 S4/AC & Battery


0 RIGHT USB (2.0) RF_PXNS@ RF GPU reserve part
don't exist X X X X 1 N/A UMA@ UMA SKU ID part
EHCI0
2 Card Reader PX@ Discrete GPU SKU part
3 Touch screen EXO@ EXO GPU Part

SMBUS Control Table 4 Blue Tooth TOPAZ@ TOPAZ GPU Part


5 Camera TPM@ TPM part

SOURCE GPU BATT IT8586E SODIMM WLAN Thermal APU Charger HDMI
xHCI 2 6 LEFT USB (3.0) AOAC@ AOAC support part
Sensor Convert 3 7 LEFT USB (3.0) HDT@ HDT Debug part
reserve TS@ Touch screen part
EC_SMB_CK1 CZ@ Carrizo Part
IT8586E
EC_SMB_DA1 X V X X X X V X CZL@ CarrizoL part
+3VALW
CZPX@ Carrizo Discrete Part
3
EC_SMB_CK2 V CZLPX@ CarrizoL Discrete Part 3

IT8586E V X X X V APU_SIC
APU_SID X V
EC_SMB_DA2
+3VS +3VS_VGA 1.8VS for CZ
3VS for CZL
PCIE PORT LIST S4GX4@ X76 SAMSUNG 2G
M4GX4@ X76 MICRON 2G
APU_SCLK0 APU H4GX4@ X76 HYNIX 2G
Port Device
APU_SDATA0
+3VS X X X V V X X X S2GX4@ X76 SAMSUNG 1G
0 N/A
M2GX4@ X76 MICRON 1G
GPP
1 WLAN
H2GX4@ X76 HYNIX 1G
2 LAN
S2G@ SAMSUNG 2G
3 N/A MICRON 2G
M2G@
EC SM Bus1 address EC SM Bus2 address 0 H2G@ HYNIX 2G
1 VRAM
GFX CZL S1G@ SAMSUNG 1G
Device Address Device Address 2 GPU M1G@ MICRON 1G
Battery 0X16 Thermal Sensor 1001_100xb(reserve) 3 CZ
H1G@ HYNIX 1G
Charger 0001 0010 b GPU 0x41(default)
4 GPU
CZLUMA@ CarrizoL UMA Part
releate to F3x1E4[SbiAddr] or Address Select Pins setting
APU SB-TSI 5
N/A CZUMA@ Carrizo UMA Part
HDMI Convert RSVD 6
4
APU SM Bus address 7
SIVCD@ SIV COST down material
4

HDMI@ HDMI Logo


Device Address
DDR DIMMA 0xA0h
DDR DIMMB 0xA2h
Security Classification LC Future Center Secret Data Title
WLAN RSVD
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Wednesday, February 24, 2016 Sheet 3 of 50
A B C D E
5 4 3 2 1

D D

UC2B
PCIE

U10 R1
U9 P_GPP_RXP0 P_GPP_TXP0 R2
P_GPP_RXN0 P_GPP_TXN0
PCIE_PRX_DTX_P1 T6 R4 PCIE_PTX_DRX_P1 CC1 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_P1
{31} PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 P_GPP_RXP1 P_GPP_TXP1 PCIE_PTX_DRX_N1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 {31}
T5 R3 CC2 1 2 0.1U_0201_6.3V6-K
WLAN {31} PCIE_PRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1 PCIE_PTX_C_DRX_N1 {31} WLAN
PCIE_PRX_DTX_P2 T9 N1 PCIE_PTX_DRX_P2 CC3 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_P2
{28} PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2 P_GPP_RXP2 P_GPP_TXP2 PCIE_PTX_DRX_N2 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 {28}
T8 N2 CC4 1 2 0.1U_0201_6.3V6-K
LAN {28} PCIE_PRX_DTX_N2 P_GPP_RXN2 P_GPP_TXN2 PCIE_PTX_C_DRX_N2 {28} LAN
P7 N4
+0.95VS P6 P_GPP_RXP3 P_GPP_TXP3 N3 +0.95VS
P_GPP_RXN3 P_GPP_TXN3
C RC1 1 CZL@ 2 1.69K_0402_1% P_TX_ZVDD U7 U6 P_RX_ZVDD 1K_0402_1% 1 2 CZL@ RC2 C
P_ZVDDP P_ZVSS/P_RX_ZVDDP
with BOM strcture control, RC1 change to 196_0402_1% for Stoney and Carrizo 196_0402_1% 1 2 STN@ RC3

PCIE_CRX_GTX_P0 P10 M2 PCIE_CTX_GRX_P0 CC5 CZLPX@1 2 0.1U_0201_6.3V6-K PCIE_CTX_C_GRX_P0


{15} PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 P_GFX_RXP0 P_GFX_TXP0 PCIE_CTX_GRX_N0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P0 {15}
P9 M1 CC6 CZLPX@1 2 0.1U_0201_6.3V6-K
{15} PCIE_CRX_GTX_N0 P_GFX_RXN0 P_GFX_TXN0 PCIE_CTX_C_GRX_N0 {15}
PCIE_CRX_GTX_P1 N6 L1 PCIE_CTX_GRX_P1 CC7 CZLPX@1 2 0.1U_0201_6.3V6-K PCIE_CTX_C_GRX_P1
{15} PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 P_GFX_RXP1 P_GFX_TXP1 PCIE_CTX_GRX_N1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P1 {15}
N5 L2 CC8 CZLPX@1 2 0.1U_0201_6.3V6-K
GPU {15} PCIE_CRX_GTX_N1 P_GFX_RXN1 P_GFX_TXN1 PCIE_CTX_C_GRX_N1 {15} GPU
PCIE_CRX_GTX_P2 N9 L4 PCIE_CTX_GRX_P2 CC9 CZLPX@1 2 0.1U_0201_6.3V6-K PCIE_CTX_C_GRX_P2
{15} PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 P_GFX_RXP2 P_GFX_TXP2 PCIE_CTX_GRX_N2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P2 {15}
N8 L3 CC10 CZLPX@1 2 0.1U_0201_6.3V6-K
{15} PCIE_CRX_GTX_N2 P_GFX_RXN2 P_GFX_TXN2 PCIE_CTX_C_GRX_N2 {15}
PCIE_CRX_GTX_P3 L7 J1 PCIE_CTX_GRX_P3 CC11 CZLPX@1 2 0.1U_0201_6.3V6-K PCIE_CTX_C_GRX_P3
{15} PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 P_GFX_RXP3 P_GFX_TXP3 PCIE_CTX_GRX_N3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P3 {15}
L6 J2 CC12 CZLPX@1 2 0.1U_0201_6.3V6-K
{15} PCIE_CRX_GTX_N3 P_GFX_RXN3 P_GFX_TXN3 PCIE_CTX_C_GRX_N3 {15}
L10 J4
L9 P_GFX_RXP4 P_GFX_TXP4 J3
P_GFX_RXN4 P_GFX_TXN4
with BOM strcture control, CC5--CC12 change to 0.22uf for STN
K6 H2
K5 P_GFX_RXP5 P_GFX_TXP5 H1
P_GFX_RXN5 P_GFX_TXN5
K9 G1
CarrizoL not support GFX4-GFX7 K8 P_GFX_RXP6 P_GFX_TXP6 G2
P_GFX_RXN6 P_GFX_TXN6
J7 G4
J6 P_GFX_RXP7 P_GFX_TXP7 G3
P_GFX_RXN7 P_GFX_TXN7

B B
FP4 REV 0.93
@ AMD-CARRIZO_FP4-BGA968

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (PCIE I/F)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Wednesday, February 24, 2016 Sheet 4 of 50
5 4 3 2 1
5 4 3 2 1

DDRB_DQS[0..7]
{12} DDRB_DQS[0..7]
DDRB_DQS#[0..7]
CarrizoL not support ChannelA {12} DDRB_DQS#[0..7]

UC2A UC2I
MEMORY A MEMORY B
{12} DDRB_MA[15..0] DDRB_MA0 DDRB_DQ0 DDRB_DQ[63..0] {12}
AE28 H17 AG31 A25
Y27 MA_ADD0 MA_DATA0 J17 DDRB_MA1 AC30 MB_ADD0 MB_DATA0 C25 DDRB_DQ1
Y29 MA_ADD1 MA_DATA1 F20 DDRB_MA2 AC31 MB_ADD1 MB_DATA1 C27 DDRB_DQ2
Y26 MA_ADD2 MA_DATA2 H20 DDRB_MA3 AB32 MB_ADD2 MB_DATA2 D27 DDRB_DQ3
W28 MA_ADD3 MA_DATA3 E17 DDRB_MA4 AA32 MB_ADD3 MB_DATA3 B24 DDRB_DQ4
D D
W29 MA_ADD4 MA_DATA4 F17 DDRB_MA5 AA33 MB_ADD4 MB_DATA4 B25 DDRB_DQ5
W26 MA_ADD5 MA_DATA5 K18 DDRB_MA6 AA31 MB_ADD5 MB_DATA5 B27 DDRB_DQ6
U29 MA_ADD6 MA_DATA6 E20 DDRB_MA7 Y33 MB_ADD6 MB_DATA6 A27 DDRB_DQ7
W25 MA_ADD7 MA_DATA7 DDRB_MA8 AA30 MB_ADD7 MB_DATA7
U26 MA_ADD8 A21 DDRB_MA9 W32 MB_ADD8 A29 DDRB_DQ8
AG29 MA_ADD9 MA_DATA8 C21 DDRB_MA10 AG32 MB_ADD9 MB_DATA8 C29 DDRB_DQ9
U27 MA_ADD10 MA_DATA9 C23 DDRB_MA11 Y32 MB_ADD10 MB_DATA9 B32 DDRB_DQ10
T28 MA_ADD11 MA_DATA10 D23 DDRB_MA12 W33 MB_ADD11 MB_DATA10 D32 DDRB_DQ11
AK26 MA_ADD12 MA_DATA11 B20 DDRB_MA13 AL31 MB_ADD12 MB_DATA11 B28 DDRB_DQ12
T26 MA_ADD13 MA_DATA12 B21 DDRB_MA14 W30 MB_ADD13 MB_DATA12 B29 DDRB_DQ13
T25 MA_ADD14/MA_BG1 MA_DATA13 B23 DDRB_MA15 V32 MB_ADD14/MB_BG1 MB_DATA13 A31 DDRB_DQ14
MA_ADD15/MA_ACT_L MA_DATA14 A23 MB_ADD15/MB_ACT_L MB_DATA14 C31 DDRB_DQ15
MA_DATA15 MB_DATA15
G22 E30 DDRB_DQ16
AG26 MA_DATA16 H22 DDRB_BS0# AH32 MB_DATA16 E31 DDRB_DQ17
MA_BANK0 MA_DATA17 {12} DDRB_BS0# DDRB_BS1# MB_BANK0 MB_DATA17 DDRB_DQ22
AG27 E25 AG33 G33
MA_BANK1 MA_DATA18 {12} DDRB_BS1# DDRB_BS2# MB_BANK1 MB_DATA18 DDRB_DQ23
T29 G25 W31 G32
MA_BANK2/MA_BG0 MA_DATA19 J20
{12} DDRB_BS2# MB_BANK2/MB_BG0 MB_DATA19 C33 DDRB_DQ20 DATA16--DATA23 Byte internal swap
MA_DATA20 {12} DDRB_DM[7..0] DDRB_DM0 MB_DATA20 DDRB_DQ21
E19 E22 D25 D33
D21 MA_DM0 MA_DATA21 H23 DDRB_DM1 D29 MB_DM0 MB_DATA21 G30 DDRB_DQ19
K21 MA_DM1 MA_DATA22 J23 DDRB_DM2 E33 MB_DM1 MB_DATA22 G31 DDRB_DQ18
F29 MA_DM2 MA_DATA23 DDRB_DM3 J33 MB_DM2 MB_DATA23
AP28 MA_DM3 F26 DDRB_DM4 AR30 MB_DM3 J30 DDRB_DQ24
AV26 MA_DM4 MA_DATA24 E27 DDRB_DM5 AW30 MB_DM4 MB_DATA24 J31 DDRB_DQ25
AR22 MA_DM5 MA_DATA25 J26 DDRB_DM6 BC30 MB_DM5 MB_DATA25 L33 DDRB_DQ26
BC22 MA_DM6 MA_DATA26 J27 DDRB_DM7 BC26 MB_DM6 MB_DATA26 L32 DDRB_DQ27
K29 MA_DM7 MA_DATA27 H25 @ TC20 1 DDRB_DM8 N33 MB_DM7 MB_DATA27 H32 DDRB_DQ29
MA_DM8 MA_DATA28 E26 MB_DM8 MB_DATA28 H33 DDRB_DQ28 DATA24--DATA31 Byte internal swap
H19 MA_DATA29 G28 DDRB_DQS0 B26 MB_DATA29 L30 DDRB_DQ30
G19 MA_DQS_H0 MA_DATA30 G29 DDRB_DQS#0 A26 MB_DQS_H0 MB_DATA30 L31 DDRB_DQ31
B22 MA_DQS_L0 MA_DATA31 DDRB_DQS1 B30 MB_DQS_L0 MB_DATA31
A22 MA_DQS_H1 AN26 DDRB_DQS#1 A30 MB_DQS_H1 AN31 DDRB_DQ36
F23 MA_DQS_L1 MA_DATA32 AP29 DDRB_DQS2 F32 MB_DQS_L1 MB_DATA32 AP32 DDRB_DQ32
E23 MA_DQS_H2 MA_DATA33 AR26 DDRB_DQS#2 E32 MB_DQS_H2 MB_DATA33 AT32 DDRB_DQ39
C
G27 MA_DQS_L2 MA_DATA34 AP24 DDRB_DQS3 K32 MB_DQS_L2 MB_DATA34 AU32 DDRB_DQ35 C
F27 MA_DQS_H3 MA_DATA35 AN29 DDRB_DQS#3 J32 MB_DQS_H3 MB_DATA35 AN33 DDRB_DQ33 DATA32--DATA39 Byte internal swap
AP25 MA_DQS_L3 MA_DATA36 AN27 DDRB_DQS4 AR32 MB_DQS_L3 MB_DATA36 AN32 DDRB_DQ37
AP26 MA_DQS_H4 MA_DATA37 AR29 DDRB_DQS#4 AR33 MB_DQS_H4 MB_DATA37 AR31 DDRB_DQ34
AW27 MA_DQS_L4 MA_DATA38 AR27 DDRB_DQS5 AW32 MB_DQS_L4 MB_DATA38 AT33 DDRB_DQ38
AV27 MA_DQS_H5 MA_DATA39 DDRB_DQS#5 AW33 MB_DQS_H5 MB_DATA39
AV22 MA_DQS_L5 AU26 DDRB_DQS6 BA29 MB_DQS_L5 AU30 DDRB_DQ41
AU22 MA_DQS_H6 MA_DATA40 AV29 DDRB_DQS#6 AY29 MB_DQS_H6 MB_DATA40 AV32 DDRB_DQ44
BA21 MA_DQS_L6 MA_DATA41 AU25 DDRB_DQS7 BA25 MB_DQS_L6 MB_DATA41 BA33 DDRB_DQ43
AY21 MA_DQS_H7 MA_DATA42 AW25 DDRB_DQS#7 AY25 MB_DQS_H7 MB_DATA42 AY32 DDRB_DQ47
L27 MA_DQS_L7 MA_DATA43 AU29 @ TC8 1 DDRB_DQS8 P32 MB_DQS_L7 MB_DATA43 AU33 DDRB_DQ45 DATA40--DATA47 Byte internal swap
L26 MA_DQS_H8 MA_DATA44 AU28 @ TC9 1 DDRB_DQS#8 N32 MB_DQS_H8 MB_DATA44 AU31 DDRB_DQ40
MA_DQS_L8 MA_DATA45 AW26 MB_DQS_L8 MB_DATA45 AW31 DDRB_DQ46
AE25 MA_DATA46 AT25 DDRB_CLK0 AE33 MB_DATA46 AY33 DDRB_DQ42
MA_CLK_H0 MA_DATA47 {12} DDRB_CLK0 DDRB_CLK0# MB_CLK_H0 MB_DATA47
AE26 AE32
MA_CLK_L0 {12} DDRB_CLK0# DDRB_CLK1 MB_CLK_L0 DDRB_DQ54
AD26 AV23 AE30 BC31
MA_CLK_H1 MA_DATA48 {12} DDRB_CLK1 DDRB_CLK1# MB_CLK_H1 MB_DATA48 DDRB_DQ53
AD27 AW23 AE31 BB30
MA_CLK_L1 MA_DATA49 {12} DDRB_CLK1# MB_CLK_L1 MB_DATA49 DDRB_DQ50
AB28 AV20 AD32 BB28
AB29 MA_CLK_H2 MA_DATA50 AW20 AD33 MB_CLK_H2 MB_DATA50 AY27 DDRB_DQ52
AB25 MA_CLK_L2 MA_DATA51 AR23 AC33 MB_CLK_L2 MB_DATA51 BB32 DDRB_DQ49 DATA48--DATA55 Byte internal swap
AB26 MA_CLK_H3 MA_DATA52 AT23 AC32 MB_CLK_H3 MB_DATA52 BA31 DDRB_DQ48
MA_CLK_L3 MA_DATA53 AR20 MB_CLK_L3 MB_DATA53 BC29 DDRB_DQ51
N29 MA_DATA54 AT20 RC240 1 2 10_0402_5% MEM_MB_RST#_R T33 MB_DATA54 BB29 DDRB_DQ55
MA_RESET_L MA_DATA55 {12} MEM_MB_RST# MEM_MB_EVENT#AG30 MB_RESET_L MB_DATA55
AE29
MA_EVENT_L {12} MEM_MB_EVENT# MB_EVENT_L DDRB_DQ60
BB23 BB27
P27 MA_DATA56 BB22 DDRB_CKE0 U32 MB_DATA56 BB26 DDRB_DQ57
MA_CKE0 MA_DATA57 {12} DDRB_CKE0 DDRB_CKE1 MB_CKE0 MB_DATA57 DDRB_DQ58
P29 BB20 U33 BB24
MA_CKE1 MA_DATA58 AY19
{12} DDRB_CKE1 MB_CKE1 MB_DATA58 AY23 DDRB_DQ59 DATA56--DATA63 Byte internal swap
MA_DATA59 BA23 MB_DATA59 BA27 DDRB_DQ61
MA_DATA60 BC23 MB_DATA60 BC27 DDRB_DQ56
AK27 MA_DATA61 BC21 DDRB_ODT0 AL30 MB_DATA61 BC25 DDRB_DQ63
MA0_ODT0 MA_DATA62 {12} DDRB_ODT0 DDRB_ODT1 MB0_ODT0 MB_DATA62 DDRB_DQ62
AL26 BB21 AM32 BB25
MA0_ODT1 MA_DATA63 {12} DDRB_ODT1 MB0_ODT1 MB_DATA63
AH25 AJ32
AL25 MA1_ODT0 K26 AM33 MB1_ODT0 N30
MA1_ODT1 MA_CHECK0 K28 MB1_ODT1 MB_CHECK0 N31
B B
AH26 MA_CHECK1 N26 DDRB_CS0# AJ33 MB_CHECK1 R33
MA0_CS_L0 MA_CHECK2 {12} DDRB_CS0# DDRB_CS1# MB0_CS_L0 MB_CHECK2
AL29 N28 AL32 R32
MA0_CS_L1 MA_CHECK3 {12} DDRB_CS1# MB0_CS_L1 MB_CHECK3
AH29 J29 AJ30 M32
AL28 MA1_CS_L0 MA_CHECK4 K25 AL33 MB1_CS_L0 MB_CHECK4 M33
MA1_CS_L1 MA_CHECK5 L29 MB1_CS_L1 MB_CHECK5 R30
MA_CHECK6 N25 MB_CHECK6 R31
AG24 MA_CHECK7 DDRB_RAS# AH33 MB_CHECK7
MA_RAS_L/MA_RAS_L_ADD16 {12} DDRB_RAS# DDRB_CAS# MB_RAS_L/MB_RAS_L_ADD16
AK29 AK32 +1.35V
MA_CAS_L/MA_CAS_L_ADD15 {12} DDRB_CAS# DDRB_WE# MB_CAS_L/MB_CAS_L_ADD15
AH28 AJ31
MA_WE_L/MA_WE_L_ADD14 {12} DDRB_WE# MB_WE_L/MB_WE_L_ADD14

B19 AD29 APU_M_VREFDQ A19 AF32 MB_ZVDDIO RC10 1 2 39.2_0402_1%


+MEM_VREF MA_VREFDQ MA_ZVDDIO_MEM_S {12} APU_M_VREFDQ MB_VREFDQ MB_ZVDDIO_MEM_S
T32
M_VREF
FP4 REV 0.93 FP4 REV 0.93

@ AMD-CARRIZO_FP4-BGA968 @ AMD-CARRIZO_FP4-BGA968

+1.35V

+1.35V
1

RC4
1K_0402_1% RC9 1 2 1K_0402_5% MEM_MB_EVENT#
2

+MEM_VREF

@
.47U_0402_6.3V6K
1

CC14 0.1U_0201_6.3V6-K

1 1 1
RC5 CC15
A A
1K_0402_1% 1000P_0201_50V7-K
2 2 2
2

CC13

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (MEM)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Wednesday, February 24, 2016 Sheet 5 of 50
5 4 3 2 1
5 4 3 2 1

+3VS_APU
UC2C For Carrizo RPC18
APU_DDC_CLK 1 4
DisplayPort Auxiliary Channel pins are dual-mode pins and are 3.3V tolerant. APU_DDC_DATA 2 3
DISPLAY/SVI2/JTAG/TEST In I2C mode AUXP pins change to SCL, and AUXN pins change to SDA.
During this operation the pin type is B-IO33-OD. FDS 2.2K_0404_4P2R_5%
B6 A9 DP_2K_ZVSS RC55 1 2 2K_0402_1%
A6 DP2_TXP0 DP_ZVSS B9 DP_150_ZVSS RC12 1 2 150_0402_1%
+1.8VS DP2_TXN0 DP_AUX_ZVSS G5 DP_ENBKL APU_EDP_HPD RC35 1 2 100K_0402_5%
D7 DP_BLON G6 DP_ENVDD
DP2_TXP1 DP_DIGON For STN,
C7 F11 DP_EDP_PWM
DP2_TXN1 DP_VARY_BL Hot Plug Detect pins is I-IO18-S,but 3.3V tolerant.
1

RC18
CarrizoL not support DP2 A7 +1.8VS
DP2_TXP2 RPC11
300_0402_5% B7 H9 STN@
D DP2_TXN2 DP2_AUXP D
G9 APU_PROCHOT#_R 3 2
D9 DP2_AUXN E9 ALERT# 4 1
2

APU_RST# C9 DP2_TXP3 DP2_HPD


DP2_TXN3 F7 APU_DDC_CLK 1K_0404_4P2R_5%
PLACE CC16 CAPS CLOSE TO APU,CRB reserve 27pf APU_HDMI_TX2+ A2 DP1_AUXP E7 APU_DDC_DATA APU_DDC_CLK {25} HDMI Convert Carrizo
{25} APU_HDMI_TX2+ APU_HDMI_TX2- DP1_TXP0 DP1_AUXN APU_HDMI_HPD APU_DDC_DATA {25}
1 A3 F5
{25} APU_HDMI_TX2- DP1_TXN0 DP1_HPD APU_HDMI_HPD {25}
CC16
150P_0402_50V8-J APU_HDMI_TX1+ B4 F8 APU_EDP_AUX +3VS_APU
{25} APU_HDMI_TX1+ APU_HDMI_TX1- DP1_TXP1 DP0_AUXP APU_EDP_AUX# APU_EDP_AUX {23} RPC12
@ A4 E8 CZL@
2 {25} APU_HDMI_TX1- DP1_TXN1 DP0_AUXN G8 APU_EDP_HPD APU_EDP_AUX# {23} eDP APU_PROCHOT#_R 3 2
CarrizoL:HDMI APU_HDMI_TX0+ D5 DP0_HPD APU_EDP_HPD {23} +3VALW_APU ALERT# 4 1
{25} APU_HDMI_TX0+ APU_HDMI_TX0- DP1_TXP2 Core_type
C5 K24 RC239 1 @ 2 100K_0402_5%
{25} APU_HDMI_TX0- DP1_TXN2 RSVD_1 E15 1K_0404_4P2R_5%
APU_HDMI_CLK+ A5 TEMPIN0 E14
+1.8VS {25} APU_HDMI_CLK+ APU_HDMI_CLK- DP1_TXP3 TEMPIN1
B5 E12
{25} APU_HDMI_CLK- DP1_TXN3 TEMPIN2 F14
TEMPINRETURN
{23} APU_EDP_TX0+
APU_EDP_TX0+ E2
DP0_TXP0 TEST410
AK24 TEST410 1 @ TC16 To EDP panel
1

APU_EDP_TX0- E1 AL24 TEST411 1 @ TC17


{23} APU_EDP_TX0- DP0_TXN0 TEST411
RC19 P24 TEST4 1 @ TC13
300_0402_5% APU_EDP_TX1+ E3 TEST4 N24 TEST5 1 @ TC14 +3VS_APU
eDP {23} APU_EDP_TX1+ APU_EDP_TX1- E4 DP0_TXP1 TEST5 AN24
{23} APU_EDP_TX1- DP0_TXN1 TEST6 AB8
2

TEST9

1
D1 Y9
APU_PWROK D2 DP0_TXP2 TEST10 B10 APU_TEST14_BP0 RC21 1 @ 2 1K_0402_5% +3VALW_APU RC70
DP0_TXN2 TEST14 D11 APU_TEST15_BP1 1 @ TC18 4.7K_0402_5%
C1 TEST15 A10 APU_TEST16_BP2 RC23 1 @ 2 1K_0402_5%
PLACE CC17 CAPS CLOSE TO APU,CRB reserve 27pf DP0_TXP3 TEST16

2
1 B1 C11 APU_TEST17_BP3 RC24 1 @ 2 1K_0402_5%

2
CC17 DP0_TXN3 TEST17 B11 APU_TEST11_BP4 RC1891 @ 2 1K_0402_5% RC71
150P_0402_50V8-J APU_SVT_R TEST11 APU_TEST18_PLLTEST1 STN@
RC249 1 2 0_0402_5% C15 A14 4 1 10K_0402_5%
{49} APU_SVT APU_SVC_R SVT0 TEST18 APU_TEST19_PLLTEST0 PCH_EDP_PWM {23}
@ RC213 1 2 0_0402_5% D17 B14 3 2
2 {49} APU_SVC APU_SVD_R SVC0 TEST19
RC215 1 2 0_0402_5% D19 1K_0404_4P2R_5%
{49} APU_SVD

1
SVD0 RPC14 +3VS_APU +1.8VS
STN@

3
APU_SVT_R B15 A13 APU_TEST28_H_PLLCHARZ 1 @ TC21 D
C B16 SVT1 TEST28_H B13 APU_TEST28_L_PLLCHARZ 1 @ TC23 RC34 1 CZL@ 2 1K_0402_5% 5 QC8B C
SVC1 TEST28_L
1

CC210 A18 P26 APU_TEST31_MEM_TEST 1 @ TC25 RC28 1 STN@2 1K_0402_5% G DMN5L06DWK-7 2N SOT363-6
1000P_0402_25V7-K SVD1 TEST31 E11 APU_TEST36_STEREOSYNC RC27 1 @ 2 1K_0402_5%
@ APU_SIC B18 DP_STEREOSYNC/TEST36 A17 APU_TEST37 RC29 1 @ 2 1K_0402_5% S
2

4
SIC TEST37

6
APU_SID C17 RC30 1 @ 2 1K_0402_5% D
SID DP_EDP_PWM STN@
2 QC8A
+1.8VS +1.8VS APU_RST# D15 G
RESET_L DMN5L06DWK-7 2N SOT363-6
APU_PWROK C19
{49} APU_PWROK PWROK

1
S

1
RC31 1 @ 2 0_0402_5% APU_PROCHOT#_R A15 RC11
{35} H_PROCHOT# PROCHOT_L STN@
ALERT# B17 100K_0402_5%
ALERT_L
4
3

H11
RPC10 APU_TDI H15 VDDCR_GFX_SENSE J12 APU_VDDNB_SEN_H
APU_VDDNB_SEN_H {49}

2
TDI VDDCR_NB_SENSE
5

APU_TDO H14 G12 APU_VDDCORE_SEN_H RC2051 CZL@ 2 0_0402_5%


G

1K_0404_4P2R_5% TDO VDDCR_CPU_SENSE APU_VDDCORE_SEN_H {49} STN@


STN@ APU_TCK D13 AY18 VDD_095_FB_H 1
APU_TMS G15 TCK VDDP_SENSE TC26 @
1
2

APU_TRST# J14 TMS H12 APU_VSS_SEN_L RC2361 @ 2 0_0402_5%


APU_SIC EC_SMB_CK2 APU_DBRDY TRST_L VSS_SENSE APU_VDD_SEN_L {49}
4 3 C13
S

DBRDY
D

APU_DBREQ# A11
STN@ DBREQ_L
QC6B
2

DP_ENVDD RC2061 @ 2 0_0402_5%


G

DMN5L06DWK-7 2N SOT363-6 PCH_ENVDD {23}


FP4 REV 0.93
@ AMD-CARRIZO_FP4-BGA968
APU_SID 1 6 EC_SMB_DA2
S

STN@ +3VS_APU
QC6A
DMN5L06DWK-7 2N SOT363-6 APU_VDDNB_SEN_H 1 @ TC27

1
APU_VDDCORE_SEN_H 1 @ TC28 +3VALW_APU RC245
RPC7 CZL@ 4.7K_0402_5%
APU_SIC 1 4 EC_SMB_CK2 APU_VDD_SEN_L 1 @ TC29
EC_SMB_CK2 {16,30,35}

2
B APU_SID 2 3 EC_SMB_DA2 B
EC_SMB_DA2 {16,30,35}

2
RC244
STN@
0_0404_4P2R_5% 10K_0402_5%
PCH_ENBKL {23}

1
STN@

3
D
5 QC9B
With HDT+ Header LCD Power IC can change for PCH_ENVDD for CZ cost down G DMN5L06DWK-7 2N SOT363-6
+1.8VS +1.8VS
S

4
6
+1.8VS JHDT1 @ RPC5 D
APU_TCK +1.8VS +1.8VS DP_ENBKL STN@
1 2 8 1 2 QC9A
1 2 7 2 G DMN5L06DWK-7 2N SOT363-6
3 4 APU_TMS 6 3
3 4
2

1
5 4 1 S

1
1

1
RC7 5 6 APU_TDI RC246
5 6 STN@
1K_0402_5% 1K_0804_8P4R_5% CC25 RC32 RC36 100K_0402_5%
7 8 APU_TDO 0.1U_0201_6.3V6-K 300_0402_5% 300_0402_5%
7 8 2
HDT@
1

2
APU_TRST# RC76 1 HDT@ 2 33_0402_5% APU_TRST#_R 9 10 APU_PWROK_BUF RC2071 CZL@ 2 0_0402_5%
STN@

2
9 10 UC6
2 11 12 APU_RST#_BUF APU_PWROK 3 4 APU_PWROK_BUF
11 12 2A 2Y
CC84 13 14 APU_DBRDY 2 5
13 14 GND VCC
0.01U_0201_6.3V7-K
1 15 16 APU_DBREQ# APU_RST# 1 6 APU_RST#_BUF
15 16 1A 1Y
8
7
6
5

17 18 APU_TEST19_PLLTEST0 HDT@ SN74LVC2G07YZPR_WCSP6


RPC17 17 18
10K_0804_8P4R_5% 19 20 APU_TEST18_PLLTEST1
19 20
HDT@
1
2
3
4

A A
SAMTE_ASP-136446-07-B

PCH_ENBKL can to con EC ADC pin for CZ cost down because 1.8V level

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (DISPLAY/CLK/MISC)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Wednesday, February 24, 2016 Sheet 6 of 50
5 4 3 2 1
5 4 3 2 1

RC46 1 2 33_0402_5% LPC_RST#_R +3VALW_APU


{30,35} APU_LPC_RST#
1
CC20
150P_0402_50V8-J

2
2 RC39 RC40 RC41
10K_0402_5% 10K_0402_5% 10K_0402_5%
15@ UMA@ @

1
RC38 1 2 33_0402_5% PCIE_RST#_R BOARD_ID0
{15,28,31} PLT_RST# BOARD_ID1
BOARD_ID2

1
1
RC43 CC19

2
D @ 100K_0402_5% 150P_0402_50V8-J D
RC47 RC48 RC49
2
2 2K_0402_5% 2K_0402_5% 2K_0402_5%
17@ PX@ @

1
+1.8VALW

1
Connected to 10-ms RC-delay circuit on VDD_18_S5 power rail.
RC2472 1 RC53
0_0402_5% 10K_0402_5%
(CRB PWR Dealy: 22K/0.1uF) UC2D
ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC
DC1 LPC_RST#_R BB12 BB2 @1 TC61

2
1 2 @ RSMRST#_R PCIE_RST#_R AN7 LPC_RST_L SD0_WP/EGPIO101 BB5 SD_PWR_CNTL @1
{35} EC_RSMRST# PCIE_RST_L/EGPIO26 SD0_PWR_CTRL/AGPIO102 TC44
BC2 ODD_DETECT# @1 TC75
SD0_CD/AGPIO25
LRB751V-40T1G_SOD323-2 1 Type1 2 3 all 1.8V RSMRST#_R AE4
RSMRST_L SD0_CLK/EGPIO95
BB4 @1
TC45
1

AY5 @1
PBTN_OUT# RC191 PWRBTN#_R SD0_CMD/EGPIO96 TC59
RC66 CC21 1 2 0_0402_5% AE1
{35} PBTN_OUT# SYS_PWRGD_R PWR_BTN_L/AGPIO0
@ 100K_0402_5% 0.1U_0201_6.3V6-K @ BC9
2 SYS_RESET# AF2 PWR_GOOD
{11} SYS_RESET# PCIE_WAKE#_RA SYS_RESET_L/AGPIO1 SD_DATA0_R
AG2 BC3 @1 TC62
2

WAKE_L/AGPIO2 SD0_DATA0/EGPIO97 BA3 SD_DATA1_R @1 TC63


PM_SLP_S3# RC193 1 2 0_0402_5% PM_SLP_S3#_R AK7 SD0_DATA1/EGPIO98 BC5 SD_DATA2_R @1 TC64
{35} PM_SLP_S3# PM_SLP_S5# RC194 PM_SLP_S5#_R SLP_S3_L SD0_DATA2/EGPIO99 SD_DATA3_R
1 @ 2 0_0402_5% AH5 BA5 @1 TC65
{35} PM_SLP_S5# SLP_S5_L SD0_DATA3/EGPIO100 SD_LED
@ BB6
AGPIO10 AE8 SD0_LED/EGPIO93
APU_S5_MUX_CTRL AH8 S0A3_GPIO/AGPIO10 BA15 APU_SMB_CLK
{9} APU_S5_MUX_CTRL S5_MUX_CTRL/EGPIO42 SCL0/I2C2_SCL/EGPIO113 APU_SMB_CLK {12,31}
TEST0 AH6 SDA0/I2C2_SDA/EGPIO114
AY17 APU_SMB_DATA
RPC2
APU_SMB_DATA {12,31} DIMM1, DIMM2, Mini CARD,HDMI Convert
TEST0
with QC16,QC17, EC must set EC_RSMRST# and EC_SYS_PWRGD reversed compare to DC1 and DC2 TEST1 AK8
TEST1/TMS SCL1/I2C3_SCL/AGPIO19
AG5 SCL1 1 4
TEST2 AE3 AG4 SDA1 2 3
+1.8VS TEST2 SDA1/I2C3_SDA/AGPIO20 CZL@
C KBRST# AY15 10K_0404_4P2R_5% C
{35} KBRST# ESPI_RESET_L/KBRST_L/AGPIO129
BC19
{35} GATEA20 GA20IN/AGPIO126
1

AD7 AL5
{35} EC_SCI# ODD_DA# LPC_PME_L/AGPIO22 AGPIO3 AGPIO3 {11}
RC72 BB13 AL6 AGPIO4
LPC_SMI_L/AGPIO86 AGPIO4
RC95 2 1 0_0402_5% 10K_0402_5% Delete Zero ODD circuit ODD_DA# 10/20 AGPIO5
AJ1 AGPIO5
@ CZL@ AC_PRESENT AG3 AJ3 LDT_RST_L @1 TC67 +3VS_APU
{35} AC_PRESENT AC_PRES/USB_OC4_L/IR_RX0/AGPIO23 AGPIO6/LDT_RST_L
Type2 1.8V, Type1 3 3.3V BOARD_ID0 AD5 AH1 LDT_PWROK @1 TC68
2

BOARD_ID1 AL8 IR_TX0/USB_OC5_L/AGPIO13 AGPIO7/LDT_PWROK AJ4 AGPIO8 RPC9


DC2
IR_TX1/USB_OC6_L/AGPIO14 AGPIO8
{35} EC_SYS_PWRGD
1 2 @ SYS_PWRGD_R Delete Zero ODD circuit ODD_EN 10/20 AN8
IR_RX1/AGPIO15 AGPIO9
AK5 APU_SMB_CLK 3 2
1 ODD_EN AE2 AD8 APU_SMB_DATA 4 1
IR_LED_L/LLB_L/AGPIO12 VDDGFX_PD/AGPIO39
1

PCH_WLAN_OFF# BC15 AG8 AGPIO40


LRB751V-40T1G_SOD323-2 {31} PCH_WLAN_OFF# WLAN_CLKREQ# CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 AGPIO40
RC82 CC22 BB17 AW15 AGPIO64 2.2K_0404_4P2R_5%
{31} WLAN_CLKREQ# LAN_CLKREQ# CLK_REQ1_L/AGPIO115 AGPIO64
@ 100K_0402_5% 0.1U_0201_6.3V6-K BC17 AU15 RPC6
2 {28} LAN_CLKREQ# PCH_BT_OFF# CLK_REQ2_L/AGPIO116 AGPIO65
BB18 KBRST# 8 1
{31} PCH_BT_OFF# GPU_CLKREQ# CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 APU_SHUTDOWN#
BB16 AT15 7 2
{16} GPU_CLKREQ# APU_SHUTDOWN# {16}
2

BOARD_ID2 AH9 CLK_REQG_L/OSCIN/EGPIO132 AGPIO66/SHUTDOWN_L AU12 PCH_BT_OFF# 6 3


USB_OC1# AG1 USB_OC0_L/TRST_L/AGPIO16 AGPIO68/SGPIO_CLK AT14 AGPIO69 RC116 1 CZLPX@2 0_0402_5% PCH_WLAN_OFF# 5 4
{32} USB_OC1# USB_OC2# USB_OC1_L/TDI/AGPIO17 AGPIO69/SGPIO_LOAD PXS_RST# {8,15}
AH2 AR14
AL9 USB_OC2_L/TCK/AGPIO18 AGPIO71/SGPIO_DATAOUT BC13 10K_0804_8P4R_5%
USB_OC3_L/TDO/AGPIO24 AGPIO72/SGPIO_DATAIN RPC21
HDA_BITCLK AU6 BA17 ODD_DA# 1 4 @
AZ_BITCLK/I2S_BCLK_MIC SPKR/AGPIO91 PCH_BEEP {34}
RC201 2 1 0_0402_5% HDA_SDIN0_R AR8 ODD_DETECT# 2 3
{34} HDA_SDIN0 HDA_SDIN1 AZ_SDIN0/I2S_DATA_MIC0
@ AP6 AN5
HDA_SDIN2 AZ_SDIN1/I2S_LR_PLAYBACK BLINK/USB_OC7_L/AGPIO11 BLINK {11}
AR5 10K_0404_4P2R_5%
HDA_RST# AU9 AZ_SDIN2/I2S_DATA_MIC1 BB14 HVB_EN
HDA_SYNC AZ_RST_L/I2S_LR_MIC GENINT1_L/AGPIO89 VR_VGA_PWRGD HVB_EN {11,35} LAN_CLKREQ#
AT9 BA19 RC67 1 2 10K_0402_5%
HDA_SDOUT AZ_SYNC/I2S_BCLK_PLAYBACK GENINT2_L/AGPIO90 VR_VGA_PWRGD {15,48} WLAN_CLKREQ#
RPC3 STN@ AR7 RC78 1 2 10K_0402_5%
1 8 I2C1SDA AZ_SDOUT/I2S_DATA_PLAYBACK BC18 PXS_PWREN_R RC109 1 PX@ 2 1K_0402_5% GPU_CLKREQ# RC64 1 UMA@2 10K_0402_5%
FANIN0/AGPIO84 PXS_PWREN {19,48} APU_SHUTDOWN#
2 7 I2C1SCL I2C0SCl BB10 BB19 RC96 1 2 10K_0402_5%
PCIE_WAKE#_RA RC88 2 1 0_0402_5% 3 6 I2C0SCl I2C0SDA BB9 I2C0_SCL/EGPIO145 FANOUT0/AGPIO85 CZL@
@ 4 5 I2C0SDA I2C1SCL BB7 I2C0_SDA/EGPIO146 AY9
I2C1SDA BC7 I2C1_SCL/EGPIO147 UART0_CTS_L/EGPIO135 AW8
AGPIO5 2 @ 1 RC92 10K_0804_8P4R_5% I2C1_SDA/EGPIO148 UART0_RXD/EGPIO136 AV5
APU_SHUTDOWN# +3VALW_APU
PCIE_WAKE# {28,31,35}
0_0402_5% AG7 UART0_RTS_L/EGPIO137 AV8 inter pull down for Cz,pull high for Czl
{11,31} SUSCLK RTCCLK UART0_TXD/EGPIO138 AW9
2 1 DC3 UART0_INTR/AGPIO139 RPC15
32K_X1 AT1 AV11 PCIE_WAKE#_RA 1 8
SDM10U45LP-7_DFN1006-2-2 X32K_X1 UART1_CTS_L/BT_I2S_BCLK/EGPIO140 AU7 AC_PRESENT 2 7
B UART1_RXD/BT_I2S_SDI/EGPIO141 B
@ DC4 AT11 AGPIO5 3 6
SYS_RESET# 1 2 @ SYS_PWRGD_R UART1_RTS_L/EGPIO142 AR11 PBTN_OUT# 4 5
+3VALW_APU RC102 32K_X2 AT2 UART1_TXD/BT_I2S_SDO/EGPIO143 AP9
1 2 X32K_X2 UART1_INTR/BT_I2S_LRCLK/AGPIO144 10K_0804_8P4R_5%
LRB751V-40T1G_SOD323-2 FP4 REV 0.93
1 20M_0402_5% RPC16
YC1 @ USB_OC1# 1 4
AMD-CARRIZO_FP4-BGA968
2

CC38 1 2 USB_OC2# 2 3
RC84 RC85 RC20 0.1U_0201_6.3V6-K Max ESR < 65K ohm !!
2 202983-PG14 10K_0404_4P2R_5%
2.2K_0402_5% 1K_0402_5% 2.2K_0402_5%
20P_0402_50V8

20P_0402_50V8

ODD_EN RC141 1 2 10K_0402_5%


@ @ @
PM_SLP_S3# RC203 1 @ 2 2.2K_0402_5%
1 1
change YC1 from SIWARD SJ10000M500 to Micro crystalSJ10000M900, SIWARD as 2nd source
1

PM_SLP_S5#
CC23

CC24

TEST0 RC208 1 @ 2 2.2K_0402_5%


TEST1 AGPIO40 RC145 1 STN@ 2 10K_0402_5%
TEST2 PXS_PWREN AGPIO4 RC94 1 @ 2 10K_0402_5%
2 2 APU_S5_MUX_CTRL RC248 1 2 100K_0402_5%
2

RC195 RC196 RC197 STN@


15K_0402_5% 15K_0402_5% 15K_0402_5%
AGPIO4 RC86 1 CZL@ 2 10K_0402_5%
AGPIO64 RC93 1 CZL@ 2 10K_0402_5%
1

QC15 D RPC4
RC170 1 @ 2 2
{35} VGA_GATE# G HDA_RST#
0_0402_5% 1 8 AGPIO8 RC83 1 STN@ 2 10K_0402_5%
{34} HDA_RST_AUDIO# HDA_SYNC
1 2 7
S {34} HDA_SYNC_AUDIO HDA_BITCLK
L2N7002KWT1G_SOT323-3 3 6
{34} HDA_BITCLK_AUDIO
3

CC96 4 5 HDA_SDOUT
@ {34} HDA_SDOUT_AUDIO SD_LED
0.1U_0201_6.3V6-K RC97 1 CZL@ 2 10K_0402_5%
2 @ 33_0804_8P4R_5%
AGPIO10 RC80 1 2 10K_0402_5%
+3VS_APU
APU_SHUTDOWN# RC68 1 @ 2 10K_0402_5%
GPU_CLKREQ# RC65 1 PX@ 2 2K_0402_5%
RC98 1 PX@ 2 10K_0402_5% PXS_PWREN_R
RC99 1 @ 2 10K_0402_5% PXS_RST# HDA_BITCLK RC90 1 @ 2 10K_0402_5%
RC100 1 @ 2 10K_0402_5% VR_VGA_PWRGD HDA_SDIN0_R RC91 1 @ 2 10K_0402_5%

A RC101 1 @ 2 100K_0402_5% PXS_PWREN_R A


RC103 1 PX@ 2 2K_0402_5% PXS_RST# RSMRST#_R RC87 1 2 100K_0402_5%
RC104 1 UMA@2 2K_0402_5% VR_VGA_PWRGD SYS_PWRGD_R RC89 1 2 100K_0402_5%

HDA_SDIN2 RC241 1 @ 2 10K_0402_5%


CRB: CARRIZO NEED 10K PD ON UNUSED SDIN HDA_SDIN1 RC242 1 @ 2 10K_0402_5%
DG: 10K PD
PXS_PWREN_R/PXS_RST#_R/VR_VGA_PWRGD internal pull up 40k
Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (GEVENT/GPIO/SD/AZ)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Wednesday, February 24, 2016 Sheet 7 of 50
5 4 3 2 1
5 4 3 2 1

UC2E
CLK/SATA/USB/SPI/LPC
SATA_PTX_DRX_P0 AU3 AP8
{33} SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_TX0P USBCLK/25M_48M_OSC
AU4
{33} SATA_PTX_DRX_N0 SATA_TX0N USB_RCOMP
HDD AP5 RC112 1 2 11.8K_0402_1%
SATA_PRX_DTX_N0 AV1 USB_ZVSS
{33} SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_RX0N USB20_P0
AV2 AR2
{33} SATA_PRX_DTX_P0 SATA_RX0P USB_HSD0P USB20_N0 USB20_P0 {32}
AR1 Left USB2.0
SATA_PTX_DRX_P1 USB_HSD0N USB20_N0 {32}
AY2
{33} SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_TX1P
AY1 AR3
+3VS_APU {33} SATA_PTX_DRX_N1 SATA_TX1N USB_HSD1P
ODD AR4 RIGHT USB (2.0)
SATA_PRX_DTX_N1 AW4 USB_HSD1N
{33} SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_RX1N
AW3 AN2
D {33} SATA_PRX_DTX_P1 SATA_RX1P USB_HSD2P D
AN1
+0.95VS RC113 1 2 1K_0402_1% SATA_CALRN AW1 USB_HSD2N
RC114 1 2 1K_0402_1% SATA_CALRP AW2 SATA_ZVSS AN3 USB20_P3
RPC13 SATA0_DEVSLP_R SATA_ZVDDP USB_HSD3P USB20_N3 USB20_P3 {24}
AT17 AN4 Card Reader
DEVSLP0/EGPIO67 USB_HSD3N USB20_N3 {24}
3 2 EGPIO70 EGPIO70 AT12
4 1 SATA0_DEVSLP_R APU_TS_ON# BB15 DEVSLP1/EGPIO70 AM1 USB20_P4
SATA_ACT_L/AGPIO130 USB_HSD4P USB20_N4 USB20_P4 {31}
AM2 Blue Tooth
USB_HSD4N USB20_N4 {31}
10K_0404_4P2R_5% AU2
STN@
Nano not support Touch 10/20 SATA_X1 AL2 USB20_P5
USB_HSD5P USB20_P5 {23}
AGPIO130 CZ STN OD output, CZL output USB_HSD5N
AL1 USB20_N5
USB20_N5 {23} Camera
RC147 1 2 10K_0402_5% APU_TS_ON# AU1 AL3 USB20_P6
SATA_X2 USB_HSD6P USB20_N6 USB20_P6 {32}
AL4 LEFT USB (3.0) upper
USB_HSD6N USB20_N6 {32}
CLK_PCIE_GPU RC117 1 2 0_0402_5% CLK_PCIE_GPU_R U4 AK2
{15} CLK_PCIE_GPU CLK_PCIE_GPU# GFX_CLKP USB_HSD7P
RC118 1 @ 2 0_0402_5% CLK_PCIE_GPU#_R U3 AJ2
{15} CLK_PCIE_GPU# GFX_CLKN USB_HSD7N
@
U1
U2 GPP_CLK0P
GPP_CLK0N
CLK_PCIE_WLAN RC119 1 2 0_0402_5% CLK_PCIE_WLAN_R W4
CarrizoL don't support USB_SS_[1:0]
{31} CLK_PCIE_WLAN GPP_CLK1P
{31} CLK_PCIE_WLAN#
CLK_PCIE_WLAN# RC120 1 @ 2 0_0402_5% CLK_PCIE_WLAN#_R W3
GPP_CLK1N
Note: Route USB 3.0 ports starting from the lowest numbered port,
@
{28} CLK_PCIE_LAN
CLK_PCIE_LAN RC121 1 2 0_0402_5% CLK_PCIE_LAN_R W1 for example, Port0, Port1, Port2.
CLK_PCIE_LAN# 2 0_0402_5% CLK_PCIE_LAN#_R GPP_CLK2P
{28} CLK_PCIE_LAN#
RC122 1 @
@
W2
GPP_CLK2N All unused ports should be the highest numbered ports.
Y2
GPP_CLK3P
For CZ and CZL Co-lay, can start from Port2
Y1
GPP_CLK3N
TC53 @ 1 X14M_25M_48M_OSC BC10
X25M_48M_OSC AD2 USBSS_CALRN RC123 1 2 1K_0402_1% +0.95VALW
USB_SS_ZVSS AD1 USBSS_CALRP RC124 1 2 1K_0402_1%
C 48M_X1 T2 USB_SS_ZVDDP C
X48M_X1 AA3
USB_SS_0TXP AA4
USB_SS_0TXN USB3.0 port0 must map to USB2.0 port4,
48M_X2 T1
X48M_X2 USB_SS_0RXP
W9 USB3.0 port1 must map to USB2.0 port5,
W8
{30} TPM_CLK RC125 1 TPM@ 2 22_0402_5% USB_SS_0RXN USB3.0 port2 must map to USB2.0 port6,
{11,35} CLK_PCI_EC
RC126
RC127
1
1
2 3.3_0402_1%
2 0_0402_5%
LPCCLK0
LPCCLK1
AW14
AY13 LPCCLK0/EGPIO74 USB_SS_1TXP
AA2
AA1
USB3.0 port0 must map to USB2.0 port7
{11} LPC_CLK1 LPCCLK1/EGPIO75 USB_SS_1TXN
@
BB11 W5
Less than two USB 3.0 ports can be utilized provided
{30,35} LPC_AD0 LAD0 USB_SS_1RXP
{30,35} LPC_AD1
BA11
LAD1 USB_SS_1RXN
W6 the unused ports are higher-numbered consecutive
{30,35} LPC_AD2 AY11
{30,35} LPC_AD3 BA13 LAD2 AC1 USB30_TX_P2 ports. 10.15
LAD3 USB_SS_2TXP USB30_TX_N2 USB30_TX_P2 {32}
AV14 AC2
{11,30,35} LPC_FRAME# LFRAME_L USB_SS_2TXN USB30_TX_N2 {32}
TC54 @ 1 BA1 LEFT USB (3.0) upper
BC14 ESPI_ALERT_L/LDRQ0_L Y6 USB30_RX_P2
{30,35} SERIRQ SERIRQ/AGPIO87 USB_SS_2RXP USB30_RX_P2 {32}
BC11 Y7 USB30_RX_N2
LPC_CLKRUN_L/AGPIO88 USB_SS_2RXN USB30_RX_N2 {32}
RC149 1 2 10K_0402_5% AGPIO21 AE9
LPC_PD_L/AGPIO21 AC4
USB_SS_3TXP AC3
SPI_CLK RC209 1 @ 2 0_0402_5% SPI_CLK_R BC6 USB_SS_3TXN
{35} SPI_CLK SPI_CS0# SPI_CS0#_R SPI_CLK/ESPI_CLK/EGPIO117
RC202 1 @ 2 0_0402_5% BB8 AB5
{35} SPI_CS0# SPI_CS1_L/EGPIO118 USB_SS_3RXP
RC144 1 STN@2 10K_0402_5% EGPIO119 AW7 AB6
SPI_SO RC199 1 @ 2 0_0402_5% SPI_SO_R BA9 SPI_CS2_L/ESPI_CS_L/EGPIO119 USB_SS_3RXN
{35} SPI_SO SPI_SI SPI_SI_R SPI_DI/ESPI_DATA/EGPIO120
RC198 1 @ 2 0_0402_5% AY7
{35} SPI_SI SPI_WP# SPI_WP#_R SPI_DO/EGPIO121
RC132 1 @ 2 0_0402_5% AW11
SPI_HOLD# RC133 1 @ 2 0_0402_5% SPI_HOLD#_R BA7 SPI_WP_L/EGPIO122
RC143 1 @ 2 10K_0402_5% AGPIO76 AW12 SPI_HOLD_L/EGPIO133
SPI_TPM_CS_L/AGPIO76
FP4 REV 0.93
RC243 1 STNPX@2 0_0402_5%
{7,15} PXS_RST#
@
B 48MHz/10pF Crystal AMD-CARRIZO_FP4-BGA968 B
Reference CG412, only reserved for Stoney
48M_X1
+VCC_SPI
48M_X2
+VCC_SPI

RC140 1 2 1M_0402_5% 8M ROM 1


+3VALW_APU
CC27 +1.8VS
0.1U_0201_6.3V6-K +VCC_SPI RC1351 CZL@ 2 0_0402_5%
YC2 UC3 2 SPI_CLK
SPI_CS0# 1 8 RC1921 STN@ 2 0_0402_5%
1 4 CS# VCC
OSC1 NC2

2
SPI_SO 2 7 SPI_HOLD#
2 3 DO HOLD# +VCC_SPI
NC1 OSC2 SPI_WP# 3 6 SPI_CLK RC139
WP# CLK 10_0402_5%
1 1
48MHZ 10PF X1E000021083400 4 5 SPI_SI RPC8 EMC_NS@

1
CC28 CC29 GND DI SPI_WP# 1 4
12P_0402_50V8-J 12P_0402_50V8-J SPI_HOLD# 2 3
2 2 W25Q64FVSSIQ_SO8 2
10K_0404_4P2R_5% CC26
CZL@ 10P_0402_50V8J
SPI_CS0# RC138 1 2 10K_0402_5% EMC_NS@
1
with BOM strcture control, UC3 change to 1.8V SPI ROM for CZ EMC

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (SATA/USB/LPC/SPI)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Wednesday, February 24, 2016 Sheet 8 of 50
5 4 3 2 1
5 4 3 2 1

+1.35V UC2F +APU_CORE +APU_CORE


POWER

3A P25 U8
+1.35V VDDIO_MEM_S3_1 VDDCR_CPU_1

180P_0402_50V8-J
P28 W7
T24 VDDIO_MEM_S3_2 VDDCR_CPU_2 W12
T27 VDDIO_MEM_S3_3 VDDCR_CPU_3 W15
VDDIO_MEM_S3_4 VDDCR_CPU_4 1 1 1 1 1 1 1 1 1

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
180P_0402_50V8-J

CC137
U25 W18
VDDIO_MEM_S3_5 VDDCR_CPU_5

CC129

CC130

CC131

CC132 SIVCD@

CC133

CC134

CC135 SIVCD@

CC136
1 1 1 1 1 1 1 U28 W21
+1.35V VDDIO_MEM_S3_6 VDDCR_CPU_6

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

CC165
V30 Y8
VDDIO_MEM_S3_7 VDDCR_CPU_7 2 2 2 2 2 2 2 2 2

CC157

CC158

CC159 SIVCD@

CC160

CC161 SIVCD@

CC163
V33 Y10
W24 VDDIO_MEM_S3_8 VDDCR_CPU_8 Y13
2 2 2 2 2 2 2 W27 VDDIO_MEM_S3_9 VDDCR_CPU_9 Y16
VDDIO_MEM_S3_10 VDDCR_CPU_10
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
Y25 Y19
Y28 VDDIO_MEM_S3_11 VDDCR_CPU_11 Y22
1 1 1 1 1 1 1 1 1 1 1 VDDIO_MEM_S3_12 VDDCR_CPU_12 OK
CC42

CC54

CC55

CC56

CC57

CC58

CC59

CC60

CC53

CC61

CC62
SIVCD@ Y30 AB7
AB24 VDDIO_MEM_S3_13 VDDCR_CPU_13 AB9
OK AB27 VDDIO_MEM_S3_14 VDDCR_CPU_14 AB12
D D
@ 2 2 2 2 2 2 2 2 @ 2 @ 2 2 AB30 VDDIO_MEM_S3_15 VDDCR_CPU_15 AB15
AB33 VDDIO_MEM_S3_16 VDDCR_CPU_16 AB18
AD25 VDDIO_MEM_S3_17 VDDCR_CPU_17 AB21
SIVCD@ SIVCD@ AD28 VDDIO_MEM_S3_18 VDDCR_CPU_18 AD6
AD30 VDDIO_MEM_S3_19 VDDCR_CPU_19 AD10
+VAUDIO +VDDIO_AZ_APU AE24 VDDIO_MEM_S3_20 VDDCR_CPU_20 AD13
RC212 1 2 0_0402_5% AE27 VDDIO_MEM_S3_21 VDDCR_CPU_21 AD16
Wake-on-Ring not supported: VDDIO_MEM_S3_22 VDDCR_CPU_22

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
@ AF30 AD19
+VDDIO_AZ_APU Connect to +1.5V S0 rail 1 1 1 AF33 VDDIO_MEM_S3_23 VDDCR_CPU_23 AD22
VDDIO_MEM_S3_24 VDDCR_CPU_24

CC184

CC185

CC193
AG25 AE7
FP4 Type 3 (Stoney) processors do not use the VDDP_GFX AG28 VDDIO_MEM_S3_25 VDDCR_CPU_25 AE12
AH24 VDDIO_MEM_S3_26 VDDCR_CPU_26 AK9
power rail so leave VDDP_GFX unconnected. 2 2 2 AH27 VDDIO_MEM_S3_27 VDDCR_CPU_42 AG10
+0.95VS +0.95VS_GFX_APU AH30 VDDIO_MEM_S3_28 VDDCR_CPU_31 AK10
RC210 1 CZLPX@2 0_0805_5% AK25 VDDIO_MEM_S3_29 VDDCR_CPU_43 AG13
place near SVC/SVD/SVT Bus
VDDIO_MEM_S3_30 VDDCR_CPU_32

10U_0603_6.3V6M
SIVCD@ AK28 AK13
VDDIO_MEM_S3_31 VDDCR_CPU_44

100_0402_5%
1 1 AK30 AG16
VDDIO_MEM_S3_32 VDDCR_CPU_33

0.22U_0201_6.3V6-K
CC180
If P_GFX[7:0] are not used, AK33 AK16
VDDIO_MEM_S3_33 VDDCR_CPU_45 +1.35V

CC181 CZLPX@
RC229
AL27 AG19 DECOUPLING BETWEEN PROCESSOR AND DIMMs
VDDP_GFX power balls can be connected to VSS. AM30 VDDIO_MEM_S3_34 VDDCR_CPU_34 AK19
2
CZLPX@ 2 VDDIO_MEM_S3_35 VDDCR_CPU_46 AG22 ACROSS VDDIO AND VSS SPLIT
CZLUMA@ AR19 VDDCR_CPU_35 AK22
0.2A

2
VDDIO_AUDIO VDDCR_CPU_47

180P_0402_50V8-J

180P_0402_50V8-J
AH7
AE6 VDDCR_CPU_36 AE18
1.5A VDDP_GFX_2 VDDCR_CPU_28 1 1 1 1 1 1

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

CC179

CC176
AE5 AE21
+3VS RC214 +3VS_APU VDDP_GFX_1 VDDCR_CPU_29

CC168

CC169

CC170 SIVCD@

CC172
AH21
1 2 AP19 VDDCR_CPU_40 AG6
@
0.2A AP21 VDD_33_1 VDDCR_CPU_30 AH12 2 2 2 2 2 2
1 VDD_33_2 VDDCR_CPU_37
+1.8VS
10U_0603_6.3V6M
CC187

0_0402_5% AN6
AP16 VDDCR_CPU_49 AH15
1.5A VDD_18_1 VDDCR_CPU_38
10U_0603_6.3V6M

AP18 AH18
2 +1.8VALW VDD_18_2 VDDCR_CPU_39 AL7
1 1 VDDCR_CPU_48
0.22U_0201_6.3V6-K
CC186

0.5A AP10 AK6


VDD_18_S5_1 VDDCR_CPU_41
CC173

AR9 AE15
+3VALW_APU VDD_18_S5_2 VDDCR_CPU_27
10U_0603_6.3V6M

2 2 AP15
1 1 0.2A VDD_33_S5_1
0.22U_0201_6.3V6-K
CC188

AR15 L8
+0.95VALW VDD_33_S5_2 VDDCR_GFX_14
CC189

10U_0603_6.3V6M
L13 Design Guide G FP4 CRB
SIVCD@ AN12 VDDCR_GFX_15 L16
2 2 1 1 0.8A VDDP_S5_1 VDDCR_GFX_16

0.22U_0201_6.3V6-K

10U_0603_6.3V6M
CC190
AP12 L19 9*22uf 0603 9*22uf 0805 13*22uf 0603
+VDDCR_FCH_S5 VDDP_S5_2 VDDCR_GFX_17

CC191
C 1 1 L22 VDDCR_CPU 8*0.22uf 0402 8*0.22uf 0402 8*0.22uf 0402 C
VDDCR_GFX_18

0.22U_0201_6.3V6-K
CC182
0.2A AP13 N7 1*180pf 0402 1*180pf 0402 1*180pf 0402
+0.95VS 2 2 VDDCR_FCH_S5_1 VDDCR_GFX_19

CC183
AR12 N12 4*22uf 0603 4*22uf 0805 6*22uf 0603
+0.95VS VDDCR_FCH_S5_2 VDDCR_GFX_20 N15 8*0.22uf 0402 8*0.22uf 0402 8*0.22uf 0402 split *5
2 2 VDDCR_GFX_21 VDDCR_NB
7A AW19 N18 1*180pf 0402 1*180pf 0402 1*180pf 0402
VDDP_6 VDDCR_GFX_22
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

180P_0402_50V8-J

AU17 N21 9*22uf 0603 10*22uf 0805 13*22uf 0603


AU19 VDDP_1 VDDCR_GFX_23 P8 9*0.22uf 0402 9*0.22uf 0402 9*0.22uf 0402
1 1 1 1 1 1 1 1 1 1 1 VDDP_2 VDDCR_GFX_24 VDDCR_GFX
0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
CC175

CC174

CC171

CC167

CC177

AV17 P13 1*180pf 0402 1*180pf 0402 1*180pf 0402


VDDP_3 VDDCR_GFX_25
CC178

CC197

CC198

CC201

CC202

CC203

AV19 P16 8*22uf 0603 8*22uf 0603 8*22uf 0603


AW17 VDDP_4 VDDCR_GFX_26 P19 6*0.22uf 0402 split*4 6*0.22uf 0402 split*4 8*0.22uf 0402 split*4
2 2 2 2 2 2 2 2 2 2 2 +APU_CORE_NB VDDP_5 VDDCR_GFX_27 VDDIO_MEM_S3
P22 1*180pf 0402 split*2 1*180pf 0402 split*2 1*180pf 0402 split*2
AL12 VDDCR_GFX_28 T7 2*10uf 0402 2*10uf 0603 2*10uf 0603
12A AL13 VDDCR_NB_1 VDDCR_GFX_29 F12 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
VDDCR_NB_2 VDDCR_GFX_1 VDDCR_FCH_S5
SIVCD@ AL15 F15
AL18 VDDCR_NB_3 VDDCR_GFX_2 G11 4*10uf 0402 4*10uf 0603 4*10uf 0603
OK AL21 VDDCR_NB_4 VDDCR_GFX_3 G14 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
VDDCR_NB_5 VDDCR_GFX_4 VDDP
AN13 J8 1*180pf 0402 1*180pf 0402 1*180pf 0402
AN16 VDDCR_NB_6 VDDCR_GFX_5 J9 1*10uf 0402 1*10uf 0603 1*10uf 0603
+APU_CORE_NB AN19 VDDCR_NB_7 VDDCR_GFX_6 J11 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
VDDCR_NB_8 VDDCR_GFX_7 VDDP_GFX
AN22 K7
VDDCR_NB_9 VDDCR_GFX_8 K12 1*10uf 0402 1*10uf 0603 1*10uf 0603
+RTCBATT +RTCBATT_APU VDDCR_GFX_9 K13 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
VDDCR_GFX_10 VDDP_S5
180P_0402_50V8-J

RC6 1 2 AR17 K15


1K_0402_5% VDDBT_RTC_G VDDCR_GFX_11 K16 1*22uf 0603 1*22uf 0603 1*22uf 0603
1 1 1 1 1 1 1 1 1 1 1 1 1 VDDCR_GFX_12
0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
CC145

T12 VDD_18 1*10uf 0402 1*10uf 0402 1*10uf 0603


VDDCR_GFX_30
CC138

CC139

CC140

CC141 SIVCD@

CC142

CC143

CC144 SIVCD@

CC146

CC195 @

CC196 @

CC199 @

CC200 @

T15
VDDCR_GFX_31 T18 1*10uf 0402 1*10uf 0603 1*10uf 0603
2 2 2 2 2 2 2 2 2 2 2 2 2 1 VDDCR_GFX_32

0.22U_0201_6.3V6-K
T21 VDD_18_S5 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
VDDCR_GFX_33

CC192
U13
VDDCR_GFX_34 U16
2 VDDCR_GFX_35 U19 1*10uf 0402 1*10uf 0603 1*10uf 0603
VDDCR_GFX_36 VDD_33
OK follow CRB reserve U22
VDDCR_GFX_37 K19 1*10uf 0402 1*10uf 0403 1*10uf 0603
VDDCR_GFX_13 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
FP4 REV 0.93
VDD_33_S5
UC5
+VCCRTC @ AMD-CARRIZO_FP4-BGA968 3*1uf 0402 3*1uf 0402 3*1uf 0402
VDDIO_AUDIO
RC231 1 2 10K_0402_5% 1
Vin
3 +RTCBATT VDDBT_RTC_G 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
Vout
1U_0402_6.3V6K

1U_0402_6.3V6K

B 2 B
1 GND 1
1
CC37

CC194

JCMOS1 RC8 @
SHORT PADS 470_0603_5%
AP2138N-1.5TRG1_SOT23-3 @
2

2 2
12

D QC7
2 EC_RTCRST#_ON QC1/QC2/QC3/QC4 Rds on should less possible, CRB is 11.8mohm,
G EC_RTCRST#_ON {35}
there is no load swtich for 0.775V power, so it need mos
1

S
L2N7002KWT1G_SOT323-3 RC15
3

100K_0402_5%
@
@
2

+APU_CORE_NB +VDDCR_FCH_S5
UC7
1 8
VIN1_1 VOUT_1
10U_0603_6.3V6M

2 7
VIN1_2 VOUT_2
1

+0.775VALW
CC207

0.22U_0201_6.3V6-K
10U_0603_6.3V6M

10U_0603_6.3V6M
3 6 APU_S5_MUX_CTRL
+5VALW VIN2 SEL APU_S5_MUX_CTRL {7}
10U_0603_6.3V6M

1 1 1
2

CC162

CC164

CC166
STN@ 4 5
VCC EN
1
CC208

1U_0402_6.3V6K

1 9
GND 2 2 2
CC209
2

STN@
G5018RD1U_TDFN8_3X3
2
STN@ STN@ STN@ STN@
STN@

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (POWER&DECOUPLING)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Wednesday, February 24, 2016 Sheet 9 of 50
5 4 3 2 1
5 4 3 2 1

UC2G UC2H
GND GND
A8 L28 AE10 AV30
A12 VSS_1 VSS_63 M4 AE13 VSS_125 VSS_187 AV33
A16 VSS_2 VSS_64 M30 AE16 VSS_126 VSS_188 AW22
A20 VSS_3 VSS_65 N10 AE19 VSS_127 VSS_189 AY4
A24 VSS_4 VSS_66 N13 AE22 VSS_128 VSS_190 AY6
A28 VSS_5 VSS_67 N16 AF1 VSS_129 VSS_191 AY8
D D
A32 VSS_6 VSS_68 N19 AF4 VSS_130 VSS_192 AY10
B2 VSS_7 VSS_69 N22 AG9 VSS_131 VSS_193 AY12
B8 VSS_8 VSS_70 N27 AG12 VSS_132 VSS_194 AY14
B12 VSS_9 VSS_71 P1 AG15 VSS_133 VSS_195 AY16
B33 VSS_10 VSS_72 P2 AG18 VSS_134 VSS_196 AY20
C3 VSS_11 VSS_73 P4 AG21 VSS_135 VSS_197 AY22
D4 VSS_12 VSS_74 P5 AH4 VSS_136 VSS_198 AY24
D6 VSS_13 VSS_75 P12 AH10 VSS_137 VSS_199 AY26
D8 VSS_14 VSS_76 P15 AH13 VSS_138 VSS_200 AY28
D10 VSS_15 VSS_77 P18 AH16 VSS_139 VSS_201 AY30
D12 VSS_16 VSS_78 P21 AH19 VSS_140 VSS_202 BB1
D14 VSS_17 VSS_79 P30 AH22 VSS_141 VSS_203 BB33
D16 VSS_18 VSS_80 P33 AK1 VSS_142 VSS_204 BC4
D18 VSS_19 VSS_81 T4 AK4 VSS_143 VSS_205 BC8
D20 VSS_20 VSS_82 T10 AK12 VSS_144 VSS_206 BC12
D22 VSS_21 VSS_83 T13 AK15 VSS_145 VSS_207 BC16
D24 VSS_22 VSS_84 T16 AK18 VSS_146 VSS_208 BC20
D26 VSS_23 VSS_85 T19 AL16 VSS_147 VSS_209 BC24
D28 VSS_24 VSS_86 T22 AL19 VSS_148 VSS_210 BC28
D30 VSS_25 VSS_87 T30 AL22 VSS_149 VSS_211 BC32
F1 VSS_26 VSS_88 U5 AM4 VSS_150 VSS_212
F2 VSS_27 VSS_89 U12 AN9 VSS_151
F4 VSS_28 VSS_90 U15 AN10 VSS_152
F9 VSS_29 VSS_91 U18 AN15 VSS_153
C
F19 VSS_30 VSS_92 U21 AN18 VSS_154 C
F22 VSS_31 VSS_93 U24 AN21 VSS_155
F25 VSS_32 VSS_94 V1 AN25 VSS_156
F30 VSS_33 VSS_95 V2 AN28 VSS_157
F33 VSS_34 VSS_96 V4 AP1 VSS_158
G7 VSS_35 VSS_97 W10 AP2 VSS_159
G17 VSS_36 VSS_98 W13 AP4 VSS_160
G20 VSS_37 VSS_99 W16 AP7 VSS_161
G23 VSS_38 VSS_100 W19 AP22 VSS_162
G26 VSS_39 VSS_101 W22 AP27 VSS_163
H4 VSS_40 VSS_102 Y4 AP30 VSS_164
H30 VSS_41 VSS_103 Y5 AP33 VSS_165
VSS_42 VSS_104 VSS_166 UC2J
J5 Y12 AR6
J15 VSS_43 VSS_105 Y15 AR25 VSS_167
J19 VSS_44 VSS_106 Y18 AR28 VSS_168 @ TC4 1 U30
J22 VSS_45 VSS_107 Y21 AT4 VSS_169 @ TC6 1 U31 RSVD_2
J25 VSS_46 VSS_108 Y24 AT19 VSS_170 @ TC5 1 AN30 RSVD_3
J28 VSS_47 VSS_109 AB1 AT22 VSS_171 RSVD_4
K1 VSS_48 VSS_110 AB2 AT30 VSS_172
K2 VSS_49 VSS_111 AB4 AU5 VSS_173
K4 VSS_50 VSS_112 AB10 AU8 VSS_174
K10 VSS_51 VSS_113 AB13 AU11 VSS_175
K22 VSS_52 VSS_114 AB16 AU14 VSS_176
K27 VSS_53 VSS_115 AB19 AU20 VSS_177
K30 VSS_54 VSS_116 AB22 AU23 VSS_178 FP4 REV 0.93
B B
K33 VSS_55 VSS_117 AD4 AU27 VSS_179
L5 VSS_56 VSS_118 AD9 AV4 VSS_180 @
VSS_57 VSS_119 VSS_181 AMD-CARRIZO_FP4-BGA968
L12 AD12 AV7
L15 VSS_58 VSS_120 AD15 AV9 VSS_182
L18 VSS_59 VSS_121 AD18 AV12 VSS_183 L24
L21 VSS_60 VSS_122 AD21 AV15 VSS_184 VSS_213 AL10
L25 VSS_61 VSS_123 AD24 AV25 VSS_185 VSS_215 AK21
VSS_62 VSS_124 VSS_186 VSS_214
FP4 REV 0.93 FP4 REV 0.93
@ AMD-CARRIZO_FP4-BGA968 @ AMD-CARRIZO_FP4-BGA968

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (VSS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Wednesday, February 24, 2016 Sheet 10 of 50
5 4 3 2 1
5 4 3 2 1

+3VS +3VALW_APU +3VS +3VALW_APU +3VS +3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU +3VS_APU

2
RC152 RC169 RC153 RC200 RC154 RC173 RC155 RC156 RC157 RC158 RC81
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ @ @ @
D D

1
{8,30,35} LPC_FRAME#

{8} LPC_CLK1

{8,35} CLK_PCI_EC

{7} AGPIO3

{7} SYS_RESET#

{7,31} SUSCLK

{7} BLINK

{7,35} HVB_EN

1
RC79
C RC159 RC160 RC161 RC162 RC163 RC164 RC165 C
2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 0_0402_5%
@ @ @ @ @ @

2
STRAP PINS
LFRAME_L LPCCLK1 LPCCLK0 GEVENT2_L/AGPIO3 SYS_RESET_L RTCCLK BLINK(for CZL strap) HVB_EN
Signal
Int pull-up Int pull-up Int pull-up Int pull-up

Type II II II II I I I I
CZL CZ
SPI ROM Internal Boot Fail Timer Normal Power Up Coin Battery PWROK and RST_L floating
PULL CLK Gen Enabled Enhanced reset &Reset Timing pin routed to APU
HIGH 1.8V SPI logic (for quicker Disable HVB
Default Default S5 resume) on FP4 platforms
Default Default Default
Default Default
B B
Boot Fail Timer Default to Reserved Direct DC Reserved connected to VSS
PULL LPC ROM Reserved Disabled 3.3VSPI traditional
LOW reset logic Enable HVB
Default Default on FP4 platforms

Type I straps become valid immediately after capture with the rising edge of RSMRST_L,they are captured only once when power is first applied to the processor
Type II straps become valid after PWR_GOOD is asserted,straps are captured every time the systems powers up from the S5 state. A transition from S3 to S0 does not trigger capture.
Type II straps should be pulled up to S0 power rail to prevent leakage when the signal is connected to a device in S0 power domain.
If the LPC bus is connected to devices that are on S0 power rail, then a pull-up resistor to VDD_33 is implemented.

All Strap pins must be configured with either external pull-up or pull-down resistors.
Platforms that are designed for AOAC complaint are recommended to use the Alternate Reset by strapping this pin to ‘1’ for CZ AGPIO3

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (STRAPS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Wednesday, February 24, 2016 Sheet 11 of 50
5 4 3 2 1
5 4 3 2 1

DDRB_DQ[0..63]
DDRB_DQ[0..63] {5}
DDR3 SO-DIMM A DDRB_DQS[0..7]
DDRB_DQS[0..7] {5}
DDRB_DQS#[0..7]
DDRB_DQS#[0..7] {5}
DDRB_MA[0..15]
+VREF_DQ DDRB_MA[0..15] {5}
JDDR1
1 2 DDRB_DM[0..7]
VREF_DQ VSS1 DDRB_DM[0..7] {5}
3 4 DDRB_DQ4
DDRB_DQ0 5 VSS2 DQ4 6 DDRB_DQ5
DDRB_DQ1 7 DQ0 DQ5 8
D 9 DQ1 VSS3 10 DDRB_DQS#0 D
DDRB_DM0 11 VSS4 DQS0# 12 DDRB_DQS0
13 DM0 DQS0 14
DDRB_DQ2 15 VSS5 VSS6 16 DDRB_DQ6 +1.35V +1.35V
DDRB_DQ3 17 DQ2 DQ6 18 DDRB_DQ7
19 DQ3 DQ7 20
VSS7 VSS8

1
DDRB_DQ8 21 22 DDRB_DQ12
DDRB_DQ9 23 DQ8 DQ12 24 DDRB_DQ13 RD10 RD12
25 DQ9 DQ13 26 +VREF_DQ 1K_0402_1% +VREF_CA
VSS9 VSS10 1K_0402_1%
DDRB_DQS#1 27 28 DDRB_DM1
DDRB_DQS1 29 DQS1# DM1 30 MEM_MB_RST#
MEM_MB_RST# {5} 15mil 15mil

2
31 DQS1 RESET# 32 R251 1 @ 2 0_0402_5%
DDRB_DQ10 VSS11 VSS12 DDRB_DQ14 {5} APU_M_VREFDQ
33 34
DQ10 DQ14

1
CD120 0.1U_0201_6.3V6-K
DDRB_DQ11 35 36 DDRB_DQ15 1
DQ11 DQ15

CD116 0.1U_0201_6.3V6-K

CD118 0.1U_0201_6.3V6-K
37 38 RD11 1 1 RD25 1 1
DDRB_DQ16 39 VSS13 VSS14 40 DDRB_DQ20 1K_0402_1% CD117 1K_0402_1% CD119
DDRB_DQ17 41 DQ16 DQ20 42 DDRB_DQ21 1000P_0201_50V7-K 1000P_0201_50V7-K
43 DQ17 DQ21 44 2 @
for MEM_MB_RST# overshoot issue

2
DDRB_DQS#2 45 VSS15 VSS16 46 DDRB_DM2 2 2 2 2
DDRB_DQS2 47 DQS2# DM2 48
49 DQS2 VSS17 50 DDRB_DQ22
DDRB_DQ18 51 VSS18 DQ22 52 DDRB_DQ23
DDRB_DQ19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDRB_DQ28
DDRB_DQ24 57 VSS20 DQ28 58 DDRB_DQ29
DDRB_DQ25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDRB_DQS#3
DDRB_DM3 63 VSS22 DQS3# 64 DDRB_DQS3
65 DM3 DQS3 66
DDRB_DQ26 67 VSS23 VSS24 68 DDRB_DQ30
DDRB_DQ27 69 DQ26 DQ30 70 DDRB_DQ31
+1.35V DQ27 DQ31 +1.35V 3A@1.5V
71 72
C VSS25 VSS26 +1.35V C
Layout Note:
{5} DDRB_CKE0
DDRB_CKE0 73
75 CKE0 CKE1
74
76
DDRB_CKE1
DDRB_CKE1 {5} Place near DIMM1
77 VDD1 VDD2 78 DDRB_MA15
NC1 A15

22P_0402_50V8-J
DDRB_BS2# 79 80 DDRB_MA14
{5} DDRB_BS2# BA2 A14

CD17 0.1U_0201_6.3V6-K

CD20 0.1U_0201_6.3V6-K

CD22 0.1U_0201_6.3V6-K

CD21 0.1U_0201_6.3V6-K

CD23 0.1U_0201_6.3V6-K

CD58 0.1U_0201_6.3V6-K

CD59 0.1U_0201_6.3V6-K

CD60 0.1U_0201_6.3V6-K

CD61 0.1U_0201_6.3V6-K
81 82 1 1 1 CD19 1 1 1 1 1 1 1 1 1
DDRB_MA12 83 VDD3 VDD4 84 DDRB_MA11
DDRB_MA9 85 A12/BC# A11 86 DDRB_MA7 CD16 CD18
87 A9 A7 88
VDD5 VDD6 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
DDRB_MA8 89 90 DDRB_MA6 2 2 @ 2 @ 2 2 2 2 @ 2 @ 2 @ 2 2 @ 2 @
DDRB_MA5 91 A8 A6 92 DDRB_MA4 RF@
93 A5 A4 94
DDRB_MA3 95 VDD7 VDD8 96 DDRB_MA2
DDRB_MA1 97 A3 A2 98 DDRB_MA0
99 A1 A0 100
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1 +1.35V
{5} DDRB_CLK0 CK0 CK1 DDRB_CLK1 {5}
DDRB_CLK0# 103 104 DDRB_CLK1#
{5} DDRB_CLK0# CK0# CK1# DDRB_CLK1# {5}
105 106
DDRB_MA10 107 VDD11 VDD12 108 DDRB_BS1#
DDRB_BS0# A10/AP BA1 DDRB_RAS# DDRB_BS1# {5}
{5} DDRB_BS0# 109 110
BA0 RAS# DDRB_RAS# {5}

CD12 22P_0402_50V8-J

CD122 22P_0402_50V8-J
22U_0805_6.3V6M

22U_0603_6.3V6-M
111 112
VDD13 VDD14

10U_0805_10V6K

10U_0805_10V6K

CD5

CD6

CD7

CD11 22P_0402_50V8-J

CD121 22P_0402_50V8-J
DDRB_WE# 113 114 DDRB_CS0# 1 1 1 1 1 1 1 1 1 1 1
{5} DDRB_WE# WE# S0# DDRB_CS0# {5}
DDRB_CAS# 115 116 DDRB_ODT0 CD62 CD63 CD66 CD67
{5} DDRB_CAS# CAS# ODT0 DDRB_ODT0 {5}
117 118
VDD15 VDD16

.047U_0201_6.3V6K

.047U_0201_6.3V6K

.047U_0201_6.3V6K
DDRB_MA13 119 120 DDRB_ODT1 @ @ @ @
A13 ODT1 DDRB_ODT1 {5} 2 2 2 2 2 2 2 2 2 2 2

RF@

RF@

RF@

RF@
DDRB_CS1# 121 122
{5} DDRB_CS1# S1# NC2 +VREF_CA
123 124
125 VDD17 VDD18 126
127 TEST VREF_CA 128
DDRB_DQ32 VSS27 VSS28 DDRB_DQ36
RF
129 130
DDRB_DQ33 131 DQ32 DQ36 132 DDRB_DQ37
B 133 DQ33 DQ37 134 B
DDRB_DQS#4 135 VSS29 VSS30 136 DDRB_DM4
DDRB_DQS4 137 DQS4# DM4 138
139 DQS4 VSS31 140 DDRB_DQ38
DDRB_DQ34 141 VSS32 DQ38 142 DDRB_DQ39
DDRB_DQ35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDRB_DQ44
DDRB_DQ40 147 VSS34 DQ44 148 DDRB_DQ45
DDRB_DQ41 149 DQ40 DQ45 150 Layout Note:
DQ41 VSS35
DDRB_DM5
151
153 VSS36 DQS5#
152
154
DDRB_DQS#5
DDRB_DQS5
+0.675VS
Place near DIMM1
155 DM5 DQS5 156
DDRB_DQ42 157 VSS37 VSS38 158 DDRB_DQ46
DDRB_DQ43 159 DQ42 DQ46 160 DDRB_DQ47
DQ43 DQ47

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

CD123 22P_0402_50V8-J
161 162
DDRB_DQ48 163 VSS39 VSS40 164 DDRB_DQ52
DQ48 DQ52 1 1 1 1 1
DDRB_DQ49 165 166 DDRB_DQ53 CD24 CD25 CD26 CD27
167 DQ49 DQ53 168
DDRB_DQS#6 169 VSS41 VSS42 170 DDRB_DM6 @ @
DQS6# DM6 2 2 2 2 2

RF@
DDRB_DQS6 171 172
173 DQS6 VSS43 174 DDRB_DQ54
DDRB_DQ50 175 VSS44 DQ54 176 DDRB_DQ55
DDRB_DQ51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDRB_DQ60
DDRB_DQ56 181 VSS46 DQ60 182 DDRB_DQ61
DDRB_DQ57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDRB_DQS#7
DDRB_DM7 187 VSS48 DQS7# 188 DDRB_DQS7
189 DM7 DQS7 190
DDRB_DQ58 191 VSS49 VSS50 192 DDRB_DQ62
DDRB_DQ59 193 DQ58 DQ62 194 DDRB_DQ63
195 DQ59 DQ63 196
A 197 VSS51 VSS52 198 MEM_MB_EVENT# A
SA0 EVENT# MEM_MB_EVENT# {5}
199 200 APU_SMB_DATA
+3VS VDDSPD SDA APU_SMB_CLK APU_SMB_DATA {7,31}
201 202
SA1 SCL APU_SMB_CLK {7,31}
CD29 0.1U_0201_6.3V6-K

1 1 203 204 +0.675VS


VTT1 VTT2
CD28 205 206 1 0.65A@0.75V Title
2.2U_0402_6.3V6M 207 GND1 GND2 208 Security Classification LC Future Center Secret Data
2 2 BOSS1 BOSS2 CD70
22P_0402_50V8-J
Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRIII SO-DIMM A
SIVCD@ LCN_DAN06-K4406-0103 2 RF@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
ME@ Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
RF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Wednesday, February 24, 2016 Sheet 12 of 50

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRIII SO-DIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Wednesday, February 24, 2016 Sheet 13 of 50
5 4 3 2 1
5 4 3 2 1

Power-Up/Down Sequence
"Topaz" has the following requirements with regards to power-supply sequencing to
avoid damaging the ASIC:
D D
All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/μs. VRAM ID config
It is recommended that the 3.3-V rail ramp up first.
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 μs Memory Type
VRAM ID PU resistor PD resistor
before VDDC, VDDCI, and VMEMIO start to ramp up. PS_3[3:1] RV63 RV70
The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example
NA 100 4.53K 4.99K
AMD PowerXpress idle state), all the power rails are removed from the dGPU.
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/μs).
For power down, reversing the ramp-up sequence is recommended. 128Mx16
NA 111 4.75K NC

NA 110 3.4K 10K


0 ~ 20ms
Hynix
VDDR3(+3VGS) H5TC4G63CFR-N0C 4Gb 900(1G)
000 NC 4.75K
0 ~ 20ms
C C
Micron
VDD_CT(+1.8VGS) 256Mx16
MT41J256M16LY-091G:N 4Gb 900(1G)
010 4.53K 2K

Samsung
PCIE_VDDC(+0.95VGS) K4W4G1646E-BC1A 4Gb 900(1G)
001 8.45K 2K

10us min.

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE) 100ms min.

PERSTb(GPU_RST#) 100us min.

REFCLK(CLK_PCIE_VGA)

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Wednesday, February 24, 2016 Sheet 14 of 50
5 4 3 2 1
5 4 3 2 1

PCIE_CTX_C_GRX_P[3..0] PCIE_CRX_GTX_P[3..0]
{4} PCIE_CTX_C_GRX_P[3..0] PCIE_CRX_GTX_P[3..0] {4}
UV1A
PCIE_CTX_C_GRX_N[3..0] PCIE_CRX_GTX_N[3..0]
{4} PCIE_CTX_C_GRX_N[3..0] PCIE_CRX_GTX_N[3..0] {4}

PCIE_CTX_C_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0 CV1 CZLPX@1 PCIE_CRX_GTX_P0


2 0.1U_0201_6.3V6-K
PCIE_CTX_C_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PCIE_CRX_C_GTX_N0 CV2 CZLPX@1 PCIE_CRX_GTX_N0
2 0.1U_0201_6.3V6-K
PCIE_RX0N PCIE_TX0N
D D
PCIE_CTX_C_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1 CV3 CZLPX@1 PCIE_CRX_GTX_P1
2 0.1U_0201_6.3V6-K
PCIE_CTX_C_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PCIE_CRX_C_GTX_N1 CV4 CZLPX@1 PCIE_CRX_GTX_N1
2 0.1U_0201_6.3V6-K
PCIE_RX1N PCIE_TX1N

PCIE_CTX_C_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2 CV5 CZLPX@1 PCIE_CRX_GTX_P2


2 0.1U_0201_6.3V6-K
PCIE_CTX_C_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_CRX_C_GTX_N2 CV6 CZLPX@1 PCIE_CRX_GTX_N2
2 0.1U_0201_6.3V6-K
PCIE_RX2N PCIE_TX2N

PCIE_CTX_C_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3 CV7 CZLPX@1 PCIE_CRX_GTX_P3


2 0.1U_0201_6.3V6-K
PCIE_CTX_C_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_CRX_C_GTX_N3 CV8 CZLPX@1 PCIE_CRX_GTX_N3
2 0.1U_0201_6.3V6-K
PCIE_RX3N PCIE_TX3N

AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N

AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N

Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N

W29 Y27
V28 PCIE_RX7P PCIE_TX7P Y26
PCIE_RX7N PCIE_TX7N
C C

V30 W24
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23

U29 V27 with BOM strcture control, CV1--CV8 change to 0.22uf for CZ
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26

PCI EXPRESS INTERFACE


T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23

R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27

P30
NC#P30 NC#T24
T24 change the GPU PN to AMD(EXO-S3 PRO), symbol check ok
N31 T23
NC#N31 NC#T23

N29
NC#N29 NC#P27
P27 11/4 change to PC sample SA000074V10
M28 P26
NC#M28 NC#P26

M30 P24
L31 NC#M30 NC#P24 P23
B NC#L31 NC#P23 B

L29 M27
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26

CLOCK
CLK_PCIE_GPU AK30
{8} CLK_PCIE_GPU CLK_PCIE_GPU# PCIE_REFCLKP
AK32
{8} CLK_PCIE_GPU# PCIE_REFCLKN
+0.95VGS
CALIBRATION
Y22 RV3 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX
1K_0402_1% 1 PX@ 2 RV4 N10 AA22 RV5 1 PX@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX

GPU_RST# AL27
{16} GPU_RST# PERSTB
1

AMD R16M-M1-30 DV3 PX@


RV7 1 @ 2 0_0402_5% RV6 EXO@ GPU_RST# 2
100K_0402_5% 1 VGA_PWROK
VR_VGA_PWRGD VGA_PWROK {48}
+3VGS PX@ 3
{7,48} VR_VGA_PWRGD
2

BAT54AWT1G_SOT323-3
5

A A
UV2
VCC

1
{7,8} PXS_RST# IN1 GPU_RST#
4
2 OUT
Title
GND

{7,28,31} PLT_RST# IN2 Security Classification LC Future Center Secret Data


MC74VHC1G08DFT2G_SC70-5 Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_PCIE
3

PX@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
Date: Wednesday, February 24, 2016 Sheet 15 of 50
5 4 3 2 1
5 4 3 2 1
RECOMMENDED SETTINGS
CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
UV1B ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE X = DESIGN DEPENDANT
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE

AF2
NC#AF2 RECOMMENDED
NC#AF4
AF4 MLPS Bit Strap Name Description
SETTINGS
N9 AG3 PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,
L9 DBG_DATA16 NC#AG3 AG5 PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
AE9 DBG_DATA15 NC#AG5 PS_0[3] ROM_CONFIG[2] X
DBG_DATA14 DPA
Y11 AH3 100 = 256MB
AE8 DBG_DATA13 NC#AH3 AH1
AD9 DBG_DATA12 NC#AH1 PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1
AC10 DBG_DATA11 AK3
AD7 DBG_DATA10 NC#AK3 AK1 AUD_PORT_CONN_ The LSB (least significant bit) of the strap option that
AC8 DBG_DATA9 NC#AK1 PS_0[5] PINSTRAP[0] indicates the number of audio-capable display outputs. X
DVO
AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3 1 = PCIe GEN3 is supported.
AB8 DBG_DATA6 NC#AM3 PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported. 0= Not support X
AB7 DBG_DATA5 AK6
AB4 DBG_DATA4 NC#AK6 AM5 0 = The CLKREQB power management capability is disabled
AB2 DBG_DATA3 NC#AM5 PS_1[2] STRAP_BIF_CLK_PM_EN 1 = The CLKREQB power management capability is enabled 0
DPB
Y8 DBG_DATA2 AJ7
D
Y7 DBG_DATA1 NC#AJ7 AH6 PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0 D
DBG_DATA0 NC#AH6
AK8 STRAP_TX_CFG_DRV_ 0 = The transmitter half-swing is enabled
NC#AK8 AL7 PS_1[4] FULL_SWING 1 = The transmitter full-swing is enabled 1
NC#AL7
0 = Tx deemphasis disabled.
W6 PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled. 1= Enable X
V6 NC#W6
NC#V6 V4 PS_2[1] N/A Reserved. NA
AC6 NC#V4 U5
AC5 NC#AC6 NC#U5 PS_2[2] N/A Reserved. NA
NC#AC5
Reserve NC#W3
W3 VGA_VSSI_SEN 1 TV10 PAD @
AA5 V2 0 = Disable the external BIOS ROM device.
AA6 NC#AA5 NC#V2 PS_2[3] STRAP_BIOS_ROM_EN 1 = Enable the external BIOS ROM device. 0= Disable X
DPC
+3VGS +1.8VGS NC#AA6 Y4
NC#Y4 W5 0 = VGA controller capacity enabled.
NC#W5 PS_2[4] STRAP_BIF_VGA_DIS 1 = The device will not be recognized as the system’s VGA 0
10K_0402_5% 1 @ 2 RV8 GPU_GPIO5 RV93 1 2 TOPAZ@ BP_0 U1 AA3 PLL_ANALOG_OUT RV94 1 @ 2 controller.
10K_0402_5% 1 @ 2 RV1011 GPU_GPIO17 4.7K_0402_5% TV11 @ 1 VGA_VDDCI_SEN W1 NC#U1 NC#AA3 Y2 16.2K_0402_1% PS_2[5] N/A Reserved NA
RV95 1 2 TOPAZ@ PAD BP_1 U3 NC#W1 NC#Y2
4.7K_0402_5% Y6 NC#U3 J8 Board configuration related strapping, such as for memory ID
NC#Y6 NC#J8 Reserve for Topaz
10K_0402_5% 1 @ 2 RV9 GPU_GPIO0 TV12 @ 1 PLL_ANALOG_IN AA1 PS_3[1] BOARD_CONFIG[0] 100 = Hynix 1G 000 = Hynix 2G X
10K_0402_5% 1 @ 2 RV12 GPU_GPIO8 PAD NC#AA1 PS_3[2] BOARD_CONFIG[1] 111 = Micron 1G 010 = Micron 2G
10K_0402_5% 1 @ 2 RV13 GPU_GPIO9 PS_3[3] BOARD_CONFIG[2] 110 = Samsung 1G 001 = Samsung 2G
10K_0402_5% 1 @ 2 RV14 GPU_GPIO10
10K_0402_5% 1 @ 2 RV25 GPU_GPIO11 Determines the maximum number of digital display audio endpoints
10K_0402_5% 1 @ 2 RV96 GPU_GPIO12 I2C that will be presented to the OS and user.(Combine with PS_0[5])
10K_0402_5% 1 @ 2 RV34 GPU_GPIO13 111 = No usable endpoints.
10K_0402_5% 1 @ 2 RV81 GPU_GPIO22 R1 AUD_PORT_CONN_ 110 = One usable endpoint.
10K_0402_5% 1 @ 2 RV97 GPU_VID1 R3 SCL PS_3[4] PINSTRAP[1] 101 = Two usable endpoints. 111= No usable endpoints.
10K_0402_5% 1 @ 2 RV98 GPU_GPIO21 SDA TOPAZ@ 100 = Three usable endpoints. X
10K_0402_5% 1 @ 2 RV99 GPU_VID5 AM26 DIECRACKMON RV120 1 2 PS_3[5] AUD_PORT_CONN_ 011 = Four usable endpoints.
10K_0402_5% 1 @ 2 RV106 GPU_VID2 NC_R AK26 10K_0402_5% PINSTRAP[2] 010 = Five usable endpoints.
GPU_GPIO0 NC_AVSSN#AK26 001 = Six usable endpoints.
U6 GENERAL PURPOSE I/O
000 = All endpoints are usable.
GPIO_0
Reserve U10 +VGA_CORE_GPIO1
NC_GPIO_1 NC_G
AL25
T10 +VGA_CORE_GPIO2 AJ25
LRB751V-40T1G_SOD323-2 U8 VGA_SMB_DATA NC_GPIO_2 NC_AVSSN#AJ25
U7 VGA_SMB_CLK SMBDATA AH24
DV1
+VGA_CORE 1 2 @ T9 GPU_GPIO5 SMBCLK NC_B AG25 +1.8VGS +1.8VGS
{35} VGA_AC_DET GPU_VID5 GPIO_5_AC_BATT NC_AVSSN#AG25
T8
RV100 1 2 0_0402_5% +VGA_CORE_GPIO1 T7 GPIO_6 DAC1 AH26
NC_GPIO_7 NC_HSYNC

1
TOPAZ@ GPU_VR_HOT# RV104 1 @ 2 0_0402_5% GPU_GPIO8 P10 AJ27 4.7K_0402_5% 1 TOPAZ@2 RV22
RV101 1 2 0_0402_5% +VGA_CORE_GPIO2 GPU_GPIO9 P4 GPIO_8_ROMSO NC_VSYNC RV71 RV74
TOPAZ@ GPU_GPIO10 P2 GPIO_9_ROMSI 8.45K_0402_1% 8.45K_0402_1%
RV102 1 2 0_0402_5% +VGA_CORE_GPIO14 GPU_GPIO11 N6 GPIO_10_ROMSCK AD22 PX@ STNPX@
GPU_GPIO12 NC_GPIO_11 NC_RSET Pull down for none OBFF design
TOPAZ@ @ PAD TV3 1 N5

2
RV108 1 2 0_0402_5% +VGA_CORE_GPIO18 GPU_GPIO13 N3 NC_GPIO_12 AG24 PS_0 PS_1
TOPAZ@ +VGA_CORE_GPIO14 Y9 NC_GPIO_13 NC_AVDD AE22
NC_GPIO_14 NC_AVSSQ

1
CV15

CV16
GPU_SVD 0_0402_5% 1 EXO@2 RV103 GPU_VID3 N1 1 1
10K_0402_5% 1 @ 2 RV67 GPU_GPIO16 M4 GPIO_15_PWRCNTL_0 AE23 RV77 RV80
C C
0_0402_5% 1 PX@ 2 RV107 GPU_GPIO17 R6 GPIO_16 NC_VDD1DI AD23 2K_0402_1% 4.75K_0402_1%
{48} GPU_VR_HOT# +VGA_CORE_GPIO18 W10 GPIO_17_THERMAL_INT NC_VSS1DI PX@ @ CZLPX@ @
PX@ 2 RV68 NC_GPIO_18 2 2

0.01U_0201_6.3V7-K

0.01U_0201_6.3V7-K
10K_0402_5% 1 GPIO_19_CTF M2 FutureASIC/SEYMOUR/PARK

2
GPU_SVC 0_0402_5% 1 EXO@2 RV105 GPU_VID4 P8 GPIO_19_CTF AM12 CEC_1 1 @ TV5
GPU_GPIO21 P7 GPIO_20_PWRCNTL_1 CEC_1 PAD
GPU_GPIO22 N8 GPIO_21
RV1012 GPU_VID2 AK10 GPIO_22_ROMCSB AK12 GPU_SVD_R RV110 1TOPAZ@ 2 0_0402_5% +1.8VGS +1.8VGS
GPU_VR_HOT# 0_0402_5% 1 GPIO_29 NC_SVI2#AK12 GPU_SVD {48}
@ 2GPU_VID1 AM10 AL11 GPU_SVT_R RV109 1TOPAZ@ 2 0_0402_5%
GPU_CLKREQ#_R GPIO_30 NC_SVI2#AL11 GPU_SVC_R GPU_SVT {48}
0_0402_5% 1 @ 2 RV124 N7 AJ11 RV111 1TOPAZ@ 2 0_0402_5%
{7} GPU_CLKREQ# CLKREQB NC_SVI2#AJ11 GPU_SVC {48}

1
JTAG_TRSTB L6 RV60 RV63
+3VGS JTAG_TDI L5 JTAG_TRSTB 10K_0402_5% 8.45K_0402_1%
JTAG_TCK L3 JTAG_TDI @ @
PAD JTAG_TMS L1 JTAG_TCK AL13 GENLK_CLK 1 TV1 PAD @

2
10K_0402_5% 1 @ 2 RV72 JTAG_TRSTB TV7 @ 1JTAG_TDO K4 JTAG_TMS NC_GENLK_CLK AJ13 GENLK_VSYNC 1 TV2 PAD @ PS_2 PS_3
10K_0402_5% 1 @ 2 RV75 JTAG_TDI RV64 1 PX@ 2 TESTEN K7 JTAG_TDO NC_GENLK_VSYNC
TESTEN

1
CV18

CV19
10K_0402_5% 1 @ 2 RV78 JTAG_TMS 1K_0402_5% AF24 1 1
NC#AF24

0.01U_0201_6.3V7-K

0.01U_0201_6.3V7-K
AG13 RV69 RV70
10K_0402_5% 1 @ 2 RV40 JTAG_TCK NC_SWAPLOCKA AH12 4.75K_0402_1% 2K_0402_1%
0_0402_5% 1 2 RV112 AB13 NC_SWAPLOCKB PX@ @ @ @
+VGA_CORE NC_GENERICA 2 2
TOPAZ@ W8

2
0_0402_5% 1 2 RV113 W9 NC_GENERICB
TOPAZ@ W7 NC_GENERICC AC19 PS_0
0_0402_5% 1 2 RV114 AD10 NC_GENERICD PS_0
TOPAZ@ AJ9 NC_GENERICE_HPD4 AD19 PS_1
AL9 NC#AJ9 PS_1
DBG_CNTL0 PS_2
Bit BOM
AE17 MLPS
PS_2
PX_EN
AC14
NC_HPD1 PS_3
5 4 3 2 1 R_pu( ) R_pd( ) C(nF)
PAD TV6 @ 1 AB16 AE20
PX_EN PS_3
PS_0[5:1] 1 1 0 0 1 RV71=8.45k RV77=2K CV15=NC
4.7K_0402_5% 1 @ 2RV54
PX@ 2 1 CV25 XTALIN AE19 PS_1[5:1] 1 1 0 0 0 RV74=NC RV77=4.75K CV16=NC
AC16 TS_A
8P_0402_50V8-D NC_DBG_VREFG
PS_2[5:1] 1 1 0 0 0 RV60=NC RV69=4.75K CV18=NC
PS_3[5:1] 1 1 X X X RV63=X76 RV70=X76 CV19=X76
DDC/AUX
2

AE6
27MHZ_10PF_7V27000050

NC_DDC1CLK
YV1 PLL/CLOCK AE5 with BOM strcture control, R_pu (Ω) R_pd (Ω) Bits [3:1]
GND1

OSC1

PX@ NC_DDC1DATA
RV63,RV70 change to different value to
1

AD2 +VGA_CORE NC 4750 000


RV46 NC_AUX1P AD4
1
adjust VRAM config
1M_0402_5% NC_AUX1N RV24 8450 2000 001
with BOM strcture control,
GND2
OSC2

PX@ AC11 RV115 1 TOPAZ@2 0_0402_5% when config PEG3


NC_DDC2CLK AC13 RV116 1 2 0_0402_5% 0_0402_5% 4530 2000 010
RV74 change to 8.45K,
2

NC_DDC2DATA TOPAZ@ EXO@


2

XTALIN AM28 AD13 RV80 change to 2K 6980 4990 011


3

XTALOUT AK28 XTALIN NC_AUX2P AD11


XTALOUT NC_AUX2N
B XO_IN VGA_VSS_SEN_R
Capacitor Value (nF) Bits [5:4] 4530 4990 100
B
10K_0402_5% 1 PX@ 2 RV45 AC22 AD20 RV125 1 TOPAZ@2 0_0402_5%
XO_IN2 XO_IN NC#AD20 VGA_CORE_SEN_R VGA_VSS_SEN {48}
10K_0402_5% 1 PX@ 2 RV50 AB22 AC20 RV126 1 2 0_0402_5% 680 00 3240 5620 101
XO_IN2 NC#AC20 VGA_CORE_SEN {48}
TOPAZ@
PX@ 2 1 CV32 XTALOUT AE16 82 01 3400 10000 110
NC#AE16 AD16
8P_0402_50V8-D NC#AD16 10 10 4750 NC 111
1

SEYMOUR/FutureASIC AC1
NC_DDCVGACLK
no symbol for 8pf cap, PLM has PN,change the PN PAD TV13@ 1 GPU_DPLUS
GPU_DMINUS
T4
DPLUS THERMAL NC_DDCVGADATA
AC3 RV23 NC 11 Note: 0402 1% resistors are required.
PAD TV14@ 1 T2
DMINUS 0_0402_5%
EXO@ +3VGS +VDDIO_GPU
2

RV41 1 @ 2 GPIO_28_FDO R5
+3VGS GPIO28_FDO
10K_0402_5% +1.8VGS LV3 1 2 PX@ +TSVDD AD17
TSVDD SVC SVD Output Voltage (V) RV234 1 2 EXO@
PBY100505T-121Y-N_2P AC17 +1.8VGS 0_0402_5%
TSVSS +VGA_CORE
CV21

0 0 1.1
1U_0402_6.3V6K
2

(1.8V@20mA TSVDD) 1 RV203 1 2 TOPAZ@


RV42 0 1 1.0 0_0402_5%
10K_0402_5% AMD R16M-M1-30
EXO@ 2
EXO@ For Topaz, RV16/RV19 stuff 100ohm 1 0 0.9
PX@

for EXO, RV16/RV19 stuff 0hm.


1

2
1 1 0.8
RV205 RV204 RV209
10K_0402_5% 10K_0402_5% 10K_0402_5%
Connect GPIO_28 to 10K pull @ PX@ @
down to enable MLPS.

1
GPU_SVD
GPU_SVC
GPU_SVT
RV242 2 @ 1 0_0402_5% WRST# {35}

2
2
RV206 RV210
RV243 2 @ 1 0_0402_5% 10K_0402_5% RV207 10K_0402_5%
APU_SHUTDOWN# {7}
PX@ 10K_0402_5% @
@

1
1
1
C

@ QV13
GPU_RST# 1 2 DV2 RV135 1 @ 2 0_0402_5% RV128 1 @ 2 2 B LMBT3904WT1G_SOT323-3 Internal VGA Thermal Sensor 
{15} GPU_RST#
2.2K_0402_5%
SDM10U45LP-7_DFN1006-2-2
1

+3VGS
CV215 0.1U_0201_6.3V6-K

1 @
RV131 +3VGS
3

GPIO_19_CTF 1 @ 2 RV132 1K_0402_5%


47K_0402_5% @
1

2
@

A