Journal of Alloys and Compounds 814 (2020) 152185

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Journal of Alloys and Compounds

journal homepage: http://www.elsevier.com/locate/jalcom

Deep trap states relaxation in CaCu3Ti4O12

X.J. Luo a, *, S. Yang a, X.R. Su a, Y.Y. Zhu a, Y. Wang a, S.L. Tang b, C.P. Yang c, Y.S. Liu a, **,
K. Ba€rner d
a
Shanghai Key Laboratory of Materials Protection and Advanced Materials in Electric Power, Shanghai, 200090, PR China
b
Nanjing National Laboratory of Microstructures, Jiangsu Provincial Laboratory for Nanotechnology and Department of Physics, Nanjing University,
Nanjing, 210093, People's Republic of China
c
Faculty of Physics and Electronic Technology, Hubei University, Wuhan, 430062, PR China
d €ttingen, F. Hund Platz 1, 37077, Germany
University of Go

a r t i c l e i n f o a b s t r a c t

Article history: The abnormal dielectric behaviors of the perovskite oxide CaCu3Ti4O12 (CCTO) ceramics were discussed.
Received 29 April 2019 The hysteretic dc current e voltage (IeV) curves that change hysteresis degree with voltage sweeping
Received in revised form rate suggest that there is a slow trap charge transfer process between deep trap sites, which at the same
4 September 2019
time involve a defect dipole movement, leading to hysteretic capacitance vs. dc voltage (CeV) curve that
Accepted 5 September 2019
also change hysteresis degree with voltage sweeping rate. Then, the polarization of the defect dipoles in
Available online 6 September 2019
the deep trap sites is further proved by the frequency dependent CeV relation as well as capacitance-
time (C-t) relation. At last, the dynamic processes for the trap charge transfer and the corresponding
Keywords:
Hysteresis
defect dipoles polarization in a specific boundary was provided. The model suggests that the permittivity
CeV (or capacitance) is dependent on the number of trap charges participating the transfer process, which
Deep traps was confined by the energy levels of trap sites.
Defect dipole © 2019 Elsevier B.V. All rights reserved.

1. Introduction
The perovskite-related material CaCu3Ti4O12 (CCTO) is a typical
colossal dielectric constant (up to105) material with good temper-
ature stability in a range of 100e300 K and good frequency stability
in a range of 102e106 Hz [1]. Such properties make it potential for
the miniaturization of electronic capacitor components. Besides the
good dielectric properties, CCTO has a remarkably nonlinear coef-
ficient of more than 900, which can be used as the varistor for the
surge protector [2]. The excellent characteristics has aroused wide
interest for researchers in recent years [3e10]. People always think,
why CCTO has so large permittivity and nonlinear coefficient? Why
the permittivity could keep stable within a wide temperature or
frequency range? Researchers try to find kinds of evidences to
disclose the mechanisms, but they always could not reach a
unanimous conclusion. There are two basic experimental facts that:
first, CCTO is not a ferroelectric but with a stable centrosymmetric
crystal structure persisting down to 35 K [1]. Second, the
* Corresponding author.
** Corresponding author.
E-mail addresses: xiaojing_luo@163.com (X.J. Luo), ysliu@shiep.edu.cn (Y.S. Liu).
impedance spectra and the Kelvin probe force microscopy mea-
surements of currentevoltage character show that the grains are n-
type semiconducting, and the grain boundaries are insulating [2].
Thus, the extrinsic relaxation mechanisms such as the barrier layer
capacitor (BLC) which based on the spatial inhomogeneity distri-
bution are widely accepted as the dielectric origin [3,11e18].
However, the BLC model could not explain the abnormal dielectric
behaviors, for example, the sharply decrease of permittivity below
100 K, the middle temperature permittivity plateau, the capaci-
tance peaks at high temperature [19e21] or in CeV curves [22,23].
Then, what should be our next concerns to discover the abnormal
dielectric behaviors? We know that though the colossal permit-
tivity in CCTO had been found for near 20 years, the high dielectric
loss factor (>0.1) always limit its application. Many attempts have
been made to reduce the dielectric loss, but at the same time the
dielectric constant decreased [24e29]. The reason may be that the
polarization process of CCTO is always accompanied by a strong
leaky conduction [30], which may be related to the oxygen vacancy
related defects, as the dielectric behavior in CCTO is very sensitive
to sintering atmospheres in the preparation process. Therefore, we
should consider the polarization and conduction behaviors of de-
fects in CCTO.
The defects are very common in the dielectric layer of the device

https://doi.org/10.1016/j.jallcom.2019.152185
0925-8388/© 2019 Elsevier B.V. All rights reserved.
2 X.J. Luo et al. / Journal of Alloys and Compounds 814 (2020) 152185
that can highly influence the transport behaviors of the related
devices, as defects can manifest as deep trap states that participate
in the charge trapping and limit the electron mobility efficiency.
According to kinds of characterization methods, there are many
papers reports that the CCTO ceramic is a defective material with
vacancies or acceptor and donor ions impurities. However, very few
people analyze the roles of these defects to the dielectric or electric
transport properties. In this work, we try to analyze the dielectric or
electric behaviors from the angle of defects, especially the trap
defects. On one hand, the defects in the boundaries may introduce a
Schottky barrier, contributing to barrier layer capacitance. On the
other hand, the defects may influence the conduction behavior or
the nonlinear characteristic. Especially, if the conduction of the
defects may involve the defect dipole moment [31e35], the defects
can contribute to the polarization, too. In this way, we can simul-
taneously explain the large permittivity and high leaky conduction
in CCTO.
2. Experiments
CCTO ceramics were synthesized by traditional solid-state re-
action method using analytically pure raw materials of CaCO3
(99.99%), CuO (99%), and TiO2 (99.5%). The materials were weighed
according to the stoichiometric ratios and mixed thoroughly. The
mixed power was first presintered at 900
C for 10 h and then
pressed into disks and sintered at 1000
C for 12 h. At last, the disks
were reground again and then pressed into disks with a diameter of
1 cm for the last sintering at 1100
C for 24 h. Silver paste were
coated on both sides of the disks and sintered at 580
C for 10 min
as electrodes. The dielectric response and the capacitance e dc
voltage (CeV) character were measured using a WK6500 (Taiwan,
China) impedance analyzer together with a Janis closed-cycle-
refrigerator. The cycling current e dc voltage character (IeV) was
measured by an electrometer Keithley 2400 with a computer-
controlled program. The X-Ray diffraction patterns and scanning
electron microscope images of the three samples were shown in
our previous work [36].
3. Results
3.1. The hysteresis behaviors in CCTO
In the experiments we found that both the electric transport and
dielectric behaviors will show hysteresis at some conditions. In the
dc electric transport measurement, if we sweep the voltage in the
way of 0 / þVmax / 0 / -Vmax / 0 of dc bias, the
currentevoltage (IeV) curve show a strong hysteresis when the
voltage sweeping rate is 4.2 V/s. However, if we slow down the
voltage sweeping rate to 0.42 V/s, the hysteresis almost disappears,
as shown in Fig. 1, which is taken at a low temperature 150 K. At
150 K, we need a large maximum voltage Vmax ¼ 200 V and a high
voltage sweeping rate to get the hysteresis. However, at a higher
temperature such as 420 K, we only need a lower Vmax ¼ 20 V to get
the hysteresis. In addition, if we sweep the voltage continuously for
several cycles, the non-linear IeV curve can gradually become near
linear under numbers of voltage cycles [37], suggesting a slow
cutting down of boundary barrier according to the charge carriers
release or capture from the trap sites. As to the reason for the
hysteresis which is easier to occur at high temperatures or higher
voltage sweeping rate, we think the high temperature is favorable
to the thermal activation of carriers from deep trap sites. The high
voltage sweeping rate actually suggests a change of dc voltage at a
low frequency.
The hysteresis can also happen in the capacitance e dc voltage
(CeV) relation, in which the line shape also depends on the test
temperature, electric field and voltage sweeping rate. When we
sweep the dc bias circularly from -V / 0 / þVmax/ 0/ -Vmax/
0 at a voltage sweeping rate of 0.2 V/s, as shown in Fig. 2(a), the CeV
curve at 420 K and 1 kHz show an obvious hysteresis and the
capacitance rises with increasing dc bias. However, if we decrease
the voltage sweeping rate to 0.05 V/s, as shown in Fig. 2(b), the
hysteresis disappears and the capacitance still rises with increasing
dc bias. If we decrease the temperature to 250 K, as shown in
Fig. 2(c), at 1 kHz, whenever the voltage sweeping rate is 0.05 V/s or
0.25 V/s, we could not observe the hysteresis. But unlike the rise of
capacitance at 420 K, we only see the capacitance decreases with
increasing dc bias at 250 K. However, our additional experiments
found that, also with the voltage sweeping rate 0.05 V/s, if we
decrease the measuring frequency to 20 Hz, we can also see a
capacitance rise at 250 K.
The presence of hysteresis in CeV curve is always considered as
an indicator of interface defect traps. Researchers have used the
hysteresis in CeV to estimate the defect density in dielectrics,
where the magnitude of hysteresis is proportional to the defect
density [38e44]. The hysteresis appear in Figs. 1 and 2 seems have
common characteristics: all of them appear easily at high temper-
ature, high electric field and high voltage sweeping rate, suggesting
a thermal or electric field activated carriers from deep trap sites.
The hysteresis in Fig. 1 is contributed by the charge transfer be-
tween deep trap sites, while the hysteresis in Fig. 2 is contributed
by the polarization of trap charges from deep trap sites. That is, the
trap charges transfer between deep trap sites simultaneously
contribute to the conduction and polarization. As to the way of the
trap charge polarization, we think the carriers trapping may
introduce a misalignment of the positive and negative charge
centers in trap sites, forming defect dipoles and leading to the
polarization of the crystal matrix. In our previous work, we called
this process the trap charge repositioning process [30]. The detailed
image of the formation of defect dipole could be seen in Fig. 8 in
discussion section.
The hysteresis can also appear in the polarization e electric field
(P-E) curves, which had already found by several researchers. In our
experiment, we reproduced the P-E loops again in Fig. 3. There are
obvious ferroelectric-like P-E loops but could not achieve satura-
tion with increasing electric field. The maximum polarization in-
tensity increases when we increase the maximum voltage.
However, unlike others, we mainly see a large positive remnant
polarization intensity. The negative remnant polarization intensity
Fig. 1. IeV curves measured at 150 K at different voltage sweeping rate.
 X.J. Luo et al. / Journal of Alloys and Compounds 814 (2020) 152185 3

Fig. 2. The CeV curves at (a) 420 K with voltage sweeping rate of 0.2 V/s, (b) 420 K voltage sweeping rate of 0.05 V/s and (c) 250 K voltage sweeping rate of 0.05 V/s and 0.25 V/s.

is very small in the negative voltage load. Therefore, it is different

from the switching of the spontaneous polarization of dipoles in
ferroelectrics, but it is the polarization behavior of defect dipoles.
The hysteresis is similar to the hysteresis appears in CeV curves
that the polarization is mainly contributed by the deep trap dipoles
which are pinned in the external filed. Due to the slow relaxation
time of the deep trap defects, the defect dipoles could not timely
orientate under the opposite electric filed, we can only see a pos-
itive polarization intensity dominate in the negative electric field.

3.2. The frequency dependent CeV relation

Another method to verify the trap charges related conduction

and polarization is the investigation of frequency dependent CeV
relation. The interface traps can modify the CeV curves of the
studied structures, which represent as the stretch-out or a voltage
shift of the curves with the measuring frequency [39,45e48]. The
reason may be that, during the CeV sweep, the interface traps with
corresponding time constant will respond to the ac signal at a
certain frequency, while these traps will contribute to the
measured capacitance, leading to a frequency dispersion in CeV
curves due to the different time constants of traps [48]. In order
to analyze the relation between polarization and conduction, in
Fig. 4 we plotted CeV curves and dielectric loss tand-V curves
together, as the ac conductivity is proportional to the dielectric loss
factor tand. In Fig. 4(a), we see that both the capacitance and
dielectric loss increase with dc bias at 100 Hz, indicating that the
polarization is built in the carriers’ electric transport process. When
Fig. 3. The P-E loops measured under different maximum electric field.
we increase the frequency to 1 kHz ((Fig. 4(b)), the capacitance rises
(the first rise) transitorily as the applied dc bias increase from
negative bias -3 V to about 1 V, and then quickly decreases with the
further increase of dc bias. After a minimum capacitance, the
capacitance begins to rise again (the second rise) at a higher applied
bias. The CeV also shown a hysteresis under the circularly
sweeping of dc bias from -V / 0 / þVmax/ 0/ -Vmax/ 0.
However, at 1 kHz, the loss factor still increases monotonically with
dc bias, without any decrease. When we increase the frequency to
10 kHz, as shown in Fig. 4 (c), the second rise of capacitance
4 X.J. Luo et al. / Journal of Alloys and Compounds 814 (2020) 152185
disappears, only the first rise exists, which followed by a capaci-
tance decrease with the further increase of dc bias. At this time, the
loss factor shows a small step from 1 V/ 4 V and the line shape of
the tand-V is like the line shape of CeV curve at 1 kHz shown in
Fig. 4 (b). It seems that, the change of conductivity falls behind the
change of capacitance at middle frequency. If we increase the fre-
quency to 1 MHz, the line shapes of the CeV and tand-V are the
same, as shown in Fig. 4 (d), after the first rise, both of them
decrease with dc voltages. According to the comparative analysis of
the line shape evolution with frequencies for both CeV and tand-V
curves, we see that both the polarization and conduction is
confined by the relaxation time of trap charges.
Hu et al. also observed a capacitance rise with dc bias in their
perovskite solar cell device. In addition, they found the capacitance
peak increases and moves to a higher dc bias with increasing light
illumination time [41]. They think the accumulation of photo-
generated charge carriers at electrode interfaces lead to the
increased capacitance with the applied bias [41]. After the capaci-
tance peak, the charge injection and recombination at higher
applied bias can occur, leading to a capacitance decrease [41]. In our
case, we think the external field will activate the trap charges,
which accumulate at the interface and lead to the capacitance rise.
The first rise of capacitance within 0e1 V seems independent on
frequencies, as it appears both at 100 Hz and 1 MHz. In addition, it
always accompanied by a rise of dielectric loss factor in the same dc
bias range. We think it originate from the polarization of defect
dipole from shallow trap sites, which response fast under the
electric filed. The second rise of capacitance can only be observed at
a higher dc voltage and a low frequency, and is also accompanied by
Fig. 4. The CeV curves for the sample sintered at vacuum at (a) 100 Hz, (b) 1 kHz, (c) 10 kHz and (d) 1 MHz.
a strong conductivity rise. We think it is due to the polarization of
defect dipoles with longer relaxation time from deep trap sites.
Yang's group found that the hysteresis occurs easily for the sample
sintered under vacuum atmosphere [49], suggesting that the defect
dipoles may come from the oxygen vacancy related deep trap sites.
We should mention that both the capacitance rise should not
come from the back to back Schottky barrier layer capacitance,
which firstly shows a decrease once the external field is applied [3].
Note that at low frequencies, for example, at 100 Hz in Fig. 4 (a),
both capacitance and loss factor increase monotonously with
increasing dc bias. Here, there may be a superposition of the first
and the second rises of capacitance. This suggests that only at low
frequencies, the deep trap charges with long relaxation time acti-
vated at higher dc bias can timely supplement their contribution to
capacitance and conductance. Therefore, we think only at higher
frequencies, we can observe the barrier layer capacitance which
decrease with increasing dc bias. As there is a depletion of shallow
trap sites and a cease working of deep trap charges.
3.3. The abnormal relaxation processes after electrical conditioning
The two relaxation processes (the two rises of capacitance)
observed in CeV curves could also reappear in the capacitance e
time (C-t) curves after the electrical conditioning. The electric
conditioning means (EC) that, let the sample undergo cycling dc
voltage sweeping in the way of 0 / þVmax / 0 / -Vmax and at
the same time monitor the change of current [37,50]. Under EC, the
initial non-linear current e voltage (IeV) curves of CCTO will
gradually become near linear, suggesting a decrease or even
 X.J. Luo et al. / Journal of Alloys and Compounds 814 (2020) 152185 5

disappearance of the boundary barrier. Then, we remove the dc

voltage immediately (operation time 3 s), and measure the
response of capacitance with recovery time at different experi-
mental parameters. Fig. 5 shows the response of capacitance
(Fig. 5(a)) and conductivity (Fig. 5(b)) with recovery time at
different temperatures. We see that at 420 K, the capacitance firstly
shows a peak (peak 1) and then recover to a capacitance plateau
(plateau 1), while the conductivity gradually recovers to its normal
state. At lower temperature such as 250 K, peak 1 and plateau 1 also
appear. However, after plateau 1, the capacitance gradually de-
creases to another lower plateau 2. if we increase the ac signal
frequencies, as shown in Fig. 6(a) and (b), peak 1 gradually disap-
pears both at 250 K and 420 K. However, at 250 K, at higher fre-
quencies such as 80 kHz and 100 kHz, the capacitance peak 2 comes
out, which followed by the plateau 2.
In our previous work, we had successfully explained the
capacitance peak by the model of trap charge repositioning be-
tween different trap sites [37]. We think the capacitance peak may
represent the largest occupation imbalance of defect dipoles at the
interface after the trap charge repositioning under the electric filed,
which is metastable that can only survive for a while. Two capac-
itance peaks suggest that the dynamic relaxation processes occur at
two different locations, or between trap sites with two different
energy levels. While two capacitance plateaus may represent two
polarization balance of related trap charges after the dynamic
relaxation processes. In addition, from Figs. 5 and 6 we can obtain
more information: 1) peak 1 disappears at high frequencies, sug-
gesting that it comes from the polarization of deep trap charges;
peak 2 can be observed clearly at low temperatures and can survive
at high frequencies, suggesting that it comes from the polarization
of shallow trap charges. 2) The height of plateau 1 decreases with
increasing frequencies, see Fig. 6 (a), but the height of plateau 2
show litter changes with frequencies, see Fig. 6(b). Thus, we deduce
that plateau 1 represent the polarization balance state of the deep Fig. 6. The time dependent capacitance at different frequencies after electric condi-
tioning, with (a) 420 K and (b) 250 K.
trap charges, which can keep a long time at high temperatures such
as 420 K, while plateau 2 may represent the polarization balance
state of the shallow trap charges that can appear at lower tem- the charges from deep trap sites even at low temperatures, the
peratures such as 250 K. 3) As the EC process may activate almost all height of plateaus 1 are almost at the same capacitance scale and
independent on the temperature change. However, the height of
plateaus 2 are different when we change temperatures, suggests
that there are different numbers of shallow trap charges partici-
pating in the polarization at different temperatures.
Actually, according to the characteristics shown in the capaci-
tance vs. temperature curves, we can further understand the two
polarization balance states represented as platforms 1 and 2. As
shown in Fig. 7, there is a broad capacitance plateau within a lower
temperature range of 100 Ke200 K and a short capacitance plateau
within a lower temperature range of 250 Ke280 K, which are cor-
responding to the polarization balance state of the shallow trap
charges and deep trap charges, respectively. Before the capacitance
plateaus, there are two sharp rises of capacitance in a lower tem-
peratures range of 53 Ke100 K and a higher temperatures range of
200 Ke230 K, respectively. The capacitance rise in the lower tem-
perature range may be due to the dynamic relaxation of shallow
trap charges, while the capacitance rise at the higher temperature
may be due to the dynamic relaxation of deep trap charges.
Correspondingly, the two relaxation processes show two loss factor
peaks at 53 K and 230 K, respectively.

4. Discussion

4.1. The different trap levels in CCTO

Fig. 5. The time dependent dielectric response of (a) capacitance and (b) ac conduc-
tivity after electric conditioning at different temperatures. By visible light absorption analysis, Rosseinsky el al found two
6 X.J. Luo et al. / Journal of Alloys and Compounds 814 (2020) 152185
gaps of 2.21 and 1.39 eV in the visible region in sol-gel synthesized
CCTO. The results were analyzed combining with the LSDA þ U
electronic structure calculations. They think there is a localized
unoccupied narrow Cu 3d band located within the gap [51],
creating localized states which can trap electrons and facilitate
recombination. This narrow band also facilitate the oxidization and
reduction of transition metal ions Ti4þ and Cu2þ. Tsuji et al.
observed three peaks from 100 to 350 K in charge-based deep level
transition spectroscopy (DLTS), and the corresponding trap energy
is 0.15, 0.79, and 0.66eV [52]. In our work, by the Arrhenius fitting of
the relaxation peaks in Fig. 7 at different frequencies, we got an
activation energy of about 0.07e0.09 eV from the low temperature
peaks (at about 60 K) and of 0.6 eV from the higher temperature
peaks (about 250 K), respectively. We think 0.07e0.09 eV is corre-
sponding to the activation energy of charges from shallow trap
sites, and 0.6 eV is corresponding to the activation energy of
charges from the deep trap sites. However, what may these trap
sites be? In our previous work we found that both conductivity and
permittivity of CCTO is sensitive to the oxygen content. Particularly,
the sample sintered under vacuum has the largest permittivity and
conductivity. Thus, the trap sites might come from oxygen vacancy
related defects. When the ceramics were sintered in the oxygen
deficient sintering atmosphere, the acceptor ions Cu1þ and Ti3þ in
ceramics may generate [53,54], which was compensated by oxygen
vacancies and form metal-oxygen vacancy defect complexes like,
 0  
ðCuCu 0  V 
o Þ or ðTiTi  V o Þ (with a dot representing a positive
charge and a single quote representing a negative charge) [33,35].
These defect complexes may capture electrons or as a recombina-
tion center. The charge transfer between these defect complexes
may create the polaron electronic transport, at the same time, the
trapping of carriers may introduce a misalignment of the positive
and negative charge centers of the defect complex, forming defect
dipoles as shown in Fig. 8(c). On one hand, the charge hopping
between defect complexes lead to the conduction; on the other
hand, the charge transfer between different trap sites may be
accompanied by the movement of the defect dipoles, introducing a
large polarization [30,37]. Different defect complexes may form
trap sites with different energies for charge carriers. The same
defect complex at different locations may also introduce different
trap energy levels in the crystal.
4.2. Repositioning dynamics for the defect complexes
The trap charge repositioning between defect complexes could
Fig. 7. The temperature dependence of capacitance and loss factor of CCTO at 20 Hz.
happen when the energy states of the charge carriers changed
under external field or the thermal enviroment. In our previous
work we had provided the detailed modle for the trap charge
repositioning between different defect trap sites [55]. Here we add
the detailed dynamic processes for the trap charge repositioning in
a specific boundary. The Kelvin probe of the IeV curves for the
single grain or grain boudary suggests that the grains are n-type
and the boundaries are insulating [2]. As the defect complexes
mainly inhabited in the boundaries will absorb the carriers from
the n-type grains, introducing two back to back space charge layer
(on A and B sides) with two inverse internal fields Ei , froming a
Schottky barrier layer in the center of the boundary. Thus, there will
be a barrier layer capaciatance provided here. But besides the
barrier layer capacitance, we should consider the polarization of
defect dipoles. Fig. 8(c) shows the detailed image of the formation
of a defect dipole. In Fig. 8 (a) and (b), the peak like lines show the
height of barriers, and the ellipsis show the defect dipoles.
Compared with the fixed Schottky barrier model, the defect dipoles
are not fixed but can move to other locations according to trap
carriers repositioning under the action of an external field E0 . As
shown in Fig. 8(a), under zero electric field, as the aborption of the
carriers from the bulk is equal, the numbers of defect dipoles with
opposite orientations on A side and B side respectively are also
equal. Therefore, both the boundary perpendicular to the external
field (“fs” boundary) and the boundary parallel to the external field
(“fp” boundary) show a zero polarization. If we apply an dc bias as
shown in Fig. 8(b), the external field will adjust the width of the
space charge layers on A side and B side differently. As shown in
Fig. 8(b), the potential will increase on the A side of “fs” boundary,
and on the both sides of “fp” boundary. Thus, the charges on the A
side of the “fs” boundary and the B side of the “fp” boundary will
hop to the B side of the “fs” boundary. Then, due to the advantage of
the charge carrier's occupation on the B side of the “fs” boundary,
there will be a large imbalanced occupation of the defect dipoles in
“fs” boundary, which will make a large polarization in the “fs”
boundary.
The situation is similar to the thermion's relaxation polarization.
When the charged particles in a weak bound of the matrix migrate
directionally under the external filed, it will cause a remnant of the
charged particles in a local region of the crystal matrix. If the
remnant charges lead to an asymmetry of the positive and negative
charge centers, the electric moments form and the matrix is
polarized. The charged particles always come from the defects that
can be easily activated by the thermal environment or electric filed.
In CCTO, the charge carriers may be activated from the oxygen
vacancy related defect complex. The dynamic repositioning process
allows us to calculate the reversible temperature and field depen-
dent excess of the defect dipoles under the assumption that there
are always enough complexes available, NC [N, with NC the con-
centration of defect complexes, and N the concentration of hopping
carriers. For a three-dimensional space the number is N/3 for each
dimension. Considering the charge carriers hopping at “fs”
boundary, before the hopping, the number of carriers both at A and
B sides are N/6. When the thermal motion energy is larger than the
barrier layer height fb , for the nearest hopping the carriers can get
over the barrier and hop from A side to B side or vice versa. A and B
sides are two equilibrium position under zero external field.
Assuming that the hopping frequency is n, the charges that hop
from A to B side and from B to A side are equal [56]:
N fb =kT
NBA ¼ NAB ¼ ne (1)
6
If we add an external filed with and electric energy Df, as shown
in Fig. 8(b). The barrier height from A to B is fb  Df, and from B to
 X.J. Luo et al. / Journal of Alloys and Compounds 814 (2020) 152185 7

Fig. 8. The schematic diagram for the trap charge repositioning (TCR) process in the back to back np junctions, with (a) the external field E0 ¼ 0 and (b) the external field E0 s
0 [45].(c) shows the schematic diagram of the formation of a defect dipole.

 
Ea
A is fb þ Df, then the charge transition rate from A to B side is N0 exp  kT , with N0 the initial numbers of carriers and Ea the
activation energy. We get,
gAB ¼ neðfb DfÞ=kT (2a)  
Ea 2
N0 exp  kT q2 d
which is larger than that of from B to A side:
ε0 ¼ þ1 (9)
12kTε0
ðfb þDfÞ=kT
gBA ¼ ne (2b)
Assuming the hopping distance d is a constant, which may only
Under electric field, if the number of the hopping carriers is DN, depend on the location of trap sites in a localized region that almost
then at A side the carrier number is reduced to N6  DN, and at B do not change once created under a high temperature sintering
sides is increased to N6 þ DN. We can get the dipole moment per unit process. Then the permittivity will sharp rise with temperature,
volume caused by the residual hopping carriers (or the defect di- which shown as the temperature regions 53 Ke100 K and
poles as a result of carrier trapping): 200 Ke230 K in Fig. 7.
After the thermal activation of the charge carriers, there is a
PT ¼ DNqd (3) stable charge carrier reserve region. Then, the number N of the
carriers ionized from the defects should be near constant or show
Where q is the charge of the hopping carrier and d is the hopping small change with temperature. Assuming that, N ¼ bT; ð0 < b < 1Þ,
distance between A and B sides. In the steady state, the charge we can get:
distribution reach to balance and no longer change, we get [56]:
    bq2 d2
N N ε0 ¼ þ1 (10)
 DN neðfb DfÞ=kT ¼ þ DN neðfb þDfÞ=kT (4) 12kε0
6 6
Then the permittivity will keep constant with temperature,
Then, which shown as the temperature regions 100 Ke200 K and
  250 Ke280 K in Fig. 7.
N eDf=kT  eDfb =kT We see that the permittivity is dependent on the number of trap
DN ¼
(5) charges activated. According to eq. (8) we can explain the capaci-
6 eDf=kT þ eDfb =kT
tance rises and plateaus in Fig. 7. However, when the temperature is
Then the polarization intensity is [56], constant, the polarization of defect dipoles is more dependent on
  the frequencies of the ac signal due to the slow relaxation of deep
Nqd eDf=kT  eDfb =kT traps, as shown in Figs. 4 and 6. Of cause the external field will
PT ¼ DNqd ¼
(6) change the space barrier layer height for charge transfer, especially
6 eDf=kT þ eDfb =kT at the interface between the surface and electrode where there is a
If the external field applied on each grain boundary is weak, and large load voltage. In addition, as the capture is always faster than
the electric energy fulfilsDf≪kT, then e±Df=kT z1±Df=kT. As Df ¼ the slow release process charges from deep trap sites, though the
1 qdE , the polarization intensity can be write as [56]: external field change signs, the Schottky barrier height in fs
2 0
boundary can gradually decrease under EC. The capture of carriers
Nqd will make the number of defect dipoles at B sides much larger than
PT ¼ DNqd ¼ E (7) that at A side, and then the capacitance will slowly rise. Then, if
12kT 0
there are more EC cycles followed, the empty trap sites on A side is
As PT ¼ ε0 ðε0  1ÞE0 , with ε0 the permittivity of vacuum, ε0 the also gradually occupied, and then the occupation imbalance will
permittivity obtained from the polarization, we get, gradually decrease. At that time, we could not observe the defect
2
dipole polarization any more, only the barrier layer polarization
Nq2 d
ε0 ¼ þ1 (8) left.
12kTε0
At low temperature, N ¼ 0 and ε' ¼ 1. 5. Conclusion
In the thermal activation of carriers from trap defects, the charge
carriers may increase exponentially with temperature. If N ¼ In summary, according to the investigation of the hysteresis
8 X.J. Luo et al. / Journal of Alloys and Compounds 814 (2020) 152185
behaviors appear in the conduction and polarization processes, and
the frequency dependent CeV relation, as well as the time response
of capacitance and conduction after the electric conditioning, we
think the conduction and polarization in CCTO ceramics are related
to the deep traps at the interface. The trap charge transfer (or
repositioning) between trap sites under electric field may cause a
hopping conduction, which at the same time involve dipole
movements and form defect dipoles, contributing to the polariza-
tion. As the charge transfer between deep trap sites is slow, we can
observe hysteretic IeV and CeV curves, as well as the frequency
dependent CeV and C-t relations. The thermal activation of these
trap sites may cause the fast rise of permittivity with temperature,
while the charge localization in the trap sites with a certain energy
level may cause the permittivity plateaus in the permittivity -
temperature curves. In conclusion, we think the trap charge repo-
sitioning between trap defect complexes is the key factor for the
high conduction and high dielectric loss in CCTO, as well as the
abnormal dielectric behaviors. Thus, it is always hard to increase
the dielectric constant significantly and at the same time decrease
the dielectric loss.
Acknowledgments
This work is supported by the National Natural Science Foun-
dation of China (Grant Nos. 11504227, 51672172, 51502168,
11674215), and the project of the Science & Technology Committee
of Shanghai Municipality (No. 19020501000).
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