VLSI Online courses demand has quadrupled

To be exact, last week I received 88 messages on Udemy and 76 messages on Linkedin asking for
discount coupons. I was wondering, why suddenly there’s such a huge demand for my VLSI online
courses. I have been trying to delay generating discount coupons, as it’s a process, which takes around
2-hrs of working time. But I just can’t ignore so many messages, so here’s generating the maximum
(90%) discounted coupons for all my online courses.

All my courses have lifetime access and 30-day’s refund policies. If you have decided to master VLSI,
then buy them all in bulk TODAY itself. If you like them and think it will be useful, then keep it. If you
don’t like them, you can ask for refund within 30-days. No questions asked. This way, you can help me
save a lot of time from generating coupons. “Time is money”

Anyone looking forward for VLSI online courses, please don’t hesitate to forward this email

Below are keywords, which you want to learn, and their respective coupon links:

Keywords – skew, pulse-width, latency, clock power, clock buffer vs regular buffer, leakage and short
circuit current, clock gating

Clock tree synthesis – Part 1 & 2:

https://www.udemy.com/course/vlsi-academy-clock-tree-
synthesis/?couponCode=863A0D887203405CB2A7

https://www.udemy.com/course/vlsi-academy-clock-tree-synthesis-
part2/?couponCode=6AC1EBB0374BA53028EF

Keywords – lateral capacitance, noise margin, crosstalk, safe/unsafe glitch, aggressor, victim, ac noise
margin, timing window, shielding, power supply noise, voltage droop, ground bounce

Signal integrity:

https://www.udemy.com/course/vlsi-academy-crosstalk/?couponCode=D594928C69CF295266CA

Keywords – Floorplanning, placement optimization, utilization factor, aspect ratio, decoupling capacitor,
pre-layout and post-layout timing analysis, multiple clock timing analysis, Maze lee’s routing algorithm,
IEEE SPEF format

Physical design:

https://www.udemy.com/course/vlsi-academy-physical-design-
flow/?couponCode=E2C87EF0413EAD778688
Physical design webinar:

https://www.udemy.com/course/vlsi-academy-physical-design-
flow/?couponCode=E2C87EF0413EAD778688

Keywords – PMOS, NMOS, SPICE simulations, Vt, drift current, pinch-off region, resistive operation,
technology parameters, CMOS VTC, noise margin derivation, power supply variation, on-chip variation
(OCV)

Circuit design and SPICE simulations – Part 1 & 2:

https://www.udemy.com/course/vlsi-academy-circuit-design/?couponCode=174C1DF748FE0413AABB

https://www.udemy.com/course/vlsi-academy-circuit-design-
part2/?couponCode=4033BE78166BCCFF8D6D

Keywords – add_buffer, size_cell, Vt-swap, DRV, setup & hold fixing strategies, PBA, latch timing, jitter,
CPPR, reg2reg analysis, interface analysis, clock-gating analysis, ICG, asynchronous checks

STA part 1 & 2:

https://www.udemy.com/course/vlsi-academy-sta-checks/?couponCode=5DB8A80E17D243BF2D52

https://www.udemy.com/course/vlsi-academy-sta-checks-2/?couponCode=20C008D7F7DF831589B3

STA webinar:

https://www.udemy.com/course/vsd-static-timing-analysis-sta-
webinar/?couponCode=3BE47EB6CC71DB06A203

Timing ECO:

https://www.udemy.com/course/vsd-timing-eco-engineering-change-order-
webinar/?couponCode=EED765FC059B7DA508B3

Keywords – n-well, p-well, source, gate, drain formation, poly, stick-diagram, layout, drc rules,
propagation delay, CCS-Timing, NLDM, ECSM, library setup/hold time, CCS-Noise, power
characterization

Custom layout:

https://www.udemy.com/course/vlsi-academy-custom-layout/?couponCode=40AE01C5A7F20EF517F2

Library characterization:

https://www.udemy.com/course/vlsi-academy-library-characterization-part-
1/?couponCode=FAD625034B06AFFDDD69
Keywords – tcl programming, eda, cad, variables, matrix, error handling, set_multi_cpu_usage

TCL Programming – Part 1 & 2:

https://www.udemy.com/course/vsd-tcl-programming-from-novice-to-
expert/?couponCode=837920D9401E4C27C841

https://www.udemy.com/course/vsd-tcl-programming-from-novice-to-expert-part-
2/?couponCode=150B1357263B4C3C122D

Keywords – RISCV, signed/unsigned, ABI, doublewords, overflow, RV64IM, IEE754 floating point, pads,
memory mapping, pipelining, SoC design, physical design implementation

RISCV- ISA – Part 1a & 1b:

https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-
1a/?couponCode=BC585DADFD2A3A35954A

https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-
1b/?couponCode=FCACAF23F2F2450A0E7A

Pipelining RISC-V using TL-verilog:

https://www.udemy.com/course/vsd-pipelining-risc-v-with-transaction-level-
verilog/?couponCode=E0302531D99078417919

RISC-V SoC Design:

https://www.udemy.com/course/vsd-making-the-raven-chip-how-to-design-a-risc-v-
soc/?couponCode=BCD3F79510D38C92DEA9

RISC-V SoC Implementation:

https://www.udemy.com/course/vsd-soc-design-of-the-picorv32-riscv-micro-
processor/?couponCode=8155DA9348580CB7065D

Keywords – functional simulation, moore’s law, emulation, multi-core, multi-threading, hardware

accelerators, avst_keccak, machine intelligence, regression model, wire error model, WiCE labs, binary
classification

Embedded UVM:

https://www.udemy.com/course/vsd-embedded-uvm/?couponCode=3605184013B6FF98BD8F

Functional Verification using E-UVM – Part 1:

https://www.udemy.com/course/functional-verification-using-embedded-uvm-part-
1/?couponCode=47F7344FEC41DDC99D94
Machine Intelligence in EDA/CAD:

https://www.udemy.com/course/vsd-machine-intelligence-in-eda-
cad/?couponCode=48553AB4FDC2B2AF1D93