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0.1 Bipolar Junction Transistor

0.1.1 Symbol and notation
We denote the Bipolar Junction Transistors in electronic schematics using the following symbols:

(C) (E) (C) (E) TERMINALS:

C: Collector

E: Emitter
(B) (B)
B: Base
NPN PNP
The arrow in the symbol denotes the emitter terminal E and is oriented:
• outward for NPN devices
• inward for PNP devices

0.1.2 Ebers Moll DC model

We use the following sign convention for both NPN and PNP devices:

VCE VCE
IC (C) (E) IE IC (C) (E) IE

VBC (B)
VBE VBC (B)
VBE

IB IB
NPN PNP

With this sign conventions we have the following DC model:

NPN - Ebers Moll model

  
IF = I0,F exp VT



VBE

−1
 13 αR IR αF IF
   
 VBC
IR = I0,R exp −1


VT

With:
IE IC
• I0,F , I0,R : saturation currents (K) (A) (A) (K)

(E) (C)
• VT : thermal voltage
IF IR
( (B)
IE = −IF + αR IR VBE VBC
IB
IC = −IR + αF IF

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 PNP - Ebers Moll model




 
VBE
IF = I0,F exp − VT

−1
 13 αR IR αF IF
   
 VBC
IR = I0,R exp − −1


VT

With:
IE IC
• I0,F , I0,R : saturation currents (A) (K) (K) (A)

(E) (C)
• VT : thermal voltage
IF IR
( (B)
IE = IF − αR IR VBE VBC
IB
IC = IR − αF IF

The parameters I0,F ,I0,R are characteristic of the transistor and may be rewritten as functions
of more fundamental physical parameters.
The thermal voltage is defined as:
kB T
VT =
q
With:

• kB : Boltzmann constant(8.314 JK−1 mol−1 )

• T : temperature in kelvin

• q: electron charge (1.6 × 10−19 C)

0.1.3 VI characteristics
The input and output characteristics are both referred to either an NPN or a PNP BJT in
common emitter configuration.
In this kind of configuration the emitter is chosen as the reference terminal and is connected to
the reference.
The 4 variables we study are thus VBE ,VCE ,IC ,IB :

IC IC
(C) (C)

(B) VCE (B) VCE

IB IB
(E) (E)

VBE VBE

NPN PNP

The two remaining variables VBC ,IE can be rewritten in terms of these four VBE ,VCE ,IC ,IB by
writing a KCL at the supernode and a KVL at the loop.

2
The result is: (
VBC = VBE − VCE
IE = −IB − IC
The input characteristic is given by the function:
IB = IB (VBE , VCE )
The output characteristic is given by the function:
IC = IC (VCE , IB )
The input and output characteristics for a NPN device are:

IB

VCE = 0.1 V

VCE = 0.5 V
NPN

0.8 V
VBE

IC
NPN

IB = 1.0 A

IB = 0.8 A
SATURATION

IB = 0.6 A

LINEAR
IB = 0.4 A

IB = 0.2 A

CUTOFF IB = 0.0 A
2V
VCE

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The input and output characteristics for a PNP device are:

IB
-0.8 V

VBE
VCE = -0.5 V

VCE = -0.1 V

PNP

IC
2V
IB = 0.0 A CUTOFF
VCE
IB = 0.2 A

IB = 0.4 A

LINEAR
SATURATION

IB = 0.6 A

IB = 0.8 A

IB = 1.0 A
PNP

All VI characteristics, being the functions we have to represent functions of two variables, are
plotted for a discrete and finite set of values of one of the variables.

We can see how the input characteristics are easily approximated with the one of a diode (with
reference sign convention for the NPN device and inverse sign direction for the PNP device.
This shows how the base current (generally input current) is almost not a function of the output
voltage
The output in the linear region can be easily approximated with horizontal lines.

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We can distinguish three different working regions:

• CUTOFF: The collector current flow is zero

• LINEAR: The collector current flow depends almost only on the base current IB and just
minimally on the collector-emitter voltage VCE because of the Early effect

• SATURATION: The collector current flow depends strongly on the collector-emitter volt-
age VCE and is almost independent from the base current IB

When we swap the roles of the emitter and collector we have another linear working region,
called the reverse linear region, so the total number of working regions is four.
The four working regions are defined according to the bias of the two PN junctions.
They are:

VCE VCE
NPN PNP

REVERSE
SATURATION LINEAR CUTOFF
LINEAR

VBE VBE
REVERSE
CUTOFF LINEAR SATURATION
LINEAR

Which correspond to the following biasing of the two PN junctions:

NPN PNP
Region BE BC Region BE BC
Saturation direct direct Saturation direct direct
Linear direct inverse Linear direct inverse
Reverse inverse direct Reverse inverse direct
Cutoff inverse inverse Cutoff inverse inverse

The working region depends just on the biasing on the two junctions and not on whether the
transistor is a PNP or an NPN.

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 0.1.4 T model (DC model for linear region)
Consider a common emitter configuration of a BJT.
We use the following sign convention for both NPN and PNP devices:

IC IC
(C) (C)

(B) VCE (B) VCE

IB IB
(E) (E)

VBE VBE

NPN PNP

13 αR IR αF IF
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With these sign conventions we have the following DC Ebers Moll models:

αR IR αF IF
NPN PNP

IE (K) (A) (A) (K)

IC IE (A) (K) (K) (A)
IC
(E) (C) (E) (C)

IF IR IF IR
(B) (B)
VBE VBC VBE VBC
IB IB

In all reverse biased junctions we have I ≈ 0, so we can neglect the currents flowing through
the reverse biased junctions and, consequently, since 0 < αR < 1, we can neglect the current
contribution of the controlled sources with coefficients αR as well. Since we have I ≈ 0 for both

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we can replace them with open circuits to get:

αF IF
13 αF IF
NPN PNP

IE (K) (A)
IC IE (A) (K)
IC
(E) (C) (E) (C)

IF IF
(B) (B)
VBE VBC VBE VBC
IB IB

We can redraw them in a nicer T shape.

This is where the ”T model” comes from.

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 NPN - T model

IE = I0,F

exp

VBE
VT

−1
 15 αF IF
IE (K) (A)
IC
With: (E) (C)

• I0,F : saturation current IF

(B)
VBE VBC
• VT : thermal voltage
IB
IC = −αF IE

PNP - T model
   
VBE
IE = −I0,F exp − −1
VT αF IF
IE (A) (K)
IC
With: (E) (C)

• I0,F : saturation current IF

(B)
VBE VBC
• VT : thermal voltage
IB
IC = αF IE

0.1.5 Π model (DC model for linear region)

NPN
15
Start from the T model for the NPN transistor:

αF IF
IE (K) (A)
IC
(E) (C)

IF
(B)
VBE VBC
IB

We can write:
IE = −IF
IC = αF IF = −αF IE = −αF (−IB − IC ) = αF IB + αF IC

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We can collect all terms with IC on the left and factor out IC :
IC − αF IC = αF IB
IC (1 − αF ) = αF IB
αF
IC = IB
1 − αF
Define the common emitter gain βF :
αF
βF =
1 − αF
By doing so, we have:
IC = βF IB
Also, we have:
IE = −IB − IC
From the input characteristics we can see how we can approximate the input characteristic
IB (VBE ) with a PN junction. Hence:

IE = −IB − IC

IC = βF IB

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
IB (VBE ) → PN Junction


The model corresponding to these equations is:

IB (B)
(A)
(C) IC

βF IB
VBE (K) VCE

(E)

IE

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In order to make the equations look better we can reverse the direction of the emitter current,
so that it becomes the sum of the collector current and the base current:

IB (B)
(A)
(C) IC

βF IB 
IE = IB + IC

VBE (K) VCE IC = βF IB

IB (VBE ) → PN Junction


(E)

IE

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PNP
Start from the T model for the PNP transistor:

αF IF
IE (A) (K)
IC
(E) (C)

IF
(B)
VBE VBC
IB

We can write:
IE = IF
IC = −αF IF = −αF IE = −αF (−IB − IC ) = αF IB + αF IC
We can collect all terms with IC on the left and factor out IC :

IC − αF IC = αF IB

IC (1 − αF ) = αF IB
αF
IC = IB
1 − αF
Define the common emitter gain βF :
αF
βF =
1 − αF
By doing so, we have:
IC = βF IB
Also, we have:
IE = −IB − IC

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From the input characteristics we can see how we can approximate the input characteristic
IB (VBE ) with a PN junction with opposite reference directions for currents and voltages.
Therefore, the equations give the following model:

IB (B) (C) IC
(K)

βF IB
VBE (A) VCE

(E)

IE

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The actual reference directions for the voltage and the current of the diode are the opposite, so
it is reasonable to change them by considering:

• IB with opposite direction

• VEB instead of VBE

In order to mantain the relationship between IC and IB we need to introduce a minus in it:

IC = −βF IB

We can now get rid of the minus sign by considering IC as exiting as well.
So, we have:

• IB exiting

• IC exiting

and the relation is:

16 IC = βF IB
So, we have to reverse the direction of the controlled current source as well.

IB (B) (C) IC
(K)

βF IB 
IE = IB + IC

The result is:
VEB VCE IC = βF IB
(A) 
IB (VEB ) → PN Junction


(E)

IE

Π MODELS

16 NPN - Π model

IB (B)
(A)
(C) IC

βF IB 
IE = IB + IC

VBE (K) VCE IC = βF IB

IB (VBE ) → PN Junction


(E)

IE

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16 PNP - Π model

IB (B) (C) IC
(K)

βF IB 
IE = IB + IC

VEB VCE IC = βF IB
(A) 
IB (VEB ) → PN Junction


(E)

IE

0.1.6 Distributed base resistance

In order to model the phenomenon of the distributed base resistance, we consider the BJT as
ideal (without any parassitic resistance) and we call its base the ”intrinsic base” B 0 .
Then we add an external resistance rBB 0 connected to the intrinsic base B 0 to model the dis-
tributed base resistance.

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We then consider the other terminal of the resistor as the physical base of the resistor.

RBB'

IB (B) (B')
(A)
(C) IC

βF IB

VB'E (K) VCE

(E)

IE

Of course, the intrinsic base is not physically accessible and this is just a model that takes into
account this parasitic phenomenon.

0.1.7 Early effect

The Early effect causes modulation of the output current due to variations of the output voltage.
It is particularly evident in the linear region, since it introduces a slope in the VI characteristic,
while the ideal one should be zero.
To model it we change the expression for the relation between the base current and the collector
current into:  
VCE
IC = IB βF 1 +
VA

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Where VA is a parameter that influences the slope and is called the Early voltage.
All the straight lines that constitute the output characteristic of the BJT, if stretched also
through the saturation, reverse and cutoff region, would meet in the point −VA :

The Early effect doesn’t influence in a relevant way the input characteristics, so it is just taken
into account on the output one

0.1.8 Power limit

Every BJT transistor has a power dissipation limit Pmax , which is the maximum thermal power
that the transistor is able to dissipate.

We can estimate the power absorbed by the device by studying the power dissipated by the
input port (base-emitter port) and the power dissipated by the output port (collector-emitter
port).

Therefore, we may estimate the dissipated power as:

P = VBE IB + VCE IC

We may now notice how, in general:

VBE  VCE
IB  IC
We may therefore neglect the first term in the expression for the power, obtaining:

P ≈ VCE IC

The power limitation can therefore be translated into a requirement on the output port (collector-
emitter port):
P ≈ VCE IC ≤ Pmax
We can notice how the following equation:

VCE IC = Pmax

is the equation of a parabola in the IC (VCE ) plane, while:

VCE IC ≤ Pmax

is the part of such plane that lies below it.

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We may now represent such parabola on the plane of the output characteristic, in order to see
the limit for the operating region imposed by this requirement:

IC
NPN

IB = 1.0 A

IB = 0.8 A

SATURATION IB = 0.6 A

LINEAR
IB = 0.4 A

IB = 0.2 A

Pmax
CUTOFF IB = 0.0 A
2V
VCE

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