JOURNAL OF COMPUTING, VOLUME 2, ISSUE 11, NOVEMBER 2010, ISSN 2151-9617

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A Reversible Design of BCD Multiplier

V. Rajmohan, Dr. V. Ranganathan and M. Rajmohan

Abstract—With the advent of quantum computer and reversible logic, the design and implementation of all devices has
received more attention. Since the prominence of commercial and financial applications which process decimal data is
increased, it needs some hardware support to handle such data. In this paper we propose a novel reversible design of single
digit decimal multiplier using reversible conservative logic 6-bit binary to 8-BCD conversion and 2:1 vector MUX. This is a fully
parallel multiplier using reversible gates. The proposed single digit BCD multiplier can be generalized for n-digit x n-digit
multiplication.

Index Terms—Keywords should be taken from the taxonomy (http://www.computer.org/mc/keywords/keywords.htm). Keywords

should closely reflect the topic and should optimally characterize the paper. Use about four key words or phrases in alphabetical
order, separated by commas.

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1 INTRODUCTION

O ne of the major goals in VLSI circuit design is the

reduction of power dissipation. R.Landauer demon-
strated in the early 1960s, irreversible hardware
computation results in energy dissipation due to the in-
formation loss, regardless of its realization technique [1].
It is proved that the loss of each one bit of information
dissipates at least KTln2 joules of energy (heat), where
K=1.3806505x10-23m2kg-2K-1 (joules Kelvin-1) is the
Boltzmann’s constant and T is the absolute temperature at
which operation is performed [1]. Reversible logic circuits
have theoretically zero internal power dissipation be-
cause they do not lose information. Bennett showed that
in order to avoid KTln2 joules of energy dissipation in a
circuit, it must be built using reversible logic gates [2]. A
circuit is said to be reversible if the input vector can be
uniquely recovered from the output vector and there is a
one-to-one correspondence between its input and output
assignments [4], [5], [6]. Thus, the number of inputs and
outputs in reversible logic circuits are equal. Such circuits
allow the reproduction of the inputs from observed out-
puts and we can determine the inputs from the outputs
[3], [4], [5].
Reversible logic has received significant attention in re-
cent years. It has applications in various research areas
such as Low Power CMOS design, quantum computing,
nanotechnology and DNA computing. It is not possible to
construct quantum circuits without reversible logic gates.
Synthesis of reversible logic circuits is significantly more
complicated than traditional irreversible logic circuits
because in a reversible logic circuit, we are not allowed to
use fan-out and feedback [4].
A reversible logic circuit should have the following fea-
————————————————
 V. Rajmohan is with the Hindustan Institute of Technology and Science,
Chennai, Tamilnadu, India.
 Dr. V. Ranganathan is with KCG College of Technology, Chennai, Tamil-
nadu, India.
 M. Rajmohan is with the Hindustan Institute of Technology and Science,
Chennai, Tamilnadu, India.
tures [5]:
 Use minimum number of reversible gates.
 Use minimum number of garbage outputs.
 Use minimum constant inputs.
The output that is not used for further computations is
called garbage output [6]. The input that is added to an
n x k function to make it reversible is called constant in-
put [6].
There are several reversible multiplier designs have been
proposed in the literature [7 ], [8], [9], [10], [11]. In this
paper, we propose a reversible design BCD multiplier
based on the designs available in the literature [14].
This paper presents a novel design for single digit decim-
al multiplication which allows for a fast multiplier design.
The partial products are generated as needed so that we
can reduce wiring and do not require registers to store the
partial products. The accumulation of partial products
generated using single digit multipliers is done by an ar-
ray of multi-operand reversible BCD adders [9] for an (n-
digit x n-digit) multiplication. This is a fully parallel mul-
tiplier utilizing only conservative reversible logic, and can
be extended for floating point multiplication of decimal
digits.
The organization of the paper is as follows: Initially, a
new approach for single digit BCD multiplication is dis-
cussed. Necessary background on reversible logic gates
that are used for the design is given. Then the proposed
blocks are implemented using reversible gates. A decimal
reversible fixed point multiplier is then proposed using
single digit decimal multipliers. Finally, the paper con-
cludes by tabulating the analyses of the proposed design.
2 REVERSIBLE LOGIC GATES
This section describes the reversible gates those are
used for the implementation of the proposed 6-bit binary
to BCD conversion and various blocks of BCD Multiplier.

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Fig 1 Feynman Gate
Figure 1 shows a Feynman Gate [12]. Feynman Gate (FG)
can be used as a copying gate. Since a fan-out greater than
one is not allowed, this gate is useful for duplication of
the required outputs. If the input vector Iv = (A, 0), then
the output vector becomes Ov = (P = A, Q = A).
Fig 2 Peres Gate
Figure 2 shows a Peres Gate (PG) [13]. It is also known as
New Toffoli Gate (NTG). Functionally Peres Gate is equal
with the transformation produced by a Toffoli Gate fol-
lowed by a Feynman Gate.
Fig 3 Double Peres Gate
Figure 3 shows a Double Peres Gate (DPG) [9]. The full
adder using DPG is obtained with C=0 and D= Cin.
Fig 4 SCL Gate
Figure 4 shows a SCL Gate (SCL) [6]. The SCL gate (Six
Correction Logic) can be used for the correction in the
BCD addition.
Fig 5 BVF Gate
113
Figure 5 shows a BVF Gate (BVF) [9]. This is a reversible
double XOR gate and can be used for the duplication of
the required inputs to meet the fan-out requirements.
This gate is used to copy the operand bits and the number
of gates required to copy is reduced by 50% with same
quantum cost. . If the input vector IV = (A, 0, C, 0), then
the output vector becomes OV = (P=A, Q=A, R=C, S=C).
Fig 6 Fredkin Gate
Figure 6 shows a 3x3 Fredkin gate. If the input vector Iv =
(0, B, C), then the output vector becomes Ov = (P = 0, Q =
B, R = C). If the input vector Iv = (1, B, C), then the output
vector becomes Ov = (P = 1, Q = C, R = B). The functionali-
ty shows that this gate can be used to design a n-bit MUX
with (n+1) garbage output.
Fig 7 TKS Gate
Figure 7 shows a TKS Gate (TKS) [17]. The TKS gate can
be used to implement any Boolean function since two of
its outputs (P & R) can function as 2:1 multiplexer. When
used as a MUX this gate produces 2 garbage outputs (Q,
R or P, Q).
Fig 8 HNG Gate
Figure 8 shows a HNG Gate (HNG) [7]. The reversible
HNG gate can work singly as a reversible full adder. If
the input vector IV = (A, B, Cin, 0), then the output vector
becomes OV = (P=A, Q=Cin, R=Sum, S=Cout). It produces
only two garbage outputs and requires only one constant
input. It needs only one clock cycle to perform the opera-
tion. It is better in terms of hardware complexity.
3 BCD MULTIPLICATION
A key component of a fixed-point multiplier is a single
digit multiplier that multiplies an n-digit multiplicand A,
by an n-digit multiplier B, producing a 2n-digit product,
P. The single digit multiplier accepts two BCD inputs (A,
B) in the range [0-9]. It realizes a function F(A, B), giving a
product in the range [0-81] represented by two BCD di-
gits. There are one hundred possible combinations of in-
puts for multiplication, out of which only 4 combinations
require 4 x 4 multiplication, 64 combinations need 3 x 3
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multiplication, and the remaining 32 combinations use
either 3 x 4 or 4 x 3 multiplication [14]. The proposed de-
sign makes use of this property. The single digit multip-
lier consists of an array of 3x3, 3x4, 4x3 binary multipliers
that gives a binary product P(7-0), a 4x4 multiplier that
gives a binary product P(6-0) and a binary to BCD conver-
ter . Since the 4-bit inputs can be either 8(10002) or
9(10012), the binary product is restricted to P(6-0). The
proposed reversible design makes use of this property.
4 PROPOSED REVERSIBLE 3X3 MULTIPLIER
Fig 9 3x3 Multiplication of BCD inputs
Figure 9 shows a 3x3 multiplication of BCD inputs.
Fig 10 Partial Product Generation
Figure 10 shows the reversible design of the partial prod-
uct generation of the above 3x3 multiplication. This de-
sign uses 9 Peres gates, 9 constant inputs and produces 18
garbage outputs.
Fig 11: Addition of Partial Products
114
Figure 11 shows the reversible design for the addition of 
the  partial  products.  Initially  Carry‐Save  Adder  (CSA) 
tree  is  used.  Thereafter  Ripple  Carry  Adder  is  used  to 
produce  the  final  6‐bit  product.  The  proposed  reversible 
design uses DPG gate as a reversible full adder and Peres 
gate as half adder. This design uses 3 DPG gates, 3 Peres 
gates, 6 constant inputs and produces 9 garbage outputs. 
5 PROPOSED REVERSIBLE 4X3 MULTIPLIER
Fig 12 Fig 12: 4x 3 multiplication of BCD inputs
Figure 12 shows the 4x3 multiplication of BCD inputs. In
4 x 3 multiplication of BCD inputs, one of the inputs is
either 8(10002) or 9(10012). So, the 4 x 3 multiplier gets
simplified to three 2-input AND gates. The reversible de-
sign is shown in figure 13. This design uses 3 Peres gates,
3 constant inputs and produces 3 garbage outputs.
Fig 13: 4x3 multiplication using Peres gates
6 PROPOSED REVERSIBLE 3X4 MULTIPLIER
Fig 14: 3x 4 multiplication of BCD inputs
Figure 14 shows the 3x4 multiplication of BCD inputs. In
3 x 4 multiplication of BCD inputs, one of the inputs is
either 8(10002) or 9(10012). So, the 3 x4 multiplier gets
simplified to three 2-input AND gates. The reversible de-
sign is shown in figure 15. This design uses 3 Peres gates,
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3 constant inputs and produces 3 garbage outputs.
Fig 15: 3x4 multiplication using Peres gates
7 PROPOSED REVERSIBLE 4X4 MULTIPLIER
Fig 16 4x4 multiplication of BCD inputs generating 8-bit BCD output
[14]
Figure 16 shows the 4x4 multiplication of BCD inputs.
Since the 4-bit inputs can be either 8(10002) or 9(10012), the
binary product is restricted to P(6-0). Instead of using a 7-
bit binary product, the 4x4 multiplier is designed to pro-
duce an 8-bit BCD output as shown in Figure 16. The re-
versible design is shown in Figure 17. This uses one HNG
gate, one DPG gate, one BVF gate, two Feynman gate, 8
constant inputs and produces 2 garbage outputs.
Fig 17: 4x4 multiplication using Reversible gates
8 PROPOSED REVERSIBLE 6-BIT BINARY TO 8-BIT
BCD CONVERTER
The 6-bit binary products from 3x3, 3x4, 4x3 multipliers
can be converted to an equivalent BCD values. A special,
simpler and faster seven -input, eight-output combina-
tional logic binary-to-BCD converter depicted in [15] is
used in this proposed design. The principle is given in
Figure 18.
115
Fig 18: Binary product to BCD conversion – the principle
The first row in Figure 18 shows the BCD weights. The
weights of p3, p2, p1 and p0 are the same as the corres-
ponding weights in the original binary number
p6p5p4p3p2p1p0. But weights 16, 32 and 64 of p4, p5 and
p6, have been decomposed to (10, 4, 2), (20, 10, 2) and (40,
20, 4) respectively. p3 has been moved to fourth row to
avoid the possibility of violating the interval [0, 9] for
each row-filled BCD digit. The four BCD digits in the
right four columns of Figure 18 may be added, by a BCD
adder, to lead to the BCD digit C (c3c2c1c0) of the product
B C and a decimal carry to be added to the two BCD di-
gits in the left three columns leading to B (b3b2b1b0). An
architecture was proposed for this BCD conversion in [16]
using array of conventional logic gates. A modified 6 -
input, 8 - output conversion principle was proposed in
[14]. In this paper we modify the design proposed in [16]
to perform 6 – input, 8 – output BCD conversion opera-
tion. The reversible design is shown in Figure 19.
Fig 19: Reversible design of binary – BCD converter
This reversible design contains an array of BCD adders
proposed in [6]. This BCD adder is the optimized since it
uses 8 reversible gates, 6 constant inputs and produces 10
garbage outputs. The design proposed in Figure 19 totally
uses 49 reversible gates, 61 constant inputs and produces
64 garbage outputs.
9 REVERSIBLE MULTIPLEXER
To design reversible MUX TKS gates and FRG gates were
considered. FRG gate is preferred since it produces less
garbage output compared to TKS. Each TKS gate produc-
es 2 garbage outputs ((P&Q) or (Q&R)). In FRG gate MUX
output can taken from either Q or R. Output P can be
used to propagate the select signal to the following gates.
An n-bit reversible FRG based Multiplexer proposed in
[8] is shown in Figure 20.
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11 RESULTS AND DISCUSSION

Fig 20: n-bit Multiplexer
Based on this, a 6-bit reversible MUX shown in Figure 21
is used in this design. This design uses 6 FRG gates, no
constant inputs and produces 7 garbage outputs.
Fig 21: 6-bit FRG based MUX
This paper proposed a reversible single digit BCD multip-
lier based on the available design in the literature. The
total delay of this design in terms of no. of gates is 93 gate
delays. The detailed analyses of each blocks of the pro-
posed design are given in Table 1. This proposed design
uses easy multiples for partial product generation in or-
der to avoid special storage elements to store them. This
single digit reversible BCD multiplier can be extended to
design multi digit BCD multiplier.

An 8-bit reversible MUX shown in Figure 22 is used in 12 CONCLUSION

this design. This design uses 8 FRG gates, no constant
inputs and produces 9 garbage outputs.
This paper proposes a BCD Multiplier circuit along with
its reversible logic implementation. The logical verifica-
tion was done using Xilinx ISE Simulator 9.1 and Model-
Sim 6.3C. The results are shown in Figure 24. The pro-
posed system can be used for designing large reversible
systems. The analyses of various blocks discussed in the
design are tabulated in Table-1.

Fig 22: 8-bit FRG based MUX

10 SINGLE DIGIT BCD MULTIPLIER

In this paper we proposed a reversible design for a single
digit multiplier available in the literature [14]. The design
architecture is shown in Figure 23.

Fig 24: Simulation Results

TABLE 1 THE ANALYSES OF VARIOUS BLOCKS

Delay
Parameters in
No. No. of No. of
terms
Fig 23: Single digit BCD Multiplier proposed in [14] of garbage constant
Various of no.
gates outputs inputs
Blocks of
The first 6-bit 2: 1 vector MUX selects the 3 x 4 or 4 x 3 gates
multiplier output depending on X3 bit. Second 6-bit 2: 1 4 x 4 mul-
vector MUX does the selection of 3 x 3 multiplier output 5 2 8 5
tiplier
or the output of the first multiplexer depending on the 3 x 4 mul-
status of X3 and Y3 bits. If X3 and Y3 are different then 3 3 3 3
tiplier
the output of the first multiplexer is passed to the BCD 4 x 3 mul-
converter, else the output of 3 x 3 multiplier is passed. 3 3 3 3
tiplier
After the 6-bit binary to BCD conversion the third 8-bit 2: 3 x 3 mul-
1 vector MUX selects the BCD converted output or the 15 27 15 15
tiplier
output of the 4 x 4 multiplier output (which gives an 8-bit 2:1 vector
BCD result) depending on X3 and Y3 bits. If both are '1' 6 7 0 6
MUX1
then the 4 x 4 multiplier output is selected, else the BCD 2:1 vector
converted output is passed as the final product. 6 7 0 6
MUX2
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Binary to [16] Jairaj Bhattacharya, Aman Gupta, Anshul Singh, ” A High Per‐

BCD con- 49 64 61 49 formance  Binary  to  BCD  Converter  for  Decimal  Multiplica‐
verter tion”, 2010 International Symposium on VLSI Design, Automa‐
2:1 vector tion and Test (2010 VLSI‐DAT), Hsinchu, Taiwan. 
8 9 0 8 [17] Himanshu Thapliyal, M.B Srinivas, “Novel Design and Reversi‐
MUX3
ble Logic Synthesis of Multiplexer Based  Full  Adder and  Mul‐
HA 1 1 1 1 tipliers”, pp. 1593 – 1596, 2005. 

Total de-
96 123 91 96 V. Rajmohan received his B.E. degree in Electronics and Commu-
sign nication Engineering from Thiayagarajar College of Engineering,
Madurai, Tamilnadu, India in 1998. He obtained his M.E. degree in
VLSI from Regional Engineering College, Trichy, Tamilnadu, India in
2000. Currently he is an Assistant Professor in the department of
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