1. List 4 important parameters of packages.

2. What are the two challenges of packages compared to the die?

3. Explain the space transformation property of packaging and how it reduces the cost?
4. What are the three hierarchies of packaging?
5. What are the functions of packaging?
6. What are the three interconnection technologies for chip to package interconnection?
7. Find the round trip delay of a Printed Circuit board of size 6” and dielectric constant of 4.
8. An interconnect has a round trip delay of 0.4 ns, determine the minimum clock frequency
for which the transmission line model should be used.
9. What are the advantages of PTH packages compared to surface mount packages?
10. Compare the speed of propagation of a signal in embedded microstrip line and microstrip line.
11. Consider a strip line of length 4” with propagation delay and characteristic impedance
as 600ps and 50 Ω respectively. If it is to be modelled as N segments of transmission
line for a clock signal with rise time 2ns, What is the value of N? What is the inductance
of each segment of the strip line?
12. An inverter drives another inverter separated by a long interconnect which is modeled as a transmission
line with characteristic impedance of 50 Ω. The inverter has ON resistance of 10 Ω. What would
be the voltage at the load end at t = 4T where T is the propagation delay from generator to load.
Assume Vdd =5V
13. An inverter drives another inverter separated a long interconnect which is modeled as a transmission
line with characteristic impedance of 50 Ω. The inverter has ON resistance of 7.5 Ω. What would be the
voltage at the load end at t = 3T where T is the propagation delay from generator to load.
Assume Vdd=5V
14. Explain how the round trip delay of a Printed Circuit board of size 6” is 1 ns. .
15. How do you determine whether the transmission line model is required for an interconnect or not?
16. What is the inductance and capacitance per unit length of a parallel strip line with separation between
the planes and the width of the plane as d and w respectively?
17. Explain how the distance between the driver and the load affect the far end and near end cross talk ?
18. Explain how the effective inductance of vias can be minimized.
19. Explain how the decoupling capacitors reduce the simultaneous switching noise?
20. Why does the location at which the decoupling capacitor is put determine the highest frequency at
which they are effective?
21. Consider an inverter circuit driving a 1 pF capacitive load. If 500 such circuit switches binary states in
time 10 ns, What should be the maximum effective inductance , if the Power supply voltage variation
should not exceed 10% of Vdd.
22. In order to restrict the SSN to be 250mV a decoupling capacitor of 20 pF is used with a power supply
path having an effective impedance of 5 pH. What is the maximum frequency upto which the
decoupling capacitor would be effective in restricting the SSN within the limit?
23. Why is the line width decreased at the branching points in the H tree?
24. With a diagram show how either a power tree or a large buffer can minimize the skew due to clock distribution network
25. Explain why a hybrid clock distribution scheme which routes the clock through both chip and package is preferred?
26. A clock distribution network has the following characteristics: Rise/Fall Time: 1 ns , Setup/Hold Time: 1 ns and Skew and
Jitter: 1 ns, what is maximum data rate that can be used with this systems?
27. In which of the clock distribution architectures, the minimum clock frequency depends on N- the number of bits transmitted
during tf (time of flight: the time taken for the signal to travel from Tx to Rx).
28. What are the advantages and challenges in source synchronous clock distribution architecture?
29. A synchronous system uses a common clock for both Tx and Rx. Calculate the operating frequency range for this system if
tf=15ns, ta=500ps, tr=100ps, tu=500ps and no. of bits on the wire during tf is 3.
30. Write the expression for the effective inductance of the package and the maximum tolerable SSN and the number of drivers
between two chips separated by interconnects modelled as transmission line.
31. What are the three places where the decoupling capacitors can be located? Upto what frequencies these capacitors are
effective?
32. What are the major sources of EMI?
33. What are the three parameters which determine the EMI?
34. List any two techniques to minimize EMI
35. Consider an inverter circuit driving a 1 pF capacitive load. Power supply voltage variation should not exceed 10%
36. of Vdd. If 500 such circuit switches binary states in time 20 ns, What will be the effective inductance?
37. Consider a package that has a power supply inductance of 10 pH and has to support the switching of 500 on-chip circuits.
These circuits draw 10 A of current in time 0.25 ns. What is the power supply noise voltage? If this noise voltage has to be
reduced by a factor of 2, what is the value of the decoupling capacitor required?
38. A decoupling capacitor of 0.1F is capable of ensuring the fluctuation in voltage to be 0.25 V when the circuit is to be
charged over a period of 5 nsec. Determine how many 50 Ω lines can be driven by this capacitor. Assume Vdd = 5V.
39. 64 low impedance buffers are switched simultaneously. The line impedance is 50 Ω, rise time 3 nsec, output swing is 5 V. If
the inductance/ line is 1 nH, what would be voltage drop across the inductance due to power/ground connections. If the
effective inductance per pair is 2 nH, how many pairs of power/ground connections should be used to ensure the maximum
fluctuation to be 0.25 V
40. A decoupling capacitor is used to reduce the SSN due to supply and ground path whose total inductance is 10 pH and is
drawing a current of 5 A. If the maximum operating frequency upto which the decoupling capacitor is effective in reducing
the SSN is 600 MHz, find the value of the decoupling capacitance and the magnitude of SSN.
41. Create an equivalent circuit model of a loss-free 50-Ω transmission line 5 in. long for thecross section shown in Figure.

Assume that the driver has a minimum rise time of 2.5ns. Assume a dielectric constant of 4.5.

42. Assume that two components, U1 and U2, need to communicate with each other via a highspeed digital bus. The components
are mounted on a standard four-layer motherboard with the stackup shown in Figure 2.30. The driving buffers on component

U1 have an impedance of 30 Ω, an edge rate of 100 ps, and a swing of 0 to 2 V. The traces on the PCB are required to be 50

Ω and 5 in. long. The relative dielectric constant of the board (εr) is 4.0, the transmission line is assumed to be a perfect

conductor, and the receiver capacitance is small enough to be ignored. Figure depicts the circuit topology

Standard four layer motherboard stackup.

a. Determine the correct cross-sectional geometry of the PCB shown in Figure that will yield an impedance of 50 Ω.

b. Calculate the time it takes for the signal to travel from the driver, U1, to the receiver, U2.
c. Determine the wave shape seen at U2 when the system is driven by U1.
d. Create an equivalent circuit of the system.

43. Assume the two-conductor system shown in Figure, where Zo ≈ 70 Ω, the termination resistors = 70 Ω, V(input) = 1.0 V, Tr

= 100 ps, and X = 2 in. Determine the near- and far-end crosstalk magnitudes assuming the following capacitance and
inductance matrices:

44. Consider the same two-conductor system of Example 3.2. If R1 = 45 and R2 = 100 Ω, what are the respective near- and far-

end crosstalk voltages?

45. From the L and C matrices, Find the Impedance and Phase Velocity for each of the following cases:-
a. Without Crosstalk (isolated case)
b. Even Mode
 c. Odd Mode
d. Also, Find the Reflection Co-efficient if Line is matched to an impedance of 65ohms.

46. Assume that a pair of coupled transmission lines is 5 in. long and a digital signal with a rise time of 100 ps is to be simulated.
Given the following inductance and capacitance matrices, calculate the characteristic impedance, the total propagation delay,
the inductive coupling factor, the number of required segments, the maximum delay per segment, and the maximum L, R, C,
G, Cm, and K values for one segment.

47.
48. Assume that two components, U1 and U2, need to communicate with each other via an 8-bitwide high-speed digital bus. The
components are mounted on a standard four-layer motherboard with the stackup shown in Figure 3.20. The driving buffers on

component U1 have an impedance of 30 Ω and a swing of 0 to 2 V. The traces on the printed circuit board (PCB) are

required to be 5 in. long with center-to-center spacing of 15 mils and impedance 50 Ω (ignoring crosstalk). The relative

dielectric constant of the board (εr) is 4.0, the transmission line is assumed to be a perfect conductor, and the receiver
capacitance is small enough to be ignored.

Figure: Cross section of PCB board

The transmission line parasitics are
􀂃 mutual inductance = 0.54 nH/in.
􀂃 mutual capacitance = 0.079 pF/in.
􀂃 self-inductance = 7.13 nH/in. (from the Chapter 2 example)
􀂃 self-capacitance = 2.85 pF/in. (from the Chapter 2 example)
a. Determine the maximum impedance variation on the transmission lines due to crosstalk.
b. Determine the maximum velocity difference due to crosstalk.
49. Explain how T and Pi terminations may be used to avoid reflections due to both odd and even mode signals.
50. Write the expressions for near end and far end cross talk when the load is (i) matched (ii) unmatched
51. Write the expression for the velocity and impedance corresponding to a bus carrying three signals when (i) all the three
signals are in phase (ii) 1st and 3rd signal are in phase and is out of phase with the middle.
52. Explain a technique to remove a cross talk? What are the disadvantages of this approach