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24-BIT DIGITAL SIGNAL PROCESSOR

The DSP56002 is a MPU-style general purpose Digital Signal Processor
(DSP) composed of an efficient 24-bit DSP core, program and data
memories, various peripherals, and support circuitry. The DSP56000
core is fed by on-chip Program RAM, and two independent data RAMs.
The DSP56002 contains a Serial Communication Interface (SCI),
Synchronous Serial Interface (SSI), parallel Host Interface (HI),
Timer/Event Counter, Phase Lock Loop (PLL), and an On-Chip
Emulation (OnCE™) port.
CODEC 4215
o
ANALOG CHARACTERISTICS(T A =25 C;VA1,VA2,Vd1,VD2
= +5V;
Input Levels : Logic 0 = 0V, Logic 1 = VD1,VD2;Full Scale Input Sine
wave,No Gain , No Attenuation 1 kHz ; Conversion Rate = 48kHz;No
Gain,No Attenuation , SCLK = 3.072MHz
, Measurement Bandwidth is 10Hz to 20kHz ; Slave Mode;Unless
otherwise specified .)
Parameter* Max Units
Symb Min Typ
ol
Analog Input Characteristics-Minimum Gain setting(0 dB);
Unless otherwise specified .
ADC Resolution 16 - - Bits
ADC Differential - - ± 0 LSB
Nonlinearity .9
Instantanneous Dynamic IDR 80 84 - dB
Range :Line Inputs
72 78 - dB

Mic Inputs
Total Harmonic Distortion : - - 0.01 %
Line Inputs 2
THD - - %
0.03
Mic Inputs 2
Interchannel Isolation : Line - 80 - dB
to Line Inputs
- 60 - dB

Line to Mic Inputs

Interchannel Gain Mismatch : - - 0.5 dB
Line Inputs
- - 0.5 dB

Mic Inputs
Frequency Respone (Note 1) -0.5 - +0.2 dB
(0 to 0.45 Fs )
Programmable Input Gain: -0.2 - 23.5 dB
Line Inputs
19.8 - 44 dB

Mic Inputs
Gain Step Size - 1.5 - dB
Absolute Gain Step Error - - 0.75 dB
Offset Error Line - ± 1 ± 4
Inputs (AC coupled) 50 00
- LSB
With HPF = 0 Line ± 1 ± 1
-
Inputs (DC coupled) 0 50
(No Gain) Mic ± 4 -
Inputs 00
Offset Error Line - 0 ± 5
Inputs(AC coupled)
- 0 ± 5 LSB
With HPF=1 Line
- 0 ± 5
Inputs(DC coupled)
(No Gain) (Notes 1,2)
Mic Inputs
Full Scale Input Voltage: 0.25 0.28 0.31 Vpp
(MLB=0) Mic Inputs
2.50 2.80 3.10 Vpp

(MLB=1) Mic Inputs 2.50 2.80 3.10 Vpp

Line Inputs
Gain Drift - 100 - ppm/
o
C
Input Resistance 20 - - k Ω

(Note 3)
Input Capacitance - - 15 PF
CMOUT Output Voltage 1.9 2.1 2.3 V
 (Note 4)
(maximum output current =
400 μ A)
Notes :
1. This specification is guaranteed by characterization ,not production
testing .
2. Very low frequency signals will be slightly distorted when using
the HPF .
3. Input resistance is for the input selected .Non-selected input have a
very high (>1M Ω ) input resistance .
4. DC current only . If dynamic loading exists ,then CMOUT must be
buffered or the performance of ADC’s and DAC’s may be
degraded .

ANALOG CHARACTERISTICS (continued)

Parameter* Symbol Min Ty Max Units
p
Analog Output Characteristics – Minimum Attenuation ;Unless
Otherwise Specified
DAC Resolution 16 - - Bits
DAC Differential - - ± 0. LSB
Nonlinearity 9
Total Dynamic Range TDR - 95 - dB
Instantanneous Dynamic IDR 80 85 - dB
Range (OLB=1) (All
Outputs)
Total Harmonic Distortion: - - 0.025 %
Line Out(Note 5)
THD - - 0.200 %
(OLB = 1)
- - 0.320 %
Headphone Out(Note 6)

Speaker Out(Note 6)
Interchannel Isolation : Line - 80 - dB
Out(Note 5)
- 40 - dB

Headphone Out(Note 6)
Interchannel Gain Mismatch - - 0.5 dB
: Line Out
- - 0.5 dB

Headphone
Frequency Respone (Note 1) -0.5 - +0.2 dB
(0 to 0.45 Fs )
Programmable Attenuation 0.2 - -94.7 dB
(All Outputs)
Attenuation Step Size - 1.5 - dB
Absolute Attenuation Step - - 0.75 dB
Error
Offset Voltage - 10 - MV
Full Scale Output Voltage 2.5 2.8 3.80 Vpp
Line Output (Note 5) 5
with OLB = 0 3.6 4.0 4.40 Vpp
Headphone Output (Note 0
8.0 8.80 Vpp
6)
7.3
Speaker Output- 0
Differential (Note 6)
Full Scale Output Voltage
Line Output (Note 5)
1.8 2.0 2.2 Vpp
with OLB = 1
1.8 2.0 2.2 Vpp
Headphone Output (Note
6) 3.6 4.0 4.4 Vpp

Speaker Output-
Differential (Note 6)
External Load Impedance 10 - - Ω

Line Output Ω
48 - -
Ω
Headphone Output 32 - -

Speaker Output
Gain Drift - 100 - ppm/oC
Deviation from Linear Phase - - 1 Degree
Out of Band Energy(22kHz - 60 - dB
to 100kHz) Line Out
Power Supply
Power Supply Current - 110 140 mA
(Note7) Operating
- 0.5 2 mA
 Power Down
Power Supply Rejection - 40 - dB
(1kHz)

Notes :
5. 10k Ω ,100pF load .Headphone and Speaker outputs disabled .
6. 48 Ω ,100pF load. For the Headphone outputs , THD with 10k Ω

,100pF load is 0.02% .

7. Typically ,50% of the power supply current is supplied to the
analog power pins(VA1,VA2) and 50% is supplied to the digital
power pins (VD1,VD2) .Values given are for unloaded outputs .

A/D DECIMATION FILTER CHARACTERISTICS

Parameter* Symbol Min Typ Max Units

Passband (Fs is 0 - 0.45Fs Hz
conversion freq.)
Frequency Respone -0.5 - +0.2 dB
Passband Ripple - - ± 0.1 dB
Transition Band 0.45Fs - 0.55Fs Hz
Stop Band ¿ 0.55 - - Hz
 Fs
Stop Band Rejection 74 - - dB
Group Delay 16Fs - s
Group Delay Variation vs. - 0 μ s
Frequency

D/A INTERPOLATON FILTER CHARACTERISTICS

Parameter* Symbo Min Typ Max Units

l
Passband (Fs is 0 - 0.45Fs Hz
conversion freq.)
Frequency Respone -0.5 - +0.2 dB
Passband Ripple - - ± 0.1 dB
Transition Band 0.45Fs - 0.55Fs Hz
Stop Band ¿ 0.55 - - Hz
Fs
Stop Band Rejection 74 - - dB
Group Delay 16Fs - s
Group Delay Variation - 0.1Fs μ s
vs. Frequency
DIGITAL CHARACTERISTICS(T A =25oC ;VA1,VA2,VD1,VD2 =
5V)

Parameter* Symbol Min Max Units

High-level Input V IH (VD1,VD2)- (VD1,VD2)+0. V
Voltage 1.0 3
Low-level Input V IL -0.3 1.0 V
Voltage
High-level V OH (VD1,VD2)- - V
Output Voltage at 0.2
I 0 =2.0mA
Low-level Output V OL - 0.1 V
Voltage at

I 0 =2.0mA
Input Leakage - 10 μA
Current (Digital
Inputs)
Output Leakage - 10 μA
Current
(High-Z Digital
Outputs)
SWITCHING CHARACTERISTICS(T A =25oC
;VA1,VA2,VD1,VD2 = +5V ,outputs loaded with 30pF ;Inputs Level ;
Logic 0 = 0V , Logic 1 =VD1,VD2 )

Parameter* Symbo Min Typ Max Units

l
SCLK period Master t sckw - 1/(Fs*bpt) - s
Mode,XCLK=1(Note 8)
t sckw 80 - - ns

Slave Mode(XCLK=0)
SCLK high time Slave t sckh 25 - - ns
Mode,XCLK =0(Note9)
SCLK low time Slave t sckl 25 - - ns
Mode,XCLK =0(Note9)
Input Setup Time t sl 15 - - ns
Input Hold Time t hl 10 - - ns
Input Transition Time - - 10 ns
(10% to 90% points)
Output delay t pd1 - - 28 ns

SCLK to TSOUT t pd2 - - 30 ns

Output to Hi-Z state t hz - - 12 ns

Time Slot 8 , Bit 0
Output to non Hi-Z t nz 15 - - ns
Time Slot 1 , Bit 7
Input Clock Frequency - - 27 Mhz
Crystals
1.204 - 13.5 Mhz

CLKIN (note 10)

Input clock (CLKIN) low 30 - - ns
time
Input clock (CLKIN) 30 - - ns
high time
Sample rate Fs 4 - 50 KHz
RESET low time 500 - - ns
(Note 11)

8. In Master mode with BSEL1,0 set to 64 or 128 bits per frame (bpf)
,the SCLK duty cycle is 50% . When BSEL1,0 is set to 256 bpf ,
SCLK will have the same duty cycle as CLKOUT . See Internal
Clock Generation section .
9. In Slave Mode ,FSYNC and SCLK must bederived from the
master clock running the codec (CLKIN , XTAL1,XTAL2) .
10. Sample rate specifications must not be exceeded .
11. After powering up the CS4215 ,RESET should be held low
for 50 ms to allow the voltage reference to settle .
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all
voltages with respect to 0V)

Parameter Symbol Min Max Units

Power Supplies : VD1,VD -0.3 6.0 V
Digital 2
-0.3 6.0 V
VA1,VA
Analog 2
Input Current - mA
(Except Supply Pins)
Analog Input Voltage -0.3 V
Digital Input Voltage -0.3 V
O
Ambient Temperature -55 C
(Power Aplied)
O
Storage Temperature -65 C

Warning : Operating beyond these limits may result in permanent

damage to the device . Normal operaion is not guaranteed at these
extremex .
RECOMMEND OPERATING CONDITIONS (AGND , DGND =
0V all voltages with respect to 0V) .

Parameter Symbol Min Max Units

Power Supplies : VD1,VD 4.75 5.0 V
Digital (Note 8) 2
4.75 5.0 V
VA1,VA
Analog (Note 8) 2
o
Operating Ambient Temperature T A 0 25 c

Note : 8. |VD−VA| must be less than 0.5Volts (one diode drop) .

DSP56002

Data Sheet Conventions

This data sheet uses the following conventions :

 OVERBARS are used to indicate a signal that is active

when pulled to ground (see Table 1)e.g. the HREQ pin is
active when pulled to ground . Therefore , references to
the HREQ pin will always have an overbar .

 The word “assert” (see Table 1) means that a high true

(active high ) signal is puulled high to VCC or that a low
true (active low) signal is pulled low to ground .

 The word “deassert” (see Table 1) means that a high true

signal is pulled low to ground or that a low true signal is
pulled high to VCC .

Table 1 High True / Low True Signal Conventions

 Signal / Logic State Signal Voltage
Symbol State
PIN True Asserted Ground
PIN False Deasserted VCC
PIN True Asserted VCC
PIN False Deasserted Ground

NOTES :
1. PIN is a generic term for any pin on the chip .
2. Ground is an acceptable low voltage level . See the DC
electrical specifications for the range of acceptable low
voltage levels (typically a TTL logic low) .
3. VCC is an acceptable high voltage level . See the DC
electrical specifications for the range of acceptable high
voltge levels (typically a TTL logic high) .
Pin Groupings
The input and output signals of the DSP56002 are organized into
functional groups as shown in Table 2 .

Table 2 DSP56002 functional Pin Groupings

Functional Group Number of Pins

Address Bus 16
Data Bus 24
Bus Control 10
Host Interface (HI) 15
 Serial Communication 3
Interface (SCI)
Synchronous Serial Interface 6
(SSI)
Timer /Event Counter 1
Interrupt and Mode Control 4
Phase-Locked Loop(PLL) and 7
Clock
On-chip Emulation (OnCE 4
TM
) Port
Power (VCC) 16
Ground (GND) 24
Reserved (no connect) 2
Total Number of Pins 132

* alternately , general purpose I/O pins

** package dependent
Electrical Specifications
DSP56002 ( 5.0 Volt Operation)

The DSP56002 is fabricated in high desity CMOS with TTL compatible

inputs and outputs .

Table 3 Absolute Maximum Ratings (GND = 0 Vdc)

 Rating Symbol Value Unit
Supply Voltage VCC -0.3 to V
+7.0
All Input Voltages V IN GND –0.5 V
to

V CC
+0.5
Current Drain per Pin I 10 mA
Excluding
VCC and GND
o
Operating Temperature T J -40 to C
Range +105
0
Storage Temperature T stg -55 to C
+150

Table 4 Thermal Characteristics of Packages

PQFP
Therm Sym Valu Uni Sym Valu Uni Sym Valu Uni
al bol e ts bol e ts bol e ts
Resista
nce
Junctio
n θJA o θJA o θJA o
38 C/ 22 C/ 49 C/
to W W W
Ambien
t
Junctio
n θJC o θJC o θJC o
13 C/ 6.5 C/ 12 C/
to Case W W W
(estimat
ed)

DSP56002
DC Electrical Characteristics

( VCC =5.0 Vdc ± 10% ; T J = -40o to +105oC)

Table 5 DC Electrical Characteristics for the DSP56002
Characteristics Symb DSP56002 Uni
ol ts
 Min Ty Ma
p x
Supply Voltage VCC 4.5 5. 5.5 V
0
Input High Voltage

Except EXTAL , RESET ,

VIH
MODA , MODB , MODC
2.0 - VCC V
VIHC
EXTAL 4.0 - VCC V
VIHR
 RESET 2.5 - VCC V
VIHM
MODA , MODB , MODC 3.5 - VCC V
Input Low Voltage

Except EXTAL VIL -0.5 - 0.8 V

,MODA,MODB,MODC
VILC -0.5 - 0.6 V
EXTAL VILM -0.5 - 2.0 V
MODA , MODB , MODC
Input Leakage Current IIN -1 - 1 μA

EXTAL, RESET , MODA/IRQA ,

MODB/ IRQB , MODC/ NMI , BR ,
WT

Three-State(Off-State) Input ITSI -10 - 10 μA

Current
(@2.4V / 0.4V)
Output High Voltage(IOH = -0.4mA) VOH 2.4 - - V
Output Low Voltage(IOL = 3mA ; VOL - - 0.4 V
HREQ IOL = 6.7mA,TXD IOL =
6.7mA)
Internal Supply Current at 40MHz ICCI - 90 105 mA
(See Note3)
ICCW - 12 20 mA
 in Wait Mode (See Note 1) μA
ICCS - 2 95
 in Stop Mode (See Note 1)
Internal Supply Current at ICCI - 95 130 mA
66MHz(See Note3)
ICCW - 15 25 mA
 in Wait Mode (See Note 1) μA
ICCS - 2 95
 in Stop Mode (See Note 1)
PLL Supply Current (See Note 4 ) - 1 1.5 mA
at 40MHz
- 1. 1.5 mA
1
at 66MHz
CKOUT Supply Current - 14 20 mA
at 40MHz
- 28 35 mA
(See Note 5)
at 66MHz
Input Capacitance (See Note 2) CIN - 10 - pF
Notes :
1. In order to obtain these results all inputs must be terminated (i.e.,
not allowed to float) using CMOS level.
 2. Periodically sampled and not 100% tested.
3. Power Consumption in the Design Considerations section
describes how to calculate the external supply current.
4. Value given are for PLL enabled.
5. Value given are for CKOUT enable.
AC Electrical Characteristics
The timing waveforms in the AC Electricl Characteristics are tested with
a VIL maximum of 0.5V and a VIH minimum of 2.4V for all pins, except
EXTAL, RESET , MODA, MODB, and MODC. These four pins are
tested using the input levels set forth in the DC Electrical Characteristics
section. AC timing specifications which are referenced to a device input
signal aremeasured in production with respect to the 50% point of the
respective input signal‘s transition. DSP56002 output levels are
measured with the producion test machine VOL and VOH reference level
set at 0.8 V and 2.0 V respectively.
Internal Clocks
For each occurrence of TH, TL,TC or ICYC substitube with the expressions
given in Table 6 .ETH, ETL, and ETC are further defined in the Table 7.
DF and MF are PLL devision and multiplication factors set registers.
Table 6 Internal Clocks
Characteristics Symbo Expression
l
Internal Operation f
Frequency
Internal Clock High Period TH
 - with PLL disabled ETH

- with PLL enabled and (Min) 0.48 x ETC x

MF ¿ 4 DF/MF
(Max) 0.52 x ETC x
DF/MF

- with PLL enabled and (Min) 0.467 x ETC x

MF >4 DF/MF
(Max) 0.533 x ETC x
DF/MF

Internal Clock Low Period TL

- with PLL disabled ETL

- with PLL enabled and (Min) 0.48 x ETC x

MF ¿ 4 DF/MF
(Max) 0.52 x ETC x
DF/MF

- with PLL enabled and (Min) 0.467 x ETC x

MF >4 DF/MF
(Max) 0.533 x ETC x
DF/MF

Internal Clock Cycle Time TC ETC x DF/MF

Intruction Cycle Time ICYC 2 x TC
Clock
The DSP56002 system clock may be derived from the on-chip crystal
oscillator as shown in Figure 1, or it may be externally supplied. An
externally supplied square wave voltage sourse should be connected to
EXTAL, leaving XTAL physically unconnected (see Figure 2 ) to the
board or socket. The rise and fall time of this external clock should be 4
ns maximum.

XTAL EXTAL EXTAL XTAL

R R1 R2

C1

C XTAL1 C XTAL1
L1 C2 C3

Fundamental Frequency 3rd Overtone

Crystal Oscillator Crystal Oscillator
Suggested Component Values Suggested Component Values
R = 680K Ω ± 10% R1 = 470K Ω ± 10%
C = 20 pF ± 20% R2 = 330K Ω ± 10%
C1 = 0.1 μ F ± 20%
C2 = 26 pF ± 20%
C3 = 20 pF ± 10%
L1 = 2.37 μ H ± 10%
XTAL = 40MHz, AT cut, 20pF
load,
50 Ω max series resistance

Figure 1 Crystal Oscillator Circuits

 VILC
EXTAL Midpoint
VIHC
ETH ETL

1 2

ETc
4

NOTE: The midpoints is VILC +0.5 (VIH –VILC).

Table 7 Clock Operation

Nu Characteristics Sym 40 MHz 66 MHz Uni

m bol t
 Mi Max Mi Max
n n
Frequency of Ef 0 40 0 66 M
Operation Hz
(EXTAL Pin)
1 Clock Input High
(See Note)
11. ∞
7.0 ∞

 with PLL 7 9
ETH ns
disabled
235.5 235.5
(46.7%-53.3% μ s μ s
10. 6.3
duty cycle)
5 6
 with PLL
enabled
(42.5%-57.5%
duty cycle)
 2 Clock Input Low
(See Note)
11. ∞
7.0 ∞

 with PLL 7 9
ETL ns
disabled
235.5 235.5
(46.7%-53.3% μ s μ s
10. 6.3
duty cycle)
5 6
 with PLL
enabled
(42.5%-57.5%
duty cycle)
3 Clock Cycle Time

 with PLL ETC 25 7.0 ns

∞ ∞

disabled 235.5 9 235.5

25
μ s μ s
 with PLL 6.3
enabled 6
4 Intruction Cycle
Time = ICYC = 2 x
ICYC
TC (See Note)
50 ∞
ns
 with PLL
50 819.2
disabled
μ s
 with PLL
enabled

NOTE: External Clock Input High and External Clock Input Low
are measured at 50% of the input transition.
Phase-Locked Loop (PLL)

Table 8 Phase-Locked Loop Characteristics

Characteristics Expression Min Max Unit

VCO frequency MF x Ef 10 F MHz
when PLL
(See Notes 1,2) (See
enabled
Note 3)
PLL external MF x CPCAP (Se
capacitor note 4)
MF x MF x480 PF
(PCAP pin to @ MF 340
MF x
VCCP) ¿ 4
MF x 970
@ MF 380
>4

NOTE:
1. The ”E” in ETH, ETL, and ETC means external.
2. MF is the PCTL Multiplication Factor bits (MF0 - MF11).
DF is the PCTL Division Factor bits (DF0 – DF3).
 3. The maximum VCO frequency is limitedto the internal
operation frequency.
4. CPCAP is the value of the PLL capacitor (connected between
PCAP pin and VCCP ) for MF = 1. The recommended value
for CPCAP is 400pF for MF ¿ 4 and 540pF for MF > 4.

Reset, Stop, Mode Select, and Interrupt Timing

VCC = 5.0 Vdc ± 10%, TJ = -40oC to +105oC, CL = 50pF + 2 TTL
Loads
WS = Number of wait states (1 WS = TC) programmed into external bus
access using BCR (WS = 0 – 15).

Table 9 Reset, Stop, Mode Select, And Interrupt Timing

Nu Characteristics 40/66MHz
m Uni
Min Max
t

1 Delay from RESET Assertion to

Address High Impedanse
- 26 ns
(periodically sampled and not
100% tested).
2 Minimum Stabilization Duration

 Internal Oscillator PLL 75000xT - ns

disabled (See Note 1) C

 External Clock PLL - ns

disabled (See Note 2) 25xTC
 External Clock PLL
Enabled (See Note 2) - ns
2500xTC
3 Delay from Asynchronuos
RESET Deassertion to First
8xTC 9xTC+20 ns
External Address Output
(Internal Reset Deassertion)
4 Synchronous Reset Setup Time
from RESET
8.5 TC ns
Deassertion to CKOUT
transition #1
5 Synchronous Reset Delay Time
from the CKOUT transition #1
8xTC 8xTC+6 ns
to the First External Address
Output

6 Mode Select Setup Time 21 - ns

7 Mode Select Hold Time 0 - ns
8 Minimum Edge – Triggered 13 - ns
Interrupt Request Assertion
Width
9 Minimum Edge – Triggered 13 - ns
Interrupt Request Deassertion
Width
10 Delay from IRQA ,IRQB ,NMI
Assertion to External Memory
Access Address Out Valid

 Cause by First Interrupt

Instruction Fetch 5xTC+TH - ns

 Cause by First Interrupt

Instruction Execution 9xTC+TH - ns
11 Delay from IRQA ,IRQB ,NMI
Assertion to General Purpose
Transfer Output Valid caused by
Fisrt Interrupt Instruction 11xTC+T - ns
Execution H

12 Delay from Address Output

Valid Caused by Fisrt Interrupt
- 2xTC+TL ns
Inctrustion to Interrupt Request
+
Deassertion for Level Sensitive
(TCxWS)
Fast Interrupts(See Note 3)
-23
13 Delay from RD Assertion to
Interrupt Request Deassertion for
- 2xTC + ns
Level Sensitive Fast
Interrupts(See Note 3) (TCxWS)
-21
14 Delay from WR Assertion to
Interrupt Request Deassertion for
Level Sensitive Fast Interrupts

 WS = 0
- 2xTC –21 ns
 WS > 0
- TC+TL+ ns
(See Note
3) (TCxWS)
-21
15 Delay from General-Purpose
Output Valid to Interrupt
Request Deassertion for Level
Sensitive Fast Interrupts - If
second Interrupt Instruction is:

 Single Cycle - TL –31 ns

 Two Cycles - (2xTC)+ ns
(See Note TL -31
3)
16 Synchronous Interrupt Setup 10 TC ns
Time from IRQA ,IRQB ,NMI
Assertion to the CKOUT
transition #2
17 Synchronous Interrupt Delay
Time from the CKOUT
transition #2 to the First External
Address Output Valid caused by 13 13 ns
the First Instruction Fetch after xTC+TH xTC+TH+
coming out of Wait State
6
18 Duration for IRQA Assertion to 12 - ns
Recover from Stop State.
19 Delay from IRQA Assertion to
Fetch of First Interrupt
Instruction (when exiting ’Stop’)
65548xT - ns
 Internal Crystal Oscillator C
Clock, OMR bit 6 = 0

 Stable External Clock, 20 xTC - ns

OMR bit 6 =1 13 xTC - ns
 Stable External Clock,
PCTL bit 17=1
(See Note 3)
20 Duration of Level Sensitive
IRQA Assertion to ensure
interrupt service (when exiting
’Stop’)

 Internal Crystal Oscillator 65534xT - ns

Clock, OMR bit 6 = 0 C

 Stable External Clock, 6 xTC+TL - ns

OMR bit 6 =1
12 - ns
 Stable External Clock,
PCTL bit 17=1
(See Note 3)
21 Delay from Level Sensitive
IRQA Assertion to Fetch of First
Interrupt Instruction (when
exiting ’Stop’)

 Internal Crystal Oscillator 65548xT - ns

Clock, OMR bit 6 = 0 C

 Stable External Clock, 20 xTC - ns

OMR bit 6 =1
13 xTC - ns
 Stable External Clock,
PCTL bit 17=1
(See Note 3)
NOTE:
1. A clock stabilization delay is required when using the on-chip
crystal oscillator in two cases:
  after power-on reset, and

 when recovering from Stop mode

During this stabilization period,TC, TH, TL will not be constant. Since this
stabilization period varies, a delay of 75,000 x TC is typically allowed to
assure that the oscillator is stable before executing programs.
2. Circuit stabilization delay is required during reset when using an
external clock in two cases:

 after power-on reset, and

 when recovering from Stop mode

3. When using fast interrupt and IRQA and IRQB are defined as
level – sensitive, then timings 19 through 22 apply to prevent
multiple interrupt service. To avoid these timing restrictions, the
deassertive edge-triggered mode is recommended when using fast
interrupt. Long interrupts are recommended when using level-
sensitive mode.

Host I/O Timing

VCC = 5.0 Vdc ± 10%, TJ = -40oC to +105oC, CL = 50pF + 2 TTL
Loads
Active allow lines should be “pulled up” in a manner consistent with the
AC nad DC specifications.
Table 10 Host I/O Timing

Nu Characteristics 40/66MHz
m Uni
Min Max
t

1 HEN / HACK Assertion Width

(See Note 1)
TC+31 - ns
 CVR, ICCR, ISR, RXL 26 -
Read
13 -
 IVR, RXH/M Read

 Write
2 HEN / HACK Deassertion Width 13 - ns
(See Note 1)
2 x TC + - ns
 Between Two TXL 31
- ns
Writes(See Note2) 2 x TC +
 Between Two CVR, ICR, 31
ISR, RXL Reads (See Note
3)
3 Host Data Input Setup Time 4 - ns
Before HEN / HACK Deassertion
4 Host Data Input Hold Time After 3 - ns
HEN / HACK Deassertion

5 HEN / HACK Assertion to Output 0 - ns

Data Active from High
Impedance
6 HEN / HACK Assertion to Output - 26 ns
Data Valid
7 HEN / HACK Deassertion to - 18 ns
Output Data High Impedance
(See Note 5)
8 Output Data Hold Time After 2.5 - ns
HEN / HACK Deassertion (See
Note 6)
9 HR/W Low Setup Time Before 0 - ns
HEN Assertion

10 HR/W Low Hold Time After 3 - ns

HEN Deassertion

11 HR/W High Setup Time to 0 - ns

HEN Assertion

12 HR/W Hold Time After HEN 3 - ns

Deassertion
13 HA0 – HA2 Setup Time Before 0 - ns
HEN Assertion

14 HA0 – HA2 Hold Time After 3 - ns

HEN Deassertion
15 DMA HACK Assertion to 3 45 ns
HREQ Deassertion (See Note 4)
16 DMA HACK Deassertion to
HREQ Assertion (See Notes 4,
5)
TL+TC+T - ns
 for DMA RXL Read H
- ns
 for DMA RXL Write TL+TC
- ns
 all other cases 0
17 Delay from HEN Deassertion to TL+TC+T - ns
HREQ Assertion for RXL Read H

(See Notes 4, 5)

18 Delay from HEN Deassertion to TL+TC - ns

HREQ Assertion for RXL Write
(See Notes 4, 5)
19 Delay from HEN Assertion to 3 58 ns
HREQ Deassertion for RXL
Read , TXL Write (See Notes 4,
5)
NOTE:
1. See Host Port Considerations in the section on Design
Considerations.
2. This timing must be adhered to only if two consecutive writes to
the TXL are executed without polling TXDE or HREQ .
3. This timing must be adhered to only if two consecutive reads from
one of these registers are executed without polling the
corresponding status bits or HREQ .

4. HREQ is pulled up by a 1K Ω resistor.

5. Specifications are periodically sampled and not 100% tested.
6. May decrease to 0 ns for future versions.
Serial Communication Interface(SCI) Timing
VCC = 5.0 Vdc ± 10%, TJ = -40oC to +105oC, CL = 50pF + 2 TTL
Loads
TSCC = Synchronous Clock Cycle Time (for internal clock, tSCC is
determined by the SCI clock control register and TC). The minimum
tSCC value is 8 x TC.

Table 11 SCI Synchronous Mode Timing

Nu Characteristics 40/66MHz
m Uni
Min Max
t

1 Synchronous Clock Cycle – 8 x TC - ns

tSCC
2 Clock Low Period tSCC/2– - ns
10.5
3 Clock High Period tSCC/2– - ns
10.5
4 < intentionally blank> - - -
5 Output Data Setup to Clock tSCC/4 - ns
Falling Edge (Internal Clock) +TL – 26
6 Output Data Hold After Clock tSCC/4 – - ns
Rising Edge (Internal Clock) TL – 8
7 Input Data Setup Time Before tSCC/4 - ns
Clock Rising Edge (Internal +TL +23
Clock)
8 Input Data Not Valid Before - tSCC/4 ns
Clock Rising Edge (Internal +TL – 5.5
Clock)
9 Clock Falling Edge to Output - 32.5 ns
Data Valid (External Clock)
10 Input Data Hold After Clock TC +8 - ns
Rising Edge (External Clock)
11 Input Data Setup Time Before 16 - ns
Clock Rising Edge (External
Clock)
12 Input Data Hold Time After 21 - ns
Clock Rising Edge (External
Clock)
Table 12 SCI Asynchronous Mode Timing – 1X Clock
Nu Characteristics 40/66MHz
m Unit
Min Max

1 Asynchronous Clock Cycle – 64 x TC - ns

tACC
2 Clock Low Period tACC/2– - ns
11
3 Clock High Period tSCC/2– - ns
11
4 < intentionally blank> - - -
5 Output Data Setup to Clock tACC/2 - ns
Rising Edge (Internal Clock) – 51
6 Output Data Hold After Clock tACC/2 - ns
Rising Edge (Internal Clock) – 51

Synchronous Serial Interface (SSI) Timing

VCC = 5.0 Vdc ± 10%, TJ = -40oC to +105oC, CL = 50pF + 2 TTL
Loads

tSSIC = SSI clock cycle time

TXC(SCK pin) = Transmit Clock
RXC(SC0 or SCK pin) = Receive clock
FTS(SC2 pin) = Transmit Frame Sync
FSR(SC1 or SC2 pin) = Receive Frame Sync
i ck = Internal Clock
x ck = External Clock
g ck = Gated clock
i ck a = Internal Clock, Asynchronous Mode
(Asynchronous implies that STD and SRD are two differrent clocks)
i ck s = Internal Clock, Synchronous Mode
(Synchronous implies that STD and SRD are two same clocks)
bl = bit length
wl = word length

Table 13 SSI Timing

Nu Characteristics 40/66MHz Ca Uni

m Min Max se t

1 Clock Cycle – tSSICC 4 x TC - i ck ns

(See Note 1)
3 x TC - x
ck
2 Clock High Period TSSICC/2 - i ck ns
-10.8
- x
TC + TL ck
3 Clock Low Period TSSICC/2 - i ck ns
-10.8
- x
TC + TL ck
4 < intentionally blank> - - - -
5 RXC Rising Edge to FSR - 40.8 x ns
Out(bl) High ck
- 25.8
i ck
a
6 RXC Rising Edge to FSR - 35.8 x ns
Out(bl) Low ck
- 25.8
i ck
a
7 RXC Rising Edge to FSR - 35.8 x ns
Out(wl) High ck
- 25.8
i ck
a
8 RXC Rising Edge to FSR - 35.8 x ns
Out(wl) Low ck
- 25.8
i ck
a
9 Data In Setup Time 3.3 - x ns
Before RXC ck
15.8 -
(SCK in Synchronous i ck
13 -
Mode)Falling Eddge a
i ck
s
10 Data In Hold Time After 18 - x ns
RXC ck
3.3 -
Falling Eddge i ck
11 FSR Input (bl) High 0.8 - x ns
Before RXC Falling Edge ck
17.4 -
i ck
a
12 FSR Input (wl) High 3.3 - x ns
Before RXC Falling Edge ck
18.3 -
i ck
a
13 FSR Input (bl) Hold Time 18.3 - x ns
After RXC Falling Edge ck
3.3 -
i ck
14 Flags Input Setup Before 0.8 - x ns
RXC Falling Edge ck
16.7 -
i ck
s
15 Flags Input Hold Time 18.3 - x ns
After RXC Falling Edge ck
3.3 -
i ck
s
16 TXC Rising Edge to FST - 31.6 x ns
Out(bl) High ck
- 15.8
i ck
17 TXC Rising Edge to FST - 33.3 x ns
Out(bl) Low ck
- 18.3
i ck
18 TXC Rising Edge to FST - 30.8 x ns
Out(wl) High ck
- 18.3
i ck
19 TXC Rising Edge to FST - 33.3 x ns
Out(wl) Low ck
- 18.3
i ck
20 TXC Rising Edge to Data - 33.3+ x ns
Out Enable from High TH ck
-
Impedance
20.8 i ck
21 TXC Rising Edge to Data - 33.3+ x ns
Out Valid TH ck
-
22.4 i ck
 22 TXC Rising Edge to Data - 35.8 x ns
Out High Impedance (See ck
- 20.8
Note 2)
i ck
23 TXC Falling Edge to Data - TC+TH g ns
Out High Impedance (See ck
Note 2)
24 FST input (bl) Setup 0.8 - x ns
Time Before TXC Falling ck
18.3 -
Edge
i ck
25 FST input (wl) to Data - 30.8 ns
Out Enable from High
Impendance
26 FST input (wl) Setup 0.8 - x ns
Time Before TXC Falling ck
20.0 -
Edge
i ck
27 FST input (bl) Hold Time 18.3 - x ns
After TXC Falling Edge ck
3.3 -
i ck
28 Flag Output Valid After - 32.5 x ns
TXC Rising Edge ck
- 20.8
i ck

NOTE:
1. For internal clock, External Clock Cycle is defined by ICYC
and SSI control register.
2. Periodically sampled, and not 100% tested.