Beruflich Dokumente
Kultur Dokumente
TPS54040
SLVS918B – MARCH 2009 – REVISED JANUARY 2016
TPS54040 80
70
Efficiency - %
EN BOOT 60
50
PH
40
SS /TR
30 VI = 12 V,
RT /CLK
20 VO = 5.0 V,
COMP fsw = 700 kHz
VSENSE 10
0
0 0.1 0.2 0.3 0.4 0.5
GND
Load Current - A
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54040
SLVS918B – MARCH 2009 – REVISED JANUARY 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 31
2 Applications ........................................................... 1 8.1 Application Information............................................ 31
3 Description ............................................................. 1 8.2 Typical Application .................................................. 31
4 Revision History..................................................... 2 8.3 System Examples ................................................... 40
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 41
6 Specifications......................................................... 4 10 Layout................................................................... 42
6.1 Absolute Maximum Ratings ..................................... 4 10.1 Layout Guidelines ................................................. 42
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 42
6.3 Recommended Operating Conditions ...................... 4 10.3 Estimated Circuit Area .......................................... 42
6.4 Thermal Information .................................................. 5 11 Device and Documentation Support ................. 43
6.5 Electrical Characteristics........................................... 5 11.1 Device Support .................................................... 43
6.6 Typical Characteristics .............................................. 7 11.2 Community Resources.......................................... 43
7 Detailed Description ............................................ 11 11.3 Trademarks ........................................................... 43
7.1 Overview ................................................................. 11 11.4 Electrostatic Discharge Caution ............................ 43
7.2 Functional Block Diagram ....................................... 12 11.5 Glossary ................................................................ 43
7.3 Feature Description................................................. 12 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 29 Information ........................................................... 43
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
DGQ Package
10-Pin HVSSOP
Top View
BOOT 1 10 PH
VIN 2 9 GND
PowerPAD
EN 3 8 COMP
(11)
SS/TR 4 7 VSENSE
RT/CLK 5 6 PWRGD
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
BOOT 1 O
minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
COMP 8 O
components to this pin.
Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
EN 3 I
undervoltage lockout with two resistors.
GND 9 – Ground
PH 10 I The source of the internal high-side power MOSFET.
PowerPAD 11 – GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or
PWRGD 6 O
EN shut down.
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
RT/CLK 5 I a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-
enabled and the mode returns to a resistor set function.
Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
SS/TR 4 I
voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
VIN 2 I Input supply voltage, 3.5 V to 42 V.
VSENSE 7 I Inverting node of the transconductance (gm) error amplifier.
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating temperature range (unless otherwise noted).
MIN MAX UNIT
VIN –0.3 47
EN –0.3 5
BOOT 55
VSENSE –0.3 3
Input voltage V
COMP –0.3 3
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 3.6
BOOT-PH 8
Output voltage PH –0.6 47 V
PH, 10-ns Transient –2 47
Voltage difference PAD to GND –200 200 mV
EN 100 μA
BOOT 100 mA
VSENSE 10 μA
Source current
Current
PH A
Limit
RT/CLK 100 μA
Current
VIN A
Limit
Sink current COMP 100 μA
PWRGD 10 mA
SS/TR 200 μA
Operating junction temperature –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
(3) Test boards conditions:
(a) 3 inches x 3 inches, 2 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground plane, bottom layer
(d) 6 thermal vias (13 mil) located under the device package
0.816
500
VI = 12 V
VI = 12 V
0.808
0.800
250
BOOT-PH = 6 V
0.792
125
0.784
0 -50 -25 0 25 50 75 100 125 150
-50 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 2. Voltage Reference vs Junction Temperature
Figure 1. On Resistance vs Junction Temperature
1.1 610
VI = 12 V,
VI = 12 V
RT = 200 kW
600
590
Switch Current - A
0.9 580
570
0.8
560
0.7 550
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
Figure 3. Switch Current Limit vs Junction Temperature Figure 4. Switching Frequency vs Junction Temperature
2500 500
VI = 12 V,
TJ = 25°C
VI = 12 V,
2000 400
fs - Switching Frequency - kHz
TJ = 25°C
fs - Switching Frequency - kHz
1500 300
1000 200
500 100
0 0
0 25 50 75 100 125 150 175 200 200 300 400 500 600 700 800 900 1000 1100 1200
RT/CLK - Resistance - kW RT/CLK - Resistance - kW
Figure 5. Switching Frequency vs Rt/clk Resistance High Figure 6. Switching Frequency vs RT/CLK Resistance Low
Frequency Range Frequency Range
130
30
110
gm - mA/V
gm - mA/V
90
20
70
10 50
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
Figure 7. EA Transconductance During Slow Start vs Figure 8. EA Transconductance vs Junction Temperature
Junction Temperature
1.40 -3.25
VI = 12 V,
VI = 12 V
VI(EN) = Threshold +50 mV
-3.5
1.30
EN - Threshold - V
I(EN) - mA
-3.75
1.20
-4
1.10 -4.25
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
Figure 9. EN Pin Voltage vs Junction Temperature Figure 10. EN Pin Current vs Junction Temperature
-0.8 -1
VI = 12 V, VI = 12 V
VI(EN) = Threshold -50 mV
-0.85 -1.5
I(SS/TR) - mA
I(EN) - mA
-0.9 -2
-0.95 -2.5
-1 -3
-50 -25 0 25 50 75 100 125 150
-50 -25 0 25 50 75 100 125 150
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
Figure 11. EN Pin Current vs Junction Temperature Figure 12. SS/TR Charge Current vs Junction Temperature
% of Nominal fsw
60
II(SS/TR) - mA
110
40
105
20
100 0
-50 -25 0 25 50 75 100 125 150 0 0.2 0.4 0.6 0.8
TJ - Junction Temperature - °C VSENSE - V
Figure 13. SS/TR Discharge Current vs Junction Figure 14. Switching Frequency vs VSENSE
Temperature
2 2
VI = 12 V
TJ = 25°C
1.5 1.5
I(VIN) - mA
I(VIN) - mA
1 1
0.5 0.5
0 0
-50 -25 0 25 50 75 100 125 150 0 10 20 30 40
TJ - Junction Temperature - °C VI - Input Voltage - V
Figure 15. Shutdown Supply Current vs Junction Figure 16. Shutdown Supply Current vs Input Voltage (Vin)
Temperature
140 140
o
VI = 12 V, TJ = 25 C,
VI(VSENSE) = 0.83 V VI(VSENSE) = 0.83 V
130 130
120 120
I(VIN) - mA
I(VIN) - mA
110 110
100 100
90 90
-50 -25 0 25 50 75 100 125 150 0 20 40
TJ - Junction Temperature - °C VI - Input Voltage - V
Figure 17. VIN Supply Current vs Junction Temperature Figure 18. VIN Supply Current vs Input Voltage
VI = 12 V VI = 12 V
60
100
40
VSENSE Rising
95
20 VSENSE Falling
90
0 85
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 20. PWRGD Threshold vs Junction Temperature
Figure 19. PWRGD ON Resistance vs Junction Temperature
2.5 3
2.3 2.75
VI(BOOT-PH) - V
VI(VIN) - V
2 2.50
1.8 2.25
1.5 2
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
Figure 21. BOOT-PH UVLO vs Junction Temperature Figure 22. Input Voltage (UVLO) vs Junction Temperature
500 60
VI = 12 V, V(SS/TR) = 0.2 V
o
TJ = 25 C VI = 12 V
55
400
50
300
Offset - mV
Offset - mV
45
200
40
100
35
0 30
0 100 200 300 400 500 600 700 800 -50 -25 0 25 50 75 100 125 150
VSENSE - mV TJ - Junction Temperature - °C
Figure 23. SS/TR to VSENSE Offset vs VSENSE Figure 24. SS/TR to VSENSE OFFSET vs Temperature
7 Detailed Description
7.1 Overview
The TPS54040 device is a 42-V, 0.5-A, step-down (buck) regulator with an integrated high side n-channel
MOSFET. To improve performance during line and load transients the device implements a constant frequency,
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency of 100kHz to 2500kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin.
The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power
switch turn on to a falling edge of an external system clock.
The TPS54040 has a default start up voltage of approximately 2.5V. The EN pin has an internal pull-up current
source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two external
resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the device will
operate. The operating current is 116μA when not switching and under no load. When the device is disabled, the
supply current is 1.3μA.
The integrated 200mΩ high side MOSFET allows for high efficiency power supply designs capable of delivering
0.5 amperes of continuous current to a load. The TPS54040 reduces the external component count by
integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a
capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the
high side MOSFET off when the boot voltage falls below a preset threshold. The TPS54040 can operate at high
duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8V
reference.
The TPS54040 has a power good comparator (PWRGD) which asserts when the regulated output voltage is less
than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which
deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the
pin to transition high when a pull-up resistor is used.
The TPS54040 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power
good comparator. When the OV comparator is activated, the high side MOSFET is turned off and masked from
turning on until the output voltage is lower than 107%.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor
divider can be coupled to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged
before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault,
UVLO fault or a disabled condition.
The TPS54040, also, discharges the slow start capacitor during overload conditions with an overload recovery
circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation
voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during
startup and overcurrent fault conditions to help control the inductor current.
Logic
SS/TR 4
And
PWM Latch
Shutdown
Slope
Compensation
COMP 8 10 PH
Frequency 11 POWERPAD
Shift
Overload Maximum
Recovery Clamp 9 GND
Oscillator TPS54040 Block Diagram
with PLL
5
RT/CLK
4 5.6
VO = 3.3 V VO = 5 V
3.8 5.4
VI - Input Voltage - V
VI - Input Voltage - V
3.6 5.2
Start
Start
3.4 Stop 5
Stop
3.2 4.8
3 4.6
0 0.05 0.10 0.15 0.20 0 0.05 0.10 0.15 0.20
IO - Output Current - A IO - Output Current - A
Figure 25. 3.3-V Start/Stop Voltage Figure 26. 5-V Start/Stop Voltage
TPS54040
VIN
Ihys
I1
R1 2.9 mA
0.9 mA
+
R2 EN 1.25 V -
V - VSTOP
R1 = START
IHYS
(2)
VENA
R2 =
VSTART - VENA
+ I1
R1 (3)
Another technique to add input voltage hysteresis is shown in Figure 28. This method may be used, if the
resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3
sources additional hysteresis current into the EN pin.
TPS54040
VIN
Ihys
R1 I1
2.9 mA
0.9 mA
+
R2 EN 1.25 V -
VOUT
R3
VSTART - VSTOP
R1 =
V
IHYS + OUT
R3 (4)
VENA
R2 =
VSTART - VENA V
+ I1 - ENA
R1 R3 (5)
Do not place a low-impedance voltage source with greater than 5 V directly on the EN pin. Do not place a
capacitor directly on the EN pin if VEN > 5 V when using a voltage divider to adjust the start and stop voltage.
The node voltage, (see Figure 29) must remain equal to or less than 5.8 V. The zener diode can sink up to 100
µA. The EN pin voltage can be greater than 5 V if the VIN voltage source has a high impedance and does not
source more than 100 µA into the the EN pin.
VIN
R1
ENA Node
10kohm
R2 5.8V
EN
SS/TR
VSENSE
VOUT
TPS54040
PWRGD
EN EN
EN1
PWRGD
VOUT1
VOUT2
Figure 31. Schematic for Sequential Start-Up Figure 32. Sequential Start-Up Using EN and
Sequence PWRGD
TPS54160
TPS54040
3 EN
EN1, EN2
4 SS/TR
6 PWRGD
VOUT1
TPS54040
TPS54160
VOUT2
3 EN
4 SS/TR
6 PWRGD
Figure 33. Schematic for Ratiometric Start-up Figure 34. Ratiometric Start-up Using Coupled
Using Coupled SS/TR Pins SS/TR Pins
TPS54040
EN VOUT 1
SS/TR
PWRGD
TPS54040
EN VOUT 2
R1
SS/ TR
R2
PWRGD
R3
R4
Ratiometric and simultaneous power-supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 35 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 7 and Equation 8, the tracking resistors can be calculated to initiate the VOUT2
slightly before, after or at the same time as VOUT1. Equation 9 is the voltage difference between VOUT1 and VOUT2
at the 95% of nominal output regulation.
The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
VSENSE offset (VSSOFFSET) in the slow start circuit and the offset created by the pullup current source (ISS) and
tracking resistors, the VSSOFFSET and ISS are included as variables in the equations.
To design a ratiometric start-up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2
reaches regulation, use a negative number in Equation 7 through Equation 9 for ΔV. Equation 9 will result in a
positive number for applications which the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved.
Since the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO or thermal shutdown fault,
careful selection of the tracking resistors is needed to ensure the device will restart after a fault. Make sure the
calculated R1 value from Equation 7 is greater than the value calculated in Equation 10 to ensure the device can
recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage the VSSOFFSET becomes larger
as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR
pin voltage needs to be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in
Figure 23.
Vout2 + deltaV Vssoffset
R1 = ´
VREF Iss (7)
SPACE
EN EN
VOUT1 VOUT1
VOUT2 VOUT2
Figure 36. Ratiometric Start-up With VOUT2 Leading VOUT1 Figure 37. Ratiometric Start-Up with VOUT1 Leading VOUT2
EN
VOUT1
VOUT2
2500 500
VI = 12 V,
TJ = 25°C
VI = 12 V,
2000 400
fs - Switching Frequency - kHz
TJ = 25°C
1000 200
500 100
0 0
0 25 50 75 100 125 150 175 200 200 300 400 500 600 700 800 900 1000 1100 1200
RT/CLK - Clock Resistance - kW RT/CLK - Resistance - kW
Figure 39. Switching Frequency vs RT/CLK Resistance Figure 40. Switching Frequency vs RT/CLK Resistance
High Frequency Range (Hi Range RT) Low Frequency Range (Low Range RT)
IL inductor current
Rdc inductor resistance
VIN maximum input voltage
VOUT output voltage
VOUTSC output voltage during short
Vd diode voltage drop
RDS(on) switch on resistance
tON controllable on time
ƒDIV frequency divide equals (1, 2, 4, or 8)
2500
Skip
fs - Switching Frequency - kHz
2000
1500
Shift
1000
500
VO = 5.0 V
0
10 20 30 40
VI - Input Voltage - V
TPS54040
10 pF 4 kW
PLL
Rfset
EXT RT/CLK
Clock 50 W
Source
PH
PH
EXT EXT
IL
IL
Figure 43. Plot of Synchronizing in CCM Figure 44. Plot of Synchronizing in DCM
PH
EXT
IL
PH
VO
Power Stage
gmps 1.9 A/V
a
R1 RESR
COMP RL
c
VSENSE COUT
0.8 V
R3 CO RO
gmea
C2
97 mA/V R2
C1
7.3.19 Simple Small Signal Model for Peak Current Mode Control
Figure 47 describes a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54040 power stage can be approximated to a voltage-controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 14 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 46) is the power stage
transconductance. The gmPS for the TPS54040 is 1.9A/V. The low-frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of
Figure 47. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions which makes it easier to design the frequency
compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on
the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number
frequency compensation components needed to stabilize the overall loop because the phase margin increases
from the ESR zero at the lower frequencies (see Equation 17).
VO
VC Adc
RESR
fp
RL
gmps
COUT
fz
Figure 47. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
æ s ö
ç1 + ÷
VOUT 2p ´ fZ ø
= Adc ´ è
VC æ s ö
ç1 + ÷
è 2 p ´ fP ø (14)
Adc = gmps ´ RL
(15)
1
fP =
COUT ´ RL ´ 2p (16)
1
fZ =
COUT ´ RESR ´ 2p (17)
VO
R1
VSENSE
gmea Type 2A Type 2B Type 1
COMP
Vref
R3 C2 R3
R2 RO CO C2
C1 C1
Aol
A0 P1
Z1 P2
A1
BW
Figure 49. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Aol(V/V)
Ro =
gmea (18)
gmea
CO =
2p ´ BW (Hz) (19)
æ s ö
ç1 + ÷
è 2p ´ fZ1 ø
EA = A0 ´
æ s ö æ s ö
ç1 + ÷ ´ ç1 + ÷
è 2p ´ fP1 ø è 2p ´ fP2 ø
(20)
R2
A0 = gmea ´ Ro ´
R1 + R2 (21)
R2
A1 = gmea ´ Ro| | R3 ´
R1 + R2 (22)
1
P1 =
2p ´ Ro ´ C1 (23)
VOUT(ac)
IL
PH
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
Figure 51. High Frequency, 5-V Output Power Supply Design with Adjusted UVLO
IRIPPLE =
VOUT ´ (Vin max - VOUT )
Vin max ´ L O ´ fSW (29)
2
1 æ VOUT ´ (Vinmax
- VOUT ) ö
IL(rms) = (IO )2 + 12 ´ çç Vinmax ´ LO ´ fSW
÷
÷
è ø (30)
Iripple
ILpeak = Iout +
2 (31)
Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which will increase
this minimum value. For this example, a 47 μF 10V X5R ceramic capacitor with 5 mΩ of ESR will be used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 36 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 36 yields
39 mA.
2 ´ DIout
Cout >
¦ sw ´ DVout (32)
Cout > Lo ´
(Ioh2
- Iol2)
(V ¦ 2
- Vi )2
(33)
1 1
Cout > ´
8 ´ ¦ sw VORIPPLE
IRIPPLE (34)
V
RESR < ORIPPLE
IRIPPLE
(35)
Vout ´ (Vin max - Vout)
Icorms =
12 ´ Vin max ´ Lo ´ ¦ sw (36)
The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, tss,
necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average
slow start current of Issavg. In the example, to charge the 47μF output capacitor up to 5.0V while only allowing
the average input current to be 0.125A would require a 1.5 ms slow start time.
Once the slow start time is known, the slow start capacitor value can be calculated using Equation 6. For the
example circuit, the slow start time is not too critical since the output capacitor value is 47μF which does not
require much current to charge to 5.0V. The example circuit has the slow start time set to an arbitrary value of
3.2ms which requires a 0.01 μF capacitor.
Cout ´ Vout ´ 0.8
Tss >
Issavg (40)
8.2.2.10 Compensation
There are several methods used to compensate DC/DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual cross over frequency will usually be lower than the cross over frequency
used in the calculations. This method assume the crossover frequency is between the modulator pole and the
esr zero and the esr zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more
accurate design.
To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 41 and
Equation 42. For Cout, use a derated value of 21.2 μf. Use equations Equation 43 and Equation 44, to estimate
a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is
753 Hz and fzmod is 1505 kHz. Equation 43 is the geometric mean of the modulator pole and the esr zero and
Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 33.7 kHz and
Equation 44 gives 16.2 kHz. Use the lower value of Equation 43 or Equation 44 for an initial crossover frequency.
For this example, fco is 16.2 kHz. Next, the compensation components are calculated. A resistor in series with a
capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the
compensating pole.
Ioutmax
¦p mod =
2 × p × Vout × Cout (41)
1
¦ z mod =
2 ´ p ´ Resr × Cout (42)
fco = f p mod ´ f z mod
(43)
f
fco = f p mod ´ sw
2 (44)
To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance,
gmps, is 1.9A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are
5V, 0.8V and 92μA/V, respectively. R4 is calculated to be 77.1 kΩ, use the nearest standard value of 76.8kΩ.
Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 2754 pF for
compensating capacitor C5, a 2700 pF is used on the board.
æ 2 ´ p ´ fco ´ Cout ö æ Vout ö
R4 = ç ÷´ç ÷
è gmps ø è Vref ´ gmea ø (45)
1
C5 =
2 ´ p ´ R4 ´ f p m od
(46)
Use the larger value of Equation 47 and Equation 48 to calculate the C6, to set the compensation pole.
Equation 48 yields 5.9pF so the nearest standard of 5.6pF is used.
C o ´ Re sr
C6 =
R4 (47)
1
C6 =
R4 ´ f sw ´ p (48)
Figure 54. Output Ripple CCM Figure 55. Output Ripple, DCM
Figure 56. Output Ripple, PSM Figure 57. Input Ripple CCM
100
90
80
VIN = 15 V VIN = 12 V
70 VIN = 24 V
VIN = 34 V
Efficiency - % 60 VIN = 42
50
40
30
20
10 VOUT = 5.0 V
0
0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
IO - Output Current - A
100 60 180
90 150
40 120
80
Phase 90
70
20 60
Efficiency - %
60 Vin = 12 V 30
Vin = 15 V
Phase - o
Gain - dB
Vin = 24 V
50 Vin = 34 V 0 Gain 0
Vin = 42 V
-30
40
-20 -60
30
-90
20
-40 -120
VOUT = 5.0 V
10 -150
0 -60 -180
0 0.02 0.04 0.06 0.08 0.10 100 1-103 1-104 1-105 1-106
IO - Output Current - A f - Frequency - Hz
Figure 60. Light Load Efficiency Figure 61. Overall Loop Frequency Response
0.1 0.1
0.08 VI = 24 V 0.08
IO = 0.2 A
0.06 0.06
0.04 0.04
Regulation (%)
Regulation (%)
0.02 0.02
0 0
-0.02 -0.02
-0.04 -0.04
-0.06 -0.06
-0.08 -0.08
-0.1 -0.1
0.00 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 12 18 24 30 36 42
VI - Input Voltage - V
Load Current - A
Figure 62. Regulation vs Load Current Figure 63. Regulation vs Input Voltage
Lo GND
VIN BOOT PH
Cd R1
GND + Co
R2
VSENSE VOUT
EN
SS/TR COMP
Rcomp
RT/CLK
Cpole
Css RT Czero
Figure 64. 24-V to - 12-V Inverting Power Supply from SLVA317 Application Note
10 Layout
Output
Capacitor Output
Topside Inductor
Ground Route Boot Capacitor
Area Catch
Trace on another layer to
provide wide path for Diode
topside ground
Input
Bypass
Capacitor BOOT PH
Vin
VIN GND
EN COMP
UVLO
SS/TR VSENSE Compensation
Adjust
Resistor
Resistors Network
RT/CLK PWRGD Divider
Slow Start
Frequency Thermal VIA
Capacitor
Set Resistor
Signal VIA
11.3 Trademarks
Eco-Mode, PowerPAD, SwitcherPro, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 2-Aug-2016
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TPS54040DGQ ACTIVE MSOP- DGQ 10 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 150 54040
PowerPAD & no Sb/Br)
TPS54040DGQR ACTIVE MSOP- DGQ 10 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 150 54040
PowerPAD & no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 2-Aug-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive: TPS54040-Q1
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Aug-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Aug-2015
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated