Book Grid Inverters

CPSS Power Electronics Series
Xinbo Ruan · Xuehua Wang

Donghua Pan · Dongsheng Yang
Weiwei Li · Chenlei Bao
Control Techniques
for LCL-Type Grid-
Connected Inverters
Series editors
Wei Chen, Fuzhou University, Fuzhou, Fujian, China
Yongzheng Chen, Liaoning University of Technology, Jinzhou, Liaoning, China
Xiangning He, Zhejiang University, Hangzhou, Zhejiang, China
Yongdong Li, Tsinghua University, Beijing, China
Jingjun Liu, Xi’an Jiaotong University, Xi’an, Shaanxi, China
An Luo, Hunan University, Changsha, Hunan, China
Xikui Ma, Xi’an Jiaotong University, Xi’an, Shaanxi, China
Xinbo Ruan, Nanjing University of Aeronautics and Astronautics, Nanjing,
Jiangsu, China
Kuang Shen, Zhejiang University, Hangzhou, Zhejiang, China
Dianguo Xu, Harbin Institute of Technology, Harbin, Heilongjiang, China
Jianping Xu, Xinan Jiaotong University, Chengdu, Sichuan, China
Mark Dehong Xu, Zhejiang University, Hangzhou, Zhejiang, China
Xiaoming Zha, Wuhan University, Wuhan, Hubei, China
Bo Zhang, South China University of Technology, Guangzhou, Guangdong, China
Lei Zhang, China Power Supply Society, Tianjin, China
Xin Zhang, Hefei University of Technology, Hefei, Anhui, China
Zhengming Zhao, Tsinghua University, Beijing, China
Qionglin Zheng, Beijing Jiaotong University, Beijing, China
Luowei Zhou, Chongqing University, Chongqing, China
This series comprises advanced textbooks, research monographs, professional
books, and reference works covering different aspects of power electronics, such as
Variable Frequency Power Supply, DC Power Supply, Magnetic Technology, New
Energy Power Conversion, Electromagnetic Compatibility as well as Wireless
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scholars and researchers and publishes authored books as well as edited
compilations. It aims to provide critical reviews of important subjects in the field,
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Supply Society and a consulting editor from Springer.
Readership: Research scientists in universities, research institutions and the

industry, graduate students, and senior undergraduates.
More information about this series at http://www.springer.com/series/15422

Xinbo Ruan Xuehua Wang
•
Donghua Pan Dongsheng Yang

•
Weiwei Li Chenlei Bao

•
Control Techniques
for LCL-Type
Grid-Connected Inverters
123
Xinbo Ruan Dongsheng Yang
College of Automation Engineering Nanjing University of Aeronautics
Nanjing University of Aeronautics and Astronautics
and Astronautics Nanjing, Jiangsu
Nanjing, Jiangsu China
China
Weiwei Li
Xuehua Wang Huazhong University of Science
Huazhong University of Science and Technology
and Technology Wuhan, Hubei
Wuhan, Hubei China
China
Chenlei Bao
Donghua Pan Huazhong University of Science
Huazhong University of Science and Technology
and Technology Wuhan, Hubei
Wuhan, Hubei China
China
ISSN 2520-8853 ISSN 2520-8861 (electronic)

ISBN 978-981-10-4276-8 ISBN 978-981-10-4277-5 (eBook)
DOI 10.1007/978-981-10-4277-5
Jointly published with Science Press, Beijing, China
ISBN: 978-7-03-043810-2 Science Press, Beijing
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Preface
Renewable energy-based distributed power generation systems (RE-DPGS) repre-

sent promising solutions to mitigate energy crisis and environmental pollution. The
LCL-type grid-connected inverter, being a conversion interface between the
renewable energy power generation units and the power grid, has been widely used
to convert dc power to high-quality ac power and feed it into the grid, and it plays
an important role in maintaining safe, stable, and high-quality operation of
RE-DPGS.
This book aims to present the control techniques for the LCL-type
grid-connected inverter to improve the system stability, control performance, and
suppression of grid current harmonics. The detailed theoretical analysis with design
examples and experimental validations are included.
This book contains twelve chapters.
Chapter 1 gives a brief review of the key techniques for the LCL-type
grid-connected inverter, including the design and magnetic integration of the LCL
filter, design of the controller parameters, the control delay effects in digital control
and the methods of reducing the control delays, suppression of the grid current
distortion caused by the grid voltage harmonics, and the grid impedance effects on
the system stability and the methods to improve the system stability.
Chapter 2 introduces the modulation strategies for the single-phase and
three-phase inverters, and presents the design methods of LCL filters for both
single-phase and three-phase inverters.
Chapter 3 presents magnetic integration methods for LCL filters, aiming to
reduce volume and weight.
In Chap. 4, the resonance hazard of LCL filters is analyzed, and six basic
passive-damping solutions are discussed in terms of their effects on the charac-
teristics of LCL filters. It is pointed out that adding a resistor in parallel with the
filter capacitor can effectively damp the resonance peak and does not affect
the frequency response of the LCL filter, but it results in high power loss. The
v
vi Preface
active-damping solutions, equivalent to a virtual resistor in parallel with the filter

capacitor, are derived, and the capacitor-current-feedback active-damping is found
superior for its simple implementation and effectiveness.
Chapter 5 presents a step-by-step parameter design method for the LCL-type
grid- connected inverter with capacitor-current-feedback active-damping, including
the capacitor current feedback coefficient and current regulator parameters.
In Chaps. 6 and 7, methods based on full feedforward of the grid voltage are
proposed for single-phase and three-phase grid-connected inverters with
capacitor-current-feedback active-damping. The feedforward function consists of a
proportional, a derivative, and a second-derivative component. The proposed full
feedforward scheme does not only reduce the steady-state error of the grid current
effectively, but also suppresses the grid current distortion arising from the har-
monics in the grid voltage.
In Chap. 8, the mechanism of the control delay in digital control systems is
discussed, and the influence of the digital control delay on the system stability and
control performance are analyzed in detail. Then, the range of the LCL filter res-
onance frequency that would lead to instability is identified and hence should
be avoided. Then, the system stability evaluation method is presented by checking
the phase margin and the gain margin at one-sixth of sampling frequency (fs/6) and
the resonance frequency of the LCL filter.
In Chap. 9, a real-time sampling method is presented to reduce the computa-
tional delay, and it is not restricted by the modulation scheme and can be applied to
the single-phase and three-phase grid-connected inverters. Furthermore, a real-time
computational method with dual sampling modes is given to completely eliminate
the computation delay, and it is suitable for the single-phase grid-connected inverter
since it is based on the unipolar SPWM. With the two computation delay reduction
methods, the steady-state and dynamic performances of the LCL-type grid-
connected inverter can be improved, and high robustness against the
grid-impedance variation is obtained.
In Chaps. 10 and 11, the virtual series–parallel impedance shaping method and
weighted-feedforward scheme of grid voltages are proposed, respectively. The
purpose is to improve the harmonic rejection capability and the stability robustness
of the LCL-type grid-connected inverter when connected into a weak grid.
In Chap. 12, the complex-vector-filter method (CVFM) is adopted to derive
various prefilters in the synchronous reference frame phase-locked loops
(SRF-PLLs), and some insights into the relationships among different prefilters are
drawn. A brief comparison is presented to highlight the features of each prefilter.
Moreover, a generalized second-order complex-vector filter (GSO-CVF) with faster
dynamic response and a third-order complex-vector filter (TO-CVF) with higher
harmonic attenuation are proposed with the help of the CVFM, which are useful to
improve the dynamic performance and the harmonic attenuation ability of the PLL
for the grid-connected inverter.
Preface vii
This book is essential and valuable reference for the graduate students and
academics majoring in power electronics and renewable energy generation system
and the engineers being engaged in developing grid-connected inverters for pho-
tovoltaic system and wind turbine generation system. Senior undergraduate students
majoring in electrical engineering and automation engineering would also find this
book useful.
Nanjing, China Xinbo Ruan

Wuhan, China Xuehua Wang
Wuhan, China Donghua Pan
Nanjing, China Dongsheng Yang
Wuhan, China Weiwei Li
Wuhan, China Chenlei Bao
The original version of the book was revised:
Bibliography has been removed from Backmatter.
ix
Acknowledgements
This research monograph summarizes the research work on the control techniques
for LCL-type grid-connected inverters since the key project of National Natural
Science Foundation of China, titled “Research on Energy Conversion, Control, and
Grid-Connection Operation of Renewable Energy Based Distributed Power
Generation Systems”, was funded in 2008.
We wish to thank the members of the key project of National Natural Science
Foundation of China: Prof. Chengxiong Mao, Prof. Buhan Zhang, Prof. Yi Luo,
Prof. Kai Zhang, Prof. Xudong Zou, and Prof. Yu Zhang from Huazhong
University of Science and Technology (HUST), Wuhan, China, and Prof. Weiyang
Wu, Prof. Chunjiang Zhang, Prof. Xiaofeng Sun, and Prof. Xiaoqiang Guo from
Yanshan University, Qinhuangdao, China, for their outstanding contribution to
this key project. We also wish to express my sincere appreciation and gratitude
to Prof. Yuan Pan, Prof. Shijie Cheng, Prof. Xianzhong Duan, Prof. Jian Chen,
Prof. Yong Kang, Prof. KexunYu, Prof. Shanxu Duan, Prof. Hua Lin, Ms. Taomin
Zou, and Ms. Yi Li in the School of Electrical and Electronic Engineering, HUST,
for their great support during the application and research of this key project.
We are grateful to Prof. Lijian Ding, Director of the Fifth Engineering Section,
Engineering and Materials Department, National Natural Science Foundation of
China, and Prof. Weiming Ma from Naval University of Engineering, Wuhan,
China, for their great support and kind encouragement.
We also wish to thank Prof. Chengshan Wang from Tianjin University, Tianjin,
China, and Prof. An Luo from Hunan University, Changsha, China, for inviting me
to participate in the project of National Basic Research Program of China (973
Program), titled “Research on the Fundamentals of Distributed Power Generation
and Supply Systems”.
Special thanks are due to Prof. Chi. K. Tse from Hong Kong Polytechnic
University for his suggestions in the writing of this book, which have led to
improvements in clarity and readability.
The work in this book was supported by the National Natural Science
Foundation of China under Award 50837003, the National Basic Research Program
xi
xii Acknowledgements
of China (973 Program) under Award 2009CB219706, and Jiangsu Province 333
Program for Excellent Talents under Award BRA2012141. I would like to express
my sincere thanks to these supports.
It has been a great pleasure to work with the colleagues of Springer, Science
Press, China, and China Power Supply Society (CPSS). The support and help from
Mr. Wayne Hu (the project editor) are greatly appreciated.
January 2017
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 1
1.1 Energy Situation and Environmental Issues . . . . . . . . . . . . .... 1
1.2 Renewable Energy-Based Distributed Power Generation
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Key Issues of LCL-Type Grid-Connected Inverters . . . . . . . . . . 4
1.3.1 Design and Magnetic Integration of LCL Filter . . . . . . . 6
1.3.2 Resonance Damping Methods of LCL Filter . . . . . . . . . 7
1.3.3 Controller Design of Grid-Connected Inverters . . . . . . . 8
1.3.4 Effects of Control Delay and the Compensation
Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 13
1.3.5 Suppression of Grid Current Distortion Caused
by Grid Voltage Harmonics . . . . . . . . . . . . . . . . . . .... 16
1.3.6 Grid-Impedance Effects on System Stability
and the Improvement Methods . . . . . . . . . . . . . . . .... 22
1.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 23
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 23
2 Design of LCL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.1 PWM for Single-Phase Full-Bridge Grid-Connected Inverter . . 32
2.1.1 Bipolar SPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.1.2 Unipolar SPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2 PWM for Three-Phase Grid-Connected Inverter . . . . . . . . . . . . . 37
2.2.1 SPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.2.2 Harmonic Injection SPWM Control . . . . . . . . . . . . . . . . 41
2.3 LCL Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.3.1 Design of the Inverter-Side Inductor . . . . . . . . . . . . . . . 47
2.3.2 Filter Capacitor Design . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.3.3 Grid-Side Inductor Design . . . . . . . . . . . . . . . . . . . . . . . 55
2.4 Design Examples for LCL Filter . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.4.1 Single-Phase LCL Filter . . . . . . . . . . . . . . . . . . . . . . . . . 57
xiii
xiv Contents
2.4.2 Three-Phase LCL Filter . . . . . . . . . . . . . . . . . . . . . . . . . 58

2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3 Magnetic Integration of LCL Filters . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.1 Magnetic Integration of LCL Filters . . . . . . . . . . . . . . . . . . . . . . 64
3.1.1 Magnetic Integration of Single-Phase LCL Filter . . . . . . 64
3.1.2 Magnetic Integration of Three-Phase LCL Filter . . . . . . 66
3.2 Coupling Effect on Attenuating Ability of LCL Filter . . . . . . . . . 67
3.2.1 Magnetic Circuit of Integrated Inductors . . . . . . . . . . . . 67
3.2.2 Characteristics of LCL Filter with Coupled
Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.3.1 Magnetics Design for Single-Phase LCL Filter . . . . . . . 71
3.3.2 Magnetics Design for Three-Phase LCL Filter . . . . . . . . 73
3.4 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.4.1 Experimental Results for Single-Phase LCL Filter . . . . . 74
3.4.2 Experimental Results for Three-Phase LCL Filter . . . . . 76
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4 Resonance Damping Methods of LCL Filter . . . . . . . . . . . . . . . . . . . 79
4.1 Resonance Hazard of LCL Filter . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.2 Passive-Damping Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.2.1 Basic Passive Damping . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.2.2 Improved Passive Damping . . . . . . . . . . . . . . . . . . . . . . 85
4.3 Active-Damping Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.3.1 State-Variable-Feedback Active Damping . . . . . . . . . . . 88
4.3.2 Notch-Filter-Based Active Damping . . . . . . . . . . . . . . . 90
4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5 Controller Design for LCL-Type Grid-Connected Inverter
with Capacitor-Current-Feedback Active-Damping . . . . . . . . . . . . . 95
5.1 Modeling LCL-Type Grid-Connected Inverter . . . . . . . . . . . . . . 96
5.2 Frequency Responses of Capacitor-Current-Feedback
Active-Damping and PI Regulator . . . . . . . . . . . . . . . . . . . . . . . 99
5.3 Constraints for Controller Parameters . . . . . . . . . . . . . . . . . . . . . 101
5.3.1 Requirement of Steady-State Error . . . . . . . . . . . . . . . . 101
5.3.2 Controller Parameters Constrained by Steady-State
Error and Stability Margin . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.3 Pulse-Width Modulation (PWM) Constraint . . . . . . . . . 104
5.4 Design Procedure for Capacitor-Current-Feedback
Coefficient and PI Regulator Parameters . . . . . . . . . . . . . . . . . . . 105
5.5 Extension of the Proposed Design Method . . . . . . . . . . . . . . . . . 107
Contents xv
5.5.1 Controller Design Based on PI Regulator

with Grid Voltage Feedforward Scheme . . . . . . . . . . . . 107
5.5.2 Controller Design Based on PR Regulator. . . . . . . . . . . 108
5.6 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.6.1 Design Results with PI Regulator . . . . . . . . . . . . . . . . . 111
5.6.2 Design Results with PR Regulator. . . . . . . . . . . . . . . . . 112
5.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6 Full-Feedforward of Grid Voltage for Single-Phase LCL-Type
Grid-Connected Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.2 Effects of the Grid Voltage on the Grid Current . . . . . . . . . . . . . 122
6.3 Full-Feedforward Scheme for Single-Phase LCL-Type
Grid-Connected Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3.1 Derivation of Full-Feedforward Function of Grid
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3.2 Discussion of the Three Feedforward Components . . . . 128
6.3.3 Discussion of Full-Feedforward Scheme with Main
Circuit Parameters Variations . . . . . . . . . . . . . . . . . . . . 130
6.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7 Full-Feedforward Scheme of Grid Voltages for Three-Phase
LCL-Type Grid-Connected Inverters . . . . . . . . . . . . . . . . . . . . . .... 139
7.1 Modeling the Three-Phase LCL-Type Grid-Connected
Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 140
7.1.1 Model in the Stationary a–b Frame . . . . . . . . . . . . .... 140
7.1.2 Model in the Synchronous d–q Frame . . . . . . . . . . .... 143
7.2 Derivation of the Full-Feedforward Scheme
of Grid Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 145
7.2.1 Full-Feedforward Scheme in the Stationary a–b
Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 145
7.2.2 Full-Feedforward Scheme in the Synchronous d–q
Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 146
7.2.3 Full-Feedforward Scheme in the Hybrid Frame . . . .... 147
7.3 Discussion of the Full-Feedforward Functions . . . . . . . . . . .... 150
7.3.1 Discussion of the Effect of Three Components
in the Full-Feedforward Function . . . . . . . . . . . . . .... 151
7.3.2 Harmonic Attenuation Affected by LCL Filter
Parameter Mismatches . . . . . . . . . . . . . . . . . . . . . . .... 154
xvi Contents
7.3.3 Comparison Between the Feedforward Functions

for the L-Type and the LCL-Type Three-Phase
Grid-Connected Inverter . . . . . . . . . . . . . . . . . . . . . . . . 154
7.4.1 Description of the Prototype . . . . . . . . . . . . . . . . . . . . . 155
7.4.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
8 Design Considerations of Digitally Controlled LCL-Type
Grid-Connected Inverter with Capacitor-Current-Feedback
Active-Damping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
8.2 Control Delay in Digital Control System . . . . . . . . . . . . . . . . . . 167
8.3 Effect of Control Delay on Loop Gain and
Capacitor-Current-Feedback Active-Damping . . . . . . . . . . . . . . . 168
8.3.1 Equivalent Impedance of Capacitor-Current-Feedback
Active-Damping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.3.2 Discrete-Time Expression of the Loop Gain . . . . . . . . . 172
8.3.3 RHP Poles of the System Loop Gain . . . . . . . . . . . . . . 174
8.4 Stability Constraint Conditions for Digitally Controlled
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
8.4.1 Nyquist Stability Criterion . . . . . . . . . . . . . . . . . . . . . . . 176
8.4.2 System Stability Constraint Conditions . . . . . . . . . . . . . 177
8.5 Design Considerations of the Controller Parameters of
Digitally Controlled LCL-Type Grid-Connected Inverter . . . . . . 179
8.5.1 Forbidden Region of the LCL Filter Resonance
Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
8.5.2 Constraints of the Controller Parameters . . . . . . . . . . . . 180
8.5.3 Design of LCL Filter, PR Regulator and
Capacitor-Current-Feedback Coefficient . . . . . . . . . . . . . 182
8.6 Design of Current Regulator for Digitally Controlled
LCL-Type Grid-Connected Inverter Without Damping . . . . . . . . 183
8.6.1 Stability Necessary Constraint for Digitally
Controlled LCL-Type Grid-Connected Inverter
Without Damping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
8.6.2 Design of Grid Current Regulator and Analysis
of System Performance . . . . . . . . . . . . . . . . . . . . . . . . . 184
8.7 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
8.7.1 Design Example with Capacitor-Current-Feedback
Active-Damping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
8.7.2 Design Example Without Damping . . . . . . . . . . . . . . . . 190
8.8.1 Experimental Validation for the Case
with Capacitor-Current-Feedback Active-Damping . . . . 191
Contents xvii
8.8.2 Experimental Validation Without Damping . . . . . . .... 193

8.9 Comparison of System Performance with Three Control
Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 194
8.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 195
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 196
9 Reduction of Computation Delay for Improving Stability and
Control Performance of LCL-Type Grid-Connected Inverters . . . . . 197
9.1 Effects of Computation and PWM Delays . . . . . . . . . . . . . . . . . 198
9.1.1 Modeling the Digitally Controlled LCL-Type
Grid-Connected Inverter . . . . . . . . . . . . . . . . . . . . . . . . 198
9.1.2 Improvement of Damping Performance
with Reduced Computation Delay . . . . . . . . . . . . . . . . . 202
9.1.3 Improvement of Control Performance
with Reduced Computation Delay . . . . . . . . . . . . . . . . . 205
9.2 Real-Time Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
9.2.1 Sampling-Induced Aliasing of the Capacitor Current . . . 208
9.2.2 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
9.2.3 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . 212
9.3 Real-Time Computation Method with Dual Sampling
Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
9.3.1 Derivation of the Real-Time Computation Method . . . . 215
9.3.2 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
9.3.3 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . 221
9.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
10 Impedance Shaping of LCL-Type Grid-Connected Inverter
to Improve Its Adaptability to Weak Grid . . . . . . . . . . . . . . . . .... 227
10.1 Derivation of Impedance-Based Stability Criterion
for Grid-Connected Inverter . . . . . . . . . . . . . . . . . . . . . . . . .... 228
10.2 Output Impedance Model of Grid-Connected Inverter . . . . .... 229
10.3 Relationship Between Output Impedance and Control
Performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
10.4 Output Impedance Shaping Method . . . . . . . . . . . . . . . . . . . . . . 233
10.4.1 Parallel Impedance Shaping Method . . . . . . . . . . . . . . . 234
10.4.2 Series–Parallel Impedance Shaping Method. . . . . . . . . . 236
10.4.3 Discussion of the Series–Parallel Impedance
Shaping Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
10.5.1 Prototype Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
10.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
xviii Contents
11 Weighted-Feedforward Scheme of Grid Voltages

for the Three-Phase LCL-Type Grid-Connected Inverters
Under Weak Grid Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 249
11.1 Impedance-Based Stability Criterion . . . . . . . . . . . . . . . . . . .... 250
11.2 Stability Analysis Under Weak Grid Condition . . . . . . . . . .... 251
11.2.1 Derivation of Output Impedance of
Grid-Connected Inverter . . . . . . . . . . . . . . . . . . . . .... 251
11.2.2 Stability of Grid-Connected Inverter Under Weak
Grid Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 254
11.3 Characteristics of the Inverter Output Impedance . . . . . . . . .... 255
11.3.1 Characteristics of the Inverter Output Impedance
Without Feedforward Scheme . . . . . . . . . . . . . . . . .... 256
11.3.2 Inverter Output Impedance Affected by the
Full-Feedforward Scheme . . . . . . . . . . . . . . . . . . . .... 257
11.4 Weighted-Feedforward Scheme of Grid Voltages . . . . . . . . .... 259
11.4.1 The Proposed Weighted-Feedforward Scheme
of Grid Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . .... 259
11.4.2 Realization of the Weighted-Feedforward Scheme
of Grid Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
11.4.3 Tuning of the Weighted Coefficients . . . . . . . . . . . . . . . 262
11.5.1 Stability Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
11.5.2 Harmonic Suppression Test . . . . . . . . . . . . . . . . . . . . . . 266
11.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
12 Prefilter-Based Synchronous Reference Frame Phase-Locked
Loop Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
12.2 Operation Principle of SRF-PLL . . . . . . . . . . . . . . . . . . . . . . . . . 272
12.3 Prefilter-Based SRF-PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
12.3.1 Complex-Vector-Filter Method (CVFM) . . . . . . . . . . . . 275
12.3.2 Derivation of the Prefilters with the CVFM. . . . . . . . . . 277
12.4 Generalized Second-Order Complex-Vector Filter . . . . . . . . . . . 285
12.5 Third-Order Complex-Vector Filter. . . . . . . . . . . . . . . . . . . . . . . 287
12.6 Simulation and Experimental Verification . . . . . . . . . . . . . . . . . . 289
12.6.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
12.6.3 Brief Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
12.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
About the Authors
Xinbo Ruan was born in Hubei Province, China, in 1970. He received the B.S. and
Ph.D. degrees in electrical engineering from Nanjing University of Aeronautics and
Astronautics (NUAA), Nanjing, China, in 1991 and 1996, respectively.
In 1996, he joined the Faculty of Electrical Engineering Teaching and Research
Division, NUAA, where he became a professor in the College of Automation
Engineering in 2002 and has been engaged in teaching and research in the field of
power electronics. From August to October 2007, he was a research fellow in the
Department of Electronic and Information Engineering, Hong Kong Polytechnic
University, Hong Kong, China. From March 2008 to August 2011, he was also with
the School of Electrical and Electronic Engineering, Huazhong University of
Science and Technology, China. He is a guest professor at Beijing Jiaotong
University, Beijing, China, Hefei University of Technology, Hefei, China, and
Wuhan University, Wuhan, China. He is the author or co-author of seven books and
more than 300 technical papers published in journals and conferences. His main
research interests include soft-switching dc–dc converters, soft-switching inverters,
power factor correction converters, modeling the converters, power electronics
system integration, and renewable energy generation system.
Dr. Ruan was a recipient of the Delta Scholarship by the Delta Environment and
Education Fund in 2003 and was a recipient of the Special Appointed Professor
of the Chang Jiang Scholars Program by the Ministry of Education, China, in 2007.
From 2005 to 2013, he served as vice president of the China Power Supply Society.
From 2014 to 2016, he served as vice chair of the Technical Committee on
Renewable Energy Systems within the IEEE Industrial Electronics Society.
Currently, He is an associate editor for the IEEE Transactions on Industrial
Electronics, IEEE Transactions on Power Electronics, IEEE Transactions on
Circuits and System II, and the IEEE Journal of Emerging and Selected Topics on
Power Electronics. He was elevated to IEEE fellow in 2015.
Xuehua Wang was born in Hubei Province, China, in 1978. He received the B.S.
degree in electrical engineering from Nanjing University of Technology, Nanjing,
China, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from
xix
xx About the Authors
Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 2004 and

2008, respectively.
From October 2008 to March 2011, he was a postdoctoral fellow at Huazhong
University of Science and Technology (HUST), Wuhan, China. Since April 2011,
he joined the School of Electrical and Electronic Engineering, HUST, and he is
currently an associate professor. His main research interests include multilevel
inverter and renewable energy generation system.
Donghua Pan was born in Hubei Province, China, in 1987. He received the B.S.
and Ph.D. degrees in electrical and electronic engineering from Huazhong
University of Science and Technology, Wuhan, China, in 2010 and 2015, respec-
tively.
He is currently a research engineer with Suzhou Inovance Technology Co., Ltd.,
Suzhou, China. His research interests include magnetic integration technique and
renewable energy generation system.
Dongsheng Yang was born in Jiangsu, China, in 1984. He received the B.S., M.S.,
and Ph.D. degrees, all in electrical engineering from Nanjing University of
Aeronautics and Astronautics, Nanjing, China, in 2008, 2011, and 2016, respec-
tively.
He is currently a postdoctoral fellow at Aalborg University, Denmark. His main
research interests include grid-connected inverter control and renewable energy
generation systems.
Weiwei Li was born in Henan Province, China, in 1987. He received the B.S. and
Ph.D. degrees in electrical engineering from Huazhong University of Science and
Technology, Wuhan, China, in 2009 and 2014, respectively.
He is currently a research assistant in SEPRI of China Southern Power Grid Co.,
Ltd, Guangzhou, China. His research interests include HVDC power transmission,
dc distribution, and renewable energy generation systems.
Chenlei Bao was born in Zhejiang Province, China, in 1987. He received the B.S.
degree in electrical engineering and automation from Harbin Institute of
Technology, Harbin, China, in 2010, and the M.S. degree in electrical engineering
from Huazhong University of Science and Technology, Wuhan, China, in 2013.
In April 2013, he joined the Shanghai Marine Equipment Research Institute,
Shanghai, China. His current research interests include digital control technique and
renewable energy generation system.
Abbreviations
ANF Adaptive notch filter

ASM Averaged switch model
CVF Complex vector filter
CVFM Complex-vector-filter method
DPGS Distributed power generation system
DSC Delayed signal cancellation
DSP Digital signal processor
E-PLL Enhanced phase-locked loop
FNC Fundamental negative-sequence components
FPC Fundamental positive-sequence components
GSO-CVF Generalized second-order complex-vector filter
LF Loop filter
LPF Low-pass filter
MAF Moving average filter
NF Notch filter
PCC Point of common coupling
PD Phase detector
PF Power factor
PI Proportional integral
PLL Phase-locked loop
PO Percentage overshoot
PR Proportional resonant
PSF Positive-sequence filter
PU Per unit
PWM Pulse-width modulation
Q-PLL Quadrature phase-locked loop
RE-DPGS Renewable energy-based distributed power generation system
RHP Right half plane
RMS Root-mean-square
R/P Reserves to production
xxi
xxii Abbreviations
SGT Sliding Goertzel transform

SO Symmetrical optimum
SO-CVF Second-order complex-vector filter
SOF Second-order scalar filter
SOGI Second-order generalized integrator
SPWM Sinusoidal pulse-width modulation
SRF-PLL Synchronous reference frame PLL
THD Total harmonic distortion
TO Technical optimum
TO-CVF Third-order complex-vector filter
VCO Voltage-controlled oscillator
VSI Voltage source inverter
ZC-PLL Zero-crossing PLL
ZOH Zero-order hold
Chapter 1
Introduction
Abstract After 200 years of continuous extraction and recent massive consump-
tion, fossil fuels have rapidly become depleted. At the same time, the process of
consuming fossil energy has produced a large amount of waste, which has seriously
polluted the environment, jeopardizing the long-term sustainability of development
of our society. The renewable energy-based distributed power generation system
(RE-DPGS) has been attracting a great deal of attention due to its sustainable and
environmental-friendly features, and its use represents an effective approach to
dealing with future energy shortage and environmental pollution. As the energy
conversion interface between the renewable energy power generation units and the
grid, the grid-connected inverter plays an important role for the safe, stable, and
high-quality operation of RE-DPGS. The worldwide energy situation is first
reviewed in this chapter, and then, the typical configurations and the advantages of
the RE-DPGS are introduced. The key control technologies of the LCL-type
grid-connected inverter are also systematically elaborated including: (1) design and
magnetic integration of LCL filter, (2) resonance damping methods, (3) design of
controller parameters, (4) control delay effects and the compensation methods,
(5) suppressing grid current distortion caused by grid-voltage harmonics, and
(6) grid-impedance effects on system stability and the improvement methods.

Keywords Renewable energy Distributed power generation Grid-connected

inverter LCL filter Phase-locked loop (PLL)
1.1 Energy Situation and Environmental Issues
Fossil energy is the cornerstone of modern civilization. After 200 years of con-
tinuous extraction and recent massive consumption, fossil fuels have rapidly
become depleted. At the same time, the process of consuming fossil energy has
produced a large amount of waste, which has seriously polluted the environment,
jeopardizing the long-term sustainability of development of our society. Table 1.1
shows the consumption shares and reserves-to-production (R/P) ratios of various
© Springer Nature Singapore Pte Ltd. and Science Press 2018 1

X. Ruan et al., Control Techniques for LCL-Type Grid-Connected Inverters,
CPSS Power Electronics Series, DOI 10.1007/978-981-10-4277-5_1
2 1 Introduction
Table 1.1 Consumption shares and R/P ratios of various primary energy sources in 2015
Energy Oil Natural Coal Hydroelectricity Nuclear Renewable
gas energy energy
Shares (%) 32.9 23.8 29.2 6.8 4.4 2.8
R/P ratios 50.7 52.8 114 – – –
(year)
primary energy sources in 2015 [1]. The R/P ratio, expressed in time, refers to the
ratio of the energy reserves to the energy production in the same year, reflecting the
remaining amount of energy source or the sustainability of the particular form of
energy supply. As shown in Table 1.1, the fossil energy, including oil, coal, and
natural gas, was still the dominant source of energy, accounting for a total of 85.9%
of the global primary energy consumption. However, of these three kinds of fossil
energy, only coal has an R/P ratio exceeding 100 years, and the others’ are less than
60 years.
To cope with problems associated with environmental pollution and the rapid
depletion of fossil fuels, tremendous efforts have been made to improve the effi-
ciency of energy utilization, reduce the energy consumptions, and lower the amount
of carbon emissions. Meanwhile, new clean energy and renewable energy have
been developed and adopted rapidly for the purpose of sustaining the energy
supply. As listed in Table 1.1, the hydroelectricity and renewable energy accounted
for 6.8% and 2.8% of the global energy consumption, respectively, in 2015. Being
the most promising forms of renewable energy, the use of wind energy and solar
energy has increased exponentially, and they will continue to play an important role
in the future energy markets.
1.2 Renewable Energy-Based Distributed Power

Generation System
Renewable energy sources, including wind and solar energy, are available over
wide geographical areas, and the utilization of renewable energy sources has caused
a significantly lower level of pollution to the environment. As a result, extensive
support policies and financial incentives have been implemented to promote the
deployment and commercialization of renewable energy in many countries [2].
The renewable energy-based distributed power generation system (RE-DPGS)
has recently become a significant development direction toward achieving a
large-scale utilization of renewable energy. The RE-DPGS is usually located in the
proximity of the load center and can be operated flexibly in either standalone mode
or grid-connected mode. The RE-DPGS has many advantages, including:
1. Environmental friendliness. The generation of renewable energy causes less
environmental pollution and produces zero carbon emission.
1.2 Renewable Energy-Based Distributed Power Generation System 3
2. Enhanced energy security. The utilization of renewable energy helps to alleviate

the energy shortage problem and reduce the dependence on energy import.
3. Low power loss. The RE-DPGS is usually located close to the load center, and
electricity is generated near where it is used. This eliminates the power loss due
to long-distance transmission.
4. High reliability. When a power grid fault happens, the RE-DPGS can be
operated as an uninterrupted power supply for the local loads, and it can help the
grid to restore from faults.
5. Cost-effectiveness. Compared with a large-scale centralized generation station, a
single RE-DPGS has relatively small capacity. Thus, the cost of installation and
construction is significantly reduced.
The electrical power generated by RE-DPGS accounted for 6.7% of the global
power generation in 2015, with a growth of 15.2% over 2014, contributing 97% of
the growth in the global power generation in 2015 [1]. In fact, the renewable energy
sources are already playing an important role in some countries. Denmark leads,
with 66% of power coming from renewables, followed by Portugal with 30%.
Among the larger EU economies, the renewables share is 27% in Germany, 24% in
Spain, and 23% in both Italy and the UK.
Figure 1.1 shows the typical configurations of RE-DPGS integrating the wind
and solar energy, where the energy storage devices, i.e., flywheel, battery, and
supercapacitor, are used to absorb the random power fluctuation of the renewable
energy generators [3–6]. Figure 1.1a shows the RE-DPGS with a dc bus, where all
the renewable energy generators and energy storage devices are connected to the dc
bus through dc–dc converters or ac–dc converters. Then, a dc–ac inverter (i.e., the
grid-connected inverter) converts the dc-bus voltage to an ac voltage and transfers
power to the utility grid through a step-up transformer [7, 8]. The dc-bus config-
uration has been widely used in small-scale DPGS for convenience of control and
the use of interface of renewable energy to the system. The RE-DPGS with ac bus is
shown in Fig. 1.2b, where all the renewable energy generators and energy storage
devices are connected to the ac bus. Then, the ac bus is connected to the utility grid
through a step-up transformer [9, 10]. Since each of the renewable energy gener-
ators and energy storage devices is interfaced with a grid-connected inverter, the
capacity of the grid-connected inverter is reduced and its reliability can be
improved.
As shown in Fig. 1.1, power electronic converters are indispensable in the
RE-DPGS. As the power conversion interface between the renewable energy
sources and the utility grid, the grid-connected inverters are used to convert the dc
power to the high-quality ac power and feed it into the grid, and they play an
important role in the RE-DPGS for achieving safe, stable, and high-quality
operation.
4 1 Introduction
dc bus 10 kV ac bus
Wind
Turbine G ac-dc
dc-ac Grid
Solar dc-dc
Array
Load
Flywheel M ac-dc
Battery dc-dc
Super dc-dc
Capacitor
(a) RE-DPGS with dc bus
ac bus 10 kV ac bus
Wind
Turbine G ac-dc-ac
Grid
Solar
Array dc-ac
Load
Flywheel M ac-dc-ac
Battery dc-ac
Super dc-ac
Capacitor
(b) RE-DPGS with ac bus
Fig. 1.1 Typical configurations of RE-DPGS
1.3 Key Issues of LCL-Type Grid-Connected Inverters
Grid-connected inverters can be either single-phase ones or three-phase ones.

Single-phase inverters are mainly used in small-volume resident power generation
system, while three-phase inverters are widely employed in large-scale distributed
power station involving renewable energy. In the grid-connected inverters, a filter is
needed to attenuate the switching harmonics generated from pulse-width modula-
tion (PWM). Usually, an L filter and an LCL filter are the two alternatives, as shown
in Fig. 1.2a, b, respectively. The L filter is formed by a single inductor L, and the
LCL filter is composed of two inductors L1 and L2 and a capacitor C. Compared
1.3 Key Issues of LCL-Type Grid-Connected Inverters 5
L L1 L2
A A
iL + i1 +
iC i2
Vin vg Vin C vg
– –
B B
(a) L filter (b) LCL filter
Magnitude (dB)
90
Phase (°)
180
270 L filter
LCL filter
fr
Frequency (Hz)
(c) Frequency responses of the two kinds of filters
Fig. 1.2 Configurations and frequency responses of the L filter and LCL filter
with the L filter, the LCL filter has an additional capacitor branch which can bypass
high-frequency current harmonics, thus allowing the use of smaller inductors to
meet the harmonic limits [11–13]. However, the LCL filter suffers from resonance
problem. At the resonance frequency fr, there is a high resonance peak, while a
sharp phase step down of −180° occurs, as shown in Fig. 1.2c. If this resonance
peak is not properly damped, it would lead to grid current oscillation or even system
instability [14, 15]. Due to this resonance hazard, the control of LCL-type
grid-connected inverter has been attracting much more interests and efforts.
The quality of the injected power into the grid and the system stability are the
two important aspects of the LCL-type grid-connected inverter. Specifically, the key
issues are summarized as follows.
1. Design of LCL filter. The LCL filter parameters need to be properly chosen to
limit the grid current harmonics. Furthermore, in order to reduce the volume of
magnetic components, the two inductors of an LCL filter can be integrated into
one.
2. Damping LCL filter resonance. Resonance of the LCL filter will cause system
instability. In order to ensure system stability, damping is required, and the
controller parameters should be properly designed.
6 1 Introduction
3. Stability problem caused by the digital control delays. If digital control is

employed in the grid-connected inverter, there will be computation and PWM
delays. These control delays will change the characteristics of the resonance
damping and degrade the control performance of thegrid current loop. Thus,
proper control strategies should be adopted to alleviate the effects of control
delays.
4. Impacts of grid voltage harmonics. The local nonlinear loads, e.g., arc welding
machine, electric rail transport, and saturated transformer, always generate
harmonic currents. The harmonic currents flow through the line impedance,
causing distortion of the grid voltage at the point of common coupling (PCC)
[16]. The grid-voltage distortion not only decreases the injected power quality,
but also degrades the tracking performance of the phase-locked loop. Thus,
efforts should be made to reduce the impacts of grid-voltage harmonics by
properly controlling the grid-connected inverters.
5. Effects of grid impedance on system stability. Generally, the grid at the PCC can
be represented by an ideal voltage source in series with grid impedance. The
grid impedance has effects on the system stability of the grid-connected inverter.
To address these issues, extensive work has been conducted in the past decades, and
they are briefly reviewed in the following.
1.3.1 Design and Magnetic Integration of LCL Filter
The LCL filter aims to reduce the switching harmonics at the grid side. When
designing the LCL filter, the following three constraints must be taken into account.
1. Individual harmonic and total harmonic distortion (THD) of the grid current.
Table 1.2 shows the current harmonic limits in IEEE std. 929-2000 [17] and
IEEE std. 1547-2003 [18]. The LCL filter parameters need to be designed to
meet these limitations.
2. Current ripple at the inverter side. To reduce the core loss of the inverter-side
inductor and the conduction loss of power switches, the current ripple at the
inverter side should be limited.
3. Reactive power introduced by the filter capacitor. Limiting the reactive power of
the filter capacitor is helpful to reduce the current stress of power switches.
Table 1.2 Current harmonic limits in percent of rated current

Harmonic order h < 11 11 h < 17 17 h < 23 23 h < 35 35 h THD
h (odd
harmonics)*
Percent (%) 4.0 2.0 1.5 0.6 0.3 5.0
*Even harmonics are limited to 25% of the odd harmonic limits above
Based on the above constraints, the design procedure for the LCL filter will be
presented in Chap. 2.
An LCL filter has two individual inductors. In order to reduce the volume of
magnetic components, these two inductors can be integrated into one. Magnetic
integration techniques have been widely used in switching-mode power supplies,
especially in dc–dc converters. According to the presence of coupling between the
integrated magnetic components, the magnetic integration techniques can be clas-
sified into two types, namely decoupled magnetic integration and coupled magnetic
integration [19, 20].
With decoupled magnetic integration, the fluxes generated by the windings of
different magnetic components are independent. Thus, the integrated magnetic
components keep the same characteristics as the discrete ones. The fundamental
principle of decoupled magnetic integration is introduced in Ref. [19]. By utilizing
an ungapped magnetic leg as the common flux path and arranging the windings
properly, the fluxes generated by different windings are largely canceled out in the
common leg. As a result, the cross-sectional area of the common leg can be reduced
due to the low flux, and the size of the magnetic core can be reduced. Based on this
principle, for example, integration can be achieved for the two inductors of an
interleaved quasi-square-wave dc–dc converter [21], the two transformers of an
asymmetrical half-bridge converter [22], as well as the inductor and the transformer
for an LLC resonant converter [23].
With coupled magnetic integration, the fluxes generated by the windings of
different magnetic components are coupled to certain degree, and the characteristics
of integrated magnetic components are thus different from the discrete ones. In
some particular applications, coupled magnetic integration can improve the
steady-state or dynamic performances of the converters. For example, by selecting a
proper method of coupling, the inductor current ripple can be reduced in interleaved
dc–dc converters [24–26], and even zero current ripple can be achieved in the Cuk
converter [27] and multioutput buck-derived dc–dc converters [28].
The decoupled magnetic integration of the two inductors in the LCL filter will be
presented in Chap. 3 of this book for the purpose of reducing the overall size of the
LCL filter while maintaining the same harmonic attenuation ability.
1.3.2 Resonance Damping Methods of LCL Filter
Basically, methods for resonance damping of LCL filter can be classified into two
types, namely passive damping and active damping. Passive-damping methods are
very simple since only a resistor is required to be inserted into the LCL filter.
Among which, connecting a resistor in parallel with the filter capacitor shows the
best damping performance, and the magnitude-frequency characteristics of LCL
filter remain unchanged at the low- and high-frequency ranges, but the power loss
in the damping resistor is relatively large, leading to reduced efficiency [29].
Comparatively, connecting a resistor in series with the filter capacitor has been
8 1 Introduction
widely used since the power loss in the damping resistor is lower, but the
high-frequencyharmonic attenuation ability of the LCL filter is weakened. In order
to retain the high-frequency harmonic attenuation, the filter capacitor can be split
into two, and the damping resistor is connected in series with one of the two
capacitors. Furthermore, an inductor can be connected in parallel with the damping
resistor to provide the flowing path for the fundamental current of the filter
capacitor, thus reducing the power loss in the damping resistor [30].
In order to avoid power loss in the damping resistor, the concept of virtual
resistor has been proposed to replace the passive one. The virtual resistor is realized
by specific control algorithms, which are referred to as active-damping methods
[31–33]. Through equivalent transformation of the control block diagram, it has
been proven that proportional feedback of the capacitor current is equivalent to a
virtual resistor connected in parallel with the filter capacitor [33]. Besides the use of
a virtual resistor, there are other active-damping methods, which are implemented
with pole-zero placement based on state-space model [34, 35], predictive control
[36, 37], and h-infinity control [38–41], etc.
In Chap. 4, a comparative study of various passive- and active-damping methods
will be given. The capacitor-current-feedback active damping is chosen in this book
due to its effectiveness and simple implementation.
1.3.3 Controller Design of Grid-Connected Inverters
1.3.3.1 Classification of Control Schemes
Besides damping the resonance peak of the LCL filter, appropriate choice of the
controller parameters is also important to ensure the stable operation of the
grid-connected inverter. The control schemes for the grid-connected inverter can be
classified into voltage-controlled schemes and current-controlled schemes.
Voltage-controlled schemes are usually referred to amplitude-phase control.
Based on the LCL filter model, the amplitude and phase of the inverter bridge
output voltage can be calculated according to the grid voltage and the command of
inverter output power. By regulating the inverter bridge output voltage, the grid
current can be indirectly controlled, thereby the inverter output power can be
controlled [42–44]. The control structure is simple, and no current sensor is needed.
However, the voltage-controlled schemes are based on the steady-state sinusoidal
model and the grid current is under open-loop control. As a result, the dynamics
response of the system is poor, and the ability of suppressing the harmonics and
unbalanced components in the grid current caused by the grid-voltage distortion is
also poor.
Current-controlled schemes can be classified into direct current control and
indirect current control. In the direct current control, the grid current is fed back and
directly regulated with a closed loop [34, 45]. Thus, fast dynamic response and
good disturbance rejection ability of the grid current can be achieved. In the indirect
L1 vC L2
+ i1 iC i2
Vin vinv C vg
–
Hi1 Hi2 Hv
Sinusoidal PWM PLL

cos
vM – + – + i2*
Gi(s) I*
Control System
Fig. 1.3 Single-phase LCL-type grid-connected inverter with capacitor-current-feedback

active-damping
current control, however, it is the inverter-side inductor current that is fed back and
regulated [31, 46]. Since the inverter-side inductor current is the sum of the grid
current and the filter capacitor current, the grid current is indirectly controlled. The
indirect current control can be regarded as the direct current control plus partial
capacitor-current-feedback active-damping [47]. In this book, the direct current
control with capacitor-current-feedback active-damping is studied, as shown in
Fig. 1.3, where the phase of the grid current reference is obtained through the
phase-locked loop (PLL) so as to synchronize with the grid voltage. The amplitude
of the grid current reference is determined by the outer voltage loop. Since the
bandwidth of the voltage loop is far narrower than that of the grid current loop, it is
reasonable to consider the voltage loop as being decoupled from the grid current
loop [48].
Three-phase three-wire grid-connected inverters are widely used in high-power
system. The closed-loop system can be designed in the stationary a–b frame [49], as
shown in Fig. 1.4a, or in the synchronous d–q frame, as shown in Fig. 1.4b. The
advantage of the former one is that the three-phase grid-connected inverter can be
equivalently transformed into two independent single-phase grid-connected
inverters, resulting in a simple control algorithm. The advantage of the latter one
is that zero steady-state error of the grid current can be achieved with a simple
proportional-integral (PI) regulator.
1.3.3.2 Closed-Loop Design Targets
In the control systems of the LCL-type grid-connected inverter shown in Figs. 1.3
and 1.4, the capacitor-current-feedback coefficient and the grid current regulator
10 1 Introduction
L1 L2
L1 L2
Vin
L1 L2
C C C
PWM
Modulator
iCa iCb N iCc i2a i2b i2c vgc vgb N' vga
/abc abc/ abc/ abc/
sin
iC – i2 –
+ + i2
Gi(s) I*
iC i2 cos
– – i2
+ Gi(s) +
(a) Stationary - frame

L1 L2
L1 L2
Vin
L1 L2
C C C
PWM
Modulator
iCa iCb N iCc i2a i2b i2c vgc vgb N' vga
dq/abc abc/dq abc/dq abc/dq
iCd – i2d – *
I2d
+ Gi(s) +
iCq – i2q – *
I2q
+ Gi(s) +
(b) Synchronous d-q frame
Fig. 1.4 Control structure of the three-phase LCL-type grid-connected inverter
should be tuned to meet the performance and stability requirements. The key design
targets are as follows: (1) small steady-state error of the grid current; (2) fast
dynamic response and low overshoot; and (3) low THD of the grid current [50, 51].
These design targets are related to the crossover frequency, phase margin, gain
margin, and the loop gain in the low-frequency range [52].
Recently, much work has been devoted to the closed-loop design of the LCL-
type grid-connected inverter. In Refs. [45, 53], the root locus method and pole-zero
placement are adopted to design the closed-loop parameters. In Ref. [46], the LCL
filter is initially approximated to an L filter, and the parameters of the grid current
regulator are adjusted using the symmetrical optimum (SO) method to achieve the
maximum phase margin, and finally, the capacitor-current-feedback coefficient is
computed using the root locus method. These parameters design methods aim to
find optimized closed-loop parameters with iteration or simulation. The technical
optimum (TO) method is widely used in designing controller parameters especially
for second-order systems, and its design target is to set the damping ratio of the
closed-loop system to 0.707. However, if the TO method is applied to high-order
systems such as LCL-type grid-connected inverters, the designed controller
parameters will lead to poor dynamic response and large steady-state error [32].
1.3.3.3 Grid Current Regulator
Usually, a PI regulator or proportional-resonant (PR) regulator is used as the grid

current regulator Gi(s), as shown in Figs. 1.3 and 1.4. The PI regulator has a simple
structure and allows easy implementation, while the PR regulator can provide a
sufficiently high gain at the fundamental frequency or selected harmonic frequen-
cies, so as to eliminate the steady-state error of the grid current or suppress the grid
current distortion caused by the specific grid voltage harmonics [11, 54].
The transfer function of the PI regulator is expressed as
Ki
Gi ðsÞ ¼ Kp þ ð1:1Þ
s
where Kp is the proportional coefficient and Ki is the integral coefficient. By

increasing Kp, a high crossover frequency can be obtained. By increasing Ki, a high
loop gain at the low frequencies can be achieved. The steady-state error of the grid
current can thus be reduced, and the harmonics and unbalance of the grid current
can be better suppressed. However, in order to ensure system stability, the selection
of Kp and Ki is subject to upper limits, implying that the harmonics and unbalance
of the grid current cannot be fully eliminated.
As for the single-phase grid-connected inverter, the PI regulator cannot achieve
zero steady-state error of the grid current [51], whereas the PR regulator can
overcome this problem [55]. The transfer function of the PR regulator is expressed
as
Kr s
s2 þ x2o
12 1 Introduction
where Kp is the proportional coefficient, Kr is the resonant coefficient, and xo = 2pfo

is the angular fundamental frequency. From (1.2), it can be observed that the gain of
the PR regulator is infinite at xo, so the steady-state error of the grid current can be
eliminated.
However, the grid frequency fluctuates when the load varies or when a grid fault
occurs. If the grid frequency deviates from the preset xo, the gain of the PR
regulator will decrease rapidly. As a result, the steady-state error of the grid current
will increase. To achieve a high gain within a grid frequency range around xo, two
solutions can be employed. One solution is to use an adaptive PR regulator whose
resonance frequency is adjusted to actual grid frequency [56, 57]. The actual grid
frequency can be measured using a PLL or other methods. The other solution is to
use a PR regulator which has a high gain within a grid frequency range around xo
[54]. Such a PR regulator is expressed as
2Kr xi s
s2 þ 2xi s þ x2o
where xi is the bandwidth of the resonant part when concerning −3 dB cutoff

pffiffiffi
frequency, which means the gain of the resonant part is Kr = 2 at xo ± xi.
Similarly, for the three-phase grid-connected inverter, adopting the PI regulator
in the stationary a–b frame cannot eliminate the steady-state error of the grid
current [50]. However, the PR regulator can accomplish it [56, 57]. Since the
positive-sequence and negative-sequence fundamental frequencies of the grid
voltage or grid current are the same in the stationary a–b frame, the PR regulator
can eliminate the steady-state error of both the positive-sequence and
negative-sequence fundamental wave components of the grid current.
The three-phase grid-connected inverter can be controlled in the synchronous d–
q frame, as shown in Fig. 1.4b. Note that the fundamental components of the
voltage and current are transformed to dc components in the synchronous d–
q frame. The PI regulator can thus eliminate the steady-state error of the grid
current. In fact, the PI regulator in the d–q synchronous frame is equivalent to the
PR regulator in the stationary a–b frame [58].
In fact, the procedure for finding the controller parameters is consistent for both
the single-phase grid-connected inverter and three-phasegrid-connected inverter
regardless of the representation in the stationary a–b frame or the synchronous d–
q frame. Except for the steady-state error, the phase margin and gain margin are
determined by both the grid current regulator and the capacitor-current-feedback
active-damping. Thus, the controller parameters should be carefully designed.
Taking the single-phase LCL-type grid-connected inverter shown in Fig. 1.3 as an
example, a step-by-step controller parameters design method will be discussed in
Chap. 5.
1.3.4 Effects of Control Delay and the Compensation

Methods
1.3.4.1 Control Delay Effects
Figure 1.5 shows the structure of a digitally controlled LCL-type grid-connected

inverter. In contrary to Fig. 1.3, the grid voltage vg, grid current i2, and capacitor
current iC are sampled and converted into digital signals by an A/D converter, and
the control algorithm is implemented with a digital signal processor (DSP).
The digitally controlled system contains computation and PWM delays. The
computation delay is one sampling period in the commonly used synchronous
sampling scheme, and it is modeled as z−1 in the z-domain and esTs in the s-
domain, where Ts is the sampling period. The PWM delay is caused by the
zero-order hold effect, which can be approximated as Ts e0:5sTs [59]. Therefore, it is
a delay of half sampling period. Hence, the total control delay is one and a half
sampling periods. Since this control delay is included in the
capacitor-current-feedback active-damping, it will certainly affect the damping
performance, thereby affecting the features of the loop gain, which will be discussed
in Chap. 8.
It is shown in Fig. 1.2c that in an analog-controlled LCL-type grid-connected
inverter, the phase plot of the loop gain crosses −180° at the resonance frequency fr.
Thus, the resonance peak must be damped below 0 dB to stabilize the system [51].
While in the digitally controlled system, the −180° crossover might take place at fr
or one-sixth of the sampling frequency (fs/6). Specifically, if fr < fs/6, the phase plot
still crosses −180° at fr, implying that the resonance damping is mandatory [60]. If
fr > fs/6, the phase lag resulted from the control delay makes the phase plot cross
−180° at fs/6 in advance. Thus, as long as the magnitude at fs/6 is below 0 dB, the
L1 vC L2
+ i1 iC i2
Vin vinv C vg
–
Sinusoidal PWM Hi1 Hi2 PLL

cos
vM – + – + i2*
Gi( z) I*
DSP Controller
Fig. 1.5 Structure of a digitally controlled LCL-type grid-connected inverter

14 1 Introduction
system can be stable even without any damping [31]. If fr = fs/6, the system can be
hardly stable even with damping.
In practice, the real grid contains inductive grid impedance, which makes the
resonance frequency lower. Moreover, the grid impedance might vary over a wide
range depending on the grid configuration, which leads to a wide range of variation
of the resonance frequency [14]. If the LCL filter with a resonance frequency higher
than fs/6 is installed, potential instability will be triggered when the grid impedance
makes the resonance frequency be reduced and pass through fs/6. Therefore, it is
necessary to alleviate the control delay effect to ensure the LCL-type grid-connected
inverter is robust against the grid-impedance variation.
1.3.4.2 Control Delay Compensation Methods
In order to compensate the control delay of one and a half sampling periods, an
ideal approach is to introduce a leading element with one and a half sample periods,
i.e., e1:5sTs , to completely cancel out e1:5sTs . For ease of implementation, e1:5sTs is
approximated by a first-order Taylor expansion, yielding e1:5sTs 1 þ 1:5sTs .
Noting that 1 þ 1:5sTs contains a derivative part, which will lead to an infinite
amplification of high-frequency noises, a lead compensator is usually adopted as an
alternative in practice, which is expressed as [61]
1 þ 1:5sTs
Glead ðsÞ ¼ ð1:4Þ
1 þ 1:5asTs
where a < 1. The phase lead introduced by Glead(s) can be regulated by tuning a.
Figure 1.6 shows the Bode diagrams of Glead(s) with two different values of a
and Ts = 50 ls. As shown in Fig. 1.6, a phase lead is achieved, but the gain at
higher frequencies is amplified at the same time. Hence, high-frequency noises will
be amplified to a certain extent. Moreover, a smaller a leads to a better compen-
sation of the phase, but a higher amplification of high-frequency noises arises. So,
the possible phase lead is limited in practice.
To achieve a more satisfactory compensation, the state observer can be used for
predicting the values one sampling period ahead [62]. Figure 1.7 shows the block
diagram of the state observer in discrete domain, where the system state-space
equations are expressed as
xðk þ 1Þ ¼ Gxðk Þ þ HuðkÞ

ð1:5Þ
yðkÞ ¼ CxðkÞ
where x(k) is the state-variable vector, u(k) is the input-variable vector, y(k) is the
output-variable vector, and G, H, and C are the state-space matrices. The observer
equations are
Fig. 1.6 Bode diagrams of 12

Glead(s) with different a =1/3
=2/3
8
|Glead (s)| (dB)

4
∠Glead (s) (°) 30
20
10
0
2 3 4 5
10 10 10 10
Frequency (Hz)
Fig. 1.7 Block diagram of

u(k) x(k+1)=Gx(k)+Hu(k) y(k)
the state observer in discrete
domain y(k)=Cx(k)
+
L
–
+ ˆ
x(k+1) ˆ
x(k) ˆ
y(k)
+
H z1 C
+
G
State observer
^xðk þ 1Þ ¼ G^xðk Þ þ Huðk Þ þ LðyðkÞ ^yðkÞÞ

ð1:6Þ
^yðkÞ ¼ C^xðkÞ
where L is the observer gain matrix, and the variables with hat (^) denote the observed
variables. From (1.6), it can be seen that based on the input and output at time step k,
i.e., u(k) and y(k), the state variable at time step k + 1, i.e., ^
xðk þ 1Þ, can be estimated.
This means that the estimated values are one sampling period ahead. Hence, if the
observed variable ^xðk þ 1Þ is used for feedback control instead of the actual vari-
able x(k), the one-sample computation delay will be completely compensated.
Since the state observer is built based on the system state-space model, its
precision of estimation is dependent on the accuracy of the model. In practice, the
16 1 Introduction
inaccuracy of the model caused by the variation of circuit parameters can lead to the
prediction error, which will degrade the control performance or even result in
system instability [63].
Instead of using a delay compensation, a direct reduction of the computation
delay is preferred. For the purpose of improving system stability and control per-
formance of LCL-type grid-connected inverter, methods of reducing or even
eliminating the computation delay will be given in Chap. 9.
1.3.5 Suppression of Grid Current Distortion Caused

by Grid Voltage Harmonics
As mentioned above, the actual grid voltage contains abundant background har-
monics, which will lead to the grid current distortion. Besides, the three-phase grid
voltages at PCC may be unbalanced during grid faults, and this will cause unbal-
ance of the three-phase grid currents. It is desirable to suppress the harmonics and
unbalanced components in the grid current since they may increase the power loss,
reduce the utilization rate and life span of the electric motors and transformers in the
power system, and reduce the reliability and accuracy of the relay protection and
measurement devices in the utility grid.
In order to guarantee safe, stable, and high-quality operation of power system
when integrating RE-DPGS, various standards for grid-connected inverters have
been established [17, 18, 64–66] to give the mandatory limitations of the grid
current harmonics and the amount of unbalanced components. This poses great
challenges to the control of the grid-connected inverters. According to Figs. 1.3 and
1.4, it can be known that the grid voltage imposes the impacts on the grid current by
two ways. One way is through the PCC, which directly generates the fundamental
positive-sequence component, unbalanced components, and the harmonic compo-
nents in the grid current. The other way is through the PLL, which introduces an
error in the grid current reference and thus generates the unbalanced components
and harmonic components in the grid current. In the following, the three-phase
grid-connected inverter is taken as the example to review the state of the art in the
suppression of grid current distortion.
1.3.5.1 Suppression of Grid Current Distortion and Unbalance

Caused by Grid Voltage
1. Control in Stationary Frame

In order to suppress the grid current harmonics caused by the grid voltagedistortion,
a multiresonant regulator can be used [14, 67], which is expressed as
Kr0 s Kr1 s Krn s

Gi ðsÞ ¼ Kp þ þ þ þ 2 ð1:7Þ
s2 þ x2o s2 þ x21 s þ x2n
where x1, x2, …, xn are the frequencies of the selected harmonics to be sup-
pressed, and Kr1, Kr2, …, Krn are the corresponding resonant gains.
Compared with (1.2), multiple resonant components are introduced in (1.7), of
which the resonance frequencies are set at the harmonic frequencies so that an
infinite loop gain at these frequencies can be obtained and the selected harmonics
can be eliminated. However, when the harmonic frequency is higher than the loop
gain crossover frequency, negative phase shift induced by the resonant components
will reduce the phase margin and even cause system instability. To solve the
problem, a phase-lead compensation has been introduced for improving the system
stability [56]. Therefore, the multiresonant regulator can be used to suppress the
current harmonics above the loop gain crossover frequency.
2. Control in Synchronous Frame
In the positive-sequence synchronous frame, the fundamental negative-sequence
components are transformed into ac components at twice the fundamental fre-
quency, which cannot be eliminated by a PI regulator. To improve the rejection
ability of the fundamental negative-sequence component, an integration regulator is
introduced in the negative-sequence synchronous frame, as shown in Fig. 1.8,
where dq+1 and dq−1 denote the positive- and negative-sequence synchronous
frames, respectively. With the control method, zero steady-state error can be
achieved for both the fundamental positive-sequence and negative-sequence com-
ponents of the grid current. In fact, the regulator shown in Fig. 1.8 is equivalent to a
PR regulator in the stationary frame [56].
To further improve the harmonic rejection ability of the grid-connected inverter,
integration compensators can be also introduced in the harmonic synchronous
frames [56], so that the loop gain at the selected harmonic frequencies can be
increased, leading to higher attenuation of the grid current harmonics. This method
is the so-called multisynchronous frame control.
Ki
αβ dq+1
s
dq+1 αβ
ωt
−1
[iαβ
* ] + [eαβ] αβ dq−1 [vM_αβ]
– dq−1 Ki
αβ
s
[iαβ]
Kp
Fig. 1.8 Control structure of the PI regulator in the positive- and negative-sequence synchronous
frames
18 1 Introduction
When the 6k + 1 positive-sequence and 6k − 1 negative-sequence components

are dominant in grid voltage harmonics (as is usually the case for the utility grid
installed with high-power diode-based or thyristor-based rectifiers), a PI-R regulator
in the positive-sequence synchronous frame has been proposed [57], which can be
expressed as
Ki X n
Krk s
Gi ðsÞ ¼ Kp þ þ 2
: ð1:8Þ
k¼1 s þ ð6kxo Þ
s 2
In the positive-sequence synchronous frame, both the 6k + 1 positive-sequence

and the 6k − 1 negative-sequence harmonics are transformed into the 6k harmonics.
Therefore, these two dominant harmonics can be suppressed by only one resonant
compensator placed at the 6kth harmonic frequency, which simplifies the controller
structure.
3. Repetitive Control
Using the multiresonant regulator in the stationary frame or the multisynchronous
frame control can eliminate the harmonics and the unbalance of the grid current.
However, the controller would be too complex when more harmonics are required
to be suppressed. Based on the internal model theory, a repetitive controller has
been proposed which can eliminate numbers of harmonics at the same time [68].
The control block diagram of the repetitive control is shown in Fig. 1.9, where r, e,
d, and y are the reference, error signal, disturbance, and the output of the system,
respectively. The repetitive controller, shown as the dashed block in Fig. 1.9,
contains a repetitive signal generator Q(z)z–N, a delay component z–N, and a com-
pensator C(z). Meanwhile, P(z) represents the transfer function of the controlled
object. Benefiting from the accumulative control, the repetitive controller acquires
high gains at the fundamental and harmonic frequencies, so that the grid current
harmonics and the unbalance can be effectively suppressed [40, 69–71]. The
repetitive control has the shortcoming of poor transient performance [40] and it can
be improved by combining the instantaneous feedback control [72].
4. Feedforward Control of Grid Voltage
All the aforementioned control methods increase the gains of the grid current loop
to suppress the grid current harmonics and unbalance caused by the grid voltage. In
fact, grid-voltage feedforward control method is an alternative way to cancel the
influence of the grid voltage, as shown in Fig. 1.10, where Gi is the current reg-
ulator, Hi2 is sensor gain of the grid current, GiM is the transfer function from the
Fig. 1.9 Control structure of d

the repetitive control r + e + y
z N C(z) P(z)
– –
Q(z)z N
Repetitive Controller
modulation wave vM to the grid current i2, and Yo is the output admittance of the
grid-connected inverter. The grid voltage vg is incorporated in the modulation wave
vM through feedforward function Gff, which can be derived from GiM and Yo to
completely eliminate the influence of vg on the grid current. Compared with the
aforementioned methods, the grid-voltage feedforward control method is very
simple, and it does not change the grid current loop gain, thus ensuring good
dynamic performance.
The grid-voltage feedforward control for the L-type grid-connected inverter has
been extensively studied and the feedforward function is 1/KPWM, where KPWM is
the transfer function from modulation wave vM to the inverter bridge output voltage
[73–75]. The grid-voltage feedforward control can effectively eliminate the
steady-state error, harmonics, and unbalance of the grid current caused by the grid
voltage even when a PI regulator is employed in the stationary frame, and it has
been widely used in the practical applications [50, 76].
As for the LCL-type grid-connected inverter, the positive feedback of capacitor
voltage can eliminate the influence of the grid voltage on the inverter-side inductor
current [77]. However, the grid current will still be distorted by the harmonics and
the unbalance of the grid voltage. In [16], a positive feedback of capacitor current is
introduced to reduce the influence of the grid voltage on the grid current. Since the
positive feedback function of the capacitor current is derived based on the
low-frequency approximation, the proposed method is only effective to reduce the
harmonic and unbalanced components of the grid current at low frequencies. In
Chaps. 6 and 7, the full feedforward control of the grid voltage for single-phase and
three-phase grid-connected inverters will be discussed to further improve the
quality of the grid current.
1.3.5.2 Suppression of the Grid Current Reference Error
The grid voltages do not only distort the grid current directly, but also cause
significant deviation of the current reference through the PLL, resulting in harmonic
and unbalanced components of the grid current. Therefore, extensive efforts have
been made to improve the performance of the PLL under distorted and unbalanced
grid voltages.
Fig. 1.10 Control diagram of vg

the grid-voltage feedforward
control
Gff Yo
i*2 + + +v M + – i2
Gi GiM
–
Hi2
20 1 Introduction
1. PLL in Synchronous Reference Frame

The synchronous reference frame PLL (SRF-PLL) is the widely used PLL for
three-phase inverters [78–81], as shown in Fig. 1.11a, where h′, x′, and vd are the
extracted phase angle, angular frequency, and amplitude of the grid voltage.
Three-phase grid voltages can be expressed as
8
< vga ¼ Vm sin h
vgb ¼ Vm sinðh 2p=3Þ ð1:9Þ
:
vgc ¼ Vm sinðh þ 2p=3Þ
where Vm and h are the amplitude and the phase of the grid voltage, respectively.
In Fig. 1.11a, the three-phase grid voltages are transformed into the synchronous
d–q frame. Applying Park transformation, the d-axis and q-axis components of the
grid voltages could be written as

vd ¼ Vm cosðh h0 Þ
: ð1:10Þ
vq ¼ Vm sinðh h0 Þ
vga v vq '
1
vgb abc PI s '
vgc v vd
dq
(a) SRF-PLL
+ vq ' 1 '
Vm PI s
(b) Linearized model of SRF-PLL
vga vg vq '
Extended 1
vgb abc PI s
Loop Filter '
vgc vg vd
dq
(c) Extended-loop-filter based SRF-PLL
vga vg v vq '
1
vgb abc PI s
vg Prefilter '
vgc v vd
dq
(d) Prefilter based SRF-PLL
Fig. 1.11 SRF-PLL and improved SRF-PLL

when h is very close to h′, (1.10) could be simplified as

vd Vm
: ð1:11Þ
vq Vm ðh h0 Þ
Therefore, vd is the amplitude information extracted by SRF-PLL, and vq reflects

the phase difference between h and h′. Also, vq is fed into the PI regulator for
closed-loop control. The output of the PI regulator is x′, which is the extracted
angular frequency of the grid voltage. Integrating x′ gives the phase angle h′, which
is used for calculation of the Park transformation. According to (1.11) and
Fig. 1.11a, the linearized model of SRF-PLL can be derived, as shown in
Fig. 1.11b. As shown, the output h′ tracks the reference h through the closed-loop
control, so the grid currents can be synchronized with the grid voltages. However,
h′ extracted by SRF-PLL will contain harmonic and unbalanced components under
the distorted and unbalanced grid conditions.
By lowering the crossover frequency, SRF-PLL can reduce the influence of the
grid voltage harmonics on h′, so that the error of the grid current reference could be
suppressed [79]. However, when the grid voltages contain low-frequency har-
monics and the negative-sequence components, it is difficult to maintain satisfac-
tory steady and dynamic performances at the same time. Therefore, many improved
PLLs have been proposed, which can be categorized into two types [82], one is
extended-loop-filter-based grid synchronization system, as shown in Fig. 1.11c; the
other is the prefilter-based grid synchronization system, as shown in Fig. 1.11d.
2. Extended-Loop-Filter-Based SRF-PLL
As shown in Fig. 1.11c, an extended-loop filter is introduced into the closed loop of
SRF-PLL to eliminate the harmonic components or the fundamental
negative-sequence components (twice the fundamental frequency) in vq, so that
SRF-PLL could extract h′ accurately. This is the so-called extended-loop-filter-
based SRF-PLL, where the extended-loop filter usually takes the form of the
low-pass filter (LPF) [83], adaptive notch filter (ANF) [84], second-order lead
compensator [85], sliding Goertzel transform (SGT) [86], and moving average filter
(MAF) [87]. The extended-loop-filter-based SRF-PLL can quickly and accurately
extract the phase angle and frequency of the fundamental positive-sequence component
of the grid voltages even under largely unbalanced and distorted grid conditions.
3. Prefilter-Based SRF-PLL
As the penetration of RE-DPGS becomes high, the related grid codes, regarding the
power quality, safe running, fault ride-through and so on, are becoming more
stringent [18, 64]. Therefore, not only the phase angle and frequency, but also the
amplitudes of fundamental positive- and negative-sequence components of the grid
voltages are required to be measured in order to ensure the RE-DPGS guarantees
the dynamic grid voltage support and power-oscillation elimination under grid fault
conditions [88–90]. However, the extended-loop-filter-based SRF-PLL has limited
ability of extracting the positive-sequence components. Under largely unbalanced
22 1 Introduction
and distorted grid conditions, even if h′ is identical with the phase of fundamental
positive-components of the grid voltages, vd will be still affected by the harmonic
and unbalanced components, for the reason that the amplitude information vd is not
processed by the extended-loop filter. Thus, it is necessary to filter vd again.
In order to extract the frequency, amplitudes, and phase of the grid voltages
quickly and accurately, the grid voltages should be filtered before they are delivered
to SRF-PLL, as shown in Fig. 1.11d. This kind of method is called prefilter-based
SRF-PLL. Recently, prefilter-based SRF-PLL has been studied extensively, and the
representative prefilters include positive-sequence filter (PSF) based on generalized
integrator [91], nonlinear adaptive filter for the enhanced phase-locked loop (E-
PLL) [92] and the quadrature phase-locked loop (Q-PLL) [93], adaptive filter based
on the second-order generalized integrator (SOGI) [81, 94, 95], decoupled double-
prefilter for SRF-PLL [96], complex coefficient prefilter [97], and delayed signal
cancellation (DSC)-based prefilter [98–103]. The analysis and comparison of the
aforementioned prefilters will be discussed in Chap. 12 in details.
1.3.6 Grid-Impedance Effects on System Stability

and the Improvement Methods
Under the stiff grid condition with small grid impedance, the grid-voltage-induced
harmonic distortion and the unbalance in the grid current can be effectively sup-
pressed by employing the multiresonant regulator, feedforward of the grid voltage,
repetitive control technique, or advanced PLL. As for the weak grid conditions,
however, the grid impedance is relatively large, which causes dynamic interactions
between the power grid and grid-connected inverter. Therefore, the stability
problems of the LCL-type grid-connected inverter may be aroused if the same
techniques are employed to suppress the harmonic distortion and unbalance in the
grid current [14, 104–107].
As pointed out in [14], using the multiresonant regulators in stationary frame, the
LCL-type grid-connected inverter can be operated stably under the stiff grid con-
dition. However, under weak grid condition, it may become unstable due to the
reduction of crossover frequency and the negative phase shift caused by the grid
impedance. In Ref. [104], it also shows that the single-phase LCL-type
grid-connected inverter may be unstable when the multiresonant regulator, feed-
forward of the grid voltage, and repetitive control technique are employed under the
weak grid conditions. Therefore, the grid impedance must be taken into account
when designing the controller parameters under the weak grid condition.
In Refs. [14, 104], when analyzing the system stability of the grid-connected
inverter under weak grid conditions, the grid-connected inverter and the grid are
taken as a whole, and then, the effects of the grid impedance on crossover fre-
quency, phase-frequency response and locations of poles and zeros of the grid
current loop gain are discussed for determining the system stability, the harmonic
rejection ability, and the transient performances.
Reference [105] extends the impedance-based stability criterion for the dc dis-
tributed power system into the ac grid-connection system. It has been pointed out
that in order to ensure the stability of the grid-connected inverter under weak grid
conditions, the following two conditions should be satisfied: (1) The
current-controlled grid-connected inverter is stable when operating under an ideal
grid with the assumption of Zg(s) = 0; and (2) the impedance ratio Zg(s)/
Zo(s) satisfies the Nyquist criterion. Here, Zg(s) and Zo(s) denote the grid impe-
danceand output impedance of the grid-connected inverter, respectively. The
impedance-based stability criterion avoids the need to remodel each inverter and
repeat its loop stability analysis when the grid impedance changes, or when more
inverters are connected to the same grid. Therefore, it is suitable for the stability
analysis of the complicated RE-DPGS operated under weak grid conditions.
Based on the above-mentioned impedance-based stability criterion, the system
stability of the single-phase and three-phase grid-connected inverters under weak
grid conditions will be discussed in Chaps. 10 and 11, respectively, and the control
strategies will be presented to improve the system stability while improve the
quality of the injected grid currents.
1.4 Summary
The worldwide energy situation is first reviewed in this chapter. The renewable
energy-based distributed power generation system (RE-DPGS) has been attracting a
great deal of attention due to its sustainable and environmental-friendly features,
and its use represents an effective approach to dealing with future energy shortage
and environmental pollution. As the energy conversion interface between the
renewable energy power generation units and the grid, the grid-connected inverter
plays an important role for the safe, stable, and high-quality operation of RE-DPGS.
The typical configurations and the advantages of the RE-DPGS are introduced in
this chapter. Moreover, the key control technologies of the LCL-type
grid-connected inverter are also systematically elaborated including: (1) design and
magnetic integration of LCL filter, (2) resonance damping methods, (3) design of
controller parameters, (4) control delay effects and the compensation methods,
(5) suppressing grid current distortion caused by grid voltage harmonics, and
(6) grid impedance effects on system stability and the improvement methods.
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Chapter 2
Design of LCL Filter
Abstract As the interface between renewable energy power generation system and
the power grid, the grid-connected inverter is used to convert the dc power to the
high-quality ac power and feed it into the power grid. In the grid-connected
inverter, a filter is needed as the interface between the inverter and the power grid.
Compared with the L filter, the LCL filter is considered to be a preferred choice for
its cost-effective attenuation of switching frequency harmonics in the injected grid
currents. To achieve high-quality grid current, the LCL filter should be properly
designed. In this chapter, the widely used pulse-width modulation (PWM) schemes
are introduced, including the bipolar sinusoidal pulse-width modulation (SPWM),
unipolar SPWM and harmonic injection SPWM. The spectrums of the output PWM
voltage with different SPWM are studied and compared. A design procedure for
LCL filter based on the restriction standards of injected grid current is presented and
verified by simulations.
Keywords Grid-connected inverter

LCL filter Pulse-width modulation

(PWM) Total harmonics distortion (THD)
As the interface between renewable energy power generation system and the power
grid, the grid-connected inverter is used to convert the dc power to the high-quality
ac power and feed it into the power grid. In the grid-connected inverter, a filter is
needed as the interface between the inverter and the power grid. Compared with the
L filter, the LCL filter is considered to be a preferred choice for its cost-effective
attenuation of switching frequency harmonics in the injected grid currents. To
achieve high-quality grid current, the LCL filter should be properly designed. In this
chapter, the widely used pulse-width modulation (PWM) schemes are introduced,
including the bipolar sinusoidal pulse-width modulation (SPWM), unipolar SPWM
and harmonic injection SPWM. The spectrums of the output PWM voltage with
different SPWM are studied and compared. A design procedure for LCL filter based
on the restriction standards of injected grid current is presented and verified by
simulations.

32 2 Design of LCL Filter
Fig. 2.1 Single-phaseLCL-

type grid-connected inverter Q1 Q3
Vin /2 L1 L2
A
O vinv C vg
B
Vin /2
Q2 Q4
2.1 PWM for Single-Phase Full-Bridge Grid-Connected

Inverter
Figure 2.1 shows the topology of a single-phase full-bridge LCL-type grid-

connected inverter, where switches Q1–Q4 compose the two bridge legs, and
inductors L1, L2 and capacitor C compose the LCL filter. Note that the two switches
in the same bridge leg are switched in a complementary manner.
Generally, the bipolar SPWM and unipolar SPWM are usually used for
single-phase full-bridge inverter. For convenience of illustration, the dc input
voltage Vin is split into two ones equally, and the midpoint O is defined as the base
potential.
2.1.1 Bipolar SPWM
Figure 2.2 shows the key waveforms of the bipolar SPWM for single-phase LCL-
type grid-connected inverter, where, vM is the sinusoidal modulation signal with the
amplitude of VM, and vtri is the triangular carrier with the amplitude of Vtri. When
vM > vtri, Q1 and Q4 turn on, Q2 and Q3 turn off, resulting in vAO = Vin/2 and
vBO = −Vin/2; When vM < vtri, Q1 and Q4 turn off, Q2, Q3 turn on, resulting in
vAO = −Vin/2 and vBO = Vin/2. The inverter bridg eoutput voltage vinv is the dif-
ference between vAO and vBO, i.e., vinv = vAO − vBO. As shown in Fig. 2.2, vinv has
only two voltage levels, namely −Vin and +Vin. So, this PWM scheme is often
called as bipolar SPWM.
In the following, xo and xsw denote the angular frequencies of the modulation
signal vM and triangular carrier vtri, respectively, the initial phase of the modulation
signal vM is set to 0, and Mr denotes the ratio of VM and Vtri, i.e.,
Mr ¼ VM =Vtri ð2:1Þ
According to the Fourier transform theory, the time-varying signals vAO and vBO
shown in Fig. 2.2 can be expressed as [1]
2.1 PWM for Single-Phase Full-Bridge Grid-Connected Inverter 33
vM vtri
Vtri
0
t
−Vtri
Q1 1
0
t
1
Q4
0
vAO t
Vin /2
0
t
−Vin /2
vBO
Vin /2
0
t
−Vin /2
vinv
Vin
0
t
−Vin
Fig. 2.2 Bipolar SPWM for single-phaseLCL-type grid-connected inverter
vAO ðtÞ ¼ vBO ðtÞ

Mr Vin 2Vin X
1 X
1
Jn ðmMr p=2Þ mp
¼ sin xo t þ sin cosðmxsw t þ nxo tÞ
2 p m¼1;3;... n¼0;2;4;... m 2
2Vin X
1 X1
Jn ðmMr p=2Þ mp
þ cos sinðmxsw t þ nxo tÞ
p m¼2;4;... n¼1;3;... m 2
ð2:2Þ
where, Jn(x) is the Bessel function of the first kind [2], expressed as
X1
ð1Þk x2k þ n
J n ð xÞ ¼ ð2:3Þ
k¼0
k!ðk þ nÞ! 2
According to (2.2), the Fourier series expansion of the inverter bridge output
voltage vinv with bipolar SPWM can be obtained, which is
vinv ðtÞ ¼ vAO ðtÞ vBO ðtÞ

4Vin X1 X
1
Jn ðmMr p=2Þ mp
¼ Mr Vin sin xo t þ sin cosðmxsw t þ nxo tÞ
p m¼1;3;5;... n¼0;2;4;... m 2
4Vin X1 X1
Jn ðmMr p=2Þ mp
þ cos sinðmxsw t þ nxo tÞ
p m¼2;4;6;... n¼1;3;... m 2
ð2:4Þ
where, the first term is the fundamental component, the second term is the sideband
harmonics around odd multiples of the carrier frequency, and the third term is the
sideband harmonics around even multiples of the carrier frequency. In the second
and third terms, m is the carrier index variable, and n is the baseband index variable.
m and n determine the harmonics distribution. When m is odd, |sin(mp/2)| = 1;
When m is even, |cos(mp/2)| = 1. With a given Vin, the amplitudes of the harmonics
in vinv are determined by |Jn(mMrp/2)/m|. Moreover, the harmonics in vinv distribute
only at the frequencies where m + n is odd.
According to (2.3), an example of |Jn(mMrp/2)/m| with Mr = 0.9 and m = 1, 2
and 3 is depicted with the dots, as shown in Fig. 2.3, where the three dashed lines
are plotted with Gamma Function C(k + n + 1), where the variable n uses a real
number. As observed, the dot with the maximum value locates at the center fre-
quency xsw, where m = 1, n = 0; the farther the sideband harmonic departs from
the center frequency, the smaller its amplitude is. In contrast to the harmonics
around the center frequency xsw, the amplitudes of the harmonics around twice and
above the carrier frequency are much smaller. Thus, the dominant harmonics in vinv
are at around xsw, which needs to be attenuated by the LCL filter.
In conclusion, the spectrum of the inverter bridge output voltage, vinv, generated
by the bipolar SPWM can be described as
1
m =1
m =2
0.8
m =3
J n ( mM rπ 2 )
0.6
m
0.4
0.2
0
9 7 5 3 1 1 3 5 7 9
n
Fig. 2.3 Characteristic curves of Bessel function

(1) The harmonics in vinv distribute only at frequencies where m + n is odd. When
m is odd, the harmonics distribute not only at m times of the carrier frequency,
but also at the sideband frequency when n is even; When m is even, the
harmonics only distribute at the sideband frequency when n is odd;
(2) The dominant harmonics in vinv are at around the carrier frequency (e.g., n = 0,
±2, ±4, …). The design of the LCL filter is determined by attenuating these
dominant harmonics.
2.1.2 Unipolar SPWM
As mentioned above, with the bipolar SPWM, the voltage levels of vinv could only
be −Vin and +Vin. In fact, when Q1 and Q3 or Q2 and Q4 turn on simultaneously, vinv
will be 0. The unipolar SPWM is such a kind of the modulation scheme that could
make vinv be not only +Vin and −Vin, but also 0.
Figure 2.4 shows the key waveforms of the unipolar SPWM for single-phase
LCL-type grid-connected inverter, where vM is the sinusoidal modulation signal,
and vtri and −vtri are the two sets of triangular carrier. Comparison of vM and vtri
leads to the control signals for Q1 and Q2, and comparison of vM and −vtri leads to
the control signals for Q3 and Q4. In detail, when vM > vtri, Q1 turns on and Q2 turns
off, thus vAO = Vin/2; When vM < vtri, Q1 turns off and Q2 turns on, thus
vAO = −Vin/2. Likewise, when vM > −vtri, Q4 turns on and Q3 turns off, thus
vBO = −Vin/2; When vM < − vtri, Q4 turns off and Q3 turns on, thus vBO = Vin/2.
Since vinv = vAO − vBO, the voltage levels of vinv could be +Vin, −Vin, and 0. In the
positive period of vM, the voltage levels of vinv could only be +Vin and 0; while in
the negative period of vM, the voltage levels of vinv could only be −Vin and 0.
Therefore, this modulation scheme is calledunipolar SPWM. Furthermore, the
ripple frequency of vinv is twice the carrier frequency.
Since the control signal for Q1 is obtained by comparing vM and vtri, the Fourier
series expansion of vAO is the same as (2.2). The control signal for Q4 is obtained by
comparing vM and −vtri, and −vtri lags vtri with a phase of p, the Fourier series
expansion of vBO can be obtained by replacing xswt in (2.2) with xswt − p. Thus,
vBO is expressed as
Mr Vin
vBO ðtÞ ¼ sin xo t
2
2Vin X 1 X
1
Jn ðmMr p=2Þ mp
sin cosðmðxsw t pÞ þ nxo tÞ
p m¼1;3;5;... n¼0;2;4;... m 2
2Vin X1 X1
Jn ðmMr p=2Þ mp
cos sinðmðxsw t pÞ þ nxo tÞ
p m¼2;4;6;... n¼1;3;... m 2
ð2:5Þ
Equation (2.5) can be further simplified as
Mr Vin 2Vin X1 X
1
Jn ðmMr p=2Þ mp
vBO ðtÞ ¼ sin xo t þ sin cosðmxsw t þ nxo tÞ
2 p m¼1;3;5;... n¼0;2;4;... m 2
2Vin X1 X1
Jn ðmMr p=2Þ mp
cos sinðmxsw t þ nxo tÞ
p m¼2;4;6;... n¼1;3;... m 2
ð2:6Þ
According to (2.2) and (2.6), the Fourier series expansion of vinv with the
unipolar SPWM is expressed as
vinv ðtÞ ¼ vAO ðtÞ vBO ðtÞ

4Vin X1 X1
Jn ðmMr p=2Þ mp
¼ Mr Vin sin xo t þ cos sinðmxsw t þ nxo tÞ
p m¼2;4;6;... n¼1;3;... m 2
ð2:7Þ
vM vtri −vtri
Vtri
0
t
−Vtri
Q1 1
0
t
1
Q4
0
vAO t
Vin /2
0
t
−Vin /2
vBO
Vin /2
0
t
−Vin /2
vinv
Vin
0
t
−Vin
Fig. 2.4 Unipolar SPWM for single-phase LCL-type grid-connected inverter

According to (2.7), the harmonic spectrum of vinv with the unipolar SPWM can
be described as
(1) The harmonics in vinv distribute only at the sideband frequencies where m is
even and n is odd.
(2) The dominant harmonics in vinv are at around twice the carrier frequency, which
is the major consideration of filter design.
Comparing (2.4) and (2.7), it shows that the frequencies of the harmonics in vinv
with the unipolar SPWM are twice that of those with the bipolar SPWM. This is
because the ripple frequencies of vinv with the bipolar and unipolar SPWMs are one
and two times of the carrier frequency, respectively, which can be found from
Figs. 2.2 and 2.4.
2.2 PWM for Three-Phase Grid-Connected Inverter
Figure 2.5a shows the topology of a three-phasegrid-connected inverter, where

switches Q1–Q6 compose the three-phase legs, and three sets of inductors L1, L2,
and capacitor C compose the three-phase LCL filter. Note that the three-phase
capacitors in LCL filter can be either delta- or star-connection. The capacitance
needed in delta-connection is one-third of that in star-connection, and the capacitor
Q1 Q3 Q5
Vin/2 L1 vCa L2
a
L1 vCb L2
O b
L1 vCc L2
c
Vin/2
Q4 Q6 Q2 C C C vgc vgb vga
N N'
(a) Main circuit
ia1 L1 vCa L2 ia2

ib1 L1 vCb L2 ib2
ic1 L1 vCc L2 ic2
iCa iCb iCc
vao vbo vco C C C vgc vgb vga
O N N'
(b) Equivalent circuit
Fig. 2.5 Three-phase LCL-type grid-connected inverter

pffiffiffi pffiffiffi
current and voltage stresses in delta-connection are 1= 3 and 3 times of that in
star-connection, respectively. In this book, star-connection is adopted. Similarly, Vin
is split into two ones equally for convenience of illustration, and the midpoint O is
defined as the base potential.
Figure 2.5b shows the equivalent circuit of the three-phase grid-connected
inverter, where vao, vbo, and vco are the three inverter bridge output voltages with
respect to midpoint O; i1x (x = a, b, c) is the inverter-side inductor current; vCx and
iCx are the filter capacitor voltage and current, respectively; i2x is the grid-side
inductor current. From Fig. 2.5b, vao, vbo and vco can be expressed as
8
< vao ¼ jxL1 i1a þ vCa þ vNO
>
vbo ¼ jxL1 i1b þ vCb þ vNO ð2:8Þ
>
:
vco ¼ jxL1 i1c þ vCc þ vNO
where vNO is the voltage across points N and O.

The three-phase filter capacitor voltages can be expressed as
8
< vCa ¼ iCa =ðjxC Þ
>
vCb ¼ iCb =ðjxC Þ ð2:9Þ
>
:
vCc ¼ iCc =ðjxCÞ
For three-phase three-wire system, i1a + i1b + i1c = 0, iCa + iCb + iCc = 0.
According to (2.8), the zero sequence component vNO is derived as
vNO ¼ ðvao þ vbo þ vco Þ=3 ð2:10Þ
Similarly, vNN 0 , the voltage across points N and N′, can be obtained, expressed as

vNN 0 ¼ vga þ vgb þ vgc =3 ð2:11Þ
With PWM control, vao + vbo + vco 6¼ 0. So, according to (2.10), vNO is not
equal to zero, which means that the potentials of N and O are not equal. When the
three-phase grid voltages are balance, i.e., vga + vgb + vgc = 0, the potentials of
N and N′ are equal according to (2.11).
2.2.1 SPWM
Figure 2.6 shows the key waveforms of SPWM for three-phase grid-connected
inverter, where vtri is the triangular carrier, and vMa, vMb, and vMc are the three-
phase sinusoidal modulation signals, expressed as
2.2 PWM for Three-Phase Grid-Connected Inverter 39
vMa vMb vMc vtri

Vtri
0
t
−Vtri
vao
Vin /2
0
t
−Vin /2
vbo
Vin /2
0
t
−Vin /2
vco
Vin /2
0
t
−Vin /2
vNO
Vin /2
0
t
−Vin /2
vaN
2Vin /3
Vin /3
0
−Vin /3 t
−2Vin /3 vab
Vin
0
t
−Vin
Fig. 2.6 SPWM for three-phase LCL-type grid-connected inverter
8
< vMa ¼ VM sin xo t
>
vMb ¼ VM sinðxo t 2p=3Þ ð2:12Þ
>
:
vMc ¼ VM sinðxo t þ 2p=3Þ
where VM is the amplitude of the modulation signals, xo is the angular frequency of

the modulation signals, which is equal to the grid angular frequency.
Obviously, the control signals for Q1 and Q4 are determined by comparing vMa
and vtri, the control signals for Q3 and Q6 are determined by comparing vMb and vtri,
and the control signals for Q5 and Q2 are determined by comparing vMc and vtri.
Thus, the voltages of the midpoints of three-phase legs with respect to O, vao, vbo,
and vco, are obtained. vNO can be determined according to (2.10). The output phase
voltage vaN is equal to vao − vNo, and the output line voltage vab is equal to
vao − vbo.
According to the modulation scheme, the expression of vao is the same as (2.2).
Since vMb lags vMa with a phase of 2p/3 and vMc leads vMa with a phase of 2p/3, by
replacing xot in (2.2) with xot − 2p/3 and xot + 2p/3, respectively, the expres-
sions of vbo and vco can be obtained as

Mr Vin 2p
vbo ðtÞ ¼ sin xo t
2 3
2Vin X 1 X Jn ðmMr p=2Þ mp
1
2p

þ sin cos mxsw t þ n xo t
p m¼1;3;... n¼0;2;... m 2 3

2Vin X 1 X
1
Jn ðmMr p=2Þ mp 2p
þ cos sin mxsw t þ n xo t
p m¼2;4;... n¼1;3;... m 2 3
ð2:13Þ

Mr Vin 2p
vco ðtÞ ¼ sin xo t þ
2 3
X
1 X
1
2Vin Jn ðmMr p=2Þ mp 2p
þ sin cos mxsw t þ n xo t þ
p m¼1;3;... n¼0;2;... m 2 3

2Vin X 1 X
1
Jn ðmMr p=2Þ mp 2p
þ cos sin mxsw t þ n xo t þ
p m¼2;4;... n¼1;3;... m 2 3
ð2:14Þ
Substituting (2.2), (2.13), and (2.14) into (2.10) yields

2Vin X1 X
1
Jn ðmMr p=2Þ 2np mp
vNO ðtÞ ¼ 1 þ 2 cos sin cosðmxsw t þ nxo tÞ
3p m¼1;3;... n¼0;2;... m 3 2

2Vin X 1 X
1
Jn ðmMr p=2Þ 2np mp
þ 1 þ 2 cos cos sinðmxsw t þ nxo tÞ
3p m¼2;4;... n¼1;3;... m 3 2
ð2:15Þ
According to (2.2) and (2.15), the output phase voltage vaN is obtained, which is
vaN ðtÞ ¼ vao ðtÞ vNO ðtÞ

Mr Vin 2Vin X1 X
1
4 Jn ðmMr p=2Þ mp 2 np
¼ sin xo t þ sin sin cosðmxsw t þ nxo tÞ
2 p m¼1;3;5;... n¼0;2;4;... 3 m 2 3
2Vin X1 X1
4 Jn ðmMr p=2Þ mp 2 np
þ cos sin sinðmxsw t þ nxo tÞ
p m¼2;4;6;... n¼1;3;... 3 m 2 3
ð2:16Þ
As seen in (2.16), for the harmonics in vaN at around odd times (m = 1, 3, 5, …)

of carrier frequency, when n = 6k (k is an integer), sin2(np/3) = 0; when
n = 6k ± 2, sin2(np/3) = 3/4. Similarly, for the harmonics in vaN at around even
times (m = 2, 4, 6, …) of carrier frequency, when n = 3(2k − 1), sin2(np/3) = 0;
when n = 6k ± 1, sin2(np/3) = 3/4.
So, the harmonics spectrum of the output phase voltages of three-phase inverter
controlled by SPWM can be described as
(1) The harmonics in the output phase voltages vxN (x = a, b, c) only distribute at
frequencies where m + n is odd. When m is odd, the harmonics only distribute
at the sideband frequencies where n = 6k ± 2 (k is an integer); when m is even,
the harmonics only distribute at the sideband frequencies where n = 6k ± 1.
(2) The harmonics in the output phase voltages vxN at around the carrier frequency
(n = ±2, ±4, …) are the dominant harmonics, which is the major consideration
of filter design.
According to (2.2) and (2.13), the output line voltage vab can be obtained,
expressed as
vab ðtÞ ¼ vao ðtÞ vbo ðtÞ

pffiffiffi
3Mr Vin p
¼ sin xo t þ
2 6
2Vin X1 X
1
Jn ðmMr p=2Þ mp np p np
þ sin 2 sin cos mxsw t þ nxo t þ
p m¼1;3;5;... n¼0;2;4;... m 2 3 2 3
2Vin X1 X1
Jn ðmMr p=2Þ mp np p np
þ cos 2 sin sin mxsw t þ nxo t þ
p m¼2;4;6;... n¼1;3;... m 2 3 2 3
ð2:17Þ
By comparing (2.16) and (2.17), it can be observed that: (1) at the fundamental
pffiffiffi
frequency, the amplitude of line voltage is 3 times of that of the phase voltage,
and the line voltage leads to the phase voltage with a phase of p/6; (2) The har-
monics of the output phase and line voltages vaN and vab distribute at the same
pffiffiffi
sideband frequencies, and the amplitudes of harmonics in line voltages are also 3
times of that of the harmonics in phase voltages, and it leads to the harmonics in the
corresponding phase voltages with a phase of p/2 − np/3.
2.2.2 Harmonic Injection SPWM Control
According to (2.17), when 0 Mr 1, the maximum amplitude of output line

pffiffiffi
voltage vab is only 3Vin =2, i.e., 0.866Vin. It means that the dc voltage utilization of
the three-phase inverter controlled by SPWM is only 0.866. However, according to
(2.3) and (2.7), the dc voltage utilization of a single-phase full-bridge inverter is 1.
To make the dc voltage utilization of three-phase inverter attain 1, a third har-

monic component vz as shown in Fig. 2.7 is injected to the three-phase sinusoidal
modulation signals. It can be observed that the peak of vMa and the valley of vz
appear at the same time. As a result, the peak of the modulation signal vMaz, which
is the sum of vMa and vz, distributes not at but on both sides of the peak of vMa.
When the amplitude of vMaz is equal to that of vtri, the real amplitude of vMa will be
larger than that of vtri. Define the modulation ratio of three-phase inverter is still the
ratio of the amplitudes of vMa and vtri, then according to (2.1), the modulation ratio
larger than 1 will be obtained.
Further study shows that when the amplitude of the injected third harmonic
component vz is one-sixth of that of modulation sinusoidal signal vMa [1], i.e.,
vMa vMaz vMb vMcz vtri

Vtri z
vz
0
t
−Vtri
vao
Vin /2
0
t
−Vin /2
vbo
Vin /2
0
t
−Vin /2
vco
Vin /2
0
t
−Vin /2
vNO
Vin /2
0
t
−Vin /2
vaN
2Vin /3
Vin /3
0
−Vin /3 t
−2Vin /3 vab
Vin
0
t
−Vin
Fig. 2.7 Third harmonic injection SPWM for three-phase LCL-type grid-connected inverter
VM
vz ¼ sin 3xo t ð2:18Þ
6
the dc voltage utilization of the three-phase inverter attains 1. A brief proof is

presented as follows.
According to (2.12) and (2.18), the modulation signal vMaz is as follows:
VM 3VM 2VM 3
vMaz ¼ VM sin xo t þ sin 3xo t ¼ sin xo t sin xo t ð2:19Þ
6 2 3
According to (2.19), it can be derived that the peak of vMaz locates at xot = p/3
or 2p/3. If the amplitude of vMaz is set to equal to that of vtri, VM/Vtri can reach 1.15,
which indicates that the modulation ratio of the third harmonic injection SPWM can
reach 1.15. When Mr = 1.15, according to (2.17), the amplitude of line voltage can
attain Vin, which is the same as that of the single-phase full-bridge inverter. In other
words, the dc voltage utilization attains 1.
From the Fourier transform theory, the expansions of vao and vbo in Fig. 2.7 can
be obtained, which are
Mr Vin Mr Vin X
1 X
1
vao ðtÞ ¼ sin xo t þ sin 3xo t þ Amn cosðmxsw t þ nxo tÞ
2 12 m¼1;2;3;... n¼0;1;2;...
ð2:20Þ

Mr Vin 2p Mr Vin
vbo ðtÞ ¼ sin xo t þ sin 3xo t
2 3 12
X 1 X
1 ð2:21Þ
2p
þ Amn cos mxsw t þ n xo t
m¼1;2;3;... n¼0;1;2;...
3
where Amn is the amplitude of harmonics, expressed as [1]

2 3
J0 ðmMr p=12ÞJk ðmMr p=2Þ sin½ðm þ k Þp=2jk¼jnj
6 7
6 þ J0 ðmMr p=2ÞJh ðmMr p=12Þ sin½ðm þ hÞp=2j3h¼jnj 7
6 7
2Vin 6 P 7
Amn ¼ 6 þ Jk ðmMr p=2ÞJh ðmMr p=12Þ sin½ðm þ k þ hÞp=2jk þ 3h¼jnj 7
6
mp 6 P 7
7
6 þ Jk ðmMr p=2ÞJh ðmMr p=12Þ sin½ðm þ k þ hÞp=2jk3h¼jnj 7
4 5
P
þ Jk ðmMr p=2ÞJh ðmMr p=12Þ sin½ðm þ k þ hÞp=2j3hk¼jnj
ð2:22Þ
Same as the derivation of output phase voltage vaN with SPWM in Sect. 2.2.1,
the expression of vaN with the third harmonic injection SPWM can be derived,
expressed as
Mr Vin X
1 X
1
4 2 np
vaN ðtÞ ¼ sin xo t þ sin Amn cosðmxsw t þ nxo tÞ
2 m¼1;2;3;... n¼0;1;2;...
3 3
ð2:23Þ
By comparing (2.16) and (2.23), the harmonics spectrum of the output phase
voltages of three-phase inverter with the third harmonic injection SPWM can be
concluded as follows:
(1) The harmonics in the output phase voltages vxN (x = a, b, c) only distribute at
the frequencies where m + n is odd. When m is odd, the harmonics only
distribute at even sideband frequencies where n = 6k ± 2 (k is an integer);
when m is even, the harmonics only distribute at odd sideband frequencies
where n = 6k ± 1.
(2) The harmonics in vxN at around the carrier frequency (n = ±2, ±4, …) are the
dominant harmonics, which is the major consideration of filter design.
According to (2.20) and (2.21), the output line voltage vab can be obtained as
vab ðtÞ ¼ vao ðtÞ vbo ðtÞ

pffiffiffi
3Mr Vin p
¼ sin xo t þ
2 6
X1 X1
np p np
þ 2 sin Amn cos mxsw t þ nxo t þ
m¼1;2;3;... n¼0;1;2;...
3 2 3
ð2:24Þ
Besides (2.18), the harmonic vz injected to the modulation sinusoidal signal can
be generated from the envelope magnitude of vMa, vMb, and vMc [1], which means
that the maximum magnitude of |vMa|, |vMb| and |vMc| is selected, as shown in
Fig. 2.8. In detail, within xot 2 [0, p/6) [ [5p/6, 7p/6) [ [11p/6, 2p), |vMa| is the
largest one, so vz is extracted from vMa; Likewise, within xot 2 [p/6, p/2) [ [7p/6,
3p/2), |vMb| is the largest one, then vz is extracted from vMc; Within xot 2 [p/2, 5p/
6) [ [3p/2, 11p/6), |vMc| is the largest one, and vz is extracted from vMb. Due to
vMa + vMb + vMc = 0, vz can be expressed as follows
vz ¼ kðmaxfvMa ; vMb ; vMc g þ minfvMa ; vMb ; vMc gÞ ð2:25Þ
It also can be proved that the peak of the modulation signal vMaz locates at
xot = p/3 or 2p/3. When k in (2.25) equals to 0.5, the dc voltage utilization can also
vMa vMaz vMbz vMcz vtri

Vtri z
vz
0
t
−Vtri
vao
Vin /2
0
t
−Vin /2
vbo
Vin /2
0
t
−Vin/2
vco
Vin /2
0
t
−Vin /2
vNO
Vin /2
0
t
−Vin /2
vaN
2Vin /3
Vin /3
0
−Vin /3 t
−2Vin /3 vab
Vin
0
t
−Vin
Fig. 2.8 Harmonic injection SPWM for three-phase LCL-type grid-connected inverter that is
equivalent to SVM
attain 1. The result of harmonic injection SPWM shown in Fig. 2.8 is equivalent to
the space vector modulation (SVM) [1]. Since the zero sequence component
extracts directly from the modulation sinusoidal signals, the realization of the
three-phase modulation signals shown in (2.25) is simple and widely used.
The amplitude Amn of output harmonics voltage controlled by the harmonic
injection SPWM shown in Fig. 2.8 is expressed as [2]
2 pffiffiffi
3
p ðm þ nÞp 3mMr p np 3mMr p
6 6 sin Jn þ 2 cos Jn 7
6 2 4 6 4 7
6 pffiffiffi
7
6 1 mp np np 3mMr p 3mMr p 7
6 þ sin cos sin J J 7
6 n 0 0 7
6 2 2 6 4 4 n6¼0 7
6 8 97
6 > 1 ð m þ k Þp ð n þ k Þp ð n þ k Þp > 7
6 >
> sin cos sin : >
> 7
6 >
< nþk >
= 7
6 X 1 2 2 6 7
4Vin 6 þ p ffiffi
ffi
7
Amn ¼ 6 > 3mMr p ð2n þ 3k Þp 3mMr p > 7
mp2 6 k¼1 >> þ >
> 7
6 >
k6¼n :
J k 2 cos J k
;7
>
6 4 6 4 7
6 8 9 7
6 7
6 >
> 1 ðm þ kÞp ðn kÞp ðn kÞp >
> 7
6 >
> sin cos sin : > 7
>
6 P1 < n k 2 2 6 = 7
6 7
6 þ pffiffiffi
7
6 k¼1 >> 3mM p ð 2n 3k Þp 3 mM p >
> 7
4 >
> Jk
r
þ 2 cos Jk
r
>
> 5
k6¼n : 4 6 4 ;
ð2:26Þ
2.3 LCL Filter Design
The PWM output voltage of the grid-connected inverters contains abundant of

switching harmonic components, which results in the harmonic current injecting
into the grid. Therefore, a filter is required to interface between the inverter bridge
and the power grid. The LCL filter is usually employed since it has better ability of
suppressing high frequency harmonics than the L filter. This section will focus on
the design of the LCL filter.
The single-phase full-bridge inverter, as shown in Fig. 2.1, could be simplified to
the equivalent circuit as shown in Fig. 2.9a. Likewise, when the three-phase grid
voltages are balanced, the voltage potentials of node N and N′ are identical. As a
result, the three-phase circuit, as shown in Fig. 2.5b, can be decoupled and each
phase could be simplified to the equivalent circuit as shown in Fig. 2.9b, where
x = a, b, c. As seen, the structures of the equivalent circuits of the single-phase and
three-phase LCL filters are the same, so the design procedures of them are almost
uniform, except that the harmonic spectrum of the imposed PWM voltages are
different. In the following, the grid voltage vg is assumed a pure sinusoidal waveform.
L1 L2 L1 L2
i1 iC i2 i1x iCx i2x
+ + + + + +
vinv C vC vg v xN C vCx v gx
– – – – – –
(a) Single-phase (b) Three-phase
Fig. 2.9 Equivalent circuits of single-phase and three-phase LCL-type grid-connected inverters
2.3 LCL Filter Design 47
2.3.1 Design of the Inverter-Side Inductor
From Figs. 2.1 and 2.5a, it can be observed that the current flowing through the
filter inductor L1 and the switches are the same. The larger the inductor current
ripple is, the larger the inductor losses and higher current stress of the switches are.
As a result, the conduction and switching losses will increase. Thus, the inductor
current ripple should be limited.
2.3.1.1 Single-Phase Full Bridge Grid-Connected Inverter
1. Bipolar SPWM
Figure 2.10a gives the key waveforms of the single-phase full-bridge inverter
with bipolar SPWM, where i1_f is the fundamental component in the inverter-side
inductor current, and Tsw is the carrier period.
When vM > vtri, switches Q1 and Q4 turn on simultaneously, and the bridge
output voltage vinv = Vin. The voltage applied on inductor L1 is
di1
L1 ¼ Vin vC ð2:27Þ
dt
where vc is the filter capacitor voltage. Within one carrier period, vC can be regarded
to be constant, and Vin > vC. So, the inductor current i1 increases linearly, and the
increment is
Tsw Tsw/2
vM vM
Vtri Vtri vtri
S vtri S
0 0
t t
−Vtri −Vtri −vtri
T+ vinv T+ vinv
Vin Vin
0 0
t t
−Vin −Vin i1_ f

i1_ f
i1 i1
0 0
t t
t '1 t1 t'2 t2 t 3 t'1 t1 t'2 t2 t3
(a) Bipolar SPWM (b) Unipolar SPWM
Fig. 2.10 Key waveforms of single-phase full bridge inverter

Vin vC
Di1ð þ Þ ¼ Tð þ Þ ð2:28Þ
L1
where T(+) = t12 is the time interval when Q1 and Q4 conduct simultaneously.
When vM < vtri, Q2 and Q3 turn on simultaneously, and vinv = −Vin. The voltage
across inductor L1 is
di1
L1 ¼ Vin vC ð2:29Þ
dt
Similarly, il decreases linearly, and the decrement is
Vin þ vC
Di1ðÞ ¼ TðÞ ð2:30Þ
L1
where T(−) = t23 is the time interval when Q2 and Q3 conduct simultaneously.
The equation for solving the intersection points of vM and vtri is transcendental,
so regular sampling SPWM is usually used to calculate T+. In detail, a horizontal
line is drawn across point S, as shown in Fig. 2.10, and it would intersect the
triangle carrier at t10 and t20 . Considering the fundamental frequency is much lower
0
than the carrier frequency, it is reasonable to have T(+) = t12 t12 . Then, T(+) can
be calculated, which is
vM þ Vtri 1
Tð þ Þ ¼ Tsw ¼ Tsw ðMr sin xo t þ 1Þ ð2:31Þ
2Vtri 2
Likewise, T(−) can be expressed as
1
TðÞ ¼ Tsw Tð þ Þ ¼ Tsw ð1 Mr sin xo tÞ ð2:32Þ
2
Generally, the fundamental component in the voltage across inductors L1 and L2

are small, so the filter capacitor voltage vC can be approximated to the grid voltage
vg and it equals to the fundamental component of the bridge output voltage vinv, i.e.,
vC vg ¼ Mr Vin sin xo t ð2:33Þ
Substituting (2.32) and (2.33) into (2.28) and (2.30), respectively, Di1(+) and Di1
(−) can be derived as
Vin Tsw
Di1ð þ Þ ¼ Di1ðÞ ¼ 1 Mr2 sin2 xo t ð2:34Þ
2L1
As seen in (2.34), either the maximum increment or decrement of the current of

inductor L1 (denoted as Di1_max) within a carrier period appears at sinxot = 0, i.e.,
Di1_max = VinTsw/(2L1). Defining the ripple coefficient as kc_L1 = Di1_max/I1, where
I1 is the rated RMS value of the fundamental component of i1, the minimum
inductance of L1 can be obtained as
Vin Tsw
L1 min ¼ ð2:35Þ
2kc L1 I1
In practice, kc_L1 is set to be 20–30% [2].

The maximum value of L1 could be determined from the fundamental voltage of
L1, which is defined as vL1_f. The smaller vL1_f is, the lower the dc-link voltage is
required. Defining the ratio of RMS values of vL1_f and vC as kv_L1, the maximum
value of L1 can be obtained, which is
kv L1 VC kv L1 Vg
L1 max ¼ ð2:36Þ
x o I1 x o I1
where Vg is the RMS value of the grid voltage, and kv_L1 is usually set to be about
5%.
2. Unipolar SPWM
Figure 2.10b gives the key waveforms of the single-phase full-bridge inverter
with unipolar SPWM. When vM > vtri and vM > − vtri, switches Q1 and Q4 turn on
simultaneously, and vinv = Vin. As a result, i1 increases linearly. From Fig. 2.10b,
the ratio of T(+) and Tsw/2 can be obtained, which is
Tð þ Þ vM
¼ ¼ Mr sin xo t ð2:37Þ
Tsw =2 Vtri
Substituting (2.33) and (2.37) into (2.28), the increment Di1(+) can be derived as
Vin Tsw
Di1ð þ Þ ¼ ð1 Mr sin xo tÞMr sin xo t ð2:38Þ
2L1
Similarly, the decrement Di1(−) when both Q2 and Q3 turn on can be calculated,
which is the same as (2.38).
As seen in (2.38), the maximum increment and decrement of i1 appear when
sinxot = 1/(2Mr), and Di1_max = VinTsw/(8L1). Then, the minimum of L1 with
unipolar SPWM is
Vin Tsw
L1 ¼ ð2:39Þ
8kc L1 I1
By Comparing of (2.35) and (2.39), it can be seen that the required L1 with
unipolar SPWM is only one-fourth of that with bipolar SPWM when that the
permitted maximum increment (or decrement) of inductor current are identical. The
reasons are: (1) the equivalent carrier frequency with unipolar SPWM is twice that
with bipolar SPWM; (2) the bridge output voltage vinv switches between Vin and
−Vin when bipolar SPWM is used, while it is switched between Vin and 0, or 0 and
−Vin when unipolar SPWM is used.
2.3.1.2 Three-Phase Grid-Connected Inverter
Similar to the single-phase grid-connected inverter, the inverter-side inductor L1 of

the three-phase grid-connected inverter is also determined by the maximum current
ripple. The fundamental voltage of L1 is also ignored here, and the filter capacitor
voltage vCx is approximated to the fundamental voltage of the inverter bridge output
voltage vxN, i.e., vCa (MrVin/2)sinxot. However, differed from the single-phase
full-bridge inverter, the three-phase inverter bridge output voltage vxN can output five
levels, i.e., 0, ±Vin/3, and ±2Vin/3. As a result, the current ripple of i1x (x = a, b, c) is
more complex. In the following, a detailed analysis about the current ripple of i1x will
be presented. Since the voltages and currents are periodic, only the key waveforms in
a quarter of one cycle, i.e., xot 2 [0, p/2] is given, as shown in Fig. 2.11.
Vtri vtri vMc Vtri vtri vMa

vMa vMc
0 t 0
t
−Vtri vMb vMb
−Vtri
vaN vaN
Vin /3 2Vin /3
0 Vin /3
t 0
−Vin /3 t
i1a i1a
0 0
t t
t0 t1 t2 t3 t 4 t5 t6 t0 t1 t2 t3 t4 t5 t6
(a) ω o t ∈ [0, /6] (b) ω o t ∈ ( /6, φ]
Vtri vtri vMa

vMc
0 t
vMb
−Vtri
vaN
2Vin /3
Vin /3
0 t
i1a
0 t
t 0 t 1 t2 t 3 t4 t 5 t6
(c) ω o t ∈ (φ, /2]
Fig. 2.11 Inverter-side inductor current of three-phase inverter

From Figs. 2.6, 2.7 and 2.8, it can be observed that no matter SPWM or har-
monic injection SPWM is used, the three-phase filter capacitor voltages satisfy the
relation vMc > vMa > vMb within xot 2 [0, p/6]. Moreover, vMa increases mono-
tonously and reaches its maximum value at xot = p/6. Since vCx is proportional to
vMx in the linear modulation region, vCc > vCa > vCb is also true, and vCa increases
monotonously and reaches its maximum value at xot = p/6. Thus, the maximum
value of vCa equals to (MrVin/2)sin(p/6) = MrVin/4. When SPWM or harmonic
injection SPWM is used, the maximum values of vCa are Vin/4 and 1.15Vin/4,
respectively. Obviously, vCa < Vin/3 is always true within xot 2 [0, p/6]. When
xot 2 [0, p/6], i1a can be divided into six sections in one carrier period, i.e., [t0, t6],
as shown in Fig. 2.11a, and three cases can be found in the six sections.
Case 1: when t 2 [t0, t1) [ [t2, t3), vaN = Vin/3. Since vCa < Vin/3, i1a increases
linearly;
Case 2: when t 2 [t1, t2) [ [t4, t5), vaN = 0. Since vCa > 0, i1a decreases linearly;
Case 3: when t 2 [t3, t4) [ [t5, t6), vaN = −Vin/3. Since vCa < Vin/3, i1a decreases
linearly.
When xot 2 [p/6, p/2], vCa > vCc > vCb is true, and vCa increases monotonously
and reaches its maximum value at xot = p/2. The maximum value of vCa is MrVin/2.
When SPWM or harmonic injection SPWM is used, the maximum values of vCa are
Vin/2 and 1.15Vin/2, respectively. Obviously, vCa < 2Vin/3 is always true within
xot 2 (p/6, p/2]. Similarly, when xot 2 (p/6, p/2], i1a can also be divided into six
sections in one carrier period, i.e., [t0, t6], as shown in Fig. 2.11b, c, and three cases
can also be found in the six sections.
Case 1: when t 2 [t0, t1) [ [t4, t5), vaN = 2Vin/3. Since vCa < 2Vin/3, i1a increases
linearly;
Case 2: when t 2 [t1, t2) [ [t3, t4), vaN = Vin/3. If vCa < Vin/3, i1a increases lin-
early, as shown in Fig. 2.11b. If vCa > Vin/3, i1a decreases linearly, as shown in
Fig. 2.11c;
Case 3: when t 2 [t2, t3) [ [t5, t6), vaN = 0. Since vCa > 0, i1a decreases linearly.
Defining xot when vCa = Vin/3 as /, yields
Mr Vin Vin
sin / ¼ ð2:40Þ
2 3
Then, / can be calculated as

2
/ ¼ arcsin ð2:41Þ
3Mr
According to (2.41), it can be obtained that only when Mr 2/3, vCa will be
possible to be larger than Vin/3, thus the case shown in Fig. 2.11c appears; and
when Mr < 2/3, vCa will be never larger than Vin/3, thus the case shown in
Fig. 2.11c does not appear.
As seen from Fig. 2.11a, i1a continues decreasing within [t3, t6]. As seen from
Fig. 2.11b, i1a continues increasing within [t0, t2] or [t3, t5], and decreases within
[t2, t3] or [t5, t6]. As seen from Fig. 2.11c, i1a increases within [t0, t1] or [t4, t5] and
continues decreasing within [t1, t4] or [t5, t6]. As mentioned above, the maximum
increment and decrement of the inverter-side inductor current is identical. In the
following, only the decrements of i1a within [t3, t6] shown in Fig. 2.11a, within [t2,
t3] or [t5, t6] shown in Fig. 2.11b, and within [t1, t4] or [t5, t6] shown in Fig. 2.11c,
will be derived. Based on these decrements, the lower limit of the inverter-side
inductor can be obtained.
According to Fig. 2.11a, the decrement of i1a within [t3, t6] can be expressed as

Vin =3 vCa 0 vCa Vin =3 vCa
Di1að1Þ ¼ t34 þ t45 þ t56
L1 L1 L1
Vin v
¼ t36
Ca
ðt36 t45 Þ þ ð2:42Þ
3L1 L1
According to Fig. 2.11b, the decrements of i1a within [t2, t3] and [t5, t6] can be,
respectively, expressed as

vCa
Di1að2Þ ¼ t23
ð2:43Þ
L1

vCa
Di1að3Þ ¼ t56
ð2:44Þ
L1
According to Fig. 2.11c, the decrement of i1a within [t1, t4] can be expressed as

Vin =3 vCa 0 vCa Vin =3 vCa
Di1að4Þ ¼ t12 þ t23 þ t34
L1 L1 L1
Vin vCa
¼ ðt14 t23 Þ t14 ð2:45Þ
3L1 L1
And the expression of the decrement of i1a within [t5, t6] is the same as (2.44).
If the SPWM is used, the following relations can be obtained from Fig. 2.11.
(
t36 ¼ Tsw ðVtri vMa Þ=2Vtri
ð2:46Þ
t45 ¼ Tsw ðVtri vMc Þ=2Vtri
(
t23 ¼ Tsw ðVtri þ vMb Þ=2Vtri
ð2:47Þ
t56 ¼ Tsw ðVtri vMa Þ=2Vtri
(
t14 ¼ Tsw ðVtri þ vMc Þ=2Vtri
ð2:48Þ
t23 ¼ Tsw ðVtri þ vMb Þ=2Vtri
If the harmonic injection SPWM is used, vMa, vMb, and vMc in (2.46)–(2.48)
should be replaced by vMaz, vMbz, and vMcz, respectively.
When the SPWM is used, vMa, vMb, and vMc given in (2.12) and Mr = VM/Vtri are
substituted into (2.46), t36 and t45 can be calculated. Then, by substituting t36, t45,
and vCa (MrVin/2)sinxot into (2.42), Di1a(1) will be obtained. On the base of
MrVinTsw/(2L1), the normalized Di1a(1) is finally expressed as

Di1að1Þ 1 1 2p Mr 2
Di1 SPWM ðxo tÞ , ¼ sin xo t þ sin xo t þ sin xo t
Mr Vin Tsw =ð2L1 Þ 6 3 3 2
ð2:49Þ
Similarly, according to (2.12), (2.43)–(2.45), (2.47) and (2.48), the normalized

Di1a(2), Di1a(3), and Di1a(4) can be derived as

Di1að2Þ 1 Mr 2p
Di2 SPWM ðxo tÞ ,
¼ sin xo t þ sin xo t
Mr Vin Tsw =ð2L1 Þ 2 2 3 ð2:50Þ

Di1að3Þ 1 Mr
Di3 SPWM ðxo tÞ ,
¼ sin xo t sin xo t ð2:51Þ
Mr Vin Tsw =ð2L1 Þ 2 2
Di1að4Þ
Di4 SPWM ðxo tÞ ,
Mr Vin Tsw =ð2L1 Þ

2 2p 1 Mr 2p

¼ sin xo t þ sin xo t sin xo t sin xo t þ
3 3 6 2 3
ð2:52Þ
Same as the above calculation procedure for the SPWM, when the harmonic
injection SPWM is used, the normalized Di1a(1), Di1a(2), Di1a(3), and Di1a(4) can be
derived, expressed as

Di1að1Þ 1 1 2p 3Mr 2
Di1 HI-SPWM ðxo tÞ , ¼ sin xo t þ sin xo t þ sin xo t
Mr Vin Tsw =ð2L1 Þ 6 3 3 4
ð2:53Þ
Di1að2Þ
Di2 HI-SPWM ðxo tÞ ,

1 Mr 2p Mr 2p

¼ sin xo t þ sin xo t þ sin xo t þ
2 2 3 4 3
ð2:54Þ
Di1að3Þ

ð2:55Þ
1 Mr Mr 2p

¼ sin xo t sin xo t sin xo t þ
2 2 4 3
Di1að4Þ

2 2p 1 3Mr 2p

¼ sin xo t þ sin xo t sin xo t sin xo t þ
3 3 6 4 3
ð2:56Þ
Note that the harmonic injection SPWM is equivalent to SVM, the discussion of
the inverter-side inductor current ripple with SVM is not repeated here.
Since sinxot = −sin(xot − 2p/3) − sin(xot + 2p/3), by substituting it into
(2.55), it is easy to find that Δi2_HI-PWM = Δi3_HI-PWM.
According to (2.49)–(2.52), the curves of Δi1_SPWM(xot), Δi2_SPWM(xot),
Δi3_SPWM(xot), and Δi4_SPWM (xot) are depicted, as shown in Fig. 2.12a.
According to (2.53)–(2.56), the curves of Δi1_HI-SPWM(xot), Δi2_HI-SPWM(xot),
Δi3_HI-SPWM (xot), and Δi4_HI-SPWM(xot) are depicted, as shown in Fig. 2.12b.
From Fig. 2.12, the maximum value of the inverter-side inductor current ripple can
be obtained. Thus, when the current ripple coefficients kc_L1 are given, the lower
limits of L1 can be determined. In addition, the maximum value of L1 can also be
calculated from (2.36). According to the lower and upper limits of L1, the value of
L1 can be properly selected.
0.6 0.6
Δ i1_SPWM ( ot) Δ i1_HI-SPWM ( ot)
Δ i2_SPWM ( ot) Δ i3_HI-SPWM ( ot)
0.4 Δ i3_SPWM ( ot) 0.4 Δ i4_HI-SPWM ( ot)

Δ i4_SPWM ( ot) Mr = 0.6
Mr = 0.6
0.2 0.2
Mr = 1 Mr = 1
0 0
0 /6 φ /3 /2 0 /6 φ /3 /2
ot ot
(a) SPWM (b) Harmonic injection SPWM
Fig. 2.12 Curves of inverter-side inductor current ripple

2.3.2 Filter Capacitor Design
The filter capacitor will lead to reactive power. The larger the capacitance is, the
higher the reactive power is introduced, and also the larger the current flows
through inductor L1 and the power switches [3]. Thus, the conduction loss of the
switches will increase. Defining kC as the ratio of the reactive power introduced by
the filter capacitor to the rated output active power of the grid-connected inverter,
the maximum value of filter capacitor could be expressed as
Po
C ¼ kC ð2:57Þ
xo Vg2
where Po is the rated output active power of single-phase full-bridge inverter or the
rated output active power of one phase for three-phase full-bridge inverter. In
practice, kC is usually recommended to be about 5% [4].
2.3.3 Grid-Side Inductor Design
According to Fig. 2.9a, the transfer function of the grid current i2 to the inverter
bridgeoutput voltage vinv can be obtained, which is
i 2 ðsÞ 1 1 x2r
GLCL ðsÞ , ¼ ¼ ð2:58Þ
vinv ðsÞ L1 L2 Cs3 þ ðL1 þ L2 Þs ðL1 þ L2 Þs s2 þ x2r
where xr is the resonance angular frequency, which is

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
L1 þ L2
xr ¼ ð2:59Þ
L1 L2 C
The expression of GLCL(s) for three-phase grid-connected inverter is the same as

(2.58).
After the inverter-side inductor and the filter capacitor are determined, the
grid-side inductor L2 could be designed according to the harmonic restriction
standards such as IEEE Std. 929-2000 and IEEE Std. 1547-2003 [5, 6]. Table 2.1
lists the current harmonic restriction, including the limits on individual harmonics
and the limit on the total harmonics distortion (THD) of the injected grid current. If
the specifications of the grid-connected inverter is given, the spectrum of vinv can be
calculated from (2.4) or (2.7), from which the angular frequency xh and amplitude
|vinv(jxh)| of the dominant harmonics can be obtained. Substituting the obtained xh
and |vinv(jxh)| into (2.59), yields
Table 2.1 Maximum harmonics limits of grid current

Harmonic order h (odd h < 11 11 h < 17 17 h < 23 23 h < 35 35 h THD
harmonic)a
Proportion to the rated 4.0 2.0 1.5 0.6 0.3 5.0
grid-connected current (%)
a
The allowable maximum limits of even harmonics is 25% of those of odd harmonics in the table
ji2 ðjxh Þj 1
¼ ð2:60Þ
jvinv ðjxh Þj L1 L2 Cðjxh Þ3 þ jxh ðL1 þ L2 Þ
According to the spectrum of the inverter bridge output voltage vinv, the angular
frequency xh and harmonic order h of the dominant harmonics can be determined.
Then, according to (2.60), Table 2.1, and the expected harmonics proportion kh, the
minimum value of L2 can be obtained, which is

1 jVinv ðjxh Þj
L2 ¼ L1 þ ð2:61Þ
L1 Cx2h 1 xh kh I2
where Vinv(jxh) and I2 are the RMS value of the inverter bridge output voltage and
the rated injected grid current, respectively. If three-phase grid-connected inverter is
used, Vinv(jxh) in (2.60) and (2.61) is replaced by VaN(jxh).
After L1, C and L2 are determined, the simulation or experimental validations is
conducted to check whether the individual harmonics and the THD of the grid
current satisfy the restriction shown in Table 2.1 or not.
2.4 Design Examples for LCL Filter
To validate the above design methods, two prototypes are designed, where
single-phase full-bridge grid-connected inverter is controlled by the unipolar
SPWM, and three-phase grid-connected inverter is controlled by the harmonic
injection SPWM. The specifications of the single-phase full-bridge grid-connected
inverter are as follows: the dc input voltage is 360 V, the rated power is 6 kW, the
carrier frequency is 10 kHz, and the grid voltage is 220 V/50 Hz. The specifica-
tions of the three-phase grid-connected inverter are as follows: the dc input voltage
is 700 V, the rated power is 20 kW, the carrier frequency is 10 kHz, and the grid
voltage is 380 V/50 Hz.
2.4 Design Examples for LCL Filter 57
2.4.1 Single-Phase LCL Filter
Setting the inductor current ripple coefficient kc_L1 to 30%, and substituting the
corresponding parameters into (2.39), the minimum value of L1 is calculated as
550 lH. Defining the ratio of the RMS value of the fundamental voltage of L1 to
that of the capacitor voltage as kv_L1, and assuming kv_L1 = 5%, the maximum
value of L1 is calculated from (2.36), which is 1.28 mH. Finally, L1 = 600 lH is
chosen.
Setting kC = 3% and substituting Po = 6 kW, Vg = 220 V, and fo = 50 Hz into
(2.58), yields C < 12 lF. Here, C = 10 lF is chosen.
Assuming that the output power factor (PF) of the grid-connected inverter equals
to 1, the fundamental RMS value of iL1 could be calculated, i.e.,
pffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 ffi
I1 ¼ IC2 þ I22 ¼ xo C Vg þ I22 = 27.28 (A). According to the dc input
voltage and the magnitude of grid voltage, the modulation ratio can be obtained,
which is Mr = 311/360 = 0.86. By substituting Mr = 0.86 into (2.7), the spectrum
of the bridge output voltage vinv can be depicted, as shown in Fig. 2.13. As seen,
the dominant harmonics locate at fh = 19.95 kHz and 20.05 kHz, and the corre-
sponding |Vinv(j2pfh)|/Vin = 28%. As long as these dominant harmonics in i2 are
attenuated to satisfy the aforementioned standards, the other harmonics in i2 will
naturally satisfy the standards. Since the orders of the dominant harmonics are
higher than 33, the required current harmonic proportion kh should be less than
0.3%. Setting kh = 0.2%, and substituting I1 = 27.28 A, |Vinv(j2pfh)|/Vin = 28%,
Vin = 360 V, L1 = 600 lH, C = 10 lF, xh = 2p 19,950, and kh = 0.2% into
(2.61) leads to L2 = 164 lH. Finally, L2 = 150 lH is selected. The final
single-phaseLCL filter parameters are listed in Table 2.2.
Figure 2.14 shows the simulation results. In Fig. 2.14a, the waveforms from top
to bottom are the inverter-side inductor current i1, the grid current i2, the capacitor
current iC and its fundamental component, respectively. In Fig. 2.14b, the wave-
forms from top to bottom are the inverter bridge output voltage vinv, the spectrums
100
30
vinv /Vin (%)
20
10
0
19.75
19.85
19.95
20.05
20.15
20.25
f (kHz)
0.05
39.65
39.75
39.85
39.95
40.05
40.15
40.25
40.35
Fig. 2.13 Calculated spectrum of vinv in single-phase LCL-type grid-connected inverter with
unipolar SPWM
Table 2.2 Parameters of single-phase LCL-type full-bridge grid-connected inverter

Parameter Symbol Value Parameter Symbol Value
Input voltage Vin 360 V Switching frequency fsw 10 kHz
Grid voltage Vg 220 V Inverter-side inductor L1 600 lH
Output power Po 6 kW Filter capacitor C 10 lF
Fundamental frequency fo 50 Hz Grid-side inductor L2 150 lH
∆i1_max=7.73 A vinv:[400 V/div]

i1:[30 A/div] I1m=40.77 A
0 0
Time:[5 ms/div]
I2=27.42 A vinv:[50 V/div]

i2:[30 A/div] I2m=38.83 A
0
50Hz
iC:[5 A/div] ICf =0.70 A, ICm=5.13 A i2:[2.5 mA/div]
Time:[5 ms/div] Freq.:[10 kHz/div]
(a) i1, i2 and vg (b) spectrum of vinv and i2
Fig. 2.14 Simulation results of single-phase full-bridge grid-connected inverter
of vinv and i2, respectively. The maximum current ripple of i1 is 7.73 A, and the
RMS value of i1 is 27.28 A. As a result, Di1_max/I1 = 28%. As seen from
Fig. 2.14b, the maximum harmonic magnitude of vinv is 100 V, and it appears at
19.95 kHz. The magnitude of the harmonic is 27.8% of Vin, which is agreement
with the calculated results shown in Fig. 2.13. Through the LCL filter, the mag-
nitude of the current harmonic in i2 at 19.95 kHz is suppressed below 0.06 A,
which is 0.15% of the rated injected grid current; and the THD of i2 is 0.8%.
Clearly, both the single harmonic and THD satisfy the restriction standards, which
validate the effectiveness of the design procedure for single-phase LCL filter.
2.4.2 Three-Phase LCL Filter
According to (2.23), the modulation ratio can be obtained as

pffiffiffi
Mr ¼ 220 2=350 ¼ 0:888. As observed from Fig. 2.12b, the maximum current
ripple of the inverter-side inductor appears at xot = 0. Setting the inductor current
ripple coefficient kc_L1 = 30%, and according to Eq. (2.49), the minimum value of
2.4 Design Examples for LCL Filter 59
Fig. 2.15 Calculated

spectrum of vaN when 100
harmonic injection SPWM is
used 30
vaN/Vin (%)
20
10
0
f (kHz)
19.75
19.95
20.05
20.25
0.05
10.1
10.2
9.8
9.9
L1 is calculated as 988 lH. Assuming kv_L1 = 5%, the maximum value of L1 is
calculated from (2.36), which is 1.16 mH. So, L1 = 1 mH is selected.
Setting kC = 5% and substituting Po = 20/3 kW, Vg = 220 V, and fo = 50 Hz
into (2.58) yields C < 22 lF. Here, C = 20 lF is selected.
Assuming PF = 1, the fundamental RMS value of iL1 could be calculated as
I1 = 30.31 A. Substituting Mr = 0.888 into (2.26), the spectrum of the output phase
voltage vaN is depicted, as shown in Fig. 2.15. As seen, the dominant harmonics
locate at fh = 9.9 kHz and 10.1 kHz, where |VaN(j2pfh)|/Vin = 17.6%. Likewise, as
long as these dominant harmonics in i2 are attenuated to satisfy the aforementioned
standards, the other harmonics in i2 will naturally satisfy the standards. Since the
orders of these dominant harmonics are higher than 33, so the required kh should be
less than 0.3%. Here, setting kh = 0.15%, and substituting I1 = 30.31 A,
|Vinv(j2pfh)|/Vin = 17.6%, Vin = 360 V, L1 = 1 mH, C = 20 lF, xh = 2p 9900
and kh = 0.15% into (2.61), produces L2 = 301 lH. Finally, L2 = 300 lH is
selected. The final three-phase LCL filter parameters are listed in Table 2.3.
Figure 2.16 shows the simulation results with the prototype parameters of
Table 2.3. In Fig. 2.16a, the waveforms from top to bottom are the inverter-side
inductor current i1a, the injected grid current i2a, the capacitor current iCa and its
fundamental component, respectively. In Fig. 2.16b, the waveforms from top to
bottom are the output phase voltage vaN, the spectrums of vaN and i2a, respectively.
The maximum current ripple of i1a is 9.5 A, and the RMS value of i1 is 30.31 A. As
a result, Di1_max/I1 = 31.4%. As seen from Fig. 2.16b, the maximum harmonic
magnitude in vaN appears at 9.9 kHz and it is about 60 V, which is 17.1% of Vin/2
and in agreement with the calculated results shown in Fig. 2.15. Through the LCL
Table 2.3 Parameters for three-phase LCL-type full-bridge grid-connected inverter

Input voltage Vin 700 V Switching frequency fsw 10 kHz
Grid voltage Vgab 380 V Inverter-side inductor L1 1 mH
Fundamental wave frequency fo 50 Hz Grid-side inductor L2 300 lH
∆ia1_max=9.5 A vaN:[400 V/div]

ia1:[30 A/div]
0 0
Time:[5 ms/div]
Ia2=30.3 A vaN:[50 V/div]

ia2:[30 A/div]
0
50Hz
iCa:[5 A/div] ICaf =1.38 A, ICam=6.63 A i2a:[2.5 mA/div]
Time:[5 ms/div] Freq.:[10 kHz/div]
(a) i1a, i2a and vag (b) spectrum of vaN and i2a
Fig. 2.16 Simulation results of three-phase grid-connected inverter
filter, the current harmonic magnitude of i2 at 9.9 kHz is suppressed below 0.05 A,
which accounts for 0.13% of the rated injected grid current. The THD of i2 is 0.8%.
Both the single harmonics and THD satisfy the restriction standards, which validate
the design procedure for three-phase LCL filter.
2.5 Summary
In this chapter, the design procedure of LCL filter is presented. The Fourier series
expansions of the inverter bridge output voltage of single- and three-phase LCL-
type grid-connected inverter with different PWM schemes are derived for the
purpose of determining the dominant harmonics which needs to be suppressed. The
harmonic spectrum shows that for single-phase inverter, the dominant harmonics
with the bipolar SPWM distribute around the carrier frequency, whereas those with
the unipolar SPWM distribute around twice the carrier frequency. For the
three-phase inverter, the dominant harmonics with both the SPWM and the har-
monic injection SPWM distribute around the carrier frequency. Considering the
permitted current ripple of the inverter-side inductor, the allowable reactive power
introduced by the filter capacitor, and the maximum harmonic limit of the grid
current, the filter parameters can be determined. The design procedure for the LCL
filter is given as follows:
(1) By limiting the maximum inductor current ripple in one cycle and the funda-
mental voltage on the inductors, the lower and upper limits of the inverter-side
inductor is obtained, from which, a proper inverter-side inductor can be
selected.
2.5 Summary 61
(2) According to the maximum reactive power introduced by the filter capacitor,
the upper limit of the filter capacitor can be obtained.
(3) By limiting the single harmonic of the grid current in accord with the restriction
standards, the minimum value of the grid-side inductor can be determined, from
which, the proper grid-side inductor can be selected.
The LCL filter design procedure is verified by simulations.
References
1. Holmes, D.G., Lipo, T.A.: Pulse Width Modulation for Power Converters: Principles and
Practice. IEEE Press & Wiley, New York, NY (2003)
2. Holmes, D.G.: A general analytical method for determining the theoretical harmonic
components of carrier based PWM strategies. In: Proceeding of Annual Conference of IEEE
Industry Applications Society, pp. 1207–1214 (1998)
5. IEEE Std. 929: IEEE Recommended Practice for Utility Interface of Photovoltaic (PV) Systems
(2000)
6. IEEE Std. 1547: IEEE Standard for Interconnecting Distributed Resources with Electric Power
Systems (2003)
Chapter 3
Magnetic Integration of LCL Filters
Abstract An LCL filter has two individual inductors. In order to reduce the volume
of magnetic components, magnetic integration of these two inductors is introduced
in this chapter. First, the integration method of the two inductors of an LCL filter is
proposed, and the magnetic circuit model of integrated inductors is built. Then,
based on this model, the coupling caused by the nonzero reluctance of the common
core is analyzed, and the coupling effect on the ability of attenuating high-frequency
harmonics of LCL filter is evaluated. According to the harmonic limits of the grid
current, the maximum allowable coupling coefficient is derived, which provides the
guidelines for selecting cross-sectional area and magnetic material of the common
core. Finally, with the help of Ansoft Maxwell software, design examples of
integrated magnetics for both single-phase and three-phase LCL filters are pre-
sented, and experiments are performed to verify the proposed method.
Keywords Grid-connected inverter LCL filter Coupling coefficient Magnetic

integration Magnetic circuit
Chapter 2 presents the design procedure for LCL filter. An LCL filter has two
individual inductors. In order to reduce the volume of magnetic components,
magnetic integration of these two inductors [1] is introduced in this chapter. First,
the integration method of the two inductors of an LCL filter is proposed, and the
magnetic circuit model of integrated inductors is built. Then, based on this model,
the coupling caused by the nonzero reluctance of the common core is analyzed, and
the coupling effect on the ability of attenuating high-frequency harmonics of LCL
filter is evaluated. According to the harmonic limits of the grid current, the maxi-
mum allowable coupling coefficient is derived, which provides the guidelines for
selecting cross-sectional area and magnetic material of the common core. Finally,
with the help of Ansoft Maxwell software, design examples of integrated magnetics
for both single-phase and three-phase LCL filters are presented, and experiments are
performed to verify the proposed method.

64 3 Magnetic Integration of LCL Filters
3.1 Magnetic Integration of LCL Filters
3.1.1 Magnetic Integration of Single-Phase LCL Filter
Figure 3.1 shows the topology of a single-phase LCL-type grid-connected inverter,

where L1 is the inverter-side inductor, C is the filter capacitor, L2 is the grid-side
inductor, i1 is the inverter-side inductor current, iC is the capacitor current, and i2 is
the grid current. As illustrated in Chap. 2, the LCL filter is designed with the
constraints that the current ripple of i1, ΔI1m, is 20–30% (peak-to-peak) of the rated
fundamental current I2 [2], and the fundamental RMS of iC, ICf, is less than 5% of I2
[3]. Under these constraints, the designed LCL filter parameters are L1 = 360 lH,
C = 10 lF, and L2 = 90 lH, and the simulation waveforms of i1, i2, and iC under
rated load are shown in Fig. 3.2, where I1m, I2m, and ICm are the maximum values of
i1, i2, and iC, respectively. As seen, ΔI1m is about 31% of I2, and ICf is about 2.6% of
I2. I1m and I2m are close to each other, and they are far larger than ICm.
An intuitive choice for inductor design is to use an individual magnetic core for
each inductor of the LCL filter, as shown in Fig. 3.3a, where EI cores are used. Due
to the symmetry of the magnetic circuit, fluxes in the I-type cores of L1 and L2 can
be obtained as
L 1 i1 L2 i2
/I1 ¼ ; /I2 ¼ ð3:1Þ
2N1 2N2
where N1 and N2 are the winding turns of L1 and L2, respectively.

If the EI cores for each inductor are with the same width and thickness, L1 and L2
can be integrated with the core structure as shown in Fig. 3.3b, where the E-type
cores and air gaps of L1 and L2 remain unchanged, and the I-type core serving as a
common flux path is arranged between the E-type cores. According to the flux
flows shown in the figure, the fluxes generated by the windings of L1 and L2 go
through the common path in the opposite directions. Thus, if the discrete inductors
are designed to meet L1/N1 = L2/N2, the flux in the common I-type core can be
obtained as
Fig. 3.1 Single-phase LCL-

type grid-connected inverter S1 S3 L1 L2
vC
+ i1 i2
iC
Vin vinv C vg
S2 S4
3.1 Magnetic Integration of LCL Filters 65
Fig. 3.2 Simulation I1m=8.52 A

i1:[30 A/div]
waveforms in single-phase I1m=40.77 A
LCL-type grid-connected
inverter 0
i2:[30 A/div] I2=27.42 A

I2m=38.83 A
0
iC:[5 A/div] ICf =0.70 A, ICm=5.13 A
Time:[5 ms/div]
Fig. 3.3 Core structures of

the two inductors for
single-phase LCL filter
(a) Discrete inductors (b) Integrated inductors
L 1 iC
/c ¼ /I1 /I2 ¼ : ð3:2Þ
2N1
It indicates that /c is generated by iC. As discussed above, ICm is far smaller than
I1m and I2m, thereby /cm will be far smaller than /I1m and /I2m (/cm, /I1m, and /I2m
are the maximum values of /c, /I1, and /I2, respectively). According to the sim-
ulation result in Fig. 3.2, we can get
/cm ICm
¼ ¼ 6:44%: ð3:3Þ
/I1m þ /I2m I1m þ I2m
Therefore, letting the E-type cores and the common I-type core operate in the
same maximum flux density, the required cross-sectional area of the common I-type
core is only 6.44% of the sum of the cross-sectional areas of the I-type cores for L1
and L2. As a result, the core volume of integrated inductors can be dramatically
reduced.
In addition, since I1m I2m, then according to (3.1), /I1m /I2m under the
condition L1/N1 = L2/N2. That means if the same maximum flux density is chosen,
the two E-type cores for the integrated inductors could have the same
cross-sectional area.
3.1.2 Magnetic Integration of Three-Phase LCL Filter
Figure 3.4 shows the topology of a three-phase LCL-type grid-connected inverter,

where i1a, i1b, and i1c are the inverter-side inductor currents, iCa, iCb, and iCc are the
capacitor currents, and i2a, i2b, and i2c are the grid currents. With the three-wire
connection, three-phase EI cores can be used for both the three inverter-side
inductors and grid-side inductors [4–6]. In this way, the proposed magnetic inte-
gration scheme can be extended to the three-phase LCL filter. The corresponding
core structure of integrated inductors is shown in Fig. 3.5, where /1a, /1b, and /1c
are the fluxes in the three legs of L1, and /2a, /2b, and /2c are the fluxes in the three
legs of L2. Their expressions are given as
L1 i1a L1 i1b L1 i1c

/1a ¼ ; /1b ¼ ; /1c ¼
N1 N1 N1
ð3:4Þ
L2 i2a L2 i2b L2 i2c
/2a ¼ ; /2b ¼ ; /2c ¼ :
N2 N2 N2
Similarly, if the condition L1/N1 = L2/N2 is met, the fluxes in the common I-type
core can be obtained as
S1 S3 S5
i1a L1 vCa i2a L2 vga
a
i1b L1 vCb i2b L2 vgb
Vin b N'
i1c L1 vCc i2c L2 vgc
c
iCa iCb iCc
S4 S6 S2 C C C
Fig. 3.4 Three-phase LCL-type grid-connected inverter

3.1 Magnetic Integration of LCL Filters 67
Fig. 3.5 Core structure of the

integrated inductors for
three-phase LCL filter
L1 iCa L1 iCc
/c1 ¼ /1a /2a ¼ ; /c2 ¼ /1c /2c ¼ : ð3:5Þ
N1 N1
From (3.5), it can be seen that the fluxes in the common I-type core are generated
by the capacitor currents, which show the same features as the single-phase inte-
grated inductors.
3.2 Coupling Effect on Attenuating Ability of LCL Filter
In the previous analysis, the reluctance of the common I-type core is ignored, and
thus, the integrated inductors are considered to be decoupled. However, in practice,
due to the nonzero reluctance of the common I-type core, the coupling between the
integrated inductors can hardly be avoided. The coupling effect on the LCL filter is
analyzed in this section.
3.2.1 Magnetic Circuit of Integrated Inductors
Taking the single-phase LCL filter as the example, the magnetic circuit of the
integrated inductors is shown in Fig. 3.6a where Rc1 and Rc2 are the reluctances of
the outer legs and the center leg for L1, Rc3 and Rc4 are the reluctances of the outer
legs and the center leg for L2, Rg1 and Rg2 are the reluctances of the center-leg air
gaps for L1 and L2, and Rcc is the reluctance of a half of the common I-type core.
Due to the symmetry of the magnetic circuit, Fig. 3.6a can be simplified into
Fig. 3.6b, from which the coupling coefficients of L1 to L2 and L2 to L1 can be
obtained as
Fig. 3.6 Magnetic circuit of (a) (b)

the integrated inductors 1
Rc1 Rc2 Rc1 2 Rc1 Rc2
N1i1 +
_ N1i1 +
_
2Rg1 Rg1 2Rg1 Rg1 Rg1

1
Rcc Rcc 2 Rcc
2Rg2 Rg2 2Rg2 Rg2 Rg2
N 2i 2 +
_ N 2i 2 +
_
1
Rc3 Rc4 Rc3 2 Rc3 Rc4
Rcc
k12 ¼
Rcc þ Rc3 þ 2Rc4 þ 4Rg2
ð3:6Þ
Rcc
k21 ¼ :
Rcc þ Rc1 þ 2Rc2 þ 4Rg1
Note that Rc1–Rc4 are far smaller than Rg1 and Rg2, so (3.6) can be approximated as
Rcc Rcc
k12 ; k21 : ð3:7Þ
4Rg2 4Rg1
Thus, the coupling coefficient between L1 and L2 is

pffiffiffiffiffiffiffiffiffiffiffiffi Rcc
k¼ k12 k21 pffiffiffiffiffiffiffiffiffiffiffiffiffi : ð3:8Þ
4 Rg1 Rg2
As seen, k is mainly determined by the reluctances of the air gaps and the
common I-type core. These reluctances are expressed as
d1 d2 lc
Rg1 ¼ ; Rg2 ¼ ; Rcc ¼ ð3:9Þ
l0 Aee l0 Aee 2l0 lr Aec
where d1 and d2 are the air gaps of the center legs for L1 and L2, respectively; lc is
the width of the EI core, l0 is the absolute permeability of free space, lr is the
relative permeability of the common I-type core, and Aee and Aec are the
cross-sectional areas of the center legs and the common I-type core, respectively.
Substituting (3.9) into (3.8) yields
1 Aee lc
k¼ pffiffiffiffiffiffiffiffiffi : ð3:10Þ
8lr Aec d1 d2
3.2 Coupling Effect on Attenuating Ability of LCL Filter 69
Note that Aee and lc are specified for a selected EI core, and d1 and d2 are
determined by the values of L1 and L2, respectively; thus, the coupling coefficient
can be specified after lr and Aec are confirmed.
3.2.2 Characteristics of LCL Filter with Coupled Inductors
Considering the coupling between L1 and L2, the equivalent circuit of the LCL filter
with coupled inductors is shown in Fig. 3.7a, where the inverter bridge output
voltage vinv is represented by a voltage source, and M is the mutual inductance,
pffiffiffiffiffiffiffiffiffiffi
expressed as M ¼ k L1 L2 . Figure 3.7a can be simplified into Fig. 3.7b, which is
further transformed into Fig. 3.7c using Y-D transformation. As seen in Fig. 3.7c,
the LCL filter with coupled inductors is equivalent to a parallel connection of an
L filter and an LCL filter, where the L filter is L3d, and the LCL filter is composed of
L1d, C, and L2d. L1d–L3d are expressed as
L1 L2 M 2 L1 L2 M 2 L1 L2 M 2
L1d ¼ ; L2d ¼ ; L3d ¼ : ð3:11Þ
L2 þ M L1 þ M M
As seen in Fig. 3.7c, the grid current i2 is the summation of i21 and i22, where i21
is supplied by the L filter branch, and i22 is supplied by the LCL filter branch. The
transfer functions from vAB to i21, i22, and i2 can be derived as
i21 ðsÞ 1
Gi21 ðsÞ ¼ ¼
vinv ðsÞ sL3d
i22 ðsÞ 1
Gi22 ðsÞ ¼ ¼ 3 ð3:12Þ
vinv ðsÞ s L1d L2d C þ sðL1d þ L2d Þ
i2 ðsÞ 1 1
Gi2 ðsÞ ¼ ¼ þ 3
vinv ðsÞ sL3d s L1d L2d C þ sðL1d þ L2d Þ
With the parameters L1 = 360 lH, C = 10 lF, L2 = 90 lH, and k = 0.01, the
magnitude plots of Gi21(s), Gi22(s), and Gi2(s) are shown in Fig. 3.8. As seen, the
magnitude plot of Gi21(s) is a straight line with slope of −20 dB/dec; the magnitude
plot of Gi22(s) has a resonance peak, and it falls with slope of −60 dB/dec above the
(a) M (b) (c) L3d i21

L1 L2 L1+M L2+M
i1 i2 i1 i2 L1d L2d
iC M i1 i22 i2
iC
vinv C vg vinv iC vg
vinv C vg
C
Fig. 3.7 Equivalent circuit of the LCL filter with coupled inductors
Fig. 3.8 Magnitude plots of 40

Gi21(s), Gi22(s), and Gi2(s)
0
Magnitude (dB)
40
80 20 dB
/dec
60
120
Gi21 dB
Gi22 /de
Gi2 c
160
102 103 104fint 105 106
Frequency (Hz)
resonance frequency, which indicates high harmonics attenuation. The frequency

where the magnitude plots of Gi21(s) and Gi22(s) intersect is called the intersection
frequency, and it is denoted by fint. Solving |Gi21(s)| = |Gi22(s)|, fint can be calculated
as
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1 L1d þ L2d L3d 1 L1 L2 þ 2M ðL1 þ L2 Þ þ 3M 2
fint ¼ ¼ : ð3:13Þ
2p L1d L2d C 2p ðL1 L2 M 2 ÞMC
The magnitude plot of Gi2(s) is the combination of those of Gi21(s) and Gi22(s).
As seen in Fig. 3.8, Gi22(s) dominates at the frequencies lower than fint, and
Gi21(s) dominates at the frequencies higher than fint. Compared with the LCL filter,
the LCL filter with coupled inductors has a poorer harmonic attenuation at the
frequencies higher than fint. Hence, to ensure the effective attenuation of the
switching harmonics, fint must be higher than the frequency where the dominant
switching harmonics lie in. According to (3.13), the curve of fint as the function of
k is depicted in Fig. 3.9. As seen, fint increases with the decrease in k. Thus, to make
the integrated LCL filter applicable, the coupling coefficient must be limited.
Fig. 3.9 Curve of fint as the 90

function of k
70
fint (kHz)
50
30
0.017
10
0 0.01 0.02 0.03 0.04 0.05
k
3.3 Design Examples 71
3.3 Design Examples
3.3.1 Magnetics Design for Single-Phase LCL Filter
Table 3.1 gives the parameters of a 6-kW single-phase LCL-type grid-connected

inverter, where the unipolar sinusoidal pulse-width modulation (SPWM) is adopted.
Magnetic cores are selected with the well-known area product method [7].
Referring to the product catalog of NCD EE ferrite cores [8], two pairs of
EE70/33/32 are used for L1; 32-turn windings are designed and fabricated by
copper foils with width of 40 mm and thickness of 0.2 mm, and the air gap
d1 = 2.4 mm. Moving the air gaps in the EE core to the end of the window, the
equivalent EI core is obtained, as shown in Fig. 3.10. The core sizes are listed as
A1–H1 in Table 3.2.
As discussed in Sect. 3.1.1, the EI core for L2 is in the same dimensions as
the one for L1 except for the window height. N2 = 8 turns can be derived from
L1/N1 = L2/N2, and the air gap d2 = 0.6 mm. To ensure the same window utiliza-
tion and current density, the windings of L2 are fabricated by copper foils with
width of 10 mm and thickness of 0.8 mm. Considering the isolation requirements, a
margin of 1 mm should be reserved at both ends of the windings [9]. Thus, a
window height of 12 mm is necessary for L2, i.e., F2 = 12 mm. Consequently, the
overall core sizes for L2 are listed as A2 – H2 in Table 3.2. According to Table 3.2,
the core volumes for L1 and L2 can be calculated as
Table 3.1 Parameters of single-phase prototype

Input voltage Vin 360 V Inverter-side inductor L1 360 lH
Grid voltage (RMS) Vg 220 V Filter capacitor C 10 lF
Output power Po 6 kW Grid-side inductor L2 90 lH
Fundamental frequency fo 50 Hz Switching frequency fsw 15 kHz
Fig. 3.10 EI-type magnetic

core
A
E
D
E
B
F
G H
Table 3.2 Parameters of Symbol Value (mm) Symbol Value (mm)

single-phase prototype
A1 70.5 A2 70.5
B1 55.1 B2 23.3
D1 22 D2 22
E1 13 E2 13
F1 43.8 F2 12
G1 31.6 G2 31.6
H1 11.3 H2 11.3
Ve1 ¼ 2A1 ðB1 þ H1 ÞG1 4E1 F1 G1 ¼ 2:24 105 mm3

ð3:14Þ
Ve2 ¼ 2A2 ðB2 þ H2 ÞG2 4E2 F2 G2 ¼ 1:34 105 mm3 :
Using the core structure shown in Fig. 3.3b for the integration of L1 and L2,
while the two parts of the E-type cores remain unchanged, the key issue lies in the
design of the common I-type core. As seen in (3.10), a larger Aec or a higher lr is
expected for a smaller coupling coefficient k. Since the common I-type core keeps
the same width and thickness as those of the E-type cores, its cross-sectional area
Aec is determined by the height Hc. And lr is related to the magnetic material that
used. Thus, to limit the coupling coefficient, the height and magnetic material of the
common I-type core need to be selected with caution.
With the limit of maximum flux density, according to (3.3), the minimum height
of the common I-type core can be obtained as
Hc min ¼ 6:44%ðH1 þ H2 Þ 2 mm: ð3:15Þ
Here, the widely used soft ferrite and silicon steel are investigated. For NCD
ferrite core, lr = 1725 [8], and for the silicon steel, lr = 5660 [10]. Based on the
Ansoft Maxwell 3D model shown in Fig. 3.11a, a more detailed investigation of the
relationship between k and Hc is carried out by simulation. The simulation result is
shown in Fig. 3.11b, where Hc 2 mm is constrained by the maximum flux
density, and Hc 22 mm is constrained to ensure that Hc will not exceed the
summation of H1 and H2. From Fig. 3.11b, Hc can be determined according to the
requirement of k.
For the single-phase grid-connected inverter adopting the unipolar SPWM, the
dominant switching harmonics are placed around twice the switching frequency
[11], i.e., 30 kHz. As previously mentioned, fint > 30 kHz is required. To achieve
that, as shown in Fig. 3.9, k < 0.017 has to be satisfied. Recalling Fig. 3.11b, if
NCD ferrite core is used for the common I-type core, k < 0.017 cannot be achieved
even if Hc = 22 mm; if the silicon steel is used for the common I-type core,
k < 0.017 can be achieved if Hc > 8 mm. Therefore, the silicon steel is preferred in
practical application. By making a tradeoff between the core volume and the
coupling coefficient, Hc = 11 mm is chosen since a further increase in Hc only
results in a little decrease in k. Thus, the reduced core volume is
0.16
Soft Ferrite
0.12 Silicon Steel
0.08
k
0.04
0.017
0
2 4 6 8 10 12 14 16 18 20 22
Hc (mm)
(a) 3-D model (b) Simulation results
Fig. 3.11 Ansoft Maxwell 3D model and simulation results
DVe ¼ 2A1 ðH1 þ H2 Hc ÞG1 ¼ 5:17 104 mm3 : ð3:16Þ
Compared with the total core volume of the discrete inductors, the reduced core
volume in percentage terms is
DVe
DVe % ¼ 100% ¼ 14:4%: ð3:17Þ
Ve1 þ Ve2
3.3.2 Magnetics Design for Three-Phase LCL Filter
Table 3.3 gives the parameters of a 20-kW three-phase LCL-type grid-connected

inverter, and the space vector modulation is adopted. The three-phase silicon steel
cores are used. Referring to the electronic transformer handbook [10], two pairs of
BSD 25 25 80 are selected and then cut into two parts with the ratio of 3:1 in
the window height. These two parts are served as three-phase E-type cores for L1
and L2, respectively (see Fig. 3.12b in Sect. 3.4). For L1, N1 = 50 turns, and the
windings are fabricated by copper foils with width of 60 mm and thickness of
0.15 mm, and for L2, N2 = 15 turns, and the windings are fabricated by copper foils
with width of 18 mm and thickness of 0.5 mm. The core structure shown in
Fig. 3.5 is used for the integration of L1 and L2. With the same design procedure
mentioned above, the common I-type core is fabricated by the silicon steel with a
height of 25 mm. Consequently, the reduced core volume can be calculated as
17.5%.
Table 3.13 Parameters of three-phase prototype

Input voltage Vin 700 V Inverter-side inductor L1 1 mH
Grid voltage (RMS) Vg 220 V Filter capacitor C 20 lF
Fig. 3.12 Photographs of the

integrated inductors
L1 L1 L1 L1
L2
L2 L2
L2
(a) Single phase (b) Three phase
3.4 Experimental Verification
Both 6-kW single-phase and 20-kW three-phase prototypes are built and tested in
the laboratory.
3.4.1 Experimental Results for Single-Phase LCL Filter
In the single-phase system, referring to Table 3.2, one pair of EE70/54/32 can be
used for the E-type core of L1. However, the E-type core required for L2 is irregular,
and for simplicity, it is replaced by one pair of EE70/33/32. As for the common
I-type cores, both the soft ferrite and silicon steel are evaluated, and Hc = 11 mm is
chosen in both cases. Figure 3.12a shows the photograph of the integrated
inductors.
According to IEEE std.1547-2003 [12], the harmonics higher than 35th in the
grid current are limited to 0.3% of its rated value. For the 6-kW single-phase
prototype, the rated current is 38.6 A, and thus, the harmonic limit is 116 mA.
Figure 3.13 shows the experimental results with discrete inductors. As seen, the key
switching harmonics in i1 are placed around multiples of twice the switching fre-
quency. Because of the high attenuating ability of the LCL filter, only a little
switching harmonics are injected into the grid. The dominant switching harmonics
in i2 are placed around 30 kHz with maximum amplitude of about 52 mA.
3.4 Experimental Verification 75
i1:[30 A/div]
i1:[50 mA/div]
i2:[30 A/div] Harmonic limit: 116mA
i2:[50 mA/div]
Time: [5 ms/div] 0 30kHz 60kHz 90kHz 120kHz
(a) Experimental waveform (b) Harmonic spectra
Fig. 3.13 Experimental results with discrete inductors in single-phase prototype
i1:[30 A/div]
i1:[100 mA/div]
i2:[30 A/div] i2:[100 mA/div]

Harmonic limit: 116mA

Fig. 3.14 Experimental results with integrated inductors in single-phase prototype (soft ferrite
used for the common I-type core)
The experimental results with integrated inductors are shown in Figs. 3.14 and
3.15. If the soft ferrite is used for the common I-type core, the measured coupling
coefficient is k = 0.045, which is larger than 0.017, and thus, the attenuating ability
of the LCL filter around 30 kHz is weakened. As seen in Fig. 3.14b, the maximum
amplitude of the dominant switching harmonics is about 100 mA, which is nearly
twice the one for discrete inductors. Fortunately, if the silicon steel is used for the
common I-type core, the measured coupling coefficient is k = 0.012, which is lower
than 0.017, and thus, the high attenuating ability of the LCL filter around 30 kHz is
remained. As seen in Fig. 3.15b, the maximum amplitude of the dominant
switching harmonics is about 60 mA, which is close to the one for discrete
inductors.
i1:[30 A/div]
i1:[50 mA/div]
i2:[30 A/div] Harmonic limit: 116mA
i2:[50 mA/div]

Fig. 3.15 Experimental results with integrated inductors in single-phase prototype (silicon steel
used for the common I-type core)
3.4.2 Experimental Results for Three-Phase LCL Filter
In the three-phase system, the three-phase integrated inductors are implemented

with the design procedure depicted in Sect. 3.3.2, the photograph is shown in
Fig. 3.12b, and the measured coupling coefficient between L1 and L2 is k = 0.02.
The harmonic limit for the 20-kW three-phase prototype is calculated as 128 mA.
Figure 3.16 shows the experimental results with discrete inductors. As seen, the key
switching harmonics in i1a are placed around multiples of the switching frequency.
And the maximum amplitude of the dominant switching harmonics in i2a is about
92 mA. Figure 3.17 shows the experimental results with integrated inductors, and
the maximum amplitude of the dominant switching harmonics in i2a is about
100 mA, which is close to the one for discrete inductors. Experimental results from
both the single-phase and three-phase prototypes confirm the theoretical
expectations.
i1a:[30 A/div] i1c:[30 A/div] i1b:[30 A/div]

i1a:[100 mA/div]
i2a:[30 A/div] i2c:[30 A/div] i2b:[30 A/div] i2a:[100 mA/div]

Time:[5 ms/div] 0 20kHz 40kHz 60kHz 80kHz

Fig. 3.16 Experimental results with discrete inductors in three-phase prototype

3.5 Summary 77
i1a:[30 A/div] i1c:[30 A/div] i1b:[30 A/div]

i1a:[100 mA/div]
i2a:[30 A/div] i2c:[30 A/div] i2b:[30 A/div] i2a:[100 mA/div]

Time:[5 ms/div] 0 20kHz 40kHz 60kHz 80kHz

Fig. 3.17 Experimental results with integrated inductors in three-phase prototype
3.5 Summary
This Chapter proposes the magnetic integration of the LCL filter in both
single-phase and three-phase grid-connected inverters. By sharing an ungapped
core and arranging the windings properly, the fundamental fluxes generated by the
two inductors of the LCL filter cancel out mostly in the common core. The coupling
caused by the nonzero reluctance of the common core is considered, and the
coupling effect on the attenuating ability of the LCL filter is analyzed. It turns out
that the LCL filter with coupled inductors is equivalent to a parallel connection of an
L filter and an LCL filter. In order to meet the harmonic limits, the cross-sectional
area and magnetic material of the common core are properly selected, ensuring the
coupling coefficient of the integrated inductors be limited to a satisfactory range.
With the proposed magnetic integration scheme, core volume is reduced by 14.4%
for a 6-kW single-phase prototype and 17.5% for a 20-kW three-phase prototype,
respectively. Experimental results from both single-phase and three-phase proto-
types confirm the theoretical expectations.
References
1. Pan, D., Ruan, X., Bao, C., Li, W., Wang, X.: Magnetic integration of the LCL filter in
grid-connected inverters. IEEE Trans. Power Electron. 29(4), 1573–1578 (2014)
2. Wang, T.C., Ye, Z., Sinha, G., and Yuan, X.: Output filter design for a grid-interconnected
three-phase inverter. In: Proceeding IEEE Power Electronics Specialists Conference,
pp. 779–784 (2003)
4. Wei, L., Lukaszewski, R.A.: Optimization of the main inductor in a LCL filter for three phase
active rectifier. In: Proceeding Annual Conference of IEEE Industry Applications Society,
pp. 1816–1822 (2007)
5. Bueno, E.J., Cóbreces, S., Rodríguez, F.J., Hernández, Á., Espinosa, F.: Design of a
back-to-back NPC converter interface for wind turbines with squirrel-cage induction
generator. IEEE Trans. Energy Convers. 23(3), 932–945 (2008)
6. Wei, L., Patel, Y., Murthy, C.: Evaluation of LCL filter inductor and active front end rectifier
losses under different PWM method. In: Proceeding of the IEEE Energy Conversion Congress
and Exposition, pp. 3019–3026 (2013)
7. Zhao, X.: Utility Power Supply Technology Handbook of Magnetic Components. Liaoning
Science and Technology Publishing House, Shenyang (2002). (in Chinese)
8. EE Ferrite Cores.: Nanjing New Conda Magnetic Industrial Co. Ltd. (2013) [Online].
Available: http://ncd.com.cn/category/eecores-2599-e179/1
9. Dixon, L.H.: Magnetics Design for Switching Power Supplies. Texas Instruments.
(2011) [Online]. Available: http://focus.ti.com/docs/training/catalog/events/event.jhtml?sku=
SEM401014
10. Wang, Q.: Electronic Transformer Handbook. Liaoning Science and Technology Publishing
House, Shenyang (2007). (in Chinese)
Practice. IEEE Press & Wiley, New York (2003)
12. IEEE Standard for Interconnecting Distributed Resources with Electric Power Systems.: IEEE
Std. 1547-2003 (2003)
Chapter 4
Resonance Damping Methods
of LCL Filter
Abstract The control challenges of LCL-type grid-connected inverter arise from

the resonance problem. At the resonance frequency, the LCL filter resonance causes
a sharp phase step down of −180° with a high resonance peak. This resonance peak
would easily lead to system instability and should be damped. In this chapter, the
resonance hazard resulted by the LCL filter is reviewed first, and then, the existing
passive- and active-damping solutions are described systematically to reveal the
relationship among them. Among the six basic passive-damping solutions, adding a
resistor in parallel with capacitor shows the best damping performance, but it results
in a high power loss. In order to avoid the power loss in the damping resistor, the
active-damping solutions equivalent to a resistor in parallel with capacitor are
derived, and the capacitor-current-feedback active damping is superior for its
simple implementation and effectiveness. This chapter provides the basis for the
study of the control techniques of LCL-type grid-connected inverter in the fol-
lowing chapters.
Keywords Grid-connected inverter LCL filter Resonance Passive damping

Active damping
Chapters 2 and 3 have presented the design and magnetic integration of LCL filters.
In the following chapters, the control techniques for the LCL-type grid-connected
inverter will be discussed. The control challenges of LCL-type grid-connected
inverter arise from the resonance problem. At the resonance frequency, the LCL
filter resonance causes a sharp phase step down of −180° with a high resonance
peak. This resonance peak would easily lead to system instability and should be
damped. In this chapter, the resonance hazard resulted by the LCL filter is reviewed
first, and then, the existing passive- and active-damping solutions are described
systematically to reveal the relationship among them.

80 4 Resonance Damping Methods of LCL Filter
4.1 Resonance Hazard of LCL Filter
Figure 4.1a shows the main circuit of a single-phase LCL-type grid-connected

inverter, where L1 is the inverter-side inductor, C is the filter capacitor, and L2 is the
grid-side inductor. By representing the inverter bridge output voltage vinv with a
voltage source, Fig. 4.1a can be simplified into Fig. 4.1b, from which the transfer
function from vinv to the grid current i2 can be derived as
i 2 ðsÞ 1 1 1
GLCL ðsÞ ¼ ¼ ¼ ð4:1Þ
vinv ðsÞ s3 L1 L2 C þ sðL1 þ L2 Þ sL1 L2 C s2 þ x2r
where xr is the resonance angular frequency of the LCL filter, expressed as

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
L1 þ L2
xr ¼ ð4:2Þ
L1 L2 C
and the resonance frequency is fr ¼ xr =ð2pÞ.

According to (4.1), the Bode diagram of GLCL(s) is shown with the solid line, as
shown in Fig. 4.2. As seen, at the resonance frequency fr, the LCL filter resonance
causes a sharp phase step down of −180° with a high resonance peak. From a
control perspective, this −180° crossing is a negative crossing, and it will create a
pair of closed-loop right-half plane poles [1], leading to system instability.
Therefore, in order to stabilize the system, the resonance peak must be damped
below 0 dB so that the negative crossing can be avoided. To achieve the resonance
damping, a first-order term related to s needs to be incorporated into the resonant
term s2 þ x2r of (4.1), yields
1 1
GLCLd ðsÞ ¼ ð4:3Þ
sL1 L2 C s2 þ 2nxr s þ x2r
where n is the damping ratio. According to (4.3), the Bode diagram of GLCL-d(s) is
depicted with the dashed line, as shown in Fig. 4.2. It can be seen that by
S1 S3 L1 L2
vC
+ i1 i2 L1 vC L2
iC
Vin vinv C vg + i1 i2 +
iC
vinv C vg
S2 S4
(a) Main circuit (b) Simplified circuit
Fig. 4.1 Single-phase LCL-type grid-connected inverter

4.1 Resonance Hazard of LCL Filter 81
Fig. 4.2 Frequency response 50

of the LCL filter
Magnitude (dB)
0
50
100
150
0
Phase (°) 90
180
270 w/ damping
w/o damping
360
10 102 103 fr 104 105
Frequency (Hz)
introducing the damping term, the resonance peak of LCL filter is effectively
suppressed, while the magnitude-frequency characteristics at the low- and
high-frequency ranges remain unchanged. This is helpful to providing high
low-frequency gains and strong high-frequency harmonic attenuating ability, and is
exactly desirable as expected.
4.2 Passive-Damping Solutions
4.2.1 Basic Passive Damping
As discussed above, the resonance hazard of LCL filter calls for damping solutions
to stabilize the system. A direct way to damp the LCL filter resonance is to insert a
resistor into the filter network, which is called the passive damping. According to
the location of the resistor, there are six basic passive-damping solutions, as shown
in Fig. 4.3. A detailed analysis of these solutions is presented in the following.
As shown in Fig. 4.3a, resistor RL11 is introduced to be in series with L1, and the
transfer function from vinv to i2 can be derived as
i2 ðsÞ 1
GLCL1 ðsÞ ¼ ¼ : ð4:4Þ
vinv ðsÞ s3 L1 L2 C þ s2 L2 CRL11 þ sðL1 þ L2 Þ þ RL11
When resistor RL21 is introduced to be in series with L2, as shown in Fig. 4.3b,
the transfer function from vinv to i2 can be derived as
L1 RL11 vC L2 L1 vC RL21 L2
+ i1 i2 + + i1 i2 +
iC iC
vinv C vg vinv C vg
(a) Resistor in series with L1 (b) Resistor in series with L2

RL12 RL22
L1 vC L2 L1 vC L2
+ i1 i2 + + i1 i2 +
iC iC
vinv C vg vinv C vg
(c) Resistor in parallel with L1 (d) Resistor in parallel with L2

L1 vC L2 L1 vC L2
+ i1 iC i2 + + i1 iC i2 +
C
vinv vg vinv C RC2 vg
RC1
(e) Resistor in series with C (f) Resistor in parallel with C
Fig. 4.3 Six basic passive-damping solutions
i2 ðsÞ 1
GLCL2 ðsÞ ¼ ¼ 3 : ð4:5Þ
vinv ðsÞ s L1 L2 C þ s L1 CRL21 þ sðL1 þ L2 Þ þ RL21
2
If resistor RL12 is located in parallel with L1, as shown in Fig. 4.3c, the transfer
function from vinv to i2 can be derived as
i2 ðsÞ sL1 =RL12 þ 1

GLCL3 ðsÞ ¼ ¼ 3 : ð4:6Þ
vinv ðsÞ s L1 L2 C þ s2 L1 L2 =RL12 þ sðL1 þ L2 Þ
The resistor, denoted as RL22, can also be added to be in parallel with L2, as
shown in Fig. 4.3d, and the transfer function from vinv to i2 can be derived as
i2 ðsÞ sL2 =RL22 þ 1

vinv ðsÞ s3 L1 L2 C þ s2 L1 L2 =RL22 þ sðL1 þ L2 Þ
When resistor RC1 is placed in series with C, as shown in Fig. 4.3e, the transfer
4.2 Passive-Damping Solutions 83
i 2 ðsÞ sCRC1 þ 1
vinv ðsÞ s3 L1 L2 C þ s2 ðL1 þ L2 ÞCRC1 þ sðL1 þ L2 Þ
Also, incorporating the resistor, denoted as RC2, to be in parallel with C, as

shown in Fig. 4.3f, can effectively damp the resonance peak, and the transfer
i2 ðsÞ 1
vinv ðsÞ s3 L1 L2 C þ s2 L1 L2 =RC2 þ sðL1 þ L2 Þ
Comparing (4.4) and (4.5) with (4.1), it can be seen that when the resistor is
added in series with L1 and L2, respectively, the transfer functions from vinv to i2 are
similar, in which, a damping term (the second-order term related to s) and a con-
stant term are added to the denominator of GLCL(s). Comparing (4.6), (4.7), and
(4.8) with (4.1), it can be seen that when the resistor is added in parallel with L1 and
L2, respectively, or the resistor is added in series with C, the transfer functions from
vinv to i2 are similar, in which, a zero is added besides introducing a damping term.
When the resistor is introduced to be in parallel with C, the transfer function from
vinv to i2, shown in (4.9) is similar to (4.3), which is the desired form with only a
damping term being added.
According to (4.4)–(4.9), the frequency responses of the six basic
passive-damping solutions are depicted, as shown in Fig. 4.4. From which, it can be
seen that:
(1) Resistor in series with inductors will reduce the low-frequency gains of LCL
filter, as shown in Fig. 4.4a, b. This is because that at the low-frequency range,
the inductor reactance is relatively small, and a series resistor distinctly
increases the impedance of inductor branch, making the gains lower. The larger
the series resistor is, the more the low-frequency gains are reduced. While at the
high-frequency range, the inductor reactance is far larger than the value of
series resistor, the series resistor can be ignored, and thus it has no effect on the
high-frequency gains of LCL filter.
(2) Resistor in parallel with inductors will weaken the high-frequency harmonic
attenuating ability of LCL filter, as shown in Fig. 4.4c, d. This is because that at
the high frequencies, the inductor reactance is relatively large, and a parallel
resistor distinctly reduces the impedance of inductor branch, lowering the
harmonic attenuating ability. The smaller the parallel resistor is, the poorer the
high-frequency harmonic attenuating ability becomes. While at the low fre-
quencies, the inductor reactance is far smaller than the value of the parallel
resistor, the parallel resistor can be ignored, and thus it has no effect on the
low-frequency gains of LCL filter.
(3) Resistor in series with capacitor will weaken the high-frequency harmonic
attenuating ability of LCL filter, as shown in Fig. 4.4e. This is because that at
the high-frequency range, the capacitor reactance is relatively small, and a
series resistor distinctly increases the impedance of capacitor branch, lowering
50 50
Magnitude (dB)
Magnitude (dB)
0 0
−50 −50
−100 −100
−150 −150
0 0
−90 −90
Phase (°)
Phase (°)
−180 −180
−270 RL11=0 Ω −270 RL21=0 Ω

RL11=1 Ω RL21=1 Ω
RL11=10 Ω RL21=10 Ω
−360 −360
10 102 103 104 105 10 102 103 104 105
Frequency (Hz) Frequency (Hz)
(a) Resistor in series with L1 (b) Resistor in series with L2
50 50
Magnitude (dB)
Magnitude (dB)
0 0
−50 −50
−100 −100
−150 −150
0 0
−90 −90
Phase (°)
Phase (°)
−180 −180
−270 RL12= ∞ Ω −270 RL22= ∞ Ω

RL12=10 Ω RL22=10 Ω
RL12=1 Ω RL22=1 Ω
−360 −360
5
10 102 103 104 105 10 102 103 104 10
(c) Resistor in parallel with L1 (d) Resistor in parallel with L2
50 50
Magnitude (dB)
Magnitude (dB)
0 0
−50 −50
−100 −100
−150 −150
0 0
−90 −90
Phase (°)
Phase (°)
−180 −180
−270 RC1=0 Ω −270 RC2= ∞ Ω

RC1=1 Ω RC2=10 Ω
RC1=10 Ω RC2=1 Ω
−360 −360
10 102 103 104 105 10 102 103 104 105
(e) Resistor in series with C (f) Resistor in parallel with C
Fig. 4.4 Frequency responses of the six basic passive-damping solutions

the harmonic attenuating ability. The larger the series resistor is, the poorer the
high-frequency harmonic attenuating ability becomes. While at the
low-frequency range, the capacitor reactance is far larger than the value of
series resistor, the series resistor can be ignored, and thus it has no effect on the
low-frequency gains of LCL filter.
(4) Resistor in parallel with capacitor will not affect the magnitude-frequency
characteristics of LCL filter at the low- and high-frequency ranges, as shown in
Fig. 4.4f. This is because that at the low-frequency range, the reactance of L2 is
far smaller than the value of parallel resistor, the parallel resistor can be ignored;
while at the high-frequency range, the capacitor reactance is far smaller than the
value of parallel resistor, the parallel resistor can also be ignored.
From the above analysis, it can be known that introducing a resistor in parallel
with the filter capacitor C shows the best damping performance among the six basic
passive-damping solutions. However, since the voltage drop on L2 is relatively
small, the capacitor voltage is much close to the grid voltage, and it is directly
applied on the parallel resistor, resulting in a high power loss. Thus, the
passive-damping solution using a resistor in parallel with the capacitor is not
applicable in practice. Comparatively, the damping solution using a resistor in
series with the capacitor has been widely used for its lower loss [2, 3].
4.2.2 Improved Passive Damping
Based on the passive-damping solution of adding a resistor in series with the

capacitor, several improved solutions has been proposed in [4–7] to further reduce
the power loss in the damping resistor. Figure 4.5 shows four representative
improved passive-damping solutions, which will be analyzed in the following.
(1) Adding a Bypass Inductor
As seen in Fig. 4.5a, an inductor Ld is connected in parallel with the damping
resistor RC1. At the fundamental frequency, the reactance of Ld is far smaller
than the value of RC1, thus the fundamental current in C is almost bypassed by
Ld, leading to reduced power loss in RC1. From Fig. 4.5a, the transfer function
from vinv to i2 can be derived as
i 2 ðsÞ
GLCL5a ðsÞ ¼
vinv ðsÞ
s2 Ld CRC1 þ sLd þ RC1
¼
s4 L1 L2 Ld C þ s3 ½L1 L2 þ ðL1 þ L2 ÞLd CRC1 þ s2 ðL1 þ L2 ÞLd þ sðL1 þ L2 ÞRC1
ð4:10Þ
L1 L2 L1 L2
+ i1 i2 + + i1 i2 +
C C
vinv vg vinv vg
Ld RC1 Ld RC1 Cd
(a) Adding a bypass inductor (b) Adding a bypass inductor and capacitor
L1 L2 L1 L2
+ i1 i2 + + i1 i2 +
C1 C1
vinv C2 vg vinv C2 vg
RC1 Ld RC1
(c) Splitting the capacitor (d) Splitting the capacitor and adding a bypass inductor
Fig. 4.5 Four improved passive-damping solutions
(2) Adding a Bypass Inductor and Capacitor

Based on Fig. 4.5a, a capacitor Cd is further connected in parallel with the
damping resistor RC1, as shown in Fig. 4.5b. At the high-frequency range, the
reactance of Cd is far smaller than the value of RC1, thus the high-frequency
harmonic current in C is almost bypassed by Cd, and the high-frequency loss of
RC1 is reduced. Moreover, Cd also reduces the high-frequency impedance of
capacitor branch, which makes the LCL filter still have a high harmonic
attenuating ability after damping. From Fig. 4.5b, the transfer function from
vinv to i2 can be derived as
i2 ðsÞ
GLCL5b ðsÞ ¼
vinv ðsÞ
s2 Ld ðC þ Cd ÞRC1 þ sLd þ RC1
¼2 3 ð4:11Þ
s5 L1 L2 Ld CCd RC1 þ s4 L1 L2 Ld C
6 7
6 þ s3 ½L L C þ ðL þ L ÞL ðC þ C ÞR 7
4 1 2 1 2 d d C1 5
þ s2 ðL1 þ L2 ÞLd þ sðL1 þ L2 ÞRC1
(3) Splitting the Capacitor

Besides adding bypass components to the damping resistor, the capacitor C can
be split into two ones, and resistor RC1 is in series with one of the capacitors,
C1, as shown in Fig. 4.5c. Essentially, this method is equivalent to adding a
bypass capacitor to the resistor RC1. From Fig. 4.5c, the transfer function from
vinv to i2 can be derived as
i2 ðsÞ
GLCL5c ðsÞ ¼
vinv ðsÞ
sC1 RC1 þ 1
¼
s4 L1 L2 C1 C2 RC1 þ s3 L1 L2 ðC1 þ C2 Þ þ s2 ðL1 þ L2 ÞC1 RC1 þ sðL1 þ L2 Þ
ð4:12Þ
(4) Splitting the Capacitor and Adding a Bypass Inductor

Similarly, based on Fig. 4.5c, an inductor Ld is further connected in parallel
with the damping resistor RC1, as shown in Fig. 4.5d. In this way, the power
loss in RC1 at the fundamental frequency can be reduced. Actually, this method
is equivalent to the method shown in Fig. 4.5b. From Fig. 4.5d, the transfer
i 2 ðsÞ s2 Ld C1 RC1 þ sLd þ RC1

GLCL5d ðsÞ ¼ ¼2 5 3 ð4:13Þ
vinv ðsÞ s L1 L2 Ld C1 C2 RC1 þ s4 L1 L2 Ld ðC1 þ C2 Þ
6 þ s3 ½L1 L2 ðC1 þ C2 Þ þ ðL1 þ L2 ÞLd C1 RC1 7
4 5
þ s2 ðL1 þ L2 ÞLd þ sðL1 þ L2 ÞRC1
According to (4.10)–(4.13), the frequency responses of the four improved

passive-damping solutions are depicted in Fig. 4.6. Compared with the basic
50 50
Magnitude (dB)
Magnitude (dB)
0 0
50 50
100 100
150 150
0 0
90 90
Phase (°)
Phase (°)
180 180
GLCL(s) GLCL(s)
GLCL-5(s) GLCL-5(s)
270 GLCL-5a(s) 270 GLCL-5c(s)
GLCL-5b(s) GLCL-5d(s)
360 360
10 102 103 104 105 10 102 103 104 105
(a) Adding bypass components (b) Splitting the capacitor
Fig. 4.6 Frequency responses of the four improved passive-damping solutions

passive-damping solution using a resistor in series with the capacitor, it can be seen
that:
(1) Adding a bypass inductor will not affect the magnitude-frequency character-
istics of the LCL filter at the high-frequency range. This is because that at the
high-frequency range, the reactance of bypass inductor is far larger than the
value of series resistor, the series resistor still plays a dominant role.
(2) Adding a bypass capacitor or splitting the capacitor will improve the
high-frequency harmonic attenuating ability of LCL filter. This is because that
at the high-frequency range, the bypass capacitor or split capacitor offers a
low-impedance branch which absorbs most of the high-frequency harmonic
currents.
From the above analysis, it can be known that among the four improved
passive-damping solutions, by adding a bypass inductor and capacitor or splitting
the capacitor and adding a bypass inductor, both a lower power loss and a high
harmonic attenuating ability can be achieved, but the circuit complexity and the
system volume and cost are also increased.
4.3 Active-Damping Solutions
As illustrated in Sect. 4.2, passive damping is able to suppress the LCL filter
resonance, but it results in power loss, and it might reduce the low-frequency gains
or the high-frequency harmonic attenuating ability of LCL filter. To overcome these
drawbacks, proper control algorithms can be adopted to compensate the frequency
response of LCL filter to achieve the desired damping performance. This method is
called active damping. Generally speaking, active-damping solutions can be clas-
sified into two kinds: one is the state-variable-feedback active damping; the other is
the notch-filter-based active damping.
4.3.1 State-Variable-Feedback Active Damping
The state-variable-feedback active damping is the method that uses the feedback of
proper state variable to mimic a virtual resistor in place of the physical one. As
reported in Sect. 4.2.1, the resistor in parallel with capacitor shows the best
damping performance, thus the active-damping solutions equivalent to a resistor in
parallel with capacitor are derived as follows.
According to Fig. 4.3f, the control block diagram of LCL-type grid-connected
inverter using a resistor in parallel with the capacitor is obtained, as shown in
Fig. 4.7. In which, vr(s) is the modulation signal and KPWM = Vin/Vtri is the transfer
function from vr(s) to the inverter bridge output voltage vinv(s), where, Vin and Vtri
are the input voltage and the amplitude of the triangular carrier, respectively.
4.3 Active-Damping Solutions 89
vg(s)
– iC(s)
vr(s)
KPWM
+ 1 + + 1 +
–
1 i2(s)
sL1 sC sL2
vinv(s) – – vC(s)
1
RC2
Fig. 4.7 Control block diagram of LCL-type grid-connected inverter using a resistor in parallel
with capacitor
Referring to Fig. 4.7, by moving the feedback node of the capacitor voltage
vC(s) to the input of KPWM, and adjusting its feedback function, an equivalent
control block diagram is obtained, as shown in Fig. 4.8a. From which, it can be
seen that derivative feedback of the capacitor voltage is equivalent to a resistor in
parallel with capacitor.
vg(s)
iC(s)
vr(s) + + 1 + 1 + 1 i2(s)
KPWM sL1 sC sL2
vinv(s) vC(s)
sL1
KPWMRC2
(a) Derivative feedback of the capacitor voltage
sL1 vg(s)
KPWMRC2
iC(s)
vr(s) + + 1 + 1 + 1 i2(s)
KPWM sL1 sC sL2
vinv(s) vC(s) v2(s)
s L1L2
2
KPWMRC2
(b) Second-derivative feedback of the grid current
vg(s)
iC(s)
vr(s) +
KPWM
+ 1 + 1 + 1 i2(s)
sL1 sC sL2
vinv(s) vC(s)
L1
KPWMCRC2
(c) Proportional feedback of the capacitor current
Fig. 4.8 Equivalent forms of the damping solution using resistor in parallel with capacitor
Considering that the capacitor voltage vC(s) is the summation of the grid voltage
vg(s) and the voltage on L2, v2(s), the feedback of vC(s) can be decomposed into the
feedbacks of vg(s) and v2(s). Then, by replacing the feedback variable v2(s) with the
grid current i2(s), and adjusting its feedback function, an equivalent control block
diagram is obtained, as shown in Fig. 4.8b. As seen, the derivative feedback of the
grid voltage plus the second-derivative feedback of the grid current is also equiv-
alent to a resistor in parallel with capacitor. It is worth noting that vg(s) is a
disturbance signal, and it makes no contribution to the damping of LCL filter
resonance. Therefore, from the viewpoint of damping the resonance, the derivative
feedback of the grid voltage can be omitted (see the dashed line in Fig. 4.8b), and
only the second-derivative feedback of the grid current is enough.
Based on Fig. 4.8a, if we replace the feedback variable vC(s) with the capacitor
current iC(s) and adjust its feedback function, an equivalent control block diagram
can be obtained as shown in Fig. 4.8c. As seen, the feedback function of the
capacitor current is a constant L1/(KPWMCRC2). Therefore, proportional feedback of
the capacitor current is equivalent to a resistor in parallel with capacitor as well.
The above analysis shows that either proportional feedback of the capacitor
current [8–11] or derivative feedback of the capacitor voltage [12, 13], or even
second-derivative feedback of the grid current [14, 15] can achieve the same
damping performance as a resistor in parallel with the capacitor. In practice,
derivative will lead to the amplification of high-frequency noise. Moreover, an ideal
derivator can hardly be implemented, and the discretization error introduced by a
digital derivator will degrade the performance of active damping. Comparatively,
proportional feedback of the capacitor current has been widely used for its simple
implementation and effectiveness. For brevity of illustration, hereinafter the
active-damping solution using proportional feedback of the capacitor current is
simply called the capacitor-current-feedback active damping.
Similarly, for the other passive-damping solutions depicted in Sect. 4.2, their
equivalent active-damping representations can also be derived through equivalent
transformation of the control block diagram, and they are not discussed here.
4.3.2 Notch-Filter-Based Active Damping
As depicted in Sect. 4.1, introducing a damping term makes the transfer function of
LCL filter, GLCL(s), become GLCL-d(s), which can be realized by either the
passive-damping solution using a resistor in parallel with the capacitor or the
capacitor-current-feedback active damping. The alternative method of introducing
the damping term is to multiply GLCL(s) by Gtrap(s) directly, and
Gtrap(s) = GLCL-d(s)/GLCL(s). According to (4.1) and (4.3), Gtrap(s) is derived as
4.3 Active-Damping Solutions 91
GLCLd ðsÞ s2 þ x2r

Gtrap ðsÞ ¼ ¼ 2 ð4:14Þ
GLCL ðsÞ s þ 2nxr s þ x2r
Obviously, Gtrap(s) is the transfer function of a notch filter. To realize the

multiplication of GLCL(s) and Gtrap(s) from the control perspective, Gtrap(s) can be
embedded into the control loop in cascade, as shown in Fig. 4.9. This method is
called the notch-filter-based active damping [16–18].
Figure 4.10a gives the Bode diagram of Gtrap(s). At the LCL filter resonance
frequency fr, an anti-resonance peak is provided by Gtrap(s), which cancels out the
resonance peak of LCL filter. While at the low- and high-frequency ranges, the
gains of Gtrap(s) are 0 dB, thus it will not affect the magnitude-frequency charac-
teristics of LCL filter at these frequency ranges. This means that the
notch-filter-based active damping can also achieve the desired damping perfor-
mance, as shown in Fig. 4.10b.
As seen in (4.14), the LCL-filter resonance frequency must be known exactly for
the purpose of implementing the notch-filter-based active damping. However, in
practice, due to the core saturation or aging of the filter components, the LCL filter
vg(s)
– iC(s)
vr(s) + 1 + 1 +
–
1 i2(s)
Gtrap(s) KPWM sL1 sC sL2
vinv(s) – vC(s)
Fig. 4.9 Notch-filter-based active damping
50 50
Magnitude (dB)
Magnitude (dB)
0 0
50 50
100 100
150 150
180 0
90 90
Phase (°)
Phase (°)
0 180
90 270 w/o damping

w/ notch-filter-
based active damping
180 360
10 102 103 fr 104 105 10 102 103 fr 104 105
(a) Bode diagram of the notch filter (b) LCL filter with notch-filter-based
active damping
Fig. 4.10 Frequency response of the notch-filter-based active damping

parameters will vary and derivate from the designed ones. As a consequence, the
resonance frequencies of the LCL filter and the notch filter will not match exactly,
and the performance of notch-filter-based active damping becomes poorer or even
ineffective. To address this issue, the LCL filter resonance frequency can be
detected online [19, 20], and the resonant frequency of the notch filter is adjusted to
be adaptive to the resonance frequency variation. But, this will raise the hardware
cost and control complexity.
Taking all these practical issues into account, it can be concluded that the
capacitor-current-feedback active damping is more valuable in practical application.
For this reason, the capacitor-current-feedback active damping is adopted in fol-
lowing chapters of this book.
4.4 Summary
In this chapter, the resonance hazard of LCL filter is analyzed, and six basic
passive-damping solutions are discussed in term of their effects on the character-
istics of LCL filter. The analysis reveals that adding a resistor in parallel with
capacitor shows the best damping performance, but it results in a high power loss;
while adding a resistor in series with capacitor is the most valuable
passive-damping solution due to its low power loss. On the basis of a resistor in
series with capacitor, four improved passive-damping solutions are introduced to
further reduce the power loss of the damping resistor. Meanwhile, the
active-damping solutions equivalent to a resistor in parallel with capacitor are
derived, which can be classified into two kinds: one is the state-variable-feedback
active damping, including proportional feedback of the capacitor current, derivative
feedback of the capacitor voltage, and second-derivative feedback of the grid
current; the other is the notch-filter-based active damping. Among the
active-damping solutions, the capacitor-current-feedback active damping is superior
for its simple implementation and effectiveness. This chapter provides the basis for
the study of the control techniques of LCL-type grid-connected inverter in the
following chapters.
References
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3839 (2014)
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13. Xiao, H., Qu, X., Xie, S., Xu, J.: Synthesis of active damping for grid-connected inverters
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Chapter 5
Controller Design for LCL-Type
Grid-Connected Inverter
with Capacitor-Current-Feedback
Active-Damping
Abstract For the LCL-type grid-connected inverter, the capacitor-current-feedback

active-damping is equivalent to a resistor in parallel with the filter capacitor to damp
the LCL filter resonance. This active-damping method has no power loss and has
been widely used. Based on the capacitor-current-feedback active-damping and the
proportional-integral (PI) regulator as the grid current regulator, this chapter pro-
poses a step-by-step controller design method for the LCL-type grid-connected
inverter. By carefully examining the steady-state error, phase margin, and gain
margin, a satisfactory region of the capacitor-current-feedback coefficient and PI
regulator parameters for meeting the system specifications is obtained. With this
satisfactory region, it is very convenient to choose the controller parameters and
optimize the system performance. Besides, the proposed design method is extended
to the situations where PI regulator with grid voltage feedforward scheme or
proportional-resonant (PR) regulator is adopted. Finally, design examples of
capacitor-current-feedback coefficient and current regulator parameters are pre-
sented for a single-phase LCL-type grid-connected inverter, and experiments are
performed to verify the proposed design method.
Keywords Grid-connected inverter LCL filter Active damping Controller

design PI regulator PR regulator
Chapter 4 has discussed the damping solutions to LCL filter resonance. Among the
six basic passive-damping solutions, adding a resistor in parallel with the filter
capacitor can effectively suppress the resonance peak without affecting the
magnitude-frequency characteristics at the low- and high-frequency ranges, but it
results in a high power loss. Capacitor-current-feedback active-damping is equiv-
alent to a resistor in parallel with the filter capacitor, and it has no power loss and
has been widely used. Based on the capacitor-current-feedback active-damping and
the proportional-integral (PI) regulator as the grid current regulator, this chapter
proposes a step-by-step controller design method for the LCL-type grid-connected
inverter. By carefully examining the steady-state error, phase margin, and gain
margin, a satisfactory region of the capacitor-current-feedback coefficient and PI

96 5 Controller Design for LCL-Type Grid …
regulator parameters for meeting the system specifications is obtained [1, 2]. With
this satisfactory region, it is very convenient to choose the controller parameters and
optimize the system performance. Besides, the proposed design method is extended
to the situations where PI regulator with grid voltage feedforward scheme or pro-
portional-resonant (PR) regulator is adopted. Finally, design examples of
capacitor-current-feedback coefficient and current regulator parameters are pre-
sented for a single-phase LCL-type grid-connected inverter, and experiments are
performed to verify the proposed design method.
5.1 Modeling LCL-Type Grid-Connected Inverter
Figure 5.1 shows the configuration of the single-phase LCL-type grid-connected

inverter, where switches Q1 to Q4 compose the single-phase inverter bridge, and the
inverter-side inductor L1, the filter capacitor C, and the grid-side inductor L2
compose the LCL filter. The primary objective of the grid-connected inverter is to
control the grid current i2, so that it can be synchronized with the grid voltage vg,
and its amplitude can be regulated as required. Generally, the phase angle of vg is
obtained through a phase-locked loop (PLL), and the current amplitude reference is
generated by the outer voltage loop [3]. Since the dynamics of the voltage loop is
much slower than that of the grid current loop, the grid current loop can be eval-
uated separately, and the current amplitude reference is directly given as I* here. Hv
and Hi2 are the sensor gains of vg and i2, respectively. The sensed grid current is
compared to the current reference i2 , and the current error signal is sent to current
regulator Gi(s). The capacitor current iC is fed back to damp the LCL filter reso-
nance actively, and Hi1 is the feedback coefficient. Subtracting the
capacitor-current-feedback signal vic from the current regulator output vr, the
modulation reference vM is yielded.
Fig. 5.1 Topology and

control scheme of LCL-type Q1 Q3 L1 L2
vC
grid-connected inverter + i1 i2
iC
Vin vinv C vg
–
Q2 Q4
Hi1 Hi2 Hv
Sinusoidal PWM vic PLL

vr cosθ
vM – + – + i2*
Gi(s) I*
Control system
5.1 Modeling LCL-Type Grid-Connected Inverter 97
Referring to Fig. 5.1, the mathematical model of LCL-type grid-connected

inverter can be obtained, as shown in Fig. 5.2, in which KPWM = Vin/Vtri is the
transfer function from vM to the inverter bridge output voltage vinv, with Vin and Vtri
as the input voltage and the amplitude of the triangular carrier, respectively. ZL1(s),
ZC(s), and ZL2(s) are the impedances of L1, C, and L2, expressed as
1
ZL1 ðsÞ ¼ sL1 ; ZC ðsÞ ¼ ; ZL2 ðsÞ ¼ sL2 ð5:1Þ
sC
Based on Fig. 5.2, a series of equivalent transformations of the control block

diagrams is shown in Fig. 5.3, where the dashed lines represent the original status,
and the solid lines represent the destination status. First, replacing the feedback of
capacitor voltage vC(s) with capacitor current iC(s), and relocating its feedback node
to the output of Gi(s), an equivalent block diagram is obtained, as shown in
Fig. 5.3a. Second, by combining the two feedback functions of iC(s), and moving
the feedback node of i2(s) from the output of 1/ZL1(s) to the output of Gi(s), the
equivalent block diagram is obtained, as shown in Fig. 5.3b. Third, moving the
feedback node of i2(s) from the output of Gi(s) to the output of ZC(s), and sim-
plifying the forward path from Gi(s) to ZC(s), results in the equivalent block dia-
gram shown in Fig. 5.3c, where
KPWM Gi ðsÞZC ðsÞ

Gx1 ðsÞ ¼ ð5:2aÞ
ZL1 ðsÞ þ ZC ðsÞ þ Hi1 KPWM
ZL1 ðsÞZC ðsÞ

Hx1 ðsÞ ¼ ð5:2bÞ
Furthermore, Fig. 5.3c can be simplified to Fig. 5.3d, where

Gx2 ðsÞ ¼ ð5:3Þ
ZL1 ðsÞZL2 ðsÞ þ ðZL1 ðsÞ þ ZL2 ðsÞÞZC ðsÞ þ Hi1 KPWM ZL2 ðsÞ
vg(s)
iC(s)
i2*(s) + – 1 + – 1 i2(s)
Gi(s) + KPWM + + ZC(s)
– – ZL1(s) – ZL2(s)
vC(s)
Hi1
Hi2
Fig. 5.2 Mathematical model of LCL-type grid-connected inverter with capacitor-current-

feedback active-damping
(a) ZC(s) vg(s)

KPWM × ×
i2*(s) + – – 1 + – 1 i2(s)
Gi(s) + KPWM + + ZC(s)
– – ZL1(s) – ZL2(s)
Hi1
Hi2
(b) vg(s)
i2*(s) +
Gi(s) + KPWM +
1 + ZC(s) + – 1 i2(s)
– – – ZL1(s) – ZL2(s)
×
ZC(s)
Hi1+
KPWM
ZL1(s)
KPWM
Hi2
(c) vg(s) (d)

vg(s)
i2*(s) + – 1 i2(s)
Gx1(s) +
– – ZL2(s) i2*(s) + – i2(s)
Gx1(s) + Gx2(s)
Hx1(s) –
Hi2 Hi2
Fig. 5.3 Equivalent transformations of the mathematical model of LCL-type grid-connected

inverter
From Fig. 5.3d, and considering (5.1), the loop gain can be obtained as
Hi2 KPWM Gi ðsÞ

TA ðsÞ ¼ Gx1 ðsÞGx2 ðsÞHi2 ¼ ð5:4Þ
s3 L 1 L2 C þ s L2 CHi1 KPWM þ sðL1 þ L2 Þ
2
and the grid current i2(s) is expressed as
1 TA ðsÞ Gx2 ðsÞ

i 2 ðsÞ ¼ i ðsÞ vg ðsÞ , i21 ðsÞ þ i22 ðsÞ ð5:5Þ
Hi2 1 þ TA ðsÞ 2 1 þ T A ðsÞ
5.1 Modeling LCL-Type Grid-Connected Inverter 99
where
1 TA ðsÞ
i21 ðsÞ ¼ i ðsÞ ð5:6aÞ
Hi2 1 þ TA ðsÞ 2
Gx2 ðsÞ
i22 ðsÞ ¼ vg ðsÞ ð5:6bÞ
1 þ TA ð s Þ
From (5.5), it is clear to see that i2(s) consists of two components i21(s) and
i22(s), where i21(s) is related to the reference tracking, and i22(s) is related to the
disturbance caused by the grid voltage.
5.2 Frequency Responses of Capacitor-Current-Feedback

Active-Damping and PI Regulator
According to (5.4), the Bode diagram of uncompensated loop gain (Gi(s) = 1) is

depicted, as shown in Fig. 5.4, where fo is the fundamental frequency, fc is the
crossover frequency of the loop gain, and fr is the LCL filter resonance frequency.
As shown in the figure, introducing the feedback of capacitor current can effectively
damp the resonance peak, and it only affects the magnitude plot of the loop gain
nearby fr. However, this damping solution has significant impact on the phase plot,
and the phase is decreased from −90° at the frequencies lower than fr. A larger Hi1
leads to a better resonance damping but a larger negative phase shift.
Since the phase plot of the loop gain crosses over −180° at fr, the crossover
frequency fc is needed to be lower than fr to preserve an adequate phase margin.
Fig. 5.4 Bode diagram of the

uncompensated loop gain
When calculating the magnitude of the loop gain at fc and the frequencies lower
than fc, the capacitor branch can be regarded as open circuit since the reactance of
the filter capacitor is far larger than that of the grid-side inductor; thus, the LCL
filter can be approximated as a pure inductor with the inductance of L1 + L2. From
(5.4), the approximated |TA(s)| can be obtained as

Hi2 KPWM Gi ðsÞ
jTA ðsÞj ð5:7Þ
sðL1 þ L2 Þ
PI or PR regulator is usually adopted as the current regulator, and their Bode

diagrams are shown in Fig. 5.5. Here, the PI regulator is discussed as an instance,
and it is expressed as
Ki
s
where Kp is the proportional gain, and Ki is the integral gain. The corner frequency
of PI regulator is fL = Ki/(2pKp). As shown in Fig. 5.5, at the frequencies around fL,
the slope of the magnitude plot changes from −20 dB/dec to 0 dB/dec, and the
phase escalates from −90° up to 0°. To alleviate the decrease of phase margin
resulted from PI regulator, fL is suggested to be sufficiently lower than fc. Thus, the
magnitude of Gi(s) can be approximated to Kp at fc and the frequencies higher than
fc. Note that the loop gain has unit magnitude at fc, i.e., |TA(j2pfc)| = 1, and sub-
stituting |Gi(j2pfc)| Kp into (5.7) yields
2pfc ðL1 þ L2 Þ
Kp ð5:9Þ
Hi2 KPWM
Fig. 5.5 Bode diagrams of PI

and PR regulators
5.3 Constraints for Controller Parameters 101
5.3 Constraints for Controller Parameters
5.3.1 Requirement of Steady-State Error
The steady-state error of the grid current is an important performance index in the
grid-connected inverter. As depicted in (5.5), the grid current i2 consists of i21 and
i22. Generally, the magnitude of the loop gain is sufficiently large at fo and then
1 + TA(j2pfo) TA(j2pfo). Thus, according to (5.6a), i21 i2 /Hi2, which means i21
is in phase with i2 . As discussed above, the capacitor branch can be regarded as
open circuit at fc and the frequencies lower than fc. Therefore, at the fundamental
frequency fo, (5.3) and (5.4) can be approximated as
1
Gx2 ðj2pfo Þ ð5:10aÞ
j2pfo ðL1 þ L2 Þ
Hi2 KPWM Gi ðj2pfo Þ

TA ðj2pfo Þ ð5:10bÞ
j2pfo ðL1 þ L2 Þ
Substituting (5.10a, 5.10b) into (5.6b) yields

vg
i22 ð5:11Þ
Hi2 KPWM Gi ðj2pfo Þ
For PI regulator, there is Gi(j2pfo) Ki/(j2pfo), so i22 −j2pfovg/(Hi2KPWMKi),

which means that i22 is 90º lagging to vg.
Figure 5.6a shows the phasor diagram of i2, i21, i22, and vg, where h is the phase
angle that i2 leads to vg and it is set according to the power factor (PF) requirement
of the system. As no active power is absorbed from the grid, there is h 2 [−90°,
90°]. As shown in the figure, the steady-state error of i2 includes the amplitude error
EA and the phase error d, and EA is expressed as
i21
i2*
θ i2 I22_δPI I22_EAPI
δ vg
I22
i22
0
−90 −45 0 45 90
θ (°)
(a) Phasor diagram of i2, i21, i22, and vg (b) Curves of I22_EAPI and I22_δPI as θ varies
Fig. 5.6 Steady-state error of the grid current with PI regulator


Hi2 I2 I2 Hi2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

EA ¼
¼ I I21 þ I22 2I21 I22 sin h 1 ð5:12Þ
2 2
I 2 2
where I2 , I2, I21, and I22 are the rms values of i2 , i2, i21, and i22, respectively.
Equation (5.12) can be rewritten as
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Hi2
EA ¼ 2 þ I 2 2I I
I21 21 22 sin h 1 ð5:13Þ
I2 22
Substituting I21 I2 /Hi2 into (5.13), the four roots of I22 can be solved as
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
I2
I22 rt1 ¼ sin h þ sin2 h 2EA þ EA2
Hi2
I
I22 rt2 ¼ 2 sin h sin2 h 2EA þ EA2
Hi2
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð5:14Þ
I
I22 rt3 ¼ 2 sin h þ sin2 h þ 2EA þ EA2
Hi2
I2
I22 rt4 ¼ sin h sin2 h þ 2EA þ EA2
Hi2
Apparently, I22_rt4 < 0, and it is an invalid root. The upper boundary of I22 con-
strained by EA is denoted by I22_EAPI, and it is determined by the smallest one of
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
I22_rt1 * I22_rt3. If h 2 [−90°, −h1] where h1 ¼ arcsin 2EA EA2 , both I22_rt1 and
I22_rt2 are negative and invalid. If h 2 (−h1, h1), sin2 h 2EA þ EA2 < 0, and I22_rt1
and I22_rt2 are inexistent. Thus, for h 2 [−90°, h1), I22_EAPI = I22_rt3. While for
h 2 [h1, 90°], I22_rt1 * I22_rt3 are all valid and I22_rt2 is the smallest, so
I22_EAPI = I22_rt2. In summary, I22_EAPI is expressed as
8 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
>
> I2
h 2 ½90 ; h1 Þ
< Hi2 sin h þ sin h þ 2EA þ EA2 ;
2
I22 EAPI ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð5:15Þ

>
> I2
: Hi2 sin h sin2 h 2EA þ EA2 ; h 2 ½h1 ; 90
Applying sine law to Fig. 5.6a yields
I22
sin d ¼ jsinð90 þ h dÞj ð5:16Þ
I21
From Fig. 5.6a and (5.16), it is obvious that d = 0° when h = ±90°, and when
h 6¼ ±90°, the upper boundary of I22 constrained by d, which is denoted by I22_dPI,
is expressed as

I2 sin d
I22 ð5:17Þ
Hi2 cosðh dÞ
dPI
According to (5.15) and (5.17), the curves of I22_EAPI and I22_dPI as the functions
of h are depicted in Fig. 5.6b, from which it can be seen that I22_EAPI is minimum
when h ±90° and I22_dPI is minimum when h 0°.
Considering (5.10b) and (5.11), I22 can be approximated as
Vg Vg
I22 ð5:18Þ
Hi2 KPWM jGi ðj2pfo Þj 2pfo ðL1 þ L2 ÞjTA ðj2pfo Þj
According to (5.18), the magnitude of the loop gain at the fundamental fre-
quency fo, which is denoted by Tfo, can be expressed as
Vg
Tfo ¼ 20 lgjTA ðj2pfo Þj 20 lg ð5:19Þ
2pfo ðL1 þ L2 ÞI22
where the unit of Tfo is dB. (5.19) indicates that I22 is related to Tfo; thus, the
requirement of steady-state error can be further converted into the requirement of
Tfo. In order to satisfy the requirements of EA and d at the same time, I22 in (5.19)
should be set as the smaller one between I22_EAPI and I22_dPI.
5.3.2 Controller Parameters Constrained by Steady-State

Error and Stability Margin
Substituting (5.8) into (5.7), the expression of Tfo with PI regulator is given as

H K
i2 PWM Kp þ j2pfi o
K
Tfo ¼ 20 lgjTA ðj2pfo Þj ¼ 20 lg

ð5:20Þ
j2pfo ðL1 þ L2 Þ
Substituting (5.9) into (5.20) and manipulating, the Ki constrained by Tfo is

obtained as
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
4p2 fo ðL1 þ L2 Þ Tfo 2
Ki Tfo ¼ 10 20 fo fc2 ð5:21Þ
Hi2 KPWM
According to (5.4), the phase margin PM can be expressed as

Hi2 KPWM Gi ðsÞ

PM ¼ 180 þ \ 3 ð5:22Þ
s L1 L2 C þ s L2 CHi1 KPWM þ sðL1 þ L2 Þs¼j2pfc
2
Substituting (5.8) into (5.22) and manipulating yields

2pL1 fr2 fc2 Ki
PM ¼ arctan arctan ð5:23Þ
Hi1 KPWM fc 2pfc Kp
Applying tangent on both sides of (5.23) and manipulating, the Ki constrained by

PM is obtained as

2pL1 fr2 fc2 Hi1 KPWM fc tan PM
Ki PM ¼ 2pfc Kp ð5:24Þ
2pL1 fr2 fc2 tan PM þ Hi1 KPWM fc
If the selected Ki meets the constraints of Tfo and PM at the same time, then
Ki_Tfo = Ki_PM. Substituting (5.9) and (5.21) into (5.24), the Hi1 constrained by Tfo
and PM is obtained as
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi !
Tfo
2
2pL1 fr2 fc 2
fc2 fo 10 fo
20 fc2 tan PM
Hi1 ¼ rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi! ð5:25Þ
Tfo PM
Tfo
2
KPWM fc fc2 tan PM þ fo 10 fo
20 fc2
Since the phase plot of the loop gain crosses over −180° at fr, the gain margin
GM can be expressed as
GM ¼ 20 lgjTA ðj2pfr Þj ð5:26Þ
where the unit of GM is dB. It is worth noting that the magnitude of the loop gain
TA(s) given in (5.7) is not accurate at fr. Therefore, substituting the loop gain
without approximation, i.e., (5.4), and (5.9) into (5.26), the Hi1 constrained by GM
is obtained as
GM 2pfc L1
Hi1 GM ¼ 10 20 ð5:27Þ
KPWM
5.3.3 Pulse-Width Modulation (PWM) Constraint
Figure 5.7 gives the schematic diagram of a modulation reference compared to the
triangular carrier in the PWM inverter, and fsw is the switching frequency. In the
LCL-type grid-connected inverter, the switching ripple on the inverter side is almost
bypassed by the filter capacitor, letting the fundamental sinusoidal current to be
injected into the grid. Hence, the current regulator output vr is nearly constant
during a switching period. As reported in Sect. 5.1, the modulation reference vM is
Fig. 5.7 Schematic diagram

of a modulation reference Vtri
compared to the triangular vr vM
carrier
0 t
vic Carrier
−Vtri
1/fsw
the difference between vr and the capacitor current feedback signal vic. Therefore,
the rate of change of vM is dependent on that of vic, which has a maximum value of
Hi1Vin/L1 (i.e., multiply the maximum rate of change of the inverter-side inductor
current by the capacitor-current-feedback coefficient). From Fig. 5.7, it can be seen
that the rate of change of the triangular carrier is 4Vtrifsw. In order to avoid the
multiple switching transitions, the maximum rate of change of the modulation
reference should be smaller than that of the triangular carrier [4–6], i.e.,
Hi1 Vin
\4Vtri fsw ð5:28Þ
L1
According to (5.28), the Hi1 constrained by PWM can be obtained as
4fsw L1 Vtri 4fsw L1

Hi1 PWM ¼ ¼ ð5:29Þ
Vin KPWM
5.4 Design Procedure for Capacitor-Current-Feedback

Coefficient and PI Regulator Parameters
Based on the above analysis, a design procedure for capacitor-current-feedback

coefficient and PI regulator parameters is given as follows.
Step 1: Specify the requirements of Tfo, PM, and GM. Specifically, Tfo is deter-
mined by the requirement of the steady-state error, and PM and GM are determined
by the requirements of the dynamic response and robustness of the system. As
shown in Fig. 5.6a, the steady-state error is more notable under light-load condi-
tion, and thus, Tfo needs to be specified by the most severe situation presented in the
standards, e.g., PF must be greater than 0.85 under 10% of the rated load condition
[7] or PF must be greater than 0.98 under half-load condition [8]. Besides, PM is set
in the range (30º, 60º) for good dynamic response, and GM > 3 dB is preserved to
ensure the system robustness.
Step 2: Based on the specific Tfo, PM, and GM, draw the curves of Hi1_Tfo_PM,
Hi1_GM, and Hi1_PWM as the functions of fc according to (5.25), (5.27), and (5.29),
respectively, and then, get the satisfactory region of fc and Hi1.
Figure 5.8 shows the satisfactory region of fc and Hi1. The area upon the dashed
line meets the requirement of GM, and the area under the solid line meets the
requirements of Tfo and PM. Thus, the shaded area between these two lines includes
all the possible fc and Hi1 satisfying the aforementioned specifications. From
Fig. 5.8, it can be seen that:
(1) With the increase of fc, the lower boundary of Hi1 constrained by GM increases.
This is because that as fc approaching fr, the resonance peak should be damped
lower to achieve the same GM, and thus, a larger Hi1 is needed.
(2) With the increase of fc, the upper boundary of Hi1 ascends first and then
descends. This is because that when fc is relatively low and is close to the
corner frequency of PI regulator, the negative phase shift caused by PI regulator
is significant at fc, and thus, a smaller Hi1 has to be chosen to preserve the
desired phase margin. With the increase of fc, the impact of the negative phase
shift caused by PI regulator becomes less, so the upper boundary of Hi1 rises
first. But when fc keeps increasing and approaches fr, the negative phase shift
caused by the capacitor-current-feedback active-damping becomes larger and
plays the dominant role, so the upper boundary of Hi1 falls then.
It is worth noting that if the requirements of Tfo, PM, and GM specified in Step 1
are too strict, the satisfactory region might be very small or even not exist. If so,
return to Step 1 and modify the specifications and then renew Step 2.
Step 3: Select a proper fc from the satisfactory region of fc and Hi1, and then,
calculate Kp from (5.9). A higher fc is expected to improve the dynamic perfor-
mance and low-frequency gains. Nevertheless, in order to suppress the
high-frequency switching noise, fc is usually limited to 1/10 of the switching fre-
quency [9].
Step 4: Select a proper Hi1 according to the requirements of PM and GM. The lower
boundary of Hi1 is Hi1_GM, and the upper boundary of Hi1 is the smaller one
between Hi1_PWM and Hi1_Tfo_PM. For a specific fc, increasing Hi1 will decrease PM
Fig. 5.8 Satisfactory region

of fc and Hi1 constrained by Hi1_PWM
Tfo, PM, GM, and PWM
PM and Tfo
constraint
Hi1
GM constraint
0
fc
5.4 Design Procedure for Capacitor-Current-Feedback … 107
but not affect Tfo. Therefore, while retaining enough GM, a smaller Hi1 is preferred
to improve the dynamic performance.
Step 5: After fc and Hi1 have been determined, select a proper Ki according to the
requirements of Tfo and PM. The upper and lower boundaries of Ki are Ki_PM and
Ki_Tfo, respectively. A larger Ki leads to a higher Tfo but a smaller PM. Therefore, Ki
needs to be chosen by making a trade-off between Tfo and PM.
Step 6: Check the compensated loop gain to ensure all the specifications are well
satisfied.
Moreover, it should be noted that the satisfactory region is an effective tool not
only to choose but also to optimize the controller parameters. While meeting the
basic specifications depicted above, the controller parameters can be further opti-
mized as follows.
(1) For a specific fc, a larger Ki can be chosen for a higher Tfo;
(2) A larger Hi1 can be chosen for a larger GM; and
(3) A smaller Ki and Hi1 can be chosen for a larger PM.
5.5 Extension of the Proposed Design Method
In practical applications, in order to reduce the steady-state error of the grid current,
PI regulator with the grid voltage feedforward scheme (the grid voltage feedforward
scheme will be discussed in Chaps. 6 and 7 of this book) or PR regulator is usually
adopted. The controller design method proposed in Sect. 5.4 is extended to these
cases in this section.
5.5.1 Controller Design Based on PI Regulator with Grid

Voltage Feedforward Scheme
PI regulator is widely used for its simplicity and effectiveness, but it cannot achieve
zero steady-state error of the grid current for a single-phase grid-connected inverter.
To overcome this drawback, a grid voltage feedforward scheme is proposed in [10].
With this scheme, the disturbance component i22 caused by the grid voltage vg can
be eliminated from the grid current. Thus, as shown in Fig. 5.6, only the amplitude
error EA is left to be considered. From (5.6a), EA is expressed as

I2 Hi2 I21 TA ðj2pfo Þ j1 þ TA ðj2pfo Þj jTA ðj2pfo Þj

EA ¼ ¼ 1
¼
I 1 þ T ðj2pf Þ j1 þ T ðj2pf Þj
2 A o A o
ð5:30Þ
Since |TA(j2pfo)| 1, then |1 + TA(j2pfo)| 1 + |TA(j2pfo)|, so (5.30) can be

approximated as
1 1 Tfo
EA ¼ 10 20 ð5:31Þ
j1 þ TA ðj2pfo Þj jTA ðj2pfo Þj
Therefore, the requirement of Tfo in Step 1 can be specified as Tfo 20lg(1/EA).

Since the grid voltage feedforward scheme has no effect on the loop gain, the
controller design method proposed in Sect. 5.4 can be extended to PI regulator plus
the grid voltage feedforward scheme without any other modification, and it is not
repeated here.
5.5.2 Controller Design Based on PR Regulator
Compared with PI regulator, PR regulator can provide far larger gain at the fun-
damental frequency and thus can greatly reduce the steady-state error [11, 12]. In
order to preserve certain adaptability to the grid frequency, a practical alternative of
PR regulator is adopted as
2Kr xi s
s2 þ 2xi s þ x2o
where Kp is the proportional gain, Kr is the resonant gain, xo = 2pfo is the fun-
damental angular frequency, and xi is the bandwidth of the resonant part con-
cerning −3 dB cutoff frequency, which means the gain of the resonant part is

pffiffiffi
Kr 2 at xo ± xi. For small-scale photovoltaic power stations, the grid-connected
inverter is required to work normally when the grid frequency fluctuates between
49.5 Hz and 50.2 Hz [8], and thus, the maximum frequency fluctuation is
Df = 0.5 Hz. In order to attain enough gain in the entire working frequency range,
xi = 2pDf = p rad/s is set.
The Bode diagram of PR regulator is depicted with the dashed line, as shown in
Fig. 5.5. As seen, PR regulator can provide a large gain at fo, but it also introduces
negative phase shift at the frequencies higher than fo, especially at the frequencies
close to fo. To alleviate the decrease of phase margin caused by this negative phase
shift, the crossover frequency fc is suggested to be far higher than fo. Thus, similar
to PI regulator, PR regulator can also be approximated to Kp in magnitude at fc and
the frequencies higher than fc. Hence, (5.9), (5.27), and (5.29) still work, that is to
say, Kp can be expressed as the function of fc given by (5.9), and Hi1 is constrained
by the requirements of GM and PWM given by (5.27) and (5.29), respectively.
Different from PI regulator, PR regulator given in (5.32) is expressed as
Gi(j2pfo) = Kp + Kr at the fundamental frequency. Substituting it into (5.11) yields
i22 −vg/[Hi2KPWM(Kp + Kr)], which means i22 and vg are opposite in phase.
5.5 Extension of the Proposed Design Method 109
I22_EAPR I22_δPR
I22
i2 i21
i2*
δ θ vg 0
−90 −45 0 45 90
i22 0 θ (°)
(a) Phasor diagram of i2, i21, i22, and vg (b) Curves of I22_EAPR and I22_δPR as θ varies
Fig. 5.9 Steady-state error of the grid current with PR regulator
Figure 5.9a shows the phasor diagram of i2, i21, i22, and vg, from which it can be
seen that d = 0° when h = 0°. The upper boundaries of I22 constrained by EA and d
are denoted by I22_EAPR and I22_dPR, respectively, and they can be derived from
Fig. 5.9a, i.e.,
8 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
< I2
cos h þ cos2 h þ 2EA þ EA2 ; h 2 ½90 ; h2 Þ [ ðh2 ; 90
I22 EAPR ¼
Hi2

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
: I2 cos h cos2 h 2EA þ EA2 ; h 2 ½h2 ; h2
Hi2
ð5:33aÞ

I2 sin d
I22 ð5:33bÞ
Hi2 sinðh þ dÞ
dPR
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
where h2 ¼ arcsin 2EA EA2 :
According to (5.33a, 5.33b), the curves of I22_EAPR and I22_dPR as the functions
of h are depicted, as shown in Fig. 5.9b. As seen, I22_EAPR is minimum when
h 0° and I22_dPR is minimum when h ±90°. Substituting the smaller one
between I22_EAPR and I22_dPR into (5.19), the desired Tfo for meeting the require-
ment of steady-state error is obtained. Further, considering that |TA[j2p
(fo ± Df)]| = 0.707Tfo, 3 dB needs to be added to (5.19) to ensure the requirement
of steady-state error is met when the grid frequency fluctuates between fo ± Df.
Substituting (5.32) into (5.7), the expression of Tfo with PR regulator is given as

Hi2 KPWM Kp þ Kr
Tfo ¼ 20 lgjTA ðj2pfo Þj ¼ 20 lg ð5:34Þ
2pfo ðL1 þ L2 Þ
Substituting (5.9) into (5.34) and manipulating, the Kr constrained by Tfo is

obtained as
Tfo 2pðL þ L Þ
1 2
Kr Tfo ¼ 10 20 fo fc ð5:35Þ
Hi2 KPWM
At the crossover frequency fc, PR regulator can be approximated as

Gi(s) Kp + 2Krxi/s. Substituting it into (5.4), the phase margin PM is derived as

2pL1 fr2 fc2 Kr xi
PM ¼ arctan arctan ð5:36Þ
Hi1 KPWM fc pfc Kp
Applying tangent on both sides of (5.36) and manipulating, the Kr constrained

by PM is obtained as

pfc Kp 2pL1 fr2 fc2 Hi1 KPWM fc tan PM
Kr PM ¼ ð5:37Þ
xi Hi1 KPWM fc þ 2pL1 fr2 fc2 tan PM
If the selected Kr meets the constraints of Tfo and PM at the same time, then
Kr_Tfo = Kr_PM. Substituting (5.9) and (5.35) into (5.37), the Hi1 constrained by Tfo
and PM is obtained as
Tfo
2
2pL1 fr2 fc2 pfc 10 20 fo fc xi tan PM
Hi10 Tfo PM ¼ Tfo ð5:38Þ
KPWM fc 10 20 fo fc xi þ pfc2 tan PM
According to Hi0 1 Tfo PM , Hi1_GM, and Hi1_PWM, the satisfactory region of fc and
Hi1 for meeting the requirements of Tfo, PM, and GM can be obtained. Thus, the
controller design method proposed in Sect. 5.4 can also be extended to PR
regulator.
5.6 Design Examples
Based on the system parameters of a single-phase LCL-type grid-connected inverter

given in Table 5.1, design examples of the controller parameters are presented in
this section for PI and PR regulators, respectively.

Grid voltage (rms) Vg 220 V Filter capacitor C 10 lF
Amplitude of the Vtri 3.05 V Grid current feedback Hi2 0.15
triangular carrier coefficient
5.6.1 Design Results with PI Regulator
According to the design procedure given in Sect. 5.4, the requirements of Tfo, PM,
and GM are specified at first, which are as follows: (1) Tfo > 52 dB to ensure that
PF is greater than 0.98 under half-load condition [8], which corresponds to
PF > 0.994 and EA
0.5% under full-load condition; (2) PM > 45° to preserve a
good dynamic performance; and (3) GM > 3 dB to ensure the system robustness.
Based on these specifications, the satisfactory region of fc and Hi1 is obtained
according to (5.25), (5.27), and (5.29), shown as the shaded area in Fig. 5.10, from
which a group of controller parameters is properly selected as follows.
In order to perform a fast dynamic response, the crossover frequency fc is
suggested to be as high as possible. Since the grid-connected inverter employs the
unipolar sinusoidal PWM, its equivalent switching frequency is 20 kHz, and thus, fc
is set at 2 kHz here. Substituting it into (5.9) yields Kp = 0.45. After fc is selected,
the possible interval of Hi1 can be determined. As shown in Fig. 5.10, the lower
boundary of Hi1 is Hi1_GM, and the upper boundary of Hi1 is Hi1_Tfo_PM.
Substituting fc = 2 kHz into (5.25) and (5.27), respectively, the possible range of
Hi1 is calculated as [0.09, 0.165]. Here, Hi1 = 0.1 is chosen to get a larger phase
margin. At last, substituting fc = 2 kHz into (5.21) yields Ki_Tfo = 1657, and sub-
stituting fc = 2 kHz, Kp = 0.45, and Hi1 = 0.1 into (5.24) yields Ki_PM = 2626, and
thus, the possible interval of Ki is [1657, 2626]. By trading off between the
steady-state error and phase margin, Ki = 2200 is chosen.
With the controller parameters designed above, the Bode diagram of compen-
sated loop gain is depicted in Fig. 5.11, where fc = 2.05 kHz, Tfo = 54.4 dB,
PM = 48.1°, and GM = 4.29 dB can be identified. It is obvious that all the spec-
ifications are satisfied as expected.
Figure 5.12 shows the Bode diagrams of compensated loop gain considering the
variations in the LCL filter parameters. The real grid contains the inductive grid
impedance, which contributes to the grid-side inductor, and can be regarded as a
part of L2. It is found that even if L1 and C vary in ±20% and L2 varies in −30% to
+100% (considering the grid impedance), the crossover frequency is still higher
Fig. 5.10 Satisfactory region 0.25

of fc and Hi1 constrained by Hi1_PWM
Tfo, PM, GM, and PWM with 0.20
PI regulator PM=45°,
0.15 Tfo=52dB
constraint
Hi1
0.10
0.05
GM=3dB
constraint
0
0.5 1.0 1.5 2.0 2.5 3.0
fc (kHz)
Fig. 5.11 Bode diagram of

compensated loop gain with
PI regulator
than 1.77 kHz, the phase margin is larger than 36°, and the gain margin is larger
than 4 dB. All of these results verify a strongly robust system. As shown in
Fig. 5.12a, the variation in L1 has little effect on the loop gain. The variation in
C mainly affects the phase margin, as shown in Fig. 5.12b. This is because that with
the increase of C, the resonance frequency fr decreases, and thus, the impact of the
capacitor-current-feedback active-damping on the phase margin becomes more
significant. The variation in L2 mainly affects the crossover frequency and phase
margin, as shown in Fig. 5.12c. This is because that with the increase of L2, both fc
and fr decrease, and thus, the impact of the negative phase shift caused by PI
regulator and the capacitor-current-feedback active-damping on the phase margin
becomes more significant. Therefore, to deal with the wide-range variations of filter
parameters, a relatively smaller Ki and Hi1 can be selected to improve the phase
margin.
5.6.2 Design Results with PR Regulator
When PR regulator is adopted, the requirements of Tfo, PM, and GM are given as
follows: (1) Tfo > 75 dB to ensure that the amplitude error of the grid current is less
than 1% when the grid frequency fluctuates in ±0.5 Hz; (2) PM > 45° to preserve a
good dynamic performance; and (3) GM > 3 dB to ensure the system robustness.
Based on these specifications, the satisfactory region of fc and Hi1 is obtained
according to (5.27), (5.29), and (5.38), shown as the shaded area in Fig. 5.13.
Fig. 5.12 Bode diagrams of compensated loop gain considering the variations in the LCL filter
parameters
Fig. 5.12 (continued)
Fig. 5.13 Satisfactory region 0.35

of fc and Hi1 constrained by
0.30 PM=45°,
Tfo, PM, GM, and PWM with Hi1_PWM Tfo=75dB
PR regulator 0.25 constraint
0.20
Hi1
0.15
0.10
0.05 GM=3dB
constraint
0
0.5 1.0 1.5 2.0 2.5 3.0
fc (kHz)
Similar to the design procedure in Sect. 5.6.1, fc = 2 kHz is still set here, which
leads to Kp = 0.45 as well. As shown in Fig. 5.13, for fc = 2 kHz, the lower
boundary of Hi1 is Hi1_GM, and the upper boundary of Hi1 is Hi1_PWM. Substituting
fc = 2 kHz into (5.27) and (5.29), respectively, the possible interval of Hi1 is cal-
culated as [0.09, 0.2]. Here, Hi1 = 0.1 is chosen. At last, substituting fc = 2 kHz
into (5.35) yields Kr_Tfo = 74, and substituting fc = 2 kHz, Kp = 0.45, and
Hi1 = 0.1 into (5.37) yields Kr_PM = 418, and thus, the possible interval of Kr is
[74, 418], and here, Kr = 350 is chosen.

compensated loop gain with
PR regulator
With the controller parameters designed above, the Bode diagram of compen-
sated loop gain is depicted in Fig. 5.14, where fc = 2.05 kHz, Tfo = 88.4 dB,
PM = 48.1°, and GM = 4.29 dB can be identified. It is obvious that all the spec-
ifications are satisfied as expected.
In order to verify the theoretical analysis and the effectiveness of the proposed
controller design method, a 6-kW prototype is built in the laboratory according to
the parameters listed in Table 5.1. Figure 5.15 shows the photograph of the
prototype.
Figure 5.16 shows the experimental results with PI regulator designed in
Sect. 5.6.1. The experimental waveform at full load is given in Fig. 5.16a, where
the measured power factor is 0.995, phase error is 3.7°, and fundamental rms value
of i2 is 27.13 A (since the reference is 27.27 A, the amplitude error is 0.5%). All of
these results are in agreement with the design target in Sect. 5.6.1. Figure 5.16b
shows the experimental result when the grid current reference steps between half
load and full load. According to (5.4), the theoretical percentage overshoot and
settling time of i2 are calculated as 45% and 1.5 ms using MATLAB. In practice,
the measured percentage overshoot i.e., r/Istep in Fig. 5.16(b) and settling time are
about 34% and 1.5 ms, respectively. Due to the effect of the parasitic parameters,
the measured percentage overshoot is a little smaller than the theoretical value.
Fig. 5.15 Photograph of the prototype
Fig. 5.16 Experimental

results with PI regulator vg:[100 V/div]
i2:[20 A/div]
(Kp = 0.45, Ki = 2200,
Hi1 = 0.1)
Time: [5 ms/div] PF = 0.995

(a) Steady-state experimental results under full load condition
vg:[100 V/div] i2:[20 A/div]
Istep
σ
Time: [20 ms/div]

(b) Experimental results when the grid current reference
steps between half load and full load
Figure 5.17 shows the experimental results with PR regulator designed in

Sect. 5.6.2. The measured power factor is 0.999, fundamental rms value of i2 is
27.1 A (the amplitude error is 0.6%), percentage overshoot is about 35%, and
settling time is about 1.5 ms.
The experimental results in Figs. 5.16 and 5.17 show that with the proposed
controller design method, the LCL filter resonance is damped effectively, and sat-
isfactory steady-state and transient performances are obtained at the same time.
Taking PI regulator for instance, Fig. 5.18 shows the plots of the measured
fundamental rms value, power factor, and percentage overshoot of i2 when Hi1
varies. As Hi1 increases from 0.1 to 0.2, the measured percentage overshoot
increases from 34% to 50%, while the fundamental rms value and power factor of i2
remain 27.13 A and 0.995, respectively. Figure 5.19 shows the experimental results
when Hi1 is reduced intentionally (Kp = 0.45, Ki = 2200, Hi1 = 0.016), where
significant oscillation arises in the grid current. From Figs. 5.18 and 5.19, it can be
seen that increasing Hi1 has no improvement in the steady-state error, but it reduces
the phase margin and thus increases the percentage overshoot, while a too small Hi1
will result in current oscillation or even system instability. The experimental results
confirm the analysis of Hi1 in Sect. 5.3.

vg:[100 V/div]
results with PR regulator i2:[20 A/div]
(Kp = 0.45, Kr = 350,
Hi1 = 0.1)
Time: [5 ms/div] PF=0.999

(a) Steady-state experimental results under full load condition
vg:[100 V/div] i2:[20 A/div]
Istep
σ
Time: [20 ms/div]

(b) Experimental results when the grid current reference
steps between half and full load
Fig. 5.18 Fundamental rms 27.4 1.000 50
Fundamental rms value (A)

value, power factor, and 27.3 0.999 48
Percentage overshoot (%)

percentage overshoot as Hi1 27.2 0.998 46
varies 27.1 0.997 44
Power factor
27.0 0.996 42
26.9 0.995 40
26.8 0.994 38
26.7 0.993 36
26.6 0.992 rms value 34
PF
26.5 0.991 32
PO
26.4 0.990 30
0.1 0.12 0.14 0.16 0.18 0.2
Hi1

vg:[100 V/div]
results with a small Hi1
(Kp = 0.45, Ki = 2200,
Hi1 = 0.016)
i2:[20 A/div]
Time: [2 ms/div]
Fig. 5.20 Fundamental rms 27.6 1.00 45

Fundamental rms value (A)
value, power factor, and

Percentage overshoot (%)
27.3 0.99 40
percentage overshoot as Ki
varies 27.0 0.98 35
Power factor
26.7 0.97 30
26.4 0.96 25
26.1 0.95 20
rms value
25.8 0.94 PF 15
PO
25.5 0.93 10
600 1000 1400 1800 2200 2600
Ki
Figure 5.20 shows the plots of the measured fundamental rms value, power
factor, and percentage overshoot of i2 when Ki varies. As Ki increases from 600 to
2600, the measured fundamental rms value of i2 increases from 25.69 A to 27.13 A,
power factor increases from 0.935 to 0.996, and the percentage overshoot increases
from 11% to 37%. Figure 5.21 shows the experimental results when Ki is increased
intentionally (Kp = 0.45, Ki = 7400, Hi1 = 0.1), where significant oscillation arises

vg:[100 V/div]
result with a large Ki
(Kp = 0.45, Ki = 7400,
Hi1 = 0.1)
ig:[20 A/div]
Time: [2 ms/div]
in the grid current. From Figs. 5.20 and 5.21, it can be seen that increasing Ki has
significant improvement in the steady-state error, but it reduces the phase margin
and thus increases the percentage overshoot as well, and a too large Ki will result in
current oscillation or even system instability. The experimental results confirm the
analysis of Ki in Sect. 5.3.
5.8 Summary
In this chapter, the mathematical model of LCL-type grid-connected inverter is

built, and the frequency responses of capacitor-current-feedback active-damping
and current regulators are investigated. The analysis reveals that
(1) capacitor-current-feedback active-damping can effectively suppress the LCL
filter resonance, but it decreases the system phase below the resonance frequency,
and (2) PI and PR regulators determine the crossover frequency and the
low-frequency gains of the system, but they also introduce negative phase shift.
Due to the interaction between the capacitor-current-feedback active-damping and
the current regulator, the negative phase shifts caused by each other are added
together, which would easily lead to system instability. Based on the steady-state
error, phase margin, and gain margin, this chapter proposes a step-by-step controller
design method to determine and optimize the controller parameters. The proposed
method is raised based on PI regulator and extended to PI regulator with grid
voltage feedforward scheme and PR regulator, respectively. Finally, design
examples are presented for a single-phase LCL-type grid-connected inverter, and
experiments are performed on a 6-kW prototype. Experimental results show that
with the proposed controller design method, the LCL filter resonance is damped
effectively, and satisfactory steady-state and transient performances are obtained at
the same time.
References
1. Bao, C.: Design of current regulator and capacitor-current-feedback active damping for LCL-
type grid-connected inverter (in Chinese). M.S. thesis. Huazhong University of Science and
Technology, Wuhan, China (2013)
2. Bao, C., Ruan, X., Wang, X., Li, W., Pan, D., Weng, K.: Step-by-step controller design for
LCL-type grid-connected inverter with capacitor-current-feedback active-damping. IEEE
1398–1409 (2006)
4. Zargari, N.R., Joós, G.: Performance investigation of a current-controlled voltage- regulated
PWM rectifier in rotating and stationary frames. IEEE Trans. Ind. Electron. 42(4), 396–401
(1995)
5. Kazmierkowski, M.P., Malesani, L.: Current control techniques for three-phase
voltage-source PWM converters: a survey. IEEE Trans. Ind. Electron. 45(5), 691–703 (1998)
6. Martinz, F.O., Miranda, R.D., Komatsu, W., Matakas, L.: Gain limits for current loop
controllers of single and three-phase PWM converters. In: Proceeding of the IEEE
International Power Electronics Conference, 201–208 (2010)
929. (2000)
8. Technical Rule for Photovoltaic Power Station Connected to Power Grid, Q/GDW 617
(2011) (in Chinese)
9. Erickson, R.W., Maksimović, D.: Fundamentals of Power Electronics, 2nd edn. Kluwer,
Boston, MA (2001)
11. Zmood, D.N., Holmes, D.G.: Stationary frame current regulation of PWM inverters with zero
12. Holmes, D.G., Lipo, T.A., McGrath, B.P., Kong, W.Y.: Optimized design of stationary frame
three phase AC current regulators. IEEE Trans. Power Electron. 24(11), 2417–2426 (2009)
Chapter 6
Full-Feedforward of Grid Voltage
for Single-Phase LCL-Type
Abstract The grid-connected inverter plays an important role in injecting

high-quality power into the power grid. The injected grid current is affected by the
grid voltage at the point of common coupling (PCC). This chapter studies the
feedforward scheme of the grid voltage for single-phase LCL-type grid-connected
inverter. First, the mathematical model for the LCL-type grid-connected inverter
with capacitor-current-feedback active-damping is presented, and then it is sim-
plified through a series of equivalent transformations. After that, a full-feedforward
of the grid voltage is proposed to eliminate the effect of the grid voltage on the
steady-state error and harmonics in the injected grid current. The feedforward
function consists of three parts, namely proportional, derivative, and
second-derivative components. A comprehensive investigation shows that if the
grid voltage contains only the third harmonic, the proportional feedforward com-
ponent is adequate to suppress the harmonic distortion in the grid current caused by
the grid voltage; when the grid voltage contains harmonic distortion up to the
thirteenth harmonic, the proportional and derivative components are required; and
when the grid voltage contains harmonic distortion higher than the thirteenth har-
monic, the second-derivative component must be incorporated, i.e., the
full-feedforward scheme is necessary.

Keywords Grid-connected inverter LCL filter Damping resonance Total

harmonics distortion (THD) Feedforward Single-phase
6.1 Introduction
As the interface between the distributed power generation system (DPGS) and
power grid, grid-connected inverter plays an important role in injecting high-quality
power into the power grid. As illustrated in Chap. 5, the injected grid current is
affected by the grid voltage at the point of common coupling (PCC). Generally, lots
of nonlinear equipments such as arc welder, saturable transformer, and electric rail
vehicles are connected to the PCC and produce harmonic current. The produced
122 6 Full-FeedForward of Grid Voltage for Single-Phase …
harmonic current flows through the grid impedance and introduces background
harmonics to the grid voltage at PCC. The background harmonics of the grid
voltage will cause the injected grid current of the grid-connected inverter distorted.
Besides, the fundamental component of the grid voltage will also lead to the
steady-state error of the grid current [1, 2]. In order to ensure the grid current to
meet the standards, the effect of the grid voltage on the grid current should be
mitigated, which can be achieved by two ways. One is to use multiple
proportional-resonant (PR) regulator [2, 3] or repetitive regulator [4, 5] as the grid
current controller, which achieve infinite loop gains at the fundamental and har-
monic frequencies. The other way is to use the feedforward schemes of the grid
voltage [6–8]. Through feedforward of the grid voltage, both the steady-state error
and the distortion of the grid current can be mitigated even if a simple regulator
such as proportional-integral (PI) regulator is used. Furthermore, a fast dynamic
response of the inverter can be achieved.
This chapter studies the feedforward scheme of the grid voltage for single-phase
LCL-type grid-connected inverter. First, the mathematical model for the LCL-type
grid-connected inverter with capacitor-current-feedback active-damping is pre-
sented, and then it is simplified through a series of equivalent transformations. After
that, a full-feedforward of the grid voltage is proposed to eliminate the effect of the
grid voltage on the steady-state error and harmonics in the injected grid current. The
feedforward function consists of three parts, namely proportional, derivative and
second-derivative components. A comprehensive investigation shows that if the
grid voltage contains only the third harmonic, the proportional feedforward com-
ponent is adequate to suppress the harmonic distortion in the grid current caused by
the grid voltage; when the grid voltage contains harmonic distortion up to the
thirteenth harmonic, the proportional and derivative components are required; and
when the grid voltage contains harmonic distortion higher than the thirteenth har-
monic, the second-derivative component must be incorporated, i.e., the full-feed-
forward scheme is necessary. Since the full-feedforward function is related to the
transfer function of the PWM modulator, the inverter-side inductor and the filter
capacitor, the impact of the variations of these parameters on the mitigation of the
harmonics in the grid current is investigated. Finally, in order to verify the effec-
tiveness of the proposed full-feedforward scheme of the grid voltage, a 6-kW
single-phase LCL-type grid-connected inverter is built and tested. The experimental
results show the proposed full-feedforward scheme can not only effectively reduce
the steady-state error of the grid current, but also sufficiently suppress the grid
current distortion arising from the background harmonics in the grid voltage.
6.2 Effects of the Grid Voltage on the Grid Current
Figure 6.1 shows the configuration of a single-phase LCL-type grid-connected

inverter, where the LCL filter is composed of L1, C, and L2. The primary objective
of the grid-connected inverter is to control the grid current i2 to synchronize with
6.2 Effects of the Grid Voltage on the Grid Current 123
Fig. 6.1 Topology and L1 vC L2

control diagram of LCL-type + i1 iC i2
grid-connected inverter
Vin vinv C vg
–
Hi1 Hi2 Hv
Sinusoidal PWM PLL

cos θ
vM – + – + i2*
Gi(s) I*
Control System
the grid voltage vg, and its amplitude can be regulated as required. i2 is the grid
current reference, which includes the amplitude I* and the phase angle h. h is
usually obtained by a phase-locked loop (PLL), and I* is generated by an outer
voltage loop. Since the bandwidth of the voltage loop is much slower than that of
the grid current loop, it is reasonable to ignore the voltage loop and set I* directly
while designing the grid current regulator Gi(s). In this figure, Hi1, Hi2, and Hv
represent the feedback coefficients of the capacitor current, grid current, and grid
voltage, respectively. Here, the capacitor-current-feedback active-damping is used
to damp the resonance of the LCL filter.
According to Fig. 6.1, the mathematical model of the LCL-type grid-connected
inverter can be derived as shown in Fig. 6.2a, where KPWM = Vin/Vtri is the transfer
function from the modulation signal vM to the inverter bridge output voltage vinv,
with Vin and Vtri as the input voltage and the amplitude of the triangular carrier,
respectively; ZL1(s), ZC(s), and ZL2(s) represent the reactance of L1, C, and L2,
respectively, expressed as
1
sC
In Chap. 5, through a series of equivalent transformations of the control block

diagram, the block diagram shown in Fig. 6.2a can be equivalently simplified to
that shown in Fig. 5.3d. For convenience of illustration, it is given here again, as
shown in Fig. 6.2b, where
KPWM Gi ðsÞZC ðsÞ


Fig. 6.2 Model of single-phase LCL-type grid-connected inverter with capacitor-current-feedback

active-damping
From Fig. 6.2b, the loop gain TA(s) and the grid current i2(s) can be obtained as
TA ðsÞ ¼ Gx1 ðsÞGx2 ðsÞHi2

Hi2 KPWM Gi ðsÞZC ðsÞ ð6:4Þ
¼
TA ðsÞ 1 Gx2 ðsÞ

i2 ðsÞ ¼ i2 ðsÞ vg ðsÞ , i21 ðsÞ þ i22 ðsÞ ð6:5Þ
1 þ TA ðsÞ Hi2 1 þ TA ðsÞ
where
1 TA ðsÞ
i21 ðsÞ ¼ i ðsÞ ð6:6aÞ
Hi2 1 þ TA ðsÞ 2
Gx2 ðsÞ
i22 ðsÞ ¼ vg ðsÞ ð6:6bÞ
1 þ TA ð s Þ
As seen from (6.5), the grid current i2 is composed of two parts. One is the static
tracking component i21, and the other is the disturbance component i22 resulting
from the grid voltage.
It can be observed from (6.6) that if the loop gain TA is large enough in mag-
nitude, both the static tracking error and the variation component i22 will be sub-
stantially reduced. However, TA cannot be designed to be too large, otherwise the
6.2 Effects of the Grid Voltage on the Grid Current 125
Fig. 6.3 Experimental waveforms of single-phase LCL-type grid-connected inverter

Input voltage Vin 360 V Filter capacitor C 10 lF
Grid voltage Vg 220 V Grid-side inductor L2 150 lH
(RMS)
Output power Po 6 kW Carrier amplitude Vtri 3V
Fundamental fo 50 Hz Capacitor-current-feedback Hi1 0.075
frequency coefficient
Switching fsw 10 kHz Grid current feedback Hi2 0.15
frequency coefficient
Inverter-side L1 600 lH Grid voltage feedback Hv 0.017
inductor coefficient
system may become unstable. Basically, when the magnitude of TA at the funda-
mental frequency is larger than 10, the static tracking error can be effectively
reduced, but the disturbance component i22 may be still large.
Figure 6.3 shows the experimental results under half-load and full-load condi-
tions tested from the prototype. The parameters of the prototype are listed in
Table 6.1. Here, PI regulator is used as the grid current loop. As seen from Fig. 6.3,
due to the disturbance component i22 resulting from the grid voltage vg, the grid
current i2 lags to vg. Besides, the distortion in i2 is evident, which is resulted by i22.
Since i22 is independent from the grid current reference i2 , it will keep the same
when i2 decreases. Meanwhile, the static tracking component i21 will decrease when
i2 decreases. Therefore, the distortion of i2 becomes more serious at light load than
at heavy load.
6.3 Full-Feedforward Scheme for Single-Phase LCL-Type

6.3.1 Derivation of Full-Feedforward Function

of Grid Voltage
In (6.5), the function −Gx2/(1 + TA(s)) can be regarded as the admittance between i2
and vg. If an additional path from the grid voltage vg to the grid current i2 with the
transfer function of Gx2 is introduced, as shown in Fig. 6.4, the effect of vg on the
grid current will be eliminated.
By moving the feedforward node from the output of Gx2(s) to the output of
Gx1(s) and modifying the feedforward function as appropriate, the equivalent block
diagram can be obtained, as shown in Fig. 6.5a. Figure 6.5a can be further
equivalently transformed into Fig. 6.5b. As seen, the feedforward of vg with the
function of 1/Gx1(s) will eliminate the effect of vg on the grid current i2.
According to Fig. 6.5b, the block diagram shown in Fig. 6.2a can be
re-configured, as shown in Fig. 6.6a. Note that the numerator of Gx1(s) shown in
(6.2) contains the current regulator function Gi(s). Thus, Fig. 6.6a can be equiva-
lently transformed into Fig. 6.6b and the feedforward component contributes to the
modulation signal.
Substituting (6.2) into Fig. 6.6b, the feedforward function can be expressed as

Gi ðsÞ 1 ZL1 ðsÞ Hi1 KPWM
Gff ðsÞ , ¼ 1þ þ : ð6:7Þ
Gx1 ðsÞ KPWM ZC ðsÞ ZC ðsÞ
vg(s)
Gx2(s)
i2* (s) +
Gx1(s)
+ – Gx2(s)
+ + i2(s)
–
Hi2
Fig. 6.4 Block diagram of full-feedforward scheme
(a) (b)
vg(s)
vg(s)
1
Gx1(s)
i2* (s) +
Gx1(s)
+ ++ – Gx2(s)
i2(s) i2* (s) + +
Gx1(s)
+ – Gx2(s)
i2(s)
– –
Hi2 Hi2(s)
Fig. 6.5 Derivation of full-feedforward scheme of grid voltage

6.3 Full-Feedforward Scheme for Single-Phase LCL-Type … 127
(a) vg(s)
1
Gx1(s)
i2* (s) + +
Gi(s)
+ KPWM
+ – 1 + ZC(s)
+ – 1 i2(s)
– – ZL1(s) – ZL2(s)
Hi1
Hi2
(b) vg(s)
Gi(s)
Gx1(s)
i2* (s) +
Gi(s)
+ + KPWM
+ – 1 + ZC(s)
+ – 1 i2(s)
– – ZL1(s) – ZL2(s)
Hi1
Hi2
vg(s)
(c) L1C·s2
KPWM
CHi1·s
1
KPWM
+
+
i2* (s) +
Gi(s)
+ +
KPWM
+ – 1 + ZC(s)
+ – 1 i2(s)
– – ZL1(s) – ZL2(s)
Hi1
Hi2
Fig. 6.6 Block diagrams of feedforward scheme of grid voltage and equivalent representations
Substituting the expressions of ZL1(s) and ZC(s) given in (6.1) into (6.7) yields
1 L1 C
Gff ðsÞ ¼ þ CHi1 s þ s2 : ð6:8Þ
KPWM KPWM
Putting the three feedforward components indicated in (6.8) into the feedforward
function in Fig. 6.6b, the equivalent transformation is obtained, as shown in
Fig. 6.6c. It can be seen that the feedforward function of the grid voltage includes
three components, i.e., the proportional, derivative, and second-derivative compo-
nents. If only the proportional component is used, as attempted previously in [6],
the result will not be very satisfactory. To differ from the proportional feedforward
of the grid voltage, the derived feedforward function as shown in (6.8) is defined as
the full-feedforward scheme in this chapter.
6.3.2 Discussion of the Three Feedforward Components
As seen in (6.8), the full-feedforward function of the grid voltage is composed of

the proportional, derivative, and second-derivative components. When the input
voltage Vin and the amplitude of the triangle carrier Vtri are determined, the pro-
portional component is a constant, whereas the magnitudes of the derivative and
second-derivative components increase as the harmonic frequency of the grid
voltage increases. Therefore, when the grid voltage contains different harmonic
distortion, the weight of the three components of the full-feedforward function will
be different.
Substituting s = j2pf into (6.8) yields
1 L1 C
Gff ðj2pf Þ ¼ þ j2pf CHi1 ð2pf Þ2
KPWM KPWM ð6:9Þ
, Gff p ðj2pf Þ þ Gff d ð j2pf Þ þ G ff dd ðj2pf Þ
where Gff_p(j2pf), Gff_d(j2pf), and Gff_dd(j2pf) are the proportional, derivative, and
second-derivative components, respectively, expressed as
1
Gff p ðj2pf Þ ¼
KPWM
Gff d ðj2pf Þ ¼ j2pf CHi1 ð6:10Þ
L1 C
Gff dd ðj2pf Þ ¼ ð2pf Þ2
KPWM
To investigate the weight of the three feedforward components, comparison is

made among the full-feedforward scheme and two simplified feedforward schemes,
i.e., the proportional feedforward scheme and the proportional and derivative
feedforward scheme. The difference between the full-feedforward scheme and the
proportional feedforward scheme is defined as E1(j2pf); the difference between the
full-feedforward scheme and the proportional and derivative feedforward scheme is
defined as E2(j2pf). So, E1(j2pf) and E2(j2pf) are expressed as
1
E1 ðj2pf Þ ¼ Gff d ðj2pf Þ þ Gff dd ðj2pf Þ ¼ j2pf CHi1 ð2pf Þ2 L1 C ð6:11Þ
KPWM
1
E2 ðj2pf Þ ¼ Gff dd ðj2pf Þ ¼ ð2pf Þ2 L1 C ð6:12Þ
KPWM
Setting the full-feedforward function Gff(j2pf) as the reference, the per-unit

values of E1(j2pf) and E2(j2pf) can be expressed as
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
h i ffi
2
ð2pf Þ2 L1 C þ ð2pf CHi1 KPWM Þ2
jE1 ðj2pf Þj
E1ðp:u:Þ ð f Þ , ¼ rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
h i2 ð6:13Þ
Gff ðj2pf Þ
1 ð2pf Þ2 L1 C þ ð2pf CHi1 KPWM Þ2
jE2 ðj2pf Þj 2pf CHi1 KPWM

E2ðp:u:Þ ð f Þ , ¼ rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
h i2 ð6:14Þ
Gff ðj2pf Þ
Substituting the corresponding parameters in Table 6.1 into (6.13) and (6.14),
the curves of E1(j2pf) and E2(j2pf) can be depicted, as shown in Fig. 6.7. As seen,
E1(j2pf) and E2(j2pf) increase as the harmonic frequency increases. It means that
the harmonic suppression ability of the two simplified feedforward schemes is
reduced. If E1(p.u.)(f) < 0.1, the harmonic suppression ability of the full-feedforward
scheme can be approximated to that of the proportional feedforward scheme.
Setting E1(p.u.)(f) = 0.1 yields fP1 181 Hz, which means the proportional feed-
forward scheme is adequate if vg contains only the third harmonic (here, the fun-
damental frequency is 50 Hz). Likewise, if E2(p.u.)(f) < 0.1, the harmonic
suppression ability of the full-feedforward scheme can be approximated to that of
the proportional and derivative feedforward scheme. Setting E2(p.u.)(f) = 0.1 yields
Fig. 6.7 Curves of E1(p.u.) 1.4

and E2(p.u.)
1.2 No Feedforward
1.0
Proportional P3 P4
0.8 Feedforward
Proportional and
0.6 (E1(p.u.))
Derivative
0.4 Feedforward (E2(p.u.))
0.1
0.2 P1 P2 Full-Feedforward
0.0
−0.1
0 fP1 0.5 fP2 1.0 1.5 2.0 2.5 3.0
f (kHz)
fP2 641 Hz. It means that the second-derivative feedforward function can be
omitted if vg contains harmonic distortion up to the thirteenth harmonic. If vg
contains harmonic distortion higher than the thirteenth harmonic, the full-feedfor-
ward scheme is necessary to ensure a satisfying harmonic suppression.
As seen in Fig. 6.7, when the harmonic distortion is higher than the thirtieth
harmonic (i.e., 1.5 kHz), E1(p.u.)(f) > 1 occurs. Compared with no feedforward
scheme, the proportional feedforward scheme will amplify the grid current har-
monics higher than 1.5 kHz. Likewise, when the harmonic distortion is higher than
the fiftieth harmonic (i.e., 2.5 kHz), E2(p.u.)(f) > 1 happens. Compared with no
feedforward scheme, the proportional and derivative feedforward scheme will also
amplify the grid current harmonics higher than 2.5 kHz.
6.3.3 Discussion of Full-Feedforward Scheme with Main

Circuit Parameters Variations
As discussed in Sect. 6.2, the effect of the grid voltage on the grid current can
theoretically be eliminated if the proportional coefficient, derivative, and second-
derivative components are accurate. However, as seen in (6.8), the three feedfor-
ward coefficients are related to KPWM, the capacitor-current-feedback coefficient
Hi1, the filter capacitor C, and the inverter-side filter inductor L1, where KPWM is
determined by the input voltage Vin and the amplitude of the triangle carrier Vtri.
Therefore, if the input voltage Vin fluctuates, or the values of inductor L1 and filter
capacitor C vary, the harmonic suppression ability of the proposed full-feedforward
scheme will be affected. Considering that the capacitor current is sensed by a
high-accuracy current hall, the variation of Hi1 is very little and can be ignored.
Therefore, the following analysis will focus on the feasibility of the full-
feedforward scheme with the variations of Vin, L1, and C.
Supposing the actual input voltage, inverter-side inductor and the filter capacitor
are V′in, L′1, and C′, respectively, the required full-feedforward function which can
completely eliminate the effect of grid voltage is
1 L01 C 0
G0ff ðj2pf Þ ¼ 0 þ j2pf C 0 Hi1 ð2pf Þ2 0 ð6:15Þ
KPWM KPWM
Setting the full-feedforward function Gff(j2pf) with the designed parameters as

the reference, the per-unit values of the amplitude difference between G′ff(j2pf) and
Gff(j2pf) can be expressed as

Gff ðj2pf Þ G0ff ðj2pf Þ
E3ðp:u:Þ ð f Þ ,
Gff ðj2pf Þ
rhffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
0
i2
1 KPWM =KPWM ð2pf Þ2 L1 C L01 C 0 KPWM =KPWM 0 þ ½2pfHi1 KPWM ðC C 0 Þ2
¼ rhffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
i 2
ð6:16Þ
As seen from Table 6.1, the rated input voltage is Vin = 360 V, and the designed
inverter-side inductor and filter capacitor are L1 = 600 µH and C = 10 µF,
respectively. Supposing that the fluctuation of Vin is between 360 V and 400 V, the
variation of L1 is between 500 µH and 700 µH, and the variation of C is between
8 µF and 12 µF. After comparing all kinds of the parameter variations, it can be
observed that the worst deterioration of harmonic suppression ability of the full-
feedforward scheme occurs in three cases: (1) L′1 = 500 µH with the rated Vin and
designed C; (2) C′ = 8 µF with the rated Vin and designed L1; and (3) V′in = 400 V
with the designed L1 and C. By substituting the corresponding parameters of the
three cases into (6.16), the curves of E3(p.u.) can be depicted, as shown in Fig. 6.8.
As seen, when the background harmonics in the grid voltage are below 1.5 kHz, the
full-feedforward scheme of the three cases can suppress the grid currents harmonics
down to 20% of that with no feedforward scheme. Even if the worst case while
C′ = 8 µF happens, the full-feedforward scheme can still suppress the harmonics
down to 35% of that with no feedforward scheme. Thus, it can be concluded that
the full-feedforward scheme is less affected when L1, C, and Vin have a relatively
large variations.
Fig. 6.8 Curves of E3(p.u.) 1.1

with main circuit parameter 1.0
variation No Feedforward
0.8
0.6
E3(p.u.)
C'=8µ F
0.4
L'1=500µ H
0.2 Vin
' =400V
Full-Feedforward
0.0
−0.1
0 0.5 1.0 1.5 2.0 2.5 3.0
f (kHz)
6.4 Experimental Results
A 6-kW prototype of single-phase LCL-type grid-connected inverter was con-

structed for verification of the full-feedforward scheme and for comparing the
effectiveness of the three constituent feedforward functions. The parameters of the
prototype are listed in Table 6.1. Experimental results of four cases are compared.
Case I is no feedforward of vg. Case II is proportional feedforward of vg, i.e., only
1/KPWM is used as the feedforward function. Case III is proportional and derivative
feedforward of vg. Case IV is full-feedforward of vg, i.e., the proportional,
derivative, and second-derivative feedforward of vg are all used. To clearly check
the harmonic suppression ability of the four cases, a programmable AC source
(Chroma 6590) is used to simulate the grid voltage.
Figure 6.9 shows the experimental results for Case I and Case II under full-load
condition. Here, the grid voltage vg is sinusoidal. It can be seen that the waveforms
of i2 are sinusoidal in both Cases I and II. However, a phase difference of about 3.7°
exists between i2 and vg in Case I, which is caused by the fundamental component
of vg according to the analysis in Sect. 6.1.
Figure 6.10 shows the experimental results for Case I and Case II at full-load
condition. Here, the third harmonic has been injected into vg, and the magnitude and
phase of the injected harmonic is 10% and 0°, respectively, with respect to the
fundamental component. It can be seen that the waveforms of i2 are distorted in
Case I, and a phase difference of about 3.7° exists between i2 and vg. For Case II, as
shown in Fig. 6.10b, i2 is perfectly sinusoidal, and the phase lag has been elimi-
nated. The THDs of the waveforms of i2 shown in Fig. 6.10a, b are 3.21% and
1.2%, respectively. The results show that when the distortion contains only the third
harmonic, the proportional feedforward scheme (Case II) is effective in suppressing
the distortion.
Figure 6.11 shows the experimental results for Cases II and III under full-load
condition. Here, the injected harmonics into vg include the third, fifth, seventh,
ninth, eleventh, and thirteenth harmonics, and the magnitudes of the injected
vg: [100V/div] iLf2: [20A/div] vg: [100V/div] iLf2: [20A/div]
Δ=3.7o
Time: [5ms/div] Time: [5ms/div]
(a) Case I (b) Case II
Fig. 6.9 Experimental waveforms with idea grid voltage

6.4 Experimental Results 133
vg: [100V/div] vg: [100V/div]

i2: [20A/div] i2: [20A/div]
Fig. 6.10 Experimental waveforms when the grid voltage contains only the third harmonic
harmonics with respect to the fundamental component of vg are 10%, 5%, 3%, 3%,
2% and 2%, respectively, and the corresponding phase angles are 0°, 90°, 0°, 0°, 0°
and 0°. As seen, for Cases II and III, the phase lag between i2 and vg is eliminated.
The measured THDs of the waveforms of i2 shown in Fig. 6.11a, b are 2.61% and
1.42%, respectively. The results show that when the harmonic distortion in the grid
voltage is up to the thirteenth harmonic, the proportional and derivative feedforward
scheme (Case III) is effective in suppressing the distortion, and the proportional
feedforward scheme (Case II) is inadequate.
Figure 6.12 shows the experimental results for four cases under full-load con-
dition. Here, the thirty-third harmonic, with magnitude and phase of 1% and 0° with
respect to the fundamental, has been injected into vg. As seen from Fig. 6.12a, when
the feedforward of vg is not used, the distortion of i2 is evident. Compared with
Fig. 6.12a, the distortion of i2 shown in Fig. 6.12b is deteriorated with proportional
feedforward of vg, which coincides with the analysis in Sect. 6.2. As seen from
Fig. 6.12c, when the proportional and derivative feedforward of vg is incorporated,

i2: [20A/div] i2: [20A/div]
(a) Case II (b) Case III
Fig. 6.11 Experimental waveforms when the grid voltage contains harmonic distortion up to the
thirteenth harmonic
the distortion of i2 is greatly reduced. As seen from Fig. 6.12d, when the
full-feedforward of vg is adopted, the distortion of i2 is the smallest. The results
show that when the grid voltage contains higher harmonics, the full-feedforward
scheme is necessary for eliminating the distortion in the grid current.
Furthermore, a test to verify the effectiveness of the proposed scheme under
possible voltage dip conditions is conducted. Figure 6.13 shows the experimental
results for the four cases when a 40 V voltage dip occurs at the trough and crest of
the voltage waveform of vg. The THDs of i2 for the four cases are 4.61%, 5.42%,
3.26%, and 2.24%, respectively. The results show that the full-feedforward scheme
can effectively suppress the current distortion even vg experiences a voltage dip.
The transient response of the grid-connected inverter under the proposed full-
feedforward scheme has been studied, and the results are shown in Fig. 6.14a
corresponding to step change of i2 . Note that the grid voltage is taken from the
active power grid. Here, i2 is stepped up from half load to full load, and vice versa.
The load changes are intentionally set to occur at the peak of i2, which is the worst
case. Results show that i2 is still kept in phase with vg, with small oscillatory
transient observed immediately after the step change of i2 . Also, Fig. 6.14b shows
the transient response corresponding to step change of vg with the full-feedforward

i2: [20A/div] i2: [20A/div]

i2: [20A/div] i2: [20A/div]
(c) Case III (d) Case IV
Fig. 6.12 Experimental waveforms when the grid voltage contains the thirty-third harmonic
6.4 Experimental Results 135

i2: [20A/div] i2: [20A/div]

i2: [20A/div] i2: [20A/div]
(c) Case III (d) Case IV
Fig. 6.13 Experimental waveforms for the four control strategies under voltage dip conditions
vg: [100V/div]
vg: [200V/div]
i2: [20A/div] i2: [50A/div]

(a) step change in i2* (b) step change in vg
Fig. 6.14 Measured transient response under step changes in i2 and vg
scheme. Here, vg is stepped down from 220 V to 180 V, and vice versa. The vg
changes are again purposely set to occur at the peak of vg, which is the worst case.
Results show that the amplitude of i2 is kept unchanged, with small oscillatory
transient immediately following the step change of vg.
Table 6.2 Measured THDs Vin (V) L1 (µH) C (µF) THD of i2 (%)
of grid current i2 with main
circuit parameters variation 360–400 600 10 1.3–1.48
360 500–700 10 1.45–1.5
360 600 8–12 1.3–1.7
To verify the adaptability of the proposed full-feedforward scheme to the vari-

ation of Vin, L1, and C, mismatches are intentionally introduced to the three
parameters, and the THDs of the grid current i2 are tested, as shown in Table 6.2.
As seen, the tested THDs changes very little, which indicates a good adaptability of
the proposed full-feedforward scheme. The results verify the analysis in Sect. 6.2.
6.5 Summary
This chapter studies the effect of the grid voltage on the grid current for the
single-phase LCL-type grid-connected inverter. It shows that the fundamental
component of the grid voltage affects the steady-state error, and the harmonic
components cause the grid current distorted. The traditional proportional feedfor-
ward of the grid voltage can suppress the current distortion but the result is not
satisfactory especially when the grid voltage contains high harmonic distortion.
This chapter proposes a full-feedforward of grid voltage scheme to suppress the
grid current distortion arising from the harmonics in the grid voltage. It is composed
by the proportional, derivative, and second-derivative components. Four cases,
namely no feedforward, the proportional feedforward of the grid voltage, the pro-
portional and derivative feedforward of the grid voltage, and the full-feedforward of
the grid voltage, are compared. The results show that if the grid voltage contains
only the third harmonic, the proportional feedforward of the grid voltage is ade-
quate for achieving good suppression of the current distortion. If the grid voltage
contains harmonic distortion up to the thirteenth harmonic, the proportional and
derivative feedforward of the grid voltage is adequate. If the grid voltage contains
higher harmonic distortion, the full-feedforward of the grid voltage is necessary.
Furthermore, the adaptability of the proposed full-feedforward scheme to the
variation of the input voltage, inverter-side inductor and filter capacitor is investi-
gated. A 6-kW single-phase LCL-type grid-connected inverter is fabricated and
tested to verify the effectiveness of the proposed full-feedforward scheme. The
experimental results show that the proposed feedforward scheme can not only
significantly reduce the steady-state error of the grid current, but also effectively
suppress the grid current distortion arising from the harmonics in the grid voltage.
Even if mismatch occurs from the input voltage, inverter-side inductor or filter
capacitor, the proposed full-feedforward scheme can still be effective.
References 137
References
1. Prodanović, M., Green, T.: High-quality power generation through distributed control of a
power park microgrid. IEEE Trans. Ind. Electron. 53(5), 1471–1482 (2006)
2. Zmood, D.N., Holmes, D.G.: Stationary frame current regulation of PWM inverters with zero
grid-connected inverters for a large set of grid impedance values. IEEE Trans. Power Electron.
21(1), 888–895 (2006)
4. Bojoi, R.I., Limongi, L.R., Roiu, D., Tenconi, A.: Enhanced power quality control strategy for
single-phase inverters in distributed generation systems. IEEE Trans. Power Electron. 26(3),
798–806 (2011)
5. Zhong, Q.C., Hornik, T.: Cascaded current-voltage control to improve the power quality for a
grid-connected inverter with a local load. IEEE Trans. Ind. Electron. 60(4), 1344–1355 (2013)
7. Wang, X.: Research on control strategies for grid-connected inverter with LCL filter.
Postdoctoral research report, Huazhong University of Science and Technology, Wuhan, China
(2011) (in Chinese)
8. Liu, S.: Control strategy for single-phase grid-connected inverter with LCL filter. M.S. thesis,
Huazhong University of Science and Technology, Wuhan, China (2011) (in Chinese)
Chapter 7
Full-Feedforward Scheme of Grid
Voltages for Three-Phase LCL-Type
Abstract In order to alleviate the effect of the grid voltage on the grid current,
Chap. 6 presented the full-feedforward scheme of grid voltages for the single-phase
LCL-type grid-connected inverters, and the harmonics of the injected grid current
are effectively suppressed. In this chapter, the full-feedforward scheme is extended
to the three-phase LCL-type grid-connected inverter. In this chapter, the mathe-
matical models of the three-phase LCL-type grid-connected inverter in both the
stationary a–b frame and synchronous d–q frame are derived first. Then, based
on the mathematical models, the full-feedforward schemes of the grid voltages
for the stationary a–b frame, synchronous d–q frame, and decoupled synchronous
d–q frame-controlled three-phase LCL-type grid-connected inverter are proposed.
After that, the full-feedforward functions are discussed, and it will be illustrated that
the simplification of the full-feedforward function should be taken with caution and
simplifying the full-feedforward functions to a proportional feedforward function
will give rise to the amplification of the high-frequency injected grid current har-
monics. The effect of LCL filter parameter mismatches between the actual and
theoretical values is also evaluated. Finally, the effectiveness of the proposed
full-feedforward schemes is verified by the experimental results. Meanwhile, the
performance of the proposed full-feedforward schemes under unbalanced grid
voltage condition is intentionally investigated.

Keywords Grid-connected inverter LCL filter Damping resonance Total

harmonics distortion (THD) Feedforward Three-phase
As described in Chap. 6, various nonlinear equipments, such as arc wielding

machine and electric rail transportation, are connected into the power grid, and they
produce harmonic currents. These harmonic currents flow through the grid impe-
dance and distort the grid voltage at the point of common coupling (PCC). The
grid-connected inverter is the interface between the distributed power generation
system (DPGS) and the power grid, and it is required to produce high-quality
current to be injected into the power grid [1]. In order to alleviate the effect of the
grid voltage on the grid current, Chap. 6 presented the full-feedforward scheme of
140 7 Full-Feedforward Scheme of Grid Voltages for Three-Phase …
grid voltages for the single-phase LCL-type grid-connected inverters, and the har-
monics of the injected grid current are effectively suppressed. In this chapter, the
full-feedforward scheme is extended to the three-phase LCL-type grid-connected
inverter [2].
Basically, the three-phase grid-connected inverter can be controlled in two
control frames, which are the stationary frame and the synchronous rotating frame.
In this chapter, the mathematical models of the three-phase LCL-type
grid-connected inverter in both the stationary a–b frame and synchronous d–
q frame are derived first. Then, based on the mathematical models, the
full-feedforward schemes of the grid voltages for the stationary a–b frame, syn-
chronous d–q frame, and decoupled synchronous d–q frame-controlled three-phase
LCL-type grid-connected inverter are proposed. After that, the full-feedforward
functions are discussed, and it will be illustrated that the simplification of the
full-feedforward function should be taken with caution and simplifying the
full-feedforward functions to a proportional feedforward function will give rise to
the amplification of the high-frequency injected grid current harmonics. The effect
of LCL filter parameter mismatches between the actual and theoretical values is also
evaluated. Finally, the effectiveness of the proposed full-feedforward schemes is
verified by the experimental results. Meanwhile, the performance of the proposed
full-feedforward schemes under unbalanced grid voltage condition is intentionally
investigated.
7.1 Modeling the Three-Phase LCL-Type

Figure 7.1 shows the three-phase LCL-type grid-connected inverter considered in

this chapter. A standard three-phase voltage source inverter (VSI) consisting of Q1–
Q6 is connected to the grid through an LCL filter. L1 is the inverter-side inductor,
C is the filter capacitor, and L2 is the grid-side inductor. Vin is the dc input voltage
and vga, vgb, and vgc are the three-phase grid voltages.
7.1.1 Model in the Stationary a–b Frame
According to Fig. 7.1, the mathematical model in the stationary a–b–c frame of the
three-phase LCL-type grid-connected inverter is described as
½vxN abc ðt Þ ¼ ½vCx abc ðtÞ þ L1 p½i1x abc ðtÞ

½vCx abc ðt Þ ¼ vgx abc ðt Þ þ vN 0 N ðtÞ½ 1 1 1 T þ L2 p½i2x abc ðt Þ ð7:1Þ
½i1x abc ðt Þ ¼ ½i2x abc ðtÞ þ Cp½vCx abc ðt Þ
7.1 Modeling the Three-Phase LCL-Type Grid-Connected Inverter 141
Fig. 7.1 Schematic diagram of the stationary a–b frame-controlled three-phase grid-connected
inverter
where [vxN_abc(t)] = [vaN(t), vbN(t), vcN(t)]T are the midpoint voltages of the three
inverter legs referred to point N, [vCx_abc(t)] = [vCa(t), vCb(t), vCc(t)]T are the filter
capacitor voltages referred to point N, [vgx_abc(t)] = [vga(t), vgb(t), vgc(t)]T are the
grid voltages referred to point N′, vN′N(t) is the voltage between points N′ and N,
[i1x_abc(t)] = [i1a(t), i1b(t), i1c(t)]T are the inverter-side inductor currents,
[i2x_abc(t)] = [i2a(t), i2b(t), i2c(t)]T are the injected grid currents, and p = d/dt. The
equivalent series resistors of L1, C, and L2 are relatively small and ignored here.
For the three-wire three-phase grid-connected inverter, there is no zero-sequence
injected grid current. Therefore, the system can be controlled in the stationary a–b
frame. The system schematic diagram of the stationary a–b frame-controlled
three-phase grid-connected inverter is shown in Fig. 7.1.
The relationship between the stationary a–b–c frame, a–b frame, and syn-
chronous d–q frame is shown in Fig. 7.2, where xo is the fundamental angular
frequency of the grid. According to Fig. 7.2, the stationary a–b–c to a–b trans-
formation and its inverse transformation used in this chapter are defined by
" #
2 1 1=2 1=2
xab ðtÞ ¼ ½P½xabc ðtÞ; ½P ¼ pffiffiffi pffiffiffi ð7:2Þ
3 0 3 2 3 2
2 3
1 0
3 3 T 6 pffiffiffi 7
½xabc ðtÞ ¼ ½PT xab ðtÞ ; ½P ¼ 6
4 1=2 3 2 75 ð7:3Þ
2 2 pffiffiffi
1=2 3 2
Fig. 7.2 Relationship

between three reference
frames
where [xab(t)] = [xa(t), xb(t)]T are the stationary a–b frame time-varying quantities,
[xabc(t)] = [xa(t), xb(t), xc(t)]T are the stationary a–b–c frame time-varying quanti-
ties, and [P] is the transformation matrix.
Applying (7.3) to transform (7.1), the mathematical model of the main circuit in
the stationary a–b frame is obtained as

vinv ab ðtÞ ¼ vC ab ðtÞ þ L1 p i 1 ab ðtÞ

vC ab ðtÞ ¼ vg ab ðtÞ þ L2 p i2 ab ðt Þ ð7:4Þ

i1 ab ðtÞ ¼ i2 ab ðt Þ þ Cp vC ab ðt Þ
where [vinv_ab(t)] = [vinv_a(t), vinv_b(t)]T, [vC_ab(t)] = [vC_a(t), vC_b(t)]T,

[vg_ab(t)] = [vg_a(t), vg_b(t)] , [i1_ab(t)] = [i1_a(t), i1_b(t)]T, [i2_ab(t)] = [i2_a(t),
T
i2_b(t)]T.
Applying the Laplace transformation to (7.4), the mathematical model in s-
domain can be obtained as

vinv ab ðsÞ ¼ vC ab ðsÞ þ L1 s i 1 ab ðsÞ

vC ab ðsÞ ¼ vg ab ðsÞ þ L2 s i2 ab ðsÞ ð7:5Þ

i1 ab ðsÞ ¼ i2 ab ðsÞ þ Cs vC ab ðsÞ
According to Fig. 7.1 and (7.5), the block diagram of the stationary a–b
frame-controlled three-phase LCL-type grid-connected inverter is shown in
Fig. 7.3, where the feedback of capacitor currents is used to damp the resonance of
the LCL filter, which is equivalent to a virtual resistor connected in parallel with
h i h iT
each filter capacitor. i2 ab ðsÞ ¼ i2 a ðsÞ; i2 b ðsÞ represents the reference of
the injected grid current, Gsi ðsÞ is the injected grid current regulator in the stationary
a–b frame, [vr_ab(s)] = [vr_a(s), vr_b(s)]T are the output signals of the injected grid
current regulators, [vM_ab(s)] = [vM_a(s), vM_b(s)]T are the modulating signals,
ZL1(s), ZC(s), and ZL2(s) are the impedances of L1, C, and L2, expressed as
7.1 Modeling the Three-Phase LCL-Type Grid-Connected Inverter 143
M inv
M inv
Fig. 7.3 Block diagram of the stationary a–b frame-controlled grid-connected inverter
1
sC
KPWM is the transfer function from the modulating signals to the three-phase
inverter bridge voltages. Since the three-phase sine-triangle pulse-width modulation
(PWM) is used here and the switching frequency is assumed to be high enough,
KPWM can be expressed as
KPWM ¼ Vin =ð2Vtri Þ ð7:7Þ
where Vtri is the amplitude of the triangle carrier. Hi1 is the feedback coefficient of
the filter capacitor current, and Hi2 is the sensor gain of the injected grid current.
7.1.2 Model in the Synchronous d–q Frame
According to Fig. 7.2, the stationary a–b frame to synchronous d–q frame trans-
formation and its inverse transformation are defined as

cos xo t sin xo t
xdq ðtÞ ¼ ½C xab ðtÞ ; ½C ¼ ð7:8Þ
sin xo t cos xo t

cos xo t sin xo t
xab ðtÞ ¼ ½C 1 xdq ðtÞ ; 1
½C ¼ ð7:9Þ
sin xo t cos xo t
where [xdq(t)] = [xd(t), xq(t)]T are the synchronous d–q frame time-varying
quantities.
Applying (7.9) to transform (7.4) and manipulating, the mathematical model of

the main circuit in the synchronous d–q frame is obtained as

vinv dq ðtÞ ¼ vC dq ðt Þþ L1 ½AðtÞ i1 dq ðt Þ

vC dq ðtÞ ¼ vg dq ðtÞ þ L2 ½AðtÞ i2 dq ðtÞ ð7:10Þ

i1 dq ðtÞ ¼ i2 dq ðtÞ þ C ½Aðt Þ vC dq ðt Þ
where [vinv_dq(t)] = [vinv_d(t), vinv_q(t)]T, [vC_dq(t)] = [vC_d(t), vC_q(t)]T, [vg_dq(t)] =

[vg_d(t), vg_q(t)]T, [i1_dq(t)] = [i1_d(t), i1_q(t)]T, [i2_dq(t)] = [i2_d(t), i2_q(t)]T,
p xo
½AðtÞ ¼ .
xo p
Applying the Laplace transformation to (7.10), the model in s-domain is given as

vinv dq ðsÞ ¼ vC dq ðsÞ þ L1 ½AðsÞ i1 dq ðsÞ

vC dq ðsÞ ¼ vg dq ðsÞ þ L2 ½AðsÞ i2 dq ðsÞ ð7:11Þ

i1 dq ðsÞ ¼ i2 dq ðsÞ þ C ½AðsÞ vC dq ðsÞ

s xo
where ½AðsÞ ¼ .
xo s
According to (7.11) and considering the controller in the synchronous d–
q frame, the block diagram of the synchronous d–q frame-controlled three-phase
LCL-type grid-connected inverter is shown in Fig. 7.4, where Gei (s) is the injected
grid current regulator in the synchronous d–q frame. Again, the feedback of ca-
pacitor currents is used here to damp the resonance of the LCL filter. From Fig. 7.4,
it is clear to see that there are three pairs of cross-coupling quantities, which are the
currents of filter inductors L1 and L2, and the filter capacitor voltages.
M inv
M inv
Fig. 7.4 Block diagram of the synchronous d–q frame-controlled grid-connected inverter
7.2 Derivation of the Full-Feedforward Scheme of Grid Voltages 145
7.2 Derivation of the Full-Feedforward Scheme of Grid

Voltages
Based on the model given in Sect. 7.1, the full-feedforward schemes of grid volt-
ages for the three-phase LCL-type grid-connected inverter controlled in stationary
a–b frame, synchronous d–q frame, and hybrid frame are derived in this section.
7.2.1 Full-Feedforward Scheme in the Stationary a–b

Frame
It can be seen from Fig. 7.3 that there are no cross-coupling terms between the a-
axis and b-axis, and the model of each axis is the same as the model of the
single-phase inverter given in Fig. 6.2. Therefore, the full-feedforward scheme of
grid voltages for the stationary a–b frame-controlled three-phase LCL-type
grid-connected inverter can be derived similarly as shown in Sect. 6.2. The block
diagram of the full-feedforward scheme of grid voltages for the stationary a–b
frame-controlled grid-connected inverter is shown in Fig. 7.5, and the same as
(6.8), the full-feedforward function of grid voltages in Fig. 7.5 is expressed as
1 L1 C 2
Gff ðsÞ ¼ þ Hi1 C s þ s ð7:12Þ
KPWM KPWM
inv
M
M inv
Fig. 7.5 Block diagram of the full-feedforward scheme for the stationary a–b frame-controlled
7.2.2 Full-Feedforward Scheme in the Synchronous d–q

Frame
The synchronous d–q frame control has the particular advantage of controlling the
active and reactive current directly, which is very convenient for the power flow
control. Therefore, the full-feedforward scheme for the synchronous d–q frame-
controlled three-phase LCL-type grid-connected inverter is derived here.
Similar to the full-feedforward scheme of the stationary a-b frame controlled
given in Fig. 7.5, the feedforward signals in the synchronous d-q frame, which are
referred as vff_d(s) and vff_q(s), can be added into Fig. 7.4, as shown in Fig. 7.6,
where [Gff_dq(s)] is the full-feedforward function for the synchronous d–
q frame-controlled three-phase LCL-type grid-connected inverter.
From Fig. 7.6, it can be obtained that

vinv dq ðsÞ ¼ vr dq ðsÞ Hi1 i1 dq ðsÞ i2 dq ðsÞ þ vff dq ðsÞ KPWM
ð7:13Þ
where [vff_dq(s)] = [vff_d(s), vff_q(s)]T are the feedforward components added to the
modulating signals.
Substituting (7.13) into (7.11) and manipulating, [i2_dq(s)] can be expressed as

1
Hi1 L2 C ½AðsÞ2 þ L2 ½AðsÞ þ L1 ½AðsÞ þ L1 L2 C ½AðsÞ3 i2 dq ðsÞ
KPWM

1
¼ vr dq ðsÞ ½I þ L1 C ½AðsÞ2 þ Hi1 C ½AðsÞ½I vg dq ðsÞ vff dq ðsÞ
KPWM
ð7:14Þ
M inv
M inv
Fig. 7.6 Block diagram of the full-feedforward scheme for the synchronous d–q frame-controlled
where [I] = diag[1] and [vr_dq(s)] = [vr_d(s), vr_q(s)]T are the output of injected grid
current regulator Gei (s), expressed as
h i
vr dq ðsÞ ¼ Gei ðsÞ½I i2 dq ðsÞ i2 dq ðsÞ ð7:15Þ
From (7.14) and (7.15), it can be found that [vg_dq(s)] can be eliminated from
[i2_dq(s)] when [vff_dq(s)] is controlled as depicted as

1 2
vff dq ðsÞ ¼ ½I þ L1 C½AðsÞ þ Hi1 C ½AðsÞ½I vg dq ðsÞ
KPWM ð7:16Þ

, Gff dq ðsÞ vg dq ðsÞ
where [Gff_dq(s)] is expressed as

Gff ðsÞ DðsÞ EðsÞ
Gff ðsÞ ¼ ð7:17Þ
dq
EðsÞ Gff ðsÞ DðsÞ
L1 Cx2o 1 xo C
where Gff(s) has been given in (7.12), DðsÞ ¼ KPWM , EðsÞ ¼ 2sL
KPWM þ xo Hi1 C.
7.2.3 Full-Feedforward Scheme in the Hybrid Frame
Comparing (7.12) and (7.17), it can be observed that the full-feedforward function
[Gff_dq(s)] in the synchronous d–q frame is more complicated than that in the
stationary a–b frame. This is due to the cross-coupling terms in the model shown in
Fig. 7.6. For the synchronous d–q frame-controlled grid-connected inverter, since
the purpose of introducing the full-feedforward of the grid voltages is to suppress
the injected grid currents caused by the grid voltages, and the feedback of the filter
capacitor currents is to damp the resonance of the LCL filter, which make no
contribution to the active and reactive power flow control, it is unnecessary to
implement them in the synchronous d–q frame. Therefore, the full-feedforward of
grid voltages and the feedback of the filter capacitor currents shown in Fig. 7.6 can
be implemented in the stationary a–b frame, while the regulation of the injected
grid currents is still implemented in the synchronous d–q frame which allows the
direct control of the active and reactive power. The block diagram of this scheme is
shown in Fig. 7.7. Hereinafter, the stationary a–b frame implemented
full-feedforward scheme for the synchronous d–q frame-controlled three-phase
grid-connected inverter is called the full-feedforward scheme for hybrid
frame-controlled three-phase grid-connected inverter.
The full-feedforward function Gff(s) in Fig. 7.7 can be directly derived from the
full-feedforward scheme for the synchronous d–q frame-controlled grid-connected
inverter given in Sect. 7.2.2. The s-domain full-feedforward function in the
inv
M
M inv
Fig. 7.7 Block diagram of the full-feedforward scheme for the hybrid frame-controlled
synchronous d–q frame shown in Fig. 7.6 is given in (7.17), and in the time
domain, the feedforward function can be expressed as

h11 ðtÞ h12 ðtÞ
Gff dq ðtÞ ¼ ð7:18Þ
h21 ðtÞ h22 ðtÞ
Therefore, the full-feedforward components of the grid voltages in the syn-

chronous d–q frame shown in Fig. 7.6 is given by

vff d ðt Þ ¼ h11 ðtÞ vg d ðtÞ þ h12 ðtÞ vg q ð t Þ
ð7:19Þ
vff q ðt Þ ¼ h21 ðtÞ vg d ðtÞ þ h22 ðt Þ vg q ð t Þ
where * denotes convolution product.

The stationary a–b to synchronous d–q transformation is given in (7.8), hence
the synchronous grid voltages in terms of the stationary grid voltages can be
expressed as
(
vg d ðt Þ ¼ vg a ðt Þ cos xo t þ vg b ðtÞ sin xo t
ð7:20Þ
vg q ðt Þ ¼ vg a ðtÞ sin xo t þ vg b ðtÞ cos xo t
The synchronous d–q to stationary a–b transformation is given in (7.9), hence

the feedforward components added to the modulating signals in the stationary a–b
frame can be expressed as
(
vff a ðt Þ ¼ vff d ðtÞ cos xo t vff q ðtÞ sin xo t
ð7:21Þ
vff b ðt Þ ¼ vff d ðt Þ sin xo t þ vff q ðt Þ cos xo t
Substituting (7.20) into (7.19), gives

8
>
> vff d ðt Þ¼ h11 ðtÞ vg a ðtÞ cos xo t þ vg b ðtÞ sin xo t
>
<
þ h12 ðtÞ vg a ðtÞ sin xo t þ vg b ðtÞ cosxo t
ð7:22Þ
>
> vff q ðtÞ ¼ h21 ðtÞ vg a ðtÞ cos xo t þ vg b ðt Þ sin xo t
>
:
þ h22 ðtÞ vg a ðtÞ sin xo t þ vg b ðtÞ cos xo t
Substituting (7.22) into (7.21), it can be obtained that

8 ( )
>
> h11 ðtÞ vg a ðt Þ cos xo t þ vg b ðtÞ sin xo t
>
> vff a ðt Þ ¼ cos xo t
>
> þ h12 ðtÞ vg
>
> a ðt Þ sin xo t þ vg b ðt Þ cos xo t
>
> ( )
>
> h21 ðtÞ vg a ðtÞ cos xo t þ vg b ðtÞ sin xo t
>
>
>
> sin xo t
< þ h22 ðtÞ vg a ðtÞ sin xo t þ vg b ðtÞ cos xo t
( ) ð7:23Þ
>
> h11 ðtÞ vg a ðtÞ cos xo t þ vg b ðtÞ sin xo t
>
> vff b ðtÞ ¼ sin xo t
>
>
>
> þ h12 ðtÞ vg a ðtÞ sin xo t þ vg b ðtÞ cos xo t
>
> ( )
>
>
>
> h21 ðtÞ vg a ðt Þ cos xo t þ vg b ðtÞ sin xo t
>
> þ cos xo t
:
þ h22 ðtÞ vg a ðt Þ sin xo t þ vg b ðt Þ cos xo t
Equation (7.23) is transformed into the s-domain by taking the Laplace trans-
formation of each term. (7.24) will be used during the transformation.

s
L hðtÞ vg ðtÞ cosðxo tÞ cosðxo tÞ ¼ L vg ðtÞ cosðxo tÞ H ðsÞ
s2 þ x2o
1 s
¼ H ðsÞvg ðs þ jxo Þ þ H ðsÞvg ðs jxo Þ 2
2 s þ x2o
" #
1 H ðs þ jxo Þvg ðs þ j2xo Þ þ H ðs jxo Þvg ðsÞ
¼
4 þ Hðs þ jxo Þvg ðsÞ þ Hðs jxo Þvg ðs j2xo Þ
" #

1 H ðs þ jxo Þvg ðs þ j2xo Þ þ H ðs jxo Þvg ðsÞ
L hðtÞ vg ðtÞ sinðxo tÞ sinðxo tÞ ¼
4 þ H ðs þ jxo Þvg ðsÞ H ðs jxo Þvg ðs j2xo Þ
" #

j H ðs þ jxo Þvg ðs þ j2xo Þ þ H ðs jxo Þvg ðsÞ
L hðtÞ vg ðtÞ sinðxo tÞ cosðxo tÞ ¼
4 H ðs þ jxo Þvg ðsÞ H ðs jxo Þvg ðs j2xo Þ
" #

j H ðs þ jxo Þvg ðs þ j2xo Þ H ðs jxo Þvg ðsÞ
L hðtÞ vg ðtÞ cosðxo tÞ sinðxo tÞ ¼
4 þ H ðs þ jxo Þvg ðsÞ H ðs jxo Þvg ðs j2xo Þ
ð7:24Þ
where h(t) can be any one of h11(t), h12(t), h21(t), and h22(t), vg(t) can be vg_a(t) or
vg_b(t). H(s) and vg(s) are the Laplace forms of h(t) and vg(t), respectively.
As shown in (7.17), we have
H11 ðsÞ ¼ H22 ðsÞ; H12 ðsÞ ¼ H21 ðsÞ ð7:25Þ
Hence, the Laplace transformation of (7.23) is simplified into (7.26) using

(7.24).
8
>
> 1
> vff
> a ðsÞ ¼ f½H11 ðs þ jxo Þ þ H11 ðs jxo Þ j½H12 ðs jxo Þ H12 ðs þ jxo Þgvg a ðsÞ
>
> 2
>
>
>
> 1
< þ f½H12 ðs þ jxo Þ þ H12 ðs jxo Þ j½H11 ðs þ jxo Þ H11 ðs jxo Þgvg b ðsÞ
2
>
> 1
>
> vff b ðsÞ ¼ f½H12 ðs þ jxo Þ þ H12 ðs jxo Þ þ j½H11 ðs þ jxo Þ H11 ðs jx0 Þgvg a ðsÞ
>
> 2
>
>
>
> 1
: þ f½H11 ðs þ jxo Þ þ H11 ðs jxo Þ j½H12 ðs jxo Þ H12 ðs þ jxo Þgvg b ðsÞ
2
ð7:26Þ
Substituting the corresponding terms shown in (7.17) into (7.26) gives

8
< vff a ðsÞ ¼ 1
þ Hi1 C s þ s 2 vg
L1 C
a ðsÞ
KPWM KPWM
ð7:27Þ
: vff b ðsÞ ¼ 1
þ Hi1 C s þ KLPWM
1C
s 2 vg b ðsÞ
KPWM
According to (7.27), the full-feedforward function in the hybrid frame is
1 L1 C 2
Gff ðsÞ ¼ þ Hi1 C s þ s ð7:28Þ
KPWM KPWM
Comparing (7.28) and (7.12), it is apparent that the full-feedforward function in

the hybrid frame is the same as the full-feedforward function in the stationary a–b
frame. Similarly, the feedback coefficient of the capacitor current can also be
transformed into the stationary a–b frame.
As mentioned above, the control strategy in the hybrid frame in Fig. 7.7 has the
following advantages:
(1) The active and reactive injected grid currents are controlled directly and
independently;
(2) The full-feedforward function is simple, which has no cross-coupling terms;
(3) Less transformation between different control frames.
7.3 Discussion of the Full-Feedforward Functions
In the previous section, the full-feedforward functions for the stationary a–b frame,
synchronous d–q frame, and hybrid frame-controlled three-phase LCL-type
grid-connected inverter have been derived. In this section, the effect of the three
components in the full-feedforward function, which are proportional, derivative,
7.3 Discussion of the Full-Feedforward Functions 151
and second-derivative components, is discussed. After that, the harmonic attenua-

tion affected by LCL filter parameter mismatches is studied. Finally, a comparison
between the full-feedforward functions for the L-type and LCL-type three-phase
grid-connected inverters is presented.
7.3.1 Discussion of the Effect of Three Components

in the Full-Feedforward Function
The full-feedforward functions of grid voltages for the three-phase LCL-type

grid-connected inverters are composed of the proportional, derivative, and
second-derivative components. The proportional component is frequency inde-
pendent, and the derivative and second-derivative components will be increased as
the harmonic frequency going high. Therefore, as the frequency of the harmonic
frequency varies, the effect of the three components will be different, and it is
possible to simplify the full-feedforward function.
For the convenience of the demonstration, a 20-kW three-phase LCL-type
grid-connected inverter prototype is taken as the example, and the main parameters
are given in Table 7.1. According to (7.12), taking the proportional component as
the base, the proportional, derivative, and second-derivative components are drawn
in p.u., as shown in Fig. 7.8. As seen, in the low-frequency range, the proportional
component is dominant; as the frequency goes high, the derivative and
second-derivative components become large and dominant in the high-frequency
range. Therefore, if the grid voltages are mainly distorted by the low-frequency
harmonics, fifth harmonic for example, the full-feedforward function in (7.12) can
be simplified to the proportional component. If the harmonic order is not higher
than thirteenth, the full-feedforward function can be simplified to the proportional
plus derivative component [3].
To help investigating the harmonic attenuation performance of the feedforward
schemes, a generalized equivalent block diagram for the stationary a–b frame-
controlled three-phase LCL-type grid-connected inverter with the feedforward
scheme is given in Fig. 7.9, where F(s) comes from the feedforward path, and it can
be derived by taking the inverse procedures shown in Figs. 6.5 and 6.6 in Chap. 6.
Table 7.1 Parameters of the Parameter Value Parameter Value

prototype
Vin 750 V C 15 lF
Vg (phase, rms) 220 V L2 110 lH
Po 20 kW Vtri 4.58 V
fo 50 Hz Hi1 0.12
fsw 15 kHz Hi2 0.14
L1 700 lH Hv 0.017
Fig. 7.8 Amplitude of the 3

three components of the
full-feedforward function Proportional
in p.u 2
Derivative
1
Second
derivative
0
100 101 102 103 104
Frequency (Hz)
Fig. 7.9 Generalized block

diagram of the three-phase
LCL-type grid-connected
inverter with the feedforward
schemes
Taking the a-axis, for example, vg_a(s) is the actual grid voltage at a-axis, while
v′g_a(s) which is used to evaluate the harmonic attenuation performance, is the
equivalent grid voltage at a-axis with feedforward schemes. Observing Fig. 7.9, it
can be obtained that
v0g a ðsÞ ¼ vg a ðsÞð1 þ F ðsÞÞ ð7:29Þ
If the full-feedforward scheme is used, F(s) equals to −1 and v′g_a(s) is zero,

which means that the injected grid currents caused by the grid voltages are elimi-
nated. In this case, the a-axis in Fig. 7.9 is equivalent to Fig. 6.5a in Chap. 6.
When the full-feedforward scheme is simplified to the proportional feedforward
scheme, according to Fig. 7.5, F(s) can be derived as
1
Gff P ðsÞGx1 ðsÞ KPWM
F ðsÞ ¼ ¼ ð7:30Þ
Gsi ðsÞ 1
KPWM þ Hi1 C s þ L1 C
KPWM s2
where Gff_P(s) is the proportional component in (7.12).

Substituting (7.30) into (7.29), v′g_a(s) can be expressed as
Fig. 7.10 Equivalent grid

voltage at a-axis in p.u
Hi1 C s þ L1 C
s2
v0g
KPWM
a ðsÞ ¼ vg a ðsÞ ð7:31Þ
1
KPWM þ Hi1 C s þ L1 C
KPWM s2
According to (7.31), the amplitude of v0g a ðsÞ in per-unit values with vg_a(s) as
the base is drawn in Fig. 7.10 using the parameters listed in Table 7.1. It can be
observed that with the proportional feedforward scheme, the low-frequency har-
monics are well suppressed, while the equivalent grid voltage is larger than that
without feedforward scheme at the frequency range higher than ft, and it means the
corresponding injected grid current harmonics are amplified. ft can be derived by
equalizing the amplitude of v′g_a(s) and vg_a(s) from (7.31), i.e.,

2
j2pft Hi1 C þ ðj2pf t Þ L1 C

K PWM ¼1 ð7:32Þ
1 ðj2pft Þ L1 C
2
K þ j2pf H
t i1 C þ KPWM

PWM
Solving (7.32), leads to
1
ft ¼ pffiffiffiffiffiffiffiffiffiffiffi ð7:33Þ
2p 2L1 C
As seen, ft is only related to the parameters of the LCL filter.

Based on the above analysis, it can be known that the high-order harmonics are
amplified by the proportional feedforward scheme, while the full-feedforward
scheme can yield a relative wide-frequency-range harmonic suppression.
7.3.2 Harmonic Attenuation Affected by LCL Filter

Parameter Mismatches
In practice, due to the tolerance or aging of the filter components and the parasitic
parameters of the system, the LCL filter parameter mismatches might happen.
Referring to (7.12), (7.17), and (7.28), the full-feedforward functions are related to
L1 and C. Therefore, the harmonic attenuation performance of the full-feedforward
schemes might be weakened by the LCL filter parameter mismatches. The effect of
LCL filter parameter mismatches is also analyzed with Fig. 7.9.
With the full-feedforward scheme, F(s) is depicted as (7.34) when LCL filter
parameter mismatches happen.
s2 L 1 C
0
1
KPWM þ Hi1 C s þ KPWM
F ðsÞ ¼ F ðsÞ ¼ s2 L01 C 0
ð7:34Þ
1
KPWM þ Hi1 C 0 s þ KPWM
where C′ and L01 are the actual parameters of the filter capacitance and inverter-side
inductance in the prototype, C and L1 are the parameters in the designer’s mind.
Assuming the variations of C′ and L01 are limited to ±10% and ±20%,
respectively. Through the enumeration method, the worst case is found to be
C′ = 0.9C and L01 = 0.8L1. Substituting (7.34) into (7.29) and taking vg_a(s) as the
base, the amplitude of v′g_a(s) under the worst case can be expressed in per-unit
values and drawn in Fig. 7.10 using the parameters listed in Table 7.1. Since larger
equivalent grid voltages bring larger injected grid currents, it can be seen that the
harmonic attenuation performance of the full-feedforward scheme at low-frequency
range is still outstanding even with large LCL filter parameter mismatches, but it is a
little weakened at higher-frequency range. Besides, using full-feedforward scheme,
no injected grid current harmonic amplification is found with LCL filter parameter
mismatches.
7.3.3 Comparison Between the Feedforward Functions

for the L-Type and the LCL-Type Three-Phase
The full-feedforward function for the three-phase LCL-type grid-connected inverter

derived in this chapter consists of three parts, which are the proportional, derivative,
and second-derivative parts. For the three-phase L-type grid-connected inverter,
C does not exist. So, Letting C = 0 in (7.12) yields the disappearance of derivative
and second-derivative parts, and only the proportional part holds. This means that
the proportional feedforward scheme is valid for the three-phase L-type
grid-connected inverter, which has been proposed in [4–7]. The connection and
differences between the three-phase grid-connected inverters with different filters
are listed as follows to help understanding the new features of the full-feedforward
schemes.
(1) Feedforward function for the three-phase L-type grid-connected inverter is the
same as the proportional part of the full-feedforward functions for the LCL-type
inverter. And, there are two additional parts, which are derivative and
second-derivative components, in the full-feedforward functions for the LCL-
type grid-connected inverter.
(2) Since there are derivative components in the full-feedforward function for the
LCL-type grid-connected inverter, when the grid voltage step happens, the
calculated feedforward signal becomes infinite, which is not applicable in
practical circuits. Therefore, compared with the L-type grid-connected inverter,
the improvement of the transient response under the step change of the grid
voltage using full-feedforward scheme for the LCL-type grid-connected inverter
is quite limited.
(3) The feedforward function for the three-phase L-type grid-connected inverter
stays the same no matter the feedforward scheme is implemented in the sta-
tionary a–b frame or the synchronous d–q frame [5, 6]. In contrast, the
full-feedforward functions for the three-phase LCL-type grid-connected inverter
are different when the feedforward schemes are implemented in different
frames.
Therefore, when applying the feedforward scheme for the three-phase LCL-type
grid-connected inverter, the full-feedforward function should be selected according
to the control strategy being used.
7.4.1 Description of the Prototype
To verify the effectiveness of the full-feedforward scheme, a 20-kW prototype is

built and tested in the laboratory. Figure 7.11 gives the photograph of the prototype.
The key parameters of the prototype have been given in Table 7.1. The power
switches use IGBT module CM100DY-24NF and the driving chip is M57962L.
The current sensors are LA-55P, and the voltage sensors are LV-25P. The controller
is implemented in a DSP (TMS320F2812). The sampling frequency (fs = 1/Ts) of
the digital control system is 20 kHz. Synchronization of the injected grid currents to
grid voltages is achieved by a digital PLL. An RC low-pass filter with the time
constant of 0.1 ls is used in the prototype to suppress the noise in the sampling
circuits of the grid voltages. A very little phase shift of the sampled grid voltage is
introduced by this low-pass filter, and it has little effect on the performance of the
full-feedforward scheme. Moreover, the backward difference approximation, which
L1 IGBT & Drive

DC Bus
Capacitor
DSP Board
L2
Auxiliary
Power
C C C
Filter capacitor and

sampling board
Fig. 7.11 Photograph of the prototype
is defined as s = (1 − z−1)/Ts, is used to discretize the controller. For example, the

full-feedforward function of the grid voltages given in (7.12) can be discretized as
" 2
#
1 1 ð1 z1 ÞHi1 C ð1 z1 Þ L1 C
Gff ðzÞ ¼ þ þ ð7:35Þ
Hv KPWM Ts Ts2 KPWM
Therefore, the output of (7.35) only depends on the past and present input, which
means that Gff(z) is a causal function.
7.4.2 Experimental Results
To get an accurate evaluation of the proposed full-feedforward schemes, the grid

voltages are simulated using a programmable AC source (Chroma 6590). The
simulated grid voltages distorted by fifth, seventh, eleventh, thirteenth, and
twenty-third harmonics. The magnitudes of the simulated grid voltage harmonics
with respect to the fundamental component of the grid voltages are 5%, 3%, 2%,
2%, and 1%, respectively, and the corresponding phases are 180°, 0°, 0°, 0°, and 0°.
Both the full-feedforward schemes for the stationary a–b frame and hybrid
frame-controlled three-phase grid-connected inverter are verified in the experiment,
which are defined as strategy I and strategy II, respectively.
Figures 7.12 and 7.13 show the experimental results with strategies I and II
under the simulated distorted grid voltages. The measured total harmonic distortion
(THD) of the injected grid currents shown in Fig. 7.12a–c are 15.6%, 13.6%, and
Fig. 7.12 Experimental vga vgb vgc

results under distorted grid
voltages with strategy I. Grid
voltage: 200 V/div, injected
grid current: 10 A/div
i2a i2b i2c
Time: [5 ms/div]
(a) No feedforward scheme
vga vgb vgc
i2a i2b i2c
Time: [5 ms/div]
(b) Proportional feedforward scheme
vga vgb vgc
i2a i2b i2c
Time: [5 ms/div]
(c) Full-feedforward scheme
4.6%, respectively. The measured THD of the injected grid currents shown in
Fig. 7.13a–c are 16.4%, 13.2%, and 5.1%, respectively. The harmonic spectrum of
the injected grid currents shown in Figs. 7.12 and 7.13 is presented in Fig. 7.14.
From Figs. 7.12, 7.13, and 7.14, it can be observed that the proposed
full-feedforward schemes suppress the injected grid current harmonics caused by
Fig. 7.13 Experimental vga vgb vgc

voltages with strategy II. Grid
i2a i2b i2c
Time: [5 ms/div]
vga vgb vgc
i2a i2b i2c
Time: [5 ms/div]
vga vgb vgc
i2a i2b i2c
Time: [5 ms/div]
(c) Full-feedforward scheme
the grid voltage distortion effectively. Compared with the full-feedforward schemes,
the proportional feedforward scheme has a relatively poor performance on sup-
pressing the injected grid current harmonics. Furthermore, Fig. 7.14 shows that the
proportional feedforward scheme amplifies the twenty-third order current harmonic.
It is in agreement with the conclusion that simplifying the full-feedforward function
Fig. 7.14 Harmonic

spectrum of the injected grid
gy I
Strate gy II
currents under distorted grid
voltages Str a t e
Percentage of injected grid

10
current harmonics (%)

9
8
7
6
5
4
3
2 23
13
1
11
0 nic
ward ard
7 armo
o r 5 r of h
e d f w
No fe al feedfor edforward Orde
tion Full f
e
Propor
for the three-phase LCL-type grid-connected inverter to a proportional feedforward

function will give rise to the amplification of the high-frequency harmonics as
shown in Fig. 7.10.
The proposed full-feedforward scheme for the three-phase LCL-type
grid-connected inverter is also investigated under unbalanced grid voltage condi-
tion. In the laboratory, the representative phase-to-phase-fault unbalanced grid
voltages and single-phase-fault unbalanced grid voltages transferred through a
Δy transformer [8] are simulated using the programmable AC source. The
positive-sequence grid voltage is 80% of the rated grid voltage and the phase is 0°.
The negative-sequence grid voltage is 20% of the rated grid voltage and the phase is
also 0°. Thus, the three-phase grid voltages are described as
vga ðtÞ ¼ 311 sinðxo tÞ

vgb ðtÞ ¼ 224 sinðxo t þ 226:1 Þ ð7:35Þ
vgc ðtÞ ¼ 224 sinðxo t þ 133:9 Þ
where vga preserves the nominal grid voltage, and the voltages of the other two
phases have reduced magnitude and present a symmetrical phase deviation of 13.9°.
Figure 7.15 gives the experimental results with strategy I under unbalanced grid
voltage condition. The positive-sequence injected grid current reference is 4 A, and
the negative-sequence injected grid current reference is 0 A. The synchronization of
the positive-sequence grid voltage is achieved with the digital PLL. As shown in
Fig. 7.15a, without the feedforward scheme of the grid voltages, the RMS value of
i2a is 4.70 A, and i2a has a large phase shift with respect to vga. The RMS value of
i2b and i2c are 4.01 A and 4.78 A, respectively. The injected grid currents are
obviously unbalanced. With the proposed full-feedforward scheme of the grid
voltages, as shown in Fig. 7.15b, the measured rms value of i2a is 4.06 A, and the
phase shift with respect to vga is eliminated. The RMS value of i2b and i2c are
4.08 A and 4.09 A, respectively. Therefore, by introducing the proposed

vga vgb vgc
voltages with strategy II. Grid
i2a i2b i2c
Time:[5 ms/div]
vga vgb vgc
i2a i2b i2c
Time:[5 ms/div]
full-feedforward scheme of the grid voltages, the negative-sequence injected grid

current is well regulated under the unbalanced grid voltage condition.
Figure 7.16 gives the experimental results with strategy I at full load (20 kW)
under a real power grid. Figure 7.16a gives the experimental results without
feedforward scheme. It can be observed that there is a little phase shift between the
injected grid currents and grid voltages. Meanwhile, the injected grid currents are
distorted by the grid voltage harmonics, and the measured THD of the injected grid
currents is 1.18%. Figure 7.16b gives the experimental results with the proposed
full-feedforward scheme. Obviously, the phase shift between grid currents and grid
voltages is eliminated, and the injected grid current harmonics are greatly reduced
with the measured THD of 0.97%. Therefore, the proposed full-feedforward
scheme works well under a real power grid.
Figure 7.17a, b show the transient response of the three-phase LCL-type
grid-connected inverter using strategy I when the step change in the grid current
reference and the grid voltages occur, respectively. The references of the injected
grid currents are stepped between half load and full load in Fig. 7.17a. Note that the
waveforms in Fig. 7.17a are taken under a real power grid. It is observed that the
Fig. 7.16 Experimental vga vgb

results under real grid with
strategy I. Grid voltage:
100 V/div, injected grid
current: 20 A/div
i2a i2b
Time:[5 ms/div]
vga vgb
i2a i2b
Time:[5 ms/div]
references are fast tracked in about 2 ms, and at steady state, the injected grid
currents are well regulated. The overshoot of the injected grid currents is large.
Fortunately, in practice, the step change of the reference is not indispensable and it
can approximately be replaced by a ramp change, for example, the reference ramps
to the final value in 1 ms. This approximation would dramatically improve the
transient performance of the system. In Fig. 7.17b, the three-phase grid voltages are
stepped between 220 V and 180 V. The step changes of the grid voltages are
simulated using the programmable AC source. It is observed that the amplitude of
the injected grid currents is kept unchanged at steady state, but the proposed
full-feedforward scheme seems useless during the transient state. This is because
there are derivative and second-derivative parts in the full-feedforward function
shown in (7.12). The step change of the grid voltages will result in infinite feed-
forward signals, and this is only possible in mathematics but not in practice.
Therefore, the improvement of the transient response under the step change of the
grid voltage using full-feedforward scheme is quite limited.
Fig. 7.17 Transient response vga

with strategy I. Grid voltage:
200 V/div, injected grid i2a i2b i2c
current: 5 A/div
Time:[10 ms/div]
(a) Step change in the grid current reference.
Grid voltage: 100 V/div, injected grid current: 20 A/div.
vga
i2a i2b i2c
Time:[10 ms/div]
(b) Step change in the grid voltages.
7.5 Summary
To suppress the harmonic and unbalance components in the grid currents injected
from the grid-connected inverter, the full-feedforward scheme of grid voltages in
the stationary a–b frame, synchronous d–q frame, and hybrid frame for the
three-phase LCL-type grid-connected inverter have been proposed and investigated
in this chapter. The full-feedforward function is mainly composed of the propor-
tional, derivative, and second-derivative components. A brief comparison between
the feedforward functions for the L-type and the LCL-type three-phase
grid-connected inverter is presented to emphasize the new features of the pro-
posed full-feedforward schemes. Moreover, it is important to notice that simplifying
the full-feedforward function for the three-phase LCL-type grid-connected inverter
to a proportional feedforward function will give rise to the amplification of the
high-frequency harmonics. With the proposed full-feedforward schemes, the
injected grid current harmonics and unbalance caused by the grid voltage are
greatly reduced. Besides, the harmonic attenuation affected by LCL filter parameter
7.5 Summary 163
mismatches is also discussed, and it is found that the harmonic attenuation per-
formance of the full-feedforward scheme is still outstanding even with large LCL
filter parameter mismatches. Finally, a 20-kW prototype has been built to verify the
effectiveness of the proposed full-feedforward scheme. It should be pointed out that
the improvement of the transient response under step change of the grid voltages is
limited in practice due to the limited amplitude of the feedforward signals.
References
1. Prodanović, M., Green, T.C.: High-quality power generation through distributed control of a
power park microgrid. IEEE Trans. Ind. Electron. 53(5), 1471–1482 (2006)
2. Li, W., Ruan, X., Pan, D., Wang, X.: Full-feedforward schemes of grid voltages for a
three-phase LCL-type grid-connected inverter. IEEE Trans. Ind. Electron. 60(6), 2237–2250
(2013)
4. Timbus, A.V., Liserre, M., Teodorescu, R., Rodriguez, P., Blaabjerg, F.: Evaluation of current
controllers for distributed power generation systems. IEEE Trans. Power Electron. 24(3), 654–
664 (2009)
three phase ac current regulators. IEEE Trans. Power Electron. 24(11), 2417–2426 (2009)
6. Kim, J.S., Sul, S.K.: New control scheme for ac-dc-ac converter without dc link electrolytic
capacitor. In: Proceeding of the IEEE Power Electronics Specialists Conference, pp. 300–306.
(1993)
7. Zeng, Q., Chang, L.: An advanced SVPWM-based predictive current controller for three-phase
inverters in distributed generation systems. IEEE Trans. Ind. Electron. 55(3), 1235–1246
(2008)
8. Bollen, M.H.J.: Characterization of voltage sags experienced by three-phase adjustable-speed
drives. IEEE Trans. Power Del. 12(4), 1666–1671 (1997)
Chapter 8
Design Considerations of Digitally
Controlled LCL-Type Grid-Connected
Inverter with Capacitor-
Current-Feedback Active-Damping
Abstract The capacitor-current-feedback active-damping is an effective approach

for damping the resonance peak of the LCL filter. When the LCL-type
grid-connected inverter is digitally controlled, the control delay will be generated.
This will result in different behavior of the capacitor-current-feedback
active-damping from that with analog control. In this chapter, the mechanism of
the control delay in the digital control system is introduced first. Then, a series of
equivalent transformations of the control block diagram considering the control
delay are performed, and it reveals that the capacitor-current-feedback
active-damping is no longer equivalent to a virtual resistor in parallel with the
filter capacitor, but a virtual frequency-dependent impedance. A forbidden region
for choosing the LCL filter resonance frequency is presented in order to guarantee
the system stability. Then, the controller design for digitally controlled LCL-type
grid-connected inverter with capacitor-current-feedback active-damping is studied.
Since the control delay leads to a phase lag and consequently changes the location
of −180°-crossing in the phase curve of the loop gain, the system stability might be
guaranteed even without damping the resonance of LCL filter. For this case, the
necessary condition for system stability is studied, and the controller design method
is presented. Finally, the controller parameters design examples for the grid current
regulator with and without the capacitor-current-feedback active-damping are
given, and the effectiveness of the theoretical analysis is verified by the experi-
mental results.

Keywords Grid-connected inverter LCL filter Active damping Digital control
Controller design
8.1 Introduction
In the LCL-type grid-connected inverter, the inherent resonance of LCL filter

exhibits a resonance peak and a sharp phase step down of −180° at the resonance
frequency, which might trigger undesired oscillation or even system instability.
166 8 Design Considerations of Digitally Controlled LCL-Type …
Therefore, the resonance peak should be damped properly to ensure system sta-
bility. Chapter 4 has presented the methods of damping the LCL filter resonance.
Adding a resistor in parallel with the filter capacitor can effectively damp the
resonance without affecting magnitude-frequency characteristics of the LCL filter at
the low- and high-frequency ranges. However, there is considerable power loss in
the damping resistor, degrading the efficiency of the grid-connected inverter. With a
series of equivalent transformation of control block diagram, it is revealed that the
capacitor-current-feedback active-damping is equivalent to a virtual resistor in
parallel with the filter capacitor, and the power loss in the real resistor is avoided.
A step-by-step controller design method for the LCL-type grid-connected inverter
with capacitor-current-feedback active-damping has been presented in Chap. 5,
where PI and PR regulators are adopted as the grid current regulator. Given the
specified grid current steady-state error, stability margin (including phase margin
and gain margin), a satisfactory region for the capacitor-current-feedback coefficient
and the crossover frequency is obtained. With this satisfactory region, it is very
convenient to choose the controller parameters and optimize the system
performance.
Actually, the equivalent transformation of the control block diagram presented in
Chap. 4 is based on the analog control. When the LCL-type grid-connected inverter
is digitally controlled, the control delay, including the computation and pulse-width
modulation (PWM) delays, will be generated. This will result in different behavior
of the capacitor-current-feedback active-damping. In this chapter, the mechanism of
the control delay in the digital control system will be introduced first. Then, a series
of equivalent transformations of the control block diagram considering the control
delay are performed, and it will reveal that the capacitor-current-feedback
active-damping is no longer equivalent to a virtual resistor, but a virtual
frequency-dependent impedance, which is in parallel with the filter capacitor. The
virtual frequency-dependent impedance consists of a virtual reactor and a virtual
resistor, which are connected in parallel. The virtual reactor makes the resonance
frequency of the system loop gain derivate from the resonance frequency of the
LCL filter. The virtual frequency-dependent resistor might be negative at the res-
onance frequency of the loop gain, which implies the loop gain will contain two
open-loop right-half-plane (RHP) poles. This is different from the characteristics of
the analog control system.
After that, a forbidden region for choosing the LCL filter resonance frequency is
presented in order to guarantee the system stability. Then, the controller design
for digitally controlled LCL-type grid-connected inverter with capacitor-
current-feedback active-damping is studied. Similar to that presented in Chap. 5,
in terms of the specified grid current steady-state error, phase margin, and gain
margin, a satisfactory region for the capacitor-current-feedback coefficient and the
crossover frequency is obtained, from which, proper controller parameters can
easily be selected.
Since the control delay leads to a phase lag and consequently changes the
location of −180°-crossing in the phase curve of the loop gain, the system stability
might be guaranteed even without damping the resonance of LCL filter. For this
8.1 Introduction 167
case, the necessary condition for system stability will be studied, and the controller
design method is presented [1].
Finally, the controller parameters design examples for the grid current regulator
with and without the capacitor-current-feedback active-damping are given, and the
effectiveness of the theoretical analysis is verified by the experimental results from a
6-kW single-phase LCL-type grid-connected inverter prototype.
8.2 Control Delay in Digital Control System
Figure 8.1 shows the main circuit and control diagram of the digitally controlled
LCL-type grid-connected inverter, where Hv and Hi2 represent the sampling coef-
ficients of the grid voltage vg and the grid current i2, respectively. The filter ca-
pacitor current iC is fed back with the coefficient Hi1 for damping the resonance of
the LCL filter. The grid current reference i2 = I*cosh, where h is the phase of vg,
which is obtained through a phase-locked loop (PLL), and I* is the current
amplitude reference, which is generated by the outer voltage loop. The error
between i2 and i2 is sent to the grid current regulator Gi(z). The modulation signal
vM is obtained by subtracting the feedback signal of filter capacitor current from the
output of Gi(z). By comparison with vM and the triangular carrier, the control
signals of the power switches in the grid-connected inverter are generated.
Generally, the crossover frequency of the outer voltage loop is far lower than that of
the grid current loop [2, 3], so the grid current loop can be designed independently.
In digital control system, the currents i2 and iC are usually sampled at the peak
and valley of the triangular carrier to avoid the switching noise, as shown in
Fig. 8.2 [4]. The sampled i2 and iC, for example at step k, are sent to the digital
signal processor (DSP) and calculated by the control algorithm to obtain the
modulation signal vM. To avoid repetitive intersections of vM and the carrier signal,
Fig. 8.1 Digital control L1 L2

vC
schematic of single-phase +
LCL filtered grid-connected i1 iC i2
inverter Vin vinv C vg
–
Sine-triangle PWM Hi1 Hi2 Hv
PLL
cosθ
vM – + – + i2*
Gi(z) I*
DSP Controller
Fig. 8.2 Key waveforms of

signal sampling and digital i2 Actual current
PWM
Sampled current
0 t
Sampled current Actual current
iC
vM
0 t
Carrier
j
l
t
Ts
k k+1 k+2 k+3 k+4
the calculated vM is updated at step k + 1 [5]. Therefore, one sampling period delay
occurs, and this delay is called computation delay [6, 7]. After that, vM keeps
constant in the following sampling period and compares with the triangular carrier.
The zero-order hold (ZOH) is used to model the PWM process, expressed as [8]
1 esTs
Gh ðsÞ ¼ Ts e0:5sTs : ð8:1Þ
s
As shown in (8.1), the ZOH induces a half sampling period delay, which is
called PWM delay.
In summary, in the digital SPWM scheme, there exists control delay, including
the computation and the PWM delays. The former one is one sampling period delay
and the latter one is half sampling period delay.
8.3 Effect of Control Delay on Loop Gain

and Capacitor-Current-Feedback Active-Damping
8.3.1 Equivalent Impedance

of Capacitor-Current-Feedback Active-Damping
According to Fig. 8.1, the mathematical model in z-domain of the digitally con-
trolled LCL-type grid-connected inverter is given in Fig. 8.3a where z−1 represents
8.3 Effect of Control Delay on Loop Gain … 169
(a)
M M inv
(b)
M M inv
(c) M inv
M
(d) inv
Fig. 8.3 Mathematical model of the digitally controlled LCL filtered grid-connected inverter with
capacitor-current-feedback active-damping
the computation delay; KPWM = Vin/Vtri is the transfer function from the modulation
signal v′M after the ZOH to the inverter bridge output voltage, with Vin and Vtri
being the input voltage and the amplitude of the triangular carrier, respectively;
ZL1(s) = sL1, ZC(s) = 1/(sC), and ZL2(s) = sL2 are the impedances of L1, C, and L2,
respectively.
To intuitively illustrate the effect of the control delay on the
capacitor-current-feedback active-damping, the z-domain model shown in Fig. 8.3a
is transferred to the s-domain one, as shown in Fig. 8.3b, where the frequency
response of the sampling switch is represented by 1/Ts within the Nyquist fre-
quency, i.e., fs/2, [9, 10], z ¼ esTs , and i*2(s) and Gi(s) are the counterparts of
i*2(z) and Gi(z) in s-domain, respectively. As observed from Fig. 8.3b, 1/Ts is
included in both the forward path of i*2(s) and the feedback paths of i2 and iC, so it
can be merged into the input of the transfer function esTs , as shown in Fig. 8.3c.
The product of 1/Ts, esTs and Gh(s) is e−1.5sTs; thus, Fig. 8.3c is simplified to
Fig. 8.3d.
By changing the feedback of capacitor current to that of capacitor voltage, and
relocating the feedback node from the output of Gi(s) to that of 1/ZL1(s), Fig. 8.3d is
equivalently transformed into Fig. 8.4a. As observed, the capacitor-current feed-
back can be equivalent to virtual impedance Zeq in paralleled with the filter
capacitor, and the expression of Zeq is
ZL1 ðsÞZC ðsÞ L1

Zeq ¼ ¼ e1:5sTs ¼ RA e1:5sTs ð8:2Þ
KPWM Hi1 e1:5sTs CKPWM Hi1
where RA = L1/(CKPWMHi1), which is the equivalent virtual resistor of the

capacitor-current-feedback active-damping in analog control system, which has
been presented in Chap. 5.
Substituting s = jx into (8.2) yields
Zeq ðjxÞ ¼ RA cosð1:5xTs Þ þ jRA sinð1:5xTs Þ , Req ðxÞ==jXeq ðxÞ ð8:3Þ
where
Req ðxÞ ¼ RA =cosð1:5xTs Þ ð8:4aÞ
Xeq ðxÞ ¼ RA =sinð1:5xTs Þ: ð8:4bÞ
vg(s)
i2*(s) + – 1 + – 1 i2(s)
Gi(s) + e –1.5sTs KPWM + + + ZC(s)
– – ZL1(s) – – ZL2(s)
KPWMHi1e–1.5sTs
Hi1
ZL1(s)ZC(s)
1/Z eq(s)
Hi2
(a) Equivalent transformation of the block diagram

L1 L2
+ +
vinv C jXeq Req vg
(b) Equivalent circuit
Fig. 8.4 Equivalent virtual impedance of the capacitor-current-feedback active-damping.

a Equivalent transformation of the block diagram. b Equivalent circuit
Fig. 8.5 Curves of Req and

Req
Xeq as the functions of
frequency Xeq
RA
0
RA
fs/6 fs/3 fs/2

f (Hz)
As shown in Eq. (8.3), Zeq can be represented in the form of parallel connection
of a resistor Req and a reactor Xeq, as shown in Fig. 8.4b.
According to (8.4), the curves of Req and Xeq as the function of frequency can be
depicted, as shown in Fig. 8.5. As observed, when Hi1 > 0, Req is positive in the
range (0, fs/6) and negative in the range (fs/6, fs/2); Xeq is inductive in the range (0,
fs/3) and capacitive in the range (fs/3, fs/2). When Hi1 < 0, the frequency charac-
teristics of Req and Xeq are opposite to that when Hi1 > 0.
Comparing Fig. 8.3d with Fig. 5.2 in Chap. 5, it can be found that the difference
is the control delay e1:5sTs . Therefore, replacing KPWM in (5.4) by KPWMe1:5sTs ,
the loop gain of the digitally controlled LCL-type grid-connected inverter can be
obtained as
Hi2 KPWM e1:5sTs Gi ðsÞ

T D ðsÞ ¼
s L1 L2 C þ s L2 CHi1 KPWM e1:5sTs þ sðL1
3 2 þ L2 Þ
1 Hi2 KPWM e1:5sTs Gi ðsÞ
¼ 2 ð8:5Þ
sL1 L2 C s þ CZeq1 ðsÞ s þ x2r
qffiffiffiffiffiffiffiffiffiffiffi
L1 þ L 2
where xr ¼ 2p fr ¼ L1 L2 C is the resonance angular frequency of the LCL filter.
As shown in (8.5), both the numerator and denominator of TD(s) contain the
control delay e1:5sTs . The e1:5sTs in numerator introduces phase lag, and the
e1:5sTs in denominator affects the location of the loop gain poles.
Figure 8.6 shows the Bode diagram of the uncompensated loop gain when
Hi1 > 0. Since Xeq behaves as a virtual inductor in the range (0, fs/3), the loop gain
resonance frequency fr′ will be higher than the LCL filter resonance frequency fr, as
shown in Fig. 8.6a, b, and Xeq behaves as a virtual capacitor in the range (fs/3, fs/2);
thus, fr′ will be lower than fr, as shown in Fig. 8.6c. According to (8.4b) and
considering RA = L1/(CKPWMHi1), a larger Hi1 will lead to a smaller RA and thus a
smaller |Xeq|. A smaller |Xeq| means that Xeq may behave as a smaller inductance or a
larger capacitance, which will cause a higher fr′ or lower fr′. That is to say,
increasing Hi1 will cause fr′ to deviate far from fr. Since fs/3 is the boundary for Xeq
is inductive and capacitive, no matter how Hi1 increases, fr′ cannot exceed fs/3. This
Hi1=0 Hi1=Hi1C Hi1=0
|AT | (dB)
|AT | (dB)
0 0
Hi1
D
D
Hi1
0 0
Ang(T ) (º)
Ang(T ) (º)
−180 −180
D
D
−360 −360
−540 −540
fr fs/6 fs/2 fs/6 fr fs/3 fs/2
(a) fr < fs/6 (b) fs/6 ≤ fr < fs/3
Hi1=0
|AT | (dB)
0
D
Hi1
0
Ang(T ) (º)
−180
D
−360
−540
fs/6 fs/3 fr fs/2
Frequency (Hz)
(c) fs/3 ≤ fr < fs/2
Fig. 8.6 Bode diagrams of the uncompensated loop gain TD(s)
means that when fr < fs/3, fr′ cannot be higher than fs/3 as Hi1 increases; when
fr > fs/3, fr′ cannot be lower than fs/3 as Hi1 increases.
8.3.2 Discrete-Time Expression of the Loop Gain
As mentioned above, Req is negative in the range (fs/6, fs/2), which implies that the
loop gain might have RHP poles. As shown in (8.5), the loop gain TD(s) contains
the nonlinear term e1:5sTs , it is difficult to directly calculate the poles in TD(s). So,
the control diagram shown in Fig. 8.3a will be transformed into z-domain. Note that
vg(s) is a disturbance which does not affect the location of the poles, so it is ignored
in the following transformation.
According to Fig. 8.3a, the transfer function from v′M to i2 can be obtained as
i 2 ðsÞ Gh ðsÞ KPWM 1 KPWM 1

0 ¼ 2 ¼ 1 esTs 2 ð8:6Þ
vM ð z Þ sL1 L2 C s þ xr
2 s L1 L2 C s2 þ x2r
While ignoring vg, i2 can be expressed as
1
i2 ðsÞ¼ iC ðsÞ ð8:7Þ
s2 L2 C
i C ðsÞ KPWM 1
0 ¼ 1 esTs ð8:8Þ
vM ðzÞ L1 s2 þ x2r
Applying z-transform to (8.6) and (8.8), respectively, yields

i 2 ðzÞ sTs
KPWM 1
¼ Z 1 e
v0M ðzÞ s L1 L2 C s þ xr
2 2 2

KPWM xr Ts ðz 1Þ sin xr Ts
¼ 2 ð8:9Þ
xr ðL1 þ L2 Þ z 1 z 2z cos xr Ts þ 1

iC ðzÞ sTs
KPWM 1 z1 KPWM sin xr Ts
¼ Z 1 e ¼ ð8:10Þ
v0M ðzÞ L1 s2 þ x2r xr L1 z2 2z cos xr Ts þ 1
Defining the output of Gi(z) in Fig. 8.3a as vr(z), v′M can be expressed as
v0M ðzÞ ¼ z1 ðvr ðzÞ Hi1 iC ðzÞÞ ð8:11Þ
Rearranging (8.11) leads to
v0M ðzÞ 1
¼ ð8:12Þ
vr ðzÞ z þ Hi1 iC ðzÞ
v0M ðzÞ
According to Fig. 8.3a, TD(z) can be expressed as
i 2 ðzÞ i2 ðzÞ v0M ðzÞ

TD ðzÞ , Hi2 Gi ðzÞ ¼ Hi2 Gi ðzÞ 0 ð8:13Þ
vr ð z Þ vM ðzÞ vr ðzÞ
i 2 ðzÞ 1
TD ðzÞ ¼ Hi2 Gi ðzÞ ð8:14Þ
v0M ðzÞ z þ Hi1 iC ðzÞ
v0M ðzÞ
Substituting (8.9) and (8.10) into (8.14) leads to
Hi2 Gi ðzÞKPWM
TD ðzÞ ¼
xr ðL1 þ L2 Þ
xr Ts ðz2 2z cos xr Ts þ 1Þ ðz 1Þ2 sin xr Ts
h i ð8:15Þ
ðz 1Þ zðz2 2z cos xr Ts þ 1Þ þ ðz 1Þ Hi1xKr LPWM
1
sin xr Ts
As shown in (8.15), there is no nonlinear term in TD(z). Thus, it is convenient to

obtain the poles in TD(z) in z-domain.
8.3.3 RHP Poles of the System Loop Gain
As shown in (8.15), since Gi(z) does not contain any open-loop unstable pole, and
the pole z = 1 locates on the unit circle which is not an open-loop unstable pole, the
open-loop unstable poles in TD(z) are determined by the following equation, i.e.,
Hi1 KPWM
z z2 2z cos xr Ts þ 1 þ ðz 1Þ sin xr Ts ¼ 0 ð8:16Þ
xr L1
In order to easily identify the number of the open-loop unstable poles in

TD(z) easily, w-transform is introduced. Substituting z = (1 + w)/(1 − w) into
(8.16) [9] gives
a0 w3 þ a1 w2 þ a2 w þ a3 ¼ 0 ð8:17Þ
where
8
> a0 ¼ 1 þ cos xr Ts þ Hi1xKr LPWM sin xr Ts
>
< 1
a1 ¼ 1 þ cos xr Ts 2 Hi1xKr LPWM sin xr Ts
1 ð8:18Þ
>
> ¼ 1 cos xr Ts þ xr L1 sin xr Ts
Hi1 KPWM
: a2
a3 ¼ 1 cos xr Ts
The Routh array for (8.17) is expressed as
w 3 : a0 a2
w 2 : a1 a3
ð8:19Þ
w 1 : b1 0
w 0 : a3
where b1 = (a1a2 − a0a3)/a1. In order to ensure the controllability of the system, fr

must be lower than fs/2, so we have xrTs < p [9]. Given Hi1 0, it can be
observed from (8.18) that a0, a2, and a3 are always larger than 0.
Based on the Routh criterion, the number of the RHP roots of (8.17) is equal to
the number of the sign changing in the first row of the Routh array in (8.19), i.e.,
(a0, a1, b1, a3)T. If (8.17) has the RHP roots, a1 < 0 or b1 < 0 must be true.
If b1 < 0 is true, Hi1 must satisfy
ð2 cos xr Ts 1Þxr L1
Hi1 [ , Hi1C ð8:20aÞ
KPWM sin xr Ts
If a1 < 0 is true, Hi1 must satisfy
ð1 þ cos xr Ts Þxr L1 0
Hi1 [ , Hi1C ð8:20bÞ
2KPWM sin xr Ts
It is obvious that cosxrTs 1, so we have H′i1C Hi1C according to (8.20a,

b). If Hi1 > Hi1C, then b1 < 0. Considering a0 > 0 and a3 > 0, no matter a1 > 0 or
a1 < 0, the sign of (a0, a1, b1, a3)T changes two times. Therefore, two open-loop
unstable poles must be in TD(z).
Substituting Hi1 = Hi1C into (8.16), the two open-loop unstable poles in
pffiffiffi
TD(z) can be calculated, which are z1;2 ¼ 12 1 j 3 . Mapping z1,2 back to s-
domain produces s1,2 = ± jpfs/3, which means that the resonance peak of the loop
gain actually locates at fs/6, as shown in Fig. 8.6a. In the range (0, fs/3), a larger Hi1
results in a higher fr′. Therefore, when Hi1 > Hi1C, fr′ > fs/6 happens. As mentioned
above, Req is negative in the range (fs/6, fs/2), so Req at fr′ must be negative when
TD(z) has open-loop unstable poles. Please note that the open-loop unstable poles in
TD(z) correspond to the RHP poles in TD(s).
Substituting x = 2pfr and x = 2pfs/6 into (8.15), respectively, yields
Hi2
TD ejxTs x¼2pfr ¼ ð8:21aÞ
Hi1 x2r L2 C
Hi2 L1 xr Ts ð1 2 cos xr Ts Þ þ sin xr Ts

TD ejxTs x¼2pfs =6 ¼ ð8:21bÞ
ðL1 þ L2 Þ sin xr Ts Hi1C Hi1
As shown in (8.21a), when Hi1 0, TD at fr is negative, which means that the

phase curve of TD crosses −180° at fr. Defining g(xrTs) = xrTs(1 − 2cosxrTs)
+ sinxrTs, and considering xrTs p, it can be calculated that the derivative of g
(xrTs), g′(xrTs), is greater than 0, which means that g(xrTs) is a monotone increasing
function, i.e., g(xrTs) g(0) = 0. So, according to (8.21b), when Hi1 > Hi1C, TD at
fs/6 is negative, which means the phase curve of TD also crosses −180° at fs/6. This
conclusion is in accord with Fig. 8.6. The analysis when Hi1 < 0 is similar to that
when Hi1 0, which is not given here.
8.4 Stability Constraint Conditions for Digitally

Controlled System
8.4.1 Nyquist Stability Criterion
As stated in Sect. 8.3.3, when Req is negative at fr′, the loop gain TD(s) contains two
RHP poles. The stability constraint conditions for the controller design are different
from those in Chap. 5. Fortunately, the Nyquist stability criterion is still applicable
for illustrating the stability constraint conditions of the digitally controlled LCL-
type grid-connected inverter. For the convenience of discussion, this criterion is
given here. Figure 8.7a, b shows the Nyquist diagram and the corresponding Bode
diagram [9], respectively. The −180°-crossing is classified as follows:
1. When the amplitude–phase curve of the loop gain in the Nyquist diagram
encircles (−1, j0) counterclockwise once, a positive crossing is recorded. It is
equivalent to that the phase curve crosses −180° (2k + 1) (k is an integer)
from down to up in the Bode diagram when the corresponding amplitude curve
is above 0 dB.
Im
Positive Mag(dB)
Negative
(–1, j0) 0
Re
0 Positive Negative
Phase(°)
–180 (2k+1)
(a) Nyquist diagram (b) Bode diagram
Fig. 8.7 Positive and negative crossing. a Nyquist diagram. b Bode diagram
8.4 Stability Constraint Conditions … 177
2. When the amplitude–phase curve encircles (−1, j0) clockwise once, a negative
crossing is recorded. It is equivalent to that the phase curve crosses
−180° (2k + 1) from up to down in the Bode diagram when the corre-
sponding amplitude curve is above 0 dB.
3. When the amplitude–phase curve ends to or starts from the negative real axis
and encircles (−1, j0) counterclockwise, a half positive crossing is recorded. It is
equivalent to that the phase curve ends to or starts from −180° (2k + 1) from
down to up when the corresponding amplitude curve is above 0 dB.
4. When the amplitude–phase curve ends to or starts from the negative real axis
and encircles (−1, j0) clockwise, a half negative crossing is recorded. It is
equivalent to that the phase curve ends to or starts from −180° (2k + 1) from
up to down when the corresponding amplitude curve is above 0 dB.
According to the Nyquist stability criterion, only when C+ − C− = P/2, the
system is stable, where C+ and C− denote the times of positive and negative
crossing, respectively, and P denotes the number of RHP poles in the loop gain.
8.4.2 System Stability Constraint Conditions
In order to guarantee system stability and good dynamic response, sufficient sta-
bility margins, i.e., gain margin and phase margin, are required for a compensated
system. As stated in Sect. 8.3.3, when Req is negative at fr′, the loop gain TD(s) has
two RHP poles, i.e., P = 2. According to the Nyquist stability criterion, it requires
C+ − C− = 1. Taking Fig. 8.6 as the example, it requires C+ = 1 and C− = 0, which
means the negative crossing must be disabled, and the positive crossing must be
enabled. Accordingly, the resonance peak of the loop gain cannot be damped below
0 dB. Obviously, the stability constraint conditions are different from those for the
analog-controlled inverter in Chap. 5.
For the convenience of illustration, GM1 and GM2 are defined as the gain
margins at fr and fs/6, respectively, and PM is defined as the phase margin at fc (the
first 0 dB-crossing frequency of the amplitude–frequency curve). Then, the stability
constraint conditions can be concluded as:
Case I When fr < fs/6 and Hi1 Hi1C, as shown in Fig. 8.8a, P = 0, and the
phase curve only crosses −180° at fr from up to down. If GM1 > 0 and
PM > 0, the system will be stable. Note that since no positive crossing
occurs, GM2 is not required.
Case II When fr < fs/6 and Hi1 > Hi1C, as shown in Fig. 8.8b, P = 2, and the
phase curve crosses −180° at fr and fs/6 from up to down and from down
Hi1=0 Hi1=0
GM2
|AT | (dB)
|AT | (dB)
0 0
D
D
GM1 GM1
0 0
Ang(T ) (º)
Ang(T ) (º)
−180 −180
D
D
PM PM
−540 −540
fc fr fs/6 fr fs/2 fc fr fs/6 fr fs/2
(a) fr < fs/6, Hi1 ≤ Hi1C (b) fr < fs/6, Hi1 > Hi1C
Hi1=0
|ATD | (dB)
GM1
0
GM2
0
Ang(TD ) (º)
−180
PM
−540
fc fs/6 fr fr fs/2
Frequency (Hz)
(c) fr ≥ fs/6
Fig. 8.8 Stability constraints in Bode diagrams
to up, respectively. If GM1 > 0, GM2 < 0 and PM > 0, the system will
be stable.
Case III When fr fs/6, as shown in Fig. 8.8c, it can be observed from (8.20a)
that Hi1C < 0. If Hi1 > 0, P = 2, and the phase curve crosses −180° at fs/
6 and fr from up to down and from down to up, respectively. If GM1 < 0,
GM2 > 0, and PM > 0, the system will be stable.
Note that by comparing Case II and Case III, the frequencies of the two
−180°-crossings of TD(s) are exchanged. Accordingly, the requirements of GM1
and GM2 are also exchanged.
8.5 Design Considerations of the Controller Parameters … 179
8.5 Design Considerations of the Controller Parameters

of Digitally Controlled LCL-Type Grid-Connected
Inverter
8.5.1 Forbidden Region of the LCL Filter Resonance

Frequency
As observed from Fig. 8.8b, c, if fr = fs/6, GM1 = GM2 will happen. At this time,
the requirements of GM1 and GM2 for Case II and Case III can never be satisfied,
and the system can hardly be stable. Since the gain margins are usually recom-
mended to be no less than 2 dB [11], a forbidden region can be obtained, where the
LCL filter resonance frequency fr cannot fall into.
According to Fig. 8.8, the gain margins GM1 and GM2 can be expressed as
GM1 ¼ 20 lgjTD ðj2pfr Þj ð8:22aÞ
GM2 ¼ 20 lgjTD ðj2pfs =6Þj ð8:22bÞ
As stated in Sect. 5.2, no matter PI or PR regulator is used, Gi(s) is approximate

to the proportional coefficient Kp within the crossover frequency fc. In practice, fc is
lower than both fr and fs/6, so we have Gi(2pfr) Gi(2pfs/6) Kp. Substituting
Gi(2pfr) Gi(2pfs/6) Kp, s = j2pfr, and s = j2pfs/6 into (8.5) yields
Hi1 ðL1 þ L2 Þ
GM1 ¼ 20 lg ð8:23Þ
Hi2 Kp L1

ð2pfs =6ÞL1 L2 C 2 2 ð2pfs =6ÞKPWM Hi1
GM2 ¼ 20 lg ð2pfr Þ ð2pfs =6Þ þ
Hi2 KPWM Kp L1
ð8:24Þ
As observed from Fig. 8.8, the magnitude curve of the uncompensated TD

descends with a slope of −20 dB/dec within fc, which means the effect of the filter
capacitor C is little within fc. Substituting C 0 into (8.5), TD can be approximated
to

TD ðsÞ ð8:25Þ
s ð L 1 þ L2 Þ
Since |TD(j2pfc)| = 1 and Gi(2pfc) Kp, Kp can be calculated from (8.25),

expressed as
2p fc ðL1 þ L2 Þ
Kp ð8:26Þ
Hi2 KPWM
Substituting (8.26) into (8.23), the Hi1 constrained by GM1 can be obtained as
GM1
Hi1 GM1 ¼ 10 20 2pfc L1 =KPWM ð8:27Þ
Substituting (8.26) and (8.27) into (8.24) yields

( 2 " #)
GM1 fs =6 fs =6 fs =6 2
GM2 ¼ 20 lg 10 20 þ 1 ð8:28Þ
fr fc fr
(8.28) can be rewritten as
GM2 fr GM1 fr
10 20 k3fr k2fr 10 20 kfr þ ¼ 0 ð8:29Þ
fc fc
where
fr
kfr ¼ ð8:30Þ
fs =6
It is worth noting that fc is determined by the phase margin PM, and fc is

commonly set to be 0.3fr so as to achieve a sufficient phase margin [12, 13]. When
fr < fs/6, substituting the expected GM1 and GM2 into (8.29), the lower limit of kfr
is obtained; when fr > fs/6, substituting the expected GM1 and GM2 into (8.29), the
upper limit of kfr is obtained. Since the sampling frequency fs is selected, the
forbidden region of LCL filter resonance frequency fr is obtained.
8.5.2 Constraints of the Controller Parameters
According to the design method of LCL filter in Chap. 2 and the forbidden region of
fr, the LCL filter can be determined. Then, considering the stability constraint
conditions presented in Sect. 8.4.2, the design procedure of the grid current regu-
lator and the capacitor-current-feedback coefficient proposed in Chap. 5 can be
applied to the digitally controlled grid-connected inverter. According to the
requirements of steady-state error of the grid current and the stability margins, the
satisfactory region of the grid current regulator or the capacitor-current-feedback
coefficient can be determined, from which the proper parameters can be selected.
Since PR regulator can provide a sufficiently high gain at the fundamental
frequency to reduce the steady-state error, it is used here. The PR regulator is
expressed as
2Kr xi s
s2 þ 2xi s þ x2o
where Kp is the proportional gain, Kr is the resonance gain; xo is the angular

fundamental frequency, and xi is the bandwidth of the resonant part concerning
−3 dB cutoff frequency to reduce the sensitivity of the regulator to grid frequency
variations at xo [14], which means the gain of the resonant part of PR regulator is
0.707Kr at xo ± xi. For the sake of the sufficiently high gain with the frequency
fluctuation of 0.5 Hz, xi = p rad/s is set.
As stated in Sect. 8.5.1, at the frequencies lower than fc, the expression of the
uncompensated system loop gain TD can be approximated to (8.25). Comparing
(8.25) with (5.7), it can be observed that the approximated TD has one more term
e1:5sTs than TA, which means the magnitude curves of TD and TA are the same at the
frequencies lower than fc. Therefore, the requirements of the loop gain at the
fundamental frequency, Tfo, constrained by steady-state value EA, and the grid
current regulator Gi(s) constrained by Tfo, are the same in both digitally controlled
and the analog-controlled inverters. So, the Kr constrained by Tfo is the same as
(5.35), which is given here again as (8.32)

Tfo 2pðL þ L Þ
1 2
Kr Tfo ¼ 10 20 fo fc ð8:32Þ
Hi2 KPWM
By substituting s = 2pfc into (8.31), and considering the crossover frequency fc

is much higher than fo and fi, Gi(j2pfc) Kp + 2Krfi/fc can be obtained. Note that
fi = xi /(2p). Substituting s = 2pfc and Gi(j2pfc) Kp + 2Krfi/fc into (8.5), PM can
be derived, expressed as

2pL1 fr2 fc2 þ Hi1 KPWM fc sinð3pfc Ts Þ Kr xi
PM ¼ arctan 3pfc Ts arctan
Hi1 KPWM fc cosð3pfc Ts Þ pfc Kp
ð8:33Þ
Applying tangent on both sides of (8.33) and manipulating, the Kr constrained

by PM is obtained as

2pðfr2 fc2 ÞL1
þ sinð3pfc Ts Þ tanð3pfc Ts þ PMÞ cosð3pfc Ts Þ
pfc2 ðL1 þ L2 Þ fc KPWM Hi1
Kr PM ¼
KPWM Hi2 fi 2pðfr2 fc2 ÞL1
fc KPWM Hi1 þ sinð3pfc Ts Þ tanð3pfc Ts þ PMÞ þ cosð3pfc Ts Þ
ð8:34Þ
If the selected Kr meets the constraints of Tfo and PM simultaneously, we have

Kr_Tfo = Kr_PM. According to (8.32) and (8.34), the Hi1 constrained by Tfo and PM
in digital control system can be obtained as
2pL1 ðfr2 fc2 Þ

h
Tfo i
fc2 2fi 10 20 fo fc tanð3pfc Ts þ PMÞ
fc KPWM cosð3pfc Ts Þ
Hi1 Tfo PM ¼ (
Tfo ) ð8:35Þ
2fi 10 20 fo fc ½tanð3pfc Ts þ PMÞ tanð3pfc Ts Þ þ 1
þ fc2 ½tanð3pfc Ts þ PMÞ tanð3pfc Ts Þ
Substituting (8.26) into (8.24), the Hi1 constrained by GM2 can be obtained as
" #
2pL1 GM2 fr 2 ðfs =6Þ2 fr2
Hi1 GM2 ¼ 10 20 fc þ ð8:36Þ
KPWM fs =6 fs =6
When Tfo, PM, GM1, and GM2 are specified, the satisfactory region formed by fc
and Hi1 can be obtained.
8.5.3 Design of LCL Filter, PR Regulator

and Capacitor-Current-Feedback Coefficient
From the above analysis, the design procedure of the grid current regulator and
capacitor-current-feedback coefficient for the digitally controlled grid-connected
inverter can be concluded as follows.
Step 1: Specify the requirements of Tfo, PM, GM1, and GM2. Tfo is determined
by the requirement of the steady-state error of grid current. GM1 and
GM2 are determined by the relationship between fr and fs/6, as well as
the requirement of system robustness: (1) When fr fs/6, GM1 < 0 dB
and GM2 > 0 dB are required; (2) when fr < fs/6, if Hi1 Hi1C,
GM1 > 0 dB is required, and if Hi1 > Hi1C, GM1 > 0 dB and
GM2 < 0 dB are required. To guarantee the system dynamic response
and robustness, PM is usually recommended to be within (30°, 60°), and
the GMs are recommended to be no less than 3–6 dB, i.e., |GM1, 2|
3–6 dB.
Note that there is no constraint on Hi1_PWM in digital control system,
since the modulation signal vM keeps constant in one sampling period
after being updated.
Step 2: Substituting the specified GM1 and GM2 into (8.29) yields the lower and
upper limits of kfr. Given the sampling frequency, the forbidden region
of the LCL filter resonance frequency fr is obtained. Referring to the
forbidden region, the designed parameters of LCL filter with the design
method presented in Chap. 2 should be carefully modified.
Step 3: According to the specified requirements of Tfo, PM, GM1, and GM2, the
boundaries of Hi1_GM1, Hi1_Tfo_PM, and Hi1_GM2 as the functions of fc can
be determined according to (8.27), (8.35), and (8.36), respectively.

According to these boundaries, the satisfactory region of Hi1 and fc can
be obtained.
Step 4: Select the proper fc from the satisfactory region. In practice, a higher fc is
recommended so as to attain the better dynamic response and a high gain
in the low-frequency range. Then, Kp can be calculated according to
(8.26).
Step 5: After fc is determined, the proper Hi1 can be selected according to the
boundaries of Hi1_GM1, Hi1_Tfo_PM, and Hi1_GM2. When fr fs/6, the
lower limit of Hi1 is Hi1_GM2, and the upper limit is the minimum value
of Hi1_GM1 and Hi1_Tfo_PM; when fr < fs/6, the lower limit of Hi1 is
Hi1_GM1, while the upper limit is the minimum value of Hi1_GM2 and
Hi1_Tfo_PM. To improve the dynamic response, a smaller Hi1 is
recommended.
Step 6: After fc and Hi1 are determined, the lower and upper limits of Kr can be
determined from (8.32) and (8.34). The larger Kr is, the larger Tfo is,
whereas the smaller PM is. Therefore, when the required Tfo and PM are
met, trade-off is needed when selecting an appropriate Kr to achieve the
expected performance.
satisfied.
Note that if the requirements of Tfo, PM, GM1, and GM2 in Step 1 are too strict,
the satisfactory region may be very small or null. If so, return to Step 1 and modify
the requirements of Tfo, PM, GM1, and GM2, and then renew Step 2.
8.6 Design of Current Regulator for Digitally Controlled

LCL-Type Grid-Connected Inverter Without Damping
As observed from Fig. 8.8c, when fr > fs/6, the phase curve of the uncompensated
loop gain TD crosses −180° from up to down only one time and it occurs at fs/6. If
the proportional gain of the grid current regulator Gi(s), Kp, is tuned to make the
loop gain TD at fs/6 below 0 dB, the negative crossing is disabled. As a result, the
system stability may be guaranteed by properly designing the grid current regulator
and the resonance damping is not required. In the following, the design of the grid
current regulator for the digitally controlled LCL-type grid-connected inverter
without damping is studied.
8.6.1 Stability Necessary Constraint for Digitally Controlled

LCL-Type Grid-Connected Inverter Without Damping
Substituting Hi1 = 0 into (8.5), the loop gain without damping is obtained as

TD nodamp ðsÞ ¼ ð8:37Þ
s3 L1 L2 C þ sðL1 þ L2 Þ
Obviously, it is shown in (8.37) that TD_nodamp contains no RHP poles, i.e.,

P = 0. As shown in Fig. 8.6, it is clear that, when Hi1 = 0, there is only one
−180°-crossing in the phase curve of TD, and it is from up to bottom and occurs at fr
when fr fs/6 or at fs/6 when fr > fs/6. This means that, for the uncompensated TD,
only one negative crossing is possible, and no positive crossing exists, i.e., C+ = 0.
According to the Nyquist stability criterion, only when C+ − C− = P/2, the
system is stable. Here, P = 0, and C+ = 0. So, in order to guarantee the system
stability, the negative crossing must be disabled, i.e., C− = 0. For the purpose of
disabling the negative crossing, the loop gain should be lower than 0 dB at the
negative crossing frequency. As shown in Fig. 8.6a, when fr fs/6, the
−180°-crossing occurs at fr. The loop gain at fr is hardly reduced below 0 dB due to
the resonance peak. As shown in Fig. 8.6b, c, when fr > fs/6, the −180°-crossing
occurs at fs/6. The loop gain at fs/6 could be easily reduced below 0 dB by selecting
a small proportional gain Kp when PI or PR regulator is adopted.
From the above analysis, it can be concluded that, for a digitally controlled LCL-
type grid-connected inverter, if fr > fs/6, the system might be stable without
damping the resonance of the LCL filter. Basically, the possibility to guarantee the
system stability when fr > fs/6 is due to the existence of the control delay, which
results in a phase lag. As shown in Fig. 8.6b, c, the phase lag makes the
−180°-crossing occur at fs/6, earlier than fr. And, the loop gain at fs/6 is far smaller
than that at fr, so it is easy to disable the negative crossing of the phase curve.
It is worth noting that when fr < fs/6, if the inverter-side inductor current is
directly controlled, the system stability without damping can also be guaranteed,
which is not discussed here.
8.6.2 Design of Grid Current Regulator and Analysis

of System Performance
Similar to Sect. 8.5, according to the requirements of the steady-state error and the
system stability margins, the design procedure of the grid current regulator without
damping will be presented. In the following, PR regulator is also used as the current
regulator.
8.6 Design of Current Regulator for Digitally Controlled … 185
8.6.2.1 Constraints of Steady-State Error and Stability Margins

on Grid Current Regulator
Since the closed-loop system without damping is the special case with Hi1 = 0,
(8.26) about the relationship of Kp and fc is still true, and (8.32) about Kr con-
strained by Tfo is also true.
Substituting Hi1 = 0 into (8.34), the Kr, constrained by the phase margin PM
without damping, is obtained as
pfc2 ðL1 þ L2 Þ
Kr PM nodamp ¼ ð8:38Þ
KPWM Hi2 fi tanð3pfc Ts þ PMÞ
Substituting Hi1_GM2 = 0 into (8.36), the crossover frequency fc_GM_nodamp

constrained by the gain margin GM2 can be obtained, expressed as
GM2 fs fr2 ðfs =6Þ2

fc GM nodamp ¼ 10 20 ð8:39Þ
6 fr2
8.6.2.2 Design Procedure of Grid Current Regulator Parameters

Without Damping
Similar to the design procedure given in Sect. 8.5.3, the design procedure of the
grid current regulator without damping can be concluded as follows:
Step 1: Specify the requirements of Tfo, PM, and GM2. The detailed require-
ments are the same as given in Sect. 8.5.3. Note that GM1 is not required
here, since the −180°-crossing does not occur at fr when the
capacitor-current-feedback active-damping is not used, as shown in
Fig. 8.8c.
Step 2: According to the specified requirements of Tfo, PM, and GM2 in Step 1,
calculate the boundaries of Kr_Tfo, Kr_PM, fc_GM with respect to fc based
on (8.32), (8.38), and (8.39), respectively. Based on these boundaries,
the satisfactory region of Kr and fc can be determined.
Step 3: Select a proper fc from the satisfactory region. Then, Kp can be calcu-
lated from (8.26).
Step 4: After fc is determined, a proper Kr can be selected according to the
boundaries of Kr_Tfo and Kr_PM.
satisfied.
Here, selecting appropriate fc and Kr in the satisfactory region is the same as that
given in Sect. 8.5.3.
8.6.2.3 Analysis of System Performance Without Damping
As illustrated in Chap. 5 and Sect. 8.5.2, the capacitor-current-feedback

active-damping can increase the gain margin, whereas reduce the phase margin
at the frequencies lower than fr. Therefore, compared to the compensated system
with capacitor-current-feedback active-damping, the compensated system without
damping can achieve a larger phase margin when fr > fs/6. Besides, as stated in
Sect. 8.5.1, at the frequencies lower than fc, the loop gain TD can be approximated
to (8.25) and is independent from Hi1. It means that the capacitor-current-feedback
active-damping has little effects on the steady-state error. So, the effect caused by
Hi1 = 0 on the crossover frequency and gain margin is analyzed in the following.
As stated in Sect. 8.5.3, when the capacitor-current-feedback active-damping is
used, if fr fs/6, the lower limit of Hi1 is Hi1_GM2, and the upper limit is the
minimum value of Hi1_GM1 and Hi1_PM. Clearly, to ensure the expected gain
margins GM1 and GM2, the maximum crossover frequency should be no higher
than the frequency when Hi1_GM1 = Hi1_GM2. For convenience, the maximum
crossover frequency is defined as fc_GM, According to (8.27) and (8.36), fc_GM can
be obtained as
fr2 ðfs =6Þ2 fs

fc GM ¼ GM2 GM1 ð8:40Þ
10 20 fr2 2
ðfs =6Þ 10 20 6
According to (8.39) and (8.40), the ratio of fc_GM_nodamp and fc_GM is derived as

fc GM nodamp fs =6 2 GM1 GM2
¼1 10 20 20 ð8:41Þ
fc GM fr
Obviously, the ratio of fc_GM_nodamp and fc_GM is less than 1. In other words, with
the same specified gain margins, the maximum crossover frequency without
damping is lower than that with capacitor-current-feedback active-damping. This is
because that the loop gain without damping at fs/6 is not attenuated, the crossover
frequency must be lowered down to reduce the loop gain at fs/6 to reserve the
specified gain margin.
8.7 Design Examples
This section will present the design examples for the LCL-type grid-connected
inverter with and without capacitor-current-feedback active-damping. The main
parameters of the single-phase LCL-type grid-connected inverter are listed in
Table 8.1, where three different LCL filters are intentionally given for the purpose
of verifying the forbidden region of fr. The resonance frequencies of filters I, II, and
III are 2.7 kHz, 3.2 kHz, and 4.6 kHz, respectively. The resonance frequencies of
filters I and II are lower than fs/6 (= 3.33 kHz), and the resonance frequency of filter
III is higher than fs/6.
8.7.1 Design Example with Capacitor-Current-Feedback

Active-Damping
When the capacitor-current-feedback active-damping is employed, Tfo, PM, GM1,

and GM2 are specified as follows:
1. Set Tfo > 73 dB, so as to ensure the steady-state error of the grid current below
1% when the grid frequency variation is ±0.5 Hz.
2) Set PM > 45°, so as to ensure a good dynamic response.
3. When fr < fs/6 and Hi1 Hi1C, set GM1 = 3 dB; when fr < fs/6 and
Hi1 > Hi1C, set GM1 = 3 dB and GM2 = −3 dB; when fr fs/6,
GM1 = −3 dB and GM2 = 3 dB. All these requirements are to ensure the sys-
tem robustness.
When fr < fs/6, setting fc to 0.3fr [13], and substituting GM1 = 3 dB and
GM2 = −3 dB into (8.29), three roots of kfr can be obtained, which are −1.08, 0.88,
and 4.9. When fr > fs/6, substituting GM1 = −3 dB and GM2 = 3 dB into (8.29),
also yields three roots of kfr, which are −0.92, 1.25, and 2.04. According to the two
sets of three roots, it can be obtained that the lower limit of kfr is 0.88 and the upper
limit of kfr is 1.25. As a result, the forbidden region of kfr is [0.88, 1.25].
When filter I is used, it can be calculated that kfr = 0.81, which is outside the
forbidden region [0.88, 1.25]. According to (8.27), (8.35), and (8.36), Fig. 8.9a can
be obtained. Referring to Step 5 of the design procedure in Sect. 8.4, the lower and
upper limits of Hi1 are determined by GM1 and PM, respectively. As observed from
Table 8.1 Parameters of prototype

System parameters
Input voltage Vin 360 V Fundamental fo 50 Hz
frequency
Grid voltage (RMS) Vg 220 V Switching frequency fsw 10 kHz
Output power Po 6 kW Sampling frequency fs 20 kHz
Amplitude of the Vtri 3V Grid Hi2 0.15
triangular carrier current-feedback
coefficient
LCL filter parameters
Filter Inverter-side Filter Grid-side Resonance
inductor L1 (lH) capacitor inductor L2 (lH) frequency fr (kHz)
C (lF)
I 600 30 150 2.7
II 600 20 150 3.2
III 600 10 150 4.6
0.1 0.1
GM1=3dB GM1=3dB
0.08 0.08
Tfo=73dB 0dB
PM=36 B =0dB
0.06 0.06 GM1 increase GM2
GM2
=0dB
Hi1
Hi1
−3dB increase
A GM1
0.04 0.04
GM2 increase
A GM2=−3dB
0.02 0.02
Tfo=73dB Tfo=73dB
PM=45 PM=45
0 0
500 1000 1500 2000 500 1000 1500 2000
fc (Hz) fc (Hz)
(a) Filter I (b) Filter II
0.1
0.08
GM2=3dB
Tfo=73dB
0.06 PM=45
0dB
Hi1
B
0.04 GM1 increase
−3dB
0.02
A
0
500 1000 1500 2000
fc (Hz)
(c) Filter III
Fig. 8.9 Satisfactory region constrained by GM1, GM2, PM, and Tfo
Fig. 8.9a, the upper limit of Hi1 is always lower than the lower limit, so the
satisfactory region of fc and Hi1 does not exist. To overcome this problem, the
expected PM is reduced to 36°. Accordingly, the satisfactory region appears, shown
as the shaded area in Fig. 8.9a. Point A is selected, where fc = 1.1 kHz and
Hi1 = 0.05. Substituting fc = 1.1 kHz into (8.26) yields Kp = 0.293. According to
(8.32) and (8.34), Kr_Tfo = 59.2 and Kr_PM = 66.6 can be calculated, respectively.
Here, we choose Kp = 0.29 and Kr = 63. With these designed parameters, the
compensated loop gain TD is depicted, as shown Fig. 8.10a. As shown,
Tfo = 73.6 dB, PM = 36.5°, GM1 = 3.1 dB, and GM2 = −6.1 dB, which meet the
expected requirements.
When filter II is used, it can be calculated that kfr = 0.96, which is in the
forbidden region [0.88, 1.25]. Likewise, according to (8.27), (8.35), and (8.36),
Fig. 8.9b can be obtained. In this case, the lower and upper limits of Hi1 are
determined by GM1 and GM2, respectively. As observed from Fig. 8.9b, the upper
limit of Hi1 is also always lower than the lower limit, so the satisfactory region of fc
and Hi1 does not exist. If both the expected GM1 and GM2 are reduced to 0, i.e.,
100 100
50
|ATD | (dB)
50
|ATD | (dB)
0 0
Uncompensated TD(s) Uncompensated TD(s)
Compensated TD(s) Compensated TD(s)
−50 −50
0 0
Ang(TD) (º)
Ang(TD) (º)
−180 −180
−360 fc: 1.1 kHz; Tfo: 73.6 dB; −360 fc: 1.0 kHz; Tfo: 73.7 dB;
GM1: dB; GM2: 6.1 dB; GM1: dB; GM2: 0.2 dB;
PM: 36.5º PM: 45º
−540 −540
10 fo 102 103 fc fr fs/6 104 10 fo 102 103(fc) fr fs/6 104
(a) Filter I (b) Filter II
100
50
|ATD | (dB)
0
Uncompensated TD(s)
Compensated TD(s)
−50
0
Ang(TD) (º)
−180
−360 fc: 1.3 kHz; Tfo: 73.6 dB;

GM1: dB; GM2: 3.2 dB;
PM: 45º
−540
10 fo 102 103 fc fs/6 fr 104
Frequency (Hz)
(c) Filter III
Fig. 8.10 Bode diagrams of uncompensated and compensated loop gains
GM1 = GM2 = 0, and the satisfactory region appears, shown as the shaded area in
Fig. 8.9b. In the satisfactory region, point A is selected, where fc = 1 kHz and
Hi1 = 0.034. Substituting fc = 1 kHz into (8.26) yields Kp = 0.27. According to
(8.32) and (8.34), Kr_Tfo = 59.2 and Kr_PM = 59.6 can be calculated. Here,
Kp = 0.27 and Kr = 59.3 are chosen. With these design parameters, the compen-
sated loop gain TD is depicted, as shown Fig. 8.10b, from which it can be measured
that Tfo = 73.7 dB, PM = 45°, GM1 = −0.2 dB, and GM2 = 0.2 dB. Clearly, GM1
and GM2 are too small, which will result in poor dynamic response.
When filter III is used, it can be calculated that kfr = 1.38, which is outside the
forbidden region [0.88, 1.25]. According to (8.27), (8.35), and (8.36), Fig. 8.9c can
be obtained. In this case, the lower and upper limits of Hi1 are determined by GM2
and GM1, respectively. As observed in Fig. 8.9c, the satisfactory region exists.
From the satisfactory region, point A is selected, where fc = 1.3 kHz and
Hi1 = 0.02. Substituting fc = 1.3 kHz into (8.26) yields Kp = 0.346. According to
(8.32) and (8.34), Kr_Tfo = 59.1 and Kr_PM = 63.1 can be calculated. We choose
Kp = 0.35 and Kr = 63. With these parameters, the compensated loop gain TD is
depicted, as shown Fig. 8.10c, from which it can be measured that Tfo = 73.7 dB,
PM = 45°, GM1 = − 6.4 dB, and GM2 = 3.2 dB. Clearly, all the expected
requirements are achieved.
8.7.2 Design Example Without Damping
As stated before, to guarantee the system stability without damping, the LCL filter
resonance frequency is required to be higher than fs/6. So, filter III is used for the
following design. The specified requirements are Tfo > 73 dB, GM2 3 dB, and
PM > 45°. According to (8.32), (8.38), and (8.39), the satisfactory region of Kr and
fc can be obtained, as shown with the shaded area in Fig. 8.11.
To ensure a sufficient gain margin, a higher crossover frequency should be
selected. According to Fig. 8.11, fc = 1.1 kHz, corresponding to the constraint
boundary of GM2 = 3 dB, is selected, and then, Kr = 75 at point A is chosen.
Substituting fc = 1.1 kHz into (8.26), we have Kp = 0.27. Figure 8.12 shows the
Bode diagrams of the uncompensated and compensated loop gains, from which,
fc = 1.1 kHz, PM = 46°, Tfo = 75.2 dB, and GM2 = 3.7 dB can be measured,
which satisfies the specifications. Compared to Fig. 8.10c, the phase margin and the
gain at the fundamental frequency are improved, at the cost of a little reduced
crossover frequency.
Fig. 8.11 Satisfactory region 100

constrained by GM2, PM, and Constrained
Tfo by PM = 45°
75 A
Kr
50 Constrained
by Tfo = 73dB
25
Constrained
by GM2 = 3dB
0
500 1000 1500 2000 2500
fc (Hz)

loop gains without damping
|ATD_nodamp| (dB)
50
0
Uncompensated TD_nodamp(s)
Compensated TD_nodamp(s)
−50
0
Ang(TD_nodamp) (º)
−180
−360
fc: 1.1 kHz; Tfo: 75.2 dB;
GM2: dB; PM: 46º.
−540
10 fo 102 103 fc fs/6 fr 104
Frequency (Hz)
A 6-kW single-phase LCL-type grid-connected inverter prototype has been fabri-

cated and tested to validate the theoretical analysis and the designed controller
parameters. The specifications of the prototype are listed in Table 8.1, and the
photograph of the prototype has been shown in Fig. 5.15 in Chap 5.
8.8.1 Experimental Validation for the Case

with Capacitor-Current-Feedback Active-Damping
The experimental waveforms of the grid-connected inverter with filters I, II, and III
are shown in Figs. 8.13, 8.14, and 8.15, respectively. Note that the
capacitor-current-feedback active-damping is adopted here. In these figures, the left
figures show the steady-state waveform at full load, and the right ones show the
transient response when the grid current reference step changes between full load
and half load. Table 8.2 shows the measured power factor, RMS value of grid
current, current overshoot, and settling time. It can be seen that the measured power
factors are all larger than 0.995. Since the full-load grid current reference is
27.27 A, the steady-state errors are all less than 1%, which satisfy the design
expectation. As the grid current reference steps from half load to full load, the
current overshoot with filter II is larger than that with the other two filters; the
corresponding settling time is also longer than that with the other two filters. These
results verify that the system dynamic performance is deteriorated when the reso-
nance frequency of LCL filter falls in the forbidden region, which is well in
agreement with the analysis in Sect. 8.5.1.
vg: [100 V/div] vg: [100 V/div] i2: [20 A/div]

i2: [20 A/div]
Time: [5 ms/div] PF=0.998 Time: [10 ms/div] %=37%
(a) Full-load steady state (b) Dynamic response
Fig. 8.13 Experimental waveform of the prototype with Filter I. a Full-load steady state.
b Dynamic response

i2: [20 A/div]
Fig. 8.14 Experimental waveform of the prototype with Filter II. a Full-load steady state.
b Dynamic response

i2: [20 A/div]
Fig. 8.15 Experimental waveform of the prototype with Filter III. a Full-load steady state.
b Dynamic response
Table 8.2 Prototype parameter of single-phase LCL filtered grid connected inverter
Power RMS value of grid Overshoot at command Settling time
factor current (A) step (%) (ms)
Filter I 0.998 27.07 37 1
Filter 0.998 27.18 78 5
II
Filter 0.997 27.09 44 1
III
vg: [100 V/div] vg: [100 V/div]

i2: [20 A/div] i2: [20 A/div]
Time: [5 ms/div] Time: [5 ms/div]
(a) Filter I (b) Filter III
Fig. 8.16 Experimental waveform of prototype in two critical stable cases. a Filter I. b Filter III
Figure 8.16a, b shows the experimental waveforms with filters I and III,
respectively. For filter I, fc = 1.125 kHz and Hi1 = 0.062, which correspond to
point B in Fig. 8.9a. It can be calculated from (8.36) that GM2 = 0 dB. For filter III,
fc = 1.25 kHz and Hi1 = 0.04, which corresponds to point B in Fig. 8.9b. It can be
calculated from (8.27) that GM1 = 0 dB. As shown in Fig. 8.16, large oscillations
occur in the measured grid current. Note that the oscillations do not divergent due to
the parasitic resistors in the LCL filter.
The experimental results shown in Figs. 8.13, 8.14, 8.15, and 8.16 indicate that
the forbidden region of kfr can guide the design of the LCL filter. If the designed LCL
filter resonance frequency falls in the forbidden region, the filter parameter should be
adjusted (e.g., modify the capacitance of the filter capacitor). Moreover, the above
experimental results indicate that the satisfactory region presented in this chapter is a
convenient and intuitive interface to guide the design of the controller parameters,
from which the proper controller parameters can be selected, guaranteeing a low
steady-state error, sufficient stability margins, and good dynamic response.
8.8.2 Experimental Validation Without Damping
Figure 8.17 shows the experimental waveforms of the grid-connected inverter with
filter III and without damping. The steady-state waveforms at full load are shown in

i2: [20 A/div]
Fig. 8.17 Experimental waveform of the prototype with Filter III and without damping.
a Full-load steady state. b Dynamic response
Fig. 8.17a, the measured power factor is 0.998, RMS value of grid current is
27.18 A, and the current amplitude error is 0.4%, which satisfies the design
expectation. Figure 8.17b shows the dynamic response when the grid current ref-
erence steps between half load and full load, the overshoot is about 40% and the
settling time is about 1 ms. It can be seen that the steady-state and dynamic per-
formances of the system are very close to the system with
capacitor-current-feedback active-damping, as shown in Fig. 8.15.
The experimental results indicate that when fr > fs/6, the system without
damping is stable, and good steady-state and dynamic responses can be also
achieved.
8.9 Comparison of System Performance with Three

Control Methods
The analog-controlled LCL-type grid-connected inverter with

capacitor-current-feedback active-damping is analyzed in Chap. 5. The digitally
controlled LCL-type grid-connected inverter with capacitor-current-feedback
active-damping and without damping are analyzed in Chap. 8. The design results
for the case with filter III with the three control methods are shown in Table 8.3,
from which, it can be concluded that:
1. Compared with analog control, digital control introduces 1.5 times sampling
period delay. This decreases the system phase margin, and the crossover fre-
quency and loop gain at the fundamental frequency are also reduced. As a result,
the steady-state and dynamic performances with digital control are not good as
those with the analog control.
2. When digital control is adopted, the LCL filter resonance damping can be
removed if fr > fs/6. Accordingly, both the phase margin and loop gain at the
fundamental frequency increase, whereas the crossover frequency decreases.
8.10 Summary 195
Table 8.3 Controller parameters design results for Filter III with different control methods
Analog control with Digital control with Digital
capacitor-current-feedback capacitor-current-feedback control
active-damping active-damping without
damping
Cutoff 2.05 1.3 1.1
frequency fc
(kHz)
Phase margin 48.1 45 46
PM (°)
Gain margin 4.29 −6.4(GM1) 3.7
GM (dB) 3.2(GM2)
Fundamental 88.4 73.7 75.2
magnitude
gain Tfo (dB)
8.10 Summary
In this chapter, the design considerations for the digitally controlled LCL-type
grid-connected inverter are presented. It reveals that the digital control produces
control delay, including the computation delay of one sampling period and PWM
delay of a half sampling period. The effect of control delay on the
capacitor-current-feedback active-damping is analyzed, and it is pointed out that the
capacitor-current-feedback active-damping is equivalent to a frequency-dependent
virtual impedance rather than a pure virtual resistor in parallel with the filter
capacitor. The virtual impedance can be represented in the form of parallel con-
nection of a virtual reactor and a virtual resistor. The reactor behaves as a virtual
inductor in the range (0, fs/3) and a virtual capacitor in the range (fs/3, fs/2), which
results that the loop gain resonance frequency deviates from the LCL filter reso-
nance frequency. The virtual resistor is positive in the range (0, fs/6) and negative in
the range (fs/6, fs/2). Two right-half-plane (RHP) poles may be in the loop gain
when the virtual resistor is negative at the resonance frequency of the loop gain.
The stability constraint conditions for digitally controlled LCL-type
grid-connected inverter are investigated. The forbidden region of the LCL filter
resonance frequency is presented to ensure the system stability, which is helpful to
guide the design of LCL filter. The constraints of the controller parameters are
studied and a step-by-step controller parameters design procedure is presented.
Given the expected steady-state error of the grid current, the stability margins, a
satisfactory region can be obtained, from which the proper controller parameters
can be selected.
It is revealed that when the LCL filter resonance frequency is higher than
one-sixth of the sampling frequency, and the digitally controlled LCL-type
grid-connected inverter can be stable without damping. The system performance
without damping is analyzed, and it is pointed out that with the same specified gain
margins, the maximum crossover frequency without damping is lower than that
with capacitor-current-feedback active-damping.
A 6-kW single-phase LCL-type grid-connected inverter prototype is built and
tested in the laboratory, and the experimental results are provided to verify the
theoretical analysis.
References
1. Bao, C.: Design of current regulator and capacitor-current-feedback active damping for LCL-
type grid-connected inverter. M.S. thesis, Huazhong University of Science and Technology,
Wuhan, China (2013) (in Chinese)
1398–1409 (2006)
3. Figueres, E., Garcera, G., Sandia, J., Gonzalez-Espin, F., Rubio, J.C.: Sensitivity study of the
dynamics of three-phase photovoltaic inverters with an LCL grid filter. IEEE Trans. Ind.
Electron. 56(3), 706–717 (2009)
Practice. IEEE Press & Wiley, New York (2003)
5. Texas Instruments.: TMS320F2812 Digital Signal Processor [Online]. Available: http://www.
ti.com/lit/ds/symlink/tms320f2812.pdf (2012)
6. Buso, S., Mattavelli, P.: Digital Control in Power Electronics. Morgan & Claypool Publishers,
Seattle (2006)
7. Dannehl, J., Fuchs, F.W., Thøgersen, P.: PI state space current control of grid-connected
PWM converters with LCL filters. IEEE Trans. Power Electron. 25(9), 2320–2330 (2010)
8. Xi, A.: Computer Control Systems. Higher Education Press, Beijing (2004)
9. Goodwin, G.C., Graebe, S.F., Salgado, M.E.: Control System Design. Prentice-Hall, Upper
Saddle River (2000)
10. Agorreta, J.L., Borrega, M., López, J., Marroyo, L.: Modeling and control of N-paralleled
grid-connected inverters with LCL filter coupled due to grid impedance in PV plants. IEEE
11. Driels, M.: Linear Control Systems Engineering. McGraw-Hill, New York (1996)
12. Parker, S.G., McGrath, B.P., Holmes, D.G.: Regions of active damping control for LCL
filters. IEEE Trans. Ind. Appl. 50(1), 424–432 (2014)
13. Tang, Y., Loh, P.C., Wang, P., Choo, F.H., Gao, F., Blaabjerg, F.: Generalized design of high
performance shunt active power filter with output LCL filter. IEEE Trans. Ind. Electron. 59
(3), 1443–1452 (2012)
14. Holmes, D., Lipo, T., McGrath, B., Kong, W.Y.: Optimized design of stationary frame three
phase ac current regulator. IEEE Trans. Power Electron. 24(11), 2417–2426 (2009)
Chapter 9
Reduction of Computation Delay
for Improving Stability and Control
Performance of LCL-Type
Abstract As illustrated in Chap. 8, in the digitally controlled LCL-type

grid-connected inverters, proportional feedback of the capacitor current is equiva-
lent to a frequency-dependent virtual impedance connected in parallel with the filter
capacitor due to the control delay including the computation and pulse-width
modulation (PWM) delays. This virtual impedance leads to the change of the LCL
filter resonance frequency. At the frequencies higher than one-sixth of the sampling
frequency (fs/6), the virtual impedance contains a negative resistor component. So,
if the actual resonance frequency is higher than fs/6, a pair of open-loop
right-half-plane (RHP) poles are generated. As a result, the LCL-type
grid-connected inverter is easier to be unstable if the resonance frequency is moved
closer to fs/6 due to the variation of grid impedance. Meanwhile, the computation
and PWM delays also reduce the control bandwidth greatly and thus impose a
severe limitation on the low-frequency gains. Therefore, it is desirable to reduce the
control delay so as to improve the stability and the control performance of the
grid-connected inverter. In this chapter, the influence of the control delay on the
LCL-type grid-connected inverter is firstly analyzed. Then, the real-time sampling
method [1] and real-time computation method with dual sampling modes [2] are
proposed to reduce or even remove the computation delay. Finally, the experi-
mental results from a 6-kW prototype verify the effectiveness of the proposed
methods.

Keywords Grid-connected inverter LCL filter Active damping Digital con-

trol Open-loop unstable poles Grid impedance
As illustrated in Chap. 8, in the digitally controlled LCL-type grid-connected

inverters, proportional feedback of the capacitor current is equivalent to a
frequency-dependent virtual impedance connected in parallel with the filter
capacitor due to the control delay including the computation and pulse-width
modulation (PWM) delays. This virtual impedance leads to the change of the LCL
filter resonance frequency. At the frequencies higher than one-sixth of the sampling
frequency (fs/6), the virtual impedance contains a negative resistor component. So,
198 9 Reduction of Computation Delay for Improving Stability …
if the actual resonance frequency is higher than fs/6, a pair of open-loop

right-half-plane (RHP) poles are generated. As a result, the LCL-type
grid-connected inverter is easier to be unstable if the resonance frequency is moved
closer to fs/6 due to the variation of grid impedance. Meanwhile, the computation
and PWM delays also reduce the control bandwidth greatly and thus impose a
severe limitation on the low-frequency gains. Therefore, it is desirable to reduce the
control delay so as to improve the stability and the control performance of the
grid-connected inverter. In this chapter, the influence of the control delay on the
LCL-type grid-connected inverter is firstly analyzed. Then, the real-time sampling
method [1] and real-time computation method with dual sampling modes [2] are
proposed to reduce or even remove the computation delay. Finally, the experi-
mental results from a 6-kW prototype verify the effectiveness of the proposed
methods.
9.1 Effects of Computation and PWM Delays
9.1.1 Modeling the Digitally Controlled LCL-Type

Figure 9.1 shows a generic structure of the LCL filtered grid-connected inverter
with digital control. The LCL filter consists of an inverter-side inductor L1, a filter
capacitor C, and a grid-side inductor L2. Generally, the grid impedance at the point
of common coupling (PCC) mainly consists of inductance and resistance [3]. Since
the grid resistance offers some damping and helps to stabilize the system, a pure
inductance Lg is considered here to draw the worse case. To make grid current i2
synchronized with the grid voltage, the grid current reference i*2 is generated using
the grid voltage phase angle h detected by a phase-locked loop (PLL) and the given
current amplitude command I*. Moreover, the capacitor current iC is fed back to
damp the LCL filter resonance. Hi1 and Hi2 are the sensor gains of the capacitor
current iC and the grid current i2, respectively. Gi(z) is the current regulator.
As previously mentioned, the digitally controlled system contains computation
and PWM delays [4, 5]. The delay mechanism is shown in Fig. 9.2, where the
sine-triangle, asymmetrical regular sampled PWM is employed, the sampling fre-
quency fs is twice the switching frequency fsw, and Ts is the sampling period. In
general, i2 and iC are sampled at the beginning and in the middle of the switching
period, and the sampled currents are shown with the dashed lines in the figure. Such
sampling scheme is called the synchronous sampling, and it has the advantage of
obtaining the average current per switching period (the fundamental component)
without requiring low-pass filtering [6]. At the time step k, the sampled currents are
used to calculate the PWM reference. In order to avoid the unwanted intermediate
PWM transitions, the PWM reference is not updated until the time step k + 1 [7].
9.1 Effects of Computation and PWM Delays 199
Fig. 9.1 Digitally controlled

LCL-type grid-connected S1 S3 L1 L2 Lg
vC PCC
inverter with + i1 i2 +
capacitor-current-feedback C iC
Vin vinv vpcc vg
active-damping
– –
S2 S4
Sinusoidal PWM Hi1 Hi2 PLL

cosθ
vM – + – + i2*
Gi(z) I*
DSP Controller
Fig. 9.2 Inherent

computation and PWM delays i2 Actual Current
in the digital PWM
Sampled Current
0 t
Sampled Current Actual Current
iC
0 t
vM
Reference
0 t
Carrier
t
Ts Td1 Td2
k k+1 k+2 k+3 k+4
Note: Synchronous sampling instants for i2 and iC;
Sampling with reduced computation delay for i2;
Sampling with reduced computation delay for iC;
PWM reference update instant.
Thus, a computation delay of Ts is introduced into both the grid current loop and the
capacitor-current-feedback active-damping.
In fact, by shifting the sampling instant toward the PWM reference update
instant, the computation delay can be reduced. As shown in Fig. 9.2, the capacitor
current iC and the grid current i2 are sampled at the time instants with time durations
of Td1 and Td2 before the PWM reference update instant, respectively, and the
sampled currents are shown with the dot-dashed lines. Thus, the computation delays
in the capacitor-current-feedback active-damping and the grid current control loop
can be reduced to Td1 and Td2, respectively. For convenience of illustration, it is
defined that Td1 = k1Ts (0 < k1 1) and Td2 = k2Ts (0 < k2 1). Obviously,
k1 = k2 = 1 for the synchronous sampling case.
After being updated, the PWM reference is held on and compared to the tri-
angular carrier to generate the duty cycle. This behavior can be modeled by the
zero-order hold (ZOH), which is expressed as [8]
1 esTs
G h ðsÞ ¼ Ts e0:5sTs ð9:1Þ
s
From (9.1), it can be known that the PWM delay is half sampling period.
Considering the computation and PWM delays, the averaged switch model
(ASM) of the digitally controlled LCL-type grid-connected inverter is given in
Fig. 9.3a, where KPWM is the transfer function of the PWM inverter, expressed as
KPWM = Vin/Vtri, Vin is the input voltage, and Vtri is the amplitude of the triangular
carrier. Meanwhile, the sampler is represented by 1/Ts [9]. As observed from
Fig. 9.3a, 1/Ts is included in the forward path of i*2(s) and the feedback paths of i2
and iC, so 1/Ts can be merged into the input port of Gh(s), as shown in Fig. 9.3b.
The ASM model shown in Fig. 9.3b can be simplified through a series of
equivalent transformations, as shown in Fig. 9.4, where the dash lines represent the
original status, and the bold solid lines represent the destination status. First,
replacing the feedback signal vC(s) with iC(s) and relocating its feedback node to the
input of the transfer function 1/Ts, an equivalent block diagram is obtained, as
(a)
vg(s)
iC(s)
i2*(s) 1 + + +
–
1 + 1 +
–
1 i2(s)
Ts Gi(s) e −sλ2Ts
Gh(s) KPWM sL1 sC s(L2+Lg)
– – vinv(s) – vC(s)
1
e −sλ1Ts
Ts Hi1
1 Hi2
Ts
(b)
vg(s)
iC(s)
i2*(s) + + 1 +
–
1 + 1 +
–
1 i2(s)
Gi(s) e −sλ2Ts
Ts Gh(s) KPWM sL1 sC s(L2+Lg)
– – vinv(s) – vC(s)
e−sλ T
1 s
Hi1
Hi2
Fig. 9.3 ASM of the digitally controlled LCL-type grid-connected inverter with
capacitor-current-feedback active-damping
Ts
(a) sCKPWMGh(s)
× × vg(s)
i2*(s) + +
–
1 +
–
1 + 1 +
–
1 i2(s)
Gi(s) e
−sλ2Ts
– – –
e−sλ T
1 s
Hi1
Hi2
Ts
sCKPWMGh(s) +Hi1e
−sλ Ts
(b) 1
vg(s)
i2*(s) + +
–
1 + 1 + 1 +
–
1 i2(s)
Gi(s) e
−sλ2Ts
– – –
sL1Ts ×
KPWMGh(s)
Hi2
(c) vg(s)
i2*(s) + +
–
1 i2(s) (d) vg(s)
Gx1(s) s(L2+Lg)
– – i2*(s) + +
– i2(s)
Gx1(s) Gx2(s)
–
Hx1(s)
Hi2 Hi2
Fig. 9.4 Equivalent transformations of control block diagram
shown in Fig. 9.4a. Second, by combining the two feedback functions of iC(s) and
moving the inner feedback node of i2(s) from the output of the transfer function
1/sL1 to the input of the transfer function 1/Ts, the equivalent block diagram is
obtained, as shown in Fig. 9.4b. Third, moving the inner feedback node of
i2(s) from the input of the transfer function 1/Ts to the output of the transfer function
1/sC and then simplifying the forward path from the transfer function Gi(s) to the
transfer function 1/sC, results in the equivalent block diagram as shown in
Fig. 9.4c, where
KPWM Gi ðsÞGd2 ðsÞ

Gx1 ðsÞ ¼ ð9:2aÞ
s L1 C þ sCHi1 KPWM Gd1 ðsÞ þ 1
2
sL1
Hx1 ðsÞ ¼ ð9:2bÞ
s2 L1 C þ sCHi1 KPWM Gd1 ðsÞ þ 1
where Gd1(s) and Gd2(s) are the control delays in the capacitor-current-feedback
active-damping and the grid current control loop, respectively, expressed as
1
Gdj ðsÞ ¼ eskj Ts Gh ðsÞ esðkj þ 0:5ÞTs 0 kj 1; j ¼ 1; 2 ð9:3Þ
Ts
Furthermore, Fig. 9.4c can be simplified to Fig. 9.4d, where Gx2(s) is the
open-loop output admittance of the LCL-type grid-connected inverter, which can be
expressed as
s2 L1 C þ sCHi1 KPWM Gd1 ðsÞ þ 1

Gx2 ðsÞ ¼
s3 L1 L2 þ Lg C þ s2 L2 þ Lg CHi1 KPWM Gd1 ðsÞ þ s L1 þ L2 þ Lg
ð9:4Þ
From Fig. 9.4d, the loop gain can be obtained as
TD ðsÞ ¼ Gx1 ðsÞGx2 ðsÞHi2

Hi2 KPWM Gi ðsÞGd2 ðsÞ
¼
s3 L1 L2 þ Lg C þ s2 L2 þ Lg CHi1 KPWM Gd1 ðsÞ þ s L1 þ L2 þ Lg
ð9:5Þ
Thus, the grid current i2(s) can be expressed as
1 T D ðsÞ Gx2 ðsÞ

i2 ðsÞ ¼ i ðsÞ vg ðsÞ ð9:6Þ
Hi2 1 þ TD ðsÞ 2 1 þ TD ð s Þ
Compared with the loop gain TA(s) with analog control presented in Chap. 5, the
loop gain TD(s) with digital control is different in two aspects: (1) additional delay
item Gd1(s) is introduced in the denominator, which will change the characteristic of
the capacitor-current-feedback active-damping, leading to the stability problem;
(2) additional delay item Gd2(s) is introduced in the numerator, which may intro-
duce negative phase angle and thus reduce the control bandwidth.
9.1.2 Improvement of Damping Performance

with Reduced Computation Delay
Referring to Fig. 9.3b, by replacing the feedback of the capacitor current iC(s) with
the capacitor voltage vC(s) and moving its feedback node from the input of the
transfer function 1/Ts to the output of 1/sL1, an equivalent block diagram is
obtained, as shown in Fig. 9.5. So the capacitor-current-feedback active-damping is
equivalent to a virtual impedance Zeq connected in parallel with the filter capacitor.
And Zeq is expressed as
vg(s)
i2*(s) + + 1 +
–
1 +
–
1 +
–
1 i2(s)
Gi(s) e
−sλ2Ts
– – –
× ×
1
e−sλ T
1 s
Hi1 Zeq(s)
Hi2
Fig. 9.5 Equivalent virtual impedance of the capacitor-current-feedback active-damping
L1
Zeq ðsÞ ¼ ¼ RA esðk1 þ 0:5ÞTs ð9:7Þ
Hi1 KPWM CGd1 ðsÞ
where RA = L1/(Hi1KPWMC) is the equivalent virtual resistor of the

capacitor-current-feedback active-damping without delays.
Zeq can be represented in form of parallel connection of a resistor Req and a
reactor Xeq, where Req and Xeq can be given by
RA
Req ðxÞ ¼ ð9:8aÞ
cos½ðk1 þ 0:5ÞxTs
RA
Xeq ðxÞ ¼ ð9:8bÞ
sin½ðk1 þ 0:5ÞxTs
As seen in (9.8a, 9.8b), both Req and Xeq are frequency dependent. The fre-
quency boundary of Req to be positive and negative is denoted by fRb, and the
frequency boundary of Xeq to be inductive and capacitive is denoted by fXb.
According to (9.8a, 9.8b), the expressions of fRb and fXb can be derived as
fs
fRb ¼ ð9:9aÞ
4ðk1 þ 0:5Þ
fs
fXb ¼ ð9:9bÞ
2ðk1 þ 0:5Þ
Obviously, fXb = 2fRb. For the synchronous sampling case (k1 = 1), fRb = fs/6,
fXb = fs/3, and the curves of Req and Xeq as the function of frequency are shown with
the solid lines in Fig. 9.6. As pointed out in Chap. 8, the virtual reactor Xeq changes
the resonance frequency. For the synchronous sampling case, if the actual reso-
nance frequency fr0 is higher than fs/6, where the virtual resistor Req is negative, a
pair of open-loop RHP poles will be generated. As a result, stringent gain margin
requirements at the LCL filter resonance frequency fr and fs/6 must be satisfied to
ensure system stability. However, as fr moves closer to fs/6, the gain margin
requirements are hardly to be satisfied, which makes the grid-connected inverter apt
Fig. 9.6 Curves of Req and

Xeq as the function of
frequency RA
Req (Ω)
0
−RA
RA
Xeq (Ω)
0
−RA λ1=1
λ1=0.5
λ1=0
fs/6 fs/4 fs/3 fs/2
Frequency
to be unstable. Especially for fr = fs/6, the gain margin requirements cannot be

satisfied, thus the system can be hardly stable.
In order to improve system stability when fr approaches fs/6, the open-loop RHP
poles need to be removed. For this purpose, a positive Req at the frequencies lower
than fr should be preserved, which means that fRb should be higher than fr.
According to (9.9a, 9.9b), both fRb and fXb increase with the decrease of k1.
Therefore, a smaller k1 would be desirable for a higher LCL filter resonance fre-
quency. Particularly, if k1 = 0, then fRb = fs/2, a positive Req will be obtained below
the Nyquist frequency (i.e., fs/2), as shown in Fig. 9.6. This is the ideal case, in
which the open-loop RHP poles can be removed for fr < fs/2. Obviously, this ideal
case can be approached by minimizing the value of k1. While in practice, k1 can be
chosen according to the specific fr. Taking the parameters given in Table 9.1 (see
Sect. 9.2.2) as an example, the resonance frequency is fr = 4.6 kHz, which is close
to fs/4 (i.e., 5 kHz). So, it is expected to make fRb fs/4. As seen in (9.9a, 9.9b),
this can be achieved by choosing k1 0.5. Taking as an instance, k1 = 0.5 is
illustrated to show how the damping performance is improved by reducing the
computation delay.
Table 9.1 Parameters of the prototype

Grid voltage (RMS) Vg 220 V Grid-side inductor L2 150 lH
Fundamental frequency fo 50 Hz Resonance frequency fr 4.6 kHz
Switching frequency fsw 10 kHz Sampling frequency fs 20 kHz
Amplitude of the Vtri 4.58 V Grid current feedback Hi2 0.15
triangular carrier coefficient
Recalling (9.7) and (9.9a, 9.9b), for k1 = 0.5, Zeq can be rewritten as RA esTs , and
fRb = fs/4, fXb = fs/2. The curves of Req and Xeq as the function of frequency are
shown with the dashed lines in Fig. 9.6. Similar to the case of fr < fs/6 for k1 = 1, in
the case of fr < fs/4 for k1 = 0.5, a higher fr0 will be yielded due to the inductive Xeq.
And fr0 might step over fs/4 if Hi1 is sufficiently large. Recalling the derivation of
Hi1C given in Sect.8.3.3, in this case, the value of Hi1 yielding fr0 = fs/4, Hi1m, can be
derived as
xr L1 cos xr Ts
Hi1m ¼ ð9:10Þ
KPWM sinð0:5xr Ts Þ
If 0 < Hi1 < Hi1m, then fr0 < fs/4, Req is positive at fr0 , no open-loop RHP pole
exists, and the phase plot crosses over −180° only once. According to the Nyquist
stability criterion [10], as long as the gain margin at the −180° crossover frequency
is greater than 0 dB, the system will be stable. Apparently, these features are
exactly the same as the case of fr0 < fs/6 for k1 = 1. Therefore, by removing the
open-loop RHP poles, the stringent gain margin requirements no longer exist, and
the grid-connected inverter is easier to be stable.
9.1.3 Improvement of Control Performance

with Reduced Computation Delay
As mentioned previously, the damping performance can be improved by reducing

the computation delay time k1Ts in the capacitor-current-feedback active damping.
In fact, the control performance can also be improved by reducing the computation
delay time k2Ts in the grid current loop. For simplicity, k1 = 0 is assumed in the
following discussions.
According to (9.5), the control delay in grid current loop Gd2(s) introduces the
phase lag to TD(s). Recalling (9.3), the phase angle generated by Gd2(s) is expressed
as
\Gd2 ðj2p f Þ ¼ 360 ðk2 þ 0:5ÞTs f ð9:11Þ
As seen in (9.11), the frequency where Gd2(s) introduces a 90º phase lag is
derived as
fs
fx ¼ ð9:12Þ
4ðk2 þ 0:5Þ
When fr < fx, the phase plot of TD(s) always crosses over −180° at fr, so the
resonance peak at fr should be damped below 0 dB to ensure system stability. When
fr > fx, the phase lag introduced by Gd2(s) makes the phase plot of TD(s) crossover
−180° at fx in advance. Hence, as long as the gain margin at fx is greater than 0 dB,
the system will be stable even without damping the resonance peak at fr [11]. As
seen in (9.12), fx increases with the decrease of k2. Thus, the expression of the gain
margin may change when k2 varies.
Taking the PR regulator as an example, the satisfactory region of Kp, Kr, and Hi1
will be derived according to the given specifications of the steady-state error, phase
margin, and gain margin. For simplicity, here it is assumed that the grid-connected
inverter is operated under the unity power factor condition with Lg = 0.
According to the analysis in Sect. 5.5.2, when the grid-connected inverter only
outputs the active power, the grid current reference i*2 is in phase with the grid
voltage vg, i.e., h = 0°. As shown in Fig. 5.9a, if h = 0°, the phase error in the grid
current is zero, and the amplitude error of the grid current EA can be expressed as
Hi2 I22
EA ¼ ð9:13Þ
I2
At the fundamental frequency fo, the PR regulator can be simplified as

Gi(j2pfo) = Kp + Kr. Substituting Gi(j2pfo) into (5.11) yields as
Vg
I22 ð9:14Þ
Hi2 KPWM Kp þ Kr
Substituting (9.14) into (9.13), EA can be rewritten as
Vg
EA ð9:15Þ
I2 KPWM Kp þ Kr
Equation (5.9) in Chap. 5 has established the relationship between Kp and the
crossover frequency fc, which is rewritten here for better illustration, i.e.,
2p fc ðL1 þ L2 Þ
Kp ð9:16Þ
Hi2 KPWM
Substituting (9.16) into (9.15), the boundary of Kr with respect to fc under the
constraint EA can be derived as
Vg 2p fc ðL1 þ L2 Þ
Kr EA ðfc Þ ¼ ð9:17Þ
EA I2 KPWM Hi2 KPWM
Substituting s = j2pfc into (9.5), the phase margin PM can be expressed as
p Kr xi
PM ¼ ð2k2 þ 1Þp fc Ts arctan
2 p fc Kp
Hi1 KPWM fc cosðp fc Ts Þ
arctan 2 ð9:18Þ
2p fr fc2 L1 þ Hi1 KPWM fc sinðp fc Ts Þ
As mentioned above, the phase plot of TD(s) will cross over −180° only once at
the smaller frequency of fx and fr. So, the gain margin GM is expressed as

20 lgjTD ðj2p fr Þj ðfr fx Þ
GM ¼ ð9:19Þ
20 lgjTD ðj2p fx Þj ðfr [ fx Þ
where jTD ðj2pfr Þj and jTD ðj2pfx Þj can be derived according to (9.5) and expressed
as
Hi2 Kp L1
jTD ðj2p fr Þj ð9:20aÞ
Hi1 ðL1 þ L2 Þ
Hi2 KPWM Kp
jTD ðj2p fx Þj ð9:20bÞ
4p2 L2 C Hi1 KPWM fx2 þ 2p Ll fx fr2 fx2
Substituting (9.16) and (9.20a) into (9.19), the boundary of Hi1 with respect to fc
under the constraint GM can be derived as
8 2p fc L1 GM
< KPWM 10 20 ðf r f x Þ
2
Hi1 GM ðfc Þ fx2 fr2 ð9:21Þ

: K2p L1 10 20
GM
PWM
fr
fx fc þ fx ðf r [ f x Þ
Since Hi1 should be selected to meet both the PM and GM constraints, Hi1 in
(9.18) satisfies Hi1 = Hi1_GM. Substituting (9.16) and (9.21) into (9.18), the
boundary of Kr with respect to fc under both the PM and GM constraints can be
derived as
2p2 fc2 ðL1 þ L2 Þ

Kr SM ðfc Þ ¼
xi Hi2 KPWM

2p L1 fr2 fc2 cos½PM þ ð2k2 þ 1Þp fc Ts KPWM Hi1 GM ðfc Þ sinðPM þ 2k2 p fc Ts Þfc

2p L1 fr2 fc2 sin½PM þ ð2k2 þ 1Þp fc Ts þ KPWM Hi1 GM ðfc Þ cosðPM þ 2k2 p fc Ts Þfc
ð9:22Þ
Substituting the parameters listed in Table 9.1 into (9.17) and (9.22), the satis-
factory regions of Kr and fc for different k2 are drawn in Fig. 9.7. As seen, the
satisfactory region becomes larger as k2 reduces, which allows the use of larger Kr
and fc to improve both the steady-state and dynamic performance.
Fig. 9.7 Satisfactory regions 400

of Kr and fc constrained by
EA, PM, and GM A
300
λ 2 =0
200
Kr
λ 2 =0.5 Constrainted
λ 2 =1 by E A
100 B
Constrainted
by PM and GM
0
0 1000 2000 3000
fc (Hz)
9.2 Real-Time Sampling Method
As analyzed above, it is desirable to minimize the control delay to improve the

stability and control performance of the LCL-type grid-connected inverter.
Basically, the control delay can be compensated either with a lead compensator [12]
or with a state observer [13]. However, the lead compensator will lead to the
amplification of high-frequency noises, and the state observer calls for an accurate
modeling of the system. In practice, the inaccuracy of the model caused by the
variation of circuit parameters can lead to the prediction error, which will degrade
the control performance or even result in system instability [14].
Different from the delay compensation method, this section focuses on the direct
reduction of the control delay. Obviously, the control delay can be reduced by
increasing the sampling frequency. Usually, the sampling frequency is equal to or
twice of the switching frequency. If the sampling frequency is further increased,
i.e., the multiple-sampling method, the sampled signal may be distorted by the
switching ripple. Given the same sampling frequency, the PWM delay caused by
the ZOH effect is definitely half sampling period, and it can not be reduced.
However, the computation delay, which is the time duration between the sampling
instant and the PWM reference update instant, can be reduced by shifting the
sampling instant properly toward the PWM reference update instant. Such sampling
scheme is defined as the real-time sampling to differ from the synchronous
sampling.
9.2.1 Sampling-Induced Aliasing of the Capacitor Current
As shown in Fig. 9.2, with the real-time sampling scheme, the capacitor current iC
and the grid current i2 are sampled at the time instants with time durations of Td1
9.2 Real-Time Sampling Method 209
Fig. 9.8 Simulation results 6

of the sampled capacitor
3
current
iC (A)
0
−3
−6
6 λ1=1
λ1=0.1
3 λ1=0.5
iCs (A)
0
−3
Time:[5 ms/div]
−6
(a) Sampled capacitor current
4
iCs harmonics (p.u.)
3 1st
2 3rd
1 5th
7th
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
λ1
(b) Harmonic analysis
(i.e., k1Ts) and Td2 (i.e., k2Ts) before the PWM reference update instant, respec-
tively, and the sampled currents are shown with the dash-dotted lines. As seen,
quite different sampling results are obtained depending on the sampling instant.
Note that the grid current is ripple-free, the modification of the sampling instant has
few influence on the accuracy of the sampling result. However, since the capacitor
current contains abundant switching ripple, aliasing might occur if the sampling
instant is not properly located.
Figure 9.8a shows the simulation results of the sampled capacitor current, where
the fundamental frequency fo = 50 Hz, the switching frequency fsw = 10 kHz, and
the sampling frequency fs = 20 kHz. Different values of k1 in the range [0, 1] are
investigated individually with a step of 0.1. As seen, the sampled capacitor current
iCs varies significantly with the sampling instant. For the synchronous sampling
case, i.e., k1 = 1, since the sampling instant locates at the beginning and in the
middle of the switching period, the average value per switching period, i.e., the
fundamental capacitor current, with an amplitude of 1 A is acquired. Thus, aliasing
is avoided [4]. For the real-time sampling method, i.e., 0 < k1 < 1, not only the
fundamental component, but also the low-order harmonics (mainly 3rd, 5th, and
7th) appear in iCs, which means aliasing is introduced. Based on the Fourier
analysis, the fundamental and harmonic amplitudes with respect to the fundamental
capacitor current (i.e., 1 A) in iCs for different k1 are lined out in Fig. 9.8b. It can be
seen that when k1 = 0.5, iCs is nearly equal to the fundamental capacitor current,
and the harmonics are minimum. Otherwise, when k1 6¼ 0.5 in the range (0, 1), the
amplitude of the fundamental component in iCs is larger than its actual value, so the
sampling error is introduced. The low-order aliased harmonics may enter into the
control loop along with the feedback of the capacitor current and thus cause a
disturbance on the grid current. Fortunately, since the feedback node of the
capacitor current is located behind the current regulator Gi(s), as shown in
Fig. 9.3b, the undesirable disturbance on the grid current can be suppressed by
increasing the low-frequency gains of the current regulator.
Besides the sampling-induced aliasing, the switching noise is another important
issue in the capacitor current sampling. The switching noise is created during
switching transitions and coupled to the current sensors. In the synchronous sam-
pling case, the sampling takes place at the beginning and in the middle of a
switching period where no switching devices are turned on or off, and the switching
noise is almost avoided in the sampled capacitor current. In the real-time sampling
scheme, the capacitor current sampling instant might be shifted to the switching
points, thus the sampled capacitor current might be distorted by the switching noise.
To overcome this drawback, some techniques are adopted in practical implemen-
tation. First, skip any sampling during switching transitions. The switching tran-
sition instant can be estimated using the PWM reference value, and then the
capacitor current sampling can be adjusted properly away from this instant. Second,
install a low-pass filter between the current sensor and the A/D converter.
Considering that the frequency of switching noise is usually higher than 1 MHz
[15], a low-pass filter with a cutoff frequency around 100 kHz will be suitable.
9.2.2 Design Example
Table 9.1 gives the parameters of a 6-kW single-phase LCL-type grid-connected

inverter. The design example with real-time sampling method is discussed as fol-
lows. In order to examine the stability improvement with reduced computation
delay in the capacitor-current-feedback active-damping, only the capacitor current
employs the real-time sampling method, and the grid current still use the syn-
chronous sampling method, i.e., k2 = 1. A PR regulator is employed and the
controller parameters are properly designed with the assumption of Lg = 0. The
system stability is examined with Lg varying up to 10% per unit (PU), which
corresponds to a short-circuit ratio of 10 [3]. In this test system, 10% PU equals to
Lg = 2.6 mH.
When the synchronous sampling method is used for sampling the capacitor
current (i.e., k1 = 1), the controller parameters can be determined with the design
procedure presented in Sect. 8.5, given by Kp = 0.48, Kr = 65, and Hi1 = 0.025.
When the real-time sampling method is used for sampling the capacitor current, it is
necessary to let k1 0.5 to remove the open-loop RHP poles, based on the
analysis in Sect. 9.1.2. In practical application, the minimum value of k1 is limited
by the time required for the capacitor current sampling and the processing of active
damping. This time is related to the adopted A/D converter and digital signal
processor (DSP). Taking a 32-bit fix-point 150-MHz TI TMS320F2812 DSP as an
instance, the single-channel conversion time of the on-chip A/D converter is 0.2 ls.
The conversion result is subtracted from the output of the current regulator, and
then the PWM reference is obtained and updated to the compare units of DSP. The
time for these processing is measured as 0.6 ls. Thus, the overall time is 0.8 ls,
which means that the minimum value of k1 is about 0.02 for fs = 20 kHz. Here,
0.1 k1 0.5 is evaluated with a step of 0.1. Taking k1 = 0.5 for instance,
Hi1m = 0.042 can be calculated out from (9.10). To remove the open-loop RHP
poles, Hi1 < 0.042 is required. Therefore, Hi1 = 0.025 is appropriate for k1 = 0.5.
The Bode diagrams of the compensated loop gain for k1 = 1 and k1 = 0.5 are
shown in Fig. 9.9. It can be seen that the two magnitude plots almost coincide with
each other, while the phase plots show quite differences at the frequencies higher
than fs/6. Specifically, for k1 = 1, the phase plot crosses over −180° both at fr and
fs/6, and the corresponding gain margins are GM1 = − 9.13 dB and
GM2 = 4.12 dB; and for k1 = 0.5, the phase plot crosses over −180° only once at
the frequency near fs/6, and the corresponding gain margin is 4.28 dB. As seen, the
3 dB gain margin requirements are well satisfied in different cases.
Figure 9.10 shows the closed-loop pole maps with Lg varying up to 10% PU (the
pair of closed-loop poles introduced by the PR regulator are not displayed since
they vary a little). For k1 = 1, as shown in Fig. 9.10a, the resonant poles move
outside the unit circle for 180 lH < Lg < 750 lH, which corresponds to
2.7 kHz < fr < 3.5 kHz. This indicates that the system instability comes about
when fr moves close to fs/6 (3.3 kHz). For k1 = 0.5, as shown in Fig. 9.10b, the
resonant poles are well damped into the unit circle, and reasonable stability margins

the compensated loop gain
|TD (s)| (dB)
40
GM1
0
GM2
−40
0
−180 PM
∠TD (s) (°)
−360
λ1=1
λ1=0.5
−540
10 102 103 fc fs/6 fr 104
Frequency (Hz)
1.0 Lg=750μH 1.0 Lg=220μH
Lg=180μH
0.6 0.6
Lg=2.6mH(0.1PU) Lg=0.1PU
Imaginary Axis
Imaginary Axis
0.2 0.2
−0.2 −0.2
−0.6 −0.6
−1.0 −1.0
−1.0 −0.6 −0.2 0.2 0.6 1.0 −1.0 −0.6 −0.2 0.2 0.6 1.0
Real Axis Real Axis
(a) λ1 = 1 (b) λ1 = 0.5
Fig. 9.10 Closed-loop pole maps for different k1 with grid-impedance variations
are preserved even for Lg = 220 lH (i.e., fr = 3.3 kHz). Therefore, by reducing the
computation delay in the capacitor-current-feedback active-damping, the system
stability is substantially improved.
9.2.3 Experimental Verification
According to the parameters given in Table 9.1, a 6-kW prototype is built and
tested in the laboratory to verify the effectiveness of the proposed real-time sam-
pling method. In the experiments, a programmable ac source (Chroma 6590) is used
to simulate the grid voltage, and the grid impedance Lg is emulated by an external
inductor.
Figure 9.11 shows the experimental capacitor current waveform and the sampled
capacitor currents for k1 = 1, k1 = 0.5, and k1 = 0.1. As seen, the measured results
are in agreement with the simulation results shown in Fig. 9.8a. Moreover, the
switching noise is rarely observed in the sampled capacitor currents.
For Lg = 0, both the steady-state and transient responses are investigated for
k1 = 1 and 0.1 k1 0.5. Figure 9.12 shows the steady-state experimental
results under full load condition, and Fig. 9.13 shows the transient experimental
results when the grid current reference steps between half and full load, both for
k1 = 1 and k1 = 0.5. Table 9.2 shows the measured results in terms of fundamental
amplitude error EA, total harmonic distortions (THDs), and percentage overshoots
(POs) to provide a more explicit comparison. As seen, EA is less than 0.4% in
different cases. This is because the PR regulator has a high gain at the fundamental
frequency, ensures the tracking accuracy, and suppresses the effect of the funda-
mental sampling error of the capacitor current (see Fig. 9.8). As for the THDs, for
4
3
iC:[2 A/div]
2
1
iCs (A)
0
−1
−2
−3
−4
Time:[5 ms/div] 0 5 10 15 20 25 30 35 40
t (ms)
(a) Experimental waveform (b) Sampled result for λ1 = 1
4 4
3 3
2 2
1 1
iCs (A)
iCs (A)
0 0
−1 −1
−2 −2
−3 −3
−4 −4
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
t (ms) t (ms)
(c) Sampled result for λ1 = 0.5 (d) Sampled result for λ1 = 0.1
Fig. 9.11 Experimental and sampled capacitor currents for different k1
vpcc:[100 V/div] vpcc:[100 V/div]

i2:[20 A/div] i2:[20 A/div]
Time:[5 ms/div] Time:[5 ms/div]

(a) λ1 = 1 (b) λ1 = 0.5
Fig. 9.12 Steady-state experimental results under full load condition with Lg = 0
k1 = 1, due to the dead-time effect, a certain amount of harmonics, which are

mainly of low order, exists in the grid current. And for 0.1 k1 0.5, the THDs
get higher due to that the sampling-induced low-order aliased harmonics of the
capacitor current are injected into the control loop. Besides increasing the loop
gains, this drawback can be overcome by selecting a proper k1. Note that, for
vpcc:[100 V/div] i2:[20 A/div] vpcc:[100 V/div] i2:[20 A/div]

(a) λ1 = 1 (b) λ1 = 0.5
Fig. 9.13 Transient experimental results when the grid current reference steps between half and
full load with Lg = 0
Table 9.2 Measured results k1 1 0.5 0.4 0.3 0.2 0.1

in different cases
EA (%) 0.4 0.4 0.3 0.22 0.18 0.25
THDs (%) 0.87 0.9 1.22 1.27 1.15 0.96
POs (%) 40 40 41 41 41 40
k1 = 0.5 and k1 = 0.1, the THDs increase a little compared with that when k1 = 1,
thus they are preferred in practice. Moreover, since satisfactory stability margins are
preserved in different cases, the measured POs are nearly the same.
As discussed in Sect. 9.2.2, in the case of k1 = 1, instability arises for
180 lH < Lg < 750 lH. To draw the worst case, Lg = 220 lH, which corresponds
to fr = 3.3 kHz, is chosen and tested, and the experimental results for k1 = 1 and
k1 = 0.5 are shown in Fig. 9.14. For k1 = 1, as shown in Fig. 9.14a, oscillation
appears in the grid current, and the oscillation frequency is equal to fr = 3.3 kHz.
This indicates the system instability and is well in agreement with the theoretical
analysis. And for k1 = 0.5, as shown in Fig. 9.14b, the oscillation disappears, and a
stable operation is retained. The experimental results show that, using the
capacitor-current-feedback active-damping with reduced computation delay, the
vpcc:[100 V/div] vpcc:[100 V/div]

i2:[20 A/div] i2:[20 A/div]

(a) λ1 = 1 (b) λ1 = 0.5
Fig. 9.14 Experimental results with Lg = 220 lH

LCL-type grid-connected inverter remains satisfactory steady-state and transient

performances and exhibits high robustness against the grid-impedance variation.
It should be noted that the presented real-time sampling method can also be
applied to the sampling of the grid current, and the computation delay in the grid
current loop can be reduced, which leads to the improvement of system phase.
Based on the analysis presented in Sect. 9.1.3, a higher crossover frequency with
satisfactory phase margin can be acquired. Detailed analysis about this issue will be
discussed in the following section.
9.3 Real-Time Computation Method

with Dual Sampling Modes
According to the analysis in Sect. 9.2, the real-time sampling method can only
reduce but not eliminate the computation delay due to the limitation of the sampling
and computation speed. Moreover, since the sampling instant no longer locates at
the beginning and in the middle of a switching period, the aliasing and switching
noise might be introduced in the real-time sampling. To overcome these drawbacks,
a real-time computation method with dual sampling modes, which can fully
eliminate the computation delay and avoid the aliasing and switching noise, is
further presented in this section.
9.3.1 Derivation of the Real-Time Computation Method
In order to eliminate the computation delays completely and meanwhile to improve

noise immunity, the real-time control can be adopted, and its digital PWM scheme
is shown in Fig. 9.15a. Since the operational principles in the positive and negative
half cycles of the fundamental waveform are similar, only the operational principle
in the positive half cycle is analyzed here. Different from the real-time sampling
method discussed in Sect. 9.2, the sampling instant is still placed at the peak and
valley of the carrier so as to avoid the sampling-induced aliasing and the switching
noise.
With the unipolar SPWM, the PWM reference is compared with two interleaved
carriers equivalently, and the obtained duty cycle dy is then used to regulate the
pulsewidth of the inverter bridge voltage vinv. To acquire a positive proportional
feature for the PWM modulator, it is chosen to output high level during the intervals
when the PWM reference is higher than the carriers.
In Fig. 9.15, vM1 is the ideal PWM reference that can be obtained at the very
instant of sampling and updated without any delay. However, the practical PWM
reference vM2 can only be obtained with an inevitable computation delay td
Fig. 9.15 PWM scheme of

real-time computation method vM1
0 vM2 t
vinv
0 t
t
Ts td 0.5(1−dy)Ts
k k+1 k+2 k+3
Note Sampling Instant; vM1 Update Instant;
vM2 Update Instant.
(a) Peak-valley sampling mode
vM2
vM1
0 t
vinv
0 t
t
Ts td 0.5dyTs
k k+1 k+2 k+3
Note Sampling Instant; vM1 Update Instant;
vM2 Update Instant.
(b) Mid-value sampling mode
compared with the ideal one vM1. As seen in Fig. 9.15a, if the PWM reference vM2
can be calculated out and updated before the rising edge of vinv, i.e.,

td \0:5 1 dy Ts ð9:23Þ
the output of the inverter bridge generated by vM2 would be exactly the same with
that generated by vM1. Thus, the computation delay td does not influence the control
system. However, the real-time computation is achieved at the price of limitation on
the maximum duty cycle.
9.3 Real-Time Computation Method with Dual Sampling Modes 217
Actually, besides the peak-valley sampling method, sampling at the mid-value of

the carrier is also free from the sampling-induced aliasing and the switching noise.
Its digital PWM scheme is shown in Fig. 9.15b. Similarly, if the PWM reference
vM2 can be calculated out and updated before the falling edge of vinv, i.e.,
td \0:5dy Ts ð9:24Þ
the computation delay td does not affect the control system either. Likewise, the
real-time computation is achieved at the price of limitation on the minimum duty
cycle.
According to (9.23) and (9.24), it is known that the duty cycle limitation
becomes severe when the time consumed by sampling and computation increases.
In other words, the wider the duty cycle range is, the shorter the allowed delay time
is. Figure 9.16 gives the relationships between the allowed delay time and the duty
cycle for the two sampling methods. As seen, the allowed delay time decreases with
the duty cycle using the peak-valley sampling method, while it increases with the
duty cycle using the mid-value sampling method.
In order to eliminate the duty cycle limitation, two sampling methods can be
combined together, and the new relationship between the allowed delay time and
the duty cycle is indicated with heavy solid line in Fig. 9.16. As seen, a minimum
allowed delay time, which is 0.25Ts, is acquired in the full range of the duty cycle,
i.e., dy 2 [0, 1].
Accordingly, the detailed operational scheme of the dual sampling modes is
shown in Fig. 9.17, where Vtri is the amplitude of the triangular carrier. When
0 < dy < 0.5, i.e., 0 < vM2 < 0.5Vtri, peak-valley sampling mode is used; and when
dy 0.5, i.e., vM2 0.5Vtri, the mid-value sampling mode is used. Thus, the
real-time computation method with dual sampling modes allows minimum delay
time of 0.25Ts and realizes the real-time control without any duty cycle limitation.
At the rising edge and falling edge of the inverter bridge voltage vinv, the
high-frequency switching noise is created due to the switch commutations and may
be coupled to the sensors. Therefore, if the sampling takes place at or close to the
very switching points, the sampled signals would be distorted by the switching
noise. As for the peak-valley sampling method, no matter using the real-time
Fig. 9.16 Allowed delay td_max Peak-Valley Sampling

time versus duty cycle Mid-Value Sampling
Dual Sampling Modes
0.5T s
0.25T s
0 0.5 1 dy
Fig. 9.17 PWM of real-time vM

computation method with v M1
dual sampling modes vM2
0.5V tri
0 t
v inv
d y =0 d y =1
0 t
t
Ts td Ts
k k+1 k+2 k+3 k+4 k+5
Note Peak-valley sampling instant;
Mid-value sampling instant;
v M1 Update instant; v M2 Update instant.
computation or the traditional computation with one step delay, the sampling
instant approaches to the switching points when dy is close to 1, as seen in
Fig. 9.15a. Thus, the switching noise may also have an impact on the sampled
signals. The situation is similar for the mid-value sampling method when dy is close
to 0. Likewise, by shifting the sampling instant toward the PWM reference update
instant, although the computation delay is reduced, the capacitor current sampling
instant might be shifted to the switching points, thus the sampled signals may be
distorted by the switching noise, as shown in Fig. 9.2. Thus, the noise immunity is
weak.
Using the proposed dual sampling modes, however, the time duration between
the sampling instant and the switching points, which equals to the allowed delay
time for computation td_max, is not shorter than 0.25Ts, and it is long enough to
prevent the switching noise from distorting the sampled signals. Therefore, the
noise immunity is enhanced with the proposed dual sampling modes.
It should be noted that the real-time computation method is based on the unipolar
SPWM, and it is not suitable for the three-phase inverter. On the contrary, the
real-time sampling method proposed in Sect. 9.2 is not restricted by the modulation
scheme and can be easily applied to the three-phase inverter.
9.3.2 Design Example
Using the parameters listed in Table 9.1, the design example with the real-time
computation method with dual sampling modes is given as follows. The total
computation time for sampling of the feedback signals and the calculation of
current controller and active damping is about 5 ls, which is less than the allowed
0.25Ts, i.e., 10 ls, thus the real-time computation method can be realized.
To guarantee the good dynamic performance and enough stability margins, the
specifications are given by PM 45° and GM 3 dB. Meanwhile, the ampli-
tude error should satisfy EA 1% to ensure good steady-state performance.
With the proposed control method, k1 and k2 are both reduced to zero. Referring
to the satisfactory region of Kr and fc with k2 = 0 depicted in Fig. 9.7, point A
(fc = 1.8 kHz and Kr = 340) is chosen. Accordingly, Kp = 0.72 and Hi1 = 0.12 can
be obtained according to (9.16) and (9.21). The compensated loop gain is plotted
with the dashed lines, as shown in Fig. 9.18. As seen, the crossover frequency is
fc = 1.9 kHz, the phase margin is PM = 47.8°, the gain margin at fr is
GM = 3.7 dB, and the loop gain at the fundamental frequency is Tfo = 84.6 dB,
corresponding to a 0.2% steady-state error. Thus, the design specifications are
satisfied as expected.
When k1 = 0 and k2 = 1, the controller parameters can be designed in the same
way. Referring to the satisfactory region of Kr and fc with k2 = 1 depicted in
Fig. 9.7, point B is chosen, and the controller parameters can be obtained by
Kp = 0.46, Kr = 100 and Hi1 = 0.01. The compensated loop gain is plotted with the
dot-dashed line shown in Fig. 9.18. The crossover frequency is fc2 = 1.2 kHz, the
phase margin is PM = 46.4°, the gain margin at fx = fs/6 is GM1 = 4.1 dB, and the
loop gain at the fundamental frequency is Tfo = 74 dB, corresponding to a 0.7%
steady-state error. Obviously, all the design specifications are also satisfied.
For a comprehensive comparison, the controller parameters are also designed
when k1 = k2 = 1, and the designed parameters can be given by Kp = 0.46,
Kr = 100 and Hi1 = 0.01. The compensated loop gain is plotted with the solid line
shown in Fig. 9.18. As seen, the characteristic of loop gain below fx is almost the
same as the one with k1 = 0, k2 = 1. However, additional gain margin requiremts at
fr, GM2 < 0, must be satisfied due to the unstable poles. As seen in Fig. 9.18,
GM2 = −11.8 dB, and thus the system is stable.

TD(s) for different k1 and k2
Magnitude (dB)
60
λ1=0, λ2=0
30 GM2
GM1
0 λ1=0, λ2=1
λ1=1, λ2=1 GM
−30
0
Phase (deg)
−180
−360
−540
10 fo 102 103 fc1 fc2 fs/6 fr 104
Frequency (Hz)
1.0 Lg=300μH 1.0

Lg=300μH
0.6 0.6
Lg=2.6mH(0.1PU) Lg=2.6mH(0.1PU)
Imaginary Axis
Imaginary Axis
0.2 0.2
−0.2 −0.2
−0.6 −0.6
−1.0 −1.0
−1.0 −0.6 −0.2 0.2 0.6 1.0 −1.0 −0.6 −0.2 0.2 0.6 1.0
Real Axis Real Axis
(a) λ1=1, λ2=1 (b) λ1=0, λ2=1
1.0
Lg=300μH
0.6
Imaginary Axis
0.2 Lg=2.6mH(0.1PU)
−0.2
−0.6
−1.0
−1.0 −0.6 −0.2 0.2 0.6 1.0
Real Axis
(c) λ1=0, λ2=0
Fig. 9.19 Closed-loop pole maps for different k1 and k2
The closed-loop poles when Lg varies up to 2.6 mH are depicted in Fig. 9.19.
When k1 = k2 = 1, the resonant poles move outside the unit circle and the system
instability arises. When k1 = 0 and k2 = 1, the resonant poles are damped into the
unit circle, but still close to the boundary of the unit circle. When k1 = 0 and
k2 = 0, the resonant poles are further moved into the unit circle, indicating strong
robustness.
9.3.3 Experimental Verification
To get an accurate evaluation of the proposed solution, a programmable ac source

(Chroma 6590) is used to simulate the grid voltage and meanwhile, an external
inductor is used to emulate the grid impedance.
Figure 9.20 gives the steady-state waveforms for different k1 and k2. The
measured results in terms of power factor(PF), fundamental amplitude error EA,
total harmonic distortions (THDs) are listed in Table 9.3. Figure 9.21 gives
dynamic response when grid current reference steps from full load to half load for
different k1 and k2. The measured results in terms of percentage overshoots
(POs) and the settling time ts are also listed in Table 9.3.
As seen in Table 9.3, the computation delay in the capacitor-current-feedback
active-damping has few effects on the steady-state and dynamic performance
because they are mainly determined by the frequency responses below the crossover
frequency, which can be tuned almost the same for different k1, as shown with the
solid line and dot-dashed line in Fig. 9.18. However, by eliminating the computation
delay in the grid current loop, the low-frequency loop gain and the control bandwidth
can be increased, as shown with the dashed line in Fig. 9.18. Thus, the tracking
performance can be greatly improved, and the current distortion caused by the
dead-time effect can be suppressed more effectively. Meanwhile, the overshoot can be
reduced due to the allowed larger damping coefficient.
vpcc: [100 V/div] vpcc: [100 V/div]

i2: [20 A/div] i2: [20 A/div]
Time: [5 ms/div] THD = 1.74% Time: [5 ms/div] THD = 1.75%
(a) λ1=1, λ2=1 (b) λ1=0, λ2=1
vpcc: [100 V/div]

i2: [20 A/div]
Time: [5 ms/div] THD = 1.06%

(c) λ1=0, λ2=0
Fig. 9.20 Steady-state experimental results under full load with grid impedance Lg = 0
Table 9.3 Measured results Case k1 = 1, k1 = 0, k1 = 0,

in different cases k2 = 1 k2 = 1 k2 = 0
PF 0.998 0.998 0.999
EA (%) 0.6 0.6 0.22
THDs (%) 1.74 1.75 1.06
POs (%) 40 38 30
ts (ms) 2.5 2.5 1.2
σ σ
i2: [20 A/div] i2: [20 A/div]

(a) λ1=1, λ2=1 (b) λ1=0, λ2=1
vpcc: [100 V/div]
i2: [20 A/div]
Time: [5 ms/div]
(c) λ1=0, λ2=0
Fig. 9.21 Transient responses when grid current reference steps down from full load to half load
with grid impedance Lg = 0
Figure 9.22 gives the experiments results when the grid impedance is 300 lH.
When k1 = k2 = 1, the grid current oscillates seriously, as shown in Fig. 9.22a.
When k1 = 0 and k2 = 1, the grid current oscillations only appear during the step
transient, as shown in Fig. 9.22b. When k1 = k2 = 0, no obvious oscillations occur
during the step transient, indicating strong stability, as shown in Fig. 9.22c. The
experimental results show that, using real-time computation method with dual
sampling modes, the LCL-type grid-connected inverter exhibits higher robustness
against the grid-impedance variation.
Figure 9.23 shows the experimental results of different delay time reduction
methods under the real power grid. Using the traditional computation method with

i2: [20 A/div] i2: [20 A/div]

(a) λ1 = 1, λ2 = 1 (b) λ1 = 0, λ2 = 1
vpcc: [100 V/div]

i2: [20 A/div]
Time: [5 ms/div]
(c) λ1 = 0, λ2 = 0
Fig. 9.22 Experimental results with grid impedance Lg = 300 lH

i2: [20 A/div] i2: [20 A/div]
Time: [5 ms/div] THD = 5.17% Time: [5 ms/div] THD = 3.34%

(a) λ1 = 1, λ2 = 1 (b) λ1 = 0.1, λ2 = 0.1
vpcc: [100 V/div]

i2: [20 A/div]
Time: [5 ms/div] THD = 2.89%

(c) λ1 = 0, λ2 = 0
Fig. 9.23 Experimental results of different delay time reduction methods under real power grid
one step delay, grid current is distorted by the grid voltage harmonics and the THD
is 5.17%, as shown in Fig. 9.23a. By shifting the sampling instant toward the PWM
reference update instant, the computation delay can be reduced to 5 ls, thus the
controller parameters can be optimized and the grid current distortion caused by the
grid voltage harmonics can be better suppressed, as shown in Fig. 9.23b. The THD
is reduced to 3.34%. Employing the real-time computation method with dual
sampling modes, both the harmonic rejection ability and noise immunity are
improved, so the grid current distortion is reduced to the most degree, as shown in
Fig. 9.23c. The corresponding THD is only 2.89%.
9.4 Summary
This chapter firstly presents the mathematical model of the digitally controlled LCL-
type grid-connected inverter. Then, the influence of the digital control delay on the
system stability and control performance are analyzed in detail. It is proved that, by
reducing the computation delay in the capacitor-current-feedback active-damping,
the virtual impedance exhibits more like a resistor in a wider frequency range, and
the open-loop RHP poles are removed, thus high robustness against the
grid-impedance variation is acquired. Moreover, by reducing the computation delay
in the grid current loop, the low-frequency loop gain and the control bandwidth can
be increased, and thus the current control performance can be enhanced. Therefore,
to reduce the computation delay, both real-time sampling method and the real-time
computation method with dual sampling modes are proposed, which have the
following features: (1) The real-time sampling method can reduce the computation
delay directly, is not restricted by the modulation scheme, and can be easily applied
to the single-phase and three-phase grid-connected inverters. However, it contains
the aliasing and switching-noise hazards. (2) The real-time computation method
with dual sampling modes can eliminate the computation delay completely and can
avoid the aliasing and switching noise at the same time. However, this method is
based on the unipolar SPWM, so it is not suitable for the three-phase
grid-connected inverter. The design examples with the two proposed methods are
presented in this chapter, and a 6-kW single-phase LCL-type grid-connected
inverter is built and tested in the laboratory. The experimental results show that,
with the computation reduction methods proposed in this chapter, the LCL-type
grid-connected inverter can improve both the steady-state and dynamic perfor-
mances and exhibits high robustness against the grid-impedance variation at the
same time.
References 225
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improve the current control performance of the LCL-type grid-connected inverter. IEEE
Electron. 21(1), 263–272 (2006)
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Seattle, WA (2006)
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(2009)
Chapter 10
Impedance Shaping of LCL-Type
Grid-Connected Inverter to Improve
Its Adaptability to Weak Grid
Abstract As the penetration of distributed power generation systems goes high,

the power grid exhibits more like a weak grid which features a large set of grid
impedance values and varieties of background voltage harmonics. The grid impe-
dance can change the loop gain of the grid-connected inverter and thus challenge
the control performance or even lead to system instability. The background voltage
harmonics will distort the grid current and result in a poor power quality. Therefore,
the grid-connected inverter should be designed with strong stability robustness and
high harmonic-rejection ability, both of which correlate closely with the inverter
output impedance. To shape the inverter output impedance, an impedance shaping
method is proposed in this chapter, which introduces a virtual parallel impedance
and a virtual series inductor. The virtual parallel impedance is used to maximize the
magnitude of output impedance, and meanwhile, a virtual series inductor is used to
boost its phase. Thus, the grid-connected inverter exhibits strong rejection ability of
grid voltage harmonics and achieves strong stability robustness against the varia-
tions of the typical inductive-resistive grid impedance. Experimental results of a
6-kW single-phase grid-connected inverter with LCL filter confirm the effectiveness
of the proposed method.
Keywords Distributed power generation Harmonic distortion Robustness

Weak grid
As the penetration of distributed power generation systems goes high, the power
grid exhibits more like a weak grid which features a large set of grid impedance
values and varieties of background voltage harmonics. The grid impedance can
change the loop gain of the grid-connected inverter and thus challenge the control
performance or even lead to system instability. The background voltage harmonics
will distort the grid current and result in a poor power quality. Therefore, the
grid-connected inverter should be designed with strong stability robustness and
high harmonic-rejection ability, both of which correlate closely with the inverter
output impedance. To shape the inverter output impedance, an impedance shaping
method is proposed in this chapter. With this method, the grid-connected inverter
228 10 Impedance Shaping of LCL-Type Grid-Connected Inverter …
can work stably over a wide range of the grid impedance and exhibit high rejection
ability of the background voltage harmonics, leading to a strong adaptability to the
weak grid condition [1].
10.1 Derivation of Impedance-Based Stability Criterion

for Grid-Connected Inverter
Usually, to analyze the stability of the inverter connected to the weak grid, it is
common to take the inverter and the grid impedance as an entirety. As a result, the
entire model is complicated and needs to be reconfigured when the grid impedance
varies. In this section, the impedance-based stability criterion is derived. With this
criterion, the stability of the grid-connected inverter can be determined using only
the inverter output impedance and the grid impedance. Thus, it avoids remodeling
the entire system when the grid impedance varies, and is more convenient to be
extended to the situation where multiple inverters are connected to the same power
grid [2].
Figure 10.1 shows the equivalent circuit of the grid-connection system. For
simplification, the grid-connected inverter is modeled by its Norton equivalent
circuit, consisting of an ideal current source is(s) in parallel with an output impe-
dance Zo(s). Likewise, the grid is modeled by its Thevenin equivalent circuit,
consisting of an ideal voltage source vg(s) in series with the grid impedance Zg(s).
vpcc(s) is the voltage at the point of the common coupling (PCC). The grid current
i2(s) can be derived as
Zo ðsÞ 1
i2 ðsÞ ¼ is ðsÞ vg ðsÞ ð10:1Þ
Zo ðsÞ þ Zg ðsÞ Zo ðsÞ þ Zg ðsÞ
Equation (10.1) can be rewritten as

1 vg ðsÞ vg ðsÞ
i2 ðsÞ ¼ is ðsÞ ¼ NðsÞ is ðsÞ ð10:2Þ
1 þ Zg ðsÞ Zo ðsÞ Zo ðsÞ Zo ðsÞ
where N(s) is given by
Fig. 10.1 Equivalent circuit i2(s) PCC Zg(s)

of the grid-connection system
+
is(s) Zo(s) vpcc(s) vg(s)
–
Inverter Grid
10.1 Derivation of Impedance-Based Stability … 229
1
NðsÞ ¼ ð10:3Þ
1 þ Zg ðsÞ Zo ðsÞ
Generally, the grid-connected inverter is designed as a stable system when

operating under an ideal grid with assumption of Zg(s) = 0. It means that the item
(is(s) − vg(s)/Zo(s)) in (10.2) is stable. Therefore, the stability of the grid-connected
inverter depends on N(s) when the grid impedance is taken into account. As seen in
(10.3), N(s) can be treated as the close-loop transfer function of a negative feedback
control system where the forward gain is unity and the feedback gain is Zg(s)/Zo(s),
and Zg(s)/Zo(s) is the equivalent system loop gain. Therefore, if the impedance ratio
Zg(s)/Zo(s) satisfies the Nyquist stability criterion, N(s) is stable, and thus, the
grid-connected inverter will be stable.
Based on the above analysis, the impedance-based stability criterion can be
derived as:
1. The grid-connected inverter is stable when operating under an ideal grid with
assumption of Zg(s) = 0.
2. The impedance ratio Zg(s)/Zo(s) satisfies the Nyquist stability criterion.
10.2 Output Impedance Model of Grid-Connected

Inverter
According to the impedance-based stability criterion, the output impedance model

of the grid-connected inverter should be firstly established before analyzing the
impact of the grid impedance on the system stability. Taking the single-phase
LCL-type grid-connected inverter as the example, the output impedance model will
be derived in this section.
Figure 10.2 shows a generic structure of the LCL-type grid-connected inverter in
digital control. The LCL filter consists of an inverter-side inductor L1, a filter
capacitor C, and a grid-side inductor L2. Vin is the input dc voltage, and vinv is the
output voltage of the inverter bridge. Hi2 is the sensor gain of the grid current i2, and
Gi(s) is the current regulator. The capacitor current iC is fed back with the coeffi-
cient of Hi1 to damp the LCL filter resonance [3]. The grid is represented by its
Thevenin equivalent circuit, i.e., an ideal voltage source vg in series with the grid
impedance Zg. The PCC voltage vpcc is sensed with the gain of Hv and then is sent
to the phase-locked loop (PLL). The grid current reference i*2 is generated using the
grid voltage phase h detected by the PLL and the current amplitude command I*.
The digitally controlled system contains a computation delay and a pulse-width
modulation (PWM) delay. The computation delay is the time duration between the
sampling instant and the PWM reference update instant for sampling and calcula-
tion, and it is one sampling period Ts in the synchronous sampling method, where the
sampling takes place at the beginning and in the middle of a switching period[4].
Fig. 10.2 Configuration of L1 L2 i2 PCC Zg

grid-connected inverter with
+ +
LCL filter
vinv C iC vpcc vg
Vin
Hi1 Hi2 Hv
SPWM
ZOH PLL
cosθ
vM + + i2*
e sλTs Gi I*
DSP controller
By shifting the sampling instant toward the PWM reference update instant, the
computation delay can be reduced [5] or even eliminated [6]. Moreover, by
employing different sampling instants for iC and i2, different computation delays can
be resulted in the capacitor-current-feedback active damping and the grid current
loop. This feature has been analyzed in Chap. 9. Here, the same computation delay
kTs (0 k 1) is used for both iC and i2, and it can be modeled as eskTs .
The PWM delay is caused by the zero-order hold (ZOH) effect which keeps the
PWM reference constant after it has been updated, and it can be modeled as
1 esTs
Gh ðsÞ ¼ Ts e0:5sTs ð10:4Þ
s
As seen in (10.4), the PWM delay is definitely a half sampling period.

Meanwhile, the sampling switch can be modeled as 1/Ts. With the above models,
the linearized model of the digitally controlled inverter with LCL filter in s-domain
can be derived as shown in Fig. 10.3a, where KPWM = Vin/Vtri is the transfer
function of inverter bridge, and Vtri is the amplitude of the triangular carrier. As
observed from Fig. 10.3a, 1/Ts is included in the forward path of i*2(s) and the
feedback paths of i2 and iC, so 1/Ts can be merged into the input port of Gh(s), as
shown in Fig. 10.3b, where Gd(s) is the transfer function combining the compu-
tation delay, the PWM delay, and the sampler [7], expressed as
1
Gd ðsÞ ¼ eskTs Gh ðsÞ esðk þ 0:5ÞTs ð 0 k 1Þ ð10:5Þ
Ts
Using the equivalent transformations presented in [8], Fig. 10.3b can be trans-
formed into Fig. 10.3c. The expressions of Gx1(s) and Gx2(s) are given by
10.2 Output Impedance Model of Grid-Connected Inverter 231
(a)
(b)
(c)
(d)
Fig. 10.3 Control block diagram of grid-connected inverter
KPWM Gd ðsÞGi ðsÞ

s2 L1 C þ sCHi1 KPWM Gd ðsÞ þ 1

s3 L1 L2 C þ s2 L2 CHi1 KPWM Gd ðsÞ þ sðL1 þ L2 Þ
Therefore, the loop gain T(s) can be derived as
Hi2 KPWM Gd ðsÞGi ðsÞ

TðsÞ ¼ Gx1 ðsÞGx2 ðsÞHi2 ¼ ð10:8Þ
s3 L1 L2 C þ s2 L2 CHi1 KPWM Gd ðsÞ þ sðL1 þ L2 Þ
According to Fig. 10.3c, the grid current i2 can be derived as
vpcc ðsÞ
i2 ðsÞ ¼ is ðsÞ ð10:9Þ
Zo ðsÞ
where is(s) and Zo(s) are the Norton equivalent current source and the inverter
output impedance, expressed as
1 TðsÞ
is ðsÞ ¼ i ðsÞ ð10:10Þ
Hi2 1 þ TðsÞ 2
1 þ TðsÞ
Zo ðsÞ ¼ ð10:11Þ
Gx2 ðsÞ
Referring to Fig. 10.3c, moving the feedback node of i2(s) from the input of
Gx1(s) to the input of Gx2(s) leads to the equivalent control block diagram as shown
in Fig. 10.3d. Thus, the output impedance can be obtained in the form of admit-
tance as indicated with the dashed block.
10.3 Relationship Between Output Impedance

and Control Performances
According to (10.1), in order to suppress the grid current distortion induced by

vg(s), the magnitude of Zo(s) + Zg(s) should be large enough. Since Zg(s) is
determined by the power grid, only Zo(s) can be shaped to achieve this target.
Typically, the output impedance of the grid-connected inverter with PI regulator
is usually capacitive within the current control bandwidth [9], and it becomes
inductive in the high-frequency range due to the grid-side inductor L2. The grid
impedance is mainly introduced by long distribution wires and low power trans-
formers, and it can be modeled as an inductor in series with a resistor for simpli-
fication [10]. The typical frequency responses of the inverter output impedance, the
grid impedance, and the sum of the two impedances are shown in Fig. 10.4.
According to Fig. 10.4, three different conditions are discussed as follows:
1. When |Zo(s)| |Zg(s)|, |Zo(s) + Zg(s)| can be approximated to |Zo(s)|. So it is
desirable to increase the magnitude of Zo(s) to improve the harmonic-rejection
ability.
2. When |Zo(s)| |Zg(s)|, |Zo(s) + Zg(s)| can be approximated to |Zg(s)|, thus the
harmonic-rejection ability of the inverter mainly depends on magnitude of Zg(s),
and it is difficult to change.
3. When |Zo(s)| |Zg(s)|, |Zo(s) + Zg(s)| mainly depends on the phase difference of
Zo(s) and Zg(s) at the frequency fi where the magnitude curves of Zo(s) and
Zg(s) intersect. The phase difference at fi is denoted by Dh. When Dh is close to
10.3 Relationship Between Output Impedance and Control Performances 233
Fig. 10.4 Frequency Zo ( s)

responses of inverter output
Zg ( s )
Magnitude (dB)
impedance, grid impedance,
Zo( s )+ Zg ( s )
and the sum of the two
impedances
Phase (°) 90
180º Δθ
PM
−90
fi fs /2
Frequency (Hz)
180°, a series resonance between Zo(s) and Zg(s) occurs at fi due to their nearly
opposite phases and equal magnitudes, and a great dip in the magnitude of
Zo(s) + Zg(s) will occur. In order to avoid this great dip, the phase of
Zo(s) should be boosted to keep Dh away from 180°.
Therefore, in order to improve the harmonic-rejection ability, it is necessary to
increase the magnitude of Zo(s), while the phase of Zo(s) at the intersection fre-
quency fi is required to be boosted to ensure the phase margin be a positive one, i.e.,
PM > 0. Here, PM is expressed as

PM ¼ 180 \Zg ðfi Þ \Zo ðfi Þ ð10:12Þ
10.4 Output Impedance Shaping Method
According to (10.11), the output impedance can be shaped by adjusting the current
loop gain T(s). However, T(s) is usually designed for ensuring the system stability
and good dynamics of the current source is(s). So, T(s) cannot be designed to shape
the output impedance. Introducing a parallel- or series-connected impedance is an
effective approach for shaping the output impedance.
10.4.1 Parallel Impedance Shaping Method
Figure 10.5 shows the equivalent circuit of grid-connected inverter with the
introduced parallel impedance. The shaped output impedance Z′o(s) becomes
Zo ðsÞZop ðsÞ
Zo0 ðsÞ ¼ ð10:13Þ
Zo ðsÞ þ Zop ðsÞ
As seen from (10.13), Z′o(s) could be increased to infinite if the parallel impe-
dance Zop(s) is set to −Zo(s). Thus, the current harmonics caused by grid voltage can
be eliminated. Meanwhile, the impedance ratio Zg(s)/Z′o(s) is always kept within the
unit circle in the complex plane, which means that the stability robustness of
inverter is very strong.
According to Figs. 10.3d and 10.5, the parallel impedance can be implemented
as shown in Fig. 10.6a, where vpcc(s) is fed forward to i2(s) with the transfer
function of 1/Zop(s). It can be seen that the parallel impedance shaping method is
equivalent to the feedforward control strategy discussed in Chap. 6.
Since it is desirable to set Zop(s) = −Zo(s), the feedforward node of vpcc(s) can be
moved from the output of Gx2(s) to the input of Gx2(s) so as to share the admittance
path 1/Zo(s), as shown in Fig. 10.6b, where the transfer function is adjusted to −1
accordingly. Gx1(s) can be split into Gi(s) and Gx1(s)/Gi(s), and then, the feedfor-
ward node of vpcc(s) is further moved to the output of the current regulator Gi(s),
and the transfer function is adjusted to Gi(s)/Gx1(s) accordingly, leading to the
equivalent control block diagram, as shown in Fig. 10.6c.
The implementation function of the parallel impedance in Fig. 10.6c can be
expressed as
Gi ðsÞ s2 L1 C þ sCHi1 KPWM Gd ðsÞ þ 1 1

GZ ðsÞ ¼ ¼ ð10:14Þ
Gx1 ðsÞ KPWM Gd ðsÞ
It can be seen that the implementation function contains a prediction component,

given by
1
¼ esðk þ 0:5ÞTs ð10:15Þ
Gd ðsÞ
Fig. 10.5 Equivalent circuit

of grid-connected inverter
with introduced parallel
impedance
10.4 Output Impedance Shaping Method 235
(a)
(b)
(c)
Fig. 10.6 Control block diagram of grid-connected inverter with parallel impedance
Featuring the unity gain with a pure phase-leading, the prediction component
cannot be realized physically. Therefore, the implementation function can only be
closely approximated as

G0Z ðsÞ ¼ ð10:16Þ
KPWM
With this approximation, the actual virtual parallel impedance is expressed as
0 GZ ðsÞ
Zop ðsÞ ¼ Zo ðsÞ ¼ Zo ðsÞ Gd ðsÞ ð10:17Þ
G0Z ðsÞ
Fig. 10.7 Frequency
∠ K Zp ( j 2π f ) (°) |KZp ( j 2π f )| (dB)

response of the gain KZp(s)
−60
−90
fu fs /2
Frequency (Hz)
Therefore, the actual shaped output impedance Z′o(s) is given by

0
Zo ðsÞZop ðsÞ
Zo0 ðsÞ ¼ 0
¼ KZp ðsÞZo ðsÞ ð10:18Þ
Zo ðsÞ þ Zop ðsÞ
where
1 1
KZp ðsÞ ¼ ¼ ð10:19Þ
1 Gd ðsÞ 1 esðk þ 0:5ÞTs
Figure 10.7 shows the plots of the frequency response of KZp(s). Letting
|KZp(j2pf)| = 1, the unity-gain frequency fu can be obtained as
1
fu ¼ fs ð10:20Þ
6ðk þ 0:5Þ
where fs = 1/Ts is the sampling frequency.

Since the PWM delay is inevitable, fu can be increased to fs/3 when k approaches
to zero. As seen in Fig. 10.7, the virtual parallel impedance can greatly increase the
output impedance at the frequencies below fu, but it fails to do so at the frequencies
above fu. Moreover, the virtual parallel impedance introduces a severe phase-lag to
the shaped output impedance and phase-lag remains 60° even at fu, which greatly
weakens the stability robustness. In brief, considering the control delay, the parallel
impedance shaping method enhances the harmonic-rejection ability, but weakens
the stability robustness.
10.4.2 Series–Parallel Impedance Shaping Method
As mentioned above, the parallel impedance enhances the harmonic-rejection

ability. However, the shaped output impedance Z′o(s) may still intersect with
Zg(s) in the high-frequency range. To guarantee the stability robustness, it is
desirable to boost the phase angle of Z′o(s) within this frequency range. According
to (10.18), this could be achieved by modifying Zo(s) in advance. Therefore, a series
impedance is introduced besides the parallel impedance, as illustrated in Fig. 10.8a.
Its Norton equivalent circuit is given in Fig. 10.8b, where the current source
i′ s (s) and the output impedance Z eq(s) can be derived as
1
i0s ðsÞ ¼ is ðsÞ ð10:21Þ
1 þ Zos ðsÞ=Zo ðsÞ
Zeq ðsÞ ¼ Zo ðsÞ þ Zos ðsÞ ð10:22Þ
Substituting Zo(s) = Zeq(s) into (10.18), yields
1
Zo00 ðsÞ ¼ ½Zo ðsÞ þ Zos ðsÞ
ð10:23Þ
1 Gd ðsÞ
As mentioned above, the series impedance Zos(s) is introduced for boosting the
phase of Zeq(s) in the high-frequency range, so as to boost the phase of Z″o(s).
Figure 10.9 depicts the vector diagram of synthesizing Zos(s) and Zo(s). As seen, in
order to boost a larger phase d, Zos(s) is required to have a higher magnitude and a
larger phase-leading h with respect to Zo(s). Therefore, featuring high magnitude in
the high-frequency range and 90° phase response, the inductor is the soundest
choice for the series impedance Zos(s). Thus, Zos(s) can be expressed as
Zos(s) = sLos, where Los is the series inductor.
According to Figs. 10.6a and 10.8a, the series impedance can be implemented
by feeding back i′2(s) to the input of Gx2(s) with the transfer function of Zos(s), as
Fig. 10.8 Equivalent circuit of grid-connected inverter with series and parallel impedances and its
Norton equivalent form
Fig. 10.9 Vector diagram of j Z.

os
synthesizing Zos(s) and Zo(s)
.
Z eq
θ
0 δ
.
Zo
pcc
pcc
Fig. 10.10 Control block diagram of grid-connected inverter with parallel and series impedances
and its equivalent transformations
shown in Fig. 10.10a, where the implementation of the parallel impedance is

remained. Figure 10.10a can be equivalently transformed into Fig. 10.10b.
Similarly, since the prediction component cannot be realized physically, the
implementation function Gi(s)/Gx1(s) can be approximately realized by (10.16).
With this approximation, the actual virtual series impedance can be obtained as
0 G0Z ðsÞ
Zos ðsÞ ¼ Zos ðsÞ ¼ sLos Gd ðsÞ ð10:24Þ
GZ ðsÞ
Figure 10.11 gives the frequency response of the virtual series impedance
Z′os(s). It can be seen that the magnitude–frequency response curve rises with a
slope of 20 dB/dec, which coincides with a pure inductor. Nevertheless, the phase
of Z′os(s) is reduced by the control delay Gd(s) compared with a pure inductor. The
phase-lag introduced by Gd(s) is proportional to the frequency and can be expressed
as
Duðf Þ ¼ \Gd ðj2pf Þ ¼ 360 ðk þ 0:5ÞTs f ð10:25Þ
Thus, it is desirable to minimize the control delay with appropriate method to

minimize Du and so as to improve the shaping ability of Z′os(s).
| Zos' ( j 2π f )| (dB)
Fig. 10.11 Frequency
response of the virtual serial
impedance
20dB/dec
∠ Z os' ( j 2π f ) (°)
90
Δφ
Frequency (Hz) fs /2
10.4.3 Discussion of the Series–Parallel Impedance

Shaping Method
As seen from (10.21), the series impedance also influences the current source
i′s(s) in terms of steady-state error and stability. Thus, Zos(s) should be designed to
alleviate this impact. Moreover, due to the tolerance or aging of the filter compo-
nents, the LCL filter parameter variations might happen. Referring to (10.16), the
implementation function of the virtual impedances is related to L1 and C. Therefore,
the accuracy of the virtual impedances might be weakened due to the LCL filter
parameter variations, which will be also analyzed in this section.
10.4.3.1 Design Rules of Series Impedance
The steady-state error induced by series impedance Zos(s) is denoted by EA, and it
can be expressed as
0
is ðjxo Þ is ðjxo Þ Zos ðjxo Þ

EA ¼
¼ ð10:26Þ
is ðjxo Þ Zos ðjxo Þ þ Zo ðjxo Þ
where xo is the fundamental angular frequency of the current source.

Being an inductor, the series impedance is far lower than the output impedance
at xo, and EA can be approximated to

Zos ðjxo Þ
EA ¼ xo Los ð10:27Þ
Zo ðjxo Þ jZo ðjxo Þj
Given that the maximum steady-state error is EA_max, the corresponding maxi-
mum value of Los can be obtained as
EA max jZo ðjxo Þj

Los max1 ¼ ð10:28Þ
xo
The series impedance also changes the stability margins of the current loop in a
way similar to the grid impedance. Therefore, the influences can be assessed by the
stability criterion illustrated in Sect. 10.1. Referring to Fig. 10.4, it can be seen that
the intersection frequency fi is reduced when the grid inductance increases, so PM is
reduced accordingly. Therefore, given a minimum phase margin PMmin, it is easy to
determine the lowest intersection frequency fi_min using the graphical method. The
same method can be used for the series impedance to determine fi_min under the
PMmin constraint. Letting |Zo(j2pfi_min)| = |Z′os(j2pfi_min)|, the maximum value of
Los under the PMmin constraint can be expressed as
jZo ðj2p fi min Þj

Los max2 ¼ ð10:29Þ
2p fi min
To meet both the steady-state error and the phase margin requirements, the
maximum value of Los should be
Los max ¼ minðLos max1 ; Los max2 Þ ð10:30Þ
10.4.3.2 Impedance Accuracy Affected by LCL Filter

Parameter Variations
When the LCL filter parameter variations happen, the actual synthesized series
impedance and parallel admittance are multiplied by an additional gain over the
designed ones. According to Fig. 10.10b, the gain KZps(s) can be derived as

KZps ðsÞ ¼ ð10:31Þ
s2 L01 C0 þ sC 0 Hi1 KPWM Gd ðsÞ þ 1
where L1′ and C′ are the actual parameters of the filter capacitance and inverter-side
inductance in the prototype, L1 and C are the designed parameters. Assuming the
variations of L1′ and C′ are limited to ±10%. Through the enumeration method, the
worst cases are found to be L′1 = 0.9L1, C′ = 0.9C and L′1 = 1.1L1, C′ = 1.1C. The
corresponding frequency responses of gain KZps(s) can be drawn in Fig. 10.12,
using the parameters listed in Table 10.1 that will be given in the next section. As
seen, under the LCL filter parameter variations, the impedance shaping method is
still with high accuracy at the low-frequency range, and the accuracy is a little
weakened in the higher-frequency range, where a maximum 3 dB (30%) magnitude
deviation and 20° phase-lead/phase-lag can be observed.
6
L'1 = L1, C' = C
|KZps( j2πf )| (dB)

3 L'1 = 0.9L1, C ' = 0.9C
L'1 = 1.1L1, C' = 1.1C
−3
−6
∠KZps( j2πf ) (°) 90
45
−45
−90
10 102 103 104 fs/2
Frequency (Hz)
Fig. 10.12 Impedance accuracy affected by LCL parameter variations
Table 10.1 Parameters of the prototype

Parameters Value Parameters Value
Grid voltage (RMS) Vg 220 V Grid-side inductor L2 330 lH
Fundamental frequency fo 50 Hz Sampling frequency fs 30 kHz
Amplitude of the triangular carrier Vtri 3.05 V Sensor gain of the grid current Hi2 0.15
10.5.1 Prototype Design
A prototype of a 6-kW single-phase LCL-type grid-connected inverter is built and

tested in the laboratory. The key parameters of the prototype are shown in
Table 10.1.
The grid-connected inverter is implemented using two insulated gate bipolar
transistor modules (CM100DY-24NF), which are driven by M57962 L. The grid
voltage at the PCC is sensed by a voltage hall (LV25-P). The filter capacitor current
and the injected grid current are sensed by two current halls (LA55-P). The current
controller and active damping are implemented in a DSP (TMS320F2812). To
avoid additional discretization delays, the virtual impedance functions are imple-
mented by the analog circuit and the output is sampled to modify the duty cycle in
the DSP. All the signals are sampled by a 14-bit A/D converter
(MAXIM-1324ECM). The control delay is minimized to 0.5Ts for better control

performances.
The PI regulator is used for the injected grid current regulator. It is discredited by
the backward difference approximation, which can be expressed as
Ki Ts
Gi ðzÞ ¼ Kp þ ð10:32Þ
1 z1
The parameters of current controller are properly designed under the ideal grid
condition with assumption of Zg = 0. Figure 10.13 plots the loop gain of the
grid-connected inverter. The dash line shows the bode diagram of the uncompen-
sated but active damped loop gain T(s) given in (10.8) with Gi(s) = 1 and
Hi1 = 0.042. It can be observed that with the active damping, the resonance of the
LCL filter is effectively damped. The solid line shows the bode diagram of the
compensated loop gain T(s) with Kp = 0.3, Ki = 1300, and Hi1 = 0.042. The cutoff
frequency fc is about 1.7 kHz with phase margin of 45°, and the loop gain at
fundamental frequency fo is 51 dB, which ensures the tracking error of the injected
grid current is less than 1%.
The frequency response of the inverter output impedance Zo(s) is depicted with
dash-dotted line in Fig. 10.14, of which the magnitude is relatively low, implying
weak harmonic-rejection ability. With the parallel impedance shaping method, the
frequency response of the equivalent output impedance Z′o(s) is given with dashed
line in Fig. 10.14. As seen, the magnitude of Z′o(s) is greatly increased in the
low-frequency range, effectively covering most of the harmonic frequencies.
However, a large phase-delay is also introduced, which leads to poor stability
robustness.
Since the resistor in grid impedance tends to increase the phase margin at the
intersection frequency and helps stabilizing the system, the pure inductor is used for
the experimental validation to draw the worst case of inductive-resistive grid
Fig. 10.13 Bode diagram of 100

Uncompensated
the loop gain Compensated
Magnitude (dB)
50 Compensated and shaped
−50
0
−90
Phase (deg)
−145
−180
−270
−360
10 fo 102 103 fc f1 104 fs/2
Frequency (Hz)
Fig. 10.14 Frequency 120

Z"o(s)
response of inverter output Z'o(s)
Magnitude (dB)
impedance and grid 80 Zo(s)
Zg(s)
impedance
40
2.6mH
0
600μH
Lg increases
−40
180
90
Phase (°)
0
−90 PM
−180
10 102 103 fi 104 fs/2
Frequency (Hz)
impedance. As the case for this experiment, the control system is examined with Lg
varying up to 2.6 mH, which corresponds to a typical short-circuit ratio of 10 [11].
As seen from Fig. 10.14, the phase difference between Z′o(s) and Zg (s) has
already approached to 180° when Lg is 600 lH. This means that the grid-connected
inverter is critical stable with nearly zero phase margin. Therefore, to enlarge the
stability range, the virtual series inductor can be introduced to boost the impe-
dance’s phase and thus to increase the phase margin.
By gradually increasing Los and checking the phase margin PM shown in
Fig. 10.14, it is known that Los should be larger than 750 lH to guarantee the phase
margin larger than 45° within the given range of grid impedance. Moreover, con-
sidering the impact on the current source, Los should be smaller than 765 lH
according to (10.30), under the conditions of EA_max = 0.5% and PM_min = 60°.
Therefore, Los is set to 760 lH here, and the corresponding frequency response of
the shaped output impedance Z″o(s) is depicted with solid line in Fig. 10.14.
The shaped output impedance Z″o(s) with ±10% variations of L1′ and C′ is
drawn in Fig. 10.15, which are deviated from the designed one in both the mag-
nitude and phase. The deviations in magnitude are mainly caused by the
phase-leading/phase-lag of KZps(s), which compensates/exacerbates the delay items
of virtual parallel impedance. Meanwhile, the deviations in phase are mainly caused
by the gain of KZps(s), which changes the virtual series impedance values. It can be
seen that the high harmonic-rejection ability and the stability robustness are still
maintained with ±10% variations of LCL parameters. Z″o(s) is measured at a few
points by testing current responses to the imposed grid voltage harmonics, and it is
in well agreement with the calculated ones.
Since the series impedance does influence the current loop gain, the compen-
sated loop gain T(s) after employing series–parallel impedance shaping method is
plotted with the dashed-dotted line, as shown in Fig. 10.13. As seen, the bandwidth
and the phase margin of the new T(s) are slightly reduced by the series impedance.
Fig. 10.15 Frequency 120

L'1 = L1, C'= C
response of shaped output L'1 = 0.9L1, C'= 0.9C
Magnitude (dB)
80 L'1 = 1.1L1, C'= 1.1C
impedance under different
Measured Points
conditions
40
0
Lg=2.6mH
−40
180
90 Lg=2.6mH
Phase (°)
0
−90
−180
10 102 103 fi 104 fs/2
Frequency (Hz)
Since the series impedance has been designed under the constraints of EA and PM,
the steady-state performance and stability of the current loop are guaranteed.
To get an accurate evaluation of the proposed solution, a programmable ac source

(Chroma 6590) is used to simulate the grid voltage distorted by the background
harmonics. The magnitudes of harmonics with respect to the grid fundamental
voltage are shown in Table 10.2. Meanwhile, an external inductor is used to
emulate the grid impedance.
Under the traditional current control with PI regulator, the injected current is
seriously distorted by the grid voltage harmonics under both the stiff and weak grid
conditions, as shown in Fig. 10.16. The measured total harmonic distortion
(THD) of the injected grid currents shown in Fig. 10.16a–c is 6.7%, 8.1%, and
8.9%, respectively.
After employing the shaping method with parallel impedance, the
harmonic-rejection ability of the inverter is greatly enhanced under the stiff grid, as
shown in Fig. 10.17a. The measured current THD is reduced to 1.27%. However,
the stability robustness is weakened greatly that even small grid inductance can
trigger the harmonic resonance, as shown in Fig. 10.17b. The injected grid current
Table 10.2 Magnitudes and phases of the injected harmonics with respect to the grid fundamental
voltage
Harmonic order 3 5 6 9 11 13 21 33 40
Amplitude (%) 10 5 3 3 2 2 1 1 0.25
Phases (°) 0 210 0 0 0 0 0 0 0
Fig. 10.16 Experimental vpcc:[100 V/div]

waveforms with traditional
current control i2:[20 A/div]
Time:[5 ms/div] THD=6.7%

(a) Lg=0
vpcc:[100 V/div]
i2:[20 A/div]

(b) Lg=1.3mH
vpcc:[100 V/div]
i2:[20 A/div]

(c) Lg=2.6mH
oscillates seriously when the grid impedance reaches 600 lH, as shown in
Fig. 10.17c, where only half-load waveform is presented for protection.
Using the shaping method with the parallel and series impedances, the inverter
can inject high-quality power reliably over a wide range of the grid inductance,
Fig. 10.17 Experimental vpcc:[100 V/div]

waveforms with the parallel
impedance shaping method i2:[20 A/div]

(a) Lg=0
vpcc:[100 V/div]
i2:[20 A/div]

(b) Lg=300μH
vpcc:[100 V/div]
i2:[20 A/div]
(c) Lg=600μH
varying from 0 to 2.6 mH, as shown in Fig. 10.18a–c. The corresponding measured
current THD is 1.35%, 1.49%, and 1.63%, respectively, indicating strong
harmonic-rejection ability.

vpcc:[100 V/div]
waveforms with the series–
parallel impedance shaping iL2:[20 A/div]
method

(a) Lg=0
vpcc:[100 V/div]
iL2:[20 A/div]

(b) Lg=1.3mH
vpcc:[100 V/div]
iL2:[20 A/div]

(c) Lg=2.6mH
10.6 Summary
Characterizing the external behavior, the output impedance of the grid-connected

inverter can be shaped to improve the harmonic-rejection ability and the stability
robustness. However, by adjusting the current loop gain, it is rather difficult to
shape the inverter output impedance to meet the both requirements of the two
aspects. Therefore, the virtual parallel impedance is used to maximize the magni-
tude of output impedance, and meanwhile, a series virtual inductor is used to boost
its phase. Thus, the grid-connected inverter exhibits strong rejection ability of grid
voltage harmonics and achieves strong stability robustness against the variations of
the typical inductive-resistive grid impedance. Experimental results of a 6-kW
single-phase grid-connected inverter with LCL filter confirm the effectiveness of the
proposed method.
References
1. Yang, D., Ruan, X., Wu, H.: Impedance shaping of the grid-connected inverter with LCL filter
to improve its adaptability to the weak grid condition. IEEE Trans. Power Electron. 29(11),
5795–5805 (2014)
Electron. 26(1), 3075–3078 (2011)
3. Twining, E., Holmes, D.G.: Grid current regulation of a three-phase voltage source inverter
with an LCL input filter. IEEE Trans. Power Electron. 18(3), 888–895 (2003)
4. Buso, S., Mattavelli, P.: Digital Control in Power Electronics. Morgan & Claypool,
Publishers, Seattle (2006)
5. Mattavelli, P., Polo, F., Lago, F.D., Saggini, S.: Analysis of control-delay reduction for the
improvement of UPS voltage-loop bandwidth. IEEE Trans. Ind. Electron. 55(8), 2903–2911
(2008)
6. Deng, H., Oruganti, R., Srinivasan, D.: PWM methods to handle time delay in digital control
of a UPS inverter. IEEE Trans. Power Electron. 3(1), 1–6 (2005)
7. Agorreta, J.L., Borrega, M., López, J., Marroyo, L.: Modeling and control of N-paralleled
8. Wang, X., Ruan, X., Liu, S., Tse, C.K.: Full feedforward of grid voltage for grid-connected
9. Chen, X., Gong, C., Wang, H., Cheng, L.: Stability analysis of LCL-type grid-connected
inverter in weak grid systems. In: Proceedings of the Renewable Energy Research and
Applications, pp. 1–6 (2012)
10. Cobreces, S., Bueno, E., Rodriguez, F.J., Huerta, F., Rodriguez, P.: Influence analysis of the
effects of an inductive-resistive weak grid over L and LCL filter current hysteresis controllers.
In: Proceedings of the European Conference on Power Electronics and Applications, pp. 1–10
(2007)
Electron. 21(1), 263–272 (2006)
Chapter 11
Weighted-Feedforward Scheme of Grid
Voltages for the Three-Phase LCL-Type
Grid-Connected Inverters Under Weak
Grid Condition
Abstract The full-feedforward scheme of grid voltages for three-phase LCL-type

grid-connected inverter has been introduced in Chap. 7, and the injected grid
current harmonics and imbalance caused by grid voltages can be effectively sup-
pressed. However, during the derivation of the full-feedforward scheme, the grid
impedance is assumed to be zero. For weak grid condition, as the grid impedance
becomes large, the full-feedforward scheme might cause the instability of the
grid-connected inverter. In this chapter, the stationary a-b frame-controlled
three-phase LCL-type grid-connected inverter with the full-feedforward scheme is
taken as the example to analyze the system stability under weak grid condition, and
the weighted-feedforward scheme is proposed to achieve a trade-off between the
stability and the harmonic suppression. With the weighted-feedforward scheme, the
extracted and weighted grid voltages are fed forward, and the injected grid current
harmonics can be effectively suppressed while the stability of grid-connected
inverter under weak grid condition is also guaranteed. Finally, the experimental
results verify the analysis in this chapter.
Keywords Distributed power generation Feedforward scheme Grid-connected

inverter Stability Weak grid
The full-feedforward scheme of grid voltages for three-phase LCL-type

grid-connected inverter has been introduced in Chap. 7, and the injected grid
current harmonics and imbalance caused by grid voltages can be effectively sup-
pressed. However, during the derivation of the full-feedforward scheme, the grid
impedance is assumed to be zero. For weak grid condition, as the grid impedance
becomes large, the full-feedforward scheme might cause the instability of the
grid-connected inverter. In this chapter, the stationary a-b frame-controlled
three-phase LCL-type grid-connected inverter with the full-feedforward scheme is
250 11 Weighted-Feedforward Scheme of Grid Voltages …
taken as the example to analyze the system stability under weak grid condition, and
the weighted-feedforward scheme is proposed to achieve a trade-off between the
stability and the harmonic suppression. With the weighted-feedforward scheme, the
extracted and weighted grid voltages are fed forward, the injected grid current
results verify the analysis in this chapter. With the weighted-feedforward scheme,
the extracted and weighted grid voltages are fed forward, the injected grid current
11.1 Impedance-Based Stability Criterion
The stability criterion for the three-phase grid-connected inverter is similar to that
for the single-phase one derived in Chap. 10, which is derived again in this chapter
for the convenience of interpretation. Based on the model given in Chap. 7, the
equivalent circuit of the three-phase LCL-type grid-connected inverter under weak
grid condition can be given in Fig. 11.1, where PCC is the point of common
coupling, the grid-connected inverter is described with its Norton equivalent circuit,
Zo(s) is the output impedance of the grid-connected inverter, [itrack_ab(s)] =
[itrack_a(s), itrack_b(s)]T are the reference tracking components of the injected grid
currents, [idis_ab(s)] = [idis_a(s), idis_b(s)]T are the disturbance components caused by
the grid voltages at PCC, and Zg(s) is the grid impedance.
According to Fig. 11.1, the injected grid current [i2_a(s), i2_b(s)]T can be
obtained with the superposition theorem, expressed as
Zo ðsÞ 1
i2 ab ðsÞ ¼ itrack ab ðsÞ vg ab ðsÞ ð11:1Þ
Zo ðsÞ þ Zg ðsÞ Zo ðsÞ þ Zg ðsÞ
where [vg_ab(s)] = [vg_a(s), vg_b(s)]T.

Manipulating (11.1), it can be obtained that

vg ab ðsÞ
i2 ab ðsÞ ¼ NðsÞ itrack ab iðsÞ ð11:2Þ
Zo ðsÞ
Fig. 11.1 Equivalent circuit

[i2_αβ(s)] PCC Zg(s)
of the three-phase LCL-type
grid-connected inverter under [itrack_αβ(s)] [idis_αβ(s)] [vpcc_αβ(s)] [vg_αβ(s)]
weak grid condition
Zo(s)
11.1 Impedance-Based Stability Criterion 251
where
1
NðsÞ ¼ ð11:3Þ
1 þ Zg ðsÞ=Zo ðsÞ
Usually, under stiff grid condition where Zg(s) is approximately zero, the
grid-connected inverter is designed to be stable. Thus, ([itrack_ab(s)] − [vg_ab(s)]/
Zo(s)) in (11.2) has no right-half-plane (RHP) poles. Therefore, when the
three-phase LCL-type grid-connected inverter is connected to weak grid, its stability
can be determined by the stability of N(s).
Note that N(s) resembles the closed-loop transfer function of a negative feedback
control system where the forward gain is unity and the feedback gain is Zg(s)/Zo(s)
which is also the equivalent loop gain. Therefore, the three-phase LCL-type
grid-connected inverter under weak grid condition is stable if
1. The three-phase LCL-type grid-connected inverter is stable when Zg(s) = 0.
2. The impedance ratio, Zg(s)/Zo(s), satisfies the Nyquist criterion.
11.2 Stability Analysis Under Weak Grid Condition
11.2.1 Derivation of Output Impedance

of Grid-Connected Inverter
According to the impedance-based stability criterion, the inverter output impedance

is needed for the stability evaluation. In this section, the output impedance of the
stationary a-b frame controlled three-phase LCL-type grid-connected inverter with
the full-feedforward scheme, which is shown in Fig. 11.2, will be derived. In
Fig. 11.2, Vin is the dc input voltage, Q1–Q6 are the switches of the inverter bridge,
Ll is the inverter-side inductor, C is the filter capacitor, L2 is the grid-side inductor,
and vga, vgb and vgc are the three-phase grid voltages.
As illustrated in Sect. 7.1.1, the a-axis mathematical model is similar to the
b-axis one. For the brevity of presentation, the a-axis mathematical model of the
grid-connected inverter is taken as the example for analysis. The a-axis mathe-
matical model with full-feedforward of the grid voltage derived in Chap. 7 is
redrawn here, as shown in Fig. 11.3a. Moving the feedforward node from the
output of Gsi ðsÞ to the input of Gsi ðsÞ and using the simplifying procedure presented
in Chap. 7, Fig. 11.3a can be equivalently transformed into Fig. 11.3b, where
Gsi ðsÞGinv ðsÞZC ðsÞ

ZL1 ðsÞ þ ZC ðsÞ þ Hi1 ðsÞGinv ðsÞ
Fig. 11.2 Schematic diagram of the stationary a-b frame controlled three-phase LCL-type
grid-connected inverter with full-feedforward scheme
pcc
inv
M
inv
pcc
pcc
Fig. 11.3 Block diagram of derivation of inverter output impedance

11.2 Stability Analysis Under Weak Grid Condition 253
ZL1 ðsÞ þ ZC ðsÞ þ Hi1 ðsÞGinv ðsÞ

ZL1 ðsÞZL2 ðsÞ þ ðZL1 ðsÞ þ ZL2 ðsÞÞZC ðsÞ þ Hi1 ðsÞGinv ðsÞZL2 ðsÞ
Moving the feedforward node from the input of Gx1(s) to the output of Gx1(s),
Fig. 11.3b can be further equivalently transformed into Fig. 11.3c, where
Gff ðsÞ
FFðsÞ ¼ 1 Gx1 ðsÞ ð11:6Þ
Gsi ðsÞ
FF(s) indicates the effect of the feedforward scheme. When Gff(s) = 0, which
means no feedforward scheme is used, FF(s) = 1.
According to Fig. 11.3c, the injected grid current can be expressed as
TðsÞ 1 Gx2 ðsÞ

i2 a ðsÞ ¼ i ðsÞ FFðsÞvpcc a ðsÞ
1 þ TðsÞ Hi2 ðsÞ 2 a 1 þ TðsÞ
ð11:7Þ
TðsÞ 1 1
¼ i ðsÞ vpcc a ðsÞ
1 þ TðsÞ Hi2 ðsÞ 2 a Zo ðsÞ
where, T(s) = Gx1(s)Gx2(s)Hi2(s) is the injected grid current loop gain, and Zo(s) is
the output impedance of the grid-connected inverter, which is expressed as
1 þ TðsÞ
Gx2 ðsÞFFðsÞ
Substituting (11.4), (11.5) and (11.6) into (11.8), it can be obtained that
s3 L1 L2 C þ s2 L2 CHi1 ðsÞGinv ðsÞ þ sðL1 þ L2 Þ þ Gsi ðsÞHi2 ðsÞGinv ðsÞ

s2 L1 Cf þ sCHi1 ðsÞGinv ðsÞ þ 1 Gff ðsÞHv ðsÞGinv ðsÞ
Letting Gff(s) = 0, Zo(s) becomes the output impedance of the grid-connected

inverter with no feedforward scheme.
It should be noted that, in Chap. 7, the transfer function of the inverter bridge,
which is Ginv(s), is approximately expressed as Vin/2Vtri, where Vin is the dc input
voltage and Vtri is the amplitude of the triangle carrier. This approximation, which is
usually used in the derivation of the grid-voltage feedforward function of the L-type
grid-connected inverter, makes the derived full-feedforward function Gff(s) causal
and simple [1], and the harmonics of injected grid current can also be effectively
suppressed. However, the accuracy of the stability analysis of the grid-connected
inverter under weak grid condition is dramatically affected by the control delay
introduced by the digital control, and the wrong stability evaluation might be made
due to the ignored control delay of Ginv(s). To obtain the accurate stability analysis
of the three-phase LCL-type grid-connected inverter, Ginv(s) should be expressed
considering the computation and zero-order hold (ZOH) delays [2–4], i.e.,
Vin 1:5sTs
Ginv ðsÞ ¼ e ð11:10Þ
2Vtri
where Ts is the sampling period of the digital controller.
11.2.2 Stability of Grid-Connected Inverter

Under Weak Grid Condition
Table 11.1 gives the main parameters of the three-phase LCL-type grid-connected
inverter prototype. Since the controller is usually implemented in a digital signal
processor (DSP), it is needed to discretize the grid current regulator Gsi ðsÞ and
full-feedforward function Gff(s), yielding the discretized transfer function Gsi ðzÞ and
Gff(z). To guarantee the accuracy of the s-domain analysis, Gsi ðzÞ and Gff(z) are
transformed back into s-domain with z = esTs : Substituting the parameters given in
Table 11.1 into (11.9), the Bode diagram of the inverter output impedance is
depicted, as shown in Fig. 11.4.
Letting Gff = 0 and using the expression of Gff given in (7.12), the output
impedances of the three-phase LCL-type grid-connected inverter without and with
full-feedforward scheme, which are referred as Zo_nff(s) and Zo_ff(s), are drawn in
Fig. 11.4 with the solid and dash lines, respectively. Since the resistance of the grid
impedance helps damp the oscillation, the grid impedance is assumed as the pure
inductor for the worse case. The grid impedance Lg = 100 lH is also given in
Fig. 11.4 with the dot-dashed line. As Lg increases, the magnitude-frequency re-
sponse of Zg(s) will move upward.
According to the impedance-based stability criterion, Zg(s)/Zo(s) should satisfy
the Nyquist criterion to guarantee the stability of the grid-connected inverter under
weak grid condition. With the Bode diagram, if the magnitude-frequency curves of
Zg(s) and Zo(s) intersect at fi, it requires that the phase difference of Zg(s) and
Zo(s) at fi should be limited between ±180° [4, 5]. The phase difference of Zg(s) and
Zo(s) is expressed as
Table 11.1 Parameters of Parameter Value Parameter Value

the 20 kW-protype
Vin 800 V L2 110 lH
Vg (phase, rms) 220 V Vtri 4.6 V
Pn 20 kW Hi1 0.12
fo 50 Hz Hi2 0.14
fs (switching frequency) 10 kHz Hv 0.018
L1 800 lH Kp 0.6
C 15lF Kr 65
11.2 Stability Analysis Under Weak Grid Condition 255
Fig. 11.4 Bode diagram of 100

Zo_nff (s)
Magnitude (dB)
the inverter output impedance
and grid impedance Zo_ ff (s)
50 Zg (s)
0
Lg = 100μH
−50
180
90
Phase (°)
0
−90
−180
101 102 103 fi1 fi2 104
Frequency (Hz)
Du ¼ \Zg ðfi Þ \Zo ðfi Þ ð11:11Þ
From Fig. 11.4, it can be observed that when Lg = 100 lH, Zo_ff(s) and
Zg(s) intersect at about 2 kHz, and Du is 180°, which indicates the critical stability
of the grid-connected inverter. As Lg increases, the magnitude-frequency curve of
Zg(s) moves upward. As a consequence, fi decreases and the corresponding Du will
exceed 180°, the three-phase LCL-type grid-connected inverter using the
full-feedforward scheme of grid voltages will become unstable. However, for the
three-phase LCL-type grid-connected inverter with no feedforward scheme, the
phase of Zo_nff(s) is always higher than −90°. Since the phase of Zg(s) is 90°, it
means Du is always less than 180°, and the three-phase LCL-type grid-connected
inverter with no feedforward scheme exhibits good stability under weak grid
condition. Therefore, it can be concluded that the full-feedforward scheme of grid
voltages weakens the stability of the grid-connected inverter under weak grid
condition.
11.3 Characteristics of the Inverter Output Impedance
The characteristics of the inverter output impedance is analyzed in this section to

find the solution to improve the stability of the grid-connected inverter under weak
grid condition.
11.3.1 Characteristics of the Inverter Output Impedance

Without Feedforward Scheme
Letting Gff = 0 in (11.9), the output impedance of the three-phase LCL-type

grid-connected inverter without feedforward scheme can be obtained that

Zo nff ðsÞ ¼
s2 L1 C þ sCHi1 ðsÞGinv ðsÞ þ 1
ð11:12Þ
Manipulating (11.12) yields
sL1 Gsi ðsÞHi2 ðsÞGinv ðsÞ

Zo nff ðsÞ ¼ sL2 þ þ
s2 L1 C þ sCHi1 ðsÞGinv ðsÞ þ 1 s2 L1 C þ sCHi1 ðsÞGinv ðsÞ þ 1
ð11:13Þ
For the convenience of illustration, the schematic diagram of the three-phase

LCL-type grid-connected inverter is given in Fig. 11.5, where Zdamp(s) is the virtual
paralleled impedance introduced by the capacitor-current-feedback active damping,
expressed as [6]
L1
Zdamp ðsÞ ¼ ð11:14Þ
Hi1 ðsÞCGinv ðsÞ
According to (11.14), (11.13) can be rewritten as
sL1 Gsi ðsÞHi2 ðsÞGinv ðsÞ

Zo nff ðsÞ ¼ sL2 þ þ
s2 L1 C þ sL1 =Zdamp ðsÞ þ 1 s2 L1 C þ sCHi1 ðsÞGinv ðsÞ þ 1
ð11:15Þ
Observing Fig. 11.5 and (11.15), it can be found that the first term on the right
side of (11.15) is ZL2(s), which is the impedance of the grid-side inductor; the
second term is ZL1(s)//ZC(s)//Zdamp(s), which is the shunt impedance of the
inverter-side inductor, filter capacitor and the virtual impedance; and the third term
is Zreg(s), which is mainly affected by the grid current regulator Gsi (s). Therefore,
Zo_nff(s) is the series impedance of ZL2(s), ZL1(s)//ZC(s)//Zdamp(s) and Zreg(s). From
(11.15), it is concluded that in the low-frequency range, Zo_nff(s) is mainly affected
Fig. 11.5 Equivalent circuit [i1_αβ(s)] L1 [vC_αβ(s)] [i2_αβ(s)] L2

of the three-phase LCL-type
grid-connected inverter [iC_αβ(s)] [vg_αβ(s)]
[vinv_αβ(s)] Z damp (s)
Vin C
11.3 Characteristics of the Inverter Output Impedance 257
Fig. 11.6 Output impedance 100 s

of the grid-connected inverter Gi(s) using PI
|Zo_nff ( j2πf )| (dB)

s
without feedforward scheme Gi(s) using PR
50
− 50
180
∠Zo_nff ( j2πf ) (°)

90
−90
−180
101 102 103 104
Frequency (Hz)
by the Gsi (s) since L1 and L2 can be regarded as short circuit, and in the
high-frequency range, Zo_nff(s) is dominated by ZL2(s).
Figure 11.6 gives the Bode diagram of Zo_nff(s) taking the PI and PR regulators
(Kp = 0.6, Kr = 65, xc = p rad/s) as Gi(s), respectively. As seen, the loop gain at
the fundamental frequency is increased with the PR regulator; Meanwhile, since the
negative phase shift introduced by the PR regulator is less than that introduced by
the PI regulator, the phase of Zo_nff(s) is boosted by taking the PR regulator as Gsi (s).
Besides, the steady-state error of the injected grid current is reduced with the
increased fundamental gain of PR regulator. Thus, the reference tracking ability of
the three-phase LCL-type grid-connected inverter under weak grid condition can be
improved by replacing the PI regulator with the PR regulator, and the PR regulator
is adopted as Gi(s) in the following analysis of this chapter.
11.3.2 Inverter Output Impedance Affected

by the Full-Feedforward Scheme
From Fig. 11.4, it can be observed that, with the full-feedforward scheme of grid
voltages, the harmonics in the injected grid currents can be effectively suppressed,
but the phase of the inverter output impedance is reduced, which weakens the
stability of the three-phase LCL-type grid-connected inverter under weak grid
condition. The interpretation of how the inverter output impedance is affected by
the full-feedforward scheme of grid voltages is given as follows.
As seen from Fig. 11.3c, the full-feedforward scheme introduces the transfer
function FF(s) on the PCC voltage [vpcc_ab(s)]. Since FF(s) = 1 when Gff(s) = 0,
the relationship between Zo_nff(s) and Zo_ff(s) can be derived from (11.8) that
Zo nff ðsÞ
Zo ff ðsÞ ¼ ð11:16Þ
FFðsÞ
It is apparent that compared with Zo_nff(s), a smaller |FF(s)| yields a larger

|Zo_ff(s)|, and a larger positive phase shift of FF(s) yields a larger negative phase
shift of Zo_ff(s).
According to (11.6), FF(s) is rewritten as
Gff ðsÞ
FFðsÞ ¼ 1 Gx1 ðsÞ ¼ 1 FVðsÞ ð11:17Þ
Gsi ðsÞ

where FVðsÞ ¼ Gff ðsÞGx1 ðsÞ Gsi ðsÞ. In (11.17), “1” represents the influence of
[vpcc_ab(s)] without feedforward scheme, and FV(s) represents the cancellation term
introduced by the full-feedforward scheme. Thus, as FV(s) approaching “1”, |FF(s)|
will be significantly reduced, which yields the effective suppression of the grid
current harmonics. However, due to the digital control delay, FV(s) can hardly be
“1”, and the full-feedforward scheme cannot completely eliminate the effect of
[vpcc_ab(s)].
Figure 11.7 gives the frequency response of FV(s). It is found that FV(s) is close
to “1” and is always lagging behind “1” with a small phase shift in the
low-frequency range. As the frequency goes high, the effect caused by the digital
Fig. 11.7 Frequency

response of FV(s)
11.3 Characteristics of the Inverter Output Impedance 259
control delay becomes apparent, the difference between FV(s) and “1” becomes
large, and the full-feedforward scheme is eventually impaired.
To better demonstrate the effect of the full-feedforward scheme, the vector
diagram of (11.17) in the low-frequency range is drawn, as shown in Fig. 11.8. It
can be seen that FV(jxk) is close to “1” but always lag behind “1” a little. For the
critical case, the amplitude of FV(jxk) equals to “1” and the phase lag is minimal,
while the remaining vector FF(jxk) will be leading “1” with 90°. And this will
cause Zo_ff(jxk) lagging behind Zo_nff(jxk) with 90° according to (11.16), which is in
agreement with Fig. 11.4 in the low-frequency range. The characteristics of other
frequency range can also be obtained with the vector diagram, which are not
interpreted here for the brevity.
Therefore, as seen from (11.16) and the analysis mentioned above, it can be
concluded that the characteristics of the inverter output impedance with the
full-feedforward scheme are significantly affected by the remaining vector FF(jxk),
including both the magnitude and direction.
11.4 Weighted-Feedforward Scheme of Grid Voltages
11.4.1 The Proposed Weighted-Feedforward

Scheme of Grid Voltages
Based on the previous analysis, the three-phase LCL-type grid-connected inverter

without feedforward scheme of grid voltages exhibits good stability under weak
grid condition, but its suppression of the grid current harmonics and unbalanced
components is not satisfactory. The full-feedforward scheme of grid voltages can
effectively suppress the grid current harmonics and unbalanced components, but it
tends to result in system instablity under weak grid condition. Therefore, it is
intuitive to try the trade-off between the harmonic suppression and stability by
introducing the weighted-coefficient Kf into the feedforward function Gff(s).
Figure 11.9 gives the vector diagram demonstration when Kf = 0.8. It can be
observed that the grid voltage cancellation term is reduced to 0.8FV(jxk) referring
to (11.17), and the corresponding remaining vector FF′(jxk) is lagging behind
FF(jxk). Therefore, the phase of Zo0 ff ðsÞ is boosted compared with that of Zo_ff(s),
which helps stabilize the grid-connected inverter under weak grid condition.
The Bode diagram of Z′o_ff(s) and Zg(s) are depicted in Fig. 11.10, where Kf is set
to 0, 0.5 and 1; and Lg varies up to 2.6 mH, which corresponds to a short-circuit ratio
Fig. 11.8 Vector diagram

demonstrating the effect of
full-feedforward scheme
Fig. 11.9 Vector diagram of

reduced feedforward scheme
effect

Zo0 ff ðsÞ and Zg(s)
of 10 [7]. As seen from Fig. 11.10, when Kf = 0, Z′o_ff(s) = Zo_nff(s); When Kf = 1,

Z′o_ff(s) = Zo_ff(s); When Kf = 0.5, the phase of Z′o_ff(s) is always above −90°, which
makes Du smaller than 180° and guarantees the stability of the grid-connected
inverter under weak grid condition. However, the magnitude of Z′o_ff(s) is signifi-
cantly reduced when Kf = 0.5, which means the grid current harmonics cannot be
effectively suppressed. Thus, introducing the same Kf in the whole frequency range
is not an effective trade-off between the harmonic suppression and stability of the
grid-connected inverter.
In addition, it can be observed from Fig. 11.10 that when Lg varies from 0 to
2.6 mH, the intersection of |Z′o_ff(s)| and |Zg(s)| only happens in the confined fre-
quency range. Therefore, it is better to selectively introduce Kf into the
full-feedforward function at the frequencies around the intersection, which is called
the weighted-feedforward scheme of grid voltages. And the Kf is individually
designed for each harmonic component to guarantee the stability and harmonic
suppression at the same time.
For the weighted-feedforward scheme of grid voltages, the corresponding har-
monic components of grid voltages are selectively extracted according to the grid
current harmonics to be suppressed. If the nth harmonic component stays in the
frequency range which is possible for the intersection of |Z′o_ff(s)| and |Zg(s)|, Kfn
11.4 Weighted-Feedforward Scheme of Grid Voltages 261
should be tuned to guarantee the stability of the grid-connected inverter. If the nth
harmonic component stays in the frequency range which is not possible for the
intersection of |Z′o_ff(s)| and |Zg(s)|, Kfn could be set to unity to maintain the excellent
harmonic suppression of the full-feedforward scheme of grid voltages.
11.4.2 Realization of the Weighted-Feedforward

Scheme of Grid Voltages
Figure 11.11 gives the realization of the weighted-feedforward scheme of grid

voltages, where the dash-line part is the multiblock-based prefilter used for the
selective extraction of the grid voltages. According to the harmonics of injected grid
currents to be suppressed, the corresponding harmonics of grid voltages are
extracted.
In Fig. 11.11, the resonance units are placed in the multiblock-based prefilter to
help extract the grid voltage harmonic components, which can be expressed as
xc xc
R þ n ðsÞ ¼ ; Rn ðsÞ ¼ ð11:18Þ
s jnx0 s þ jnx0
where n is the positive number, representing the frequency ratio between the har-
monic and fundamental components.
According to Fig. 11.11, the extracted component of the multiblock-based
prefilter can be expressed as
Ri ðsÞ
vi
ab ðsÞ ¼ eðsÞRi ðsÞ ¼ Pn vpcc ab ðsÞ ði 2 R þ Þ
1þ k¼1 ðR þ k ðsÞ þ Rk ðsÞÞ
ð11:19Þ
pcc
Fig. 11.11 Realization of the weighted-feedforward scheme

To achieve the trade-off between the stability and harmonic suppression, the
weighted coefficient Kfn is introduced. Therefore, the processed signal sent to the
full-feedforward function Gff(s) in Fig. 11.11 can be obtained, expressed as
Pn
þk k
k¼1 K f R þ k ðsÞ þ Kf Rk ðsÞ
vf ab ðsÞ ¼ P vpcc ab ðsÞ ð11:20Þ
1 þ nk¼1 ðR þ k ðsÞ þ Rk ðsÞÞ
Thus, the weighted-feedforward scheme is realized by sending vf_ab(s) into

Gff(s), which means the weighted-feedforward scheme equals to the
full-feedforward scheme with a prefilter whose expression is
Pn
k¼1Kfþ k R þ k ðsÞ þ Kfk Rk ðsÞ
Hf ðsÞ ¼ Pn ð11:21Þ
1 þ k¼1 ðR þ k ðsÞ þ Rk ðsÞÞ
And the weighted-feedforward function of grid voltages is
Gwgt ff ðsÞ ¼ Hf ðsÞGff ðsÞ ð11:22Þ
11.4.3 Tuning of the Weighted Coefficients
The harmonic and unbalanced component suppression and stability of the

grid-connected inverter with the weighted-feedforward scheme highly depends on
the selection of proportional coefficients Kfn . Thus, taking the parameters shown in
Table 11.1 as the example, the tuning procedure of Kfn is given as follows.
According to (11.9), the output impedance of the three-phase LCL-type
grid-connected inverter with the weighted-feedforward scheme can be obtained that

Zo wgt ff ðsÞ ¼
s2 L1 C þ sCHi1 ðsÞGinv ðsÞ þ 1 Gwgt ff ðsÞHv ðsÞGinv ðsÞ
ð11:23Þ
Assuming all the Kfn = 1, Zo_wgt_ff(s) can be drawn in Fig. 11.12. The Zo_ff(s),
which is the output impedance of the grid-connected inverter with full-feedforward
scheme, is also drawn in Fig. 11.12 for the comparison. As seen, the common
harmonics in the grid voltage, such as the fifth-, seventh-, eleventh-, thirteenth-, and
twenty-third-order components, are suppressed by the weighted-feedforward
scheme of grid voltages. Since all the Kfn = 1, Zo_wgt_ff(s) equals to Zo_ff(s) at
these harmonic frequencies.
Besides, it is observed from Fig. 11.12 that when Lg varies from 0 to 2.6 mH,
|Zo_wgt_ff(s)| and |Zg(s)| will not intersect at the frequencies including the

Zo_ff(s), Zo_wgt_ff(s), and Zg(s)
Fig. 11.13 Vector diagram

for the twenty-third-order
harmonic
fundamental, fifth-, seventh-, eleventh-, and thirteenth-order components.

Therefore, Kf1 , Kf5 , Kf7 , Kf11 , and Kf13 can be set to unity to keep the excellent
harmonic suppression of the full-feedforward scheme. However, it is possible for
the intersection appearing at the twenty-third-order harmonic frequency, and Du is
231° when Lg = 2.6 mH at this frequency, which means the grid-connected inverter
with the weighted-feedforward scheme will be unstable under weak grid condition.
Therefore, Kf23 should be further tuned to improve the stability of the
grid-connected inverter under weak grid condition.
The vector diagram is depicted in Fig. 11.13 to help tuning Kf23 , where
FV(jx23) is the cancellation term when full-feedforward scheme is used, and
FF(jx23) refers to the remaining vector of grid voltage disturbance. As seen, with
the reduced cancellation term Kf23 FV(jx23), the corresponding remaining vector
FF′(jx23) is lagging behind the original FF(jx23) by u. Therefore, the phase of
Zo_wgt_ff(s) given in Fig. 11.12 can be boosted by u to improve the stability of the
grid-connected inverter under weak grid condition. Assuming that the intended
phase margin is 20°, the phase of Zo_wgt_ff(jx23) is set to −70°. Because the original
phase of Zo_wgt_ff(jx23) is −141°, the boosted phase u should be set to 71°.
Substituting s = jx23 into (11.17) and calculating with the parameters given in
Table 11.1, it is obtained that
(a) (b)
Fig. 11.14 Bode diagram of Zo_ff(s), Zo_wgt_ff(s) and Zg(s)
Gff ðjx23 Þ
FFðjx23 Þ ¼ 1 Gx1 ðjx23 Þ ¼ 0:363\137:7 ð11:24Þ
Gsi ðjx23 Þ
From Fig. 11.13, it is obtained that
Kf23 Gff ðjx23 Þ

FF 0 ðjx23 Þ ¼ 1 Gx1 ðjx23 Þ ¼ A\ð137:7 uÞ ð11:25Þ
Gsi ðjx23 Þ
According to (11.24), it can be obtained that
Gff ðjx23 Þ
Gx1 ðjx23 Þ ¼ 1:292\ 10:9 ð11:26Þ
Gsi ðjx23 Þ
Substituting u = 71° and (11.26) into (11.25), it is obtained that
Kf23 ¼ 0:73
ð11:27Þ
A ¼ 0:193
Let Kf23 = 0.73 and redraw Zo_wgt_ff(s), as shown in Fig. 11.14a. As seen, the
phase of Zo_wgt_ff(s) at 1.15 kHz is boosted to −70° as expected and the stability of
the grid-connected inverter is improved.
Since the multiblock-based prefilter needs to be discretized for the implemen-
tation in the DSP, the resonance unit of it is discretized as [8]
xc
R þ n ðzÞ ¼ 12 1z1
Ts 23z1 16z2 þ 5z3 jnxo
xc ð11:28Þ
Rn ðzÞ ¼ 12 1z1
Ts 23z1 16z2 þ 5z3 þ jnxo
Substituting (11.28) into (11.21) and letting all the Kfn = 1 and z ¼ esTs , it can be
calculated that Hf(jx23) = 0.66. Therefore, taking the discretization approximation
into account, Kf23 is finally tuned as

Kf23 ¼ 0:73 Hf ðjx23 Þ 1:11 ð11:29Þ
Adopting the discretized weighted-feedforward function, the Bode diagram of

Zo_wgt_ff(s) is redrawn in Fig. 11.14b. It can be found that the phase of Zo_wgt_ff(s) at
1.15 kHz is boosted to −70° as expected.
Summarizing the tuning example depicted above, the weighted-feedforward
scheme of grid voltages selectively launches the full- or partial-feedforward
scheme, and the detailed tuning procedure is described as follows:
1. According to the grid current harmonics to be suppressed, the corresponding
harmonic components of grid voltages are selectively extracted.
2. In the range of the grid impedance variation, if the extracted nth harmonic
component stays in the frequency range which is possible for the intersection of
|Zg(s)| and |Zo(s)| while the |∠Zg(j2pfn) − ∠Zo(j2pfn)| > 180°, it should be
proportionally reduced with Kfn to boost ∠Zo(j2pfn) to improve the stability of
the grid-connected inverter under weak grid condition. Kfn is initially tuned with
the help of vector diagram according to (11.17).
3. If the nth harmonic component stays in the frequency range which is not pos-
sible for the intersection of |Zg(s)| and |Zo(s)|, it should be directly sent to the
full-feedforward function, which means Kfn is initially set to 1, to keep the
excellent harmonic suppression of the full-feedforward scheme of grid voltages.
4. Finally, the Kfn is adjusted according to the discretization approximation of the
multiblock-based prefilter as shown in (11.29).
Using the same prototype given in Chap. 7, the correctness of the theoretical
analysis and the effectiveness of the proposed weighted-feedforward scheme of grid
voltages are verified with the experimental results. The main parameters of the
prototype are given in Table 11.1. In the experiment, the injected grid current
regulator adopts the PR regulator, and the grid-connected inverter with no, full-, and
weighted-feedforward schemes are all investigated.
11.5.1 Stability Test
To verify the stability of the three-phase LCL-type grid-connected inverter under

weak grid condition, Lg is in series with the real grid in the laboratory to emulate the
line inductor and transformer leakage inductor under weak grid condition.
Figure 11.15 shows the experimental results of the stability test. Figure 11.15a
shows the experimental result when Lg = 2.6 mH and no feedforward scheme is
adopted in the grid-connected inverter. The THD of the injected grid currents is
3.44%. When Lg varies from 0 to 2.6 mH, the grid-connected inverter without
feedforward scheme always keeps stable. Figure 11.15b shows the experimental
results when Lg = 0.3 mH and the full-feedforward scheme is adopted. There is an
evident oscillation in the injected grid currents, and as Lg increases, the
grid-connected inverter becomes unstable. This is in agreement with the conclusion
that the grid-connected inverter with the full-feedforward scheme tends to be
unstable under weak grid condition given in the previous section. Figure 11.15c
shows the experimental result when Lg = 2.6 mH and the weighted-feedforward
scheme is adopted. The THD of the injected grid currents is 2.04%. When Lg varies
from 0 to 2.6 mH, the grid-connected inverter with the weighted-feedforward
scheme still keeps stable, which verifies the improved stability of the
grid-connected inverter by adopting the weighted-feedforward scheme of grid
voltages.
11.5.2 Harmonic Suppression Test
To perform an accurate evaluation of the harmonic suppression for the

grid-connected inverter using the weighted-feedforward scheme of grid voltages,
the grid voltages are simulated by a programmable ac source (Chroma 6590). Lg is
in series with the programmable ac source to emulate the weak grid. The magni-
tudes of the emulated grid voltage harmonics, which are the fifth-, seventh-, ele-
venth-, thirteenth-, and twenty-third-order harmonics, with respective to the
fundamental component of the grid voltages are 5%, 2%, 2%, and 1%, respectively,
and the corresponding phases are 180°, 0°, 0°, 0°, and 0°. Figure 11.16 gives the
experimental results of the harmonic suppression test. Figure 11.16a, b shows the
experimental results of the grid-connected inverter with no feedforward scheme
when Lg = 0 and 2.6 mH, respectively. The THD of the injected grid currents are
25.65% and 21.14%, respectively. Figure 11.16c, d shows the experimental results
of the grid-connected inverter with the full-feedforward scheme and
weighted-feedforward scheme, respectively, when Lg = 0. The THD of the injected
grid currents are 5.22% and 5.16%, respectively. Figure 11.16e shows the exper-
imental result of the grid-connected inverter with the weighted-feedforward scheme
when Lg = 2.6 mH. The THD of the injected grid currents is 5.03%. The harmonic
spectrum of the injected grid currents shown in Fig. 11.16 are given in Fig. 11.17.

results for stability test PCC
vpcc_a vpcc_b
i2_a i2_b
Time: [5 ms/div]
(a) No feedforward ( L g =2.6mH )
vpcc_a vpcc_b
i2_a i2_b
Time: [5 ms/div]
(b) Full - feedforward ( Lg =0.3 mH)
vpcc_a vpcc_b
i2_a i2_b
Time: [5 ms/div]
(c) Weighted - feedforward ( L g =2.6 mH )
From Figs. 11.15, 11.16 and 11.17, it is obvious that the grid-connected inverter
without feedforward scheme exhibits good stability under weak grid condition,
while its suppression of grid current harmonics is poor. The grid-connected inverter
with the full-feedforward scheme can effectively suppress the injected grid current
vpcc_a vpcc_b vpcc_c vpcc_a vpcc_b vpcc_c
i2_a i2_b i2_c i2_a i2_b i2_c
(a) No feedforward (Lg=0) (b) No feedforward (Lg=2.6mH)
vpcc_a vpcc_b vpcc_c vpcc_a vpcc_b vpcc_c
i2_a i2_b i2_c i2_a i2_b i2_c
(c) Full-feedforward (Lg=0) (d) Weighted-feedforward (Lg=0)
vpcc_a vpcc_b vpcc_c
i2_a i2_b i2_c
Time: [5 ms/div]
(e) Weighted-feedforward (Lg=2.6mH)
Fig. 11.16 Experimental results for harmonic suppression test PCC voltage: 200 V/div, injected
harmonics, but it tends to be unstable under weak grid condition. The

grid-connected inverter with the proposed weighted-feedforward scheme can
effectively suppress the injected grid current harmonics, and its stability under weak
grid condition is also guaranteed.
11.6 Summary 269
20 20
Harmonic percentage (%)

Harmonic percentage (%)
No feedforward No feedforward
Full-feedforward Weighted-feedforward
16 16
Weighted-feedforward
12 12
8 8
4 4
0
5 7 11 13 23 5 7 11 13 23
Harmonic order Harmonic order
(a) Lg=0 (b) L g =2.6mH
Fig. 11.17 Harmonic spectrum of the injected grid currents with no feedforward,
full-feedforward, and weighted-feedforward schemes
11.6 Summary
In this chapter, the output impedance of the three-phase LCL-type grid-connected

inverter has been derived, and its characteristics are analyzed. After that, the sta-
bility of the grid-connected inverter under weak grid condition is investigated with
the impedance-based stability criterion. It is pointed out that the grid-connected
inverter with full-feedforward scheme tends to be unstable under weak grid con-
dition due to its increased negative phase shift of the output impedance. Therefore,
the weighted-feedforward scheme of grid voltages has been proposed to improve
the stability of grid-connected inverter. With the weighted-feedforward scheme, the
extracted and weighted grid voltages are fed forward, the injected grid current
References
2. Buso, S., Mattavelli, P.: Digital Control in Power Electronics. Morgan and Claypool
Publishers, Seattle, WA (2006)
3. Corradini, L., Stefanutti, W., Mattavelli, P.: Analysis of multi-sampled current control for
active filters. IEEE Trans. Ind. Applicat. 44(6), 1785–1794 (2008)
4. Yang, D., Ruan, X., Wu, H.: Impedance shaping of the grid-connected inverter with LCL filter
to improve its adaptability to the weak grid condition. IEEE Trans. Power Electron. 29(11),
5795–5805 (2014)
Electron. 26(11), 3075–3078 (2011)
6. Pan, D., Ruan, X., Bao, C., Li, W., Wang, X.: Capacitor-current-feedback active damping with
reduced computation delay for improving robustness of LCL-type grid-connected inverter.
grid-connected inverters for a large set of grid impedance values. IEEE Trans. Power Electron.
21(1), 263–272 (2006)
8. Li, W., Ruan, X., Bao, C., Pan, D., Wang, X.: Grid synchronization systems of three-phase
grid-connected power converters: a complex-vector-filter perspective. IEEE Trans. Ind.
Electron. 61(4), 1855–1870 (2014)
Chapter 12
Prefilter-Based Synchronous Reference
Frame Phase-Locked Loop Techniques
Abstract Due to the significance of extracting the grid voltage information, the
grid synchronization system plays an important role in the control of grid-connected
power converters, and various grid voltage synchronization schemes have been
proposed. This chapter adopts the complex-vector-filter method (CVFM) to analyze
the grid synchronization systems. With this method, the pairs of scalar signals, for
example, the a- and b-axis components in the stationary a-b frame, are combined
into one complex vector. As a consequence, the grid synchronization systems can
be described with the complex transfer functions, which is very convenient to
evaluate the steady-state performance, for example, the fundamental and harmonic
sequences decoupling/cancellation, and dynamic performance of these systems.
Besides, the CVFM also provides a more generalized perspective to understand and
develop the grid synchronization systems. Therefore, some of the representative
systems are reanalyzed with the CVFM in this chapter. A generalized second-order
complex-vector filter and a third-order complex-vector filter are proposed with the
CVFM to achieve better dynamic performance or higher harmonic attenuation.
Moreover, a brief comparison of the complex-vector filters analyzed in this chapter
is presented. The effectiveness of the CVFM and the proposed two complex-vector
filters are verified by the simulation and experimental results.

Keywords Complex-vector filter Distributed power generation Grid synchro-

nization Power converters Phase-locked loop
12.1 Introduction
In order to ensure a high-quality power to be injected into the power grid and to
control the active power and reactive power flexibly according to the power dis-
patching demands, the grid current of the grid-connected inverter is required to be
synchronized with the grid voltage, as specified in IEEE std. 1547-2003 and State
Grid Corporation of China enterprise standard Q/GDW 480-2010 “Technical Rule
for Distributed Resources Connected to Power Grid” [1–5]. In the previous
272 12 Prefilter-Based Synchronous Reference Frame …
chapters, the grid-current reference is assumed to be a sinusoidal signal which is

synchronized with the grid voltage. However, due to the inevitable voltage fluc-
tuation in a real grid, a phase-locked loop (PLL) is needed to obtain the amplitude,
frequency, and phase angle of the grid voltage. Then, based on this information, the
grid-current reference can be determined, and the synchronization between the grid
current and the grid voltage can be achieved. Thus, the performance of the PLL is
highly related to the control performance of the grid current loop.
Generally, the performance of the PLL is evaluated from two aspects, namely the
dynamic performance and the harmonic attenuation ability. Specifically, the
dynamic performance of the PLL will affect the response of the grid-connected
inverter under a rapid change of the grid voltage; the harmonic attenuation ability
will affect the total harmonic distortion (THD) of the grid current reference under a
distorted grid voltage. The commonly used PLLs include the zero-crossing PLL
(ZC-PLL) [6] and the synchronous reference frame PLL (SRF-PLL) [7, 8]. Through
the zero-crossing detection of the grid voltage, the ZC-PLL transforms the sinu-
soidal grid voltage into a square wave signal, and then extracts the frequency and
phase angle of the grid voltage according to the instants when the jump edges of the
square wave occur. The ZC-PLL has the advantage of simple implementation, but it
is easily affected by the grid voltage harmonics. The SRF-PLL is based on the
real-time sampling of the instantaneous value of the grid voltage, and it exhibits
better attenuation of the grid voltage harmonics. Thus, the SRF-PLL has been
widely used in single-phase and three-phase grid-connected inverters. However, the
SRF-PLL has poor ability of attenuating the fundamental unbalanced components
of the grid voltage. To overcome this drawback, a prefilter is usually introduced into
the SRF-PLL to filter the unbalanced components of the grid voltage [9]. Due to the
dual-input/dual-output nature, for example, the a- and b-axis components in the
stationary a-b frame and the ubiquitous cross-coupling terms between the two axes
in the prefilter-based SRF-PLL, it is not easy to analyze the prefilters with the scalar
notation. Nevertheless, because of the compact representation and easy algebraic
manipulation, the complex-vector-filter method (CVFM) can be adopted to analyze
the prefilters. In this chapter, the operation principle of SRF-PLL is briefly intro-
duced, and the CVFM is adopted to derive the various prefilters and to reveal the
relationship among them. Moreover, a generalized second-order complex-vector
filter (GSO-CVF) with faster dynamic response and a third-order complex-vector
filter (TO-CVF) with higher harmonic attenuation are proposed with the CVFM,
which are useful to improve the dynamic performance and the harmonic attenuation
ability of the PLL for the grid-connected inverter [10].
12.2 Operation Principle of SRF-PLL
Figure 12.1 shows the basic principle of the PLL. It is composed of a phase detector
(PD), a loop filter (LF), and a voltage-controlled oscillator (VCO). As seen, the
input signal ui(t) and the output signal uo(t) are sent into the PD, and PD compares
12.2 Operation Principle of SRF-PLL 273
Fig. 12.1 Schematic diagram ui(t) ue(t) uc(t) uo(t)

of PLL PD LF VCO
the phases of ui(t) and uo(t). The resultant error ue(t) is processed through the LF.
uc(t) is the output of LF, and it is sent into the VCO. The frequency of uo(t) is
regulated by the VCO, which ensures the output signal of PLL to track the input
signals via the closed loop.
Figure 12.2a shows the principle of SRF-PLL for three-phase grid-connected
inverter, where PD is depicted in the dash-line frame, VCO is depicted in the
shadow, and PI regulator is commonly employed for LF.
The three-phase grid voltages are defined as
8
< vga ¼ Vm cos h
vgb ¼ Vm cosðh 2p=3Þ ð12:1Þ
:
vgc ¼ Vm cosðh þ 2p=3Þ
where Vm and h are the amplitude and phase of grid voltages, respectively.
As seen from Fig. 12.2a, the three-phase grid voltages in stationary a-b-c frame
are transformed into stationary a-b frame, and then transformed into synchronous d-
q frame. The transformation formulas are [11]
2 3
vga
va 2 1 1=2
pffiffiffi 1=2
pffiffiffi 4 vgb 5
¼ ð12:2Þ
vb 3 0 3 2 3 2
vgc

vd cos h0 sin h0 va
¼ ð12:3Þ
vq sin h0 cos h0 vb
Based on (12.2) and (12.3), the d- and q-axis scalar notations of grid voltages
can be obtained from (12.1) and expressed as
Fig. 12.2 Schematic diagram PD

and model of SRF-PLL vga v vq 1 '
vgb abc PI s '
vgc v vd
dq VCO
(a) Schematic diagram of SRF-PLL
+ vq ' 1 '
Vm PI s
(b) Model of SRF-PLL

vd ¼ Vm cosðh h0 Þ
ð12:4Þ
vq ¼ Vm sinðh h0 Þ
where h′ is the phase angle of the grid voltage extracted by SRF-PLL. When h′ is
close to h, (12.4) can be approximated as

vd ¼ Vm
ð12:5Þ
vq ¼ Vm ðh h0 Þ
As seen in (12.5), vd is the grid voltage amplitude extracted by SRF-PLL; vq is

proportional to the difference of the real grid voltage phase h and the extracted
phase h′ by SRF-PLL. Then, vq is sent to PI regulator, yielding the grid voltage
angular frequency x′. Via an integrator, h′ which is used for axis transformation is
obtained. According to (12.5) and Fig. 12.2a, the linear model of SRF-PLL is
plotted, as shown in Fig. 12.2b. As seen, the grid voltage phase h is used as the
command, and the output phase h′ of SRF-PLL tracks h by the closed loop, yielding
the grid voltage synchronization.
As for single-phase grid-connected inverter, in order to adopt SRF-PLL, an
orthogonal system generation (OSG) is needed to fabricate a couple of orthogonal
components [12], as shown in Fig. 12.3.
12.3 Prefilter-Based SRF-PLL
When the grid voltages contain large amount of harmonics and unbalanced com-
ponents, the output grid-voltage amplitude, frequency, and phase angle of SRF-PLL
shown in Fig. 12.2 will be distorted. To overcome this drawback, we can adjust the
PI regulator parameters to reduce the loop gain of the PLL [7] or introduce extended
loop filters, e.g., adaptive notch filter [13], second-order lead compensator [14],
sliding Goertzel transform [15], and moving average filter [16]. However, since the
extracted amplitude vd is not processed by the extended loop filter, vd will still be
affected by the harmonics and unbalanced components even if h′ is exactly the same
as the phase angle of fundamental positive-sequence components of the grid volt-
ages. Thus, further filtering is still needed for vd.
As the penetration of distributed power generation systems (DPGSs) goes high,
the related grid codes, regarding power quality, safe running, fault ride-through, and
so on are getting more stringent [1, 4]. According to the grid codes, not only the
Fig. 12.3 Schematic diagram

of SRF-PLL for single-phase v vq 1 '
grid-connected inverter vg PI s
OSG '
v vd
dq
12.3 Prefilter-Based SRF-PLL 275
frequency and phase angle, but also the amplitudes of fundamental positive- and
negative-sequence components (FPC and FNC) of the grid voltages are required in
the control of power converters to guarantee the dynamic grid voltage support or
other related issues such as the power-oscillation elimination under grid fault
condition [16–18]. In order to extract the amplitude, frequency, and phase angle of
the grid voltages fast and accurately, the grid voltages can be filtered before they are
sent into SRF-PLL. For the three-phase three-wire system, the prefilter is usually
placed in the stationary a-b frame, as shown in Fig. 12.4. This method is called the
prefilter-based SRF-PLL.
Recently, the prefilter-based SRF-PLL has been widely studied in the literatures.
The typical prefilters include the positive-sequence filter based on the generalized
integrator [19], the nonlinear adaptive filters proposed in the enhanced PLL [20]
and the quadrature PLL [21], the adaptive filter based on the second-order gener-
alized integrator [22–24], the prefilter in the decoupled double SRF-PLL [25], the
complex-coefficient prefilter [26], and the prefilters based on the delayed signal
cancellation [27–32].
12.3.1 Complex-Vector-Filter Method (CVFM)
As shown in Fig. 12.4, by filtering the a- and b-axis parts of the grid voltages, i.e.,
vga and vgb, with the prefilter, va and vb are obtained. Therefore, the prefilter is a
dual-input/dual-output system. If the a- and b-axis paths of the prefilter are inde-
pendent, the scalar notation can be used to analyze a- and b-axis components,
respectively. However, if there is cross coupling between these two axes, four scalar
transfer functions, i.e., Haa(s), Hbb(s), Hab(s), and Hba(s), are needed to describe the
dual-input/dual-output prefilter. Obviously, this is too complicated. Considering the
symmetry and quadrature between the a- and b-axis, the inputs and outputs of the
prefilter can be represented by the complex vectors. In this way, the prefilter can be
simplified into one single-input/single-output complex-vector filter [10].
In the stationary a-b frame, the s-domain mapping of the complex vector to
scalar notation is shown as
vgab ðsÞ ¼ vga ðsÞ þ jvgb ðsÞ ð12:6Þ
where vgab(s) represents the complex vector of the grid voltages, vga(s) and
vgb(s) are the corresponding a- and b-axis scalar notations.
vga vg v vq '
1
vgb abc PI s
vg Prefilter '
vgc v vd
dq
Fig. 12.4 Schematic diagram of prefilter-based SRF-PLL

vg (s) R(s) v (s)
Q(s)
Q(s)
vg (s) H(s) v (s) vg (s) R(s) v (s)
(a) Complex signal-flow graph (b) Scalar transfer-function implementation
Fig. 12.5 Schematic diagram of the complex-vector filter
The complex signal-flow graph [33] of a complex-vector filter is given in

Fig. 12.5a, where H(s) is the complex transfer function of this complex-vector
filter, and it can be expressed in form of
HðsÞ ¼ RðsÞ þ jQðsÞ ð12:7Þ
where R(s) and Q(s) are the scalar transfer functions.

According to (12.6), (12.7), and Fig. 12.5a, the output of this complex-vector
filter is derived as
vab ðsÞ ¼ HðsÞvgab ðsÞ

¼ RðsÞvga ðsÞ QðsÞvgb ðsÞ þ j QðsÞvga ðsÞ þ RðsÞvgb ðsÞ ð12:8Þ
¼ va ðsÞ þ jvb ðsÞ
where
va ðsÞ ¼ RðsÞvga ðsÞ QðsÞvgb ðsÞ ð12:9aÞ
vb ðsÞ ¼ QðsÞvga ðsÞ þ RðsÞvgb ðsÞ ð12:9bÞ
According to (12.9a, 12.9b), the scalar transfer-function implementation of H(s)

is given in Fig. 12.5b.
From the above analysis, it can be seen that with the CVFM, the dual-input/
dual-output and cross-coupled prefilter can be described with a single complex
transfer function H(s). Moreover, observing (12.7) and Fig. 12.5b, it can be found
that it is the cross-coupling terms that give rise to the imaginary part of H(s). In
particular, it should be noted that, for the magnitude/phase-frequency plots of the
complex-vector filter, the response to the positive frequencies corresponds to the
positive-sequence input complex vectors which are rotating forward, and the
response to the negative frequencies corresponds to the negative-sequence input
complex vectors which are rotating backward. This feature is very helpful in
evaluating the sequence selectivity of the prefilter-based SRF-PLL.
12.3.2 Derivation of the Prefilters with the CVFM
With the help of the CVFM depicted previously, the prefilter can be seen as a
complex-vector filter and described with the complex transfer function. In this
section, some of the representative prefilters are derived and analyzed in their
complex-vector-filter perspective. The features and relationships among them are
also interpreted to help designing and improving the prefilters.
1. First-Order Complex-Vector Filter
As is widely known, a typical first-order low-pass scalar filter [34], which has a
unity gain for the dc component while attenuating the harmonics, is in form of
xc
H 0 ðsÞ ¼ ð12:10Þ
s þ xc
where xc is the cutoff angular frequency, and it is set to 0.707xo. Here, xo = 2pfo
is the angular frequency of the FPC of the grid voltages, and fo = 50 Hz is the
fundamental positive frequency of the grid voltages.
The magnitude/phase-frequency plot of (12.10) is shown in Fig. 12.6. As seen,
this first-order scalar filter is not a competent prefilter for SRF-PLL because of the
non-unity gain together with the phase delay at the fundamental positive frequency
fo and the sequence-nonselective frequency response.
In order to achieve unity gain and zero phase delay at fo, it is intuitive to put
forward a complex-vector filter by right frequency shifting with 50 Hz. Therefore,
Fig. 12.6 Frequency 1.2

response of the first-order
|H'(j2 f)|
low-pass scalar filter 0.8
0.4
0.0
90
∠H'(j2 f) (°)
60
30
0
30
60 = 0.707· o
c
90
200 150 100 50 0 50 100 150 200
Frequency (Hz)
1.2
|H(j2 f)|
0.8
0.4
0.0
90
60
∠H(j2 f) (°)
30
0
30
c=0.707· o
60
c= o
90
200 150 100 50 0 50 100 150 200
Frequency (Hz)
Fig. 12.7 Frequency response of the first-order complex-vector filter
c c
vg (s) v (s) vg (s) v (s)
s j o+ c s j o
(a) Complex signal-flow graph (b) Equivalent complex signal-flow graph
Fig. 12.8 Schematic diagram of the first-order complex-vector filter
the first-order complex vector can be obtained by substituting s = s − jxo into

(12.10), i.e.,
xc
HðsÞ ¼ H 0 ðs jxo Þ ¼ ð12:11Þ
s jxo þ xc
The magnitude/phase-frequency plot of (12.11) is given in Fig. 12.7. As seen, it

is obvious that this first-order complex-vector filter has a unity gain and no phase
shift is introduced at fo. Taking the inverse Laplace transform of (12.11) gives the
impulse response of this first-order complex-vector filter, i.e.,
hðtÞ ¼ xc ejxo txc t ¼ xc exc t ðcos xo t þ j sin xo tÞ ð12:12Þ
The real and imaginary parts of (12.12) correspond to the impulse responses at the
a- and b-axes, respectively, and both of them decay exponentially with the index of
xc. Obviously, a smaller xc leads to slower dynamic response, and it can be found
from Fig. 12.7 that a smaller xc leads to better fundamental negative-sequence and
harmonic attenuation. Therefore, a trade-off between the dynamic response and
harmonic attenuation is usually made when designing this first-order
complex-vector filter.
Fig. 12.9 Scalar (a)

implementation of the vg (s) e (s) s y (s) v (s)
first-order complex-vector 2 2 c
filter s+ o
s 2+ o
2
s 2+ o
2
vg (s) s y (s) v (s)

2 2 c
e (s) s+ o
(b)
vg (s) e (s) y (s) v (s)
1 c
s
vg (s) e (s) v (s)

1
c
s y (s)
The implementation of the first-order complex-vector filter can be derived as

follows. A complex signal-flow graph of (12.11) is given in Fig. 12.8a. By intro-
ducing a negative-feedback path, Fig. 12.8a can be equivalently transformed into
Fig. 12.8b. In Fig. 12.8b, 1/(s − jxo) can be rewritten as
1 s þ jxo s xo
¼ 2 ¼ 2 þj 2 ð12:13Þ
s jxo s þ xo s þ xo
2 2 s þ x2o
Recalling (12.7) and Fig. 12.5b, the scalar implementation of (12.11) is given in
Fig. 12.9a, where the shaded part is the scalar representation of (12.13). Comparing
Fig. 12.9a with the positive-sequence filter proposed in [19], it will be found that
they are, in fact, the same, which means that the positive-sequence filter is essen-
tially a first-order complex-vector filter.
From Fig. 12.9a, the following equation is obtained:
ea ðsÞ þ jeb ðsÞ

ya ðsÞ þ jyb ðsÞ ¼ ð12:14Þ
s jxo

sya ðsÞ þ xo yb ðsÞ þ j syb ðsÞ xo ya ðsÞ ¼ ea ðsÞ þ jeb ðsÞ ð12:15Þ
Examining the real and imaginary parts in both sides of (12.15), it can be
obtained that

sya ðsÞ þ xo yb ðsÞ ¼ ea ðsÞ
ð12:16Þ
syb ðsÞ xo ya ðsÞ ¼ eb ðsÞ
which then leads to

ya ðsÞ ¼ ea ðsÞ xo yb ðsÞ 1s
ð12:17Þ
yb ðsÞ ¼ eb ðsÞ þ xo ya ðsÞ 1s
According to (12.17), Fig. 12.9a can be further equivalently transformed into

Fig. 12.9b, which presents a relatively simple alternative to implement the
first-order complex-vector filter.
2. Second-Order Complex-Vector Filter
As shown in Fig. 12.7, at f = −50 Hz, the magnitude of the first-order
complex-vector filter is smaller than 1, but not zero. That means the first-order
complex-vector filter can only attenuate but not eliminate the FNC of the grid
voltages. Therefore, its performance might not be satisfactory under severely
unbalanced grid voltage conditions. Adding a complex zero of sz = − jxo into
(12.11) will immediately yield a zero gain at the fundamental negative frequency
which indicates the elimination of the FNC, but the harmonic attenuation of this
complex filter will be obviously impaired due to the increased order of the
numerator in the resulted complex transfer function. Thus, taking the harmonic
attenuation and elimination of the FNC into account, a second-order
complex-vector filter (SO-CVF) with a complex zero of sz = −jxo can be given as
xg ðs þ jxo Þ
HðsÞ ¼ ð12:18Þ
s2 þ 2fxn s þ x2n
where f is the damping ratio, xn is the undamped natural angular frequency, and xg
is an adjustable gain. For the extraction of the FPC of the grid voltages, it is
required that
xg ðjxo þ jxo Þ
Hðjxo Þ ¼ ¼1 ð12:19Þ
ðjxo Þ2 þ 2fxn jxo þ x2n
Manipulating (12.19), it can be obtained that
j2xg x2o ¼ x2n x2o þ j2fxn x2o ð12:20Þ
Examining the real and imaginary parts in both sides of (12.20) gives
xn ¼ xo ; xg ¼ fxo ð12:21Þ
2.0 = 0.3
= 0.707
= 1.5
1.5
|H( j2 f )| 1.0
0.5
0.0
200 150 100 50 0 50 100 150 200
Frequency (Hz)
Fig. 12.10 Magnitude-frequency plot of the SO-CVF
fxo ðs þ jxo Þ
HðsÞ ¼ ð12:22Þ
s2þ 2fxo s þ x2o
The magnitude-frequency plot of (12.22) is given in Fig. 12.10. As expected, the

SO-CVF has a zero gain at the fundamental negative frequency and a unity gain at
the fundamental positive frequency. From Fig. 12.10, it is also found that a smaller
f leads to better harmonic attenuation. In practical, f is usually set to 0.707 for the
optimum dynamic performance [22].
The implementation of this SO-CVF is very flexible, which includes the prefilter
based on the second-order generalized integrator [22], the prefilter in the decoupled
double SRF-PLL [25], and the two-module complex-coefficient prefilter [26]. The
implementation of the two-module complex-coefficient prefilter is given in
Fig. 12.11. The first-order complex-vector filter for extracting the FPC has been
given in (12.11). Accordingly, its counterpart for extracting the FNC can be
obtained by conjugating (12.11). Introducing the cross-feedback structure, which
prevents the inputs of each complex-vector filter from the unwanted sequence
component, yields the complex signal-flow graph depicted in Fig. 12.11.
3. Multiblock High-Order Complex-Vector Filter
Previous analysis shows that the SO-CVF can extract the FPC and eliminate the
FNC at the same time. However, the SO-CVF can only attenuate but not eliminate
the harmonics of the grid voltages. To overcome this drawback, a multiblock
high-order complex-vector filter can be adopted. Compared with the SO-CVF, the
multiblock-based prefilter has a better performance when the harmonics to be
attenuated are close to the fundamental frequency. Moreover, multiblock-based
prefilter is capable of extracting multiple harmonic components, which is a
promising feature for the selective harmonic compensation in active power filter.
Fig. 12.11 Two-module c

complex-coefficient prefilter vg (s) v+1 (s)
s j o+ c
c
v 1 (s)
s+j o+ c
Fig. 12.12 Schematic c

diagram of the vg (s) v (s)
s j o
complex-vector filter
(a) First-order complex-vector filter
vg (s) e(s) v+1 (s)

R+1(s)
v 1 (s)
R 1(s)
v (s)
+n
v (s)
R+n(s)
v n (s)
R n(s)
(b) multiblock-based complex-vector filter
Multiblock-based prefilter can be seen as the extension of the primary prefilter.

For interpretation, the first-order complex-vector filter of the unity-feedback form
given in Fig. 12.8b is redrawn in Fig. 12.12a. As seen, the first-order
complex-vector prefilter adopts a resonator of R(s) = xc/(s − jxo). To eliminate
the FNC and harmonic components, the resonators tuned at the corresponding fre-
quencies are introduced in the loop, yielding the multiblock-based complex-vector
prefilter, as shown in Fig. 12.12b. These resonators are expressed as

R þ n ðsÞ ¼ sjnx
xc
o
ð12:23Þ
Rn ðsÞ ¼ s þ jnxo
xc
where n is a positive integer, which represents the ratio of the harmonic frequency
to the fundamental positive frequency.
Referring to Fig. 12.12b, the multiblock-based prefilter can be described as
vi
ab ðsÞ ¼ eðsÞRi ðsÞ
Ri ðsÞ
¼ Pn vgab ðsÞ , H i ðsÞvgab ðsÞ ði 2 R þ Þ
1þ k¼1 ð R þ k ðsÞ þ Rk ðsÞÞ
ð12:24Þ
where H–i(s) is the complex transfer function for the ith-component extraction and
is expressed as
Ri ðsÞ
H i ðsÞ ¼ Pn ð12:25Þ
1þ k¼1 R þ k ðsÞ þ Rk ðsÞÞ
ð
In particular, for the two-block prefilter with R+1(s) and R−1(s), the complex
transfer function for the FPC extraction can be expressed as
R þ 1 ðsÞ xc ðs þ jxo Þ
H þ 1 ðsÞ ¼ ¼ ð12:26Þ
1 þ R þ 1 ðsÞ þ R1 ðsÞ s2 þ 2xc s þ x2o
which is the same as the SO-CVF given in (12.22) when letting xc = fxo.
Therefore, the SO-CVF can be regarded as a special case of multiblock-based
prefilter, and xc is still set to 0.707xo in the following analysis of the
multiblock-based prefilter.
Since the more resonators introduced, the higher the complex transfer function
order becomes, so the pole-zero map of the complex transfer function is drawn to
investigate the performance of the multiblock-based prefilter. Four multiblock
prefilters are investigated, which are the SO-CVF with R+1(s) and R−1(s); the
three-block-based filter with R+1(s), R−1(s), and R−5(s); the three-block-based filter
with R+1(s), R−1(s), and R+2(s); and the six-block- based filter eliminating most of
the common low-order harmonics with R+1(s), R−1(s), R−5(s), R+7(s), R−11(s), and
R+13(s). Their complex transfer functions for the FPC extraction can be easily
obtained from (12.25), and the pole-zero maps of these complex transfer functions
are drawn in Fig. 12.13.
From Fig. 12.13a, it can be seen that there are two poles and one zero in the
SO-CVF. The poles are p1,2 = −222 ± j222. The zero is located at −xo in the
imaginary axis which indicates the elimination of the FNC. In Fig. 12.13b–d, there
are three, three, and six poles and two, two, and five zeros, respectively. From
Fig. 12.13a, b, d, it can be observed that the real parts of the poles of each complex
transfer function are approximately the same, which indicates that the decaying
time constants of these prefilters are similar. Comparing Fig. 12.13b, c, it is found
that, although they both have three poles, a pole close to the imaginary axis appears
in Fig. 12.13c, and this pole will cause the slow dynamic response of the prefilter.
The appearance of this slow pole in Fig. 12.13c is because the resonators of
R+1(s) and R+2(s) are tuned too close that the interaction between them becomes
significant. This conclusion is consistent with the comments presented in [24] and
will be verified by the simulation results in Sect. 12.6. It is noted that the pole-zero
maps shown in Fig. 12.13 are asymmetric. This is due to the fact that the inputs and
outputs of the transfer function are no longer scalar signals but complex vectors.
To further investigate the harmonic attenuation of the multiblock-based prefilter,
the magnitude-frequency plot of the six-block-based prefilter is taken as an example
and depicted in Fig. 12.14, from which the multiple-harmonic elimination and
inherent high-frequency harmonic attenuation features can be easily observed.
5k 5k
4k 4k
3k 3k
Imaginary Axis
Imaginary Axis
2k 2k
1k 1k
0 0
1k 1k
2k 2k
3k 3k
4k 4k
5k 5k
500 400 300 200 100 0 50 500 400 300 200 100 0 50
Real Axis Real Axis
(a) R+1(s) and R 1(s) (b) R+1(s), R 1(s), and R 5(s)
5k 5k
4k 4k
3k Causing slow 3k
Imaginary Axis
Imaginary Axis
2k dynamic performance 2k
1k 1k
0 0
1k 1k
2k 2k
3k 3k
4k 4k
5k 5k
500 400 300 200 100 0 50 500 400 300 200 100 0 50
Real Axis Real Axis
(c) R+1(s), R 1(s), and R+2(s) (d) R+1(s), R 1(s), R 5(s), R+7(s),
R 11(s), and R+13(s)
Fig. 12.13 Pole-zero maps of the multiblock-based prefilter
1.2
1.0
0.8
|H+1( j2 f )|
0.6
0.4
0.2
0.0
1200 800 400 0 400 800 1200
Frequency (Hz)
Fig. 12.14 Magnitude-frequency plot of the six-block-based prefilter

Moreover, there are still other structures to implement the multiblock-based

prefilter [24, 26, 35]. From the analysis presented earlier, it can be generally con-
cluded from the complex-vector filter perspective that the zeros in the complex
transfer functions are introduced to eliminate the unwanted components, and the
poles together with the zeros in the transfer functions determine the dynamic per-
formance and inherent filtering characteristic of the multiblock-based prefilters.
12.4 Generalized Second-Order Complex-Vector Filter
As shown in (12.22), the undamped natural angular frequency xn is fixed at xo.

Thus, there is only one freedom, which is the damping ratio f, to tune this SO-CVF.
For the optimum dynamic performance, f is usually set to 0.707. It is apparent that a
faster dynamic performance will be achieved for the second-order complex-vector
prefilter if a larger xn can be tuned. However, an immediate problem is that H(jxo)
no longer equals unity which can be seen from the derivation of the SO-CVF given
in Sect. 12.3.2. To solve this problem while seeking for a faster dynamic perfor-
mance, a GSO-CVF is proposed as [10]
fxn ðs þ jxo Þ
HðsÞ ¼ CðsÞ ð12:27Þ
s2 þ 2fxn s þ x2n
where a complex compensator C(s) is introduced to guarantee H(jxo) = 1 with

larger and adjustable xn. Letting xn = dxo and substituting s = jxo into (12.27)
yields
fdxo ðjxo þ jxo Þ

Hðjxo Þ ¼ Cðjxo Þ ¼ 1 ð12:28Þ
ðjxo Þ2 þ j2fdx2o þ ðdxo Þ2
where d is a real number. Manipulating (12.28) gives
1 d2
Cðjxo Þ ¼ 1 þ j ð12:29Þ
2df
From (12.29), it is found that C(jxo) is frequency independent. Therefore, the

complex compensator C(s) is a constant complex gain; the complex transfer
function of the GSO-CVF can be derived as

fdxo ðs þ jxo Þ 1 d2
HðsÞ ¼ 1 þ j ð12:30Þ
s2 þ 2fdxo s þ d2 x2o 2df
Notice that, when d = 1, (12.30) becomes the same as (12.22), which indicates
that the SO-CVF is a special case of the GSO-CVF.
1.2 =1
=1.5
1.0 =2
0.8
|H(j2 f)| 0.6
0.4
0.2
0.0
400 300 200 100 0 100 200 300 400
Frequency (Hz)
Fig. 12.15 Magnitude-frequency plot of the GSO-CVF with f = 0.707
The magnitude-frequency plot of (12.30) is given in Fig. 12.15, where the

damping ratio f is still set to 0.707. As seen, the features of unity gain at funda-
mental positive frequency and zero gain at fundamental negative frequency are
maintained in the GSO-CVF. Meanwhile, a larger d leads to impaired harmonic
attenuation. However, with the fixed f and complex zero, a larger d leads to a larger
xn, which indicates a faster dynamic performance. Since there are two freedoms in
tuning the GSO-CVF, it can be concluded that the GSO-CVF is capable of pro-
viding an alternative with faster dynamic performance at the cost of impaired
harmonic attenuation compared with the SO-CVF, and this feature might be helpful
in some specific situation, such as the sudden greatly unbalanced grid fault where
the FPC and FNC of grid voltages should be extracted within the limited time for
implementing the low-voltage ride-through strategies in the power converters [36].
This GSO-CVF can be implemented as shown in Fig. 12.16a, where SOF-a and
SOF-b represent the a- and b-axis second-order scalar filters (SOFs), respectively.
SOF-a and SOF-b are in the same structure, and their scalar implementation is
depicted in Fig. 12.16b. In Fig. 12.16a, the dashed box refers to the instantaneous
symmetrical component (ISC) calculation unit [37, 38], and the shaded part is the
scalar implementation of the complex gain C(s). According to (12.29), the constant
scalar gain c in the shaded part is
1 d2
c¼ ð12:31Þ
2df
Besides, the implementation for the extraction of the FNC can be obtained with
the similar method given in this section and is also shown in Fig. 12.16.
12.5 Third-Order Complex-Vector Filter 287
v p v+1
1/2
v c
vg +1
SOF- qv v p
c v
1/ 1/2
o
v
ISC
vg SOF- qv
1/
1
v n v
1/2
c
c 1
v n v
1/2
(a) Block diagram of the GSO-CVF
vg v
2
qv
o
(b) Block diagram of the SOF-
Fig. 12.16 Scalar implementation of the GSO-CVF
12.5 Third-Order Complex-Vector Filter
With the same complex zero, a TO-CVF might have better inherent filtering
characteristic than the second-order one because of the increased order of the
denominator in its complex transfer function. Thus, the complex transfer function
of the TO-CVF can be given as [10]
k1 x2o ðs þ jxo Þ
HðsÞ ¼ ð12:32Þ
s3 þ k2 xo s2 þ k3 x2o s þ k4 x3o
Again, H(jxo) = 1 is required, which leads to
k1 x2o ðjxo þ jxo Þ

Hðjxo Þ ¼ ¼1 ð12:33Þ
ðjxo Þ3 þ k2 xo ðjxo Þ2 þ k3 x2o jxo þ k4 x3o
1.2
Second-order
1.0
= 0.707
Third-order
0.8 k1= 2.33,k2= 3.18
|H(j )| 0.6
0.4
0.2
0.0
400 300 200 100 0 100 200 300 400
Frequency (Hz)
Fig. 12.17 Magnitude-frequency plots of the SO-CVF and TO-CVF
j2k1 x3o ¼ ðk4 k2 Þx3o þ jðk3 1Þx3o ð12:34Þ
Examining the real and imaginary parts in both sides of (12.34) gives
k4 ¼ k2 ; k3 ¼ 2k1 þ 1 ð12:35Þ
As a consequence, (12.32) can be rewritten as
k1 x2o ðs þ jxo Þ
HðsÞ ¼ ð12:36Þ
s3 þ k2 xo s2 þ ð2k1 þ 1Þx2o s þ k2 x3o
To achieve a similar dynamic performance compared with the SO-CVF, k1 and

k2 are tuned for the third-order one with the pole placement method [39]. With
k1 = 2.33 and k2 = 3.18, the poles of (12.36) become p1 = − 274 and
p2,3 = −363 ± j478, whose real parts are relatively similar to the poles of the
SO-CVF which are p1,2 = −222 ± j222 with f = 0.707. The magnitude-frequency
plots of (12.22) and (12.36) are given in Fig. 12.17. Obviously, the TO-CVF has a
better harmonic attenuation than the second-order one.
The TO-CVF can be implemented as shown in Fig. 12.18a. Again, it is an
ISC-based structure. The block diagram of the third-order scalar filter (TOF) of
Fig. 12.18a is shown in Fig. 12.18b which is similar to the structure depicted in
Fig. 12.16b.
12.6 Simulation and Experimental Verification 289
Fig. 12.18 Scalar v v+1

implementation of the vg
TOF- qv v+1
TO-CVF
ISC
o 1
v v
vg TOF- qv v 1
(a) Block diagram of the TO-CVF
vg v
2k1
o k2
k2
qv
(b) Block diagram of the TOF-
12.6 Simulation and Experimental Verification
12.6.1 Simulation Results
For the multiblock-based complex-vector prefilter, the representative

phase-to-phase-fault unbalanced grid voltages are used to investigate its perfor-
mance. The unbalanced grid voltages used in the simulation are shown in
Fig. 12.19a. The root-mean-square value of the rate grid voltage is 220 V. The
positive-sequence grid voltage is 60% of the rated grid voltage, and the phase is 0°.
The negative-sequence grid voltage is 40% of the rated grid voltage, and the phase
is also 0°. The severely unbalanced grid fault occurs at 0.2 s, and the grid voltages
recover at 0.28 s. Based on the analysis given in Sect. 12.3.2, it is expected that the
three-block-based prefilter consisting of R+1(s), R−1(s), and R+2(s) has a relatively
slow dynamic performance. Therefore, the two three-block-based prefilters are
investigated. The prefilter consisting of R+1(s), R−1(s), and R+2(s) is referred to as
MCVF1, and the one consisting of R+1(s), R−1(s), and R−5(s) is referred to as
MCVF2. xc is set to 0.707xo for each resonator. The estimated amplitudes of the
FPC and FNC from the three-block-based prefilters can be directly calculated by
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi
2 þ 1 2 2 1 2
vaþ 1 þ vb and v1
a þ vb and are given in Fig. 12.19b. It can be
observed that the dynamic performance is much worse for the prefilter consisting of
R+1(s), R−1(s), and R+2(s), which is consistent with the conclusion drawn from the
pole-zero maps in Sect. 12.3.2.
400 vga vgb vgc
Grid Voltage (V) 200
200
400
0.18 0.22 0.26 0.3 0. 3 4
t (s)
(a) Grid voltages
400
300
FPC.MCVF1
Amplitude (V)
FPC.MCVF2
200
100
FNC.MCVF2 FNC.MCVF1
0
0 .1 8 0.22 0.26 0.3 0. 3 4
t (s)
(b) Estimated amplitudes of the FPC and FNC of grid voltages
Fig. 12.19 Simulation waveforms of the multiblock-based prefilters
To experimentally validate the CVFM-based analysis and investigate the perfor-

mance of the proposed prefilters in this chapter, the SO-CVF, GSO-CVF, and
TO-CVF are implemented in TMS320F2812 which is a fixed-point 32-b 150-MHz
digital signal processor. To avoid the algebraic loop and guarantee the accuracy of
the implementation, the integrator in the prefilters is approximated by [40]
1 Ts 23z1 16z2 þ 5z3

¼ ð12:37Þ
s 12 1 z1
Moreover, the sampling rate is 20 kHz. A 16-bit digital-to-analog converter

(DAC) DAC7664 and an RC low-pass output filter with the time constant of 1 ls
are used to display the interesting signals in the oscilloscope. The grid voltages used
in the experiment are simulated by a programmable ac source (Chroma 6590). f is
set to 0.707 for both SO-CVF and GSO-CVF. The d of the GSO-CVF is set to 2 for
a faster dynamic response.
1. Balanced Grid Fault Test
The dynamic performance of the proposed prefilters is tested with the balanced
grid fault, and the experimental results are shown in Fig. 12.20. As can be seen
from Fig. 12.20a, the balanced grid fault lasts 45 ms, and the grid voltages step
between 220 and 44 V (20% of the rated grid voltage). The estimated amplitudes of
FPC and FNC from SO-CVF, TO-CVF, and GSO-CVF, which are obtained from
the DAC and 250 times smaller than their actual values, are demonstrated in
Fig. 12.20b, c, respectively. It can be observed that the GSO-CVF achieves the best
dynamic performance and its settling time is approximately a half of the one of
SO-CVF. The SO-CVF and TO-CVF have the similar dynamic performance, which
is in good agreement with the theoretical analysis.
SO-CVF
TO-CVF
GSO-CVF
Time : [10 ms/div] Time : [10 ms/div]
(a) Grid voltages: 100 V/div (b) Estimated amplitudes of FPC: 0.5 V/div
SO-CVF
TO-CVF
GSO-CVF
Time : [10 ms/div]
(c) Estimated amplitudes of FNC: 0.5 V/div
Fig. 12.20 Experimental waveforms under balanced grid fault

2 Severely Unbalanced Grid Voltage Test

The experimental results under severely unbalanced grid voltage condition are
shown in Fig. 12.21. The grid voltages are depicted in Fig. 12.21a, where FPC is
60% of the rated grid voltage and the phase is 0°; the FNC is 40% of the rated grid
voltage, and the phase is also 0°. And, the grid voltages are slightly distorted with
1.5% negative-sequence fifth-order, 1.5% positive-sequence seventh-order, 1%
negative-sequence eleventh-order, and 0.5% positive-sequence thirteenth-order
harmonics whose phases are 180°, 0°, 0°, and 0°, respectively. The estimated FPC
SO-CVF
TO-CVF
GSO-CVF
(a) Grid voltages: 100 V/div (b) Estimated FPC of grid voltages at
-axis: 0.5 V/div
SO-CVF SO-CVF
TO-CVF TO-CVF
GSO-CVF
GSO-CVF
(c) Estimated FNC of grid voltages at (d) Estimated amplitudes of FPC: 0.5 V/div
-axis: 0.5 V/div
SO-CVF
TO-CVF
GSO-CVF
Time : [5 ms/div]
(e) Estimated amplitudes of FNC: 0.5 V/div
Fig. 12.21 Experimental waveforms under severely unbalanced grid voltage condition
and FNC of grid voltages at the a-axis are given in Fig. 12.21b, c, respectively.
Because the DAC works in the unipolar-output mode, a 1-V dc bias is added to
display the sinusoidal signals. The amplitudes of FPC and FNC are shown in
Fig. 12.21d, e, respectively. As seen, the SO-CVF, GSO-CVF, and TO-CVF all
work well under the severely unbalanced grid voltage condition.
3. Severely Distorted Grid Voltage Test
The performance of the proposed TO-CVF under severely distorted grid voltage
condition is investigated, and the experimental results are shown in Fig. 12.22. The
SO-CVF
TO-CVF
(a) Grid voltages: 100 V/div (b) Estimated FPC of grid voltages at
-axis: 0.5 V/div
SO-CVF
SO-CVF
TO-CVF
TO-CVF
(c) Estimated FNC of grid voltages at (d) Estimated amplitudes of FPC: 0.5 V/div
-axis: 0.5 V/div
SO-CVF
TO-CVF
Time : [5 ms/div]
(e) Estimated amplitudes of FNC: 0.5 V/div
Fig. 12.22 Experimental waveforms under severely distorted grid voltage condition
grid voltages are depicted in Fig. 12.22a, where the rated balanced grid voltages are
distorted with 20% negative-sequence fifth-order, 15% positive-sequence
seventh-order, 10% negative-sequence eleventh-order, 8% positive-sequence
thirteenth-order, and 5% negative-sequence seventeenth-order harmonics whose
phases are 180°, 180°, 180°, 180°, and 180°, respectively.
The estimated FPC and FNC of grid voltages at the a-axis are given in
Fig. 12.22b, c, respectively. A 1.25-V dc bias is added to display the sinusoidal
signals. The amplitudes of FPC and FNC are shown in Fig. 12.22d, e, respectively.
From Fig. 12.22b–e, it can be observed that, compared with the SO-CVF, the
proposed TO-CVF achieves better harmonic attenuation under the highly distorted
grid voltage condition which is consistent with the analysis in Sect. 12.5.
12.6.3 Brief Comparison
Different prefilters have been analyzed in this chapter. Based on the previous
analysis, a brief comparison among the prefilters mentioned earlier is presented as
follows. For the generality of different prefilters, the frequency of the grid voltages
is assumed constant in the following comparison. Five types of prefilters, which are
the first-order, second-order, generalized second-order, third-order complex-vector
prefilters, and the multiblock-based one, have been compared, and each of them
might have different structures to implement. With the help of the CVFM, the
FPC-extracting complex transfer functions of these five types of prefilters have
already been derived in the previous sections. The different features of these
complex prefilters are listed in Table 12.1. The first-order complex-vector prefilter
has the simplest structure. However, it can only attenuate but not eliminate the FNC
of the grid voltages. The second-order one can be seen as a special case of the
generalized second-order one. It achieves a trade-off between the dynamic perfor-
mance and harmonic attenuation with a relatively simple structure. The generalized
second-order one provides an alternative to achieve better dynamic performance at
the cost of impaired harmonic attenuation. The third-order one has a better inherent
filtering characteristic while keeping the similar dynamic performance compared
Table 12.1 Comparison of different complex-vector prefilters

Feature Types of prefilters
First-order Second-order Generalized Third-order Multiblock
second-order
FNC elimination No Yes Yes Yes Yes
Dynamic performance Good Good Better Good Good
Inherent filtering Good Good Neutral Better Good
characteristic
Multiple harmonic No No No No Yes
elimination
Simplicity Better Good Neutral Neutral Bad
with the second-order one. The multiblock-based prefilter is well known for its
multiple-harmonic elimination, but its dynamic performance might get worse when
the harmonic to eliminate is too close to the fundamental positive frequency.
12.7 Summary
The CVFM is adopted in this chapter to analyze the prefilters in the SRF-PLL. It
has the advantage of compact representation and easy algebraic manipulation and
provides a generalized perspective to understand and develop the grid synchro-
nization system. With the CVFM, the complex transfer functions of the prefilters
can be obtained, and it permits the utilization of the classical analyzing tools, such
as the magnitude/phase-frequency plots and pole-zero maps, in the analysis of the
prefilters. The generalized second-order complex-vector prefilter for better dynamic
performance and the third-order complex-vector prefilter for higher harmonic at-
tenuation are proposed in this chapter with the help of the CVFM. Some insights
into the relationships among different prefilters can be drawn with the CVFM, and a
brief comparison is presented to highlight the features of each prefilter.
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Index
A 144, 147, 150, 167, 170, 198, 199, 202,

Active damping, 7–9, 13, 88, 90–92, 119, 168, 208, 210, 212, 218, 229, 241
185, 187, 191, 194, 196, 199, 201–203, Capacitor-current-feedback
205, 210–212, 214, 219, 221, 224, 230, active damping, 8, 9, 12, 13, 90, 92, 95, 97,
241, 242, 256 106, 112, 119, 122, 123, 166, 169,
Active power, 55, 101, 134, 206, 271, 282 185–187, 191, 194, 195, 199, 200, 202,
Adaptability, 108, 136, 228 205, 212, 214, 221, 224, 230, 256
Adaptive filter, 275 coefficient, 9, 11, 95, 96, 105,
Adaptive notch filter, 21, 274 166, 180, 182
Air gap, 64, 67, 68, 71 Capacitor voltage, 19, 38, 47, 48, 50, 57, 85,
Amplitude error, 101, 107, 112, 115, 194, 206, 89, 92, 97, 141, 144, 170, 202
212, 219, 221 Carrier period, 47, 48, 51
Amplitude-phase Center frequency, 34
control, 8 Closed-loop
curve, 176 system, 9, 11, 185
Analog control, 13, 166, 170, 194, 202 Complex
coefficient prefilter, 22, 275, 281
B compensator, 275
Background harmonics, 16, 122, 131, 244 signal-flow graph, 276, 279, 281
Backward difference approximation, 155, 242 transfer function, 276, 280, 283, 285–287,
Bandwidth, 9, 12, 108, 123, 181, 202, 221, 294, 295
224, 232, 243 Complex-vector-filter method, 272, 275, 277,
Bessel function, 33 291, 294, 295
Block diagram, 8, 14, 15, 18, 88–90, 97, 123, Computation delay, 13, 15, 16, 168, 169, 195,
126, 127, 142–147, 151, 152, 166, 170, 197–200, 202, 204, 205, 208, 212,
200–202, 231, 234, 238, 289 214–218, 221, 224, 229, 230
Bode diagram, 14, 15, 80, 91, 99, 108, Condition
111–113, 115, 171, 172, 176, 178, 189, full-load, 125
190, 211, 219, 242, 254, 255, 257, 259, half-load, 125
260, 263, 264 stiff grid. See Stiff grid condition
Boundaries, 107, 109, 182, 185 weak grid. See Weak grid condition
Bypass Control
capacitor, 5, 86, 88 algorithm, 8, 9, 13, 88, 167
inductor, 86–88 delay, 6, 13, 14, 23, 166, 168, 169, 171,
184, 195, 201, 205, 208, 224, 236, 238,
C 242, 253, 258
Capacitor current, 8, 9, 13, 19, 38, 57, 59, 64, Corner frequency, 100, 106
66, 67, 90, 92, 96, 97, 105, 123, 130, 142, Coupled inductor, 69, 70, 77
CPSS Power Electronics Series, DOI 10.1007/978-981-10-4277-5
300 Index
Coupling coefficient, 63, 67, 69, 70, 72, 75, 77 E

Coupling effect, 63, 67, 77 Enhanced phase-locked loop, 22
Cross-coupling, 144, 145, 147, 150, E-PLL. See Enhanced phase-locked loop
272, 276 Equivalent transformations, 97, 98, 122, 123,
Crossover frequency, 11, 17, 21, 22, 99, 108, 166, 200, 201, 230, 238
110–112, 119, 166, 167, 179, 181, 185, Extended-loop-filter, 21
186, 190, 194, 196, 205, 206, 215, 219, 221
Cross-section area, 63, 66, 68, 72, 77 F
Current Feedback
hall, 130 coefficient, 96, 123, 143, 150
loop, 6, 9, 18, 22, 96, 123, 125, 167, 199, paths, 170, 200, 230, 279
205, 215, 233, 240, 243, 248, 272 Feedforward
regulator, 9, 11, 12, 18, 95, 96, 100, 104, function, 19, 122, 126, 128, 132, 154, 155,
119, 123, 126, 142, 144, 147, 166, 167, 159, 162, 253, 259, 262
180–185, 198, 210, 211, 229, 234, 242, node, 126, 234, 251, 253
254, 256, 265 scheme, 122, 127–133, 136, 151–154,
ripple, 6, 7, 47, 50, 54, 58–60, 64 158–160
ripple coefficient, 54, 57, 58 Filter capacitor, 6, 7, 9, 38, 51, 55, 60, 64, 80,
Current-controlled scheme, 8 85, 95, 96, 100, 104, 122, 130, 131, 136,
Cutoff frequency, 12, 108, 181, 210, 242 140–142, 166, 170, 193, 195, 198, 202,
CVFM. See Complex-vector-filter method 229, 251, 256
First-order low-pass scalar filter, 277
D Flux
Damping density, 66, 72
performance, 7, 13, 85, 88, 90–92, 202, path, 7, 64
204, 205 FNC. See Fundamental negative-sequence
ratio, 11, 80, 280, 285 components
resistor, 7, 85, 86, 92, 166 Forbidden region, 166, 179, 180, 182,
solution, 81, 85, 89, 95, 99 186–188, 191, 193, 195
Dc-ac inverter, 3 Fourier
Dc voltage utilization, 41, 43, 44 series expansion, 33, 35, 36, 60
Delayed signal cancellation, 22, 275 transform theory, 32, 43
Delta-connection, 37 FPC. See Fundamental positive-sequence
Derivative component, 122, 151, 155 components
Digital control, 6, 155, 166, 167, 181, 182, Frequency
194, 195, 198, 202, 224, 229, 253, 259 center. See Center frequency
Digitally controlled, 13, 168, 169, 194, 199, corner. See Corner frequency
200, 224, 229, 230 crossover. See Crossover frequency
Digital signal processor, 13, 167, 211, 254, 291 cutoff. See Cutoff frequency
Direct current control, 8 fluctuation, 108, 181
Discrete inductor, 64, 73–76 fundamental. See Fundamental frequency
Disturbance grid. See Grid frequency
component, 107, 124, 250 response, 5, 22, 81, 83, 84, 87, 91, 119,
rejection ability, 8 169, 221, 232, 233, 236, 238–240,
DSC. See Delayed signal cancellation 242–244, 254, 258, 277, 278
DSP. See Digital signal processor Full-bridge, 32, 41, 43, 46, 47, 49, 50, 55, 56,
Dual-input/dual-output, 272, 275, 276 58, 59
Dynamic Full feedforward
performance, 7, 19, 21, 106, 111, 112, 191, function, 122, 126, 128–130
194, 207, 219, 221, 224, 272, 281, 285, scheme, 122, 126, 128, 130–132,
286, 288, 289, 291, 292, 295 134, 136
response, 8, 10, 11, 105, 111, 122, 177, Fundamental
182, 187, 189, 192–194, 221, 272, 278, angular frequency, 12, 181
283, 291 current, 8, 64, 85
Index 301
frequency, 11, 17, 21, 41, 48, 85, 87, 99, suppression, 130–132, 153, 259, 260, 262,
101, 103, 108, 125, 129, 181, 190, 194, 263, 266, 268
206, 209, 212, 219, 257, 282 suppression ability, 129
negative-sequence components, 17, 21, 275 synchronous frames, 17
positive-sequence components, 21, Harmonic injection SPWM, 31, 41–45, 51, 53,
274, 275 54, 56, 59, 60
Harmonic-rejection ability, 227, 233, 236, 246,
G 248
Gain margin (GM), 11, 12, 95, 104, 112, 119, Harmonics
166, 177, 179, 185, 186, 190, 196, 203, spectrum, 41, 44
205, 207, 211, 219 voltage, 45
Gamma Function, 34 High-frequency noises, 14, 90, 208
Generalized integrator, 22, 275, 281 H-infinity control, 8
Generalized second-order complex-vector Hybrid frame, 145, 147, 148, 150, 156, 162
filter, 272, 285
Grid I
codes, 21, 274 Impedance
frequency, 12, 108, 109, 112, 181, 187 ratio, 23, 229, 234, 251
impedance, 6, 14, 22, 23, 122, 139, 198, shaping, 227, 233–236, 240
212, 221, 222, 227–229, 232, 233, 240, Indirect current control, 8
242–245, 248, 254, 255 Inherent resonance, 165
voltage, 6, 8, 11, 12, 16, 18, 19, 21, 23, 46, Input-variable vector, 14
48, 56, 90, 96, 107, 119, 121–123, Input voltage, 32, 56–58, 71, 74, 88, 97, 110,
125–127, 130, 131, 133, 134, 136, 139, 123, 125, 128, 130, 131, 136, 140, 169,
140, 152, 153, 155, 158, 159, 161, 162, 187, 200, 204, 241, 251, 253
198, 206, 221, 224, 229, 234, 241, 243, Instability, 5, 14, 16, 17, 79, 80, 117, 119, 165,
244, 248, 251, 259, 261, 263, 266, 272, 208, 211, 214, 220, 227
274, 275, 280, 289, 293, 294 Instantaneous symmetrical component (ISC),
Grid-connected inverter, 3–6, 8–13, 16, 17, 19, 286
22, 23, 31, 32, 37, 46, 55, 60, 80, 96, 119, Integrated inductor, 63, 66–68, 74–77
132, 139, 141, 146, 154, 162, 194, 200, Integrated magnetics, 63
228, 251, 257, 265, 271, 272 Internal model theory, 18
Grid current Inverse Laplace transform, 278
distortion, 11, 16, 23, 122, 136, 224, 232 Inverter bridge, 8, 19, 32–34, 38, 46, 50,
loop, 6, 9, 18, 22, 96, 123, 125, 167, 205, 55–57, 60, 69, 80, 88, 96, 123, 169, 216,
215, 221, 224, 230, 253 217, 229, 230, 251, 253
reference, 9, 16, 19, 115, 123, 125, 159, Inverter-side
160, 167, 191, 194, 198, 206, 212, 214, inductor, 6, 9, 19, 38, 47, 50, 52, 54, 55,
229, 272 57–60, 64, 66, 80, 96, 105, 110, 122,
regulator, 9, 11, 12, 95, 123, 142, 144, 147, 125, 130, 136, 140, 141, 184, 187, 198,
166, 167, 180, 182–185, 242, 254, 256, 204, 251, 256
265 inductor current, 9, 47, 54, 64
Grid fault condition, 21, 275
Grid-side inductor, 38, 55, 61, 64, 66, 80, 96, L
100, 111, 140, 198, 232, 256 LCL filter, 4–8, 14, 23, 31, 34, 37, 46, 56–58,
GSO-CVF. See Generalized second-order 60, 64, 67, 69, 70, 74, 75, 77, 79–81, 83,
complex-vector filter 85, 86, 88, 90–92, 95, 96, 122, 140, 142,
153, 166, 171, 180, 182, 186, 193, 195,
H 229, 230, 242
Harmonic LCL-filter resonance, 91, 96, 166
attenuation, 8, 70, 151, 154, 163, 272, 278, LCL-type, 4, 5, 9, 10, 12, 13, 16, 22, 32, 33, 36,
280, 281, 285, 286, 289, 294, 295 37, 39, 42, 45, 57, 58, 60, 64, 66, 71, 73,
limit, 5, 6, 60, 63, 74, 77 79, 80, 92, 95, 96, 98, 110, 119, 122–126,
spectrum, 37, 46, 60, 157, 159, 266, 269 136, 140, 142, 144–146, 151, 152, 154,
302 Index
162, 166, 167, 176, 183, 186, 194, 195, Norton equivalent circuit, 228, 237, 250
199, 202, 210, 222, 224, 229, 251, 253, Notch filter, 91
255, 256, 259, 269 Nyquist
Lead compensator, 14, 21, 208, 274 frequency, 169, 204
LF. See Loop filter stability criterion, 23, 176, 177, 184, 205,
L filter, 4, 5, 11, 46, 69 229, 251, 254
Line inductor, 266
Line voltage, 39, 41, 43, 44 O
Loop Observed variables, 15
filter, 21, 22, 272, 274 Observer
gain, 11, 13, 17, 19, 98–101, 103, 104, 107, equations, 14
108, 111–113, 115, 122, 124, 166, 168, gain matrix, 15
171, 172, 174–177, 181, 183–186, One sampling period, 13, 14, 168, 182, 195,
189–191, 194, 195, 202, 211, 213, 219, 229
221, 227, 229, 231, 242, 257, 274 Open-loop
Lower limit, 52, 54, 183, 186, 188 control, 8
Low-voltage ride-through, 286 system, 204, 205, 224
Orthogonal system generation, 274
M Oscillation, 5, 117, 119, 165, 193, 214, 254
Magnetic Oscillatory transient, 134
circuit, 63, 64, 67, 68 OSG. See Orthogonal system generation
component, 5, 7, 63 Output
core, 7, 64, 71 admittance, 19, 202
material, 63, 72, 77 impedance, 23, 227, 229, 232–234, 236,
Magnetic integration 239, 242–244, 248, 250–257, 259, 269
coupled, 7 Output-variable vector, 14
decoupled, 7
techniques, 7 P
Magnitude curve, 179, 181, 232 Parallel impedance, 234–239, 242, 244, 246
Magnitude-frequency Park transformation, 20
characteristics, 7, 81, 85, 88, 91, 95, 166 Partial-feedforward scheme, 265
plot, 281, 284–286, 288 Passive damping, 7, 81, 85
Magnitude plot, 69, 70, 99, 100, 211 PCC. See Point of common coupling
Mathematical model, 97, 98, 119, 122, 123, PD. See Phase detector
140, 142, 144, 168, 169, 224, 251 Peak-valley sampling method, 217
Maximum decrement, 48, 49, 52 Percentage overshoot, 115, 117, 118, 212, 221
Maximum increment, 48, 49, 52 Permeability
Mid-value sampling method, 217, 218 absolute, 68
Minimum value, 56, 58, 61, 183, 186, 211 relative, 68
Modulation Per-unit values, 129, 130, 153, 154
ratio, 42, 43, 57, 58 Phase
reference, 96, 104, 105 curve, 166, 176–178, 183, 184
wave, 19 detector, 272
Multi-synchronous frame control, 17, 18 error, 101, 115, 206
Mutual inductance, 69 lag, 13, 132, 166, 171, 184, 205, 259
margin, 11, 12, 17, 95, 99, 100, 103, 106,
N 108, 110–112, 117, 119, 166, 177, 180,
Negative crossing, 80, 176, 177 185, 186, 190, 194, 195, 206, 219, 233,
Negative feedback, 229, 251 240, 242, 243, 263
Negative phase-shift, 17, 22, 257, 258 plot, 13, 99, 104, 205, 207, 211
Negative-sequence voltage, 40, 41, 44, 59, 140
synchronous frame, 12, 17 Phase-frequency response, 22
Nonlinear adaptive filters, 22, 275 Phase-locked loop
Nonlinear term, 172, 174 E-PLL, 22
Index 303
Q-PLL, 22 Regular sampling SPWM, 48

SRF-PLL, 20, 21, 272–274, 277 Reluctance, 63, 67, 68, 77
zero-crossing, 272 Renewable energy, 2, 3, 23, 31
Phase-to-phase-fault, 159, 289 Renewable energy based distributed power
PI. See also Proportional-integral regulator generation system, 2, 23
controller, 232 Repetitive controller, 18
PI-R regulator, 18 Repetitive signal generator, 18
PLL. See Phase-locked loop Resonance
Point of common coupling, 6, 121, 139, 198, angular frequency, 55, 80, 171
250 damping, 6, 7, 13, 23, 80, 99, 183, 194
Pole-zero map, 283–285, 290, 295 frequency, 5, 12–14, 70, 79, 80, 91, 92, 99,
Positive-crossing, 177, 184 112, 119, 165, 166, 171, 179, 180, 182,
Positive-sequence 187, 190, 191, 193, 195, 203, 204
filter, 22 gain, 181
Power peak, 5, 8, 13, 69, 79–81, 83, 91, 95, 99,
factor, 57, 101, 115, 117, 118, 191, 194, 106, 165, 175, 177, 184, 205, 206
206, 221 RHP. See Right-half plane
generation system, 3, 4, 23, 31, 121, 139, Right-half plane
227, 274 poles, 80, 166
loss, 3, 7, 8, 16, 85, 87, 88, 92, 95, 166 roots, 175
PR. See Proportional-resonant regulator Robustness, 105, 111, 112, 182, 187, 215, 220,
Predictive control, 8 222, 224, 227, 234, 236, 242–244, 248
Prefilter Root locus, 11
complex coefficient. See Complex Routh
coefficient prefilter array, 175
cross-coupled, 276 criterion, 175
multiblock based, 261, 264, 265
Proportional component, 128, 151, 152 S
Proportional feedback, 8, 90, 92 Sampling instant, 199, 208–210, 215, 218, 224,
Proportional gain, 100, 108, 181, 183, 184 229, 230
Proportional-integral regulator, 9, 11, 12, 17, Satisfactory region, 95, 106, 107, 110–112,
19, 21, 95, 99–101, 105–108, 110–112, 114, 166, 180, 182, 183, 185, 188–190,
115–117, 119, 122, 125, 166, 179, 184, 195, 206–208, 219
232, 242, 244, 257, 273, 274 s-domain, 13, 142, 144, 147, 149, 169, 175,
Proportional-resonant regulator, 11, 12, 17, 96, 230, 254, 275
100, 107–110, 112, 114, 115, 117, 119, Second-derivative component, 122, 128, 130,
122, 166, 179, 180, 182, 184, 206, 136, 151, 155, 162
210–212, 257, 265 Second-order
PSF. See Positive-sequence filter complex-vector filter, 272, 280, 285
Pulsewidth modulation generalized integrator, 22, 275, 281
asymmetrical regular sampled, 198 scalar filters, 286
delay, 6, 13, 166, 168, 195, 198, 199, 208, Sensor gain, 18, 96, 143, 198, 229
229, 230, 236 Series impedance, 237–240, 243, 245, 256
PWM. See Pulsewidth modulation Series-parallel impedance, 236, 239, 243, 247
Settling time, 115, 117, 191, 194, 221, 292
Q Sideband harmonics, 34
Q-PLL. See Quadrature phase-locked loop Single-input/single-output, 275
Quadrature phase-locked loop, 22 Single-phase, 4, 9, 11, 12, 19, 22, 23, 32, 33,
35, 36, 41, 43, 46–49, 50, 55–58, 60,
R 63–65, 67, 71, 72, 74–77, 80, 96, 107, 110,
Reactive power, 6, 55, 60, 61, 147, 271 119, 122, 124, 125, 132, 136, 140, 145,
Real resistor, 166 159, 167, 186, 191, 193, 196, 210, 224,
RE-DPGS. See Renewable energy-based 229, 241, 248, 250, 272, 274
distributed power generation system Sinusoidal modulation signal, 32, 35, 38, 42
304 Index
Sinusoidal pulse-width modulation (SPWM) Synchronous d-q frame, 140, 147, 148
bipolar, 31–35, 37, 47, 49, 60 Synchronous reference frame PLL, 20, 272
harmonic injection. See Harmonic injection Synchronous sampling, 13, 198, 200, 203,
SPWM 208–210, 229
regular sampling, 48
unipolar, 31, 35, 36, 49, 56, 57, 60, 71, 72, T
111, 215, 218, 224 THD. See Total harmonics distortion
Six-block-based filter, 283 Thevenin equivalent circuit, 228, 229
Sliding Goertzel transform, 21, 274 Third-order
SO-CVF. See Second-order complex-vector complex-vector filter, 272, 287
filter scalar filter, 289
SOFs. See Second-order scalar filters Three-block-based filter, 283
SOGI. See Second-order generalized integrator Three-phase, 4, 9, 10, 12, 16, 19, 20, 23,
Space vector modulation, 45, 73 37–39, 41–46
Spectrums, 31, 57, 59 Three-wire, 9, 38, 66, 141, 275
Square wave, 272 TO-CVF. See Third-order complex-vector filter
SRF-PLL. See also Synchronous reference TOF. See Third-order scalar filter
frame PLL Total harmonics distortion, 55
decoupled double, 22, 275, 281 Tracking performance, 6, 221
Stability Transfer function, 11, 18, 19, 55, 69, 80–83,
constraint conditions, 176, 177, 180, 195 85–88, 91, 97, 122, 123, 126, 143, 169,
criterion, 23, 176, 177, 228, 229, 250, 251, 170, 173, 200–202, 229, 230, 234, 237,
254, 269 251, 253, 254, 258, 275–277, 283, 285
margin, 166, 177, 180, 184, 185, 193, 195, Transient response, 134, 135, 155, 160–163,
211, 214, 219 191, 212, 222
performance, 10, 208, 224, 244 Triangular carrier, 32, 35, 38, 88, 97, 104, 105,
Star-connection, 37 123, 167–169, 200, 217, 230
State
observer, 14, 15, 208 U
variable, 15, 88 Unbalanced
State-space components, 8, 16, 19, 21, 22, 259, 272,
equations, 14 274
matrices, 14 grid fault, 286, 289
model, 8, 15 grid voltage, 19, 140, 159, 160, 280, 289,
Static tracking component, 124, 125 292–294
Static tracking error, 124 Undamped natural angular frequency, 280, 285
Stationary a-b-c frame, 140–142, 273 Ungapped magnetic leg, 7
Stationary a-b frame, 9, 12, 140–143, 145, Unipolar SPWM, 31, 32, 35–37, 49, 50, 56, 57,
147, 148, 150, 151, 155, 156, 162, 251, 252 60, 72, 215, 218, 224
Steady-State Unit circle, 174, 211, 220, 234
error, 9–12, 17, 19, 95, 101, 103, 105, Unity gain, 235, 277, 278, 281, 286
107–109, 111, 117, 119, 122, 136, 166, Unstable pole, 174, 175, 219
180, 182, 184–186, 195, 206, 219, 239, Upper limit, 11, 54, 60, 180, 182, 183,
240, 257 186–189
waveform, 191, 221
Stiff grid condition, 22, 251 V
Superposition theorem, 250 VCO. See Voltage controlled oscillator
Switching frequency, 31, 72, 74, 76, 104, 106, Vector diagram, 237, 259, 260, 263, 265
111, 143, 198, 208, 209 Virtual capacitor, 171, 195
Switching harmonics, 4, 6, 70, 72, 74–76 Virtual frequency-dependent impedance, 166
Switching noise, 106, 167, 210, 212, 215, 217, Virtual inductor, 171, 195, 248
218 Virtual reactor, 166, 195, 203
Switching period, 104, 198, 209, 210, 215, 229 Virtual resistor, 8, 88, 142, 166, 170, 195, 203
Switching ripple, 104, 208, 209 Voltage
Index 305
dip, 134, 135 w-transform, 174

loop, 9, 96, 123, 167
source, 6, 69, 80, 228, 229 Z
Voltage controlled oscillator, 272 ZC-PLL. See Zero-crossing PLL
Voltage-controlled scheme, 8 z-domain, 13, 168, 172, 174
Zero-crossing detection, 272
W Zero-crossing PLL, 272
Weak grid condition, 22, 23, 228, 244, 250, Zero current ripple, 7
251, 253–255, 257, 259, 260, 263, 265–269 Zero gain, 280, 281, 286
Weight, 128 Zero order hold, 168
Weighted coefficient, 262 Zero sequence, 38, 45
Weighted-feedforward scheme, 259–263, 265, ZOH. See Zero order hold
266, 268, 269

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CPSS Power Electronics Series

Xinbo Ruan · Xuehua Wang

Readership: Research scientists in universities, research institutions and the

More information about this series at http://www.springer.com/series/15422

Donghua Pan Dongsheng Yang

Weiwei Li Chenlei Bao

ISSN 2520-8853 ISSN 2520-8861 (electronic)

Library of Congress Control Number: 2017936335

© Springer Nature Singapore Pte Ltd. and Science Press 2018

Printed on acid-free paper

This Springer imprint is published by Springer Nature

Renewable energy-based distributed power generation systems (RE-DPGS) repre-

active-damping solutions, equivalent to a virtual resistor in parallel with the ﬁlter

Nanjing, China Xinbo Ruan

2.4.2 Three-Phase LCL Filter . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.5.1 Controller Design Based on PI Regulator

7.3.3 Comparison Between the Feedforward Functions

8.8.2 Experimental Validation Without Damping . . . . . . .... 193

11 Weighted-Feedforward Scheme of Grid Voltages

Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 2004 and

ANF Adaptive notch ﬁlter

SGT Sliding Goertzel transform

1.1 Energy Situation and Environmental Issues

© Springer Nature Singapore Pte Ltd. and Science Press 2018 1

1.2 Renewable Energy-Based Distributed Power

2. Enhanced energy security. The utilization of renewable energy helps to alleviate

(a) RE-DPGS with dc bus

(b) RE-DPGS with ac bus

Fig. 1.1 Typical conﬁgurations of RE-DPGS

1.3 Key Issues of LCL-Type Grid-Connected Inverters

Grid-connected inverters can be either single-phase ones or three-phase ones.

(a) L filter (b) LCL filter

3. Stability problem caused by the digital control delays. If digital control is

1.3.1 Design and Magnetic Integration of LCL Filter

Table 1.2 Current harmonic limits in percent of rated current

1.3.2 Resonance Damping Methods of LCL Filter

1.3.3 Controller Design of Grid-Connected Inverters

1.3.3.1 Classiﬁcation of Control Schemes

Sinusoidal PWM PLL

Fig. 1.3 Single-phase LCL-type grid-connected inverter with capacitor-current-feedback

1.3.3.2 Closed-Loop Design Targets

/abc abc/ abc/ abc/

(a) Stationary - frame

dq/abc abc/dq abc/dq abc/dq

(b) Synchronous d-q frame

Fig. 1.4 Control structure of the three-phase LCL-type grid-connected inverter

1.3.3.3 Grid Current Regulator

Usually, a PI regulator or proportional-resonant (PR) regulator is used as the grid

where Kp is the proportional coefﬁcient and Ki is the integral coefﬁcient. By

where Kp is the proportional coefﬁcient, Kr is the resonant coefﬁcient, and xo = 2pfo

where xi is the bandwidth of the resonant part when concerning −3 dB cutoff

1.3.4 Effects of Control Delay and the Compensation

1.3.4.1 Control Delay Effects

Figure 1.5 shows the structure of a digitally controlled LCL-type grid-connected

Sinusoidal PWM Hi1 Hi2 PLL

Fig. 1.5 Structure of a digitally controlled LCL-type grid-connected inverter

1.3.4.2 Control Delay Compensation Methods

xðk þ 1Þ ¼ Gxðk Þ þ HuðkÞ

Fig. 1.6 Bode diagrams of 12

|Glead (s)| (dB)

∠Glead (s) (°) 30

Fig. 1.7 Block diagram of

^xðk þ 1Þ ¼ G^xðk Þ þ Huðk Þ þ LðyðkÞ ^yðkÞÞ

1.3.5 Suppression of Grid Current Distortion Caused

According to (2.17), when 0 Mr 1, the maximum amplitude of output line

vC vg ¼ Mr Vin sin xo t ð2:33Þ