Thermal Effects in Nanoscale Devices

Thermal Effects in
Nanoscale Devices. What

Do We Know So Far …
Dragica Vasileska
Arizona State University, Tempe, AZ

pdfMachine server
Dragica signed document. See ht
tp://broadgun.com/serve
Vasileska rsigned.html
Outline
 Technology Trends
 Why Thermal Effects?
 The Theoretical Model and Its Implementation
- Model Description
- Convergence
- Transport in a 25 nm Gate Length Device
- The Role of the Substrate
- Boundary Conditions
- Choice of a Proper Device Domain
 Applications
- FD SOI Devices: SiO2, Diamond and SiC as BOX layers
- Dual Gate Devices
 Conclusions From This Work
Ira A. Fulton School of Engineering

AINE – Arizona Institute for Nanoelectronics
Technology Trends

Alternative Device Technologies

Alternative Technologies:
Strained Si

Alternative Technologies:
Alternative Device Designs
These non-classical transistor

structures offer paths for further
scaling, bellow 35nm.
Dual-gate (DG) transistors allow
twice the drive current with an
inherent coupling between the
gates and the channel that makes
the design more scalable.
In ultra-thin-body (UTB) silicon-
on-insulator (SOI), power
consumption is drastically reduced
along with leakage current.
Alternative silicon devices are
designed on SOI wafers.
Three variations of dual-gate

structures

Advantages (SOI CMOS over bulk
CMOS):
VG1
- absence of latch-up; VS VD
- reduced parasitic source and Gate
tox1
drain capacitances; Si02
- ease of making shallow junctions.
Source - N+ P Drain - N+ tSi
Buried Si02
tox2
Back gate (substrate)
n-channel
VG2

Advantages (SOI CMOS over bulk
CMOS):
VG1
- absence of latch-up; VS VD
- reduced parasitic source and Gate
tox1
drain capacitances; Si02
- ease of making shallow junctions.
Source - N+ P Drain - N+ tSi
Problem: SOI devices exhibit self-
Buried Si02
heating effects. tox2
Any state-of-the-art device
These effects arise because SOI simulator must take into
devices are thermally isolated from account the heat
the substrate by the buried oxide
generation.
n-channel
layer (BOX).
V
G2
Self-heating leads to a substantial Also, thermal and electrical
elevation of the local device effects within the device
temperature, which modifies the have to be coupled via a
device output characteristics. self-consistent scheme.

Why Thermal Effects?
material Kth(W/m/K)
Si 148
Ge 60
2
Sillicide 40
1 Si (10nm) 13
SiO2 1.4
Hot spot
Earlier Theoretical Models implemented in
Silvaco ATLAS Device Simulator
(T) + JE = 0
Temperature dependent
mobilities and diffusion coefficients

The Theoretical Model and Its
Implementation
VG1 High Electric Field
VS VD
Gate
tox1
Si02
Hot Electron Transport
Source - N+ P Drain - N+ tSi -13
ô ~10 s ô ~10 -13 s
Buried Si02
tox2 Optical Phonon Acoustic Phonon
Emission Emission
ô ~10 -11 s
n-channel Heat Conduction

VG2 in Semiconductor
Hot Spot

Model Description
  e  k+q  k k+q  k k  k+q k  k+q
 t

 ve (k)   r 

E  r   
 q

k  f   We,q  Wa ,  q  We, q  Wa ,q  (13a)
   k+q  k k  k+q  g 
 t  v p ( q )   r



g  
k
We,q  Wa ,q 
  t


 p p
(13b)
J. Lai and A. Majumdar, “Concurent

thermal and electrical modeling of
submicrometer silicon devices”, J.
Appl. Phys. , Vol. 79, 7353 (1996).
TLO 3nk B  Te  TL  nm * vd2  T  TA 

C LO     C LO  LO , (14a )
t 2   e  LO  2 e  LO 
 LO  A 
TA  T  TA  3nk B  Te  TL 
CA     k ATA   C LO  LO    . (14b)
t 
 LO  A  2   e L 

Meaning of Various Terms
Energy loss to acoustic

Energy gain from the electrons phonons
 TLO 3 nk B  Te  TL  nm * v d2  TLO  T A 
C LO     C LO  , (14 a )
t 2   e  LO  2 e  LO 
 LO  A 
T A  T  T A  3 nk B  Te  TL 
CA     k A  T A   C LO  LO   . (14 b )
t   LO  A  2   e L 
Heat Diffusion Gain term due to electrons

(omitted if acoustic phonon
Gain term due
scattering is treated as
to optical phonons
elastic scattering process)

Is Energy Balance Model for Phonons
Appropriate?
- phonon mean free -Phonon mean free path
length (=1-2nm) (=300nm)
Molecular Phonon Boltzmann Fourier Law

Dynamics Transport Equation
Superlattice Classical SOI Structures
Nanotubes
-9 -8 -7 -6
10 10 10 10
Silicon layer thickness (m)

Joule Heating Approximation
 Acoustic Phonons energy balance equation is of the
form:
3 1 2
k BTe  m*vd
T 3 nk B
C A A   ( ATA )  TA  n  2 2
t 2  e A  e A
 Under the assumption of very low electric fields, the

electron temperature and acoustic phonon temperature
equal the lattice temperature
 Using low the low field conductivity and the mobility
expressions we get that the heat source term reduces to
the last term of the above equation
2  vd2 nm * vd2
qgen  J E   E  2 
 

What is the Proper Value for the Thermal
Conductivity?
Phonon Boundary
 ~ 300nm
Scattering dS
Phonon Phonon
Reduction in
Thermal
Conductivity

Thermal Conductivity of Thin Silicon Films
Must be Used
 /2
3  a   a  2z 
(z)  0 (T )  sin  1 exp   cosh  d
0   2(T )cos   2(T )cos 
 (T )  0 (300 / T ) 80
Thermal conductivity (W/m/K)

experimental data
135 full lines: BTE predictions
0 (T )  2
W/m/K dashed lines: empirical model
a  bT  cT 60 thin lines: Sondheimer
• E. H. Sondheimer, “The Mean Free Path of

Electrons in Metals”, Advances in Physics, 100nm
Vol. 1, no. 1, Jan. 1952, reprinted in 40
Advances in Physics, Vol. 50, pp. 499-537,
50nm
2001.
• M. Asheghi,., M. N. Touzelbaev., K. E. 30nm
Goodson, Y. K. Leung, and S. S. Wong., 20
“Temperature Dependent Thermal 20nm
Conductivity of Single-Crystal Silicon Layers
in SOI Substrates,” ASME Journal of Heat 300 400 500 600
Transfer, Vol.120, pp. 30-33, 1998.
Temperature (K)

Practical Implementation of the Theoretical
Model
Start
2.Average and smooth:electron
Define device structure density,drift velocity and
electron energy at each mesh
1.Generate phonon temperature point
dependent scattering tables
Initial potential, fields, positions no End of MCPS

and velocities of carriers phase?
t=0 yes
3.Acoustic and Optical Phonon
t = t + t Energy Balance Equations
Solver
Transport Kernel (MC phase)
no no End of
t = n t? simulation?
yes yes
Field Kernel (Poisson Solver)
End

Exchange of Variables Between the Two
Modules
Ensemble Monte Find electron position in a grid:(i,j)
Particle Model Carlo Device
Simulator
Find: TL(i,j)=TA(i,j) and TLO(i,j)
TA n
TLO vd Select the scattering table with
Te “coordinates”: (TL(i,j)=TLO(i,j))
Phonon Energy Generate a random number and

Fluid Model Balance Equations choose the scattering mechanism
Solver for a given electron energy
25
x 10
0.7
1.5 0.6
Electron Density (m-3)
0.5
Energy (eV)
0.4
1
0.3
0.2
0.5
Si/SiO2 interface Si/BOX 0.1
interface
10 drain 0 drain
source channel 11 source channel
5 6
y (nm) 50 75 50 75
0 0 25 x (nm) y (nm) 10 25 x (nm)

Convergence of the Scheme
25nm FD-SOI nMOSFET (Vgs=Vds=1.2V)
substrate region is not modeled (Tgate=Tbox=300K)
Current decrease (%) 8
2
device width=1um; #electrons=7692
device width=3um; #electrons=23842
0
0 20 40 60 80 100
Number of iterations

Transport in a 25 nm Gate Length
Device
5
x 10
2 2.5
Vds=1.2V
isothermal Vds=1.1V
2
T=300K Vds=1.0V
1.5
Vds=0.8V
Ids (mA/um)
1.5
Velocity (m/s)
Vds=0.6V
isothermal Vds=0.4V
1 T=400K 1
0.5
thermal
0.5
simulations
0
source channel drain
0 -0.5
0 0.2 0.4 0.6 0.8 1 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
Vds (V) x (m) x 10
-8
Carriers are in the velocity

overshoot
Acoustic and Optical Phonon Temperatures
for a 25 nm Channel Length Device
-8 -8
x 10 x 10
-0.2 -0.2 400
0.6 source drain 0.6 source drain
380
380
1.4 1.4
2.2 360 2.2 360
y (m)
y (m)
3 3
340 340
3.8 BOX 3.8 BOX
4.6 320 4.6 320
5.4 5.4
6 300 6 300
0 2.5 5 7.5 0 2.5 5 7.5
x (m) x 10
-8 x (m) x 10
-8
Acoustic phonon temperature Optical phonon temperature

In Longer Channel Devices Self-Heating is
Larger
2 5 n m F D S O I n M O S F E T
Channel 5
TGATE=300K TGATE=400K x 1 0
Length VGS=VDS 2 .5
Current Current
(FD-
(FD-SOI (V)
Decrease (%) Decrease (%)
MOSFET)
25nm 1.2 5.78 9.45 2
45nm 1.2 5.93 10.79
80nm 1.5 11.0 17.96 1 .5
90nm 1.5 11.19 17.95
100nm 1.5 11.20 18.48
1
140nm 1.8 15.6 21.85
180nm 1.8 15.22 21.52
0 .5
0
0 2 .5 5 7 .5
x (m ) -8
x 1 0

Larger
100 nm FD S O I nM O S FE T
5
2 x5 1n 0m F D S O I n M O S F E T
2 .5 5
Channel x 1 0
TGATE=300K TGATE=400K 2 .5 T g a te = 3 0 0 K
Length VGS=VDS
Current Current T g a te = 4 0 0 K
(FD-
(FD-SOI (V)
Decrease (%) Decrease (%) T g a te = 6 0 0 K
MOSFET) 2
25nm 1.2 5.78 9.45 2
45nm 1.2 5.93 10.79 1 .5
80nm 1.5 11.0 17.96 1 .5
90nm 1.5 11.19 17.95
1
100nm 1.5 11.20 18.48
1
140nm 1.8 15.6 21.85
180nm 1.8 15.22 21.52 0 .5
0 .5
0
2 .7 0 1 2 3
x (m ) -7
0 x 10
0 2 .5 5 7 .5
x (m ) -8
x 1 0

Larger
5 140 nm
x 1 0
2 .5 2 .5
100 nm FD S O I nM O S FE T
5
2 x5 1n 0m F TD g Sa Ot eI =
n M
3 0O 0SKF E T
2 .5 5
Channel x 1 0 T g a te = 4 0 0 K
Length VGS=VDS
TGATE=300K TGATE=400K 2 2. 5 T
T
g a te = 3
g a te =
0
6
0K
0 0 K
Current Current T g a te = 4 0 0K
(FD-
(FD-SOI (V)
Decrease (%) Decrease (%) T g a te = 6 0 0K
MOSFET) 2
1 .5 1 .5
25nm 1.2 5.78 9.45 2
45nm 1.2 5.93 10.79 1 .5
80nm 1.5 11.0 17.96 1
1 .5
90nm 1.5 11.19 17.95
1
100nm 1.5 11.20 18.48 0 .5 0 .5
1
140nm 1.8 15.6 21.85
180nm 1.8 15.22 21.52 0 .5
0
3 . 6 0 . 50 1 .4 2 .8 4 .2
x (m ) x 1 0
-7
0
2 .7 0 1 2 3
x (m ) -7
0 x 10
0 2 .5 5 7 .5
x (m ) -8
x 1 0

T=300K on gate
25 nm FD SOI nMOSFET (Vgs=Vds=1.2V)
T=400K on gate
25 nm FD SOI nMOSFET (Vgs=Vds=1.2V)
3 3 600
source contact drain contact
500
source contact
drain contact 500
8 8
400
source region drain region 400
13 300 13 300
10 20 30 40 50 60 70 10 20 30 40 50 60 70
45 nm FD SOI nMOSFET (Vgs=Vds=1.2V) 45 nm FD SOI nMOSFET (Vgs=Vds=1.2V)
3 3
500
500
12 400 12
400
21 300 21 300
20 40 60 80 100 120 20 40 60 80 100 120
50 100 150 200
3 3
600
500
21 21
400 400
39 300 39
50 100 150 200 250 50 100 150 200 250
3 3
600
500
23 500
23
400
400
43 300
50 100 150 200 250 300 43 300
0 120 240 360 5050 100100 150 150 200 250
200 300
250 350
300
4 4
600 600
33 33
400 400
60 60
50 100 150 200 250 300 350 400 50 100 150 200 250 300 350 400
4 4
600 600
41 41
400 400
76 76
100 200 300 400 500 100 200 300 400 500
x (nm) x (nm)

Temperature and Thickness Dependent
Thermal Conductivity
W/m/K W/m/K
40
2 14
al conductivity: Thermal conductivity: 20
4 35
nt Mean Free 12
y (nm)
y (nm)
Constant Mean Free

6 10 40
Path 30
8 8 60
10 25
6
25 50 75 0 180 360 540
Along the channel (nm) Along the channel (nm)
W/m/K
2 45
al conductivity: 12 Thermal conductivity:
4 20
T-Dependent Mean
y (nm)
y (nm)
11 40
6
Free Path 40
8 10 35
60
10 9 30
25 50 75 0 180 360 540
Along the channel (nm) Along the channel (nm)
2 550
4
500 Lattice Temperature: 20 500
nt Mean Free 6 382K 554K
450 Constant Mean Free 40 455K
450
8 400 Path 559K 400
350 60 350
10
25 50 75 0 180 360 540
2
4
500 Lattice Temperature: 20
520
500
6 383K 528K 450 T-Dependent Mean 480
40
8 Free Path 450K 539K 460
10 400 60 440
420
25 50 75 0 180 360 540

The Role of the Substrate
25 nm FD-SOI nMOSFET 25 nm FD-SOI nMOSFET
VGS=VDS=1.2V VGS=VDS=1.2V
Substrate
Gate Electrode substrate region is not with substrate region
Type of Electrode
Temperature modeled (250nm)
simulation Temperature
(K)
(K) Current Current
Current Current
Decrease Decrease
(mA/um) (mA/um)
(%) (%)
isothermal 300 300 1.7706 \ 1.7682 \
thermal 300 300 1.6557 6.49 1.6388 7.32
Dirichlet boundary
condition: Tgate=300K
VG1 Boundary condition at
Neumman VS VD Neumman
boundary boundary
condition Gate condition the bottom of the
tox1
Si02
Neumman
boundary
Source - N+ P Drain - N+
Neumman
substrate maps as a
condition boundary
Buried Si022)
BOX(SiO condition
boundary condition at
the bottom of the BOX.

Boundary Conditions
 The choice of the boundary conditions is essential for the

proper prediction of the operation of the device.
 Before we talk about boundary conditions, let us talk
about variables analogy:
T1  T2 T1  T2
q  kA 
L L kA
T V
q i
Rt R

Choice of Boundary Conditions
 Dirichlet BC on the bottom of the BOX
 Neighboring Device: ON → Dirichlet on the sides
OFF → Neumann on the sides
 Source/Drain region: THERMAL CONTACT →Dirichlet
NEAR HOT SPOT → Neumann
 Gate: THERMAL CONTACT → Dirichlet
NEAR HOT SPOT → Neumann
Worst case scenario: Neumann Boundary Conditions

everywhere except at the bottom of the BOX

Current Degradation for Different Technology
Generations and Different Boundary Conditions
50
300K
Degradation (%)
40 400K
600K 100
300K
30
Degradation (%)
80 Neumann
100
20 300K
60
Degradation (%)
400K
10 75 600K
40
Neumann
0 20 50
50 100 150
Gate Length (nm)
0
50 100 150 25
Gate: Dirichlet Gate Length (nm)
Sides: Neumann 0
50 100 150
Gate: Dirichlet Gate Length (nm)
S/D: Neumann
Sides: Dirichlet
Subst.: Dirichlet Gate: Neumann
S/D: Neumann
Subst.: Dirichlet Sides: Neumann
S/D: Neumann
Subst.: Dirichlet
Choice of a Proper Device Domain
12n 13n 25n 13n 12n
m m m m m
 Substrate was found
37nm
metal
NOT to play role metal air air metal
oxide 2nm
significant role in the
10nm
source channe drain
amount of self-heating
l
 What happens with the
inclusion of metal
50nm
BOX
source, gate drain in
the simulation domain?

Thermal Conductivity Definition
Thermal conductivity (isothermal simulation) W/m/K “Initial” thermal conductivity
distribution in the active
10 air copper 350
copper (0.025
silicon layer
(400W/m/K) air copper
20 W/m/K) 2
300 14
30 SiO2
4
250 13.5
40 silicon 6
silicon silicon source channel drain 13
50 200
8
Non-isotropic thermal 12.5
60 conductivity 150 10
(around 13-14 12
70 SiO2 (1.38W/m/K) 10 20 30 40 50 60 70
W/m/K) 100
80
50 Notice the variation of the
90
thermal conductivity
10 20 30 40 50 60 70 along the thickness

Electrostatic Potential
POTENTIAL (ISOTHERMAL SIMULATION)
10 source
gate drain
metal -0.2
metal metal
20 electr.
electr. electr.
30 -0.4
40 source drain
50 -0.6
60
-0.8
70
BOX
80 -1
90
10 20 30 40 50 60 70

Lattice Temperature Profile
380
10
source gate metal drain 370
20 metal electr. metal
electr. electr. 360
30
350
40
y(nm)
50 340
60 330
70
320
80
310
90
300
10 20 30 40 50 60 70
x(nm)

Self-Heating Effect
1-4: Conventional device
5: Extended gates
Tgate Tsource Tdrain Tsides Current Degradation
1. 300K Neumann Neumann Neumann 6.7%
2. 300K Neumann Neumann 300K 3.8%
3. Neumann Tsource Neumann 300K 11.6%
4. Neumann Tsource Neumann Neumann 38.7%
5. 300K 300K 300K Neumann 3.96%
380
2 2 420
360 400
4 4
380
6 source channel drain 340 6 source channel drain 360
8 8 340
320
10 10 320
20 40 60 20 40 60
Acoustic Optical
Applications
 Alternative Device Geometries
 Alternative Materials
Source (n+) Drain (n+)
OUR ALTERNATIVES:
Bottom
BOX gate
Si substrate
0
Dual Gate Devices 335
2 330
325
4
y (nm)
320
source drain
6 315
310
8
305
10 300
0 25 50 75
x (nm)

1. Alternative Device Geometries
Conduction band profile for 25nm DG SOI nMOSFET
0.5 Bottom of
Source the BOX
region
Source (n+) Drain (n+)
0
Bottom -0.5
BOX gate
-1
Si substrate
-1.5 Bottom
gate
20 Drain
40 region
Dual Gate Structure 60
10 20 30 40 50 60
x (nm)
y (nm)

Double-Gate SOI:
From Electrical Perspective
Double-Gate SOI:
Top
+ Enhanced SCE scalability
S D + Lower junction capacitance
+ Light doping possible
Bottom
BOX + Vt can be set by WF of metal
Tsi, Ultra-
thin gate electrode
Body, SUBSTRATE + ~2x drive current
Fully - ~2x gate capacitance
Depleted
- High Rseries,s/d  raised S/D
- Complex process

Double-Gate SOI:
From Thermal Perspective
Average acoustic and optical phonon temperature profile in the silicon layer
580
560 Higher
source channel drain
540 Number
520
of Carriers
Temperature (K)
500 optical phonon temperature profile


480
25nm dual-gate Higher Lattice
FD SOI nMOSFET
460 25nm single-gate
FD SOI nMOSFET Temperature
440
420

400
More Velocity
lattice temperature profile
380
Degradation
0 10 20 30 40 50 60 70
along the channel (nm)

A Closer Look …
Single gate lattice
temperature profile
Lattice temperature profile for undoped, single-gate 25nm FD SOI MOSFET
500
4 Average electron velocity and energy for 25nm single-gate and dual-gate FD SOI nMOSFET
10 480 x 10
18 0.7
460
20
440
16
420 0.6
30
400 14
40 380
12 0.5
360
50
340
320 Velocity (m/s) 10
Energy (eV)
60 0.4
300
10 20 30 40 50 60 70
Lattice temperature profile for 25nm DG SOI MOSFET

8
550
X= 15
Y= 9
Level= 416.422
0.3
10
X= 68
Y= 6
Level= 560.9467
6
500
20
bottom gate
4 0.2
region
set to 300K 450
30
y (nm)
2
40 400 dual-gate 0.1
0 single-gate
50
350
-2 0
60 0 25 50 75 0 25 50 75
300
along the channel (nm) along the channel (nm)
10 20 30 40 50 60 70
x (nm)
Dual gate lattice

temperature profile
25nm FD SOI nMOSFET
Where Does the Type of
Gate
temperatu
Bottom of
the BOX
Current
(mA/um)
Current
decrease
simulation re temperatu (%)
Benefit of the DG re
Structure Comes isothermal 300K 300K 1.9428 \
thermal 300K 300K 1.7644 9.18
From? thermal 400K 300K 1.6641 14.35
thermal 600K 300K 1.4995 22.82
25nm DG SOI nMOSFET

25nm DG SOI nMOSFET
(Vgate-top=Vgate-bottom=1.2V; Vdrain=1.2V; Vsource=0V; Vsubstrate=0V)
Type of Top gate Bottom Bottom of Current Current
simulation temperatur gate the BOX (mA/um) decrease
For almost the same e temperatur temperatur (%)
Current degradation e e
DG devices offer isothermal 300K 300K 300K 3.0682 \
1.5-1.7 times more thermal 300K 300K 300K 2.7882 9.13
current thermal 400K 400K 300K 2.6274 14.37
thermal 600K 600K 300K 2.3153 24.54

2. Alternative Materials
Silicon-On-Diamond and
Silicon-On-Aluminum Nitride
(SOAlN) Technologies as
viable alternatives to
Silicon-On-Insulator Devices
Standard Si technology
BOX Dielectric Kth
Material constant (W/mK)
SiO2 3.9 1.38
Diamond 5.68 2000
AlN 9.14 272
SOD technology
(Vin-V1)/(Vin-VREF)
Device
Current w/o w
SOI 0.0196 0.01869
Degradation
SOAlN 0.8 0.267
SOD 0.969 0.304
Device width=3um Device width=3um

(without substrate) (with substrate)
Device Average Average

Current Current
Current Current Current Current
(mA/um) (mA/um)
(mA/um) Decrease (%) (mA/um) Decrease (%)
isothermal isothermal
thermal thermal
SOI 1.82 1.70 7.05 1.82 1.70 7.05
SOAlN 1.85 1.82 1.55 1.88 1.84 2.18
SOD 1.84 1.81 1.41 1.84 1.82 1.08

Circuit description for heat flow in vertical direction (normal to Si/SiO2 interface) when
substrate region is modeled
Rsi 1
Thermal Resistance Value for 25nm FD Silicon-On-Insulator Structures
VIN VOUT1 with geometrical dimensions given in Table 1.
R BOX
BOX Material Rsi Rsubstr R BOX t BOX k
2 VOUT2   si
SiO2 0.02RBOX 0.05RBOX
R si t si k BOX
Rsubstr
AlN 4RBOX 10RBOX R BOX t k
 BOX  si
Diamond 31RBOX 70RBOX R substr t substr k BOX
VREF
1 Si/BOX interface
0
2 BOX/substrate interface Device vOUT1 vOUT2 vBOX=vOUT1- vOUT2
FD-SOI vIN VREF vIN-VREF
FD-SOAlN (11vIN+4VREF)/15 (10vIN+5VREF)/15 (vIN-VREF)/15
FD-SOD (70vIN+31VREF)/101 (70vIN+31VREF)/101 0
Circuit description for heat flow in vertical direction (normal to Si/SiO2 interface) when
Rsi 1
substrate region is not modeled
VIN VOUT1
RBOX
2 VOUT2
Rsubstr=0
Device vOUT1 vOUT2 vBOX=vOUT1- vOUT2
FD-SOI vIN VREF vIN-VREF

VREF
FD-SOAlN (vIN+4VREF)/5 VREF (vIN-VREF)/5
1 Si/BOX interface
0 FD-SOD (vIN+31VREF)/32 VREF (vIN-VREF)/32
2 End of the BOX

Acoustic
3
Phonon Temperature Optical Phonon Temperature
325 3
390
4 4
380
5 SOD 320 5 SOD
370
6 6
7 360
315 7
y (nm)
8 8 350
9 310 9 340
10 10 330
11 305 11 320
12 12 310
13 300 13 300
10 20 30 40 50 60 70 10 20 30 40 50 60 70
x (nm) x (nm)
3 330 3
4 SOAlN 4 SOAlN 390
5 325 5 380
6 6 370
320
7 7 360
y(nm)
8 315 8 350
9 9 340
310
10 10 330
11 11 320
305
12 12 310
13 300 13 300
10 20 30 40 50 60 70 10 20 30 40 50 60 70
x (nm) x (nm)
Conclusions
 At least energy balance treatment of phonons is needed in
conjunction with BTE solution for the electron modeling to
properly estimate self-heating effects in nano-devices
(Phonon Monte Carlo is currently being developed)
 Temperature and thickness dependent thermal conductivity
must be used to predict device reliability based on the
peak temperature of the hot spot
 Boundary conditions play crucial role on the value of the
current degradation
 Alternative materials (Diamond and AlN) and alternative
device technologies (dual gate devices) can aleviate the
problems with self-heating in Silicon on Insulator
Technology

References
 K. Raleva, D. Vasileska, S. M. Goodnick and M. Nedjalkov, Modeling Thermal
Effects in Nanodevices, IEEE Transactions on Electron Devices, vol. 55, issue 6, pp.
1306-1316, June 2008.
 K. Raleva, D. Vasileska, S. M. Goodnick, Is SOD Technology the Solution to
Heating Problems in SOI Devices?, Electron Device Letters, IEEE, Volume 29,
Issue 6, June 2008 Page(s):621 - 624.
 K. Raleva, D. Vasileska, S. M. Goodnick and T. Dzekov, “Modeling thermal effects
in nano-devices”, Journal of Computational Electronics, DOI 10.1007/s10825-008-
0189-3 © Springer Science+Business Media LLC 2008, J. Computational
Electronics, Vol. 7, pp. 226-230 (2008).
 K. Raleva, D. Vasileska and S.M. Goodnick, Influence of lattice heating on device
electrical characteristics for different technologies of FD-SOI devices, Eurotherm
Conference Proceedings, 2008.
 Invited review paper for special issue, “Semiconductor Device Modeling”,
Vasileska, D.; Mamaluy, D.; Khan, H.R.; Raleva, K.; Goodnick, S.M., Journal of
Computational and Theoretical Nanoscience, Volume 5, Number 6, June 2008 , pp.
999-1030(32).
 Invited review paper: D. Vasileska, K. Raleva, S.M. Goodnick, “Modeling
heating effects in nanoscale devices: the present and the future”, Journal of Comp.
Electronics, DOI 10.1007/s10825-008-0254-y (2008).
 (invited paper) D. Vasileska, K. Raleva and S. M. Goodnick, “Thermal Effects in
Fully-Depleted SOI Devices”, ECS Transactions, in press.

No exponential is forever…
But we can delay forever…
Gordon E. Moore, Intel

Thanks to …
AINE
Katerina Raleva, Stephen M. Goodnick
 Office of Naval Research (ONR)
 National Science Foundation


Thermal Effects in Nanoscale Devices

Hochgeladen von

Dokumentinformationen

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Thermal Effects in Nanoscale Devices

Hochgeladen von

Copyright:

Verfügbare Formate

Thermal Effects in

Nanoscale Devices. What

Arizona State University, Tempe, AZ

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

These non-classical transistor

Three variations of dual-gate

Ira A. Fulton School of Engineering

Back gate (substrate)

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

n-channel Heat Conduction

Ira A. Fulton School of Engineering

J. Lai and A. Majumdar, “Concurent

TLO 3nk B  Te  TL  nm * vd2  T  TA 

Ira A. Fulton School of Engineering

Energy loss to acoustic

Heat Diffusion Gain term due to electrons

Ira A. Fulton School of Engineering

Molecular Phonon Boltzmann Fourier Law

Superlattice Classical SOI Structures

Ira A. Fulton School of Engineering

 Under the assumption of very low electric fields, the

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Thermal conductivity (W/m/K)

• E. H. Sondheimer, “The Mean Free Path of

Ira A. Fulton School of Engineering

Initial potential, fields, positions no End of MCPS

Ira A. Fulton School of Engineering

Phonon Energy Generate a random number and

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Carriers are in the velocity

Acoustic phonon temperature Optical phonon temperature

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Constant Mean Free

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

 The choice of the boundary conditions is essential for the

Ira A. Fulton School of Engineering

Worst case scenario: Neumann Boundary Conditions

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

Ira A. Fulton School of Engineering

500 optical phonon temperature profile

Ira A. Fulton School of Engineering

320 Velocity (m/s) 10

Lattice temperature profile for 25nm DG SOI MOSFET

Dual gate lattice

25nm DG SOI nMOSFET

Ira A. Fulton School of Engineering