Sie sind auf Seite 1von 29

NCN

www.nanohub.org


ECE606:
Solid
State
Devices

Lecture
37:
Nonideal
Effects
in
MOSFET

Muhammad
Ashraful
Alam

alam@purdue.edu


Alam

ECE‐606
S09
 1
Topic
Map


Equilibrium
 DC
 Small
 Large
 Circuits



signal
 Signal

Diode


SchoDky


BJT/HBT


MOS


Alam

ECE‐606
S09
 2
Outline


1.  Flat
band
voltage



2.  Threshold
voltage
shiN
due
to
trapped
charges


3.  Physics
of
interface
traps


4.  Conclusion


REF.
Chapter
18,
SDF


Alam

ECE‐606
S09
 3
(1)
Idealized
MOS
Capacitor


Vacuum
level

ci
y
 Substrate
(p)

cs
Fm
EC

Recall
that
 EF

EV


metal
 insulator
 p
semiconductor


Alam

ECE‐606
S09
 4
Poten\al,
Field,
Charges


ci
V


cs
x

Fm

E
x


Vbi=0
 r
x


Alam

ECE‐606
S09
 5
Real
MOS
Capacitor with
M
<
S

Note
the
difference

EVAC

EC
EC
EF
EF
EV
EV

Do we need to apply less or more VG to invert the channel ?


6
Physical
Interpreta\on
of
Flatband
Voltage


E C


E C

EF


EV
 EF


EV


flat
band

Alam

ECE‐606
S09
 7
How
to
Calculate
Built‐in
or
Flat‐band
Voltage


Vacuum
level

qVbi

cs

Fm EC
Therefore,
 EF
EV

Alam

ECE‐606
S09
 8
Measure
of
Flat‐band
shiN
from
C‐V
Characteris\cs


C/Cox


Ideal
Vth

VG

Actual
Vth


Alam

ECE‐606
S09
 9
Outline


1.  Flat
band
voltage



2.  VT‐shiH
due
to
trapped
charges


3.  Physics
of
interface
traps


4.  Conclusion


Alam

ECE‐606
S09
 10
(2)
Idealized
MOS
Capacitor


Vacuum level
ci
y
 Substrate
(p)

cs
Fm
EC

Qox=0
EF
Recall that
EV

metal insulator p semiconductor

Alam

ECE‐606
S09
 11
Distributed
Trapped
charge
in
the
Oxide


EC

EF

EV

Alam

ECE‐606
S09
 12
An
Intui\ve
View

 Reduced
gate
charge



Bulk
charge

Ideal
charge‐free
oxide

‐E

0

‐E
Interface
charge

0

‐E

0


Alam

ECE‐606
S09
 13
Gate
Voltage
and
Oxide
Charge


‐E


0


Alam

ECE‐606
S09
 14
Gate
Voltage
and
Oxide
Charge


Alam

ECE‐606
S09
 15
Interpreta\on
for
Bulk
Charge



C/Cox


Ideal
VT

VG

New
VT


Alam

ECE‐606
S09
 16
Interpreta\on
for
Interface
Charge


C/Cox


Ideal
VT

VG

New
VT


Alam

ECE‐606
S09
 17
Time‐dependent
shiN
of
Trapped
Charge


C/Cox


E


Ideal
VT

VG


Sodium related bias temperature instability (BTI) issue


18
Bias
Temperature
Instability
(Experiment)

M
 O
 S
 M
 O
 S

‐
 ‐

‐
 ‐

‐
 +
 +
 ‐

‐
 +
 +
 ‐

‐
 +
+
 +
 +
 +

+
+
 ‐‐


‐
 +
+
 +
 +
 +
+
 ‐

‐
 +
 +
 +

‐
 ‐

‐
 ‐

‐
 ‐

(‐)
biases
 (+)
biases

ρion


ρion


x
 x

0.1xo
 0.9xo

0
 xo
 0
 xo

Alam

ECE‐606
S09
 19
Outline


1.  Flat
band
voltage



2.  VT‐shiN
due
to
trapped
charges


3.  Physics
of
interface
traps


4.  Conclusion


Alam

ECE‐606
S09
 20
Google
image

SiO
and
SiH
Bonds


Alam

ECE‐606
S09
 21
Interface
States


HW: Unpassivated bonds ~1014 cm-2 22


‘Annealing’
of
Interface
States


Forming
gas
anneal


H
 H
 H


Alam

ECE‐606
S09
 23
C‐V
Stretch
Out


Forming
gas
anneal


H
 H
 H


Alam

ECE‐606
S09
 24
Nature
of
Donor
and
Acceptor
Traps


Donor
level
 Acceptor
level
 Combina\on
when




Posi\ve
when
empty

 Neutral
when
empty

 both
are
present

Neutral
when
full
 Nega\ve
when
full

Alam

ECE‐606
S09
 25
Donor
like
Interface
States


C/Cox


VG

Alam

ECE‐606
S09
 26
Acceptor
like
Interface
States


0 0

-1
‐1


C/Cox


VG
Alam

ECE‐606
S09
 27
Acceptor
and
Donor
Traps
Combined


Donor-related Acceptor-related
stretchout stretchout
C/Cox


VG


Alam

ECE‐606
S09
 28
Conclusion


1)  Non‐ideal
threshold
characteris\cs
are
important

considera\on
of
MOSFET
design.


2)  The
non‐ideali\es
arise
from
differences
in
gate
and

substrate
work
func\on,
trapped
charges,
interface

states.


3)  Although
nonindeal
effects
oNen
arise
from
transistor

degrada\on,
there
are
many
cases
where
these
effects

can
be
used
to
enhance
desirable
characteris\cs.



Alam

ECE‐606
S09
 29