 STP50NE10L

N - CHANNEL 100V - 0.020Ω - 50A TO-220

STripFET POWER MOSFET
TYPE V DSS R DS(on) ID
STP50NE10L 100 V <0.025 Ω 50 A
■ TYPICAL RDS(on) = 0.020 Ω
■ EXCEPTIONAL dv/dt CAPABILITY
■ 100% AVALANCHE TESTED
■ LOW GATE CHARGE AT 100 oC
■ APPLICATION ORIENTED
CHARACTERIZATION
3
2
DESCRIPTION 1
This Power MOSFET is the latest development of
STMicroelectronics unique ”Single Feature TO-220
Size” strip-based process. The resulting
transistor shows extremely high packing density
for low on-resistance, rugged avalanche
characteristics and less critical alignment steps
therefore a remarkable manufacturing
reproducibility. INTERNAL SCHEMATIC DIAGRAM

APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING

■ SOLENOID AND RELAY DRIVERS

■ MOTOR CONTROL, AUDIO AMPLIFIERS

■ DC-DC & DC-AC CONVERTERS

■ AUTOMOTIVE ENVIRONMENT (INJECTION,

ABS, AIR-BAG, LAMPDRIVERS, Etc.)

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Un it
V DS Drain-source Voltage (VGS = 0) 100 V
V DGR Drain- gate Voltage (R GS = 20 kΩ) 100 V
V GS G ate-source Voltage ± 20 V
o
ID Drain Current (continuous) at Tc = 25 C 50 A
o
ID Drain Current (continuous) at Tc = 100 C 35 A
I DM (•) Drain Current (pulsed) 200 A
o
P tot T otal Dissipation at Tc = 25 C 150 W
Derating Factor 1 W /o C
dv/dt ( 1) Peak Diode Recovery voltage slope 6 V/ns
o
Ts tg Storage Temperature -65 to 175 C
o
Tj Max. Operating Junction Temperature 175 C
(•) Pulse width limited by safe operating area ( 1) ISD ≤ 50 A, di/dt ≤ 275 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX

May 1999 1/8

STP50NE10L

THERMAL DATA
o
R thj -case Thermal Resistance Junction-case Max 1 C/W
Rthj -amb Thermal Resistance Junction-ambient Max 62.5 oC/W
o
R thc-sink Thermal Resistance Case-sink Typ 0.5 C/W
o
Tl Maximum Lead Temperature F or Soldering Purpose 300 C

AVALANCHE CHARACTERISTICS
Symbo l Parameter Max Value Unit
IAR Avalanche Current, Repetitive or Not-Repetitive 50 A
(pulse width limited by Tj max)
E AS Single Pulse Avalanche Energy 400 mJ
(starting Tj = 25 o C, ID = IAR , V DD = 50 V)

ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)

OFF
Symbo l Parameter Test Con ditions Min. Typ. Max. Unit
V (BR)DSS Drain-source I D = 250 µA V GS = 0 100 V
Breakdown Voltage
I DSS Zero Gate Voltage V DS = Max Rating 1 µA
Drain Current (V GS = 0) V DS = Max Rating T c = 125 oC 10 µA
IGSS Gate-body Leakage V GS = ± 20 V ± 100 nA
Current (VDS = 0)

ON (∗)
Symbo l Parameter Test Con ditions Min. Typ. Max. Unit
V GS(th) Gate Threshold Voltage V DS = V GS ID = 250 µA 1 1.7 2.5 V
R DS(on) Static Drain-source On V GS = 10 V ID = 25 A 0.020 0.025 Ω
Resistance V GS = 5 V ID = 25 A 0.024 0.030 Ω
I D(o n) On State Drain Current V DS > ID(o n) x R DS(on )ma x 50 A
V GS = 10 V

DYNAMIC
Symbo l Parameter Test Con ditions Min. Typ. Max. Unit
g f s (∗) Forward V DS > ID(o n) x R DS(on )ma x I D =25 A 45 S
Transconductance
C iss Input Capacitance V DS = 25 V f = 1 MHz V GS = 0 5000 pF
C os s Output Capacitance 500 pF
C rss Reverse Transfer 180 pF
Capacitance

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 STP50NE10L

ELECTRICAL CHARACTERISTICS (continued)

SWITCHING ON
Symbo l Parameter Test Con ditions Min. Typ. Max. Unit
t d(on) Turn-on Delay T ime V DD = 50 V I D = 25 A 30 ns
tr Rise Time R G = 4.7 Ω V GS = 5 V 105 ns
(Resistive Load, see fig. 3)
Qg Total G ate Charge V DD = 80 V ID = 50 A V GS = 5 V 82 105 nC
Q gs Gate-Source Charge 17 nC
Q gd Gate-Drain Charge 49 nC

SWITCHING OFF
Symbo l Parameter Test Con ditions Min. Typ. Max. Unit
t d(of f) Turn-off Delay T ime V DD = 50 V I D = 25 A 135 ns
tf Fall T ime R G = 4.7 Ω V GS = 5 V 45 ns
(Resistive Load, see fig. 3)
tr (Voff) Off-voltage Rise T ime V clamp = 80 V I D = 50 A 45 ns
tf Fall T ime R G = 4.7 Ω V GS = 5 V 45 ns
tc Cross-over Time (Induct ive Load, see fig. 5) 85 ns

SOURCE DRAIN DIODE

Symbo l Parameter Test Con ditions Min. Typ. Max. Unit
ISD Source-drain Current 50 A
I SDM (•) Source-drain Current 200 A
(pulsed)
V SD (∗) Forward On Voltage I SD = 50 A V GS = 0 1.5 V
t rr Reverse Recovery I SD = 30 A di/dt = 100 A/µs 165 ns
Time V DD = 50 V T j = 150 o C
Q rr Reverse Recovery (see test circuit, fig. 5) 870 nC
Charge
I RRM Reverse Recovery 10.5 A
Current
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area

Safe Operating Area Thermal Impedance

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Output Characteristics Transfer Characteristics

Transconductance Static Drain-source On Resistance

Gate Charge vs Gate-source Voltage Capacitance Variations

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 STP50NE10L

Normalized Gate Threshold Voltage vs Normalized On Resistance vs Temperature

Temperature

Source-drain Diode Forward Characteristics

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STP50NE10L

Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform

Fig. 3: Switching Times Test Circuits For Fig. 4: Gate Charge test Circuit
Resistive Load

Fig. 5: Test Circuit For Inductive Load Switching

And Diode Recovery Times

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 STP50NE10L

TO-220 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
E
A

D
C

D1

L2
F1

G1

H2
G

Dia.
F
F2

L5
L9
L7

L6 L4
P011C

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 STP50NE10L

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 1999 STMicroelectronics – Printed in Italy – All Rights Reserved

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