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Description
Data Rate
1 tAA tRCD tRP
Speed Grade (MT/s) Target CL-nRCD-nRP (ns) (ns) (ns)
-062E 3200 22-22-22 13.75 13.75 13.75
-068 2933 21-21-21 14.32 (13.75) 14.32 (13.75) 14.32 (13.75)
-075E 2666 18-18-18 13.50 13.50 13.50
-075 2666 19-19-19 14.25 (13.75) 14.25 (13.75) 14.25 (13.75)
-083E 2400 16-16-16 13.32 13.32 13.32
-083 2400 17-17-17 14.16 (13.75) 14.16 (13.75) 14.16 (13.75)
-093E 2133 15-15-15 14.06 (13.50) 14.06 (13.50) 14.06 (13.50)
-093 2133 16-16-16 15.00 15.00 15.00
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Products and specifications discussed herein are subject to change by Micron without notice.
16Gb: x4, x8 TwinDie DDR4 SDRAM
Description
Table 2: Addressing
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Important Notes and Warnings
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Functional Description
Functional Description
The TwinDie DDR4 SDRAM is a high-speed, CMOS dynamic random access memory
device internally configured as two 16-bank DDR4 SDRAM devices.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like-die tested within a monolithic die package.
The DDR4 SDRAM uses a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-
nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O balls.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR4 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR4 SDRAM and edge-aligned to the
data strobes.
Read and write accesses to the DDR4 SDRAM are burst-oriented. Accesses start at a se-
lected location and continue for a programmed number of locations in a programmed
sequence. Operation begins with the registration of an ACTIVATE command, which is
then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVATE command are used to select the bank and row to be accessed. The
address bits (including CSn#, BAn, and An) registered coincident with the READ or
WRITE command are used to select the rank, bank, and starting column location for the
burst access.
This data sheet provides a general description, package dimensions, and the package
ballout. Refer to the Micron monolithic DDR4 data sheet for complete information re-
garding individual die initialization, register definition, command descriptions, and die
operation.
Industrial Temperature
The industrial temperature (IT) option, if offered, requires that the case temperature
not exceed –40°C or 95°C. JEDEC specifications require the refresh rate to double when
TC exceeds 85°C; this also requires use of the high-temperature self refresh option. Addi-
tionally, ODT resistance, IDD values, some IDD specifications and the input/output im-
pedance must be derated when T C is < 0°C or > 95°C. See the DDR4 monolithic data
sheet for details.
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Functional Block Diagrams
Rank 1
(128 Meg x 4 x 16 banks)
Rank 0
(128 Meg x 4 x 16 banks)
CS0#
CS1# PAR
CK CKE0
CKE1 TEN
CK# A[13:0],
ODT0
ODT1 RESET ACT_n,
ZQ
WE_n/A14,
ALERT_n
CAS_n/A15,
RAS_n/A16, DM
BA[1:0], DQ[3:0]
BG[1:0] DQS, DQS#
Rank 1
(64 Meg x 8 x 16 banks)
Rank 0
(64 Meg x 8 x 16 banks)
CS0#
CS1# PAR CK
CKE0
CKE1 TEN CK# A[13:0],
RESET ZQ ACT_n, ODT0
ODT1
ALERT_n WE_n/A14,
CAS_n/A15,
RAS_n/A16,
BA[1:0], TDQS#
BG[1:0] DQ[7:0]
DBI/DM/TDQS
DQS, DQS#
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – Leakages
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – Leakages
Notes: 1. MAX operating case temperature TC is measured in the center of the package, as shown
below.
2. A thermal solution must be designed to ensure that the device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the device exceeds maximum TC during
operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9µs
interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh
(ASR), if available, must be enabled.
Test point
Length (L)
0.5 (L)
0.5 (W)
Width (W)
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – Leakages
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Characteristics – AC and DC Output Measurement
Levels
Note: 1. The swing of ±0.15 × VDDQ is based on approximately 50% of the static single-ended
output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load
of 50Ω to VTT = VDDQ.
Using the same reference load used for timing measurements, output slew rate for fall-
ing and rising edges is defined and measured between V OL(AC) and V OH(AC) for single-
ended signals.
Measured
Description From To Defined by
Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC) - VOL(AC)]/ΔTRse
Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC) - VOL(AC)]/ΔTFse
VOH(AC)
Single-Ended Output Voltage (DQ)
VOL(AC)
TFse
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Characteristics – AC and DC Output Measurement
Levels
Differential Outputs
Note: 1. The swing of ±0.3 × VDDQ is based on approximately 50% of the static single-ended out-
put peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of
50Ω to VTT = VDDQ at each differential output.
Using the same reference load used for timing measurements, output slew rate for fall-
ing and rising edges is defined and measured between V OL,diff(AC) and V OH,diff(AC) for dif-
ferential signals.
Measured
Description From To Defined by
Differential output slew rate for rising edge VOL,diff(AC) VOH,diff(AC) [VOH,diff(AC) - VOL,diff(AC)]/ΔTRdiff
Differential output slew rate for falling edge VOH,diff(AC) VOL,diff(AC) [VOH,diff(AC) - VOL,diff(AC)]/ΔTFdiff
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Characteristics – AC and DC Output Measurement
Levels
VOL,diff(AC)
TFdiff
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Characteristics – AC and DC Output Measurement
Levels
VSSQ
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters
Table 12: DDR4 ICDD Specifications and Conditions - Rev. A (0° ≤ TC ≤ 85°C)
Note 1 applies to the entire table
Combined Individual Bus
Symbol Die Status Width DDR4-2133 DDR4-2400 DDR4-2666 Units
ICDD0 ICDD0 = x4, x8 83 93 103 mA
IDD0 + IDD2P + 3
ICPP0 ICPP0 = x4, x8 6 6 6 mA
IPP0 + IPP3N
ICDD1 ICDD1 = x4, x8 98 108 118 mA
IDD1 + IDD2P + 3
ICDD2N ICDD2N = x4, x8 70 80 90 mA
IDD2N + IDD2P
ICDD2NT ICDD2NT = x4, x8 80 90 100 mA
IDD2NT + IDD2P
ICDD2P ICDD2P = x4, x8 50 60 70 mA
IDD2P + IDD2P
ICDD2Q ICDD2Q = x4, x8 70 75 85 mA
IDD2Q + IDD2P
ICDD3N ICDD3N = x4, x8 80 85 95 mA
IDD3N + IDD2P
ICPP3N ICPP3N = x4, x8 6 6 6 mA
IPP3N + IPP3N
ICDD3P ICDD3P = IDD3P + IDD2P x4, x8 60 70 75 mA
ICDD4R ICDD4R = x4 163 178 198 mA
IDD4R + IDD2P + 3 x8 178 183 213
ICDD4W ICDD4W = x4 163 178 198 mA
IDD4W + IDD2P + 3 x8 178 193 213
ICDD5R ICDD5R = x4, x8 89 94 103 mA
IDD5R + IDD2P
ICPP5R ICPP5R = x4, x8 8 8 8 mA
IPP5R + IPP3N
ICDD6N ICDD6N = x4, x8 60 60 60 mA
IDD6N + IDD6N
ICDD6E ICDD6E = x4, x8 70 70 70 mA
IDD6E + IDD6E
ICDD6R2 ICDD6R = x4, x8 50 50 50 mA
IDD6R + IDD6R
ICDD6A (25°C)2 ICDD6A = x4, x8 40 40 40 mA
IDD6A + IDD6A
ICDD6A (45°C)2 ICDD6A = x4, x8 50 50 50 mA
IDD6A + IDD6A
ICDD6A (75°C)2 ICDD6A = x4, x8 70 70 70 mA
IDD6A + IDD6A
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters
Table 12: DDR4 ICDD Specifications and Conditions - Rev. A (0° ≤ TC ≤ 85°C) (Continued)
Note 1 applies to the entire table
Combined Individual Bus
Symbol Die Status Width DDR4-2133 DDR4-2400 DDR4-2666 Units
ICDD7 ICDD7 = x4 278 288 303 mA
IDD7 + IDD2P + 3 x8 228 238 253
ICPP7 ICPP7 = x4 28 28 28 mA
IPP7 + IPP3N x8 18 18 18
ICDD8 ICDD8 = IDD8 + IDD8 x4, x8 40 40 40 mA
Notes: 1. ICDD values reflect the combined current of both individual die. IDDx represents individu-
al die values.
2. ICDD , ICDD6A, and ICDD6E values are verified by design and characterization, and may not
be subject to production test.
3. ICDD values must be derated (increased) when operated outside of the range 0°C ≤ TC ≤
85°C. They must also be derated when using features such as CAL, CA Parity, Read/Write
DBI, AL, Gear-down, Write CRC, 2X/4X REF, and DLL disabled. Refer to the 8Gb monolith-
ic data sheet for all derating values. Derating values apply to each individual IDDx that
make up the combined ICDD
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters
Table 13: DDR4 ICDD Specifications and Conditions - Rev. B (0° ≤ TC ≤ 85°C)
Note 1 applies to the entire table
Combined Individual Bus
Symbol Die Status Width DDR4-2133 DDR4-2400 DDR4-2666 Units
ICDD0 ICDD0 = x4 68 71 74 mA
IDD0 + IDD2P + 3 x8 73 76 79
ICPP0 ICPP0 = x4, x8 6 6 6 mA
IPP0 + IPP3N
ICDD1 ICDD1 = x4 80 83 86 mA
IDD1 + IDD2P + 3 x8 85 88 91
ICDD2N ICDD2N = x4, x8 58 59 60 mA
IDD2N + IDD2P
ICDD2NT ICDD2NT = x4, x8 70 75 75 mA
IDD2NT + IDD2P
ICDD2P ICDD2P = x4, x8 50 50 50 mA
IDD2P + IDD2P
ICDD2Q ICDD2Q = x4, x8 55 55 55 mA
IDD2Q + IDD2P
ICDD3N ICDD3N = x4 60 63 66 mA
IDD3N + IDD2P x8 65 68 71
ICPP3N ICPP3N = x4, x8 6 6 6 mA
IPP3N + IPP3N
ICDD3P ICDD3P = IDD3P + IDD2P x4 55 57 59 mA
x8 60 62 64
ICDD4R ICDD4R = x4 138 138 149 mA
IDD4R + IDD2P + 3 x8 153 163 174
ICDD4W ICDD4W = x4 123 131 140 mA
IDD4W + IDD2P + 3 x8 143 151 160
ICDD5R ICDD5R = x4, x8 75 78 81 mA
IDD5R + IDD2P
ICPP5R ICPP5R = x4, x8 8 8 8 mA
IPP5R + IPP3N
ICDD6N ICDD6N = x4, x8 60 60 60 mA
IDD6N + IDD6N
ICDD6E ICDD6E = x4, x8 70 70 70 mA
IDD6E + IDD6E
ICDD6R2 ICDD6R = x4, x8 40 40 40 mA
IDD6R + IDD6R
ICDD6A (25°C)2 ICDD6A = x4, x8 17.2 17.2 17.2 mA
IDD6A + IDD6A
ICDD6A (45°C)2 ICDD6A = x4, x8 40 40 40 mA
IDD6A + IDD6A
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters
Table 13: DDR4 ICDD Specifications and Conditions - Rev. B (0° ≤ TC ≤ 85°C) (Continued)
Note 1 applies to the entire table
Combined Individual Bus
Symbol Die Status Width DDR4-2133 DDR4-2400 DDR4-2666 Units
ICDD6A (75°C)2 ICDD6A = x4, x8 60 60 60 mA
IDD6A + IDD6A
ICDD7 ICDD7 = x4 203 213 228 mA
IDD7 + IDD2P + 3 x8 198 203 208
ICPP7 ICPP7 = x4 19 20 21 mA
IPP7 + IPP3N x8 18 18 18
ICDD8 ICDD8 = IDD8 + IDD8 x4, x8 50 50 50 mA
Notes: 1. ICDD values reflect the combined current of both individual die. IDDx represents individu-
al die values.
2. ICDD6R , ICDD6A, and ICDD6E values are verified by design and characterization, and may
not be subject to production test.
3. ICDD values must be derated (increased) when operated outside of the range 0°C ≤ TC ≤
85°C. They must also be derated when using features such as CAL, CA Parity, Read/Write
DBI, AL, Gear-down, Write CRC, 2X/4X REF, and DLL disabled. Refer to the 8Gb monolith-
ic data sheet for all derating values. Derating values apply to each individual IDDx that
make up the combined ICDD
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters
Table 14: DDR4 ICDD Specifications and Conditions - Rev. D (0° ≤ TC ≤ 85°C)
Note 1 applies to the entire table
Combined Individual Bus
Symbol Die Status Width DDR4-2133 DDR4-2400 DDR4-2666 Units
ICDD0 ICDD0 = x4 68 71 74 mA
IDD0 + IDD2P + 3 x8 73 76 79
ICPP0 ICPP0 = x4, x8 6 6 6 mA
IPP0 + IPP3N
ICDD1 ICDD1 = x4 80 83 86 mA
IDD1 + IDD2P + 3 x8 85 88 91
ICDD2N ICDD2N = x4, x8 58 59 60 mA
IDD2N + IDD2P
ICDD2NT ICDD2NT = x4, x8 70 75 75 mA
IDD2NT + IDD2P
ICDD2P ICDD2P = x4, x8 50 50 50 mA
IDD2P + IDD2P
ICDD2Q ICDD2Q = x4, x8 55 55 55 mA
IDD2Q + IDD2P
ICDD3N ICDD3N = x4 65 68 71 mA
IDD3N + IDD2P x8 70 73 76
ICPP3N ICPP3N = x4, x8 6 6 6 mA
IPP3N + IPP3N
ICDD3P ICDD3P = IDD3P + IDD2P x4 55 57 59 mA
x8 60 62 64
ICDD4R ICDD4R = x4 128 138 149 mA
IDD4R + IDD2P + 3 x8 153 163 174
ICDD4W ICDD4W = x4 133 141 150 mA
IDD4W + IDD2P + 3 x8 153 160 170
ICDD5R ICDD5R = x4, x8 81 83 86 mA
IDD5R + IDD2P
ICPP5R ICPP5R = x4, x8 8 8 8 mA
IPP5R + IPP3N
ICDD6N ICDD6N = x4, x8 62 62 62 mA
IDD6N + IDD6N
ICDD6E ICDD6E = x4, x8 72 72 72 mA
IDD6E + IDD6E
ICDD6R2 ICDD6R = x4, x8 42 42 42 mA
IDD6R + IDD6R
ICDD6A (25°C)2 ICDD6A = x4, x8 17.2 17.2 17.2 mA
IDD6A + IDD6A
ICDD6A (45°C)2 ICDD6A = x4, x8 42 42 42 mA
IDD6A + IDD6A
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters
Table 14: DDR4 ICDD Specifications and Conditions - Rev. D (0° ≤ TC ≤ 85°C) (Continued)
Note 1 applies to the entire table
Combined Individual Bus
Symbol Die Status Width DDR4-2133 DDR4-2400 DDR4-2666 Units
ICDD6A (75°C)2 ICDD6A = x4, x8 62 62 62 mA
IDD6A + IDD6A
ICDD6A (95°C)2 ICDD6A = x4, x8 72 72 72 mA
IDD6A + IDD6A
ICDD7 ICDD7 = x4 203 213 228 mA
IDD7 + IDD2P + 3 x8 198 203 208
ICPP7 ICPP7 = x4 19 20 21 mA
IPP7 + IPP3N x8 18 18 18
ICDD8 ICDD8 = IDD8 + IDD8 x4, x8 50 50 50 mA
Notes: 1. ICDD values reflect the combined current of both individual die. IDDx represents individu-
al die values.
2. ICDD6R , ICDD6A, and ICDD6E values are verified by design and characterization, and may
not be subject to production test.
3. ICDD values must be derated (increased) when operated outside of the range 0°C ≤ TC ≤
85°C. They must also be derated when using features such as CAL, CA Parity, Read/Write
DBI, AL, Gear-down, Write CRC, 2X/4X REF, and DLL disabled. Refer to the 8Gb monolith-
ic data sheet for all derating values. Derating values apply to each individual IDDx that
make up the combined ICDD
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters
Table 15: DDR4 ICDD Specifications and Conditions - Rev. J (0° ≤ TC ≤ 85°C)
Note 1 applies to the entire table
Combined Individual Bus
Symbol Die Status Width DDR4-2133 DDR4-2400 DDR4-2666 Units
ICDD0 ICDD0 = x4 57 59 61 mA
IDD0 + IDD2P x8 59 61 63
ICPP0 ICPP0 = x4, x8 6 6 6 mA
IPP0 + IPP3N
ICDD1 ICDD1 = x4 70 72 73 mA
IDD1 + IDD2P x8 74 76 78
ICDD2N ICDD2N = x4, x8 50 51 52 mA
IDD2N + IDD2P
ICDD2NT ICDD2NT = x4, x8 56 58 60 mA
IDD2NT + IDD2P
ICDD2P ICDD2P = x4, x8 44 44 44 mA
IDD2P + IDD2P
ICDD2Q ICDD2Q = x4, x8 48 48 48 mA
IDD2Q + IDD2P
ICDD3N ICDD3N = x4 56 58 60 mA
IDD3N + IDD2P x8 57 59 61
ICPP3N ICPP3N = x4, x8 6 6 6 mA
IPP3N + IPP3N
ICDD3P ICDD3P = IDD3P + IDD2P x4 50 51 52 mA
x8 51 52 53
ICDD4R ICDD4R = x4 127 136 147 mA
IDD4R + IDD2P x8 150 160 170
ICDD4W ICDD4W = x4 113 122 130 mA
IDD4W + IDD2P x8 130 138 147
ICDD5R ICDD5R = x4, x8 66 67 67 mA
IDD5R + IDD2P
ICPP5R ICPP5R = x4, x8 8 8 8 mA
IPP5R + IPP3N
ICDD6N ICDD6N = x4, x8 64 64 64 mA
IDD6N + IDD6N
ICDD6E ICDD6E = x4, x8 110 110 110 mA
IDD6E + IDD6E
ICDD6R2 ICDD6R = x4, x8 40 40 40 mA
IDD6R + IDD6R
ICDD6A (25°C)2 ICDD6A = x4, x8 16.4 16.4 16.4 mA
IDD6A + IDD6A
ICDD6A (45°C)2 ICDD6A = x4, x8 40 40 40 mA
IDD6A + IDD6A
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16Gb: x4, x8 TwinDie DDR4 SDRAM
Electrical Specifications – ICDD Parameters
Table 15: DDR4 ICDD Specifications and Conditions - Rev. J (0° ≤ TC ≤ 85°C) (Continued)
Note 1 applies to the entire table
Combined Individual Bus
Symbol Die Status Width DDR4-2133 DDR4-2400 DDR4-2666 Units
ICDD6A (75°C)2 ICDD6A = x4, x8 60 60 60 mA
IDD6A + IDD6A
ICDD6A (95°C)2 ICDD6A = x4, x8 110 110 110 mA
IDD6A + IDD6A
ICDD7 ICDD7 = x4 188 198 212 mA
IDD7 + IDD2P x8 183 188 193
ICPP7 ICPP7 = x4 14 14 14 mA
IPP7 + IPP3N x8 13 13 13
ICDD8 ICDD8 = IDD8 + IDD8 x4, x8 36 36 36 mA
Notes: 1. ICDD values reflect the combined current of both individual die. IDDx represents individu-
al die values.
2. ICDD6R , ICDD6A, and ICDD6E values are verified by design and characterization, and may
not be subject to production test.
3. ICDD values must be derated (increased) when operated outside of the range 0°C ≤ TC ≤
85°C. They must also be derated when using features such as CAL, CA Parity, Read/Write
DBI, AL, Gear-down, Write CRC, 2X/4X REF, and DLL disabled. Refer to the 8Gb monolith-
ic data sheet for all derating values. Derating values apply to each individual IDDx that
make up the combined ICDD
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. G 10/19 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8 TwinDie DDR4 SDRAM
DRAM Package Electrical Specifications
Table 16: DRAM Package Electrical Specifications for x4, x8, and x16 DDP Devices
Notes 1-2 apply to the entire table
DDR4-1600, 1866, 2133,
2400, 2666, 2933, 3200
Parameter Symbol Min Max Unit Notes
Input/output Zpkg ZIO 35 60 ohm 3
Package delay TdIO 60 120 ps 3
Lpkg LIO – 5.5 nH
Cpkg CIO – 4 pF
DQSL_t/DQSL_c/ Zpkg ZIO DQS 35 60 ohm
DQSU_t/DQSU_c Package delay TdIO DQS 60 120 ps
Lpkg LIO DQS – 5.5 nH
Cpkg CIO DQS – 4 pF
DQSL_t/DQSL_c, Delta Zpkg DZIO DQS – 5 ohm 4
DQSU_t/DQSU_c, Delta delay DTdIO DQS – 5 ps 4
Input CTRL pins Zpkg ZI CTRL 30 70 ohm 5
Package delay TdI CTRL 60 120 ps 5
Lpkg LI CTRL – 7.5 nH
Cpkg CI CTRL – 4 pF
Input CMD ADD Zpkg ZI ADD CMD 30 60 ohm 6
pins Package delay TdI ADD CMD 60 120 ps 6
Lpkg LI ADD CMD – 7.5 nH
Cpkg CI ADD CMD – 4 pF
CK_t, CK_c Zpkg ZCK 30 60 ohm
Package delay TdCK 60 120 ps
Delta Zpkg DZDCK – 5 ohm 7
Delta delay DTdDCK – 5 ps 7
Input CLK Lpkg LI CLK – 7.5 nH
Cpkg CI CLK – 4 pF
ZQ Zpkg ZO ZQ – 50 ohm
ZQ delay TdO ZQ 30 135 ps
ALERT Zpkg ZO ALERT 30 60 ohm
ALERT delay TdO ALERT 60 110 ps
Notes: 1. The values in this table are guaranteed by design/simulation only, and are not subject to
production testing.
2. Package implementations should satisfy targets if the Zpkg and package delay fall with-
in the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maximum
values shown. The package design targets are provided for reference, system signal sim-
ulations should not use these values but use the Micron package model.
3. ZIO and TdIO apply to DQ, DM, DQS_c, DQS_t, TDQS_t, and TDQS_c.
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16Gb_x4_x8_2cs_TwinDie.pdf - Rev. G 10/19 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8 TwinDie DDR4 SDRAM
DRAM Package Electrical Specifications
4. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO
(DQS_t), TdIO (DQS_c) for delay (Td).
5. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE.
6. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, and WE_n.
7. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c
for delay (Td).
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. G 10/19 EN 22 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8 TwinDie DDR4 SDRAM
Package Dimensions
Package Dimensions
Seating plane
A 0.1 A
A
B
C
D
13 ±0.1 E
F
9.6 CTR G
H
J
K
L
M
0.8 TYP N
9.5 ±0.1
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16Gb_x4_x8_2cs_TwinDie.pdf - Rev. G 10/19 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8 TwinDie DDR4 SDRAM
Package Dimensions
Figure 8: 78-Ball FBGA Die Rev. B/Die Rev. D (package code NRE)
Seating plane
A 0.12 A
78X Ø0.47
Dimensions apply Ball A1 ID
to solder balls post- (covered by SR) Ball A1 ID
reflow on Ø0.42 SMD
ball pads. 9 8 7 3 2 1
A
B
C
D
E
12 ±0.1 F
9.6 CTR G
H
J
K
L
M
0.8 TYP
N
8 ±0.1
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. G 10/19 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8 TwinDie DDR4 SDRAM
Package Dimensions
Seating plane
A 0.12 A
E
11 ±0.1
F
H
9.6 CTR J
M
0.8 TYP
N
7.5 ±0.1
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. G 10/19 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.