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HFAN-06.0.1
Rev.2; 04/08
clock
Figure 5 shows a functional diagram of a two-tap Adequate performance can be achieved with a single
digital FIR transmit equalizer implemented in a delay (two taps) as shown, but up to five taps may
system SERDES transceiver IC, where recovered be appropriate for signal paths with complex
clock and data are both present. The transfer frequency response characteristics. Of course,
Application Note HFAN-06.0.1 (Rev.2, 04/08) Maxim Integrated Products
Page 4 of 6
similar performance can also be achieved with an sin2(x)/x2 spectrum characteristic of NRZ signals.
analog network; however, in either case, the amount This approach is stable, converges quickly to the
of transmit equalization (digital or analog) is limited correct response and is amenable to a low power
to around 9dB of maximum boost, because peaking implementation.
results in large signal swings. Large swings are
difficult to implement, consume power in the
Flat Variable
drivers, and often present an EMI challenge. Amp Attenuator
SDI+ SDO+
CML Limiting
In Amp
SDI- SDO-
BPF/Power
BPF/Power
Boost Variable
Detector
Detector
Amp Attenuator
LOS
When maximum performance (longest signal path) Loop
Settable Rx Equalizer