www.ietdl.

org
Published in IET Power Electronics
Received on 17th January 2011
Revised on 20th February 2012
doi: 10.1049/iet-pel.2011.0018

ISSN 1755-4535

Model-based methodology using modified sneak

circuit analysis for power electronic converter
fault diagnosis
R.R. Soman1 E.M. Davidson1 S.D.J. McArthur1 J.E. Fletcher2 T. Ericsen2,3
1
Advanced Electrical Systems Group, Institute for Energy and Environment, Department of Electronic and Electrical
Engineering, University of Strathclyde, Glasgow, UK
2
School of Electrical Engineering and Telecommunications, University of New South Wales, NSW, Australia
3
US Office of Naval Research, Arlington, Virginia, USA
E-mail: raj.soman@eee.strath.ac.uk

Abstract: This study presents a novel research methodology and approach for diagnosing pertinent failures for power electronic
converters. The concept of the generalised connection matrix for a sneak circuit analysis is used in this research. A novel
modification to this process shown in this study produces a usable feature that provides unique signatures under fault
scenarios and could be used to diagnose faults. The novelty lies in using component currents to form the generalised
connection matrix. This study presents the results obtained using data collected from fault scenarios on a hardware set-up for
the dc – dc buck converter.

Nomenclature system (DCZEDS) following the integrated fight through

power (IFTP) approach [2] that is envisioned for US Navy
C1 Input-side filter capacitor warships. The primary objective of the FACS is to take
C2 Output-side filter capacitor necessary action to prevent the system from becoming
unstable and to maintain successful mission control after
L1 Inductor
the action of detecting and isolating faults. Owing to a lack
S1 Semiconductor switch of benchmark systems, the need to understand failures
S2 Freewheeling diode and their effects is vital for efficient fault identification,
V1 Input voltage location and accommodation. Furthermore, the fundamental
differences between shipboard power systems (SPSs) and
V2 Output voltage
land-based systems [3] impose analytical challenges relating
IIN Input current to system behaviour under various operating conditions.
IOUT Output current A preliminary failure mode and effects analysis (FMEA)
IC1 Current through capacitor C1 is proposed as the first step towards achieving the overall
FACS for the medium-voltage DC (MVDC) SPS [4] as a
IC2 Current through capacitor C2 detailed FMEA is the logical starting point to understand
IS1 Current through switch S1 faults and failures in a system or component [5]. This paper
IS2 Current through diode S2 reports focused research stemming from the application of
IL1 Current through inductor L1 relatively new and unproven power electronic equipment
within the envisioned DCZEDS. The new power electronics
|S1on| Final determinant equation for switch S1’s on technology will make possible the plug-and-play operations
state concept of power electronic building block (PEBB)-based
|S1off| Final determinant equation for switch S1’s off devices [6] and rapid power changes (both in quantity and
state direction), thereby facilitating a distributed power and
energy management approach. The automated operation
of such a distributed approach will also introduce risks in
1 Introduction handling of power swings, stability and degradation of
physical parts of power system components. Therefore the
The overall aim of the research reported in this paper is the move towards zonal distribution architecture requires
development of a fault-accommodating control system research into de-risking the system from the effects of faults
(FACS) [1] for the notional DC zonal electrical distribution at all levels, that is component, device, sub-system (zone)

IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813–826 813

doi: 10.1049/iet-pel.2011.0018 & The Institution of Engineering and Technology 2012
www.ietdl.org
and system level. Another aspect of the future warship is a
70% (or greater) decrease in the number of crew [7] and the
subsequent increase in automation. Automated diagnostics
may have a number of benefits, the major ones are
enhanced decision support for the on-board crew and
system protection and control.
Fig. 1 shows the zonal MVDC system modelled on a
real-time digital simulator (RTDS) [8, 9] at the Centre for
Advanced Power Systems (CAPS) at Florida State
University (FSU). The architecture follows a multi-zonal,
IFTP approach in order to maximise the operational
capability of the SPS even when the ship is experiencing
adverse conditions, for example, unexpected damage. Ship
service loads are distributed in load centres in four zones,
from bow to stern along the ship, and are fed MVDC
power from both port and starboard DC buses which run
longitudinally along the ship. The zonal load centre
topology is illustrated in Fig. 2 showing the use of various
converter types for the dc – dc and dc – ac power conversions. Fig. 2 Zonal load centre topology
Power electronic conversion forms an integral part of Image courtesy CAPS-FSU
these topologies [1 – 4]. Power electronic converters provide
increased controllability and flexibility in power systems
and find increasing application at various power levels.
Among converter topologies, multi-level and cascaded for fault identification. For the purpose of demonstrating
types have emerged as an important technology in high- such a methodology, the dc – dc buck converter was chosen
power applications [10 – 14]. The evolution of existing by the authors for analysis into fault diagnosis at the device
power semiconductor switches Gate turn-off thyristor and component level. This paper presents a novel approach
(GTO), insulated gate bipolar transistor (IGBT) and the combining FMEA to focus fault diagnosis research with
development of new devices (e.g. integrated gate- sneak circuit analysis (SCA) and heuristics. A heuristics-
commutated thyristor (IGCT), injection enhanced gate based fault diagnosis method using a novel modification to
transistor (IEGT) have allowed the increase of power and conventional SCA is presented. A hardware set-up was used
voltage ratings of electronic converters [15]. to generate data for the fault cases studied. The modified
The research-reported details a methodology aimed at SCA-based diagnostic feature was applied to discriminate
providing high-level diagnostics for crew decision support between the different faults and the normal circuit state.
at system and sub-system levels and focuses on component The results are presented in the form of graphs and
level and incipient failures to provide a general framework confusion matrices.

Fig. 1 Medium-voltage dc shipboard architecture modelled at CAPS-FSU on the RTDS

Image courtesy CAPS-FSU

814 IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813 –826
& The Institution of Engineering and Technology 2012 doi: 10.1049/iet-pel.2011.0018

2 Related research
2.1 System-level diagnostics, reconfiguration and
supporting research
The move towards a dc distribution system places emphasis
on a greater use of power electronics equipment as
described in Section 1. Advances in power electronics make
it feasible and possible to deploy the envisioned power
distribution architecture. The challenges of adopting a dc
power distribution system for ships are highlighted by
Baran and Mahajan [16]. Stability issues relating to the
proposed dc architecture were discussed in [17] and a
security assessment is reported by Momoh et al. [18].
Momoh and Ishola-Salawu [19] discuss a neural network
application for arcing fault detection. Butler-Purry [20],
Butler-Purry and Srivastava [21] and Butler-Purry and
Sarma [22] report the use of multi-agent systems, expert
systems and self-healing aspects for the SPS. Agent-based
reconfiguration is also reported by Baran and Mahajan [23].
2.2 Power electronics development and device/
component level diagnostic research
The field of high-power drives has been an active research and
development area of power electronic application in the last
decade. Many industrial processes have increased power-
level needs, giving rise to the development of new power
semiconductors, converter topologies and control methods.
A survey of the most important converter topologies with
related control schemes has been presented in [24].
Research has also focused on associated fault diagnosis for
power electronic equipment. A variety of techniques have
been proposed and employed for diagnosing faults in the
different types of power converters and their components.
The techniques range from comparing measured values of
input and output quantities to detect discrepancies; Artificial
Intelligence (AI)-based techniques like neural networks,
fuzzy systems; statistical techniques like Fourier transforms
and wavelets and model-based methods. Furthermore, the
diagnostics proposed include higher level device diagnosis
as well at the internal component level.
Literature exists for voltage–source inverter fault diagnostics
using normalised dc components [25], open circuit fault
detection by pole-voltage measurement [26] and also using
output voltage frequency analysis [27]. Dc link current shapes
were utilised to diagnose faults in zero-voltage switching
converters [28]. For multi-level inverter a fuzzy-based
diagnosis approach is presented in [29], whereas an AI-based
diagnosis and reconfiguration technique is reported in
[30]. Application of wavelets to detect faults in power systems
and conversion modules has been demonstrated in [31, 32].
An approach using rotor current space vector angle patterns to
detect short and open circuit faults for rectifiers in a sub-
synchronous cascade drive is detailed in [33]. Design of
ground fault detection and overvoltage limiting for three-
level pulse width modulation (PWM) inverter is covered in
[34–36]. Further, Rothenhagen and Fuchs [37] evaluate
different fault diagnosis strategies for a voltage–source
inverter-fed variable speed drive comparing MATLAB-
SIMULINK results with an experimental setup. Here, a
comparison is made among fault-detection techniques such as
Park’s vector approach, slope method and variations of using
direct current methods. A comprehensive comparison and
evaluation of over a total of 30 diagnostic methods mainly for
IGBT open-circuit and short-circuit faults are provided in [38].
IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813–826
doi: 10.1049/iet-pel.2011.0018
www.ietdl.org
Filter capacitors have been the focus of component-level
fault diagnosis apart from previously mentioned literature
for semiconductor switch open- and short-circuit faults.
Capacitor failures and their diagnosis are addressed in
[39 – 41]. A strategy is explained in [42] to find the
condition of an aluminium electrolytic capacitor based on
factors such as equivalent series resistance, capacitance and
dissipation factor values, which change with temperature,
frequency, current ripple as well as ageing. A review of
intelligent techniques applied for fault diagnosis in power
electronics is presented in [43]. A model-based diagnostic
system trained with the machine learning technology for
inverters feeding electric drives is presented in [44].
2.3 Concept of fault accommodation
Fault accommodation is a related area of research which takes
the role of automated fault diagnosis a step further [45, 46]. It
could be viewed as a type of fault tolerance wherein the
system is reconfigured to operate at the best possible
efficiency even with the presence of one or more faults.
Although fault tolerance could be achieved in its simplest
form using redundancy, fault accommodation in theory is
expected to adapt controller parameters or reconfiguration
of the system to avoid and/or minimise the consequences of
a fault where performance may degrade. A simple well-
established way of fault accommodation is based on pre-
designed controllers, which are trained offline in known and
expected failure modes. Thereafter, appropriate online
failure accommodation techniques are suggested by a fault
diagnosis system which analyses fault patterns online.
Further related work on this methodology can be found in
[47 – 50]. Similar to fault diagnosis research activities, most
of the fault accommodation schemes are primarily
developed based on the powerful and well-understood
linear control methodology. Fig. 3 shows the various fault
accommodation techniques.
2.4 Reliability analyses
As mentioned earlier, a lack of benchmark systems makes it
vital to understand various pertinent faults and their
associated risks. Following this process, research diagnosing
these faults can be undertaken. Owing to this pressing need
of understanding system failure at all levels, attention was
turned to reliability analysis techniques.
Reliability analysis techniques such as FMEA can be used
to support reliability, maintainability, testability, safety and
logistics analyses. When performed in an accurate and
timely fashion, FMEA information can be used to aid the
design of test systems, the development of trouble-shooting
procedures, the planning of scheduled maintenance and
the development of integrated diagnostic capabilities. In
addition, an effective FMEA presents an examination of a
system’s strengths and weaknesses [51 – 54]. The two
approaches to FMEA, functional FMEA and hardware
FMEA [5], were used in this research and their application
is reported in [1].
Another reliability analysis method called SCA was studied
to be utilised in this research. SCA is conventionally used
during design phases of electronic circuits to help detect
unwanted current paths so that the circuit could be
redesigned if necessary. Although designing a new
electrical circuit is not a part of this research, conventional
SCA was modified to produce diagnostic features able to
differentiate between different fault states for the dc – dc
815
& The Institution of Engineering and Technology 2012
www.ietdl.org
Fig. 3 Known fault accommodation techniques [45]
buck converter. This approach forms the novelty of this
research as explained in later sections.
2.5 Motivation for research reported in this paper
The research work across the various categories described
encompasses studies directly related to the SPS fault issues
as well as indirectly related but relevant fields such as
general applicable power electronic diagnostics. The
research mainly focuses on system-level issues such as
system reconfiguration to accommodate faults. Power
electronics research focuses on component failures wherein
the devices are utilised on terrestrial systems and grids. The
gap in research for the particular case presented in this
paper exists for high-level diagnostics that aids in decision
support for the shipboard crew, capable of indicating
failures and faults both at the component level as well as at
subsequently higher levels. The methodology and approach
reported highlights the application of the research novelty
for component level faults in the dc –dc power converter.
The potential of the proposed method to upgrade to zonal
and system level fault diagnosis is a matter of further study
that could be either conducted on a real-time digital
simulation system or on a scaled-down hardware test-bed
developed to mimic the proposed warship architecture.
3 Research novelty
3.1 Approach using FMEA to focus research for
the novel shipboard architecture
This research follows a methodology informed through a
detailed FMEA for the novel SPS architecture. FMEA was
conducted beginning at the device level gradually moving
to sub-system (zone) and system levels [1]. FMEA done on
the buck converter was used to increase understanding
about its component-level faults and their effects. This
information is then used for simulating fault scenarios to
generate data used for further research and analysis into
diagnostics. The data are used to calculate circuit currents
and voltages applying circuit laws and component models
816
& The Institution of Engineering and Technology 2012
Fig. 4 Research approach beginning with FMEA leading to
focusing diagnostic research for identified pertinent failures
[55] by using local measurements (input/output currents and
voltages) and values of component parameters. The
advantage lies in the fact that additional sensors are not
needed to obtain measurements of quantities required.
Fig. 4 explains the proposed approach to identify pertinent
failures in a buck converter circuit to inform and direct
further research.
3.2 Modification of SCA technique to produce
usable features for diagnosis of faults
The other aspect of the novelty lies in the modification of
SCA to output usable features that were effectively
employed to differentiate between fault scenarios. The
modification differs from the convention of using
component symbols to form the generalised connection
matrix as actual current and voltage values are used to form
the generalised connection matrix. The determinant of the
generalised connection matrix outputs numeric values that
are shown to differentiate between various operating
scenarios of the buck converter circuit.
Data for various fault cases were generated using a buck
converter hardware circuit. The proposed novel approach
was then used to compute features using this simulation
data. Employing the projective adaptive resonance theory
(PART) algorithm [56], heuristics were generated utilising
the software tool Weka [57]. Thereafter, these rules were
encoded using conditional statements (IF – ELSE) and tested
on the data offline to check the diagnostic efficiency. The
results showed promising classification rates which have
IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813 –826
doi: 10.1049/iet-pel.2011.0018

Fig. 5 Methodology to diagnose pertinent failures in a buck
converter using proposed modified SCA technique and heuristic
classification
been elaborated in later sections. This approach is shown in
Fig. 5.
The PART algorithm is based on the assumption that the
model equations of PART (a large-scale singularly
perturbed system of differential equations having a reset
mechanism) have regular computational performance. The
PART neural network developed by Cao and, rule-based
system developed by Wu have been shown to be effective
in clustering data sets in high-dimensional spaces. The
proofs and simulation results are available for further
reading in [56]. The PART functionality in Weka was
chosen as it produces IF – ELSE rules that can be easily
read and interpreted as opposed to other formats such as
decision trees produced by a similar classification algorithm
called J48 (which is an extension of C4.5).
4 Sneak circuit analysis
4.1 SCA definition
SCA [58 – 61] is a functional reliability analysis technique
with the potential of detecting unintended and thereby
undesirable system operation. A sneak circuit is a latent
path or condition that inhibits the desired function or
causes undesired operation to occur. In contrast to failure
effects, a sneak circuit does not require a component
failure to occur. SCA is a unique method of evaluating the
electrical circuit topology to detect specific patterns which
are characteristic of sneak paths. A sneak condition or path
is present in a circuit, as designed, but may not always be
active.
4.1.1 Obtaining sneak paths for an electrical circuit
by constructing its directed graph: The sneak paths
or sneak circuits are established through the determinant
of the generalised connection matrix [57, 58] which in
turn is formulated by constructing the directed graph of
the circuit analysed. In general, a directed graph of a
circuit depicts component connections with directions of
associated currents and voltages. From this, an N × N
(where N ¼ no. of nodes) matrix can be constructed using
component symbols. This matrix is known as the
generalised connection matrix and the determinant of this
matrix provides sneak paths represented in terms of
component symbols. The determinant could output
numbers as well as terms with squared or higher order
component symbols. These are ignored as they do not
provide information regarding a logical path, for example,
a number is not a circuit path and a squared component
symbol does not indicate its own connection with other
components in the circuit. Thus, what remains are
possible and legitimate current paths within the given
circuit. This information about sneak paths is useful in
IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813–826
doi: 10.1049/iet-pel.2011.0018
www.ietdl.org
the design phase of a device in order to modify a design
if a sneak path is identified. This feature is not utilised in
this research. Instead, the novel modification applied
yields numeric values or signatures from the determinant
of the generalised connection matrix that are shown to
be useful for differentiating between various operating
scenarios.
5 Application of methodology to buck
converter circuit
5.1 Device – buck converter circuit
Fig. 6 shows the dc – dc buck converter circuit used for the
analysis.
5.2 Fault cases studied
The common failure modes for components like
semiconductor switches and diodes are typically open and
short circuits. Similar failure modes exist for capacitors and
inductors. Electrolytic capacitors display electrolyte leakage
and dielectric breakdown, whereas inductors may suffer
inter-turn winding faults. Table 1 shows fault scenarios
conducted for the buck converter considering single and
multiple fault cases. The notion of incipient capacitor or
inductor failure was simulated on hardware by manually
reducing the net capacitance and inductance, respectively.
5.3 Different states of the circuit
The buck converter circuit has two distinct states when the
switch S1 is ON and when it is OFF. The equivalent
circuits during these two states are shown in Figs. 7a and
8a. The modified directed graphs are constructed for the
two states separately which are shown in Figs. 7b and 8b.
Fig. 6 Buck converter circuit
Table 1 Fault cases conducted for buck converter
Component Failure induced
capacitor (C2) (single fault) degrading – net filter capacitance
was reduced to half the original
value at start
semiconductor Switch (S1) 1. short circuit
(single fault) 2. open circuit
inductor (L1) (single fault) net inductance was reduced to half
the original value at start
capacitor (C2) and inductor values of both C2 and L1 reduced to
(L1) (multiple fault) half their original amounts
817
& The Institution of Engineering and Technology 2012
www.ietdl.org
two states are

|S1on | = IC1 × IIN × V1 + V2 × IOUT × IC2 (3)

|S1off | = V2 × IOUT × IC2 (4)

|S1on| and |S1off| differentiate between various operating

scenarios. The quantities V1, V2, IIN and IOUT are directly
measured by voltage and current measurement devices,
respectively. The currents IC1 and IC2 are computed using
IC1 ¼ C1 × d(V1)/dt and IC2 ¼ C2 × d(V2)/dt.

6 Results
6.1 SIMULINK circuit

The buck converter circuit was set up in SIMULINK (Fig. 9)

to generate data for the fault cases in Table 1 and the no-fault
case. The circuit parameters are; V1 ¼ 15 V, V2 ¼ 7.5 V,
IIN ¼ 0.625 A, IOUT ¼ 1.25 A, duty cycle ¼ 0.5, switching
frequency ¼ 10 kHz, C1 ¼ 100 mF, C2 ¼ 13.6 mF made up
of two parallel connected capacitors (6.8 mF), L1 ¼ 1.2 mH
(two 0.6-mH inductors). Disconnecting one of the C2
Fig. 7 Buck converter circuit when the switch S1 is ON capacitors halves the net capacitance of the parallel
a Equivalent circuit in which case IS1 ¼ IL1 connection. This is used to simulate a degrading filter
b Modified directed graph
c Modified connection matrix
capacitor. On a similar basis, one of the series inductors can
be bypassed thereby halving the net inductance to simulate
an inductor failure.
The modified generalised connection matrices are shown in
Figs. 7c and 8c. The determinants of the matrices are 6.2 Hardware set-up
shown below
The buck converter hardware circuit shown in Fig. 10 was set
up to generate experimental data for the fault scenarios in
ON-state = 1 − V12 − IC1
2
+ IC1 × IIN × V1 − IC2
2
+ IC2 Table 1 as well as the no-fault case. The circuit parameters
and strategies to introduce faults were identical to the
× IS1
2
× IC1 + IC2 × IS1
2
× IIN × V1 − V22 SIMULINK model.
It is important to verify the circuit model with the hardware
+ V2 × IOUT × IC2 + V2 × IOUT × IS1
2
set-up to check for the model’s accuracy and reliability. The
× IC1 − V2 × IOUT × IS1
2
× IIN × V1 (1) comparison is shown (first two rows of Table 2) between
the input current and output voltage waveforms obtained
from the two circuits for the two switch failure modes,
inductor and capacitor failures.
OFF-state = 1 − V22 + V2 × IOUT × IC2 − IC2
2 The switch-fault is introduced after approximately three
switching cycles. The waveform at the bottom of the plot is
+ IOUT × IS2
2
× V2 + IS2
2
× IC2 (2) the input current, whereas the one nearer the top is the output
voltage. The horizontal axis in each plot of Table 2 represents
time, whereas the vertical axis represents the quantity
Following SCA convention of ignoring numbers and terms measured (either current or voltage). The measured signal is
with higher order parts, the final usable equations for the marked with an arrow and text indicating the particular quantity.

Fig. 8 Buck converter circuit when the switch S1 is OFF

a Equivalent circuit, where IS2 ¼ IL1
b Modified directed graph
c Modified generalised connection matrix

818 IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813 –826
& The Institution of Engineering and Technology 2012 doi: 10.1049/iet-pel.2011.0018
 www.ietdl.org

Fig. 9 Buck converter SIMULINK circuit

6.3 Data preparation

Fig. 10 Hardware test set-up for buck converter circuit
For both circuits, the data for fault and no-fault cases were
collected at 10 ns sampling rate over a 1-ms time period
(thus 100 000 samples). Using (3) and (4), the features
|S1off| and |S1on| are computed for the respective cases.
There are then 12 data sets, six for |S1off| (five fault
cases + no fault case) and six for |S1on|. Each set is
separately processed by the classification algorithm to yield
two results.
These data used in the classifier are first divided into ranges
and windows. The range variable reflects the total number of
samples considered by the classifier at one time and is set

Table 2 Comparison of waveforms generated by the model and hardware circuit with fault detection results on hardware data

Semiconductor switch (S1) open Semiconductor switch (S1) Inductor fault case: input current Capacitor fault case: input current
circuit case: input current and short circuit case: input current and output voltage and output voltage
output voltage and output voltage

SIMULINK circuit SIMULINK circuit SIMULINK circuit SIMULINK circuit

hardware circuit hardware circuit hardware circuit hardware circuit

semiconductor switch (S1) open
circuit case: output voltage with
fault indication
continuous fault indication
approximately 0.3 ms after fault
introduction
semiconductor switch (S1) short
circuit case: output voltage with
fault indication
fault indication approximately
0.4 ms after fault introduction
inductor fault case: output capacitor fault case: output voltage
voltage with fault indication with fault indication
fault indication approximately fault indication approximately
0.2 ms after fault introduction 0.17 ms after fault introduction

IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813–826 819

doi: 10.1049/iet-pel.2011.0018 & The Institution of Engineering and Technology 2012
www.ietdl.org
ideally in integral multiples of one switching cycle (i.e.
10 000 samples).
These ranges are separated and labelled as per the data
type. The window is the number of data points considered
within each range. The idea is to use a small window size
which then reflects the amount of samples needed per cycle
to classify the data. Thus, a small window size produces a
faster result. Further, the data are sorted in ascending order
within each window. The final data set for the six cases
consists of a number of rows (6 × range) and number of
columns (6 × window). An extra column is added at the
end of each row to assign its label. This file is saved in an
attribute relation file format (.arff) to be used in the Weka
classification software [62].
6.4 Heuristic classification results
The data produced were used with the classifier employing
the PART algorithm in the software package Weka. The
data were re-sampled at 100 ns, thus reducing the total
captured data samples by a factor of 10. Re-sampling eases
the computational effort and memory requirements of the
classifier. The algorithm uses a 10-fold cross validation
testing scheme to calculate error rates. The output is a set of
rules and a confusion matrix that shows the number of
correctly and incorrectly classified instances.
6.4.1 Results for the |S1off | equation: The processed
data had the following attributes after re-sampling:
Total samples = 10 000; range = 2000; window = 10
Total number of data sets
= 6 (1 no fault case + 5 fault cases)
With six data set used, the total range becomes
6 × 2000 ¼ 12 000. The confusion matrix with the rule set
is shown in Fig. 11. The 23 classification rules for the
hardware data are shown in Table 3.
6.4.2 Results for the |S1on | equation: The data
attributes are identical to the |S1off| case used previously.
The data are re-sampled in Weka in a similar manner. The
confusion matrix with the rule set is shown in Fig. 12. The
13 classification rules for the hardware data are shown in
Table 4. It is important to note that the SIMULINK circuit
consists of an ideal voltage source which exhibits zero
source impedance. This is unlike the case in the real
hardware circuit. The implication is that in the simulation,
dV1/dt ¼ 0 which means the input capacitor current IC1 ≃ 0.
Fig. 11 Confusion matrix using |S1off| equation for
a Hardware data
b SIMULINK data
820
& The Institution of Engineering and Technology 2012
6.5 Interpretation of results
The rules produced by the PART algorithm can be understood
using conditional execution statements as shown in Tables 3
and 4. The algorithm uses the absolute values of the data fed
to it (in this case the six data sets) to produce thresholds. The
heuristics are derived for these absolute values. The data
stream is input in windows of the specified length. The
rules are output with reference to the position of every
value within the window. Knowing that the data used were
divided into a window size of 10, then the terms ‘Value1’
or ‘Value9’ refer to the first and ninth elements,
respectively, in a given window.
The data sets used in this case were from a SIMULINK
model (Fig. 9) and a corresponding hardware circuit
(Fig. 10). The classifier was trained on these different sets
of data separately and then tested on the same respective
types. This demonstrated the relative lack of confusion and
the ability of the feature to discriminate between different
faults for the particular type of data presented. The
classification rates in Figs. 10 and 11 signify the percentage
of data samples correctly distinguished as being of a certain
type. Thus out of 12 000, the number of correctly classified
samples (as being of a certain type) is 11 997 and there are
only three samples which have led to ‘confusion’
(Fig. 11a). The high classification rate is a promising result
in this research and indicates the ability to discriminate
between the particular types of faults studied.
6.6 Application of results
The rules listed in Table 4 (|S1on| equation) were coded in
MATLAB to test the ability to detect the fault types. This
fault detection was done offline. However, investigation is
ongoing to use a similar approach for a real-time online
application. The results of the offline application are plotted
on the same graph as the output voltage waveforms (third
row of Table 2). This shows when the fault was introduced
and gives an idea of the time taken by the proposed method
to detect it. The plots show that the encoded heuristics are
able to indicate the presence of a fault for each case. The
data were collected for a total of 2 ms at a 10-ns sampling
rate (total 200 000 samples). As before, this is re-sampled at
100 ns (total 20 000 samples). The fault is introduced at
1 ms for each case.
To avoid false alarms, the frequency of the fault indications
was included over batches of data samples. This was
performed using additional code which counts the number
of fault indications every 5000 samples of the 100-ns
re-sampled data, that is, every 0.5 ms, and indicates a fault
only if more than ten events are counted. A slight
modification to this fault indicator counting scheme had to
IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813 –826
doi: 10.1049/iet-pel.2011.0018
 www.ietdl.org
Table 3 Rules derived using S1-off equation for classification of hardware data

Rules 1–5 Rules 6 –10 Rules 11– 15 Rules 16– 20 Rules 21 –23

IF Value 8 . 2500.26 AND IF Value 2 . 2349.08 AND IF Value 2 . 2341.57 IF Value 1 . 2349.08 ANDIF Value 8 ≤ 2 500.26 AND
Value 5 ≤ 2 350.48 AND Value 1 . 2341.57 AND THEN data is of type ‘d’ Value 8 ≤ 0 AND Value 4 . 2683.15 AND
Value 1 . 2698.16 AND Value 1 ≤ 2 224.59 Value 7 . 2334.53 AND Value 2 ≤ 2 806.82
Value 9 . 2358.19 AND THEN data is of type ‘c’ Value 1 ≤ 2224.59 AND THEN data is of type ‘f’
Value 8 ≤ 2 212.37 AND Value 3 ≤ 2341.57 AND
Value 4 . 2500.26 Value 4 ≤ 2218.48 AND
THEN data is of type ‘a’ Value 6 ≤ 2334.53
THEN data is of type ‘e’
IF Value 2 ≤ 2665.33 AND IF Value 3 . 2332.666 ANDIF Value 8 ≤ 2 212.37 AND IF Value 1 . 2349.08 ANDIF Value 5 ≤ 2 500.26 AND
Value 2 . 2727.5238 Value 3 ≤ 2218.4866 Value 2 ≤ 2 500.2624 Value 8 ≤ 0 AND Value 2 . 2619.93
THEN data is of type ‘a’ THEN data is of type ‘c’ THEN data is of type ‘e’ Value 7 . 2218.48 AND THEN data is of type ‘f’
Value 6 . 2218.48 AND
Value 1 ≤ 2224.59 AND
Value 3 ≤ 2341.57
THEN data is of type ‘e’
IF Value 1 ≤ 2 349.08 ANDIF Value 2 ≤ 2 698.16 AND IF Value 2 2 . 2349.08 ANDIF Value 8 ≤ 365.89 AND IF Value 1 ≤ 2 500.26
Value 1 . 2500.26 Value 9 ≤ 2212.37 Value 2 ≤ 2341.57 AND Value 4 ≤ 569.77 THEN data is of type ‘f’
THEN data is of type ‘a’ THEN data is of type ‘d’ Value 10 . 2341.57 AND THEN data is of type ‘e’
Value 1 . 2349.08 AND
Value 8 ≤ 2 334.53
THEN data is of type ‘e’
IF Value 8 ≤ 2500.26 AND IF Value 8 ≤ 2212.37 IF Value 1 . 2727.52 AND IF Value 7 ≤ 2 218.48 –
Value 6 ≤ 2 727.5238 THEN data is of type ‘d’ Value 2 . 2349.08 AND THEN data is of type ‘e’
THEN data is of type ‘b’ Value 2 ≤ 2218.48 AND
Value 1 ≤ 2500.26
THEN data is of type ‘e’
IF Value 2 ≤ 2500.26 AND IF Value 3 ≤ 2218.48 IF Value 1 . 2349.08 AND IF Value 8 ≤ 0 AND –
Value 1 ≤ 2619.93 THEN data is of type ‘d’ Value 8 ≤ 20 AND Value 7 . 2218.48 AND
THEN data is of type ‘b’ Value 3 ≤ 2341.57 AND Value 3 . 2218.48 AND
Value 10 . 2174.59 Value 2 . 2218.48
THEN data is of type ‘e’ THEN data is of type ‘e’

Fig. 12 Confusion matrix using |S1on| equation for

a Hardware data
b SIMULINK data

be used for the switch open circuit fault case. As the switch
being ‘open’ is a legitimate state of the circuit, the output
would show a fault indicator continuously.
Hence, to detect the introduction of this type of fault,
consecutive fault indications were counted per 0.5 ms worth
of data as opposed to the total number for other fault types
mentioned. This was done based on the notion that since
the switch open circuit would occur every cycle, only a
large enough consecutive count will suggest a permanent
switch open circuit failure. Therefore the added code was
modified to count 200 consecutive fault indications per
5000 data samples (i.e. worth 0.5 ms).
This frequency check was found to reduce the number of
false alarms while preserving the speed and reliability of
fault detection. A similar procedure could be used over a
larger or smaller batch size of data samples. Too large a
batch (over 8000) might not reduce false alarms
significantly, whereas too small a batch (below 4000) may
impose additional computational burden. The authors
preferred to use a batch size of 5000 samples as it
conveniently divides the pre-fault and post-fault parts of the
data into two sub-parts each.
7 Discussion
This research stems from the application of power electronic
converters within the zonal shipboard power distribution
architecture for US Navy warships and other tightly
coupled finite inertia systems. As mentioned before, the
power converter forms an integral part of these topologies

IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813–826 821

doi: 10.1049/iet-pel.2011.0018 & The Institution of Engineering and Technology 2012
www.ietdl.org
Table 4 Rules derived using S1on equation for classification of hardware data

Rules 1–3 Rules 4 –6 Rules 7– 9 Rule 10 –12 Rule 13

IF Value 3 ≤ 2 3473 AND IF Value 1 . 2942.24 IF Value 1 . 22605.36 IF Value 6 . 23563.6 IF Value 5 . 23630 AND
Value 9 ≤ 22001.3696 THEN data is of type ‘c’ AND AND Value 2 ≤ 2350.48
AND Value 7 ≤ 2 491.18 Value 2 . 21800 AND THEN data is of type ‘a’
Value 1 ≤ 24130.2624 THEN data is of type ‘e’ Value 2 ≤ 2499.73
THEN data is of type ‘a’ THEN data is of type ‘f’
IF Value 1 . 23580.4848 IF Value 1 ≤ 21766.7 AND IF Value 1 . 21766.7 IF Value 1 . 24223.15 –
AND Value 2 ≤ 2 1848.24 AND THEN data is of type ‘e’ AND
Value 2 ≤ 23050.2 Value 9 . 23473 Value 1 ≤ 23654.2 AND
THEN data is of type ‘a’ THEN data is of type ‘d’ Value 2 ≤ 23654.2 AND
Value 3 ≤ 23805.2
THEN data is of type ‘f’
IF Value 2 ≤ 2 4983 IF Value 3 ≤ 23998.16 IF Value 1 ≤ 2 4677.37 IF Value 2 ≤ 21536 AND –
THEN data is of type ‘b’ AND THEN data is of type ‘e’ Value 1 . 23998.16 AND
Value 9 . 23890.93 Value 8 . 23360 AND
THEN data is of type ‘d’ Value 1 ≤ 23654.2
THEN data is of type ‘f’

and the buck converter section was chosen by the authors for
analysis into automated fault diagnosis. The research is aimed
at providing high-level diagnostics to aid in decision support
at system and sub-system levels and focuses on component
level and incipient failures to provide a general framework
for fault identification. FMEA enables understanding of
pertinent component-level failures for the devices which in
turn informs the simulation studies to generate fault data.
Along with a detailed FMEA, modification of an SCA
method for electrical circuits is used to produce usable
features that are believed to aid in differentiating operating
scenarios.
7.1 Proposed diagnostic method compared to
existing research
In Section 2, a comprehensive literature review highlights
research in diagnostics for the related areas of this particular
research arena. As highlighted in the references, a major
research thread is system reconfiguration, restoration and
automatic mitigation of faults at the system level. Such
faults are typically ground faults or faults at the main
motor/generator/prime mover side. Research into the need
for autonomous high-level diagnostics providing decision
support assistance to the reduced numbers of on-board
crew, giving fault information and their risk mitigation for
component-level faults has been ignored. This gap in
research led the authors to conduct studies into component
level diagnostics for the dc – dc power electronic converter
since the proposed architectures are envisioned to include
a large number of power electronic sub-systems which as of
now is a relatively new and unproven technology for
warships.
The proposed approach beginning at FMEA, feeds
further research by providing information about pertinent
failures at all levels (FMEA can be conducted at system,
sub-system and device/component level), whereas the
modified SCA methodology provides diagnosable features
for faults for the shown converter type. Done together as
part of a systematic methodology as proposed, the FMEA
and modified-SCA approach can be extended to other
power electronic systems to provide high-end diagnosable
features. It could also potentially provide diagnosable
features for zone- and system-level faults, which forms part
of future research.
7.2 Rationale for using SCA
The need to understand pertinent failures in a novel system
without any prior benchmarking lead this research into
reliability analysis, in turn identifying FMEA as a valid
starting point. Further, SCA being a known reliability
analysis technique to diagnose design stage circuit faults
was studied to check its applicability for the novel
shipboard distribution architecture.
Thereafter, novel modification of conventional SCA
provided a means to conduct component-level fault
signature analysis using a high-level approach with basic
measurements such as input and output currents and
voltages. This novel methodology thus gives an analysis
technique stemming from well-known design-stage
reliability analysis which is in turn able to provide
diagnostic indicators. Further, as the explained SCA
methodology can be derived for other converter circuits, its
application to other types of power electronic converters is
potentially extendable.
7.3 Relevance and benefits of proposed approach
This research is directed at proposed naval shipboard power
systems which are envisioned to integrate the plug and play
PEBB devices, automated diagnostics and reconfiguration
systems among others. One method is that this integration
could be facilitated by multi-agent systems [63] that aim to
provide robustness and extensibility. As mentioned earlier,
the reduction in the numbers of onboard crew with increase
in automation put added importance on enhanced
communication systems with decision support besides the
obvious criticality of accurate fault diagnosis and
monitoring. The nature of such envisioned SPS architecture
puts emphasis on condition monitoring and diagnostics at
various system levels.
The diagnostic indicators explained in this paper arise from
the changes in voltage and current during the various
operating conditions (fault and no-fault). These measured
quantities change during various operating scenarios to
provide signatures that could be used as diagnostic
indicators for those respective cases using a similar rule-
based approach. SCA provides the means of understanding
circuit connectivity at a device/component level and also on
a sub-system/zonal level. The novelty proposed here by

822 IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813 –826
& The Institution of Engineering and Technology 2012 doi: 10.1049/iet-pel.2011.0018

modifying conventional SCA provides the potential for
single-signal diagnostics for individual inter-connected
devices. Further, the key to the technique lies in its
potential extendibility to more complex systems (a zone in
the case of notional shipboard systems followed by
interconnected zones), where the circuit connectivity
information coupled with a fault diagnostic indicator could
provide valuable additions for a crew’s decision support
which is an important application considering the heavy
reduction in crew numbers on future ships. Also, a positive
is that owing to the approach using one signal for
diagnostics per device (or per zone), the potential for
adding to the burden of the notional warship’s
communication network is minimal.
Ongoing research aims to investigate the novel modified
SCA methodology reported in this paper to generate single-
signal fault diagnostic indicators at various levels of the
system’s power distribution architecture. This paper reports
an application of the methodology at one such level, that is,
the device level (buck converter). Further research is
actively aimed at extending this methodology to higher
levels of the network wherein not only device-level
diagnostics is available but ideally ship-wide diagnostics
with resourceful decision support can be provided.
7.4 Fault introduction procedure in hardware
circuit and avoiding false alarms
A hardware setup was used to simulate specific faults and
failures that are known to occur in the semiconductor
devices (typically open-circuit failures which usually have a
pre-cursor of a rapid short-circuit time prior to bond wires
arcing in plastic packages). In the passive components the
authors simulated the effects of electrolyte leakage in
capacitors (an incipient fault) or rapid turn – turn failures in
inductor windings. These tests are realistic in terms of the
overall impact on the performance of the converter circuit.
The halving of net capacitance by parallel connected
capacitors (and halving of net inductance by series
connected inductors) is used to simulate respective fault
cases. Although the step changes are not representative of
practical failure modes, it provides an accelerated test
method in order to assess the suitability of the proposed
technique to detect and diagnose such faults. However, it is
acknowledged that the actual failure because of such
incipient faults is a slower process potentially occurring
over several hundred hours of operation. An alternative
method for simulation of a capacitor fault of this type could
be to employ differently aged capacitors in parallel, such
that the progressive blocking of individual capacitors at
designated instants in time would switch to the more ‘aged’
or worn-out capacitor with prior-estimated (or known)
changes in related parameters [64]. This method potentially
may provide more accurate capacitor fault data and is
anticipated to be applied in future research plans.
For the switch open and short circuit faults, the faults
are introduced when the switch is open and closed,
respectively. However, in a real system it is difficult to
predict the switch’s state when the passive component fails
because of electrolyte leakage or inductor windings fault.
In this case, however, as fault introduction is manual, it is
known that the faults for both the capacitor and inductor
have been introduced when the switch S1 is open (off state).
The counting scheme explained in Section 6.6 checks for
consistency in the data stream thus reducing the possibility
of a false diagnosis. Owing to the time scales of the data
IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813–826
doi: 10.1049/iet-pel.2011.0018
www.ietdl.org
recorded (in microseconds) and computing the time needed
to diagnose the data (,0.5 ms as shown in Table 2), the
counting schemed does not have any major detrimental
impact on the speed of diagnosis.
7.5 Observability condition and effective series
resistance
The experiments reported include four measurement signals,
namely the input current, input voltage and output current
and output voltage. All other internal currents and voltages
are computed using well-known circuit laws as explained
in Section 5. However, if quantities internal to a circuit
are not measurable satisfactorily by indirect methods, then
additional sensors may be needed to obtain these
measurements.
For low-voltage supplies, capacitor ESR can be the greatest
contributor to voltage ripple in comparison with the voltage
ripple across the capacitive element of the capacitor. In the
case studied in this paper, the voltage supply is high and
the relative contribution to voltage ripple from ESR is
small. In general, the technique is capable of including ESR
in the algorithm and derivation process. The main change is
in the modified-SCA that is performed, wherein ESR could
be considered as a resistor in series with the capacitor. This
added ‘component’ changes the determinant obtained from
the modified SCA method, although the analysis and
derivation technique to obtain the diagnostic feature is
fundamentally same as proposed.
7.6 Scalability issue of proposed method
The advantage of utilising data from local measurements such
as input/output measured currents and voltages as well as
known circuit parameters avoids the use of additional
sensors. Furthermore, the novel diagnosis method presented
makes use of this local data for each converter to produce
usable features from the determinant of the modified
generalised connection matrix for the respective device.
This is irrespective of the number of interconnected devices
as each converter will have its own matrix. Thus, for a
scaled up complex system with many power electronic
converters, the modified matrix would be constructed
separately for each device to provide localised diagnosis at
the component level for each converter. This concept
prevents the modified generalised connection matrix from
becoming too large to pose any issues relating to
computational burden.
7.7 Future research plans
In order to form a topology-independent approach, the
proposed methodology is to be applied to dc – dc converter
circuits such as the boost and buck – boost converters. The
verification could be similarly carried out using hardware
setups. The next step is to implement the methodology on a
real-time basis, for example, using field programmable gate
arrays [65]. Fig. 13 shows the basic setup to investigate
real-time diagnostics.
This research was conducted on a single isolated
buck converter circuit with fixed parameters. Applying
the proposed diagnosis technique in a grid-connected
environment is a matter of further investigation. This could
ideally be done by using the converter with loads (such as
motors) the parameters of which can be changed when
faults are introduced in the converter circuit. The feasibility
823
& The Institution of Engineering and Technology 2012
www.ietdl.org
Fig. 13 Real-time diagnostic setup following proposed modified
SCA-based heuristics technique
Fig. 14 System with loads to test feasibility of proposed dc –dc
converter diagnosis technique in a more complex set-up
of the presented technique will then be tested against issues
relating to more complex networks as shown in the line
diagram of Fig. 14.
An important part of further research plans is simulation of
fault scenarios using an interconnected system to mimic
the power-dense finite inertia shipboard architecture. As
mentioned, the research reported in this paper is from
experiments conducted on an isolated buck converter
circuit, whereas the real system would have interconnected
devices, loads as well as multiple power conversions. A
count-based scheme was proposed to prevent false alarms
(Section 6.6). This method obviously will need to be tested
along with the proposed diagnostic approach on a power-
dense system.
8 Conclusions
The method presented makes use of a model-based approach,
utilising local measurements without the need for extra
sensors to compute a signature. These quantities are used to
produce the usable feature derived from the determinant of
the generalised connection matrix from the directed graph
of the electrical circuit. The modification of using currents
and voltages for constructing the directed graph helps to
provide quantifiable numbers that aid in diagnosing various
component-level faults for the two types of converter
circuits examined. The proposed method tested on a
SIMULINK model was verified using hardware data which
showed that the signature distinguishes various single-fault
cases as well as a multiple fault case.
For SIMULINK model and hardware data, the results of
classification using a rule-based technique employing the
824
& The Institution of Engineering and Technology 2012
PART algorithm in Weka show that the |S1on| and |S1off|
equations could be utilised to discriminate between
identified pertinent failures. The threshold values to perform
the diagnosis (in Tables 3 and 4) are computed by the
PART algorithm for the particular operating parameters of
the buck converter circuit used. The authors believe the
marginal improvement in accuracy using the |S1on| equation
is due to the fact that it contains two terms as opposed
to the single term in the |S1off| equation. This extra
information provided to the classifier via the |S1on| equation
is believed to increase the rate of discrimination. However,
considering computational time and power needed for both
computations, the |S1off| equation needs half the efforts
compared to the |S1on| equation while providing a
negligibly lower classification rate.
Furthermore, there are fundamental differences between
the SIMULINK model and hardware circuit owing to the
lack of real-world parameters like line inductance, parasitic
capacitance and imperfect square wave pulse. But the
SIMULINK model used is within acceptable limits to
generate additional fault data for cases which would be
relatively unsafe to conduct on the hardware circuit, for
example, freewheeling diode and capacitor short-circuit
faults.
The proposed technique provides a potential for a fast-
acting fault diagnostic system. In order to avoid false
alarms, an additional piece of code employing a fault
indication frequency counter was utilised. In the presented
case, this code checked batches of the data every 0.5 ms
and indicated a fault only if more than 10 events occurred
every 0.5 ms. The off-line application of the heuristics, for
the switch failures produces permanent fault indications
approximately within 4500 samples after the fault is
introduced. With a 100-ns sampling rate that means the
fault is detected within 0.45 ms of its introduction. For
inductor and capacitor faults, the indication in both cases
occurs well before 2200 samples after the fault inception,
that is, within 0.22 ms of its introduction.
The proposed approach to generate heuristics for identified
pertinent failures could be evaluated with data from
sophisticated high-fidelity software models. One possible
method would be to employ converter models run on an
RTDS. Advanced models on the RTDS could better
simulate circuit behaviour in the presence of faults which
are relatively unsafe to conduct on hardware circuitry. The
data from such RTDS tests could be processed in the
manner presented in this paper to generate heuristics to
diagnose pertinent component level faults. This could also
positively aid the research into component-level diagnostics
for power electronic converters in more complex networks
and on a real-time basis.
The work reported in this paper used the classifier to train
and test the same type of data separately, that is, either from
the model or the hardware circuit. The next step is planned
to be the evaluation of the classifier by training it on
simulation data from a model and then testing it on data
from a hardware set-up. This evaluation will test the
classifier’s ability to generalise and form heuristics that
could be encoded for diagnosis purposes as explained
previously.
The extension of this research is aimed at conducting a
similar approach for the other types of dc – dc converters
namely the boost and buck – boost. This is with the view
of developing a topology-independent approach to detect
and diagnose pertinent component-level faults. Also,
investigation is ongoing for application of the proposed
IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813 –826
doi: 10.1049/iet-pel.2011.0018

method on a real-time basis for a buck converter hardware
circuit. In addition to component level fault diagnostics, the
applicability of the proposed method for sub-system (zone)
and system-wide faults (e.g. ground faults) is also an aim
for further study.
9 Acknowledgments
The authors thank the US Office of Naval Research for
funding this research. They also authors thank the support
of David Cartes, Karl Schoder and Sanjeev Srivastava of
the Centre for Advanced Power Systems at Florida State
University for their support.
10 References
1 Soman, R.R., Davidson, E.M., McArthur, S.D.J.: ‘Using functional
failure mode and effects analysis to design the monitoring and
diagnostics architecture for the zonal MVDC shipboard power
system’. IEEE Electric Ship Technologies Symp., (ESTS 2009),
20– 22 April 2009, pp. 123–128
2 Hegner, H., Desai, B.: ‘Integrated fight through power’. IEEE Power
Engineering Society Summer Meeting, July 2002, vol. 1, pp. 336 –339
3 Amy, J.V.: ‘Considerations in the design of naval electric power
systems’. IEEE Power Engineering Society Summer Meeting, 25–25
July 2002, vol. 1, pp. 331– 335
4 Mair, A.J., Soman, R.R., Davidson, E.M., et al.: ‘Intelligent distributed
control for shipboard power systems based on fault diagnosis and
condition monitoring’. Engine as a Weapon III, Portsmouth, UK,
23– 24 June 2009
5 Mikulak, R.J., McDermott, R., Beauregard, M.: ‘The basics of FMEA’
(CRC Press, 2nd edn.), Dec. 2008
6 Ericsen, T., Hingorani, N., Khersonsky, Y.: ‘Power electronics and
future marine electrical systems’, IEEE Trans. Ind. Appl., 2006, 42,
(1), pp. 155– 163
7 Logan, K.P.: ‘Intelligent diagnostic requirements of future all
electric ship integrated power systems’, IEEE Trans. Ind. Appl., 2007,
43, (1), pp. 139–149
8 RTDS Technologies: ‘Real-time digital simulator controls library
manual’ (2002)
9 Real Time Digital Simulator Tutorial Manual, RSCAD version,
September 2005
10 Rodriguez, J., Pontt, J., Alzarnora, G., Becker, N., Einenkel, O., Weinstein,
A.: ‘Novel 20-MW downhill conveyor system using three-
level converters’, IEEE Trans. Ind. Electron., 2002, 49, (5), pp. 1093–1100
11 Rodriguez, J., Bernet, S., Wu, B., Pontt, J.O., Kouro, S.:
‘Multilevel voltage-source-converter topologies for industrial medium-
voltage drives’, IEEE Trans. Ind. Electron., 2007, 54, (6),
pp. 2930– 2945
12 Cheng, Y., Qian, C., Crow, M.L., Pekarek, S., Atcitty, S.: ‘A comparison
of diode-clamped and cascaded multilevel converters for a STATCOM
with energy storage’, IEEE Trans. Ind. Electron., 2006, 53, (5),
pp. 1512– 1521
13 Alepuz, S., Busquets-Monge, S., Bordonau, J., Gago, J., Gonzalez, D.,
Balcells, J.: ‘Interfacing renewable energy sources to the utility grid
using a three-level inverter’, IEEE Trans. Ind. Electron., 2006, 53, (5),
pp. 1504– 1511
14 Veerachary, M.: ‘Analysis of fourth-order DC– DC converters: a flow
graph approach’, IEEE Trans. Ind. Electron., 2008, 55, (1), pp. 133 –141
15 Barrena, J.A., Marroyo, L., Vidal, M.A.R., Apraiz, J.R.T.: ‘Individual
voltage balancing strategy for PWM cascaded H-bridge converter-
based STATCOM’, IEEE Trans. Ind. Electron., 2008, 55, (1),
pp. 21–29
16 Baran, M.E., Mahajan, N.R.: ‘DC distribution for industrial systems:
opportunities and challenges’, IEEE Trans. Ind. Electroni, 2003, 39,
(6), pp. 1596– 1601
17 Ciezki, J.G., Ashton, R.W.: ‘Selection and stability issues associated
with a navy shipboard DC zonal electric distribution system’, IEEE
Trans. Power Deliv., 2000, 15, (2), pp. 665– 669
18 Momoh, J.A., Kaddah, S.S., Salawu, W.: ‘Security assessment of DC
zonal naval-ship power system’. Large Engineering System Conf. on
Power Engineering LESCOPE ’01, 2001, pp. 206– 212
19 Momoh, J.A., Ishola-Salawu, A.S.: ‘A new arcing fault modeling and
detection technique for navy IPS power system’. IEEE Power
Engineering Society General Meeting, 2006, p. 7
IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813–826
doi: 10.1049/iet-pel.2011.0018
www.ietdl.org
20 Butler-Purry, K.L.: ‘Multi-agent technology for self-healing shipboard
power systems’. Proc. 13th Int. Conf. on Intelligent Systems
Application to Power Systems, 6–10 November 2005, p. 5
21 Butler-Purry, K., Srivastava, S.K.: ‘Expert system-based reconfiguration
of shipboard power distribution systems’. 2008 IEEE Power and Energy
Society General Meeting – Conversion and Delivery of Electrical
Energy in the 21st Century, 20–24 July 2008, pp. 1 –5
22 Butler-Purry, K.L., Sarma, N.D.R.: ‘Self-healing reconfiguration for
restoration of naval shipboard power systems’, IEEE Trans. Power
Syst., 2004, 19, (2), pp. 754– 762
23 Baran, M.E., Mahajan, N.: ‘System reconfiguration on shipboard DC
zonal electrical system’. IEEE Electric Ship Technologies Symp.,
25– 27 July 2005, pp. 86– 92
24 Rodriguez, J., Lai, J.-S., Zheng Peng, F.: ‘Multilevel inverters: a survey
of topologies, controls, and applications’, IEEE Trans. Ind. Electron.,
2002, 49, (4), pp. 724–738
25 Sleszynski, W., Nieznanski, J., Cichowski, A.: ‘Open-transistor fault
diagnostics in voltage-source inverters by analyzing the load currents’,
IEEE Trans. Ind. Electron., 2009, 56, (11), pp. 4681– 4688
26 Kim, T.-J., Lee, W.-C., Hyun, D.-S.: ‘Detection method for open-circuit
fault in neutral-point-clamped inverter systems’, IEEE Trans. Ind.
Electron., 2009, 56, (7), pp. 2754–2763
27 Lezana, P., Aguilera, R., Rodriguez, J.: ‘Fault detection on multicell
converter based on output voltage frequency analysis’, IEEE Trans.
Ind. Electron., 2009, 56, (6), pp. 2275–2283
28 Young Kim, S., Nam, K., Song, H.-K., Kim, H.-G.: ‘Fault diagnosis of a
ZVS DC– DC converter based on DC-link current pulse shapes’, IEEE
Trans. Ind. Electron., 2008, 55, (3), pp. 1491–1494
29 Zidani, F., Diallo, D., Benbouzid El Hachemi, M., Nait-Said, R.: ‘A
fuzzy-based approach for the diagnosis of fault modes in a voltage-fed
PWM inverter induction motor drive’, IEEE Tran. Ind. Electron.,
2008, 55, (2), pp. 586–593
30 Khomfoi, S., Tolbert, L.M.: ‘Fault diagnosis and reconfiguration for
multilevel inverter drive using AI-based techniques’, IEEE Trans. Ind.
Electron., 2007, 54, (6), pp. 2954–2968
31 Pan, Y., Silveira, P.M., Steurer, M., Baldwin, T.L., Ribeiro, P.F.: ‘A fault
location approach for high-impedance grounded DC shipboard power
distribution systems’. IEEE Power and Energy Society General
Meeting – Conversion and Delivery of Electrical Energy in the 21st
Century, 20–24 July 2008, pp. 1 –6
32 Charfi, F., Lesecq, S., Sellami, F.: ‘Fault diagnosis using SWT and
Neyman Pearson detection tests’. IEEE Int. Symp. on Diagnostics for
Electric Machines, Power Electronics and Drives, SDEMPED 2009,
31 August, 6–3 September 2009, pp. 1– 6
33 Tsoumas, I.P., Safacas, A.N.: ‘Investigation of a novel approach for fault
diagnosis in power electronic converters: the case of the subsynchronous
cascade drive’. IEEE Int. Symp. on Diagnostics for Electric Machines,
Power Electronics and Drives, 2007, SDEMPED 2007, 6– 8
September 2007, pp. 58–63
34 Wang, F., Lai, R., Yuan, X., Luo, F., Burgos, R., Boroyevich, D.:
‘Fault detection and protection of three-level neutral-point-
clamped PWM voltage source converters’. IEEE Industry
Applications Society Annual Meeting, (IAS ’08), 5 –9 October 2008,
pp. 1– 7
35 Wang, F., Lai, R., Yuan, X., Luo, F., Burgos, R., Boroyevich, D.:
‘Failure-mode analysis and protection of three-level neutral-point-
clamped PWM voltage source converters’, IEEE Trans. Ind. Appl.,
2010, 46, (2), pp. 866–874
36 Bose, B.: ‘Power electronics – an emerging technology’, IEEE Trans.
Ind. Electron., 1989, 36, (3), pp. 403–412
37 Rothenhagen, K., Fuchs, F.W.: ‘Performance of diagnosis methods for
IGBT open circuit faults in three phase voltage source inverters for
AC variable speed drives’. European Conf. on Power Electronics and
Applications, 2005, p. 10
38 Lu, B., Sharma, S.: ‘A literature review of IGBT fault diagnostic
and protection methods for power inverters’. IEEE Industry
Applications Society Annual Meeting, (IAS ’08), 5 –9 October 2008,
pp. 1– 8
39 Chen, Y.-M., Wu, H.-C., Chou, M.-W., Lee, K.-Y.: ‘Online failure
prediction of the electrolytic capacitor for LC filter of switching-mode
power converters’, IEEE Trans. Ind. Electron., 2008, 55, (1),
pp. 400–406
40 Imam, A.M., Divan, D.M., Harley, R.G., Habetler, T.G.: ‘Real-time
condition monitoring of the electrolytic capacitors for power
electronics applications’. 22nd Annual IEEE Applied Power
Electronics Conf. (APEC 2007), 25 February–1 March 2007,
pp. 1057– 1061
41 Amaral, A.M.R., Cardoso, A.J.M.: ‘Use of ESR to predict failure of
output filtering capacitors in boost converters’. IEEE Int. Symp. on
Industrial Electronics, 4 –7 May 2004, pp. 1309– 1314
825
& The Institution of Engineering and Technology 2012
www.ietdl.org
42 Amaral, A.M.R., Cardoso, A.J.M.: ‘A simple offline technique for
evaluating the condition of aluminum– electrolytic–capacitors’, IEEE
Trans. Ind. Electron., 2009, 56, (8), pp. 3230–3237
43 Fenton, W.G., McGinnity, T.M., Maguire, L.P.: ‘Fault diagnosis of
electronic systems using intelligent techniques: a review’, IEEE Trans.
Syst. Man Cybern. C, Appl. Rev., 2001, 31, (3), pp. 269–281
44 Murphey, Y.L., Masrur, M.A., Chen, Z.H., Zhang, B.: ‘Model-based
fault diagnosis in electric drives using machine learning’, IEEE/ASME
Trans. Mechatronics, 2006, 11, (3), pp. 290–303
45 Liang-Wei, H., Yen, G.G.: ‘Reconfigurable control system design for
fault diagnosis and accommodation’. IEEE Proc. 40th Conf. on
Decision and Control, FL, December 2001
46 Ho, L.-W., Yen, G.G.: ‘Online multiple-model-based fault diagnosis
and accommodation’, IEEE Trans. Ind. Electron., 2003, 50, (2),
pp. 296–312
47 Maybeck, P., Stevens, R.: ‘Reconfigurable flight control via multiple
model adaptive control methods’, IEEE Trans. Aerosp. Electron. Syst.,
1991, 27, pp. 470–480
48 Zhang, Y., Li, X.: ‘Detection and diagnosis of sensor and actuator
failures using IMM estimator’, IEEE Trans. Aerosp. Electron. Syst.,
1998, 34, pp. 1293– 1313
49 Zhang, Y., Jiang, J.: ‘An interacting multiple-model based fault
detection, diagnosis and fault-tolerant control approach’. IEEE Proc.
38th Conf. Decision and Control, 1999, pp. 3593– 3598
50 Laparo, K., Buchner, M., Vasudeva, K.: ‘Leak detection in an
experimental heat exchanger process: a multiple model approach’,
IEEE Trans. Autom. Control, 1991, 36, pp. 167–177
51 Dussault, H.B.: ‘Automated FMEA status and future’. Annual Proc.
Reliability and Maintainability Symp., 1984, 24–26 January 1984,
pp. 1– 5
52 Herrin, S.A.: ‘Maintainability applications using the matrix FMEA
technique’, IEEE Trans. Reliab., 1981, R-30, (2), pp. 212–217
53 Legg, J.M.: ‘Computerized approach for matrix form FMEA’, IEEE
Trans. Reliab., 1978, R-27, (1), pp. 254– 257
826
& The Institution of Engineering and Technology 2012
54 Goddard, P.L.: ‘Software FMEA techniques’. Annual Proc. Reliability
and Maintainability Symp., 24–27 January 2000, pp. 118– 123
55 de Kleer, J.: ‘How circuits work’, Artif. Intell., 1984, 24, (1– 3),
pp. 205–280
56 Cao, Y., Wu, J.: ‘Dynamics of projective adaptive resonance theory
model: the foundation of PART algorithm’, IEEE Trans. Neural
Netw., 2004, 15, (2), pp. 245–260
57 ‘Weka 3: Data Mining Software in Java’, available at http://www.cs.
waikato.ac.nz/ml/weka/
58 Walker, F.E.: ‘Sneak circuit analysis automation’. Annual Proc.
Reliability and Maintainability Symp., 24–26 January 1989, pp. 502–506
59 Savakoor, D.S., Bowles, J.B., Bonnell, R.D.: ‘Combining sneak circuit
analysis and failure modes and effects analysis’. Annual Proc.
Reliability and Maintainability Symp., 26–28 January 1993,
pp. 199–205
60 Qu, L., Zhang, B., Qiu, D., Tu, W.: ‘Sneak circuit analysis method based
on generalized connection matrix for power converters’. Int. Conf.
Electrical Machines and Systems, (ICEMS 2008), 17– 20 October
2008, pp. 1587–1590
61 Qiu, D., Zhang, B.: ‘Discovery of sneak circuit phenomena in resonant
switched capacitor DC-DC converters’. IEEE Conf. Industrial
Electronics and Applications, 1ST, 24–26 May 2006, pp. 1– 4
62 ‘Attribute relation file format’. http://www.cs.waikato.ac.nz/~ml/weka/
arff.html
63 Davidson, E.M., McArthur, S.D.J., Srivastava, S.K., Cartes, D.A.:
‘Development of an integrated control and monitoring architecture for
shipboard power systems’. All Electric Ship (AES) 2007 Conf.,
IMarEST
64 Venet, P., Perisse, F., Husseini, M.H.E., Rojat, G.: ‘Realization of a
smart electrolytic capacitor circuit’, IEEE Ind. Appl. Mag., 2002, 8,
(1), pp. 16–20
65 Karimi, S., Gaillard, A., Poure, P., Saadate, S.: ‘FPGA-based real-time
power converter failure diagnosis for wind energy conversion
systems’, IEEE Trans. Ind. Electron., 2008, 55, (12), pp. 4299– 4308
IET Power Electron., 2012, Vol. 5, Iss. 6, pp. 813 –826
doi: 10.1049/iet-pel.2011.0018