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3 Laboratory Steps
In Lab 4, and also in the prelab for this lab, you tested your design in the
manner that most digital design engineers test their initial designs — in
simulation. To recap, you exercised your state machine with a sequence
of values for the inputs (X[0] and X[1]) at appropriate times relative to
a clock signal, and with a reset signal that started active (bringing the
machine to a known state), and then remained inactive for the duration of
the simulation.
By testing every possible transition from each state, you were able to verify
that the state machine behaved correctly, because you also had a “solution”
vector with the correct outputs. Both the input and solution vectors were
provided to shorten the process for you, but you could have figured them
out. Here is how you would do that. Since there are three states, and
each could have any of four possible input combinations applied to them
(00, 01, 10, and 11), there are only 12 (3 times 4) vectors needed, assuming
you do not need additional vectors for the sole purpose of getting to a
particular test state. (A simulation that tests all 12 possibilities in this case
would be said to provide 100% coverage.)
Although simulation makes the design process more efficient by finding
most errors prior to implementation, it can sometimes produce the wrong
answer, particularly if the software models of the actual target hardware
are inaccurate. So testing is never complete until the real hardware — the
device under test (DUT), the circuit under test (CUT), or unit under test
(UUT) — is exercised. That is what you will be doing in this lab.
SIM SM_VHDL
RESET_SIM RESETN RESETN
Q
CLK_IN CLOCK CLOCK
Z
Q X X
Z P/F
Figure 5.7. The ATE configuration for this lab is a VHDL device called SIM that
generates the same vectors used earlier in simulation and compares the state machines
Q and Z values against correct ones.
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Hardware is generally tested either manually (verifying that output
signals change as expected) or with automatic test equipment (ATE). Such
equipment will drive all of the input pins with test signals (a “stimulus,”
like the test vectors you have used), and automatically compare the output
pins against expected values (a “response monitor”). The combination of
the stimulus generator, the UUT, and the response monitor is called a
testbench. The automatic test equipment used in this lab is another VHDL
device, predesigned and given to you, that will be programmed into the
Cyclone chip alongside your state machine, as shown in Figure 5.7. In
other words, one device in the FPGA is going to test another device in the
FPGA— your state machine.
The SIM module in Figure 5.7 drives the RESETN, CLOCK, and X inputs
to the circuit designed during the prelab, SM_VHDL.VHD. It can just
as easily be used to test the functionally identical device from Lab 4,
SM_SCHEMATIC.BDF. The outputs of the UUT are then checked by the
SIM module to determine if the state machine has been implemented
correctly. So, the SIM module is functioning as both the stimulus generator
and the response monitor. It also has some extra capability to display
debugging information on the VGA output of the DE2 board, as well as
simple pass/fail LED indicators.
Once the ATE steps of the lab are completed, you will also learn how to
manually verify the state machine operation with a logic analyzer. But
since the state machine still needs to be stimulated for the logic analyzer to
see any outputs change, we will make use of the SIM module once again.
Test engineers will generally use some sort of signal generator (or pattern
generator) for this purpose, so think of SIM as your pattern generator when
you get to that step.
1. Place all of your files into a working directory in the lab computer.
From the class web site, download the file named SM_TESTER.zip
and unpack it to the same directory (do not create a subdirectory).
2. Also from the web site, download the file VECTORS.MIF that is
unique for your section, placing it in the same directory. This
is the same information as the VECTORxxxSOLUTION.TBL
file contained last week, but in a form that can be stored in the
Cyclone chip and accessed by SIM for pattern generation.
the top-level design file in the new project. Note that it includes
a symbol for SM_VHDL. Since your SM_VHDL.VHD is the only
appropriate “SM_VHDL” source file in the directory, it will be
compiled as part of the project. Note also that SIM is reset by
KEY0, and started by KEY1. When first loaded to the board,
SIM starts in the reset state even without pushing the KEY0 reset
button.
chip.) You can also verify that the pins listed in Table
5.1 were assigned, in order to bring signals out to the
JP2 (GPIO1) header. Pin and location assignments may
not be visible in a schematic until after a compilation.
Also note that SIM drives the LEDs with its PASS and FAIL
signals. You may be able to figure out how the PASS and FAIL
signals drive different LEDs, but it will be clear soon enough,
anyway.
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button to reset the circuit. At this point, both the SIM device
and your SM_VHDL device are in the Cyclone chip, and SIM is
waiting to be started. Note that none of the red or green LEDs are
illuminated (but the blue power LED should be lit).
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10. Save and compile the project (generating a new SM_TESTER.SOF
in the process).
11. Repeat steps 5-7 for this SCHEMATIC version, instead of the
VHDL version. (Download, get the pass response, and get a
checkoff.) ()
What have you just done? Does it make sense? In the past
two labs, you’ve implemented the same state machine in
Note!
12. If you have not watched and understood the logic analyzer
tutorial video from the class web site, look at it now (more than
once, if necessary). In the lab, there are two different versions of
the logic analyzer. The newer ones have larger screens, but either
Figure 5.8a. TLA5201B logic analyzer connections. Top left: Two probe pods plugged
into a logic analyzer (the C2/C3 pod on the left and the A2/A3 pod on the right). Top
right: The individual probes break out in two groups on each pod (A2 and A3, here).
Bottom: Each group separates eventually to a ground and eight color-coded signals.
The second group and a separate clock probe are not shown.
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Figure 5.8b. TLA6401 logic analyzer connections. Left: One probe pod plugged into
a logic analyzer (the A2/A3 pod). Middle: The individual probes break out in two
groups on each pod (A2 and A3, here). Bottom: Each group separates eventually to a
ground and eight color-coded signals. The second group and a separate clock probe
are not shown.
version will work fine for this lab. Turn on the logic analyzer and
prepare to attach the A2 connector’s probes as will be described
below. Use the KVM switch (Keyboard/Video/Mouse switch)
to switch the video display to show the logic analyzer while also
connecting the keyboard and mouse for ease of data entry.
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Figure 5.9. Connection of the logic analyzer to the DE2 board showing the TLA5201B
probes (left) and the TLA6401 probes (right). Specific choices (i.e., colors) are arbitrary,
but must be recorded. These specific locations are important, because SM_TESTER.
BDF directs state machine input and output signals to particular pins on expansion
header JP2.
14. Connect all remaining signals in Table 5.1 using any seven of the
eight signal probes on the A2 pod, but keep track of which color
is on the probe connected to each signal. You can record these
colors in the blank column of Table 5.1 for now. This information
will be needed later. Notice that the JP2 expansion header pins
correspond to different pins on the two types of Cyclone II devices
(EP2C35 or EP2C70). In either case, however, the result is that a
particular signal will end up on the same JP2 pin, with either a
DE2 board or a DE2-70 board.
If you need to leave the lab at any point during the steps
that follow, you can save your entire logic analyzer
setup to a USB stick. You will have to reconnect the
Hint!
Lab 5 109
Figure 5.11. The first step of the setup informs the analyzer that the circuit has a two-
bit vector, or group, named X and connected to specific probes, which will vary based
on your selection of colored probes for each signal. The top image (a) shows the setup
window of the TLA5201B, and the bottom image (b) shows the setup window of the
TLA6401.
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and clicking on the Delete Group option.
b. Add a group for the two-bit signal X by simply typing X
under the Group Name heading in the first blank row (for the
TLA5201B) or in the first field below Groups (for the TLA6401).
c. While the X group is still active (highlighted with a box around
it), add the X[1] and X[0] signals to the X group either
• (for the TLA5201B) by clicking on the grey box under the
corresponding color band codes (from Lab step 14) in the
A2 probe’s row, or
• (for the TLA6401) by dragging the channels from the probe
area of the screen that represent the colors you chose (from
Lab step 14) to the region below the group name you just
created.
The TLA5101B will build the group in the order you pick
signals, so be sure to select the most significant bit first. In this
case, it will be the X[1] signal. This will result in something
similar to Figure 5.11, but you may have chosen different
probes (different color bands).
The TLA6401 will allow you to drag the signals between the
MSB and LSB, so that you can reorder them if necessary.
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Figure 5.12. After setting up both groups and the three individual signals, your setup
window should resemble the top figure (a) on the TLA5201B, or the bottom figure
(b) on the TLA6401. But in either case, it is likely that you made different choices of
probes.
At this point, every used probe now has a name that is relevant
to your circuit. (Specifically, seven of the eight color-coded
signals should have either a name in the A2 row, or they
should have the grey box selected. The eighth signal and the
clock will remain unused.) See Figure 5.12a or 5.12b.
f. Set the logic analyzer is to use its own internal clock:
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Figure 5.13. The Probe Properties window allows the user to specify voltage threshold levels,
which should be TTL-compatible for this circuit.
g. The logic analyzer must be set for the proper logic thresholds,
since it cannot represent 0 and 1 correctly unless you define
logic levels.
• (for the TLA5201B) Click on the Probes drop-down menu
near the top left and select the Thresholds tab. As shown
in Figure 5.13, pick a threshold of 1.5 V for the TTL-
compatible signals of the FPGA. You can set the threshold
for every probe at 1.5 V by using Set All, or just set the
thresholds for probe A2.
• (for the TLA6401) Set the Global Threshold to 1.5 V. See
Figure 5.12b.
• (for the TLA5201B) Note the Activity tab that is also a part
of the Probe Properties window. Select it, and you can see
the current logic level of each probe input. Close the Probe
Properties window before continuing.
• (for the TLA6401) The symbol that looks like a circle in
each channel grid location is actually a zero, showing a low
logic level. It will change to a 1 if that signal goes high, or
to a combined 0/1 signal when rapidly changing. (With the
state machine just downloaded, you will see only zeros.)
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b. We would like to see what happens during and immediately
after a reset, which occurs when the RESETN signal goes
high. So pick Trigger on channel transition (edge), and note
on the lower half of the screen that you can select both a
channel and an edge direction. Channels are given by their
probe number (which you could provide, of course). But since
you have assigned meaningful names, it is easier to use the
Select Channel button to select RESETN by name, rather than
by probe number, as shown in Figure 5.14. Make sure that
you choose a trigger condition of a rising edge for RESETN
(“Channel RESETN Goes High” is the exact wording of the
desired trigger condition).
c. At this point, the analyzer is ready to enter the “Run” mode,
at which time it will continuously store data until the trigger
condition is met, then stop as soon as the required amount of
data is collected for display and analysis by you, the user.
18. Logic Analyzer Capture
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The reason that our data occupies such a small region
Question...
or the timescale (i.e., the reason that we had to zoom in)
goes back to the step where we chose 128K samples, at a
10 µsec sampling rate. Is there something we could have
done differently, knowing what we do about how fast the
state machine is clocked and how many clock cycles are
needed for all of the test vectors to run?
Lab 5 117
Figure 5.16. After changing the state (Q) radix from binary to symbolic, as defined
by symbols in STATELABELDEFS.TSF, the waveform should be very similar to a
simulated waveform with the A, B, C state names.
20. Press the reset button and make sure that the state machine goes
to state A (00). Try all four switch combinations for the X inputs,
one at a time (resetting the state machine between each test).
When you press the clock pushbutton, you should see the correct
state transition on the LEDs. Show this for a checkoff. ()
21. You do not have to test the remaining state transitions (the ones
from state B and the ones from state C), as long as you at least
verify that all of the transitions from state A work correctly.
(Realize, of course, that had this been a real job, you should find a
way to test them all!)
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22. Retain as results the following items:
• the SM_VHDL.VHD file (from prelab step 6, fixed if necessary
in lab step 7, and formatted as required)
• the SM_VHDL.VWF file (from prelab step 16, reopened and
saved as a screen grab, properly formatted)
• schematic after replacement of SM_VHDL with
SM_SCHEMATIC, adding title block and properly formatted
(from lab step 9)
• TWO logic analyzer screen grabs (from lab step 18h and 18i)
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