DFT for fragmented digital blocks in mixed signal designs

Richard Illman

Dialog Semiconductor
Edinburgh, UK

www.diasemi.com

ABSTRACT

Increasingly mixed signal designs have small digital blocks embedded within the analogue func-
tions as well as a main digital core. This paper describes a scan compression architecture to
minimise the impact and risks associated with this design style. It also describes the techniques
used to ensure the accuracy of test coverage reporting in these types of designs.
 Table of Contents
1. Introduction ........................................................................................................................... 4
2. Target Design ........................................................................................................................ 4
3. DFT architecture ................................................................................................................... 5
4. Design Flow .......................................................................................................................... 6
COMPRESSION/SCAN SYNTHESIS .................................................................................................. 6
ATPG ........................................................................................................................................... 7
PATTERN VERIFICATION ............................................................................................................... 9
ATE PATTERN DEBUG .................................................................................................................. 9
DEBUG AND TOLERANCE OF SCAN CHAIN TIMING ERRORS .......................................................... 10
5. Test Coverage Reporting .................................................................................................... 11
REMOVAL OF NON-DIGITAL PINS FOR ATPG ............................................................................. 12
USE OF EMPTY BOXES ................................................................................................................ 12
USE OF “PORTFAULT” BOXES ..................................................................................................... 14
USE OF GREY BOXES .................................................................................................................. 14
USE OF “ADD_NOFAULTS” AND “ADD_EQUIVALENT_NOFAULTS” COMMANDS ........................... 15
INPUT ONLY ANALOGUE MODELS ................................................................................................ 16
POWER ON RESET BLOCKS........................................................................................................... 17
VERIFYING CORRECT MODELLING ............................................................................................. 17
DESIGN FLOW RECOMMENDATIONS ........................................................................................... 18
COVERAGE RESULTS .................................................................................................................. 19
DO THE UNTESTABLE FAULTS MATTER? .................................................................................... 19
IMPACT ON RUN TIMES AND MEMORY UTILISATION .................................................................... 20
6. Conclusions ......................................................................................................................... 20
7. References ........................................................................................................................... 20

Table of Figures
Figure 1 Chip architecture and scan chains ............................................................................... 6
Figure 2 Comparative ATPG runs............................................................................................. 8
Figure 3 Verilog empty module .............................................................................................. 13
Figure 4 TetraMAX set_build -black_box .............................................................................. 13
Figure 5 UU/UO fault propagation through the design ........................................................... 14
Figure 6 Oscillator Module View ............................................................................................ 15
Figure 7 Oscillator Internal Logic ........................................................................................... 15
Figure 8 Propagation of equivalent nofaults ........................................................................... 16
Figure 9 Reference Voltage Generator .................................................................................... 17

SNUG 2012 2 DFT for fragmented digital blocks

 Table of Tables
Table 1 Initial Tester Yield Losses ................................................................................................. 9
Table 2 Fault Classifications ......................................................................................................... 19
Table 3 Impact of no unused gate deletion ................................................................................... 20

SNUG 2012 3 DFT for fragmented digital blocks

1. Introduction

Based on a recent design project, this paper describes the use of scan compression to provide a
DFT architecture which is robust to potential design problems and also improves diagnosability
and yield tracking. Techniques to ensure accurate test coverage for this design style are also de-
scribed.

2. Target Design

This design is a combined power management and audio chip. It contains several digital blocks:

A power management (PM) digital block with around 4000 scan flops.

Audio block A (ABA) with around 300 scan flops

Audio block B (ABB) with around 60 scan flops

A low frequency digital block (LFD) with around 150 scan flops

There are also analogue blocks such as LDO and BUCK power supplies and a charge pump.

The chip is implemented in 0.25 micron technology and the full digital design is less than 100K
gates.

It was a key DFT requirement that the scan architecture should still be usable even if one of the
smaller blocks was non-functional or only partially working. The smaller blocks were seen as a
potential risk because:

The LFD is only designed to operate at <100 KHz; it might not support a high shift fre-
quency. It also uses a switched power supply which might not work in scan mode.

The ABB is partially implemented as a custom layout of digital cells within an analogue
block; outside the normal digital P&R flow.

The top level interconnect between the blocks, including level shifters, is done within the
analogue design environment and STA and SDF extraction were not available.

There is also a requirement to be able to track the yield of the different blocks passed on a simple
pass/fail criteria of sets of scan vectors, without the use of detailed failure logs and analysis. Past
experience has shown that yield problems can be associated with these types of small blocks.

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3. DFT architecture

The design has limited digital pins available so only 4 scan chains can be used. This would not
allow a fixed configuration with separate chains to be used for the different blocks without ex-
tremely unbalanced and inefficient scan chains. It would be possible to have a reconfigurable
architecture that allowed each block to be accessed individually. However, it was felt that the use
of an X-tolerant compression architecture was the simplest way to meet all the requirements and
would also reduce test time. In addition, if compression was not used, the 4 scan chains would
have a length of around 1,100 bits. There would be a risk that even if test time was acceptable
the test data size could exceed the limit of a few million cycles imposed by the type of produc-
tion testers used for high volume, low cost, consumer devices.

There is an area overhead of around 1% of the digital logic for implementing the compression
logic. However, typically the digital logic is less than 25% of the overall chip area and there is
some “slack” in the layout to implement the extra logic with no increase in die area, only addi-
tional run-time during layout. The DFTMAX Compression options allow the compression to be
downgraded to a lower ratio/area or even remove with very simple changes to the synthesis
script. So changes can be made very late in the design flow if the area does become an issue.

The chosen architecture was 4 external scan chains and a compression ratio of 8 (32 scan chains
within the compressor). The 32 compressor chains were allocated to the sub-blocks:

PM - 27 scan chains ~ 140 bits long

LFD - 2 scan chains ~ 70 bits long
ABA - 2 scan chains ~ 150 bits long
ABB - 1 scan chain ~ 60 bits long

The overall chip architecture is illustrated in the diagram below. The 32 internal compressed
scan chains are shown in red, the 4 external scan chains are shown in green.

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 Figure 1 Chip architecture and scan chains

4. Design Flow

Compression/Scan Synthesis

Synthesis did not use the classic hierarchical scan insertion flow using CTL models for the
smaller blocks because they were not hierarchically below the main PM block.

Scan chains were inserted into the smaller blocks using either standard scan synthesis (for the
ABA block) or a combination of scan synthesis and manual stitching of custom digital blocks.

When synthesising using DFTMAX (version F-2011.09 was used) the PM digital block the ex-
ternal scan chains were specified with set_scan_group:

set_scan_group name \
-segment_length length \
-serial_routed true \
-access [list ScanDataIn pin ScanDataOut pin] \

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 -clock clock -edge rising|falling

The set_scan_path command is used to control placement of the segments into the overall
scan chains.

When inserting the scan chains, “false lengths” were specified for the Audio, LFD and ABB scan
chains. For example, the LFD and ABB scan chains are both specified as having a “seg-
ment_length” of 150 bits, even though they are physically only 60 or 70 bits. This stops DFT-
MAX trying to balance the overall scan chains lengths, which would have created compressed
mode scan chains which crossed between blocks. The use if “false lengths” does not cause any
issues during synthesis because these are describing “grey boxes” which are outside the scope of
the synthesis. The expected scan lengths reported during synthesis will be incorrect. However,
the compressor description is still valid, so DRC checking later in the flow will extract, use and
report the correct physical scan chain lengths and the rest of the flow will work as normal.

ATPG

As stated earlier, it was important that it should be possible to scan test the chip even if one of
the small blocks did not function correctly. It should also be possible to track the yield of the
individual blocks.

To do this we generated patterns on an incremental basis, first for just the PM block. Then for the
PM block plus one other block and finally for the complete design.

1. PM only
2. PM + ABA
3. PM + ABB
4. PM + LFD
5. All blocks

The intention was that the test should work even if one of the “excluded” blocks was completely
non-functional, including the scan chains.

Unfortunately it is not possible to simply black-box the “excluded” module during model build
and subsequent DRC checking. The DRC will fail during the scan and compressor checks. In-
stead, the blocks are “excluded” by placing XX cell constraints are on the scan chains in the “ex-
cluded” blocks during DRC

add_cell_constraints XX chain_name –all

In the case of compression the “chain_name” will simply be the integer in the normal scan cell
report.

ATPG is run incrementally, always using the same SPF file with the compressed scan chain de-
scription, but returning to DRC mode to remove/add cell constraints as required.

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All the faults are added at the start of the ATPG process. The following TetraMAX command is
used to create a persistent fault model which retains fault classification when switching between
DRC and TEST modes.

set_faults -persistent_fault_models

The faults at the boundaries between two blocks will be untestable until a run when both blocks
are “included”. The final ATPG run with all blocks “included” will ensure no loss of test cover-
age compared with a conventional ATPG approach. No special isolation between blocks is re-
quired or implemented.

This approach to generating patterns increases ATPG run times and pattern counts but has the
benefits described earlier.

Figure 2 Comparative ATPG runs

The “Single Run” shows the coverage curve if conventional ATPG is run across all blocks with
no cell constraints. The red “Individual Runs” shows the effect of running the ATPG on each
block individually. The pattern count more than doubles because of the blocks are tested serially
rather than in parallel and X-masking for the chains in the “excluded” blocks results in more pat-
terns.

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The number of extra patterns could be reduced by including a bypass for the chains in the “ex-
cluded” blocks. This would reduce the number of X-states propagating to the compressor and the
number of masking bits needed. This bypass logic would need to be included within the main
PM block to maintain the “failure tolerance” and needs to be configurable.

The green “Pattern Limit” curve shows the effect of limiting the number of patterns allowed per-
block before switching to a single run to cover the remaining faults across all blocks in a single
run. This dramatically decreases the pattern count. In practice there is a variable trade-off be-
tween diagnostic/yield resolution and pattern count.

Note – the figures shown are not the final test coverage, only those in scan compression mode. A
small additional ATPG run in normal scan mode gives <1% additional coverage, mainly in the
codec and some faults affected by the compressor/decompressor dependencies (reported as R
Rule violations during DRC checking). The “scan untestable” logic at the analogue digital
boundary will be covered by the analogue tests.

Pattern Verification

This incremental ATPG flow and the correct “exclusion” of the various blocks should be verified
in simulation. It is possible to black box some models during simulation. However, the standard
parallel and serial simulation testbenches produced by the “stil2verilog” utility will not compile
correctly because they include references to all the scan elements identified. Instead a serial only
testbench must be used:

stil2verilog pattern_file tbench_file –ser_only

Because full serial simulation can be fairly slow, just a subset of patterns could be used for this
verification. The full set of patterns could be simulated in parallel mode with no modules black-
boxed.

ATE Pattern Debug

During initial vector debug we saw significant yield loss on the tester for the small blocks with
the simple scan chain continuity test.

Table 1 Initial Tester Yield Losses

Block Initial Yield Loss
PM <1%
ABA ~24%
ABB ~41%
All ~28%

SNUG 2012 9 DFT for fragmented digital blocks

Using the individual sets of block patterns we were able to identify that the problem was a “top
level” issue affecting the Audio and Low Frequency blocks. Strangely the scan continuity test
failed at the start but then started working. This cause was eventually identified as a delay in set-
tling one of the power supplies at the start of the scan tests. This showed the value of being able
to resolve fails to individual blocks. If the individual compression mode scan chains had con-
tained flops from different blocks then this type of analysis would be much more difficult.

Debug and tolerance of scan chain timing errors

On a related project we made similar use of the compression technology to improve diagnosabil-
ity and tolerance of scan chain timing issues. The design used DFTMAX compression with 75
chains of 45 bits in compression mode and 15 chains of 225 bits in full scan mode.

In production we saw a loss of around 10% yield during scan test using compressed patterns.
Analysis of the tester fail logs showed that the failing devices were failing the simple scan conti-
nuity test with a race condition in the scan chain. However, the fails were intermittent and incon-
sistent.

Using a simple scan continuity test it is possible to identify the type of error within a scan chain
but not the physical location. Scan chain fails can be diagnosed from the full set of scan patterns.
A “candidate” fault location and type are identified and then the scan patterns are simulated as-
suming this fault. The simulation matches/mismatches in the faulty simulation are compared
against the observed results from the tester. The candidate fault location is iterated to find the
best possible match between simulation and tester results. However, this process does not always
yield an accurate result. Particularly if the fault is intermittent no diagnosis may be possible.

Using TetraMAX diagnostics on the compressed patterns gave very low scores for diagnosis
accuracy. If the compressed patterns were mapped to scan mode via the netlist independent bina-
ry format and run on the tester, no accurate diagnostic results were reported.

However, if the diagnostics were run on the compressed patterns with the “mapping_report” op-
tion set, then it could be seen that in 80% of cases a single chain was identified as the location of
the failing flop. A new set of chain test patterns with XX cell constraints on the suspect chain ran
with much lower yield loss and confirmed the faulty chain

It was then possible to rerun ATPG with “XX” cell constraints applied to the failing chain. Be-
cause X-tolerant DFTMAX had been implemented only the 45 flops (out of 3375) in this broken
chain had to be treated as non-scan. The loss of test coverage was around 0.84%, which is rea-
sonable if 1.3% of scan flops have been constrained.

Further diagnosis identified the exact location of the “break” in the scan chain due to the inter-
mittent race condition. It was then possible to rerun ATPG with different constraints:

Flops between the scan-in of the chain and the break have OX constraints because they are
unobservable

SNUG 2012 10 DFT for fragmented digital blocks

 Flops between the break and the scan-out have constraint to “load 0” (assuming no chain
inversions) because the load of a constant value will work independent of possible race
conditions. A second ATPG run used a “load 1” constraint.

In this new ATPG run the loss of coverage was 0.06% compared with fully functional scan
chains.

If only conventional scan chains were implemented then 225 flops would be in the broken chain.
The much larger number of constrained flops would give a much greater loss of test coverage.

The use of DFTMAX also gave a much smaller list of candidate flops when diagnosing the tim-
ing problem, which made the task easier and quicker.

5. Test Coverage Reporting

Producing accurate test coverage numbers might appear a trivial task, but because of the design
style and tool flow used it is not always easy to produce accurate results.

The test coverage values reported by TetraMAX can be distorted for two main reasons:

1. Logic is “stripped” during the model build phase and the corresponding faults are conse-
quently lost.

2. Faults are incorrectly assigned to the “unused” category and so excluded from test cover-
age (but not fault coverage) calculation.

TetraMAX has two different categories for unused faults:

UU – the gate output is unconnected or feeds only a gate with unconnected output, without any
fan-out.

UO – the gate feeds only unused outputs, but does so via fanout.

In a purely digital design it is accepted that faults on “unused” logic is excluded from test cover-
age calculation (but not fault coverage). This unused logic can be QN (or Q) outputs of flops that
are not used functionally. It may also be unused outputs of complex blocks such as adders or
“spare cells” which are included in the design to support metal only ECOs but are not yet con-
nected.

TetraMAX can exclude these faults in three ways:

1) The logic feeding any unconnected outputs is removed during the build phase unless the fol-
lowing option is used:

set_build -nodelete_unused_gates

SNUG 2012 11 DFT for fragmented digital blocks

Obviously, if the logic has been removed the corresponding faults will also be removed

2) The logic can be incorrectly classified as unused and removed from the test coverage calcula-
tion.

3) Manipulation of the test coverage equation:

set_faults –test_coverage_include {UU UO}

NOTE: This would only be needed if the default had been changed so the faults were not deduct-
ed from the calculation with the set_faults –test_coverage_exclude option.

There are several ways in which test coverage can be affected by design style in mixed signal
designs:

Removal of Non-Digital Pins for ATPG

When generating scan tests for a mixed signal design it may be convenient to remove the ana-
logue pins from the TetraMAX model so that they do not appear in the final test data. Two pos-
sible methods for doing this are:

1) Add an extra top level of hierarchy (often called a “wrapper”) which has only the digital pins
defined on the interface. The real design is instantiated within the wrapper and the analogue pins
are left unconnected.

2) Use the TetraMAX “add_net_connection” commands to delete the pins from the compiled
model:

add_net_connection tiex { <pin_name> } –remove # remove input

add_net_connection tiez { <pin_name> } –remove # remove inout

add_net_connection po { <pin_name> } –remove # remove output

Both these techniques create the problem that the logic feeding the “removed” outputs and inouts
will be seen as unused and removed from the calculation. This fault removal can propagate itera-
tively through the design and down through the hierarchy.

Use of Empty Boxes

In a chip level netlist for a mixed signal design the analogue blocks may be defined as empty
Verilog modules. These will affect the test coverage because faults on the input of an empty box
are classified as UU or UO. This problem can be solved by using a TetraMAX command to de-
fine “black box” or “empty box” for the modules in question:

SNUG 2012 12 DFT for fragmented digital blocks

 set_build -black_box module_name

set_build -empty_box module_name

The first option fills the module with a “TIEX” cell; the second fills the module with “TIEZ”
cell. Both will move the input faults from the “UNUSED” to “ATPG UNTESTABLE” category,
provided the module outputs are not “unused”. It is important to realise that a TetraMAX “empty
box” is different from a Verilog empty module definition.

The effects of these options are shown in the diagrams below:

Figure 3 Verilog empty module

Figure 4 TetraMAX set_build -

black_box

SNUG 2012 13 DFT for fragmented digital blocks

As described, the classification of the faults on the block input as UU/UO will propagate across
and through the hierarchy. In the example shown below the classification crosses from an ana-
logue block, through a level shifter and into the digital core of the design.

Figure 5 UU/UO fault propagation through the design

Use of “portfault” Boxes

The is another option for set_build:

set_build –portfault_box module_name

This forces the build process to preserve the module pin names and prevent them from being
removed during the model optimisation process. However, this option does not prevent the mod-
ule instance from being stripped from the design if it is classified as “unused” and the “de-
lete_unused_pins” options is set. Also, if it is on an empty Verilog module, the faults on the in-
puts will still be classified as “UO”.

Use of Grey Boxes

Where a module does not need to be defined the fault classification can be resolved by the meth-
od described above. However, some blocks need a partial or “grey” box definition which leaves
some ports unused. For example an oscillator block may be bypassed in scan mode. In the exam-
ple shown below of an oscillator block when the oscillator is disabled (XTAL_EN=0) the
OSC_OK signal is forced to a known state and the XOUT signal is sent to OSC_CLK_1 and
OSC_CLK_2 to allow scan test of the associated blocks. This simple model is essential for scan
test but will create UO/UU faults on the remaining inputs which are only used in functional
mode.

SNUG 2012 14 DFT for fragmented digital blocks

 Figure 6 Oscillator Module View

Figure 7 Oscillator Internal Logic

Use of “add_nofaults” and “add_equivalent_nofaults” commands

An alternative approach to producing an accurate fault model is to “nofault” the analogue blocks
before adding all faults:

add_nofaults –module module_name

add_nofaults –instance { instance_name_list }

This will mean that possible fault locations in the analogue blocks will not have faults added. It
may also be valid to add the equivalent faults to the list

add_equivalent_nofaults

SNUG 2012 15 DFT for fragmented digital blocks

This prevents faults being added on the equivalent sites. Where there is buffering or isolation
logic (to prevent analogue blocks being switched during scan test) it is reasonable to exclude
these faults. However, the “equivalent faults” can continue to propagate into the core part of the
design.

Figure 8 Propagation of equivalent nofaults

The figure above shows an example of how this can occur. On the right there is a D-to-A block
which has been “nofaulted”. The “nofault” sites are indicated by “#” in the TMAX schematic.
The AND2 gate providing isolation at the digital/analogue interface has been (reasonably) no-
faulted. However, there is a functional 8 input AND tree (built from 2 AND4 gates and one
AND2 gate) in the digital core which has had all the stuck-at-0 faults “no faulted”. This approach
to using TMAX can be particularly risky because it can affect some of the hardest to test logic, at
the digital/analogue interface. Also, the effects do not show up in the standard fault lists and
test/fault coverage reports. There is a separate command to report the nofault sites:

report_nofaults -all

However, some analysis needs to be done to ensure that the only valid fault sites have been ex-
cluded.

Input only analogue models

Even if Verilog modules are defined as “black_box” incorrect fault classification can occur with
inputs to analogue blocks where all ports are declared as input. The example below shows a ref-
erence voltage generator.

SNUG 2012 16 DFT for fragmented digital blocks

 Figure 9 Reference Voltage Generator
It may appear incorrect to have a module with only input ports. However, when creating Verilog
models for analogue signals such as voltage references the concept of port direction has no
meaning.

Power on reset blocks

A commonly used design style is to model POR blocks with the output POR signal tied to a con-
stant value for the inactive state:

assign por_n = 1’b1;

The actual reset state of the flops can be created using the TetraMAX command:

set_drc -initialize_dff_dlat <0|1|x|random> instance_name

However, the constant assignment on the por_n signal will create “Untestable Tied” (UT) faults
which can propagate into the logic.

Verifying Correct Modelling

There is no standard command in TetraMAX to report empty modules. The online help docu-
mentation suggests that the following command would report these:

report_modules -black_box

However, this only reports modules which have been explicitly defined as black-boxes with the
command set_build. (STAR 9000521474 is related to these issues).

It is possible to automate checking using the output of the command:

report_modules –verbose -all

This generates a text format description of each module including the following information:

SNUG 2012 17 DFT for fragmented digital blocks

 Name
Number of instances
Is the module explicitly defined as a black or empty box?
The list of input/output/bidi pins
The internal instances and connectivity.

pins
module name tot( i/ o/ io) inst refs(def'd) used
-------------------------------- ---------------- ---- ----------- ----
BUFX1 2( 1/ 1/ 0) 1 2 (Y) 2
Inputs : A ( )
Outputs : Y ( )
I0 : buf conn=( O:Y I:A )
my_block 2( 1/ 1/ 0) 0 1 (Y) 1(BB)
Inputs : IN1 ( )
Outputs : OUT1 ( )
example 2( 1/ 1/ 0) 3 0 (Y) 1
Inputs : IN ( )
Outputs : OUT ( )
i0 : BUFX1 conn=( O:in_int=Y I:IN=A )
i1 : BUFX1 conn=( O:OUT=Y I:out_int=A )
i_my_block: my_block conn=( O:out_int=OUT1 I:in_int=IN1 )
------------------------------------------------------------------------------

By parsing this file it is possible to identify all empty modules in the design (all IO ports have no
connections) and check if they are explicitly defined as black or empty boxes. An error report for
undefined empty boxes can be generated.

It is also possible to check for grey boxes (some inputs unused) but some normal digital blocks
may meet this description after synthesis propagates constants or removes unused outputs. So the
results should be reviewed. Similarly “input only” blocks can also be identified and reported.

Design Flow Recommendations

Based on the experience of this project the following suggestions are made:

1. Always use the –nodelete_unused_gates option for set_build.

2. Do not delete pins from the chip top level, either with the add_net_connection
command or by use of a wrapper. These should be constrained/masked during ATPG and
can be removed during the vector translation flow to the ATE format.

3. All “empty” Verilog module definitions should be defined as either black_box or

empty_box with the set_build command.

SNUG 2012 18 DFT for fragmented digital blocks

 4. Use the option set_faults -fault_coverage. If there is a significant discrepan-
cy between the test and fault coverage numbers this can indicate potential issues.

Ideally, TetraMAX should be enhanced to automatically report all “empty modules” and/or
check that they are defined as empty or black boxes. The command report_modules –
black_box does not report these, only modules which have been explicitly defined as black
boxes.

Coverage Results

A basic TetraMAX flow was run on this design using the same ATPG flow but with different
options for pin removal and empty module handling.

Run 1 Non digital pins removed and empty modules not declared as black boxes.
Run 2 Non-digital pins retained and empty modules defined as black boxes.

The table below shows the difference in fault classification for the main blocks between the two
runs. The differences arise mainly because of changes in the fault classification between Unde-
tectable and Untestable:

Table 2 Fault Classifications

Fault Classification Run 1 Run 2
Undetectable Unused (UU) 5.4% 5.2%
Undetectable Unobservable (UO) 4.4% 1.6%
ATPG Untestable (AU) 4.2% 7.1%
UU/UO/AU Percentage of Total 14.0% 13.9%

In summary, faults which were propagating into empty modules or deleted pins in “run 1“ and so
incorrectly classified as UO have now been correctly classified as ATPG untestable.

Do the Untestable Faults Matter?

The percentage of untestable faults seems fairly high. However, most of this logic consists of
isolation gates which force known states onto the digital block outputs to prevent unpredictable
and potentially damaging behaviour in the analogue blocks during test. This “isolation” behav-
iour will be implicitly tested during scan test (or is not needed). The “unisolated” values will be
implicitly tested when the digital core is used to test the analogue blocks. For example all bits of
the voltage select signal to an LDO should be used during the test.

However, it is important to correctly classify faults otherwise the incorrect fault classification
can propagate through the isolation logic into the digital core. In a worst case scenario non-scan

SNUG 2012 19 DFT for fragmented digital blocks

sequential elements, such as register files, driving the analogue interface will be removed from
the calculation.

Impact on run times and memory utilisation

Setting the option “set_build –nodelete_unused_gates” is not normally recom-

mended unless there is a requirement to report fault coverage. (If this option is used with
“set_faults –fault_coverage” TMAX will issue an M245 message warning that the
fault coverage calculation is affected). However, if unused gates are not deleted it will impact the
model build size, memory usage and run times. The details for this design are shown below:

Table 3 Impact of no unused gate deletion

-delete_unused_gates -nodelete_unused_gates
#primitives 41,775 99,587
CPU time 0.58 seconds 0.87 seconds
Memory 14MB 25MB

On small mixed signal designs these increases may not cause problems. On large designs,
particularly when multi-process ATPG is being run they may not be acceptable. In those cases it
would be possible to use a separate build_model run to check the accuracy of the fault
classification and use of black boxes before rebuilding a model optimised for ATPG.

6. Conclusions

The paper has described some DFT techniques for mixed signal designs which contain a number
of digital blocks, rather than just a single monolithic block.

Firstly, it has been shown that the DFTMAX compression architecture can be used to create ro-
bust scan chains, tolerant to failure and giving improved yield analysis and diagnosis of scan
chain failures.

Secondly, possible inaccuracies in test coverage calculation have been shown and methods with-
in TetraMAX to avoid these problems.

7. References

[1] TetraMAX Online Help.

[2] Digital Systems Testing and Testable Design; Abromovici, Breuer and Friedman.

SNUG 2012 20 DFT for fragmented digital blocks