BCA-VI SEM

SUBJECT: MICROPROCESSOR & ASSEMBLY LANGUAGE

PROGRAMMING
UNIT: III
Memory:
Memory stores information such as instructions and data in binary format (0 and 1). It provides this
information to the microprocessor whenever it is needed. There is a memory “sub-system” in a
microprocessor-based system. This sub-system includes the registers inside the microprocessor. These
memory can be classified as:
Read Only Memory (ROM) used to store information that does not change.
Random Access Memory (RAM) (also known as Read/Write Memory) is used to store information
supplied by the user such as programs and data.
The memory map is a picture representation of the address range and shows where the different memory
chips are located within the address range.

To execute a program the user enters its instructions in binary format into the memory. The
microprocessor then reads these instructions and whatever data is needed from memory, executes the
instructions and places the results either in memory or provides it on an output device.
To execute a program, the microprocessor “reads” each instruction from memory, “interprets” it, then
“executes” it. The microprocessor fetches each instruction, decodes it & then executes it. This sequence
is continued until all instructions are performed.
For this process it uses address bus & data buses. The address bus has 8 signal lines A8 –A15 which are
unidirectional. The other 8 address bits are multiplexed (time shared) with the 8 data bits. So, the bits
AD0 –AD7are bi-directional & and work as A0 –A7 & D0 –D7at the same time. During the execution of
the instruction, these lines carry the address bits during the early part, then during the later parts of the
execution, they carry the 8 data bits.
In order to separate the address from the data, we can use a latch to save the value before the function of
the bits changes. This is called as Demultiplexing AD7-AD0. Since, the AD7–AD0 lines are working as
dual purpose so they need to be demultiplexed to get all the information.
The high order bits of the address remain on the bus for three clock periods. But, the low order bits
remain for only one clock period & they would be lost if they are not saved externally & so, the low
order bits of the address disappear when they are needed.
To make the entire address for the full three clock cycles, we will use an external latch to save the value
of AD7–AD0 when it is carrying the address bits. We use the ALE signal to enable this latch.
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 BCA-VI SEM
SUBJECT: MICROPROCESSOR & ASSEMBLY LANGUAGE
PROGRAMMING
UNIT: III
The ALE operates as a pulse during T1 (timing state 1), we will be able to latch the address. Then when
ALE goes low, the address is saved and the AD7–AD0 lines can be used as the bi-directional data lines.
The high order address is placed on
the address bus and hold for 3
clock periods.
The low order address is lost after
the first clock cycle, this address
needs to be hold so we need to use
latch.
The address AD7 –AD0 is
connected as inputs to the latch
74LS373. The ALE signal is
connected to the enable (G) pin of
the latch and the OC –Output
control –of the latch is grounded.

Accessing Information in Memory:

For the microprocessor to access (Read or Write) information in memory (RAM or ROM), it needs to do
the following- Select the right memory chip (using part of the address bus). Identify the memory location
(using the remaining of the address bus). Access the data (using the data bus).
For accessing information from the memory tri-state buffers & latches are used.
1). Tri-State Buffers: An important circuit element that is used extensively in memory. This buffer is a
logic circuit that has three states: Logic 0, logic1, and high impedance.
When this circuit is in high impedance mode it looks as if it is disconnected from the output completely.
This circuit has two inputs and one output. The first input behaves like the normal input for the circuit.

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 BCA-VI SEM
SUBJECT: MICROPROCESSOR & ASSEMBLY LANGUAGE
PROGRAMMING
UNIT: III
The second input is an “enable”. If it is set high, the output follows the proper circuit behavior. If it is set
low, the output looks like a wire connected to nothing.

2). Latch: This latch has an input

where the data comes in. It has an enable input and an output on which data comes out. Data is always
present on the input and the output is always set to the contents of the latch. To avoid this, tri-state
buffers are added at the input and output of the latch. The WR signal controls the input buffer. The bar
over WR means that this is an active low signal. So, if WR is 0 the input data reaches the latch input. If
WR is 1 the input of the latch looks like a wire connected to nothing. The RD signal controls the output
in a similar way.
The WR signal controls the input buffer. The bar over WR means that this is an active low signal. So, if
WR is 0 the input data reaches the latch input. If WR is 1 the input of the latch looks like a wire
connected to nothing. The RD signal controls the output in a similar manner.

Design of a Memory Chip: The

Memory is usually measured by two numbers: its length and its width (Length X Width).The length is the
total number of locations. The width is the
number of bits in each location. The length
(total number of locations) is a function of the
number of address lines.
# of memory locations = 2( # of address lines)
So, a memory chip with 10 address lines would
have:
210 = 1024 locations (1K)
So, a memory chip with 4K locations would
need:
Log24096=12 address lines
The 8085 has 16 address lines. That means it
can address:
216 = 64K memory locations.

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 BCA-VI SEM
SUBJECT: MICROPROCESSOR & ASSEMBLY LANGUAGE
PROGRAMMING
UNIT: III
Then it will need 1 memory chip with 64 k locations, or 2 chips with 32 K in each, or 4 with 16 K each or
16 of the 4 K chips, etc.
Memory interfacing to 8085
8085 has 16 bit address bus; hence it can access 216 no. of memory locations, which is equal to 64KB
memory. For any microprocessor memory is required to store program as well as data. Since
microprocessor doesn’t have on-chip memory, we need to connect it externally. So it requires addressing
mechanism. The following are the steps involved in interfacing memory with 8085 processor.
First decide the size of memory requires to be interfaced. Depending on this we can say how many
address lines are required for it. For example if you want to interface 4KB (212) memory it requires 12
address lines. Remaining address lines can be used in address decoding.
Depending on the size of memory required and given address range, construct address decoding circuitry.
This address decoding circuitry can be implemented with NAND gates and/or decoders. Connect data bus
of memory to processor data bus. Generate the control signals required for memory using IO/ Ḿ , WR
´ , RD
´
signals of 8085 processor.
Example:
Q). Interface 4KB memory to 8085 with starting address A000H.
Sol: 4KB memory requires 12 address lines for addressing as already mentioned. But 8085 has 16
address lines. Hence four of address lines are used for address decoding
Given that starting address for memory is A000H. So for 4KB memory ending address becomes
A000H+0FFFH (4KB) = AFFFH. A0-A11 address lines are directly connected to address bus of memory
chip. A12-A15 are used for generating chip select signal for memory chip.

Address decoding circuit using 3X8 decoder: A15 line is use for enabling 74x138 decoder chip. A12,
A13, A14 lines are connected to 74X138 chip as inputs. When theses lines are 010 output should be ‘0’ ie
it should be ‘low’. This is provided at O2 pin of 74X138 chip.

Address decoding circuit using only NAND gates: A15, A14, A13, A12 inputs should be 1010, for
enabling the chip.
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 BCA-VI SEM
SUBJECT: MICROPROCESSOR & ASSEMBLY LANGUAGE
PROGRAMMING
UNIT: III
Types of address decoding:
There are two types of address decoding mechanism, based on address lines used for generating chip
select signal.
1. Absolute decoding
2. Partial decoding
Absolute decoding:
All the higher order lines of microprocessor, left after using the required signals for memory are
completely used for generating chip select signal. This type of decoding is called absolute decoding.
Partial decoding / Linear decoding:
Only some of the address lines of microprocessor left after using the required signals for memory are
used for generating chip select signal. Because of this multiple address ranges will be formed. If total
memory space is not required for the system then, this type of address decoding can be used. The
advantage of this technique is fewer components are required for memory interfacing because of this
board size reduces and in turn cost reduces.
Example:
Q). Connect 512 bytes of memory to 8085
1. For interfacing 512 bytes 9 address lines are required. So A0-A8 can be used to directly connect
to address bus of memory.
2. In the remaining A9-A15 for example only A15-A12 are used for generating chip select signal.
A11-A9 are don’t care signals. 

Because of the don’t care signals the address range can be

(0000 to 01FF), (0200 to 03FF), (0400 to 05FF), (0600 to 07FF), (0800 to 09FF), (0A00 to 0BFF), (0C00
to 0DFF), (0E00 to 0FFF)
Address decoding circuit:
 

IO interfacing to 8085
There are two techniques through which devices can be interfaced to microprocessor.
1. Memory mapped I/O
2. Peripheral mapped I/O or I/O mapped I/O 

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 BCA-VI SEM
SUBJECT: MICROPROCESSOR & ASSEMBLY LANGUAGE
PROGRAMMING
UNIT: III
Memory mapped I/O:
I/O devices are interfaced using address from memory space. That means IO device address are part of
addresses given to memory locations. 8085 uses 16-bit address to memory interfacing. So any address
between 0000H-FFFFH can be given to each peripheral. But the addresses given to peripheral can’t be
used for memory.
Memory control signals are used as read and write control signals for peripherals & all the operations that
can be performed on memory can also be performed on peripherals. There is no need of using IO
instructions such as IN, OUT.
IO mapped IO:
In this method separate address space is given to IO devices. Each IO device is given a 8-bit address.
Hence maximum 256 devices can be interfaced to the processor. The address range for the IO devices is
00H-FFH. IO control signals are used to perform read, write operations.
For reading data from IO device or writing data to IO device IN, OUT instructions needs to be used.
Arithmetic and logical operations can’t be performed directly on IO devices as in memory mapped IO.    
IO devices can be interfaced, by using buffers for simple IO i.e. by using address decoding circuit to
enable buffer.  For handshake IO or to interface more peripherals ICs like 8255 peripheral programmable
interface (PPI) can be used.  
8085 interrupts
An interrupt is a signal or condition that causes processor to stop its normal execution flow and makes it
to jump to some other location for processing the interrupt.
8085 has 4 mask-able interrupts and 1 non-mask-able interrupts. Maskable interrupts can be disabled
using DI instruction. Out of the four (4) mask-able interrupts one is non-vectored interrupt, that is
processor cannot go to a fixed location as it can in case of vectored interrupt, the external device which
caused interrupts needs to specify the vector address.
8085 interrupt response process:
Interrupts should be enabled by using EI instruction, then only processor responds to all mask able
interrupts.
 When microprocessor is executing a program, it checks for INTR line or signal during execution
of each instruction.
 If INTR is high then processor completes executing the current instruction, disables the interrupts
and sends a INTA signal
 INTA is used by the external hardware to specify the restart instruction to processor since INTR
is a non-vectored interrupt.
 When microprocessor receives the RST instruction, it saves PC content on stack and PC is loaded
with the vector address.
 Microprocessor executes the instructions at vector address.
 The interrupts should be enabled if required in the ISR(interrupt service routine)
 At the end of interrupt service routine, RET instruction loads the PC from the stack. So processor
comes back to the instruction where it was interrupted previously.
Restart instructions: RST n
These instructions are like software interrupts to 8085. When these instructions are executed processor
vectors or jumps to a specific location called restart location. The restart location for different RST
instructions are:
'n' value -- Vector location -- hex code
RST 0 -- 0000H -- C7
RST 1 -- 0008H -- CF
RST 2 -- 0010H -- D7
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 BCA-VI SEM
SUBJECT: MICROPROCESSOR & ASSEMBLY LANGUAGE
PROGRAMMING
UNIT: III
RST 3 -- 0018H -- DF
RST 4 -- 0020H -- E7
RST 5 -- 0028H -- EF
RST 6 -- 0030H --F7
RST 7 -- 0038H –FF
To get the vector location 'n' value is multiplied by 8 and the result is converted to hexadecimal notation.
For example RST 3 instruction, multiply 3*8=24. 24 in hexadecimal notation is 18H. So vector address is
0018H.
8085 has 5 external interrupts.
RST 5.5, RST 6.5, RST 7.5, TRAP are vectored interrupts. INTR is non-vectored interrupt. TRAP is a
non mask able interrupt. TRAP is level and edge triggered, RST 7.5 is positive edge triggered, RST 6.5,
RST 5.5 are level triggered.
Interrupt Priority:
When more than one interrupts occur at the same time, then processor responds to them according to the
following priority
TRAP(highest)
RST 7.5
RST 6.5
RST 5.5
INTR (lowest)
Interrupt vector locations:
TRAP – 0024H(it is same as RST 4.5)
RST 5.5 – 002CH
RST 6.5 – 0034H
RST 7.5 – 003CH
To get the vector location for RST interrupts, interrupt value is multiplied by 8 and the result is converted
to hexadecimal notation. For example RST 5.5 instruction, multiply 5.5*8=44. 44 in hexadecimal
notation is 2CH. So vector address is 002CH.
Masking of interrupts:
SIM instruction sets mask pattern for RST 5.5, RST 6.5, RST 7.5.
SIM instructions reads accumulator bit pattern and accordingly masks the interrupts. The bit pattern is as
following: It also resets D flip-flop of RST 7.5 interrupt & it also implements serial I/O transmission.

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 BCA-VI SEM
SUBJECT: MICROPROCESSOR & ASSEMBLY LANGUAGE
PROGRAMMING
UNIT: III

Reading pending interrupts:

RIM instruction is used to read pending interrupts. After executing this instruction accumulator is loaded
with the interrupt status signals. This instruction is also used to receive serial data. The given fig. shows
the bit pattern:

Data Transfer Schemes:

Data between the µP and I/O devices is transferred according to schemes that may fall into one of the
following categories:
1. Programmed data transfer, and
2. Direct memory access memory transfer.
Programmed data transfers are generally used when a relatively small amount of data is transferred using
relatively slow I/O devices, e.g. some A/D, D/A converters. In these schemes, usually one byte or word
of data is transferred at a time. When a large block of data is to be transferred, DMA is used. DMA is
used for transferring data from peripheral mass storage devices like a hard disk or a high-speed line
printer.
Programmed data transfer can be further classified as:
1. Synchronous transfer,
2. Asynchronous transfer (or handshaking),
3. Interrupt driven transfer.
All these schemes require both hardware and software for their implementation. Within a µC, more than
one scheme can be used for interfacing various I/O devices.
Programmed Data Transfer:
a). Synchronous Mode : This is the simplest of all the data transfer schemes. Synchronous mode of data
transfer is used for I/O devices whose timing characteristics are precisely known, or fast enough to be
compatible in speed with the communicating microprocessor. Whenever data is to be obtained from the
device, or transferred to the device, the user program may issue a suitable instruction for the device. At
the end of the execution of this instruction, the transfer gets completed. Hence, if an output device is
connected to the 8085 in the memory mapped mode, the instruction MOV M, A may be used for
transferring Accumulator contents to the device, assuming that the address of the device is already stored
in the HL register pair. If the device is connected in I/O mapped mode, then the OUT instruction may be
issued. The synchronous mode can also be applied to slow I/O devices, if the timing characteristics of
these devices are precisely known. In this case the data transfer is initiated by requesting the I/O device to
get ready and hen the PROCESSOR waits for some predetermined time, usually by generating a delay,
and then executes the I/O instruction to complete the data transfer.
b). Asynchronous Mode
When the I/O device speed and µp speed do not match, asynchronous mode may be used. The key feature
of this mode is that, the microprocessor initiates(start) data transfer by requesting the device to get ready
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 BCA-VI SEM
SUBJECT: MICROPROCESSOR & ASSEMBLY LANGUAGE
PROGRAMMING
UNIT: III
and then goes on checking its status. The I/O instruction is executed only when the I/O device is ready to
accept or supply data. So, each data transfer is preceded by a ‘request ready’ signal generated by the
microprocessor & an acknowledgement signal issued by the I/O device. The method is known as
handshaking mode of data transfer, as it resembles the back-and-forth movement of hands involved in
handshaking, to coordinate the data transfer. The asynchronous mode is ideal for reconciling the timing
differences between the microprocessor & I/O devices. But, an important disadvantage is that a lot of
precious processor time is wasted during the looping to check the I/O device status.
c). Interrupt driven Mode: To overcome the drawbacks of the synchronous and asynchronous modes of
data transfer, another programmed data transfer called Interrupt driven mode has been designed. The
basic idea of this mode is that, the processor initiates the data by requesting the device ‘to get ready’ and
then goes on executing its original program instead of wasting its time by continuously monitoring the
status of the I/O device. When the device is ready to accept or supply data, it informs the processor
through some special control line known as interrupt line. In reply to this, the processor completes the
execution current instruction. So, it does not execute the next instruction, but it saves the PC & other
registers in stack and branches to a pre-determined location, which is the starting address of a subroutine
called interrupt service subroutine (ISS). The ISS saves the processor status on the stack, completes the
data transfer with the I/O responsible for interrupt, restores the processor status and then returns to the
original program that the processor was executing before the interrupt. In this mode, the time needed by
the I/O device to get ready after receiving the ‘get ready’ is utilized by the processor. But the processor
has to do some extra task in storing and restoring the processor status to and from the stack.
DMA mode of data transfer
For any processor, there are instructions for data transfer from memory or I/O device to the processor
registers and vice versa. But there does not exist any instruction for data transfer between memory and
I/O devices directly. So, using any one of the programmed I/O modes, data transfer between memory and
I/O devices can be done in two steps using one of the processor registers i.e. the accumulator through a
media. This makes the programmed I/O data transfer modes very slow. If a large block of data is to be
transferred between memory and a fast I/O device, the extra task can be controlled. The direct memory
access (DMA) mode has been designed to overcome this problem. The main idea in this method is that,
the processor is dissociated(detached) from the data transfer process by tri-stating its system bus. A direct
link is established between the memory and I/O device, and an external circuit known as DMA controller
controls data transfer. Here, the data transfer rate is only limited by the minimum speed of either of the
two devices. So, to follow DMA mode of data transfer, the processor should have following features:
1. An input control line, through which the I/O device, through the DMA controller, requests the
processor for DMA data transfer.
2. An output control line, through which the processor informs the DMA grant(permission).
3. The processor must be able to tri-state the address, data and necessary control lines throughout the
DMA data transfer duration.
The DMA controller must also perform the following functions:
1. Interface the processor buses with the I/O device.
2. Generate DMA request signal.
3. In response to the DMA grant signal from the processor, it must control the address bus and the
control lines needed for data transfer.
4. It must hold the information about the number of bytes to be transferred, along with starting address of
the data in memory, so that it can sequentially generate the RAM address one by one and can withdraw
the DMA request when the last byte of data transfer is over.
Two different types of DMA transfer are possible. In the first case, once initiated, the data transfer
process does not stop until the complete block is transferred. Therefore, this is known as the block DMA
mode. But if the processor cannot be kept inactive for the long duration needed to transfer the complete
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 BCA-VI SEM
SUBJECT: MICROPROCESSOR & ASSEMBLY LANGUAGE
PROGRAMMING
UNIT: III
block of data, or there is significant delay between the consecutive data, the other scheme known as the
cycle stealing DMA mode can be used. In this case, one or two bytes of data are transferred on being
granted the DMA by the processor, and then withdraw the DMA request. After certain time the DMA
controller interrupts the processor, indicating the end of the DMA.

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