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UNIT I
CMOS TECHNOLOGY
UNIT II
CIRCUIT CHARACTERIZATION AND SIMULATION
UNIT III
COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN
UNIT IV
CMOS TESTING
PART- A
UNIT V
SPECIFICATION USING VERILOG HDL
PART - A
1. How do you declare the bus in the HDL?
2. Write the HDL coding for Modulo 2 Adder.
3. What are the uses of UCF file?
4. What do you mean by Data flow model?
5. Define vector in verilog.
6. What is component in HDL?
7. What are the difference between task and function?
8. What is the difference between = = = and = = ?
9. What is meant by continuous assignment statement in Verilog HDL?
10. What is a task in Verilog?
11. Differentiate between conditional and procedural assignment.
12. Why do you require sensitivity list?
13. What are the data types in Verilog?
14. What is wire in Verilog?
15. How to specify nMOS in Verilog?
16. What is the structural gate-level modeling?
17. What are the value sets in Verilog?
18. What are gate primitives?
19.
PART-B
1. Explain the process flow that is followed to develop a project by any HDL with
example. (16)
2. Differentiate the various modes to develop the project and explain them with an
example. (16)
3. Develop the project using HDL to realize the function of a ripple carry adder and
draw its RTL. (16)
4. Design and develop a project in HDL to compare x5x4x3x2x1x0 with
y5y4y3y2y1y0. (16)
5. Design a full adder by cascading two half adders and develop a project to realize it
in model simulator 6.0. (16)
6. Design and develop a HDL project in structural model to realize the priority encoder.
(16)
8. i)Write the verilog code for 4 bit ripple carry full adder.(10)
ii)Give the structural description for priority encoder using verilog.(6)
9. (i) Give a verilog structural gate level description of a bit comparator.
(ii) Give a brief account of timing control and delay in verilog.
10.(i) Give a verilog structural gate level description of a ripple carry adder.
(ii) Write a brief note on the conditional statements available in verilog.
11. (i) write a Verilog program for 3 to 8 decoder in gate level description. (12)
(ii) What are the differences between behavioral and RTL modeling? (4)
12. Write a Verilog program for 8 bits full adder using one bit full adder. The one bit full adder
should be written in behavioral modeling.