Chap04 (12 21 06) PDF

Chapter4 – Introduction (12/21/06) Page 4.0-1.
CHAPTER 4 – CMOS SUBCIRCUITS

INTRODUCTION
Chapter Outline
4.1 MOS Switch
4.2 MOS Diode/Resistor
4.3 Current Sinks and Sources
4.4 Current Mirrors
4.5 Current and Voltage References
4.6 Bandgap Reference
Goal
To develop an understanding of the subcircuits used in CMOS analog circuit design.
What is a subcircuit?
A subcircuit is a circuit primitive used in building other circuits. A subcircuit cannot
typically stand by itself but needs to be connected to other subcircuits to implement a
circuit function.
CMOS Analog Circuit Design © P.E. Allen - 2006
Hierarchy in Analog Circuits

In design, hierarchy is very important as it allows the designer to focus in on the various
blocks without being overwhelmed by the circuit complexity.
Functional blocks or circuits

(perform a complex function)
Blocks or circuits
(Combination of subcircuits, perform a simple function)
Subblocks or subcircuits
(A primitive, not independent)
060526-01

Example of Hierarchy in Analog Circuits
Complex Operational Amplifier

Circuits
Simple Biasing Input Second Output

Circuits Circuits Differential Gain Stage
Amplifier Stage
Sub- Inverter Current

Current Current Current Source Current Source Current
Circuits Sink Load
Source Mirrors Sink Coupled Pair Mirror Load Follower Sink Load
060526-02
Chapter4 – Section 1 (12/21/06) Page 4.1-1.
SECTION 4.1 –MOSFET SWITCH

Switch Model
• An ideal switch is a short-circuit when ON and IAB
an open-circuit when OFF. VC = controlling A B RAB = 0Ω
(VC= high)
terminal for the switch (VC high switch ON, +
VC low switch OFF) VC VAB
− RAB = ∞Ω
(VC= low)
060526−03
• Actual switch:
ron = resistance of the switch when ON IOFF
roff = resistance of the switch when OFF rOFF
VOS
VOS = offset voltage when the switch is ON A
rON
B
Ioff = offset current when the switch is OFF CAB
IA and IB are leakage currents to ground

IA CAC CBC IB
C
CA and CB are capacitances to ground
CA CB
VC
CAC and CBC = parasitic capacitors between
the control terminal and switch terminals 060526-04

MOS Transistor as a Switch

Bulk
A B A B
(S/D) (D/S)
060526-05 C (G)
On Characteristics of a MOS Switch
Assume operation in active region (vDS < vGS - VT) and vDS small.
μCoxW vDS μCoxW
iD = L (vGS - VT) - 2 vDS L (vGS - VT)vDS
vDS 1
Thus, RON iD = μCoxW
L (vGS - VT)
OFF Characteristics of a MOS Switch
If vGS < VT, then iD = IOFF = 0 when vDS 0V.
If vDS > 0, then
1 1
ROFF iD = IOFF
MOS Switch Voltage Ranges

If a MOS switch is used to connect two circuits that can have analog signal that vary
from 0 to 1V, what must be the value of the bulk and gate voltages for the switch to work
properly?
Bulk
(0 to 1V) (0 to 1V)
Circuit (S/D) (D/S) Circuit

1 2
Gate
Fig.4.1-3
• To insure that the bulk-source and bulk-drain pn junctions are reverse biased, the bulk
voltage must be less than the minimum analog signal for a NMOS switch.
• To insure that the switch is on, the gate voltage must be greater than the maximum
analog signal plus the threshold for a NMOS switch.
Therefore:
VBulk 0V
and VGate(on) > 1V + VT
Also, VGate(off) 0V
Unfortunately, the large value of reverse bias bulk voltage causes the threshold voltage to
increase.
Current-Voltage Characteristics of a NMOS Switch

The following simulated output characteristics correspond to triode operation of the
MOSFET. 100μA
VGS=3.0V
VGS=3.5V VGS=2.5V
VGS=4.0V
50μA VGS=4.5V
VGS=5.0V VGS=2.0V
iD 0μA VGS=1.5V
VGS=1.0V
-50μA
-100μA
-1V -0.5V 0V 0.5V 1V
vDS Fig. 4.1-4
SPICE Input File: VGS 2 0 DC 0.0
VBS 3 0 DC -5.0
MOS Switch On Characteristics .DC VDS -1 1 0.1 VGS 1 5 0.5
M1 1 2 0 3 MNMOS W=1U L=1U .PRINT DC ID(M1)
.MODEL MNMOS NMOS VTO=0.7, KP=110U, .PROBE
+LAMBDA=0.04, GAMMA=0.4 PHI=0.7 .END
VDS 1 0 DC 0.0
MOS Switch ON Resistance as a Function of Gate-Source Voltage

100kΩ
MOSFEET On Resistance
10kΩ
W/L = 1μm/1μm
1 kΩ W/L = 5μm/1μm
W/L = 10μm/1μm
100Ω
W/L = 50μm/1μm
10Ω
1V 1.5V 2V 2.5V 3V 3.5V 4V 4.5V 5V
VGS Fig. 4.1-5
SPICE Input File: +LAMBDA=0.04, GAMMA=0.4, PHI=0.7

VDS 1 0 DC 0.001V
MOS Switch On Resistance as a f(W/L) VGS 2 0 DC 0.0
M1 1 2 0 0 MNMOS W=1U L=1U .DC VGS 1 5 0.1
M2 1 2 0 0 MNMOS W=5U L=1U .PRINT DC ID(M1) ID(M2) ID(M3) ID(M4)
M3 1 2 0 0 MNMOS W=10U L=1U .PROBE
M4 1 2 0 0 MNMOS W=50U L=1U .END
.MODEL MNMOS NMOS VTO=0.7, KP=110U,

Influence of the ON Resistance on MOS Switches

Finite ON Resistance: v (0) = 0 v
C
+ - + C -
C VGate C
vin=2.5V vin>0 RON
Example Fig. 4.1-6
Initially assume the capacitor is uncharged. If VGate(ON) is 5V and is high for 0.1μs,
find the W/L of the MOSFET switch that will charge a capacitance of 10pF in five time
constants.
Solution
The time constant must be 100ns/5 = 20ns. Therefore RON must be less than 20ns/10pF
= 2k. The ON resistance of the MOSFET (for small vDS) is
1 W 1 1
RON = KN’(W/L)(VGS-VT) L = RON·KN’(VGS-VT) = =1.06
2k·110μA/V2·4.3
Comments:
• It is relatively easy to charge on-chip capacitors with minimum size switches.
• Switch resistance is really not constant during switching and the problem is more
complex than above.
Including the Influence of the Varying On Resistance

Gate-source Constant gON(0)
ID t=0
K’W VGS=5V
gON(t) = L (vGS(t)-VT) -0.5vDS(t)
1 gON(0) + gON()
gON(aver.) = rON(aver.) 2 gON(∞)
K’W K’WVDS(0) K’W

= 2L (VGS-VT) - 4L + 2L (VGS-VT) t=∞
VDS
vDS(∞) vDS(0) Fig. 4.1-7
K’W K’WVDS(0)
= L (VGS-VT) - 4L
Gate-source Varying ID g (0) t=0 VGate
ON VGS=5V
+
vGS(t)
-
+
vIN C vC(0) = 0
VGS=5V-vIN -
gON(∞)
t=∞
VDS Fig. 4.1-8
vDS(∞) vDS(0)
K’W K’WVDS(0) K’W

gON = 2L [VGS(0)-VT] - 4L + 2L [VGS()-vIN-VT]
Example 4.1-1 - Switch ON Resistance

5V
Assume that at t = 0, the gate of the switch shown is C2 = 10pF
taken to 5V. Design the W/L value of the switch to 0V
0V vout(t)
+ -
discharge the C1 capacitor to within 1% of its initial -
+
charge in 10ns. Use the MOSFET parameters of Table 5V C1 = +
3.1-2. - 10pF
Fig.4.1-9
Solution
Note that the source of the NMOS is on the right and is always at ground potential so
there is no bulk effect as long as the voltage across C1 is positive. The voltage across C1
can be expressed as
-t

vC1(t) = 5expRONC1
At 10ns, vC1 is 5/100 or 0.05V. Therefore,
-10-8 3
0.05=5exp = 5exp -10 exp(G 103)=100 G =
ln(100)
=0.0046S
RON10-11 R ON ON ON 103
K’W K’WVDS(0)
110x10-6·5 W W
0.0046 = L (VGS-VT) - = 110x10 -6 ·4.3- = 356x10 -6
4L 4 L L
W 0.0046
Thus, L = = 13.71 14
356x10-6
Influence of the OFF State on MOS Switches

The OFF state influence is primarily in any current that flows from the terminals of the
switch to ground.
An example might be:
vin
+ vout
+ -
RBulk CH vCH
-
Fig. 4.1-10
Typically, no problems occur unless capacitance voltages are held for a long time. For
example,
vout(t) = vCH e-t/(RBulkCH)
If RBulk 109 and CH = 10pF, the time constant is 109·10-11 = 0.01seconds

Influence of Parasitic Capacitances

The parasitic capacitors have two influences:
• Parasitics to ground at the switch terminals (CBD and CBS) add to the value of the
desired capacitors.
This problem is solved by the use of stray-insensitive switched capacitor circuits
• Parasitics from gate to source and drain cause charge injection and clock feedthrough
onto or off the desired capacitors.
This problem can be minimized but not eliminated.
Model for studying gate capacitance:
1 Cchannel Cchannel 1 Cchannel
1
2 2
CGS0 CGD0 CGS0 CGD0
CL + Rchannel CL + Rchannel CL +
VS vCL VS vCL VS vCL
- - -
A simple switch circuit useful A distributed model of A lumped model of

for studying charge injection. the transistor switch. the transistor switch. Fig. 4.1-11
Channel Charge Injection

Consider the simple switch configuration shown: ON
Clk
OFF OFF
When the switch is ON, a charge is stored in the vin CL

channel which is equal to,
060613-03
Qch = -WLCox(VH-vin-VT)
where VH is the value of the clock waveform when the switch is on (VH VDD)
When the switch turns OFF, this charge is injected into ON
the source and drain terminals as shown. Clk
vin
Assuming the charge splits evenly, then the change of OFF ΔV
voltage across the capacitor, CL, is
vin e- e-
CL
Qch -WLCox(VH-vin-VT)
V = 2CL = 2CL 060613-04
The charge injection does not influence vin because it is a voltage source.

Clock Feedthrough
In addition to the charge injection, the overlap capacitors of the MOSFET couple the
turning off part of the clock to the load capacitor. This is called clock feedthrough.
The model for this case is given as:
A
B VS +VT
Switch OFF VT
C COL
VL
COL COL
Charge +
injection VS +VT CL
vCL
vin ≈VS ≈VD Circuit at the VL
CL VS
instant gate
-
reaches VS +VT
Fig. 4.1-16
The gate decrease from B to C is modeled as a negative step of magnitude VS +VT - VL.
The output voltage on the capacitor after opening the switch is,

CL COL
COL

COL

vCL = COL+CLVS-COL+CLVT -(VS+VT -VL)COL+CL VS-(VS+2VT -VL) CL

if COL < CL.

Therefore the error voltage is, COL COL
Verror -(VS + 2VT – VL) CL = -(vin + 2VT – VL) CL

Modeling the Influence of Charge Injection and Clock Feedthrough

The influence of change injection and clock feedthrough on a switch is a complex
analysis which is better suited for computer analysis. Here we will attempt to develop an
understanding sufficient to show ways of reducing these effects.
To begin the model development, there are two cases of charge injection depending upon
the transition rate when the switch turns off.
1.) Slow transition time – the charge in the channel can react instantaneously to changes
in the turning-off, gate-source voltage.
2.) Fast transition time – the charge in the channel cannot react fast enough to respond to
the changes in the turning-off, gate-source voltage.

Slow Transition Time

Consider the following switch circuit:
A A
Switch ON
B vin+VT B vin+VT
Switch OFF
C C
Charge
injection
vin CL vin CL
Fig. 4.1-13
1.) During the on-to-off transition time from A to B, the charge injection is absorbed by
the low impedance source, vin.
2.) The switch turns off when the gate voltage is vin+VT (point B).
3.) From B to C the switch is off but the gate voltage is changing. As a result charge
injection occurs to CL.
Fast Transition Time

For the fast transition time, the rate of transition is faster than the channel time constant
so that some of the charge during the region from point A to point B is injected onto CL
even though the transistor switch has not yet turned off.
A A
Switch ON
B vin+VT B vin+VT
Switch OFF
C C
Charge Charge
injection injection
vin CL vin CL
Fig. 4.1-14

A Quantized Model of Charge Injection/Clock Feedthrough†

Approximate the gate transition as a stair case and discretize in voltage as follows:
Voltage Voltage
Discretized Gate Voltage

Discretized Gate Voltage
vGATE vGATE
Charge
vin+VT vin+VT injection
vin vin due to fast
vCL vCL transition
t t
Slow Transition Fast Transition Fig 4.1-15
The time constant of the channel, Rchannel·Cchannel, determines whether or not the
capacitance, CL, fully charges during each voltage step.
†
B.J. Sheu and C. Hu, “Switched-Induced Error Voltage on A Switched Capacitor,” IEEE J. Solid-State Circuits, Vol. SC-19, No. 4, pp. 519-525,
August 1984.
Analytical Expressions to Approximate Charge Injection/Clock Feedthrough

Assume the gate voltage is making a transition from high, VH, to low, VL.
vGate = vG(t) = VH – Ut where U = magnitude of the slope of vG(t)
K’W
Define VHT = VH - VS - VT and = L .
The error in voltage across CL, Verror, is given below in two terms. The first term
corresponds to the feedthrough that occurs while the switch is still on and the second
term corresponds to feedthrough when the switch is off.
2
VHT
1.) Slow transition occurs when 2CL >> U.
C
W·CGD0 + channel
2 UCL W·CGD0
Verror = - CL

2 - CL (VS+2VT -VL)
2
VHT
2.) Fast transition occurs when 2CL << U.
C
W·CGD0 + channel V
3
W·CGD0
2 HT
Verror = - CL VHT - 6U·CL - CL (VS+2VT -VL)
Example 4.1-2 - Calculation of Charge Feedthrough Error

Calculate the effect of charge feedthrough vG
on the previous circuit where VS = 1V, CL 5V
= 1pfF, W/L = 0.8μm/0.8μm, and VG is
Case 2
given below for the two cases. Use model
parameters from Tables 3.1-2 and 3.2-1. Case 1
Neglect L and W effects. 0V t
Solution 0.2ns 50ns Fig. 4.1-17
Case 1:
The value of U is equal to 5V/0.2nS or 25x109. Next we must test to see if the slow
or fast transition time is appropriate. First calculate the value of VT as
VT = VT0 + 2|F| -VBS - 2|F| = 0.7 + 0.4 0.7+1 - 0.4 0.7 = 0.887V
Therefore, 2
VHT 110x10-6·3.1132
VHT =VH-VS-VT = 5-1-0.887=3.113V 2CL = 2·1pF = 5.32x108< 25x109
which corresponds to the fast transition case. Using the previous expression gives,
Verror =
176x10-18+0.5(1.58x10-15) -3 -18
- 3.113-3.32x10 - 176x10 (1+1.774-0) = -3.39mV
1x10-12 30x10-3 1x10-12
Example 4.1-2- Continued

Case 2:
In this case U is equal to 5V/50ns or 1x108 which means that the slow transition case
is valid (1x108 < 5.32x108).
Using the previous expression gives,
176x10-18+0.5(1.58x10-15)
314x10-6 176x10-18
Verror = - - (1+1.774-0) = -1.64mV
1x10 -12 220x10-6 1x10-12
Comment:
These results are not expected to give precise answers regarding the amount of
charge feedthrough one should expect in an actual circuit. Rather, they are a guide to
understand the effects of various circuit elements and terminal conditions in order to
minimize unwanted behavior by design techniques.

Solutions to Charge Injection

1.) Use minimum size switches to reduce the overlap capacitances and/or increaseCL.
2.) Use a dummy compensating transistor.
φ1 φ1
W1 W D = W1
L1 LD 2L1
M1 MD
Fig. 4.1-19
• Requires complementary clocks
• Complete cancellation is difficult and may in fact may make the feedthrough
worse
3.) Use complementary switches (transmission gates)
4.) Use differential implementation of switched capacitor circuits (probably the best
solution)
Input-Dependent Charge Injection

Examination of the error voltage reveals that,
Error voltage = Component independent of input + Component dependent on input
This only occurs for switches that are floating and is due to the fact that the input
influences the voltage at which the transistor switches (vin VS VD). Leads to spurious
responses and other undesired results.
Solution: 1
Use delayed clocks to re-
Ci
move the input-depend- t
Cs 2 2
Vin 1d
ence by removing the S1 S4 Vout
path for injection from 2 S2 S3 1
CL t
the floating switches. 1d
Assume that Cs is
t
charged to Vin (both 1 Clock Delay Fig. 4.1-20
and 1d are high):
1.) 1 opens, no input-dependent feedthrough because switch terminals (S3) are at
ground potential.
2.) 1d opens, no feedthrough occurs because there is no current path (except through
small parasitic capacitors).
CMOS Switches (Transmission Gate)

Clock
Clock
A B A B
VDD
Clock
Clock Fig. 4.1-21

Advantages:
• Feedthrough somewhat diminished
• Larger dynamic range
• Lower ON resistance
Disadvantages:
• Requires a complementary clock
• Requires more area
Example 4.1-3 - Charge Injection for a CMOS Switch

Calculate the effect of charge feedthrough on the 5V
circuit shown below. Assume that U = 5V/50ns = vin-|VTP|
108V/s, vin = 2.5V and ignore the bulk effect. Use 0.8μm M2 0V
0.8μm
the model parameters from Tables 3.1-2 and 3.2-1. CL = +
0.8μm
Solution vin
0.8μm
M1
5V
1pF vCL
First we must identify the transition behavior. For -
the NMOS transistor we have vin+VTN

0V Fig. 4.1-18
2
NVHTN 110x10-6·(5-2.5-0.7)2
2CL = 2·10-12
= 1.78x108
For the PMOS transistor, noting that
VHTP = VS - |VTP| - VL = 2.5-0.7-0 = 1.8
2
PVHTP 50x10-6·(1.8)2
we have 2CL = = 8.10x107 . Thus, the NMOS transistor is in the
2·10-12
slow transition and the PMOS transistor is in the fast transition regimes.

Example 4.1-3 - Continued

Error due to NMOS (slow transition):
176x10-18 + 0.5(1.58x10-15) ·108·10-12 176x10-18

Verror(NMOS) = -
- (2.5+1.4-0)
10-12 2·110x10-6 10-12
= -1.840mV
Error due to PMOS (fast transition):
176x10-18+0.5(1.58x10-15) -6 3 -18
Verror(PMOS) = 1.8-50x10 (1.8) +176x10 (5+1.4-2.5)
10-12 6·108·10-12 10-12
= 1.956mV
Net error voltage due to charge injection is 116μV. This will vary with VS.
Dynamic Range of the CMOS Switch

The switch dynamic range is the 10kΩ
VDD VDD=1V
range of voltages at the switch =1V
terminals (VAVB=VA,B) over which 8kΩ
Switch On Resistance
VDD VDD=1.5V
the ON resistance is small. =1.5V
VDD 6kΩ
M1 VDD=2V
4kΩ
A B VDD
VDD
=2V
VA,B 1μA 2kΩ VDD=2.5V
M2
VDD=3V
Fig. 4.1-22
0
0V 0.5V 1V 1.5V 2V 2.5V 3V
Spice File: VA,B (Common mode voltage) Fig. 4.1-22A
Simulation CMOS transmission switch resistance VDD 3 0
M1 1 3 2 0 MNMOS L=1U W=10U VAB 1 0
M2 1 0 2 3 MPMOS L=1U W=10U IA 2 0 DC 1U
.MODEL MNMOS NMOS VTO=0.7, KP=110U, .DC VAB 0 3 0.02 VDD 1 3 0.5
+LAMBDA=0.04, GAMMA=0.4, PHI=0.7 .PRINT DC V(1,2)
.MODEL MPMOS PMOS VTO=-0.7, KP=50U, .END
+ LAMBDA=0.05, GAMMA=0.5, PHI=0.8
Result:
Low ON resistance over a wide voltage range is difficult as the power supply decreases.
CMOS Switch with Twin-Well Switching

VControl
M1
VDD
M3
Analog Analog
Signal Signal
Input Output
M4 M5
VSS
M2
VControl
Circuit when VControl is in its high state. Circuit when VControl is in its low state.
High State Low State
M1 M1
Analog Analog Analog VSS Analog

Signal Signal Signal Signal
Input
VDD Output
Input Output
M2 M2
Low State High State

Charge Pumps for Switches with Low Power Supply Voltages

As power supply voltages decrease below 2V, it becomes difficult to keep the switch
on at a low value of on-resistance over the range of the power supply. The result is that
rON becomes a function of the signal amplitude and produces harmonics.
Consequently, charge pumps are used to provide a gate voltage above power supply.
Principle of a charge pump:
≈2VDD VDD To another

charge pump
M1 vOUT ≈2VDD
+ +
C1 V VDD C2
0 _ DD _
vIN + CL Single
VDD NMOS
vIN VDD 0
Switch
0 _
t 0 060526-06
C2
vOUT = 2VDDC2 + CL + CNMOSswitch

Charge Pump - Continued

High voltage generator for the well of M1:
VDD
2VDD
Vsub_hi To bulk
of M1
VDD C1 C2 CBulk CStorage
0V 060526-07
Prevents latch-up of M1 by providing a high bulk bias (2VDD).
Use a separate clock driver for each switch to avoid crosstalk through the gate clock
lines. Area for layout can be small.
Simulation of the Charge Pump Circuit†

Circuit:
VDD
CLK_out M1 M2 CLK_out
M5 M3
C1 C1
M6 M4
CLK_in
VSS Fig. 4.1-23
Simulation:
3.0
Output
2.0
Input
Volts
1.0
0.0
-1.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
Time (μs) Fig. 4.1-24
†
T.B. Cho and R.R. Gray, “A 10b, 20 Msample/s, 35mW Pipeline A/D Converter,” IEEE J. of Solid-State Circuits, Vol. 30, No. 3m March 1995, pp.
166-172.
Bootstrapped Switches with High Reliability†

In the previous charge pump switch driver, the amount of gate-source drive depends
upon the input signal and can easily cause reliability problems because it becomes too
large for low values of input signal.
VDD
The solution to this problem is a
bootstrapped switch as shown.
Actual bootstrap switch:
VDD OFF ON Fig. 4.1-25
vg
φ Boosted Clock
M2 φ
M1 M3 M4
M8 VDD
C2 M7 M10 VDD
C1
C3 φ Input Signal
M5 M13 vg
φ M9
M12 t
S D
M11 Fig. 4.1-26
low: M7 and M10 make vg=0 and C3 charges to VDD, high: C3 connected to vGS11.
M7 reduces the vDS and vGS of M10 when = 0. M13 ensures that vGS8 VDD.
The parasitics at the source of M11 require this node to be driven from a low impedance.
†
A.M. Abo and P.R. Gray, “A 1.5V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, IEEE J. of Solid-State Circuits, Vol. 34, No. 5,
May 1999, pp. 599-605.
Summary of MOSFET Switches

• Symmetrical switching characteristics
• High OFF resistance
• Moderate ON resistance (OK for most applications)
• Clock feedthrough is proportional to size of switch (W) and inversely proportional to
switching capacitors.
• Output offset due to clock feedthrough has 2 components:
Input dependent
Input independent
• Complementary switches help increase dynamic range.
• Fully differential operation should minimize the clock feedthrough.
• As power supply reduces, switches become more difficult to fully turn on.
• Switches contribute a kT/C noise which can get folded back into the baseband.

SECTION 4.2 –MOSFET DIODE/RESISTOR

MOS DIODES
MOS Diode
When the MOSFET has the gate connected to the drain, it acts like a diode with
characteristics similar to a pn-junction diode.
i
+ +
i
vSG = v
vGS = v
i
- -
v
VT Fig. 4-2-1
Note that when the gate is connected to the drain of an enhancement MOSFET, the
MOSFET is always in the saturation region.
vDS vGS - VT vD - vS vG - vS - VT vD - vG -VT vDG -VT
Since VT is always greater than zero for an enhancement device, then vDG = 0 satisfies
the conditions for saturation.
• Works for NMOS or PMOS
• Note that the drain could be VT less than the gate and still be in saturation
How Does the MOS Diode Compare with a pn Diode?

The comparison is basically the difference between an exponential and a square-law
function. However, if the designer is willing to spend W/L, the comparison becomes
more interesting as shown below.
1mA
Is = 10fA
Output Current
0.8mA
Vt = 26mV
0.6mA
β = 0.01mA/V2
0.4mA VT = 0.3V
0.2mA β = 0.1mA/V2
VT = 0.4V
0mA
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Input Voltage 060526-08
If the threshold voltage is less than 0.4V, the MOS diode is a clear winner over the pn
junction diode even for modest W/L ratios.

Use of the MOS Diode for Biasing

Large-Signal Characteristics:
Ignore channel modulation-
K’W 2iD
i = iD = 2L (vGS - VT)2 = 2 (vGS - VT)2 and v = vGS = vDS = VT +
VDD iD
VDD
R IBias R
+ IBias
VBias
−
vGS
0600526-09 VBias VDD
MOSFET RESISTORS
Why MOSFET Resistors?
• Smaller in area than actual resistors
• Can pass a large current through a large resistance without a large voltage drop
iD
MOSFET (rds = 100kΩ)
100μA
100kΩ Resistor
10μA vDS
1V 10V 060526-10
vds 1
AC resistance = id = gds
where

gds 2 (VGS-VT)2 = ID

MOS Diode as a Resistor

AC and DC resistance: i
AC Resistance
VDS VT 2 DC Resistance
DC resistance = ID = ID + ID
ID
v
VT VDS Fig. 4-2-2B
Small-Signal Load (AC resistance):
D=G D=G
id
G
+ +D
vgs gmvgs rds vds
- -
S S
S S 060526-11
vds 1 1
AC resistance = id = gm + gds gm
where
gm = (VGS-VT) = 2ID
Use of the MOSFET to Implement a Floating Resistor

In many applications, it is useful to implement a VBias
resistance using a MOSFET. First, consider the RAB
A B A B
simple, single MOSFET implementation.
L Fig. 4.2-9
RAB = K’W(VGS - VT)
100μA
VGS=10V
VGS=9V
60μA
VGS=8V
VGS=7V
20μA
VGS=2V
-20μA
VGS=3V
VGS=4V
-60μA
VGS=5V
VGS=6V
-100μA
-1V -0.6V -0.2V 0.2V 0.6V 1V Fig. 4.2-95
Cancellation of Second-Order Voltage Dependence – Parallel MOSFETs

Circuit:
M1
iAB VC VC iAB
A B A RAB B
M2
+ - + -
vAB
vAB 060526-12
Assume both devices are non-saturated

vAB2

iD1 = ß1 (vAB + VC - VT)vAB - 2

vAB2

iD2 = ß2 (VC - VT)vAB - 2
vAB2 vAB2

iAB = iD1 + iD2 = ß vAB2 + (VC - VT)vAB - 2 + (VC - VT)vAB - 2
1
iAB = 2ß(VC - VT)vAB RAB = 2ß(VC - VT)
Parallel MOSFET Performance

Voltage-Current Characteristic:
2mA
Vc=7V
6V
5V
1mA
W=15u 4V
L=3u 3V
I(VSENSE)
VBS=-5.0V
0
-1mA
-2mA
-2 -1 0 1 2 Fig. 4.1-11
VDS
SPICE Input File:

NMOS parallel transistor realization VDS 10 0
M1 2 1 0 5 MNMOS W=15U L=3U VSS 5 0 DC -5
M2 2 4 0 5 MNMOS W=15U L=3U .DC VDS -2.0 2.0 .2 VC 3 7 1
.MODEL MNMOS NMOS VTO=0.75, KP=25U, +LAMBDA=0.01, .PRINT DC I(VSENSE)
GAMMA=0.8 PHI=0.6 .PROBE
VC 1 2 .END
E1 4 0 1 2 1.0
VSENSE 10 2 DC 0

Double MOSFET Differential Resistor

Cancels the bulk effect.
VC1
iD1 i1
M1
v1
iD2 VSS
R i1 - -
v1 M2 v
R i2 VC2
v2 + iD3 v +
M3
iD4 VSS i2
v2
M4
Fig. 4.2-12
VC1
iD1 = [(VC1-v-VT)(v1-v) - 0.5(v1-v)2] iD2 = [(VC2-v-VT)(v1-v) - 0.5(v1-v)2]
iD3 = [(VC2-v-VT)(v2-v) - 0.5(v2-v)2] iD4 = [(VC1-v-VT)(v2-v) - 0.5(v2-v)2]
i1 = iD1+iD3 = [(VC1-v-VT)V1-v) - 0.5(v1-v)2 + (VC2-v-VT)(v2-v) - 0.5(v2-v)2]
i2 = iD2+iD4 = [(VC2-v-VT)(v1-v) - 0.5(v1-v)2 + (VC1-v-VT)(v2-v) - 0.5(v2-v)2]
i1 - i2 = [(VC1-v-VT)(v1-v) + (VC2-v-VT)(v2-v) + (VC2-v-VT)(v1-v) + (VC1-v-VT)(v2-v)]
= [v1(VC1-VC2) + v2(VC2-VC1)] = (VC1-VC2)(v1-v2)
Differential input resistance is
v1-v2 v1-v2 1
Rin = i1-i2 = (VC1-VC2)(v1-v2) = (VC1-VC2) , v1,v2 min{(VC1-VT),(VC2-VT)}
Double-MOSFET, Differential Resistor Performance
150uA
VC2 = 6V SPICE Input File:
5V Double MOSFET Differential Resistor
100uA
VBC =-5V
4V Realization
V3 =0V M1 1 2 3 4 MNMOS1 W=3U L=3U
VC1 =7V 3V
50uA
2V M2 1 5 8 4 MNMOS1 W=3U L=3U
I(VSENSE)
M3 6 5 3 4 MNMOS1 W=3U L=3U

0
M4 6 2 8 4 MNMOS1 W=3U L=3U
VSENSE 3 8 DC 0
- 50uA
VC1 2 0 DC 7V
VC2 5 0
- 100uA
VSS 4 0 DC -5V
- 150uA
V12 1 6
.MODEL MNMOS1 NMOS VTO=0.75 KP=25U
-3 -2 -1 0 1 2 3
+LAMBDA=0.01 GAMMA=0.8 PHI=0.6
V1-V2
.DC V12 -3 3 0.2 VC2 2 6 1
.PRINT DC I(VSENSE))
.PROBE
.END
Comments:
• Good linearity and tunability.
• Can be used as a multiplier.
Summary of MOSFET Resistor Realizations
AC Resistance Linearity How Restrictions

Realization Controlled
Single MOSFET Poor VGS or vBULK < Min (vS, vD)
W/L
Parallel MOSFET Good VC or W/L v (VC - VT)
VC1 - VC2 v1, v2 < min(VC1-VT,VC2-VT)

Very
Double-MOSFET, or vBULK < min(v1,v2)
Good
differential resistor W/L Transresistance only
SECTION 4.3 - CURRENT SINKS AND SOURCES

Ideal Current Sinks and Sources
What is an ideal current sink or source?
i
Io
i +
Io v
− v
060527-01
• Current is fixed at a value of Io

• Voltage can be any value from + to -
• Be careful when using a current sink or source to replace a MOSFET sink/source in
simulation

Characterization of MOSFET Sinks and Sources

A sink/source is characterized by two quantities:
• rout - a measure of the “flatness” of the current sink/source (its independence of
voltage)
• VMIN - the min. across the sink or source for which the current is no longer constant
NMOS Current Sink:
VDD VDD iDS= i
VMIN
VGG
Io
i Slope = 1/rout
i +
+ v
Io v -
- VGG
0 vDS = v
0 VGG-VT0 VDD
0601527-02
1 1+VDS 1
rout = diD/dvDS = D ID and VMIN = VDS(sat) = VGS - VT0 = VGG - VT0
Note: The NMOS current sink can only have positive values of v.
PMOS Current Source

VDD VDD iSD= i
VMIN
+ VGG
Io v VGG +
- v Io
- Slope = 1/rout
i i
0 vSD = v
0 VGG-|VT0| VDD
0601527-03

Gate-Source Voltage Components

It is important to note that the gate-source voltage consists of two parts as illustrated
below:
iD
10W/L W/L 0.1W/L
ID
Enhance Provide
Channel Current
0 vGS
0 VT VGS Fig. 280-03
VGS = VT0 + VON = Part to enhance the channel + Part to cause current flow
where
VON = VDS(sat) = VGS - VT0
2ID
VMIN = VON = VDS(sat) = K’(W/L) for the simple current sink.
Note that VMIN can be reduced by using large values of W/L.

;
Simulation of a Simple MOS Current Sink
120
100
;
;
80
Slope = 1/Rout
iOUT (μA)
;
10μm iOUT
60 1μm +
vOUT
;
VGS1 =
40 -
1.126V
;
20
Vmin
0
0 1 2 3 4 5
vOUT (Volts)
Comments:
VMIN is too large - desire VMIN to approach zero, at least approach VCE(sat)
Slope too high - desire the characteristic to be flat implying very large output resistance
(KN’ = 110μA/V2, VT = 0.7Vand = 0.04V-1) rds = 250k

How is VGG Implemented?

The only voltage source assumed available is VDD.
Therefore, VGG, can be implemented in many ways with the example below being one
way.
VDD VDD
R
i i
+ +
v + v
VGG - VBias=VGG -
-
0601527-04
Better and more stable implementations of VGG will be shown in a later section of this
chapter.
Improving the Performance of the Simple NMOS Current Sink

The simple NMOS current sink shown previously had two problems.
1.) The value of VMIN may be too large.
2.) The output resistance (250k) was too small.
How can the designer solve these problems?
1.) The first problem can be solved by increasing the W/L value of the NMOS transistor.
2ID
VMIN = VON = VDS(sat) = K’(W/L)
In the simulation shown previously,

2·100μA
VMIN = 110μA/V2·10 = 0.426V
We could decrease this to 0.1V with a W/L = 182.

2.) How can the small output resistance be increased? Answer is feedback.

Use of Feedback to Change Resistance

It is well known that feedback can change the
value of a resistance at a pair of terminals (a Feedback
port). The principles are elaborated in the Circuit
figure and table below.
rout
Current Sink
Io
Implementation
060527-05
Type of Feedback rout without feedback (ro) rout with feedback

Negative-series feedback ro ro(1+ Loop Gain)
Negative-shunt feedback ro ro
1 + Loop Gain
Positive-series feedback ro ro(1- Loop Gain)
Positive-shunt feedback ro ro
1 - Loop Gain
Obviously, the loop gain must be less than unity for positive feedback.
How do you identify Shunt and Series Feedback?

For a single input port, the circuit variables associated with the input port should be able
to be expressed as,
Input Variable to the Feedback Loop = Signal variable to the circuit – Feedback variable
1.) Series feedback:
Vin = Vsig -Vfb
+ +
Vsig Vin
+ +
− − Vin
− Vfb + Vsig −
+
− Vfb −
Feedback Loop −
061221-02
2.) Shunt feedback:

Iin = Isig -Ifb
Iin
Ifb
Isig Ifb
Isig Iin
Feedback Loop
061221-03

Increasing the Output Resistance of a Current Sink/Source

In order to increase the output resistance, use negative series feedback because,
rout (with feedback) = rout(without feedback) x [1 + Loop gain]
Circuit:
iOUT
How does it work?
+
M2
1.) Assume iout increases.
+v
VGG
GS - + v
OUT 2.) As a result, vS increases.
R vS
- - 3.) Since the gate is held constant at VGG, then vGS decreases.
Fig. 280-08
4.) The decrease in vGS causes iOUT to decrease opposing the
original increase
Loop Gain?
iOUT' iOUT
iOUT’ = gmvS = gmRiOUT
+ iOUT’
M2 Loop gain = i = gmR
OUT
iOUT
M2' + vOUT rout(w.fb.) = rout(w/o fb.)x [1+gmR] = rds(1+gmR)
VGG vS
R
- - If gmR >>1, then rout(w. fb.) gmrdsR
Fig. 280-09
Comment: Feedback is a great conceptual tool but a questionable analytical tool.

Increasing the Output Resistance of a Simple MOS Current Sink

Small signal model for calculating the iOUT iout
output resistance for the cascode M2 + +

gmvgs2 gmbsvbs2 rds2
current sink:
vOUT + vout
VGG
R R vs2
- vg2 = vb2 = 0 - -
Loop equation: Fig. 280-10
vout = (iout-gm2vgs2-gmbs2vbs2)rds2 + ioutR

= iout(rds2+R) - gm2rds2vgs2 - gmbs2rds2vbs2
But,
vgs2 = 0 - vs2 = -ioutR and vbs2 = 0 - vs2 = -ioutR
Therefore,
vout = iout[rds2 + R + gm2rds2R + gmbs2rds2R]
or
vout
rout = iout = rds2 + R + gm2rds2R + gmbs2rds2R gm2rds2R = μ2R (μ = gmrds)
A general principle emerges:
The output resistance of a cascode circuit R x (Common source voltage gain of the
cascoding transistor)
MOS Cascode Current Sink

iout
iOUT
+
M2 + gm2vgs2 gmbs2vbs2 rds2
M1 vOUT vout
VGG2 +
VGG1 gm1vgs1 rds1 vs2
- - -
vgs1 =vg2 = vb2 = 0
Fig. 280-11
Small signal output resistance:

Noting that vgs1 = vg2 = vb2 = 0 and writing a loop equation we get,
vout = (iout - gm2vgs2 - gmbs2vbs2)rds2 + rds1iout
However,
vgs2 = 0 - vs2 = -ioutrds1 and vbs2 = 0 - vs2 = -ioutrds1
Therefore,
vout = iout[rds1 + rds2 + gm2rds1rds2 + gmbs2rds1rds2]
or vout
rout = iout = rds1 + rds2 + gm2rds1rds2 + gmbs2rds1rds2 gm2rds1rds2 = μ2rds1
Comments:
1.) Same as before if R = rds1 2.) Bulk effects have little influence.
Design of VGG1 and VGG2
M2 +
+ VDS2 ≥VDS2(sat)
VGS2 − vOUT(min) = VDS1(sat)+VDS2(sat)
− +
VGG2
VDS1= VDS1(sat)
VGG1 −
060527-06
1.) VGG1 is selected to provide the desired current. M1 is assumed to be in saturation.

2.) VGG2 is selected to keep VDS1 as small as possible and still be in saturation.
VGG2 = VDS1(sat) + VGS2 = VDS1(sat) + VT + VDS2(sat)
If W1/L1 = W2/L2, then VGG2 = 2VDS(sat) + VT = 2VON + VT
Thus, for the previous NMOS current sink, VGG2 would be equal to,
VGG2 = 2(0.426) + 0.7 = 1.552V

;;
Simulation of the Cascode CMOS Current Sink
Example 120
;;
Slope = 1/Rout
Use the model parameters 100
KN’=110μA/V2, VT = 0.7 and N =
;;
80 All W/Ls are iOUT
0.04V-1 to calculate (a) the small-
iOUT (μA)
10μm/1μm +
;;
signal output resistance for the simple 60 VGG2 =
current sink if IOUT = 100μA and (b) 1.552V vOUT
;;
the small-signal output resistance for 40
the cascode current sink with IOUT = VGG1 =
;;
-
20 1.126V
100μA. Assume that all W/L values Vmin
are 1. 0
0 1 2 3 4 5
vOUT (Volts) Fig. 280-12
Solution
(a) Using = 0.04 V-1 and IOUT = 100μA gives rds1 = 250k = rds2. (b) Ignoring the
bulk effect, we find that gm1 = gm2 = 469μS which gives rout = (250k)(469μS)(250k)
= 29.32M.
High-Swing Cascode Current Sink
VDD VDD
Since
iOUT iOUT
2ID VMIN
VON = K’(W/L) , M4
1/1
M2 + +
1/4 VON
+ +
then if L/W of M4 is VT+VON - vOUT
VT+2VON M3 -
quadrupled, then M1 +
1/1 VON
VON is doubled. + -
VT+VON 1/1 -
-
VMIN = 2VON. -
2VON vOUT
0
060527-07
Example
Use the cascode current sink configuration above to design a current sink of 100μA
and a VMIN = 1V. Assume the device parameters of Table 3.1-2.
Solution
With VMIN = 1V, choose VON = 0.5V. Assuming M1 and M2 are identical gives
W 2·IOUT 2·100x10-6 W1 W2 W3 W4
L K’·V 2 110x10-6x0.25 = 7.27 L1 = L2 = L3 = 7.27 and L4 = 1.82
= =
ON
Improved High-Swing Cascode Current Sink

Because the drain-source voltages of the VDD VDD
matching transistors, M1 and M3 are not equal,
iOUT IREF. R1 R2
iOUT
+
M4 M5 M2 + +
VT 1/1 VON
To circumvent this problem the cascode 1/4 + 1/1 +
- VT+VON -
current sink shown is utilized: + M3 - vOUT
VT+2VON M1 +
VON + VON
Note that the drain-source voltage of M1 and 1/1 VT+VON 1/1
- - - - --
M3 are identical causing iOUT to be a
060527-08
replication of IREF.
Design Procedure
1.) Since VMIN = 2VON = 2VDS(sat), let VON = 0.5VMIN.
2IREF W1 W2 W3 W5 2IREF 8IREF
2.) VON = K’(W/L) = = = = =
L1 L2 L3 L5 K’V 2 K’V 2 ON MIN
W4 2IREF 2IREF IREF
3.) L4 = = =
K’(VGS4-VT)2 K’(2VON)2 2K’VON2
Signal Flow in Transistors

The last example brings up an interesting and important point. This point is illustrated
by the following question, “How does IREF flow into the M3-M5 combination of
transistors since there is no path to the gate of M5?”
Consider how signals flow in transistors:
Output Only Output Only
D C
- + - +
+ +
Input Input
G Only B
Only
+ +
+ + + + VDD
S E
Fig. 4.3-12B
IREF
Answer to the above question:
As VDD increases (i.e. the circuit begins to operate),
IREF cannot flow into the drain of M5, so it flows through M5
the path indicated by the arrow to the gate of M3. It M3 VT +2VON

charges the stray capacitance and causes the gate-source
+
voltage of M3 to increase to the exact value necessary to VGS3
cause IREF to flow through the M3-M5 combination. -
Fig. 4.3-12A
Example 4.3-1 - Design of a Minimum VMIN Current Sink

Assume IREF = 100μA and design a cascode current sink with a VMIN = 0.3V using the
following parameters: VTO=0.7, KP=110U, LAMBDA=0.04, GAMMA=0.4, PHI=0.7
Solution
From the previous equations, we get
W1 W2 W3 W5 8IREF 8·100
L1 L2 L3 L5 K’VMIN 2 = 110·(0.3V)2 = 80.8 and
= = = =
W4 IREF 100
L4 2K’VON 2 = 2·110·0.152 = 20.2
=
120
Simulation Results:
Low Vmin Cascade Current Sink - Method No. 2 100
M1 5 1 0 0 MNMOS W=81U L=1U
M2 2 3 5 5 MNMOS W=81U L=1U 80
iOUT(μA)
M3 4 1 0 0 MNMOS W=81U L=1U
M4 3 3 0 0 MNMOS W=20U L=1U
M5 1 3 4 4 MNMOS W=81U L=1U 60
.MODEL MNMOS NMOS VTO=0.7 KP=110U
+LAMBDA=0.04 GAMMA=0.4 PHI=0.7 40
VDD 6 0 DC 5V
IIN1 6 1 DC 100U
IIN2 6 3 DC 100U 20
VOUT 2 0 DC 5.0 VMIN
.OP 0
.DC VOUT 5 0 0.05 0 1 2 3 4 5
.PRINT DC ID(M2) vOUT(V) Fig. 290-06
.END
Self-Biased Cascode Current Sink†

The VT + 2VON bias voltage is developed through a series VDD
resistor.
IREF
VT+2VON
Design procedure: +
Same as the previous except VON R
VON VMIN - VT+VON iOU
R = IREF = 2IREF + M3 M4
VT
For the previous example, -
0.3V + M1 M2 +
R = 2·100μA = 1.5k VON VON
- -
Fig. 290-
†
T.L. Brooks and A.L. Westwick, “A Low-Power Differential CMOS Bandgap Reference,” Proc. of IEEE Inter. Solid-State Circuits Conf., Feb.
1994, pp. 248-249.
MOS Regulated Cascode Sink†

VDD
iD3
M5 iOUT
VGS3(max)
Increasing vGS3
M7 M6
IREF
+
IREF VGS3(norm)
A M3
VO1
vOUT
IREF M4
M1 M2
- vDS3
VDS3(min) VDS3(sat)
Fig. 290-08
Comments:
• Achieves very high output resistance by increasing the loop gain due to the M4-M5
inverting amplifier.
gm4 gm3rds2gm4rds4 rds3gm3rds2gm4rds4

LG = gm3rds2gds4+gds5

2 If rds4rds5, then rout 2
• M3 maintains “constant” current even though it is no longer in the saturation region.
Assume an iOUT increase vS3 increase vGS4 increase
vG3 decrease Large decrease in vGS3 Large decrease in iOUT
†
E. Sackinger and W. Guggenbuhl, “A Versatile Building Block: The CMOS Differential Difference Amplifier,” IEEE J. of Solid-State Circuits,
vol. SC-22, no. 2, pp. 287-294, April 1987.
Regulated Cascode Current Sink - Continued

Small signal model:
D2=
Solving for the output resistance: S3= iout
G3=D4=D5 G4 g v
iout = gm3vgs3 + gds3(vout-vgs4) + vgs3 -
+
m3 gs3
D3 +
But rds5 rds4 rds2 v vout
gs4 r
gm4vgs4 ds3 -
vgs4 = ioutrds2 -
S2 = G2= S4 Fig. 290-09
and
vgs3 = vg3 - vs3 = -gm4(rds4||rds5)vgs4 - vgs4 = -rds2[1 + gm4(rds4||rds5)]iout
iout = -gm3rds2[1 + gm4(rds4||rds5)]iout + gds3vout - gds3rds2iout
vout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(rds4||rds5)]iout
vout
rout = iout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(rds4||rds5)]
rds3gm3rds2gm4(rds4||rds5)
If IREF = 100μA, all W/Ls are 10μm/1μm we get rds = 0.25M and gm = 469μS which
gives
rout (0.25M)(469μS)(0.25M)(469μS)(0.125M) = 1.72G

Regulated Cascode Current Sink - Continued

VMIN:
Without the use of the VO1 battery shown, VMIN is pretty bad. It is,
VMIN = VGS4 + VDS3(sat) = VT + 2VON
Minimizing VMIN:
If VO1 = VT , then VMIN = 2VON. This is accomplished by the following circuit:
VDD VDD VDD
iOUT
IREF
+IB
ID4A IB
M3 + +
If VGS4A - VGS4B = VDS2(sat) = VON,
VDS2
-
then VMIN = 2VON
M4A M4B
+ + vOUT 2ID4 2IB 2IB+2IREF
VGS4AVGS4B IB
- - IREF+IB
KN’(W4A/L4A) - KN’(W4B/L4B) = KN’(W2/L2)
M1 M2 +
VDS2
- -
ID4 IB IB+IREF
or W4A/L4A - W4B/L4B = W2/L2
Fig. 290-10
A number of solutions exist. For example, let IB = IREF. This gives ID4A = 5.824IREF
assuming all W/L ratios are identical.
Example 4.3-4 - Design of a Minimum VMIN Regulated Cascode Current Sink

Design a regulated cascode current sink for 100μA and minimum voltage of VMIN =
0.3V.
Solution
Let the W/L ratios of M1 through M5 be equal and let IB = 10μA. Therefore,
2·100μA 2·110μA
VMIN = 0.3V = VON3 + VON2 = 110μA/V2(W/L) + 110μA/V2(W/L)
2·100μA
= 110μA/V2(W/L) 1 + 1.1 +5V +5V +5V
Therefore, 110μA 186μA 10μA iOUT

2·100μA M3 +
0.3V = 110μA/V2(W/L)(2.049) 85/1
M4A M4B
W 2·100μA·2.0492
L = 110μA/V20.32 = 84.8 85. 85/1 85/1
10μA vOUT
With IB = 10μA, then ID4A = M1 M2 110μA
2
10 + 110 = 186μA
85/1 85/1
-
Fig. 290-11

Comparison of the MOS Cascode and Regulated Cascode Current Sink

Close examination in the knee area reveals interesting differences.
Simulation results:
110
105
BJT Cascode
100 MOS Cascode
Regulated
iOUT (μA)
95 MOS
Cascode
90
85
80
0 0.1 0.2 0.3 0.4 0.5
vOUT (V) Fig. 290-12
Comments:
• The regulated cascode current is smaller than the cascode current because the drain-
source voltages of M1 and M2 are not equal.
• The regulated cascode current sink has a smaller VMIN due to the fact that M3 can have
a drain-source voltage smaller than VDS(sat)
Summary of Current Sinks and Sources

Current Sink/Source rOUT VMIN
Simple MOS Current Sink 1
rds = D VDS(sat) =
VON
Simple BJT Current Sink VA VCE(sat)
ro = C
0.2V
Cascode MOS gm2rds2rds1 2VON
Cascode BJT Fro 2VCE(sat)
Regulated Cascode Current Sink rds3gm3rds2gm4(rds4||rds5) VT +VON
Minimum VMIN Regulated rds3gm3rds2gm4(rds4||rds5) VON
Cascode Current Sink

SECTION 4.4 - CURRENT MIRRORS

INTRODUCTION
What is a Current Mirror?
A current mirror replicates the input current of a current sink or current source as an
output current. The output current may be identical to the input current or can be a scaled
version of it.
VDD VDD VDD VDD
IIN IOUT = KIIN

iIN iOUT = KiIN
iin iout
iIN iOUT
Current Current
Mirror Mirror
060528-01
The above current mirrors are referenced with respect to ground. Current mirrors can
also be referenced with respect to VDD and current sink inputs and outputs.
Characterization of Current Mirrors

A current mirror is basically nothing more than a current amplifier. The ideal
characteristics of a current amplifier are:
• Output current linearly related to the input current, iout = Aiiin
• Input resistance is zero
• Output resistance is infinity
Also, the characteristic VMIN applies not only to the output but also the input.
• VMIN(in) is the range of vin over which the input resistance is not small
• VMIN(out) is the range of vout over which the output resistance is not large
iin iout iout
Graphically:
iin iout Slope Slope = 1/Rout
+ Current + = 1/Rin
vin vout Ai
- Mirror -
1
vin iin vout
VMIN(in) VMIN(out)
Input Characteristics Transfer Characteristics Output Characteristics
Fig. 300-01
Therefore, Rout, Rin, VMIN(out), VMIN(in), and Ai will characterize the current mirror.

Gate-Source Matching Principle

iD1
A. If the gate-source voltages of two or more transistors M1 M2
iD2
are equal and the transistors are matched and operating W1 W2
L1 + + L2
in the saturation region, then the currents are related by
vGS1 vGS2
the W/L ratios of the individual transistors. The gate-
- -
source voltages may be directly connected or implied. Fig. 290-02
K’W1 2K’iD1
iD1 = 2L1 (vGS1-VT1)2 (vGS1-VT1)2 = (W1/L1)
K’W2 2K’iD2
iD2 = 2L2 (vGS2-VT2)2 (vGS2-VT2)2 = (W2/L2)

W2 W1 W1/L1 iD1
If vGS1 = vGS2, then L2 iD1 = L1 iD2 or
iD1 = W2/L2 iD2

W1
+ L1
B. If the drain currents of two or more transistors are equal and the trans- vGS1
istors are matched and operating in the saturation region, then the gate- -
iD2
source voltages are related by the W/L ratios (ignoring bulk effects). M2
W2
W2/L2 + L2
vGS2
If iD1 = iD2, then vGS1 = VT1 + W1/L1 (vGS2 - VT2) -
Fig. 290-03
or
if W2/L2 = W1/L1, then vGS1 = vGS2 (Note: VDS1must equal VDS2 for ideal results)
MOSFET CURRENT MIRRORS

Simple MOS Current Mirror
iI iO
+ M1 M2 +
vDS1 + vDS2
- -
vGS -
-
Fig. 300-02
Assume that vDS2 > vGS - VT2, then
iO
L1W2
VGS-VT221 + vDS2
K2’
iI =
W1L2
VGS-VT1 1 + vDS1
K1’
If the transistors are matched, then K1’ = K2’ and VT1 = VT2 to give,
iO
L1W2
1 + vDS2
iI =
W1L2
1 + vDS1
If vDS1 = vDS2, then
iO
L1W2
iI =
W1L2
Therefore the sources of error are 1.) vDS1 vDS2 and 2.) M1 and M2 are not matched.
Influence of the Channel Modulation Parameter,

If the transistors are matched and the W/L ratios are equal, then
iO 1 + vDS2
iI = 1 + vDS1
if the channel modulation parameter is the same for both transistors (L1 = L2).
Ratio error (%) versus drain voltage difference:
8.0 λ= 0.02
− 1 ⎥ × 100 %
Note that one could use this effect to 7.0 Ratio Error vDS2 - vDS1 (volts)
measure . 6.0 λ= 0.015
⎤
⎦
5.0
Measure VDS1,VDS2, iI and iO and
⎣ 1 + λ vDS1
1 + λ vDS2
4.0 λ= 0.01
solve the above equation for the channel
modulation parameter, .
Ratio Error ⎡
⎢
3.0
2.0
1.0 vDS1 = 2.0 volt
0.0
0.0 1.0 2.0 3.0 4.0 5.0
Fig. 300-03 vDS2 - vDS1 (volts)
Influence of Mismatched Transistors

Assume that vDS1 = vDS2 and that K1’ K2’ and VT1 VT2. Therefore we have
iO K2’(vGS - VT2)2
iI = K ’(v - V )2
1 GS T1
How do you analyze the mismatch? Use plus and minus worst case approach. Define
K’ = K’2-K’1 and K’ = 0.5(K2’+K1’) K1’= K’-0.5K’ and K2’= K’+0.5K’
VT = VT2-VT1 and VT = 0.5(VT1+VT2) VT1 =VT -0.5VT and VT2=VT+0.5VT
Substituting these terms into the above equation gives,
K’

VT
2
iO (K’+0.5K’)(vGS - VT - 0.5VT )2 1 +

1 -
2K’ 2(vGS-VT)

iI = (K’-0.5K’)(v - V + 0.5V )2 = K’

VT
2
GS T T 1 -
2K’
1 + 2(vGS-VT)

Assuming that the terms added to or subtracted from “1” are smaller than unity gives
iO K’
K’
VT
2 VT
2 K’ 2 VT
iI 1 + 2K’ 1 + 2K’ 1 - 2(vGS-VT) 1 - 2(vGS-VT)
1 + K’ - (vGS-VT)

Assume K’/K’ = ±5% and VT/(vGS-VT) = ±10%.

iO/iI 1 ± 0.05 ±(-0.20) = 1 ± (0.25) ±15% error if tolerances are correlated.
Illustration of the Offset Voltage Error Influence

Assume that VT1 = 0.7V and K’W/L = 110μA/V2.
iI = 1μA
16.0
14.0
Ratio Error ⎡ O − 1 ⎤ × 100 %

12.0
⎥
⎦
10.0 iI = 3μA
⎣ ii
i
⎢ 8.0
iI = 5μA
6.0
iI = 10μA
4.0
2.0 iI = 100μA
0.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
ΔVT (mV) Fig. 300-4
Key: Make the part of VGS causing the current to flow, VON, more significant than VT.
Influence of Error in Aspect Ratio of the Transistors

Example 1 - Aspect Ratio Errors in Current Mirrors
Figure 4.4-4 shows the layout of a one-to-four current amplifier. Assume that the lengths
are identical (L1 = L2) and find the ratio error if W1 = 5 ± 0.1 μm. The actual widths of the
two transistors are
W1 = 5 ± 0.1 μm and W2 = 20 ± 0.1 μm
iI iO
Solution i i O I
;;;;;;;;;;
M2 M1
We note that M1 M2
+ +
the tolerance VDS1 VDS2
+
is not multi- GND
-
VGS
-
plied by the -
nominal gain Fig. 300-5
factor of 4.
The ratio of W2 to W1 and consequently the gain of the current amplifier is
iO W2 20 ± 0.1 1 ± (0.1/20)
0.1 ±0.1
0.1 ±0.4
= =
iI W1 5 ± 0.1 = 4 41 ±
1 ± (0.1/5)
1 -
20 41 ±
5 20 - 20 = 4 - (±0.03)
where we have assumed that the variations would both have the same sign (correlated). It
is seen that this ratio error is 0.75% of the desired current ratio or gain.
Influence of Error in Aspect Ratio of the Transistors-Continued

Example 2 - Reduction of the Aspect Ratio Errors in Current Mirrors
Use the layout technique illustrated in Fig. 4.4-5 and calculate the ratio error of a current
amplifier having the specifications of the previous example.
Solutions
The actual widths of M1 and M2 are
W1 = 5 ± 0.1 μm and W2 = 4(5 ± 0.1) μm
The ratio of W2 to W1 and consequently the current gain is given below and is for all
practical purposes independent of layout error.
iO 4(5 ± 0.1)
iI = 5 ± 0.1 = 4
;;;;;; ; ;
iI iO
;;;;;; ; ;
M2a M2b M1 M2c M2d iI iO
;;;;;; ; ; M1 M2
;;;;;; ; ;
GND
GND
Fig. 300-6
Summary of the Simple MOS Current Mirror/Amplifier

• Minimum input voltage is VMIN(in) = VT+VON
Okay, but could be reduced to VON.
Principle:
VDD
M5 M6 M7
Ib Ib
Ib
M3 M4
iI iO
iI VT iO VT
+ M1 M2
VON +
+ M1
VON + M2 - VT+VON Ib
- VT+VON
- -
Fig. 300-7
Will deal with later in low voltage op amps.
• Minimum output voltage is VMIN(out) = VON
1
• Output resistance is Rout = ID
1
• Input resistance is Rin gm
• Current gain accuracy is poor because vDS1 vDS2
Large Output Swing Cascode Current Mirror

VDD VDD VDD
IIN IOUT
R iin iout
D5=G3
M4 M5 M2 +
1/1 rds5
1/4 1/1 gm5vgs5
M3 M1 iin vin
D3=S5 +
1/1 1/1 gm3vgs3
rds3 vs5
= gm3vin
- S3=G5 -
060528-02
• Rout gm2rds2rds1
• Rin = ? vin = rds5(iin-gm5vgs5)+vs5 = rds5(iin +gm5vs5)+vs5 = rds5iin+(1+gm5rds5)vs5
But, vs5 = rds3(iin - gm3vin)
vin = rds5iin + (1+gm5rds5)rds3iin - gm3rds3(1+gm5rds5)vin
vin rds5 + rds3 + rds3gm5rds5 1
Rin = iin = gm3rds3(1+gm5rds5) gm3
• VMIN(out) = 2VON
• VMIN(in) = VT + VON
• Current gain is excellent because vDS1 = vDS3.
Self-Biased Cascode Current Mirror

VDD VDD
I1 I2
iin iout
+ iin R
R gm3vgs3
• Rin = ? + +
M3 M4
vin = iinR + rds3(iin-gm3vgs3) vin rds3
+
vin v2
+ rds1(iin-gm1vgs1) M1 M2 gm1vgs1 v1 rds1
-
But, - - -
vgs1 = vin-iinR
Self-biased, cascode current mirror Small-signal model to calculate Rin.
and Fig. 310-03
vgs3 = vin-rds1(iin-gm1vgs1) = vin-rds1iin+gm1rds1(vin-iinR)

vin = iinR+rds3iin-gm3rds3[vin-rds1iin+gm1rds1(vin-iinR)]+rds1[iin-gm1(vin+iinR)]
vin[1+gm3rds3+gm1rds1gm3rds3+gm1rds1]
= iin[R+rds1+rds3+gm3rds3rds1+ gm1rds1gm3rds3R]
R + rds1 + rds3 + gm3rds3rds1 + gm1rds1gm3rds3R 1
Rin = 1 + gm3rds3 + gm1rds1gm3rds3 + gm1rds1 gm1 + R
• Rout gm4rds4rds2
• VMIN(in) = VT + 2VON •VMIN(out) = 2VON • Current gain matching is excellent
MOS Regulated Cascode Current Mirror
VDD VDD VDD

IBias
I IO
ii I io
M3
M1
M4 M2
FIG. 310-11
• Rout gm2rds3
1
• Rin g
m4
• VMIN(out) = VT+2VON (Can be reduced to 2VON)
• VMIN(in) = VT+VON (Can be reduced to VON)
• Current gain matching - good as long as vDS4 = vDS2
SUMMARY
Summary of MOS Current Mirrors
Current Accuracy Output Input Minimum Minimum

Mirror Resistance Resistance Output Input
Voltage Voltage
Simple Poor rds 1 VON VT+VON
gm
Wide Output Excellent gmrds2 1 2VON VT+VON
Swing gm
Cascode
Self-biased Excellent gmrds2 1 2VON VT+2VON
Cascode R + gm
Regulated Good- gm2rds3 1 VT+2VON VT+VON
Cascode Excellent gm (min. is (min. is
2VON) VON)

SECTION 4.5 - CURRENT AND VOLTAGE REFERENCES

INTRODUCTION
Characteristics of a Voltage or Current Reference
What is a Voltage or Current Reference?
A voltage or current reference is an independent voltage or current source that has a
high degree of precision and stability.
Requirements of a Reference Circuit:
• Should be independent of power supply
• Should be independent of temperature
• Should be independent of processing variations
• Should be independent of noise and other interference
Reference
Nominal ss
Value Proce
Temperature
Powe
r Sup
060528-03 ply
How Does PVT Influence Voltage and Current References?

1.) Process and temperature – Changes in K’, VT, and will cause the voltage and current
to change.
iD ΔKʼ VDD iD
VDD VDD
R ΔKʼ R IBias ΔVT R
variation variation
ΔIBias + ΔIBias
IBias VBias IBias
VBias VBias
−
vGS
VDD VDD vGS
ΔVBias ΔVT ΔVBias 0600528-04
2.) Power supply –

VDD iD
VDD
R IBias R
+ ΔIBias
VBias IBias
VBias VDD
−
vGS
0600528-05
ΔVBias ΔVDD

VOLTAGE REFERENCES WITH POWER SUPPLY INDEPENDENCE

Power Supply Independence
How do you characterize power supply independence?
Use the concept of:
VREF VREF/VREF VDD VREF
S VDD = VDD/VDD = VREF VDD
Application of sensitivity to determining power supply dependence:
VREF VREF VDD
VREF = S VDD VDD
Thus, the fractional change in the reference voltage is equal to the sensitivity times the
fractional change in the power supply voltage.
For example, if the sensitivity is 1, then a 10% change in VDD will cause a 10% change
in VREF.
VREF
Ideally, we want S V to be zero for power supply independence.
DD
Voltage References using Voltage Division

VDD VDD
R1 M2
+ +
R2 M1 V
VREF REF
- -
Resistor voltage divider. Active device voltage divider. Fig. 370-01

R2 VTN + (P/N) (VDD-|VTP|)
VREF = R1+R2 VDD VREF = 1 + (P/N)
VREF VREF VDD (P/N) VDD (P/N)
S VDD =1 S VDD =VREF 1+ ( / ) = V + ( / ) (V -|V |)
P N TN P N DD TP
VDD (P/N)
=V
TN + (P/N) (VDD-|VTP|)
VREF
Assume N = P and VTN = |VTP| S VDD =1

MOSFET-Resistance Voltage References

VDD
VDD
R
R vout
+
+ R1
VREF VREF
-
R2
-
Fig. 370-03
2(VDD-VREF) This circuit allows VREF to be
VREF = VGS = VT + R
larger. If the current in R1 (and
or R2) is small compared to the
1 2(VDD-VT) 1 current flowing through the
VREF = VT - R + R +
(R)2 transistor, then
VREF
VDD 1

R1 + R2

S VDD = 1 + (VREF-VT)R VREF

VREF R2 VGS

Assume that VDD=5V, W/L =100 and R=100k,
VDD
Thus, VREF 0.7875V and SVREF = 0.0653
Bipolar-Resistance Voltage References

VCC
VCC
R
R vout
+
+ R1
VREF VREF
- R2
-
Fig. 370-04
kT I
VREF = VEB = q ln Is

If the current in R1 (and R2)
VCC VEB VCC is small compared to the
and I = R R current flowing through the
kT VCC
transistor, then
give VREF q ln RIs

R1 + R2
VREF 1 1 VREF R1
VEB
SVCC = ln[VCC/(RIs)] = ln(I/Is)
If VCC = 5V, R = 4.3k and Is = 1fA,
then VREF = 0.719V.
VREF
Also, S V = 0.0362
CC
CURRENT REFERENCES WITH POWER SUPPLY INDEPENDENCE

Power Supply Independence
Again, we want
IREF IREF/IREF VDD IREF
SVDD = VDD/VDD = IREF VDD
to approach zero.
IREF
Therefore, as SVDD
approaches zero, the change in IREF as a function of a change in
VDD approaches zero.
Simple Current Reference

VCC VDD
IIN R IIN R
IOUT IOUT
IC1 ID1
IB1 IB2
Q1 Q2 M1 M2
Fig. 360-02
2IIN
VCC-VBE 1 VDD-VGS VDD - 1 - VT
IOUT IOUT =
R 2 R R
1+ F
IREF IREF
S VCC = 1 SVDD = 1

Gate-Source Referenced Current Reference

The circuit below uses both positive and negative feedback to accomplish a current
reference that is reasonably independent of power supply.
Circuit:
VDD i
K'NW (V 2
I1 = GS1 - VT)
RB M3 M5 2L
M4 Desired
I5
M7 I1 I2 operating
point V
IQ I2 = GS1
M2 R
I6
M6 Undesired
M8 M1 operating
+ point
VGS1 R
Startup - VQ v
0V Fig. 370-06
Principle:
2I1
If M3 = M4, then I1 I2. However, the M1-R loop gives VGS1=VT1 + KN’(W1/L1)
VGS1 VT1 1 2I1
Solving these two equations gives I2 = R = R + R KN’(W1/L1)
VT1 1 1 2VT1 1
The output current, Iout=I1=I2 can be solved as Iout= R + + +
1R2 R 1R (1R)2
Simulation Results for the Gate-Source Referenced Current Reference

120μA
ID1
100μA The current ID2 appears to be okay, why is
80μA
ID2 ID1 increasing?
Apparently, the channel modulation on the
60μA
current mirror M3-M4 is large.
40μA
At VDD = 5V, VSD3 = 2.83V and VSD4 =
20μA 1.09V which gives ID3 = 1.067ID4
0 107μA
0 1 2 3 4 5
VDD Fig. 370-07
Need to cascode the upper current mirror.
SPICE Input File:
Simple, Bootstrap Current Reference
VDD 1 0 DC 5.0 RB 1 6 100KILOHM
VSS 9 0 DC 0.0 .OP
M1 5 7 9 9 N W=20U L=1U .DC VDD 0 5 0.1
M2 3 5 7 9 N W=20U L=1U .MODEL N NMOS VTO=0.7 KP=110U
M3 5 3 1 1 P W=25U L=1U GAMMA=0.4 +PHI=0.7 LAMBDA=0.04
M4 3 3 1 1 P W=25U L=1U .MODEL P PMOS VTO=-0.7 KP=50U
M5 9 3 1 1 P W=25U L=1U GAMMA=0.57 +PHI=0.8 LAMBDA=0.05
R 7 9 10KILOHM .PRINT DC ID(M1) ID(M2) ID(M5)
M8 6 6 9 9 N W=1U L=1U .PROBE
M7 6 6 5 9 N W=20U L=1U .END

Cascoded Gate-Source Referenced Current Reference

VDD
120μA
M3 M4
M5 ID2
M3C MC4
100μA
MC5
RB 80μA
I1 RON I2 I5 ID1
M7 60μA
M2
40μA
M8 M1 20μA
+
VGS1 R
Startup - 0
SPICE Input File: 0V 0 1 2
VDD
3 4 5
Fig. 370-08
Cascode, Bootstrap Current Reference M7 6 6 5 9 N W=20U L=1U
VDD 1 0 DC 5.0 RB 1 6 100KILOHM
VSS 9 0 DC 0.0 .OP
M1 5 7 9 9 N W=20U L=1U .DC VDD 0 5 0.1
M2 4 5 7 9 N W=20U L=1U .MODEL N NMOS VTO=0.7 KP=110U
M3 2 3 1 1 P W=25U L=1U GAMMA=0.4 PHI=0.7 LAMBDA=0.04
M4 8 3 1 1 P W=25U L=1U .MODEL P PMOS VTO=-0.7 KP=50U
M3C 5 4 2 1 P W=25U L=1U GAMMA=0.57 PHI=0.8 LAMBDA=0.05
MC4 3 4 8 1 P W=25U L=1U .PRINT DC ID(M1) ID(M2) ID(M5)
RON 3 4 4KILOHM .PROBE
M5 9 3 1 1 P W=25U L=1U .END
R 7 9 10KILOHM
M8 6 6 9 9 N W=1U L=1U
Base-Emitter Referenced Circuit

VDD
M3 M4 M5
i2 i2=VTln(i1/Is)/R
M6 I
1 Desired i2=i1
I2 I5 operating
point
M1 M2
+
VEB1
Undesired
+ operating
M7 Q1 - point
R VR
Startup
i1
- -
Fig. 370-09
VEB1
Iout = I2 = R
BJT can be a MOSFET in weak inversion.

Low Voltage Gate-Source Referenced MOS Current Reference

The previous gate-source referenced circuits required at least 2 volts across the power
supply before operating.
A low-voltage gate-source referenced circuit:
VDD
M3 M4 VT+VON
VON VT
I1
VT I2
VON
M1 M2
VT+VON
R VR
VSS Fig. 4.5-8A
Without the batteries, VT, the minimum power supply is VT+2VON+VR.

With the batteries, VT, the minimum power supply is 2VON+VR 0.5V
Summary of Power-Supply Independent References

• Reasonably good, simple voltage and current references are possible
• Best power supply sensitivity is approximately 0.01
(10% change in power supply causes a 0.1% change in reference)
Type of Reference VREF IREF

SV or S V
PP PP
Voltage division 1
Simple Current Reference 1
MOSFET-R <1
BJT-R <<1
Gate-source Referenced <<1
Base-emitter Referenced <<1

REFERENCES WITH TEMPERATURE INDEPENDENCE

Characterization of Temperature Dependence
The objective is to minimize the fractional temperature coefficient defined as,
1 VREF 1 VREF
TCF = VREF T =

T S T parts per million per °C or ppm/°C
Temperature dependence of PN junctions:
v

i IsexpVt
1 Is = (ln Is) = 3 + VGO VGO

-V
I T T T TVt TVt
Is = KT3exp Vt
GO

s
dvBE VBE - VGO
dT T = -2mV/°C at room temperature
(VGO = 1.205 V at room temperature and is called the bandgap voltage)
Temperature dependence of MOSFET in strong inversion:
dvGS dVT 2L d iD
dT = dT + WCox dT μo
dvGS - -2.3mV
μo = KT-1.5 dT °C
VT(T) = VT(To) - (T-To)
Resistors: (1/R)(dR/dT) ppm/°C

VDD
Bipolar-Resistance Voltage References
From previous work we know that, R
V
kT DD - VREF +
VREF = q ln RIs

VREF
However, not only is VREF a function of T, but R and Is are also -
Fig. 380-1
functions of T.
dVREF k VDD-VREF kT RIs -1 dVREF VDD-VREF dR dIs
dT = q ln RIs
+ q VDD-VREF
RIs dT - RIs
RdT + IsdT

VREF Vt dVREF dIs VREF-VGO Vt dVREF 3Vt Vt dR

dR
= T - VDD-VREF dT - Vt RdT + IsdT
= T - VDD-VREF dT - T - R dT
VREF-VGO dR 3Vt
dVREF T - Vt RdT - T VREF-VGO dR 3Vt
dT = Vt T - Vt RdT - T
1 + VDD-VREF
1 dVREF VREF-VGO Vt dR 3Vt
TCF = VREF dT = VREF·T - VREF RdT - VREF·T
If VREF = 0.6V, Vt = 0.026V, and the R is polysilicon, then at 27°K the TCF is
0.6-1.205 0.026·0.0015 3·0.026
TCF = 0.6·300 - 0.6 - 0.6·300 = 33110-6-65x10-6-433x10-6 =-3859ppm/°C
MOSFET Resistor Voltage Reference

From previous results we know that VDD
2(VDD-VREF)
VREF = VGS = VT + R R
1 2(VDD-VT) 1
or VREF = VT - R + R + +
(R)2
VREF
Note that VREF, VT, , and R are all functions of temperature. -
It can be shown that the TCF of this reference is
Fig. 380-02
VDD VREF 1.5 1 dR
dVREF + 2R T R dT

dT = 1
1 + 2R (V V )
DD REF
VDD VREF 1.5 1 dR

+
2R T R dT

TCF = 1
VREF(1 + 2R (V V ))
DD REF
Example 4.5-1 - Calculation of MOSFET-Resistor Voltage Reference TCF

Calculate the temperature coefficient of the MOSFET-Resistor voltage reference where
W/L=2, VDD=5V, R=100k using the parameters of Table 3.1-2. The resistor, R, is
polysilicon and has a temperature coefficient of 1500 ppm/°C.
Solution
dR
First, calculate VREF . Note that R = 220x10-6x105 = 22 and RdT = 1500ppm/°C
1 2(5 0.7) 1 2
VREF = 0.7 22 + 22 + 22 = 1.281V
5 1.281 1.5
-6
dVREF 2.3x10-3 +
2(22)

300 1500x10
Now, dT = 1 = -1.189x10-3V/°C
1+
2(22) (5 - 1.281)
The fractional temperature coefficient is given by
1

TCF = 1.189x10-3 1.281 = 928 ppm/°C

Gate-Source and Base-Emitter Referenced Current Source/Sinks

Gate-source referenced source:
VT1 1 1 2VT1 1
The output current was given as, Iout = R + R2 + R 1R + (1R)2
1
Although we could grind out the derivative of Iout with respect to T, the temperature
performance of this circuit is not that good to spend the time to do so. Therefore, let us
assume that VGS1 VT1 which gives
VT1 dIout 1 dVT1 1 dR
Iout R dT = R dT - R2 dT
In the resistor is polysilicon, then
1 dIout 1 dVT1 1 dR - 1 dR -2.3x10-3
TCF = Iout dT = VT1 dT - R dT = VT1 - R dT = 0.7 -1.5x10-3 = -4786ppm/°C
Base-emitter referenced source:
VBE1
The output current was given as, Iout = I2 = R
1 dVBE1 1 dR
The TCF = VBE1 dT - R dT
1
If VBE1 = 0.6V and R is poly, then the TCF = 0.6 (-2x10-3) - 1.5x10-3 = -4833ppm/°C.
Technique to Make gm Dependent on a Resistor

Consider the following circuit with all transistors having a VDD
W/L = 10. This is a bootstrapped reference which creates a
Vbias independent of VDD. The two key equations are: M3 M4
I3 = I4 I1 = I2
and M2D
M1
VGS1 = VGS2 + I2R +
M2A
Solving for I2 gives: M2B M2CV
Bias
VGS1-VGS2 1 2I1 2I2 2I1 1 R=5kΩ -
I2 = R = R ß1 - ß2 = R ß1 1 - 2

Fig. 4.5-11
1 1 1
I2 = R 2ß I2 = I1 = = = 18.18μA
1 2ß1R2 2·110x10-6·10·25x106
Now, Vbias can be written as
2I2 1 1
Vbias=VGS1= ß1 +VTN = ß1R+VTN = + 0.7 = 0.1818+0.7=0.8818V
110x10 ·10·5x103
-6
Any transistor with VGS = Vbias will have a current flow that is given by 1/2ßR2.
2ß 1 1
Therefore, gm = 2Iß = 2 = R gm = R
2ßR
Summary of Reference Performance

VREF
Type of Reference S VDD TCF Comments
MOSFET-R <1 >1000ppm/°C

BJT-R <<1 >1000ppm/°C
Gate-Source Good if currents >1000ppm/°C Requires start-
Referenced are matched up circuit
Base-emitter Good if currents >1000ppm/°C Requires start-
Referenced are matched up circuit
• A MOSFET can have zero temperature dependence of iD for a certain vGS
• If one is careful, very good independence of power supply can be achieved
• None of the above references have really good temperature independence
Consider the following example:
A 10 bit ADC has a reference voltage of 1V. The LSB is approximately 0.001V.
Therefore, the voltage reference must be stable to within 0.1%. If a 100°C change in
temperature is experienced, then the TCF must be 0.001%/C or multiplying by 104
requires a TCF = 10ppm/°C.
SECTION 4.6 - BANDGAP REFERENCES

Temperature Stable References
• The previous reference circuits failed to provide small values of temperature coefficient
although sufficient power supply independence was achieved.
• This section introduces the bandgap voltage concept combined with power supply
independence to create a very stable voltage reference in regard to both temperature and
power supply variations.
Bandgap Voltage Reference Principle
The principle of the bandgap VDD
voltage reference is to balance VBE
the negative temperature I1 -2mV/°C
coefficient of a pn junction with
the positive temperature T
coefficient of the thermal voltage, VREF = VBE + KVt
+ Σ
Vt = kT/q. VBE tV
-
+0.085mV/°C
Concept:
T KVt
Result: References with TCF’s Vt = kT

q K
Fig. 390-01
approaching 10 ppm/°C.
Voltage and Current Proportional to Absolute Temperature (PTAT)

How do you create a voltage and current whose temperature is proportional to absolute
temperature?
VDD VDD
Creation of a PTAT voltage:
I1 I2 I1 I2
VD = VD1 – VD2 = Vt ln Is1 - Vt ln Is2 + −
ΔVD
I1 Is2 Is2 A A
= Vt ln I2 = V ln = V ln 2 = kT ln 2 D1
A1
D2
A2
Is1 t Is1 t A1 q A1
060529-02
if I1 = I2.
Creation of a PTAT current (superimpose VD across a VDD VDD VDD
resistor):
VD1 + VGS1 - VGS2 - VD2 Μ3 Μ5
IR = IPTAT = I1 Μ4 I2
R
IPTAT
If VGS1 = VGS2, then Μ1 Μ2
+ +
VGS1 VGS2
kT A2 − −
IPTAT = Rq ln A1 R IPTAT
D1
A1 D2
Note: All currents flowing in the upper mirror are PTAT. A2
060529-03
True PTAT Current

In the previous slide, the PTAT current is divided by a resistor that will introduce a
temperature dependence.
The following circuit uses the zero temperature coefficient operation of a MOSFET to
obtain a true PTAT current: VDD VDD VDD
kT A2
IPTAT’ = R1q ln A1 Μ3 Μ5
I1 Μ4 I2
VGS6(ZTC) = IPTAT’ R2 IPTATʼ IPTAT
Μ1 + + Μ2
R2 kT A2 VGS1 VGS2
= R1 q ln A1 − − + M6
R1 IPTATʼ
D1 VGS6(ZTC)
A1 D2 R2
R2 A2 −
The temperature influence of R1 is given as 060529-10
d(R2/R1) 1 dR2 R2 dR1 R2 1 dR2 1 dR1

dT = R1 dT - R 2 dT = R1
R2 dT - R1 dT
1
which has no temperature influence if R1 and R2 have the same temperature coefficient.
Since the drain current of M6 does change with temperature, the current is truly PTAT.
Voltage Complementary to Absolute Temperature (CTAT)

A complementary to absolute temperature function is one that is T-1.
One way of creating this voltage is shown below. VDD
It can be shown, that vD(T) can be given as,
T T kT T0 kT JD IPTAT

vD(T) = V GO1 - T0 + vD0T0 + q ln T + q lnJD0
+
where, vD
−
VGO = bandgap voltage of silicon (1.205V) 060529-04
T0 = a reference temperature about which T varies
= a temperature coefficient for the pn junction saturation current ( 3)
JD = pn junction current density
kT T0
In the above expression for vD(T) the term q ln T is not linear with T!!
This term will create a problem called “bandgap curvature problem” because a perfectly
linear PTAT function cannot be cancelled by a term that is not truly CTAT.
Value of the CTAT Slope

Differentiating vD(T) with respect to T and assuming that the current flowing through the
pn junction is PTAT, gives,
VD | VD0 - VGO k
VD0 - VGO Vt0
T T=T0 = T0 + ( - )q =

T0 + ( - ) T0
where
= temperature dependence of JD ( = 1 for PTAT current flowing
through the pn junction)
Typical values of and are 1 and 3.2. If VD0 = 0.6V, then at room temperature:
VD | 0.6-1.205 0.026
0.6-1.205-0.1092
T T=T0 = 300 + (1-3.2) 300 = 300 = -1.826mV/°C

Setting Up the Bandgap Relationship

The bandgap voltage is expressed as
kT A2
VREF = VD + K"VD = VD + K" q ln A1 = VD + KVt
where
J
A2
D1
K = K" ln J
D2 = K" ln A1, gives

In order to achieve a zero temperature coefficient at T = T0, the following equation must
be satisfied:
dVREF VD | (VD)
dT = T T=T0+ K" = 0
Therefore, we get
V
t0
J
D1 VD0 - VGO ( - )Vt0
0 = K" T0 lnJD2 + T0 + T0

Vt0
VD0 - VGO ( - )Vt0
0 = K T0 +

T0 + T0
VGO - VD0 - Vt0(-)
Solving for K gives K= Vt0
The Bandgap Reference Voltage

Assuming that JD1/JD2 = A1/A2 = 10 and VD0 = 0.6V gives,
1.205 - 0.6 + (2.2)(0.026)
K= 0.026 = 25.469
The output voltage of the bandgap voltage reference is found as,
|
VREFT=T0 = VD0 + KVt0 = VD0 + VGO - VD0 + (-)Vt0 or VREF = VGO + (-)Vt0
For the previous values, VREF = 1.205 + 0.026(2.2) = 1.262V.
This value is very close to the bandgap voltage VGO = 1.205V and is the reason this
reference is called the “bandgap voltage reference”.

Variation of the Bandgap Reference Voltage with respect to Temperature

The previous derivation is only valid at a given temperature, T0. As the temperature
changes away from T0, the value of VREF/T is no longer zero.
Illustration:
VREF(V)
1.290 VREF
=0
T0 = 400°K T
1.280
1.270 VREF= 0
T T0 = 300°K
1.260
VREF= 0 1.250
T0 = 200°K
T
1.240
T°C
-60 -40 -20 0 20 40 60 80 100 120
Fig. 4.6-3
Bandgap curvature correction will be necessary for low ppm/°C bandgap references.
Examples of the Classical Bandgap Voltage Reference

1.) Classical bandgap voltage reference using BJTs. VDD

VBE1 - VBE2 V I I
t
1
2
I2 = R2 = R ln I - ln I
2

s1

s2
VT+
Vt I

s2 Vt A

E2 2VDS(sat) M1 M2
= R2 ln I

s1 = R2 ln A

E1
Since I1 = I2 which is forced by the current mirror, then I1 M3 M4 I2

R1
AE2
VREF = VBE1 + I1R1 = VBE2 +
R2 ln
AE1 Vt +
R1
= VBE1 + KVt
Q1 Q2
While an op amp could be used to make I1 = I2 it VREF AE1 AE2
suffers from offset and noise and could lead to
deterioration of the bandgap temperature performance.
− R2
060529-05

Examples of the Classical Bandgap Voltage Reference - Continued

2.) Classical bandgap voltage reference using VDD
pn junctions.
Operation: VT+
2VDS(sat) M6 M7 M8
The current mirror (M3-M8) keeps the
currents in D1, D2, and D3 identical. M3 M4 M5
Thus, I1 I2 I3
M1 M2
VD1 = I2R + VD2 +
or R kR
D1 VREF
Vt x1
D2 D3 −
I3 = I2 = R ln(n) xn xn
060529-06
Therefore,
VREF = VD3 + I3(kR) = VD3 + kVt·ln(n)
Use k and n to design the desired value of K (n is an integer greater than 1).
Weak Inversion Bandgap Voltage Reference

Circuit: VDD
+
ID6
VR1 R1
Analysis: - M6
For the p-channel transistors: + +

V -V -V M2 M4
BG
BS BD R2 VR2
ID = IDO(W/L) exp nVt exp Vt - exp Vt

ID1=ID2 ID3=ID4 -
VREF
where Vt = kT/q. M1 M3
V Q5
BG VBS
If VBD >> Vt, then ID = IDO(W/L) exp nVt - Vt . -
Fig. 390-07
The various transistor currents can be expressed as:
V V
BG2 BG4 VBS4
ID1 = ID2 = IDO(W2/L2) exp nVt and ID3 = ID4 = IDO(W4/L4) exp nVt - Vt
Note that VBG2 = VBG4 and VBS4 = VR1.
Therefore,

ID1 W2/L2 VR1
ID3 = W4/L4 exp
Vt
which gives
W W L L VR1
1 4 2 3
VR1 = Vt ln L1L4W2W3 and IR1 = R1
Weak Inversion Bandgap Voltage Reference - Continued

The reference voltage can be expressed as,
VREF = R2I6 + VBE5
However,
W6L2 W6L2 Vt W W L L

1 4 2 3
I6 = L6W2 IR1 = L6W2 R1 ln
L1L4W2W3 .
Substituting I6 and the previously derived expression for VBE(T) in VREF gives,
W6L2 R2 W W L L T T T

1 4 2 3

0
VREF = L6W2 R1 Vt ln
L1L4W2W3 + VGO
1 - T0 + VBE0
T0 + 3Vt ln
T
To achieve VREF/T = 0 at T = T0, we get
VREF
k
R2
W6L2
W1W4L2L3 VGO VBE0 3k
T =
q
R1
L6W2 ln
L1L4W2W3 - T0 + T0 + q
Therefore,
R2W6L2
W1W4L2L3 q
R1L6W2 ln
L1L4W2W3 = kT0 (VGO - VBE0) - 3
Under the above constraint, VREF has an zero TCF at T = T0 and has a value of
3kT T

0 3kT
VREF = VGO + q 1 + ln
T = VGO + q
Practical values of VREF/T for the weak inversion bandgap are less than 100 ppm/°C.
Current Complementary to Absolute Temperature

How can one generate a current that is CTAT?
VDD VDD
M3 M4
M4 M5
M5 M6
IPTAT IPTAT
IVBE IVBE or IVD IVD
M2 M3
Q1 + M1 M2
+
VBE R VD R
− −
060529-07
Operation:
The PTAT current creates a voltage drop across the pn junction which provides the
voltage which is CTAT. The negative feedback loop forces all the currents flowing in the
current mirror to have CTAT characteristics.
VBE VD
IVBE = IVD = R = R

Parallel Form of the Bandgap Voltage Reference

The classical form is often called series because it is the summation of a CTAT voltage
and a multiplied PTAT voltage.
The parallel form: VDD VDD
IPTAT IVBE
Vt VBE
If, IPTAT = R1 and IVBE = R2
+
R3 R3 R3 VREF
−
then, VREF = R1Vt + R2VBE 060118-10
R3 kT A2 R3 T T
kT T0 kT JD
VREF = R1 q ln A1 + R2 VGO 1 - T0 + vD0 T0 + q ln T + q ln JD0
Note that it is important that the temperature coefficient of R1, R2, and R3 be identical.
d(R3/R1) 1 dR3 R3 dR1 R3 1 dR3 1 dR1
dT = R1 dT - R 2 dT = R1
R3 dT - R1 dT = 0
1
The advantage of the parallel form is that the bandgap reference voltage can be any value
and the circuitry is compatible with low voltage power supplies.
How Can a Bandgap “Current” Reference be Obtained?

Use a MOSFET under ZTC operation and design the parallel form of the bandgap voltage
reference to give a value of VZTC.
VDD VDD
IPTAT IREF
IVBE
+
R3 VREF =VGS(ZTC)
−
060529-09

Curvature Correction Techniques:

• Squared PTAT Correction:
Temperature coefficient 1-20 ppm/°C VBE
VPTAT
Voltage
• VBE loop
M. Gunaway, et. al., “A Curvature- VPTAT2
Corrected Low-Voltage Bandgap
Reference,” IEEE Journal of Solid- VRef = VBE + VPTAT + VPTAT2
State Circuits, vol. 28, no. 6, pp. 667- Temperature Fig. 400-01
670, June 1993.
• ß compensation
I. Lee et. al., “Exponential Curvature-Compensated BiCMOS Bandgap References,”
IEEE Journal of Solid-State Circuits, vol. 29, no. 11, pp. 1396-1403, Nov. 1994.
• Nonlinear cancellation
G.M. Meijer et. al., “A New Curvature-Corrected Bandgap Reference,” IEEE
Journal of Solid-State Circuits, vol. 17, no. 6, pp. 1139-1143, December 1982.
VBE Loop Curvature Correction Technique

Circuit:
VDD Operation:
3-Output Current Mirror (IVBE+INL) VBE1-VBE2 Vt Ic1A2
VDD IVBE+INL VDD VDD INL = R3 = R3 lnA1Ic2
IPTAT IPTAT
IVBE
Vt 2IPTAT
R3 INL VREF = R3 lnINL+IConstant
IPTAT
Qn1
IConstant where
Qn2 R1
x1 R2 x2 Iconstant = INL + IPTAT + IVBE
Fig. 400-02 Vt VBE
INL + Rx + R2
(a quasi-temperature independent current subject to the TCF of the resistors)
where
Vt = kT/q
Ic1 and Ic2 are the collector currents of Qn1 and Qn2, respectively
Rx = a resistor used to define IPTAT
V
BE Vt 2IPTAT

VREF = R2 + R3 lnINL + Iconstant
+ IPTAT R1
Temperature coefficient 3 ppm/°C with a total quiescent current of 95μA.
ß Compensation Curvature Correction Technique

Circuit: Operation:
Vin BT
BT

VREF = VBE + AT + (1+ß)
R VBE + AT + ß
R
where
I=AT I=BT
A and B are constant
T = temperature
VREF The temperature dependence of ß is
R BT
1+ß ß(T) e-1/T ß(T) = Ce-1/T
Fig. 400-0

BTe1/T

VREF = VBE(T) + AT + C

Not good for small values of Vin.

Vin VREF + Vsat. = VGO + Vsat. = 1.4V
Nonlinear Cancellation Curvature Correction Technique

Objective: Eliminate nonlinear term from the BE. VCC
IConstant
Result: 0.5 ppm/°C from -25°C to 85°C. IPTAT V
VCC = REF
Operation: From above, Q8 R2
VREF = VPTAT + 4VBE(IPTAT) - 3VBE(IConstant) Q4 Q7

IPTAT
Note that, IPTAT Ic T 1 = 1 Q3 Q6
and Iconstant Ic T 0 = 0, Q2 Q5
VBE
Previously we found,
T T VREF Q1 VBE

VBE(T) VGO - T0 VGO-VBE(T0) -( -)Vt ln
T0 R1 VPTAT R2 VREF
VPTAT R1
so that
T T
Conventional Curvature Corrected
VBE(IPTAT) =VGO-T0VGO-VBE(T0)-(-1)Vt ln
T0 Bandgap Reference Bandgap Reference
Fig. 400-04
and
T T

VBE(IConstant) =VGO - T0 VGO -VBE(T0) -Vt ln
T0

Combining the above relationships gives,

VREF(T) = VPTAT + VGO - (T/T0)[VGO - VBE(T0)] - [ - 4] Vt ln
(T/T0)
If 4, then VREF(T) VPTAT + VGO
1 - (T/T0) + VBE(T0)(T/T0)
A Parallel Version of the Nonlinear Curvature Correction Technique

The last idea was good in concept but not appropriate for CMOS implementation. The
following is a possible implementation.
VDD
VDD VDD
VDD VDD Iconst IVBE KIPTAT
IPTAT IVBE(PTAT) Iconst
IVBE(Const)
+
+ VGS(ZTC)
Q1 Q2 -
VREF R0
R1 R2 Constant Current
- Generator
040629-01
VBE(PTAT) VBE(Const)
VREF = R0[IVBE(PTAT) - IVBE(Const)] = R0 R1 - R 0 R2
R0 T T R

0 T T

= R1 VGO-T0VGO-VBE(T0)-(-1)Vt lnT0 - R2 VGO-T0VGO-VBE(T0)-Vt ln
T0

R0 R0 R0 R0 R1 -1
Let R1 - R2 = 1 and R1 (-1) = R2 R2 = to cancel the nonlinear curvature term.
Other Characteristics of Bandgap Voltage References

Noise
Voltage references for high-resolution ADCs are particularly sensitive to noise.
Noise sources: Op amp, resistors, switches, etc.
VCC
PSRR
+
Maximize the PSRR of the op amp.
Q2 Q1
Offset Voltages
Becomes a problem when op amps are used. +
VREF
VBE2 = VBE1 + VR1 + VOS R1 VR1V
i A - OS -
C2 E1 iC2 iC1 -
VBE = VBE2 - VBE1 = VR1 + VOS = Vt ln iC1AE2 +
Since iC2R3 = iC1R2 - VOS
R3 R2
iC2 R2 VOS R2 VOS
then iC1 = R3 - iC1R3 = R3 1 + iC1R2
Fig. 400-05 VEE
Therefore,

R2AE1
VOS
VR1 = -VOS + Vt ln
R3AE2 1 + iC1R2
V R
R1 2
VREF = VBE2 - VOS + iC1R2 = VBE2 - VOS + R1 R2 = VBE2 - VOS + R1 VR1

R2 R2
R2AE1
VOS
VREF = VBE2 - VOS 1+ R1 + R1 Vt ln
R3AE2 1 - iC1R2
Noise Analysis of a Bandgap Reference

Consider the simple classical BG reference VDD
M4 M5
shown (R2 = 10 R1 = 10k):
M3 * * *
The open-circuit output noise voltage squared en32 en42 en52
is found as,
i1 i2 i3
eno2 = [en12/R12 + en22/R12 + gm52en32
M1 * * M2
+ g 2e 2 + g 2e 2 + i 2/(g 2R 2) en12 en22 +
m5 n4 m5 n5 nd1 m1 1 R1 R2
+ ind22 + ind32 + inr12 + inr22] R22 D1 inr12 inr22 eno2
x1 D2 D3 −
ind12
Assuming the MOSFETs are matched and the xn i 2 xn i 2
nd2 nd3
dc currents in D1, D2, and D3 are equal gives, 060605-02
eno2 [gm52(en32+en42+en52) + ind22+ ind32 + inr12 + inr22] R22

Thermal noise gives (gm5 = 400μS),
4kT 4kT

eno2 = 8kTgm52R22+4qI1+ R1 + R2 R22 5.3x10-19+6.4x10-23+1.7x10-15(V2/Hz)
1/f noise gives,
KF
eno2 = 3gm522fCoxWL K’)
Practical Aspects of Temperature-Independent and Supply-Independent Biasing

A temperature-independent and supply-independent current source and its distribution:
VDD
VT+2VON
VDD VDD
IPTAT IREF
IVBE
To Slave To Slave
+ Bias Ckt. Bias Ckt.
R3 VREF =VGS(ZTC)
−
060704-01
The currents are used to distribute the bias voltages to remote sections of the chip.

Practical Aspects of Bias Distribution Circuits - Continued

Distribution of the current avoids change in bias voltage due to IR drop in bias lines.
Slave bias circuit: VDD
VPBias1
From Master Bias
Ib Ib VPBias2
VNBias2
VNBias1
Fig. 400-08
From here on out in these notes,
VPBias1 = VPB1 = VDD-|VTP|-VSD(sat) VPBias2 = VPB2 = VDD-|VTP|-2VSD(sat)
and
VNBias1 = VNB1 = VTN + VDS(sat) VNBias2 = VNB2 = VTN + 2VDS(sat)
SUMMARY OF VOLTAGE AND CURRENT REFERENCES

• Reasonably good, simple references are possible
• Best power supply sensitivity is approximately 0.01
(10% change in power supply causes a 0.1% change in reference)
• Typical simple reference temperature dependence is 1000 ppm/°C
• Can obtain zero temperature coefficient over a limited range of operation
• Bandgap voltage references can achieve temperature dependence less than 50 ppm/°C
• Correction of second-order effects in the bandgap voltage reference can achieve very
stable (1 ppm/°C) voltage references.
• Watch out for second-order effects such as noise when using the bandgap voltage
reference in sensitive applications.
We will examine bandgap voltage references once again when we consider low
voltage circuits in Section 6 of Chapter 7.

CHAPTER 4 - SUMMARY
• This chapter covered the analysis and design of sub-blocks or subcircuits including:
- Switches - MOS diode and floating resistor realizations
- Current sinks and sources - Current mirrors (amplifiers)
- Current and voltage references - Bandgap reference
• Subcircuits represent primitives of circuit design and do not stand alone
• The current sink/source is an important subcircuit which is used for biases and ac loads
• A current sink/source is characterized by
1.) The independence of the current on the voltage across it (rout)
2.) The voltage range over which the current is not independent of the voltage (VMIN )
• A current mirror is characterized by
1.) The independence of the output current on the voltage across it (rout large)
2.) The output voltage range over which output current is dependent (VMIN (out))
3.) The independence of the input voltage on the input current (rin small)
4.) The range of input voltage over which the input current is independent (VMIN(in))
5.) The accuracy of the current out as a function of the current in ratio.
• A voltage or current reference is independent of power supply and temperature
• The bandgap reference is the best realization of a voltage reference

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Chapter4 – Introduction (12/21/06) Page 4.0-1.

CHAPTER 4 – CMOS SUBCIRCUITS

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter4 – Introduction (12/21/06) Page 4.0-2.

Hierarchy in Analog Circuits

Functional blocks or circuits

CMOS Analog Circuit Design © P.E. Allen - 2006

Example of Hierarchy in Analog Circuits

Complex Operational Amplifier

Simple Biasing Input Second Output

Sub- Inverter Current

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter4 – Section 1 (12/21/06) Page 4.1-1.

SECTION 4.1 –MOSFET SWITCH

roff = resistance of the switch when OFF rOFF

Ioff = offset current when the switch is OFF CAB

IA and IB are leakage currents to ground

CMOS Analog Circuit Design © P.E. Allen - 2006

MOS Transistor as a Switch

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter4 – Section 1 (12/21/06) Page 4.1-3.

MOS Switch Voltage Ranges

Circuit (S/D) (D/S) Circuit

Current-Voltage Characteristics of a NMOS Switch

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter4 – Section 1 (12/21/06) Page 4.1-5.

MOS Switch ON Resistance as a Function of Gate-Source Voltage

SPICE Input File: +LAMBDA=0.04, GAMMA=0.4, PHI=0.7

CMOS Analog Circuit Design © P.E. Allen - 2006

Influence of the ON Resistance on MOS Switches

Example Fig. 4.1-6

Chapter4 – Section 1 (12/21/06) Page 4.1-7.

Including the Influence of the Varying On Resistance

K’W K’WVDS(0) K’W

K’W K’WVDS(0) K’W

Example 4.1-1 - Switch ON Resistance

Chapter4 – Section 1 (12/21/06) Page 4.1-9.

Influence of the OFF State on MOS Switches

CMOS Analog Circuit Design © P.E. Allen - 2006

Influence of Parasitic Capacitances

A simple switch circuit useful A distributed model of A lumped model of

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter4 – Section 1 (12/21/06) Page 4.1-11.

Channel Charge Injection

When the switch is ON, a charge is stored in the vin CL

CMOS Analog Circuit Design © P.E. Allen - 2006

if COL < CL.

Chapter4 – Section 1 (12/21/06) Page 4.1-13.

Modeling the Influence of Charge Injection and Clock Feedthrough

CMOS Analog Circuit Design © P.E. Allen - 2006

Slow Transition Time

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter4 – Section 1 (12/21/06) Page 4.1-15.

Fast Transition Time

CMOS Analog Circuit Design © P.E. Allen - 2006

A Quantized Model of Charge Injection/Clock Feedthrough†

Discretized Gate Voltage

Chapter4 – Section 1 (12/21/06) Page 4.1-17.

Analytical Expressions to Approximate Charge Injection/Clock Feedthrough

Example 4.1-2 - Calculation of Charge Feedthrough Error

Chapter4 – Section 1 (12/21/06) Page 4.1-19.

Example 4.1-2- Continued

CMOS Analog Circuit Design © P.E. Allen - 2006