IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO.
9, SEPTEMBER 2003
A Direct-Conversion Receiver IC for WCDMA
Mobile Systems
Scott K. Reynolds, Brian A. Floyd, Member, IEEE, Troy Beukema, Thomas Zwick, Member, IEEE, Ullrich Pfeiffer,
and Herschel Ainspan
Abstract—A prototype design of a 2.7–3.3-V 14.5-mA SiGe di-
rect-conversion receiver IC for use in third-generation wide-band
code-division multiple-access (3G WCDMA) mobile cellular sys-
tems has been completed and measured. The design includes a by-
passable low-noise amplifier (LNA), a quadrature downconverter,
a local-oscillator frequency divider and quadrature generator, and
variable-gain baseband amplifiers integrated on chip. The design
achieves a cascaded, LNA-referred noise figure (including an in-
terstage surface acoustic wave filter) of 4.0 dB, an in-band IIP3
of 18.6 dBm, and local-oscillator leakage at the LNA input of
112 dBm. The static sensitivity performance of the receiver IC
is characterized using a software baseband processor to compute
link bit-error rate.
Index Terms—code division multiaccess, land mobile radio
cellular systems, receivers, mixers, low noise amplifiers (LNAs),
BiCMOS, direct conversion.
I. INTRODUCTION
A SINGLE-MODE 2.7–3.3-V wide-band code-division
multiple-access (WCDMA) direct-conversion receiver
IC has been designed and fabricated using a 0.24- m SiGe
BiCMOS technology. The receiver design has been targeted to
address the industry needs of high integration, low power, and
low cost, while meeting all WCDMA RF system performance
requirements [1] with design margin. The prototype design
represents a first step toward a fully integrated monolithic
WCDMA/UMTS receiver system-on-chip.
II. ARCHITECTURE
A high-level block diagram of the receiver is shown in
Fig. 1. The direct-conversion architecture eliminates a second
frequency synthesizer, removes the need for an off-chip IF
filter, reduces spurious mixer products, and has the potential to
efficiently accommodate multiple radio standards. However,
several difficulties arise in the design of a practical direct-con-
version receiver, including dc and low-frequency distortion
terms which fall on top of the desired signal at baseband. These
distortion terms arise from local-oscillator (LO)-RF coupling
and from second-order intermodulation. The receiver archi-
tecture shown in Fig. 1 minimizes LO-RF leakage by driving
the LO port of the IC at twice the desired channel frequency
[2]. The 2 LO is divided on-chip to generate differential
quadrature LO signals for the mixers. Attenuation of any
Manuscript received November 19, 2002; revised April 10, 2003.
The authors are with the IBM Thomas J. Watson Research Center, Yorktown
Heights, NY 10598 USA (e-mail: skreyn@us.ibm.com).
Digital Object Identifier 10.1109/JSSC.2003.815914
0018-9200/03$17.00 © 2003 IEEE
1555
LO-RF leakage through the mixer circuitry to the mixer input
is also provided by the low-noise amplifier (LNA2) reverse
isolation. This design allows the LNA1 to be powered down
and bypassed while keeping the LO power at the antenna well
below WCDMA specification requirements. A 4-MHz pole on
the output of the quadrature mixers attenuates high-frequency
distortion terms such as the transmitter leakage signal and
both in-band and out-of-band interference signals. Because
the desired signal can still be relatively small at the mixer
output, a low-noise variable-gain amplifier (BBVGA1) is used
to amplify the signal so that the input noise of the following
active channel select filter does not degrade system sensitivity.
The channel select filter and following VGAs have not been
integrated onto the IC described in this paper.
System performance requirements for the receiver include
LNA-referred noise figure (NF), second- and third-order
linearity (IIP2, IIP3), input 1-dB compression point (ICP1-dB),
quadrature accuracy, balance, in-channel phase distortion,
and LO phase noise. Because the front-end switch/RF filter
characteristics can vary depending on vendor and design, the
receiver performance requirements such as NF, IIP2, IIP3,
and ICP1-dB cannot be directly derived from the WCDMA
specification. Our system performance targets for some of these
parameters are summarized in Table I. Out-of-band linearity
requirements assume 22-dBm transmit leakage at LNA1
input, with 50-dB transmit band attenuation and 2-dB receive
band attenuation in the duplexer. NF requirements assume 4-dB
duplexer loss.
III. CIRCUIT DESIGN
The SiGe BiCMOS technology in which this chip was
fabricated has n-p-n transistors with a peak of 47 GHz,
CMOS field-effect transistors (FETs) with 0.24- m drawn
channel lengths, metal–insulator–metal (MIM) capacitors, and
high- inductors using thick final aluminum. Referring to the
block diagram of Fig. 1, the switched-gain low-noise amplifier
(LNA1) provides either 14 dB of gain or 4 dB of loss, depending
on the strength of the input signal level. Following LNA1, the
50- signal goes off chip to a band-select surface acoustic
wave (SAW) filter, which attenuates RF signals outside the
2110–2170-MHz WCDMA band, easing linearity requirements
further downstream. In particular, the SAW filter attenuates the
handset’s own transmit signal in the 1920–1980-MHz band,
which appears at the LNA1 input due to finite isolation in the
duplexer. The output of the SAW filter comes back on chip to
the 50- input of LNA2, which has 12 dB of gain and acts as
an active balun to provide differential signals to the two mixers.
1556 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 9, SEPTEMBER 2003

Fig. 1. Direct-conversion WCDMA FDD receiver system design.

TABLE I
SYSTEM PERFORMANCE TARGETS AND MEASURED RESULTS FOR THE RECEIVER. THE DESIGNATIONS “BAND1,” “BAND2,” “BAND3,” AND “Tx”
REFER TO INTERFERING TONES IN THE THREE BLOCKER BANDS AND THE TRANSMIT BAND, AS DEFINED IN THE 3GPP SPECIFICATION [1]

The mixers have 6 dB of gain, and BBVGA1 has five selectable
gain states of 16 10 4 2, and 8 dB, respectively.
The receive chip uses no external components except for the
SAW filter shown in Fig. 1 (labeled BPF) and a dc blocking
capacitor at the LNA1 input. LNA1 uses bondwire inductances
for degeneration and impedance matching, as well as on-chip
inductors. Total current consumption is 14.5 mA with LNA1
on and 10.5 mA with LNA1 off.
A simplified schematic of LNA1 is shown in Fig. 2. In
high-gain mode, the LNA is biased at 4 mA; in bypass mode,
the bias current for LNA1 is switched off and the signal is
routed around the gain stage through a MOSFET switch. In
both modes, the LNA is matched to 50 at the input and
output, targeted for a specification of dB and
dB. A proportional to absolute temperature (PTAT)
bias circuit derived from an on-chip bandgap reference in the
downconverter sets Q1’s transconductance approxi-
mately constant over temperature.
In high-gain mode, amplification is provided by a common-
emitter device (Q1) with inductive degeneration . Optimum
noise matching and power matching are obtained simultane-
ously [3], [4]. A small amount of feedback is used from the
base to the collector to ease the input match, as well as facil-
itate matching in bypass mode. As a result, the input bondwire
inductance is enough to complete the 50- match. In bypass
mode, Q1 is powered down and M1 is switched on. This routes
the signal from the input matching network through ,
M1, and to the output matching network. Since the LNA
is passive in bypass mode, its linearity is very high. Due to the
on-resistance of switch M1 and the loss in the matching ele-
ments, there is approximately 4 dB of loss in the bypass mode.
The characteristics of LNA1 were measured on a receiver IC
which was directly bonded to the board (chip-on-board) with
the output SAW filter removed. The gain and NF results given
have the loss due to the input and output coplanar waveguides
de-embedded. In high-gain mode, the gain is 13.2 dB and
REYNOLDS et al.: DIRECT-CONVERSION RECEIVER IC FOR WCDMA MOBILE SYSTEMS 1557

TABLE II
LNA1 PERFORMANCE TARGETS AND MEASURED RESULTS

Fig. 2. Simplifed schematic of LNA1.

the NF is 1.8 dB. Input and output return loss are 10.7 and
12 dB, respectively. The reverse isolation in high-gain mode
is 22 dB. The in-band IIP3 (10-MHz tone spacing) is 5.6 dBm,
the out-of-band IIP3 (70-MHz tone spacing) is 3.9 dBm, and
ICP1-dB is 11.5 dBm. In bypass mode, the gain and NF are
4.0 and 3.6 dB, respectively. The 0.4-dB discrepancy between
the measured gain and NF is due to the tolerance of the mea-
surements. Again, the LNA is matched input and output, with
and better than 12 dB. Finally, IIP3 is 20 dBm in
bypass mode.
Referring to Fig. 1, the downconverter includes LNA2, the
mixers, and the quadrature divider. A simplified schematic of
LNA2 is shown in Fig. 3. It employs inductive degeneration
(Le1 and Le2) to increase the linear range of a standard differ-
ential pair (Q1 and Q2). A tuned RLC load is used so that the
gain peaks in the 2110–2170-MHz WCDMA band, but the cir-
cuit is kept low by resistors R1 and R2 so that the circuit gain
and frequency response are not sensitive to process variations.
Load capacitance of the mixers and interconnect can be ab-
sorbed into C1 and C2. Shunt feedback is applied through Rfb1
and Cfb1 to reduce distortion and make input matching easier,
and Rfb2 and Cfb2 are used to balance the output level of the
Fig. 3. Simplified schematic of LNA2.
inverting and noninverting outputs. Lmatch and Cmatch com-
prise an impedance matching network to match the unbalanced
input of LNA2 to 50 . The output of LNA2 is ac coupled to the
mixers. The combination of the load inductors L1 and L2 and
the ac-coupling capacitors (not shown) forms a second-order
high-pass filter which removes even-order distortion products
generated in LNA2 and prevents them from unbalancing the
mixers. All five inductors in LNA2 are fabricated on the chip.
LNA2 is biased at 3.2 mA.
A simplified schematic of the mixers is shown in Fig. 4. De-
vices Q8–Q11 form a conventional doubled-balanced Gilbert
cell mixer. The transconductor portion of the mixer (devices
Q4–Q7) uses a multi-tanh (or Schmook) cell to expand the linear
input range [5]. This cell gives a better tradeoff between noise
and linearity than a conventional resistively degenerated differ-
ential pair. Note that biasing circuitry is not shown in Fig. 4. The
mixers are biased at 1.2 mA each.
The quadrature divider is a conventional emitter-coupled
logic (ECL) D-flip-flop configured as a divide-by-two. The
1558
Fig. 4. Simplified schematic of the mixer. Biasing arrangements are not
shown.
double-frequency LO signal comes onto the chip differentially
at approximately 10 dBm and is capacitor coupled into the
clock input of the ECL flip-flop. The flip-flop clock input
is matched to 100 at 4280 MHz. The flip-flop quadrature
outputs are buffered and applied to the mixer LO inputs. The
quadrature divider and LO buffer consume 2.05 mA.
The baseband variable-gain amplifier (BBVGA1 in Fig. 1)
consists of five transconductance cells sharing a common input
buffer, a common output buffer, and common load resistors.
Only one of the transconductance cells is biased at a time and
the transconductance of that cell (together with the load resis-
tors) determines the gain of BBVGA1. An RC filter at the input
has a cutoff frequency of 4 MHz. The two ( and channel)
BBVGA1 amplifiers consume 2 mA total.
Measurements on the downconverter were made by wafer
probing of a breakout site. All downconverter measurement re-
sults refer to the 50- unbalanced input of LNA2. The down-
converter voltage gain is 17.4 dB, the NF is 10.5 dB, is
less than 18.6 dB, and the ICP1 dB is 16.2 dBm. The IIP3
of the downconverter is in the range of 5.7 to 6.3 dBm for
all twelve chips tested (using 10 and 19.5 MHz downconverted
tones). The IIP2 is greater than 44 dBm for all twelve samples
(using 14.5 and 15.5 MHz downconverted tones). The ampli-
tude balance of the two quadrature channels is better than 0.1 dB
and the quadrature error is less than 1.5 for all twelve samples
tested. Ten of the twelve samples have quadrature error of less
than 0.8 .
IV. RFIC TEST RESULTS
The system test results of the RFIC on an evaluation board
including the SAW filter (but no duplexer) are presented in
Figs. 5–7 and Table I. The chip was packaged in a QFN-32
plastic package. The evaluation board (shown in Fig. 8) was
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 9, SEPTEMBER 2003
Fig. 5. Measured RFIC frequency response.
Fig. 6. Measured Rx band frequency response and NF.
2.8 cm 4.9 cm and fabricated from a low-loss Teflon-based
laminate on top of an FR-4 carrier.
The measured frequency response of the system (shown in
Fig. 5) revealed that the transmit band suppression was only
21 dB at 1980 MHz, not nearly as good as the 35-dB or greater
suppression expected from the SAW filter specifications. This
problem was traced to a grounding error on our IC. The sub-
strate contacts in LNA1 were placed too close to substrate con-
tacts in the rest of the chip, so that the LNA1 ground was not
effectively isolated from the ground on the rest of the chip. This
allowed ground current from LNA1 to flow through the mutual
ground inductance, so that signals in LNA1 could partially by-
pass the SAW filter and be impressed on the LNA2 input. All
board-level measurement results presented in this paper include
the effect of this grounding error and the resulting reduction in
Tx band attenuation by the SAW filter. As will be seen later, the
RFIC is still within 1 dB of meeting all of our system perfor-
mance targets for out-of-band IIP3 and compression. The mea-
sured noise figure at all twelve WCDMA receive channels is
plotted together with the frequency response in Fig. 6. In the
worst case channel for NF (channel with lowest gain), a margin
of 1 dB is maintained below the required 5 dB.
Fig. 7 shows the measured IIP3 in the receive band for
10-MHz tone spacing for all of the twelve channels. The four
curves represent the two cases of placing the two tones below
or above the LO frequency for both baseband channel outputs
REYNOLDS et al.: DIRECT-CONVERSION RECEIVER IC FOR WCDMA MOBILE SYSTEMS
Fig. 7. Measured Rx band IIP3.
Fig. 8. RFIC evaluation board.
( and ). The worst of all results is then compared with the
specification. For in-band IIP3, there is still 1 dB margin in the
worst case. For out-of-band IIP3, all possible combinations of
LO frequencies and continuous-wave (CW) tones anywhere in
the Tx band and the receive blocker bands (1, 2, and 3 above
and below Tx) at outputs and have been used to determine
the worst case linearity point for each of the blocking bands.
The worst measurement results out of all possible combinations
of tones are summarized in Table I, which shows that under
nominal conditions the chip meets our system performance
targets for IIP3 except for two out-of-band IIP3 cases that
miss the design goal by about 1 dB. This is due to the poor
Tx suppression in the external SAW filter, as discussed above.
For the same reason, the chip slightly misses our target for
out-of-band IIP2, achieving 69 dBm Tx-band IIP2 (for the
worst measured combination of tones) versus a 72-dBm
target.
Measurements with modulated WCDMA signals were also
performed. A sensitivity test according to the 3GPP specifica-
tion [1] was run for WCDMA Rx channel 6 (2137.5 MHz),
which has the worst NF in Fig. 5. The LNA-referred sensitivity
is 124.1 dBm at a bit-error rate (BER) of 0.1%, with an im-
1559
Fig. 9. Die photograph of the chip. Die size is 2.07 mm 2 2.07 mm.
plementation loss of 0.37 dB in the software baseband demod-
ulator. Compared with the required sensitivity of 121 dBm,
there is a margin of over 3 dB. An LNA-referred BER sensitivity
of 123.3 dBm was measured with a simultaneous 1977.5-MHz
Tx interference signal of 22 dBm at the LNA input. Thus, the
receiver is desensed by 0.8 dB by the transmit band blocker. This
desense will be reduced greatly when the Tx band attenuation
provided by the off-chip SAW filter is increased.
A die photograph of the chip is shown in Fig. 9. LNA1 is at
the lower left, while the five inductors of LNA2 are visible in the
upper half of the chip. The die size is 2.07 mm 2.07 mm to the
outside of the pad frame. About 40% of the area within the pad
frame is empty space that will be used in future prototypes.
V. CONCLUSION
A direct-conversion receiver optimized for application in
low-power WCDMA mobile systems has been described.
Key features of the design include a bypassable LNA which
saves 4 mA in low-gain mode and a single-ended-input active
downconverter which draws less than 8.5 mA from a 2.7–3.3-V
supply. The chip consumes 14.5 mA total in high-gain mode
and uses only two external components: an interstage SAW
filter and a dc blocking capacitor at the LNA input. Out-of-band
linearity performance slightly misses some of our desired tar-
gets, but this is due to poor transmitter leakage attenuation
through the interstage SAW filter, a problem which has been
traced to a grounding error on our IC. Otherwise, the receiver
meets all needed WCDMA RF performance requirements
under nominal operating conditions.
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[2] D. Y. C. Lie, J. Kennedy, D. Livezey, B. Yang, T. Robinson, N. Sornin,
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[6] G. Niu, Q. Liang, J. D. Cressler, C. S. Webster, and D. L. Harame, “RF
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Scott K. Reynolds received the B.S. degree in elec-
trical engineering from the University of Michigan,
Ann Arbor, in 1983 and the M.S. and Ph.D. degrees
in electrical engineering from Stanford University,
Stanford, CA, in 1984 and 1987, respectively.
He joined IBM in 1988 and is currently a Research
Staff Member with the IBM Thomas J. Watson Re-
search Center, Yorktown Heights, NY. His research
has involved analog and mixed-signal circuit design
for high-speed communication systems, including
optical, wired, and RF wireless systems, and disk
drive channels. Currently, he is engaged in development of RFICs for 3G
cellular systems and high data rate wireless communication links.
Brian A. Floyd (S’98–M’01) received the B.S. (with
highest honors), M.Eng., and Ph.D. degrees in elec-
trical and computer engineering from the University
of Florida, Gainesville, in 1996, 1998, and 2001, re-
spectively.
Since 2001, he has been with the IBM Thomas
J. Watson Research Center, Yorktown Heights,
NY, designing integrated circuits in CMOS and
silicon-germanium BiCMOS technologies for
wireless, high-speed wired, and millimeter-wave
applications.
While at the University of Florida, Dr. Floyd held the Intersil/Semiconductor
Research Corporation Graduate Fellowship and the Robert C. Pittman Graduate
Fellowship. His doctoral research on wireless interconnects for multigigahertz
clock distribution was a Phase One winner and a Phase Two first runner-up in
the 2000 SRC Copper Design Contest.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 9, SEPTEMBER 2003
Troy Beukema received the B.S. and M.S. degrees in electrical engineering
from the Michigan Technological University, Houghton, in 1984 and 1988, re-
spectively.
Hewlett-Packard in the area of communications test equipment. He joined
Motorola in 1989, where he contributed to the development of digital cellular
wireless systems with a focus on digital signal processing algorithm design
and implementation. In 1996, he joined the IBM Thomas J. Watson Research
Center, Yorktown Heights, NY, where he is currently a Research Staff Member
involved in communications system research. His research interests include
communication link system design and simulation, with an emphasis on signal
processing algorithms for wireless and high-speed wireline channels.
Thomas Zwick (S’95–M’00) was born in Lud-
wigshafen-Rhein, Germany, in 1970. He received the
Dipl.-Ing.(M.S.E.E.) and the Dr.-Ing. (Ph.D.E.E.)
degrees from the Universität Karlsruhe, Karlsruhe,
Germany, in 1994 and 1999, respectively.
From 1994 to 2001, he was a Research Assistant
at the Institut für Hochstfrequenztechnik und Elek-
tronik, Universitat Karlsruhe. Since February 2001,
he has been with the IBM Thomas J. Watson Re-
search Center, Yorktown Heights, NY. His research
topics include em-wave propagation, stochastic
channel modeling, channel measurement techniques, material measurements,
microwave techniques, wireless communication system design, and millimeter
wave antenna design. He participated as an expert in the European COST231
Evolution of Land Mobile Radio (Including Personal) Communications and
COST259 Wireless Flexible Personalized Communications. For the Carl Cranz
Series for Scientific Education, he served as a lecturer for Wave Propagation.
Dr. Zwick received the Best Paper Award from the International Symposium
on Spread Spectrum Techniques and Applications, 1998.
Ullrich Pfeiffer received the diploma degree in
physics and the Ph.D. degree in physics from the
University of Heidelberg, Heidelberg, Germany, in
1996 and 1999, respectively.
In 1997, he was a Research Fellow with the
Rutherford Appleton Laboratory, Oxfordshire, U.K.,
where he developed high-speed multichip modules.
In 2000, he was with the European Organization
for Nuclear Research (CERN), Switzerland, where
his research was based on high-integrated real-time
electronics for a particle physics experiment. He
joined IBM in 2001 and is currently a Research Staff Member with the IBM
Thomas J. Watson Research Center, Yorktown Heights, NY. His research
involves RF circuit design, high-power amplifier design at 60 and 77 GHz, and
high-frequency modeling and packaging for 60-GHz and 3G cellular systems.
Herschel Ainspan received the B.S. and M.S. degrees in electrical engineering
from Columbia University, New York, NY, in 1989 and 1991, respectively.
In 1989, he joined the IBM Thomas J. Watson Research Center, Yorktown
Heights, NY, where he has been involved in the design of mixed-signal and RF
ICs for high-speed data communications.