Danang University of Science and Technology

LAB 1
REPORT

Instructor : Nguyen Tri Bang

Class : 15ECE2
Group members: Vo Hoang Chuong
Nguyen Cong Thien
Le Duc Minh Tuan
Tran Le Quoc

Danang 2018
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CONTENTS

1. Part 1 : Modeling, Simulating, and Testing a Digital

Comparator
2. Part 2 : Modeling, Simulating, and Testing a
MultiFunction Logic Block
3. Part 3 : Working with Real World Devices

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PART 1
Modeling, Simulating, and Testing a Digital
Comparator

1. Draw a logic diagram using the logic gates that were used to build the digital circuit in the
Verilog source code. Use the same signal names indicated in the source code. Use AND, OR,
and NOT gates.

2. Draw the truth table for this circuit

3. a b c d output

0 0 0 0 1

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 1

0 1 0 1 1

0 1 1 0 0

0 1 1 1 0

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1 0 0 0 1

1 0 0 1 1

1 0 1 0 0

1 0 1 1 0

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

3. Run the simulation:

The simulation is quite different from the truth table.

4. The producing glitch prints:

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5. Change the delay to 0, we have

When we run the simulation with delay = 0, the result is almost the same with the truth table.
The delay changes from 0 to 10 affects the lesseq. The delay of lesseq delays for a time from 0
to 10 ps.

6. Change the delay to 10, stimdelay to 5

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7. Advantage of Verilog:
 Verilog is easier to learn because it of it's loosely type definition, and less of a need to
call of the packages to handle std_logic, conversions, and reduce operators.
 The code for Verilog is short, easy to understand.
 Verilog has a good module interface, also many good features
 Some program language is close to Verilog: VHDL,C/C++ …

 Code :
module testBench;
// wires connect things together
wire lesseq, a, b, c, d;
Comparator myComp (lesseq, a, b, c, d);
TestModule myTester (a,b,c,d, lesseq);
endmodule
module Comparator(lesseq, a, b, c, d);
// within the modules, wires are implied?we can put them in if we want
to
parameter delay = 10;
output lesseq; // Ouputs: lesseq
input a, b, c, d; // Inputs: to compare, ab and cd
and #delay and1(term0, notC, notD);
and #delay and2(term1, a,b);
and #delay and3(term2, a, c, notD);
and #delay and4(term3, b, notC);
and #delay and5(term4, a, notC);

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not #delay inv0(notC, c);

not #delay inv1(notD,d);
or #delay or1(lesseq, term0, term1, term2, term3, term4);
endmodule //close Comparator module
 Test code :
module TestModule (a,b,c,d, lesseq); // declare test module
input lesseq; // Module inputs
output a, b, c, d; // Module outputs
parameter stimDelay = 5; // Delay between generating stimuli
reg a, b, c, d; // regs for setting values for checking outputs
initial // this initial block assigns initializing
begin // values to the designated variables
a = 0;
b = 0;
c = 0;
d = 0;
end
initial // this initial block will apply the test vectors
begin // begin initial loop
$display("CLOCK\t\t INPUTS \t\t OUTPUT\t\tTIME");
$display("--a-- \t --b--\t --c--\t--d--\t --lesseq--\t\t------");
$monitor(" %b \t %b \t %b \t %b \t\t %b" ,a,b,c,d,lesseq,$time);
begin // begin REPEAT loop
// we write in decimal and the compiler translates to binary
#stimDelay {a,b,c,d} = 0; // a=0, b=0, c=0, d=0
#stimDelay {a,b,c,d} = 1; // a=0, b=0, c=0, d=1
#stimDelay {a,b,c,d} = 2; // a=0, b=0, c=1, d=0
#stimDelay {a,b,c,d} = 3; // a=0, b=0, c=1, d=1
#stimDelay {a,b,c,d} = 4; // a=0, b=1, c=0, d=0
#stimDelay {a,b,c,d} = 5; // a=0, b=1, c=0, d=1
#stimDelay {a,b,c,d} = 6; // a=0, b=1, c=1, d=0
#stimDelay {a,b,c,d} = 7; // a=0, b=1, c=1, d=1
#stimDelay {a,b,c,d} = 8; // a=1, b=0, c=0, d=0
#stimDelay {a,b,c,d} = 9; // a=1, b=0, c=0, d=1
#stimDelay {a,b,c,d} = 10; // a=1, b=0, c=1, d=0
#stimDelay {a,b,c,d} = 11; // a=1, b=0, c=1, d=1
#stimDelay {a,b,c,d} = 12; // a=1, b=1, c=0, d=0
#stimDelay {a,b,c,d} = 13; // a=1, b=1, c=0, d=1
#stimDelay {a,b,c,d} = 14; // a=1, b=1, c=1, d=0
#stimDelay {a,b,c,d} = 15; // a=1, b=1, c=1, d=1
end
begin
$display("Producing Glitch");
#stimDelay {a,b,c,d} = 0; // a=0, b=0, c=0, d=0
#stimDelay {a,b,c,d} = 10; // a=1, b=0, c=1, d=0

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end
#(2*stimDelay); // needed to see END of simulation
$stop;
$finish; // finish simulation
end // close second initial loop
endmodule // close test-module
PART 2
Modeling, Simulating, and Testing a
MultiFunction Logic Block

 Main code :

module Lab2(lesseq,a,b,sel1,sel2);
parameter delay=10;
output lesseq;
input a,b,sel1,sel2;
and and1(term00,a,b);
or or1(term10,a,b);
xor xor1(term20,a,b);
not not1(notsel1,sel1);
not not2 (notsel2,sel2);
and and2(term01,notsel1,notsel2,term00);
and and3(term11,notsel1,term10,sel2);
and and4(term21,sel1,notsel2,term20);
or or2(lesseq,term01,term11,term21);
endmodule

 Test bench :
module Lab2_tb;
wire result, sel1, sel2, a, b;
Lab2 myComp(result, sel1, sel2, a, b);
Lab2_multitest myTester(sel1, sel2, a, b, result);
endmodule

 Test code :
module Lab2_multitest(sel1, sel2, a, b, result);
input result;
output sel1, sel2, a, b;
parameter stimdelay=25;
reg sel1, sel2, a, b;
initial
begin

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sel1=0;
sel2=0;
a=0;
b=0;
end
initial
begin
#stimdelay{sel1, sel2, a, b}=1;
#stimdelay{sel1, sel2, a, b}=2;
#stimdelay{sel1, sel2, a, b}=3;
#stimdelay{sel1, sel2, a, b}=4;
#stimdelay{sel1, sel2, a, b}=5;
#stimdelay{sel1, sel2, a, b}=6;
#stimdelay{sel1, sel2, a, b}=7;
#stimdelay{sel1, sel2, a, b}=8;
#stimdelay{sel1, sel2, a, b}=9;
#stimdelay{sel1, sel2, a, b}=10;
#stimdelay{sel1, sel2, a, b}=11;
#stimdelay{sel1, sel2, a, b}=12;
#stimdelay{sel1, sel2, a, b}=13;
#stimdelay{sel1, sel2, a, b}=14;
#stimdelay{sel1, sel2, a, b}=15;
end
endmodule

 Result :

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PART 3
Working with Real World Devices

 Set up with 10Ω resistor :

Results :

2.3 m
V 10 Ω=2.3mV =¿ I 1= =0.23 mA
10

2.33
V 330 Ω=2.33 V =¿ I 2= =7.06 mA
330

When remove LED & resistors V 1=144 mV

 Set up with 1000 Ω resistor :

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Results :

101 m
V 1 kΩ =101mV =¿ I 3= =0.101 mA
1000

2.69
V 330 Ω=2.69 V =¿ I 4 = =8.15 mA
330

When remove LED & resistors V 1=146 mV

 Datasheet info:
 I IL =−0.4 mA is the input LOW current.
 I OH =−0.4 mA is the output HIGH current.
 I IH =20 µA ¿ 0.1 mA is the input HIGH current.
 I OL=0.8 mA is the output LOW current.
 V IL=0.8V is the input LOW voltage.
 V OH =3.5 V is the output HIGH voltage.
 V IH =2.0 V is the input HIGH voltage.
 V OL =0.25 ¿ 0,35V is the output LOW voltage.

Base on the infomation from the datasheet and our result, the current is quite far difference
but the voltage is quite similar to the datasheet.

The LED in figure 12 is brighter than its one in figure 11 because we have I 330Ω on figure 12 is
larger than on figure 11. Therefore, the Voltage throught the LED in fig. 12 is larger than in fig.
11.

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