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Honeywell
Aerospace Electronic Systems
CES--Phoenix
P.O. Box 21111
Phoenix, Arizona 85036-1111
U.S.A.

TO HOLDERS OF COMPONENT MAINTENANCE MANUAL, PUB. NO. A09--1147--034,


FLIGHT GUIDANCE COMPUTER (PART NO. 7003974--708, --713, AND
--717)

REVISION NO. 1 DATED 1 NOV 2004

HIGHLIGHTS

This manual was previously published as a multi--volume manual, Pub. No. A09--1147--034.
The volumes and their applicable revisions were:
Volume I, Description, Operation, Maintenance, Revision 0, dated 1 Mar 1992
Volume II, Testing and Fault Isolation, Revision 0, dated 1 Mar 1992
This manual is now merged into a single--volume manual and published as Pub. No.
A09--1147--034, Revision 1, dated 1 Nov 2004.

Please replace your copies of the manual with the attached revision.

Page Description of Change Effectivity


Complete manual All data has been reformatted to better meet the digital data All
delivery requirements of ATA 2200.
T--1, T--2 Revised to show the revision date of this manual. Added --724, All
--725, --728, and --732 as new part numbers.
H--1, H--2 Removed these pages because material safety information is the
responsibility of the material manufacturer.
(DELETED)
RTR--1, RTR--2 Added RECORD OF TEMPORARY REVISIONS. All
SBL--1 thru SBL--13 Separated Service Bulletins into a list of each end item. Removed All
all Service Bulletins that are not applicable to this book. Added
new Service Bulletin lists for 7003974--724, --725, --728, and --732.
LEP--1 thru LEP--12 Revised to show where changes are made in the manual. All
TC--1 thru TC--8 Revised to show the location of the data in this manual. All
INTRO--1 thru Revised the INTRODUCTION to include volume, proprietary
INTRO--8 notice, and export notice paragraphs. Revised the Table of Related
Publications and Verification Dates. Added CAUTIONS and
hazardous materials WARNING. Revised the list of acronyms and
abbreviations.
1 Included --724, --725, --728, and --732 in paragraph (3) and Table 1. All
3, 4 Revised Table 2 for Part No. 7003974 --708, --713, --717, --724, All
--725, --728, and --732. Revised Table 3 to include CCAs
superseded in end item Dash No. --708, --713, --717, --724, --725,
--728, and --732. Revised Table 4 to include end item Dash No.
converted to --725, --728 and --732.
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COMPONENT MAINTENANCE MANUAL


Flight Guidance Computer / Part No. 7003974

Page Description of Change Effectivity


22 Added paragraph 2.D. description to apply to CCA A2 Part No. All
7007585--922.
35 Revised Figure 7 to E7007587--904--16--H status. All
37 Revised Figure 8 to E7007587--904--17--H status. All
41 Revised Figure 9 to E7007587--904--21--H status. All
43 Revised Figure 10 to E7005789--904--20--H status. All
47 Revised Figure 12 to E700587--904--19--H status. All
57 Revised Figure 15 to E7007589--907--23--H status. All
64 Added paragraph 2.G. description to apply to CCA A5 All
Part No. 7007591--903.
65 Revised Figure 22 to E7007591--903--16 status. All
69 Revised Figure 23 to E7007591--903--18 status. All
71 Revised Figure 24 to E7007591--903--21 status. All
75 Revised Figure 25. All
77 Revised Figure 26 to E7007591--903--17 status. All
85 Revised Figure 28 to E7007591--903--19--E status. All
87 Revised Figure 29 to E7007591--903--20--G status. All
102 Revised paragraph 2.I. for Analog Inputs CCA A7, All
Part No. 7007595--908 and --928.
112 Added paragraph 2.J. description to apply to CCA A7, All
Part No. 7007595--913 and --933.
1001 thru 1406 Reformatted section. Section revised and new figures added. All
Tables added and numbering changed accordingly.
2001 thru 2182 Added new section titled SCHEMATIC AND WIRING DIAGRAMS. All
Tables and figures numbered accordingly. Relocated Wire List No.
7004617--910 Revision D, 7004617--915 Revision C, and
7004617--917 Revision C to this section.
3001, 3002 Reformatted section. Added Table 3001, Equipment for All
Disassembly.
4001, 6001, 7001 Revised hazardous materials WARNING. Removed the Hazard
Rating Codes shown in the materials list. Refer to the
manufacturer’s material safety data sheets for safety information.
4001, 4002 Reformatted section. Added Table 4001, Equipment for Cleaning, All
and 4002, Materials for Cleaning.
5001, 5002 Reformatted section. All
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Page Description of Change Effectivity


6001 thru 6006 Reformatted section. Added Table 6001, Equipment for Special All
Repair and Table 6002, Materials for Special Repair. Renumbered
figures according to new format procedures.
7001 thru 7006 Reformatted section. Added Table 7001, Equipment for Assembly, All
and Table 7002, Materials for Assembly. Moved paragraph on
Storage to new section, STORAGE (INCLUDING
TRANSPORTATION).
8001, 8002 Added section on Fits and Clearances. All
9001 thru 9006 Reformatted section. Added new updated table designations. All
Updated list of Special Tools, Fixtures, Equipment, and Materials.
in Table 9001, Equipment for Maintenance and Table 9002,
Materials for Maintenance.
10001 thru 10060 Reformatted section. Revised Parts List to add data from All
incorporated service bulletins and to give new parts data.
Renumbered figures according to new format.
15001 thru 15004 Added section STORAGE (INCLUDING TRANSPORTATION). All
Included Table 15001, Materials for Storage and Transportation
and Figure 15001, Shipping and Storage Container.
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Honeywell
Aerospace Electronic Systems
CES--Phoenix
P.O. Box 21111
Phoenix, Arizona 85036-1111
U.S.A.

Component Maintenance Manual


with illustrated parts list

Flight Guidance Computer


Part No. 7003974--708, --713, --717, --724,
--725, --728, --732

This document contains technical data and is subject to U.S. export regulations.
These commodities, technology, or software were exported from the United States in accordance with the
export administration regulations. Diversion contrary to U.S. law is prohibited.

22--11--81
UP184442

Title Page T--1


Printed in U.S.A. Pub. No. A09--1147--034, Revision 1 Revised 1 Nov 2004
1 Mar 1992
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COMPONENT MAINTENANCE MANUAL


Flight Guidance Computer / Part No. 7003974

PROPRIETARY NOTICE

This document and the information disclosed herein are proprietary data of Honeywell. Neither
this document nor the information contained herein shall be used, reproduced, or disclosed to
others without the written authorization of Honeywell, except to the extent required for
installation or maintenance of the recipient’s equipment.
NOTICE -- FREEDOM OF INFORMATION ACT (5 USC 552) AND
DISCLOSURE OF CONFIDENTIAL INFORMATION GENERALLY (18 USC 1905)
This document is being furnished in confidence by Honeywell. The information disclosed
herein fall within exemption (b) (4) of 5 USC 552 and the prohibitions of 18 USC 1905.
S2004

Honeywell is a U.S. registered trademark of Honeywell. All other marks are owned by their respective companies.

22--11--81
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Copyright 2004 Honeywell Revised 1 Nov 2004
All Rights Reserved 1 Mar 1992
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Please cut along the dotted line.

FOR HONEYWELL USE ONLY


REPORT OF POSSIBLE DATA ERROR CONTROL NO.

DATE RECEIVED

To help us improve the quality of our publication, Honeywell encourages any report of a possible data error.

PUBLICATION INFORMATION
Volume No.
Publication ATA Latest Issue Date
Number A09--1147--034, Revision 1 (Book, or
Number 22--11--81 From Title Page
Addendum)

Publication Flight Guidance Computer Document


Component Maintenance Manual
Title 7003974--708, --713, --717, --724, --725, --728, --732 Type

READER INFORMATION
Please check all that apply:
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Local reproduction of this form is encouraged. This form is based on electronic form INF--300, Revision 0
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PUBLICATION INFORMATION
Volume No.
Publication ATA Latest Issue Date
Number A09--1147--034, Revision 1 (Book, or
Number 22--11--81 From Title Page
Addendum)

Publication Flight Guidance Computer Document


Component Maintenance Manual
Title 7003974--708, --713, --717, --724, --725, --728, --732 Type

READER INFORMATION
Please check all that apply:
h Trainer h Technician h Librarian h Engineer h Other (Please specify)
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UP184442

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the use of staples). If sending by FAX, the Technical Publications’ U.S. FAX No. is (602- 436- 3900). If sending by email, the email address is
tpqa@honeywell.com.
Local reproduction of this form is encouraged.
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UNITED STATES

BUSINESS REPLY MAIL


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POSTAGE WILL BE PAID BY ADDRESSEE


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RECORD OF REVISIONS
For each revision, put the revised pages in your manual and discard the superseded pages. Write
the revision number and date, date put in manual, and the incorporator’s initials in the applicable
columns on the Record of Revisions. The initial H shows Honeywell is the incorporator.

Revision Revision Date Put Revision Revision Date Put


Number Date In Manual By Number Date In Manual By
1 1 Nov 2004 1 Nov 2004 H
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Flight Guidance Computer / Part No. 7003974

RECORD OF TEMPORARY REVISIONS


Instructions on each page of a temporary revision tell you where to put the pages in your manual.
Remove temporary revision pages only when discard instructions are given. For each temporary
revision, put the applicable data in the record columns on this page.

Temporary Temporary Temporary Date


Revision Revision Revision Date Put Removed
Number Date Status in Manual By * from Manual By *

* The initial H in this column shows Honeywell has done this task.
UP184442

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COMPONENT MAINTENANCE MANUAL


Flight Guidance Computer / Part No. 7003974

SERVICE BULLETIN LIST

7003974--708 and --713


Identified Date Included
Service Bulletin Mod in this Manual Description
7003974--34--12 B 1 Mar 1992 The cooling fan and fan shroud are removed and
(21--1984--77) the top cover is replaced with a perforated cover.
7003974--34--9 J 1 Mar 1992 Improves performance of the hardware monitors
(21--1984--158) and permits operation at 18 V dc. On CCA A1, C26
and R126 are replaced and CR28 is removed.
7003974--34--8 K 1 Nov 2004 Changes the flap position input by removing a trim
(21--1984--159) servo series diode and adds trim arm feedback.
7003974--34--11 P 1 Mar 1992 Corrects low voltage start--up problems. On CCA
(21--1985--20) A1, R127 is replaced and R147 and CR35 are
added.
7003974--34--13 R 1 Mar 1992 Ensures a soft start of the power supply during
(21--1985--22) power--up. On CCA A1, R133, R143, and CR31
are removed and R144 and R145 are replaced.
7003974--34--21 W 1 Mar 1992 Eliminates failing the power--up test due to monitor
(21--1985--65) trips. On CCA A1, R144 and R145 are removed.
7003974--34--24 AB 1 Mar 1992 Reduces noise susceptibility of A/D converters. On
(21--1985--92) CCA A5, R58 and R59 are added.
7003974--34--25 AE 1 Mar 1992 The power--down timer circuitry is changed to
(21--1985--102) eliminate indications that data in RAM is valid after
a power interrupt. On CCA A2, C23 is replaced.
7003974--34--40 AS 1 Mar 1992 Ensures computer will continue to operate during
(21--1985--159) brief input power interruptions. On CCA A1, R127,
R128, R147, and C73 are replaced and R148 is
added.
7003974--34--43 AV 1 Mar 1992 7003974--708 and --713 only. Ensures that the
(21--1985--181) FMC turns on with 18 volts input power. On CCA
A1, R127, R128, and R147 are replaced and R106
and Q15 are removed.
7003974--34--50 BD 1 Mar 1992 Reduces the switching FEET failure rate in the
(21--1986--66) power supply current limit circuit. On CCA A1, C83
is replaced with CR33, R138 is replaced with
FR.21, R137 and R139 are replaced, and R149 is
added.
7003974--34--59 BL 1 Mar 1992 Improves operation of the overcorrect protection
(21--1986--166) circuit in the power supply. On CCA A1, three bus
wires are moved.
7003974--34--63 BR 1 Mar 1992 Allows for installation of a nonvolatile (battery
(21--1986--204) backup) RAM for troubleshooting. On the
motherboard assembly, four wires are added.
7003974--34--67 BS 1 Mar 1992 Allows using a test card in the A8 card location.
(21--1986--210) Eleven harness wires are added.
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COMPONENT MAINTENANCE MANUAL


Flight Guidance Computer / Part No. 7003974

7003974--708 and --713 (cont)


Identified Date Included
Service Bulletin Mod in this Manual Description
7003974--34--66 BU 1 Mar 1992 Corrects yaw damper motor 1 time constant and
(21--1986--221) flap angle loading.
7003974--34--79 CC 1 Mar 1992 Installation of NVRAM. (Applicable to --708 only.)
(21--1987--85)
7003974--34--73 -- 1 Mar 1992 Changes the Flight Guidance Computer from Part
(21--1987--86) No. 7003974--703 to Part No. 7003974--708.
7003974--34--74 CD 1 Mar 1992 Installs released software.
(21--1987--87)
7003974--34--77 CF 1 Mar 1992 Grounds LSB of pre--bus interrupt controller on
(21--1987--117) CCA A3.
7003974--34--89 -- 1 Mar 1992 Changes the Flight Guidance Computer from Part
(21--1988--029) No. 7003974--708 to Part No. 7003974--713.
7003974--34--95 CR 1 Mar 1992 Improves power supply.
(21--1988--075)
7003974--34--105 CS 1 Mar 1992 Corrects worst--case timing and eliminates
(21--1989--155) intermittent heartbeat reset pulse.
7003974--34--96 CW 1 Mar 1992 Corrects monitor trip point circuitry design error.
(21--1989--09)
7003974--34--98 CY 1 Mar 1992 Eliminates intermittent motherboard terminals.
(21--1989--39)
7003974----104 CZ 1 Mar 1992 Eliminates problems caused by MOD CR.
(21--1989--148)
7003974--34--101 DB 1 Mar 1992 Eliminates intermittent sockets and potential shorts
(21--1989--101) to covers.
7003974--34--106 DC 1 Mar 1992 Eliminates low pass filter created by isolation
(21--1989--181) resistor in latched power--valid circuit.
7003974--34--118 DF 1 Nov 2004 Aids fault isolation. Adds nonvolatile RAM to CCA
(A21--1991--095) A6 to record the autopilot part of the computer.
TESTING is revised.
7003974--34--126 DR 1 Nov 2004 Changes the bias point on the drive transistor
(A21--1992--036) which controls the pre--zero function in the B
processor’s D/A conversion circuitry for Part
No. 7003974--713 and --717. TESTING is not
revised.
7003974--34--141 EA 1 Nov 2004 Eliminates pitch oscillation in altitude hold mode at
(A21--1995--083) low speeds by reducing the angle--of--attach rate
gain for Part No. 7003974--713. TESTING is not
revised.
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COMPONENT MAINTENANCE MANUAL


Flight Guidance Computer / Part No. 7003974

7003974--708 and --713 (cont)


Identified Date Included
Service Bulletin Mod in this Manual Description
7003974--34--147 EE 1 Nov 2004 Reduces wire walk in Heading Hold and Heading
(A21--1998--105) Select Modes only. Delays ASCB control
transmissions to add a gap between frame start
and frame control to insure compatibility with
ASCB VLSI chips. For Part No. 7003974--713.
TESTING is not revised.
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Flight Guidance Computer / Part No. 7003974

SERVICE BULLETIN LIST

7003974--717
Identified Date Included
Service Bulletin Mod in this Manual Description
7003974--34--118 DF 1 Nov 2004 Aids fault isolation. Adds nonvolatile RAM to CCA
(A21--1991--095) A6 to record the autopilot part of the computer.
TESTING is revised.
7003974--34--121 1 Nov 2004 Changes Part No. 7003974--717 Red Label Units
(A21--1991--144) to Part No. 7003974--717 Silver Label Units and
ensures all units being tested in the field contain
the hardware and software to complete the
change. TESTING is revised.
7003974--34--126 DR 1 Nov 2004 Changes the bias point on the drive transistor
(A21--1992--036) which controls the pre--zero function in the B
processor’s D/A conversion circuitry for Part No.
7003974--713 and --717. TESTING is not revised.
7003974--34--138 DZ 1 Nov 2004 Improves backcourse high intercept angle (greater
(A21--1995--061) than 45 degrees) performance and prevents
nuisance trim switches monitor failures for Part
No. 7003974--717. TESTING is not revised.
7003974--34--127 -- 1 Nov 2004 Changes 7003974--717 to 7003974--725.
(A21--1992--168) TESTING is revised.
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Flight Guidance Computer / Part No. 7003974

SERVICE BULLETIN LIST

7003974--724
Identified Date Included
Service Bulletin Mod in this Manual Description
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Flight Guidance Computer / Part No. 7003974

SERVICE BULLETIN LIST

7003974--725
Identified Date Included
Service Bulletin Mod in this Manual Description
7003974--34--127 -- 1 Nov 2004 Changes 7003974--717 to 7003974--725.
(A21--1992--168) TESTING is revised.
7003974--34--138 DZ 1 Nov 2004 Improves backcourse high intercept angle
(A21--1995--061) performance and prevents nuisance trim switches
monitor failures. TESTING is not revised.
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Flight Guidance Computer / Part No. 7003974

SERVICE BULLETIN LIST

7003974--728
Identified Date Included
Service Bulletin Mod in this Manual Description
7003974--34--148 -- 1 Nov 2004 Changes the Flight Guidance Computer from Part
(A21--1999--013) No. 7003974--713 to Part No. 7003974--728.
TESTING is revised.
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Flight Guidance Computer / Part No. 7003974

SERVICE BULLETIN LIST

7003974--732
Identified Date Included
Service Bulletin Mod in this Manual Description
7003974--34--0153 -- 1 Nov 2004 Converts FZ--800 Flight Guidance Computer from
(A21--1150--001) Part No. 7003974--728 to Part No. 7003974--732;
(1) Prevents nuisance overspeed annunciations,
(2) Prevents standoffs in approach modes, (3)
Prevents nuisance trim runaway trips, (4)
Incorporates new EPROM part numbers.
TESTING is revised.
UP184442

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LIST OF EFFECTIVE PAGES

Subheading and Page Date Subheading and Page Date

Title LEP--11 H 1 Nov 2004


T--1 H 1 Nov 2004 LEP--12 H 1 Nov 2004
T--2 H 1 Nov 2004 Table of Contents
Record of Revisions TC--1 H 1 Nov 2004
RR--1 H 1 Nov 2004 TC--2 H 1 Nov 2004
RR--2 H 1 Nov 2004 TC--3 H 1 Nov 2004
TC--4 H 1 Nov 2004
Record of Temporary Revisions
TC--5 H 1 Nov 2004
RTR--1 H 1 Nov 2004
TC--6 H 1 Nov 2004
RTR--2 H 1 Nov 2004
TC--7 H 1 Nov 2004
Service Bulletin List TC--8 H 1 Nov 2004
SBL--1 H 1 Nov 2004
Introduction
SBL--2 H 1 Nov 2004
INTRO--1 H 1 Nov 2004
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SBL--5 H 1 Nov 2004
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SBL--7 H 1 Nov 2004
SBL--8 H 1 Nov 2004 INTRO--6 H 1 Nov 2004
SBL--9 H 1 Nov 2004 INTRO--7 H 1 Nov 2004
SBL--10 H 1 Nov 2004 INTRO--8 H 1 Nov 2004
SBL--11 H 1 Nov 2004 Description and Operation
SBL--12 H 1 Nov 2004 1 H 1 Nov 2004
SBL--13 H 1 Nov 2004 2 H 1 Nov 2004
SBL--14 H 1 Nov 2004 3 H 1 Nov 2004
List of Effective Pages 4 H 1 Nov 2004
LEP--1 H 1 Nov 2004 5 H 1 Nov 2004
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1381 H 1 Nov 2004 2015 H 1 Nov 2004
1382 H 1 Nov 2004 2016 H 1 Nov 2004
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2012 H 1 Nov 2004 2050 H 1 Nov 2004
2013 H 1 Nov 2004 2051 H 1 Nov 2004

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2149 H 1 Nov 2004 4001 H 1 Nov 2004
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Fits and Clearances 10027 H 1 Nov 2004


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10031 H 1 Nov 2004
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Blank Page
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TABLE OF CONTENTS
Subject Page

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--1
1. Proprietary, Export, and Precautionary Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--1
A. Proprietary Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--1
B. Export Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--1
C. Special Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--1
2. Content Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--2
A. Volume History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--2
B. How to Use This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--2
C. Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--4
D. Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--4
E. Weights and Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--5
F. Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--5

DESCRIPTION AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1


1. Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
A. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
A. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
B. Power Supply CCA A1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
C. Servo Drive CCA A2 (7007585--901, --902) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
D. Servo Drive CCA A2 (7007585--922) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
E. B--Processor CCA A3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
F. A--Processor CCA A4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
G. Serial Data Interface CCA A5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
H. Direct Discretes CCA A6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
I. Analog Inputs CCA A7 (7007595--908, --928) . . . . . . . . . . . . . . . . . . . . . . . . . . 102
J. Analog Inputs CCA A7 (7007595--913, --933) . . . . . . . . . . . . . . . . . . . . . . . . . . 112

TESTING AND FAULT ISOLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
A. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
B. Equipment and Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
UP184442

Page TC--1
22--11--81 1 Nov 2004
Use or disclosure of information on this page is subject to the restrictions in the proprietary notice of this document.
RELEASED FOR THE EXCLUSIVE USE BY: CHARTER JETS UAB

COMPONENT MAINTENANCE MANUAL


Flight Guidance Computer / Part No. 7003974

Subject Page
2. Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
A. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
B. Test Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
C. Fault Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
SCHEMATIC AND WIRING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
A. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
B. Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
C. Schematic and Wiring Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2002
DISASSEMBLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3001
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3001
A. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3001
B. Equipment and Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3001
2. Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3001
A. Removal of the Top Cover and Retaining Bars . . . . . . . . . . . . . . . . . . . . . . . . . 3001
B. Removal of the CCAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3001
C. Removal of the Bottom Cover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3002
D. Removal of the Harness Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3002
CLEANING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4001
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4001
A. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4001
B. Equipment and Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4001
2. Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4002
A. External Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4002
B. Electrical Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4002
C. Metallic Mechanical Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4002
CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5001
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5001
A. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5001
B. Equipment and Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5001
2. Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5001
A. Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5001
B. Visual Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5001
UP184442

Page TC--2
22--11--81 1 Nov 2004
Use or disclosure of information on this page is subject to the restrictions in the proprietary notice of this document.
RELEASED FOR THE EXCLUSIVE USE BY: CHARTER JETS UAB

COMPONENT MAINTENANCE MANUAL


Flight Guidance Computer / Part No. 7003974

Subject Page

REPAIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6001
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6001
A. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6001
B. Equipment and Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6001
2. Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6002
A. References for Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6002
B. Special Repair of the Knob Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6003
C. Special Repair of the Motherboard CCA A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6004
D. Touch Up Painted Surfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6005
ASSEMBLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7001
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7001
A. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7001
B. Equipment and Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7001
2. Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7002
A. Installation of the Harness Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7002
B. Installation of the Bottom Cover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7003
C. Installation of the CCAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7003
D. Installation of the Top Cover and Retaining Bars . . . . . . . . . . . . . . . . . . . . . . . 7004
FITS AND CLEARANCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8001
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8001
A. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8001
SPECIAL TOOLS, FIXTURES, EQUIPMENT, AND CONSUMABLES . . . . . . . . . . . . 9001
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9001
A. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9001
B. Special Tools, Fixtures, Equipment, and Consumables . . . . . . . . . . . . . . . . . . 9001
ILLUSTRATED PARTS LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10001
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10001
A. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10001
B. How to Find a Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10001
2. Contents of the IPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10001
A. List of Suppliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10001
B. Equipment Designator Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10001
UP184442

Page TC--3
22--11--81 1 Nov 2004
Use or disclosure of information on this page is subject to the restrictions in the proprietary notice of this document.
RELEASED FOR THE EXCLUSIVE USE BY: CHARTER JETS UAB

COMPONENT MAINTENANCE MANUAL


Flight Guidance Computer / Part No. 7003974

Subject Page
C. Numerical Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10001
D. Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10002
3. List of Suppliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10005
4. Equipment Designator Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10007
5. Numerical Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10009
6. Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10019
SPECIAL PROCEDURES (Not Applicable)

REMOVAL (Not Applicable)

INSTALLATION (Not Applicable)

SERVICING (Not Applicable)

STORAGE (INCLUDING TRANSPORTATION) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15001


1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15001
A. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15001
B. Equipment and Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15001
2. Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15002
A. Storage Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15002
B. Packaging Procedure for the FGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15002
UP184442

Page TC--4
22--11--81 1 Nov 2004
Use or disclosure of information on this page is subject to the restrictions in the proprietary notice of this document.
RELEASED FOR THE EXCLUSIVE USE BY: CHARTER JETS UAB

COMPONENT MAINTENANCE MANUAL


Flight Guidance Computer / Part No. 7003974

List of Illustrations
Figure Page
Figure Intro--1. Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--4
Figure 1. FZ--800 Flight Guidance Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. I/O Function Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Engage Logic Interlock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Power Supply Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. CCA A3 Bus Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7. B--Processor Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 8. EPROM, RAM, Transceiver and Latch Controls . . . . . . . . . . . . . . . . 37
Figure 9. ASCB Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 10. Interrupt Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 11. Bus Interrupt Synchronous Up--Counter Bus Diagram . . . . . . . . . . . 46
Figure 12. Bus Counter Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 13. CCA A4 Bus Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 14. Transceiver and Microprocessor Controls . . . . . . . . . . . . . . . . . . . . . . 53
Figure 15. RAM Control Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 16. Serial Communications Controller Controls . . . . . . . . . . . . . . . . . . . . 59
Figure 17. Memory Map CCA A4 Memory Devices . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 18. EPROM Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 19. Transceiver Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 20. Counter Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 21. SRAM (NVRAM) Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 22. CCA A5 Bus Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 23. Interrupt Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 24. Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 25. B--Processor Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 26. A/D Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 27. A/D Conversion Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 28. Serial Data Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 29. Serial Data RAM Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 30. CCA A6 Bus Diagram (7003974--708 and --713) . . . . . . . . . . . . . . . . 91
Figure 31. CCA A6 Bus Diagram for Part No. 7007593--913
(7003974--708) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
UP184442

Page TC--5
22--11--81 1 Nov 2004
Use or disclosure of information on this page is subject to the restrictions in the proprietary notice of this document.
RELEASED FOR THE EXCLUSIVE USE BY: CHARTER JETS UAB

COMPONENT MAINTENANCE MANUAL


Flight Guidance Computer / Part No. 7003974

List of Illustrations (cont)


Figure Page
Figure 32. CCA A6 Bus Diagram (7003974--708) with NVRAM . . . . . . . . . . . . . 95
Figure 33. CCA A6 Bus Diagram (7003974--713, --717, --724, --725, --728,
and --732) with NVRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 34. CCA A6 U4 (U28) [U14] A--Data Transceiver Controls . . . . . . . . . . . 99
Figure 35. CCA A6 U23 (U35) [U5] B--Data Transceiver Controls . . . . . . . . . . . 99
Figure 36. CCA A6 U2, U5 (U15, U18) [U2, U6] Multiplexer Controls . . . . . . . . 100
Figure 37. CCA A6 Addressable Latch Controls . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 38. SRAM (NVRAM) and Transceiver Controls for 7007593--904,
--913 and --914 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 2001. Motherboard CCA A9, Detail/Schematic . . . . . . . . . . . . . . . . . . . . . . . 2005
Figure 6001. Knob Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6004
Figure 6002. Repair of Motherboard CCA A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6006
Figure 7001. Application of Tape to the Electrical Rack Assembly . . . . . . . . . . . . . 7005
IPL Figure 1. Flight Guidance Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10020
IPL Figure 2. Electrical Rack Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10049
IPL Figure 3. Motherboard Circuit Card Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . 10055
Figure 15001. Shipping and Storage Container . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15003
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Flight Guidance Computer / Part No. 7003974

List of Tables
Table Page
Table Intro--1. Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRO--3
Table 1. FGC Leading Particulars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Current CCA Configuration and Function ..................... 3
Table 3. Superseded CCAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 4. Conversions of End Item Dash Numbers . . . . . . . . . . . . . . . . . . . . . . 4
Table 5. WAIT States for the A--Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 6. Function Table U8 Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 7. U28 Up--Counter Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 8. Discrete RAM Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 9. Analog Inputs to Multiplexer U18 (U14) (Enabled by A--M6SEL,
A--M7SEL, and A--M8SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 10. Analog Inputs to Multiplexer U21 (U24) (Enabled by
A--M2SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 11. Analog Inputs to Multiplexer U19 (U23) (Enabled by
A--M4SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 12. Analog Inputs to Multiplexer U30 (U10) (Enabled by A--D0
and A--D1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 13. Analog Inputs to Multiplexer U15 (U25) (Enabled by
A--M3SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 14. Analog Inputs to Multiplexer U16 (U12) (Enabled by
A--M5SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 15. Analog Inputs to Multiplexer U14 (U13) (Enabled by
A--M1SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 16. Analog Inputs to Multiplexer U24 (U21) (Enabled by
B--M3SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 17. Analog Inputs to Multiplexer U25 (U11) (Enabled by
B--M1SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 18. Analog Inputs to Multiplexer U26 (U15) (Enabled by
B--M2SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 19. Analog Inputs to Multiplexer U27 (U22) (Enabled by
B--M4SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 20. Analog Inputs to Multiplexer U19 (U13) (Enabled by A--M1SEL,
A--M7SEL, and A--M8SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 21. Analog Inputs to Multiplexer U6 (U24) (Enabled by A--M2SEL) . . . 117
Table 22. Analog Inputs to Multiplexer U18 (U23) (Enabled by
A--M4SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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List of Tables (cont)


Table Page
Table 23. Analog Inputs to Multiplexer U17 (U25) (Enabled by
A--M3SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 24. Analog Inputs to Multiplexer U21 (U21) (Enable by B--M3SEL) . . . 119
Table 25. Analog Inputs to Multiplexer U9 (U11) (Enabled by B--M1SEL) . . . 119
Table 26. Analog Inputs to Multiplexer U8 (U15) (Enabled by B--M2SEL) . . . 120
Table 1001. Test Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
Table 1002. Equipment for Fault Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
Table 1003. Troubleshooting Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
Table 1004. NVRAM Initialization and Data Retrieval . . . . . . . . . . . . . . . . . . . . . . . 1021
Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 . . 1031
Table 1006. Integrated Test Procedure for 7003974--717, --724, --725 . . . . . . . . 1155
Table 1007. Burn--In Test Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
Table 1008. End Item Test Procedure for 7003974--708, --713, --728,
and --732 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289
Table 1009. End Item Test Procedure for 7003974--717, --724, and --725 . . . . . 1329
Table 1010. Fluke 9010 Test Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
Table 1011. Integrated Test Procedure for the FZ800 Power Supply Card . . . . 1375
Table 2001. Materials Used for Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
Table 2002. CCA Schematic Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2002
Table 2003. Wire List No. 7004617--910, Revision D . . . . . . . . . . . . . . . . . . . . . . . 2011
Table 2004. Wire List No. 7004617--915, Revision C . . . . . . . . . . . . . . . . . . . . . . . 2067
Table 2005. Wire List No. 7004617--917, Revision C . . . . . . . . . . . . . . . . . . . . . . . 2125
Table 3001. Location of CCAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3002
Table 4001. Equipment for Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4001
Table 4002. Materials for Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4001
Table 6001. Equipment for Special Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6001
Table 6002. Materials for Special Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6002
Table 7001. Materials for Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7001
Table 7002. CCA A9 Motherboard Connector Keying . . . . . . . . . . . . . . . . . . . . . . 7003
Table 7003. Location of CCAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7004
Table 8001. Fits and Clearances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8001
Table 9001. Equipment for Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9001
Table 9002. Materials for Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9004
Table 15001. Materials for Storage and Transportation . . . . . . . . . . . . . . . . . . . . . . 15001
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Flight Guidance Computer / Part No. 7003974

INTRODUCTION
1. Proprietary, Export, and Precautionary Data
A. Proprietary Notice

(1) This document and the information disclosed herein are proprietary data of
Honeywell. Neither this document nor the information contained herein shall be used,
reproduced, or disclosed to others without the written authorization of Honeywell,
except to the extent required for installation or maintenance of the recipient’s
equipment. FREEDOM OF INFORMATION ACT (5 USC 552) AND DISCLOSURE
OF CONFIDENTIAL INFORMATION GENERALLY (18 USC 1905).

(2) This document is being furnished in confidence by Honeywell. The information


disclosed herein falls within exemption (b) (4) of 5 USC 552 and the prohibitions of 18
USC 1905. Copyright 2004 Honeywell. All Rights Reserved.

(3) Honeywell is a U.S. registered trademark of Honeywell. All other marks are owned by
their respective companies.

B. Export Notice

(1) This document contains unrestricted technical data and is being exported under
license exception TSU/OTS in accordance with EAR Section 740.13(a).

(2) These commodities, technology, or software were exported from the United States in
accordance with the export administration regulations. Diversion contrary to U.S. law
is prohibited. ECCN: 7E994 Schedule B#4901.99.0050

C. Special Precautions

(1) Warnings, cautions, and notes in this manual give the data that follows:
• A WARNING is an operation or maintenance procedure or condition that, if not
obeyed, can cause injury or death.
• A CAUTION is an operation or maintenance procedure or condition that, if not
obeyed, can cause damage to the equipment.
• A NOTE gives data to make the work easier or gives directions to go to a
procedure.
(2) All personnel who operate equipment and do maintenance specified in this manual
must know and obey the safety precautions. The warnings and cautions that follow
apply to all parts of this manual.
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Flight Guidance Computer / Part No. 7003974

WARNING: BEFORE YOU USE A MATERIAL, REFER TO THE MANUFACTURERS’


MATERIAL SAFETY DATA SHEETS FOR SAFETY INFORMATION. SOME
MATERIALS CAN BE DANGEROUS.

CAUTION: DO NOT USE MATERIALS THAT ARE NOT EQUIVALENT TO


MATERIALS SPECIFIED BY HONEYWELL. MATERIALS THAT ARE NOT
EQUIVALENT CAN CAUSE DAMAGE TO THE EQUIPMENT AND CAN
VOID THE WARRANTY.

CAUTION: THE FGC CONTAINS ITEMS THAT ARE ELECTROSTATIC DISCHARGE


SENSITIVE (ESDS). IN THE IPL OF THIS MANUAL, THESE ITEMS ARE
IDENTIFIED AS ESDS. IF YOU DO NOT OBEY THE NECESSARY
CONTROLS, A FAILURE OR UNSATISFACTORY OPERATION OF THE
UNIT CAN OCCUR FROM ELECTROSTATIC DISCHARGE. USE
APPROVED INDUSTRY PRECAUTIONS TO KEEP THE RISK OF
DAMAGE TO A MINIMUM WHEN YOU TOUCH, REMOVE, OR INSERT
PARTS OR ASSEMBLIES.

CAUTION: THE FGC INCLUDES PRODUCTION CRITICAL CCAS. THE PRESENCE


OF CORRECT PARTS MAKE SURE THAT THE UNIT MEETS THE
AIRWORTHINESS CRITICAL REQUIREMENTS.

2. Content Data
A. Volume History

(1) This manual was previously published as a multi--volume manual, Pub No.
A09--1147--034. The volumes and their applicable revisions were:
• Volume 1, FZ--800 Flight Guidance Computer Part No. 7003974--708, --713,
and --717
Component Maintenance Manual with illustrated parts list
Volume 1 -- Description, Operation, Maintenance Practices, and
Illustrated Parts List, Revision 0 dated 1 Mar 1992
• Volume 2, FZ--800 Flight Guidance Computer Part No. 7003974--708, --713,
and --717
Component Maintenance Manual with illustrated parts list
Volume 2 -- Testing and Fault Isolation, Revision 0 dated
1 Mar 1992
(2) This manual was merged into a single--volume and published as Pub No.
A09--1147--034, Revision 1, dated 1 Nov 2004.

B. How to Use This Manual

(1) The instructions in this manual give the data necessary to do all recommended
maintenance functions to put the FZ--800 Flight Guidance Computer (FGC) in
serviceable condition. Standard maintenance procedures that technicians are
thought to know are not given in this manual.
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Flight Guidance Computer / Part No. 7003974

(2) Refer to the table of contents to see which subheadings are included in this manual.
The table of contents identifies those subheadings that are not applicable or require
no special instructions.

(3) We recommend that the tests in TESTING AND FAULT ISOLATION be done before
the unit is disassembled. These tests can tell the condition of the FGC or most
probable cause of any malfunction. Should any malfunction occur, repair as
necessary.

(4) To decrease the length of sentences and titles, complete part numbers are not
always shown in this manual. A piece of the part number can show applicability to a
specific assembly or component on illustrations as well as in text and tables.
Complete part numbers are always given in the parts list subheading. Refer to the
introduction in the ILLUSTRATED PARTS LIST (IPL) to find how to use that
subheading.

(5) Related publications that are referred to in this manual are identified in Table Intro--1.

Table Intro--1. Related Publications


Publication Publication No. ATA No.
The United States Government Printing Office
(GPO) Style Manual 2000
Abbreviations for Use on Drawings and in Text* ASME Y14.38--1999
(Formerly ASME Y1.1--1989)
Graphic Symbols for Electrical and Electronics ANSI Y32.2 (1975)
Diagrams*
Standard Letter Symbols for Units of ANSI/IEEE Std 260 (1978)
Measurement*2
Graphic Symbols for Logic Functions* ANSI/IEEE Std 91 (1984)
Standard Repair Procedures for Honeywell A09--1100--004
Avionics Equipment Instruction Manual
FZ--600/800/820 Flight Guidance Computer A09--1147--056 22--11--92
Circuit Card Assembly Component
Maintenance Manual
STZ--100 Series Test Systems Ground A31--1146--04
Equipment Manual Vol I and III
STZ--100 Test Adapters and Card Edge A31--1146--10
Adapters for testing FZ--600/800 FGC Vol II
Ground Equipment Manual
NOTES:
1. You can order a Honeywell publication from Honeywell as follows:
Telephone No.: 602--436--6900 (domestic) or 877--484--2979 (international)
Fax No.: 602--822--7272 or 872--484--2980 (toll free)
E--mail: cas--publications--distribution@honeywell.com
2. *Available from the American National Standards Institute, New York, NY
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Flight Guidance Computer / Part No. 7003974

C. Verification

(1) Verification of these technical instructions is done by performance or by simulation of


the necessary procedures. Checks of the manual by the engineering staff make sure
the instructions and description data agree with the applicable engineering
specifications and drawings and are accurate and sufficient. The level of verification
for this manual is shown in the list that follows.

Subheading Level of Verification


Testing and Fault Isolation By performance, 9 Apr 2003
Disassembly By performance, 4 Aug 2004
Assembly By performance, 4 Aug 2004

(2) Honeywell will revise this manual as necessary to give current data. The sources for
data supplied in this manual include engineering drawings and change orders
released as of 9 Apr 2003.

D. Symbols

(1) The symbols in Figure Intro--1 may be used to identify static sensitive (ESDS) and
moisture sensitive devices.

ESDS Moisture Sensitive

Figure Intro--1. Symbols


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Flight Guidance Computer / Part No. 7003974

E. Weights and Measurements

(1) All weights and measurements are in U.S. and S.I. (metric) values.

(2) The letter symbols for units of measurement are the same as shown in the GPO
Style Manual and in ANSI/IEEE Std 260.

F. Acronyms and Abbreviations

(1) The acronyms and abbreviations that follow help the reader identify terms and
definitions used by Honeywell.

(2) The letter symbols for units of measurement are the same as shown in the GPO
Style Manual and in ANSI/IEEE Std 260.

Term Definition
A/D analog--to--digital
A/P autopilot
ANN annunciator
ANSI American National Standards Institute
AR as required
AS address strobe
ASCB avionics standard communications bus
ASCBEN ASCB enable
ASME American Society of Mechanical Engineers
assy assembly
ATA Air Transport Association
ATR Air Transport Radio
AWG American Wire Gage

B/W byte/word
BSRAMA bus RAM address
BUSEN bus enable
BUSTMRCK bus timer clock
BUSTMRCO bus timer carryout
BUSTMREN bus timer enable
BUSTMRLD bus timer load
BUSTMRUP bus timer up
CAGE Commercial and Government Entity
CCA circuit card assembly
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Flight Guidance Computer / Part No. 7003974

Term Definition
CCWE counterclockwise elevator
CE chip enable
CPU central processing unit
CS chip select
CWE clockwise elevator

D/A digital--to--analog
DISC discrete
DRIVENWA drive enable wrap around
DS data strobe
DSB data strobe buffered

ED equipment designator
eff effectivity
ELEV elevator
ELEV TRIM DR EN elevator trim drive enable
EN enable
ENG engage
EPROM erasable programmable read only memory
ESDS electrostatic discharge sensitive

FET field effect transistor


FGC Flight Guidance Computer
fig. figure
FIL filtered

HBMONINT heartbeat monitor interrupt


HMN Honeywell Material Number
HPN Honeywell part number
HSCD Honeywell specification control drawing

IEEE Institute of Electrical and Electronics Engineers


INT interrupt
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Flight Guidance Computer / Part No. 7003974

Term Definition
IPL illustrated parts list
ISO isolated

LPV latched power valid


LRN LAT STR CMD long range navigation lateral steering command
LRN_LT_S_CD long range navigation lateral steering command

MFG manufacturer
MREQ memory request

NMI nonmaskable interrupt


No. 10023 number
NVRAM nonvolatile RAM

OE output enable
ONBDIS onboard discrete
OPT optional
OV DISC overvoltage discrete

PGSEL0 page select ZERO


PREBUSINT pre--bus interrupt
PV power valid
PVB power valid buffered
PVC power valid complement
PWR power

R/W read/write
R/WB read/write buffered
RAM random access memory
RD reference designator
RD/WR read
RDPVB read power valid buffered
req required
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Flight Guidance Computer / Part No. 7003974

Term Definition
RF reference
RTx CA receive transmit clock
RVT rotary variable transformer
Rx DA receive data

S.I. International System of Units


SCC serial communications controller
SRAMs static RAMs
ST status
STRAMA static RAM address
SVO PWR EN servo power enable
SW Switched switch

TRIM SW PWR OK trim switched power OK


TRM DISC SW OFF trim disconnect switch off 102
TRxCA transmit clock (ASCB)
TxDA transmit data (ASCB)

UV DISC undervoltage discrete

VI vectored interrupt
VIACK vector interrupt acknowledge
VLD valid

WR Write
WRPVB write power valid buffered

XFR transfer

Y/D Yaw damper


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Flight Guidance Computer / Part No. 7003974

DESCRIPTION AND OPERATION


1. Physical Description
A. General

(1) The Flight Guidance Computer (FGC) is contained in a 1/2 Air Transport Radio (ATR)
short rack. The FGC has seven plug--in circuit card assemblies (CCA) A1 through A7
that plug into a motherboard assembly designated A9. Space is provided for an A8
card assembly.

(2) Filter capacitors for the 28 V dc power is contained on the motherboard. Two
double--insert connectors (J1 and J2) with polarizing keyways are mounted on the
rear of the rack. Interconnection between connectors J1 and J2 and the motherboard
is provided by a harness which utilizes solderless wire--wrap connections.

(3) The FGC is shown in Figure 1. Leading particulars for the FGC are listed in Table 1.
Table 2 lists the CCA part numbers in the FGC and the main function of each CCA.
Table 3 lists the part numbers of superseded CCAs and the end item part numbers
where they may be found. Table 4 shows the progression of part number conversions
of 7003974--708, --713, --717, --724, --725, --728, --732.

Table 1. FGC Leading Particulars


Characteristic Specification
Dimensions (maximum):
• Length 15.13 in. (38.43 cm)
• Width 4.91 in. (12.47 cm)
• Height 7.62 in. (19.35 cm)
Weight (maximum) for 70073974--708, --713, 14.1 lb (6.40 kg)
--717, --724, --725, --728, --732
Power 28 V dc, 40 W
Mating connector:
• J1 Cannon Part No. DPX2--67S--106P--33B--004
• J2 Cannon Part No. DPX2--67S--106P--33B--0017
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Figure 1. FZ--800 Flight Guidance Computer


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Flight Guidance Computer / Part No. 7003974

Table 2. Current CCA Configuration and Function


Ref Des CCA Part No. Part No. 7003974 Dash No. CCA Function
A1 7013181--902 --708, --713, --717, --724, --725, --728, --732 Power supply
A2 7007585--922 --708, --713, --717, --724, --725, --728, --732 Servo logic
A3 7007587--904 --708, --713, --717, --724, --725, --728, --732 B--processor
A4 7007589--907 --708, --713, --717, --724, --725, --728, --732 A--processor
A5 7007591--903 --708, --713, --717, --724, --725, --728, --732 Serial data interface
A6 7007593--913 --708 Direct discretes
7007593--914 --713, --717, --724, --725, --728, --732
A7 7007595--928 --708, --713, --728, --732 Analog inputs
7007595--933 --717, 724, 725
A9 7007736--910 --708, --713, --728, 732 Motherboard
7007736--914 --717, --724, --725

Table 3. Superseded CCAs


Ref Des Part No. End Item Dash No.
A1 7007583--901 --708, --713
A1 7007583--902 --708, --713
A2 7007585--901 --708, --713, --717, --724, --725, --728, --732
A2 7007585--902 --708, --713, --717, --724, --725, --728, --732
A3 7007587--901 --708
A3 7007587--902 --708, --713
A3 7009230--905 --708
A4 7007589--903 --708, --713
A5 7007591--901 --708, --713, --717, --724, --725, --728, --732
A6 7010683--903 --708
A6 7010683--903 --708
A6 7007593--903 --708
A6 7007593--904 --713, --717, --725, --728, --732
A7 7007595--905 --708, --713
A7 7007595--908 --708, --713, --728, --732
A7 7007595--913 --717, --724, --725
NOTE: The ILLUSTRATED PARTS LIST for these CCAs is in 22--11--92, Honeywell Pub. No. A09--1147--056. Before
these CCAs can be replaced, modifications may have to be made. Contact Honeywell Customer Engineering,
Glendale, AZ, for details.
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Table 4. Conversions of End Item Dash Numbers


End Item Dash No. Converted From End Item Dash No. Field Service Bulletin No.
--708 --703 21--1987--86
--713 --708 21--1988--29
--725 --717 A21--1992--168
--728 --713 A21--1999--013
--732 --728 21--1150--001

2. Functional Description
A. General

(1) A functional description of the FGC is given in the paragraphs that follow. Detailed
functional descriptions are given for each CCA. The detailed descriptions are based
on the schematic drawings of each CCA. The schematic sheets referenced in this
section are found in 22--11--92, Honeywell Pub. No. A09--1147--056.

(2) The detailed descriptions contain signal names as they are shown on the schematic
drawings. Many nonstandard abbreviations appear in these signal names. The
abbreviated signal names are defined in the text where it will aid in understanding the
function being described.

(3) Active low signals in the text are shown with an asterisk following the signal name.
The designation of an active low signal may be different on block diagrams and
schematic drawings. Some drawings and diagrams use an asterisk, some use an
overbar, and some use a diagonal to show that the signal is active low. Examples of
some active low signals are as follows:
• _____
• F772
• /F772
• F772*.
(4) Active high signals in the text or on the schematics are given without additional marks
by the signal name.

(5) The FGC supplies roll, pitch, and yaw axis control for the aircraft. Command and
error signals are processed by the FGC to drive the flight director command bars and
control the aileron, elevator, and rudder control surfaces. The major
hardware--centered circuits are:
• A-- and B--processors
• Serial communications controller
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• Bus and transfer RAMs


• Memory devices
• Digital--to--analog (D/A) converters
• Analog--to--digital (A/D) converters
• Serial data RAMs
• Bus and interrupt timers
• Heartbeat monitors
• Power supply
• Servo power relays.
(a) Processors

1 The FGC has an A--processor and a B--processor. Figure 2 is a functional


diagram that shows the internal functions, the inputs, and the outputs of the
FGC. The A--processor controls the outer loop or flight director functions and
the output to the trim servo. The B--processor controls the inner loop or
autopilot functions and the outputs to the autopilot (aileron and elevator)
servos and the yaw damper servo. Each processor monitors the other
processor’s flight control functions as well as its own.

(b) Serial Communications Controller (SCC)

1 The SCC controls the avionics standard communications bus (ASCB) which
is the link to the FGC for attitude and rate data for each axis. Figure 3 shows
the data transfer of ASCB data to the A-- and B--processors. This data
transfer is controlled by the A--processor.

(c) Bus and Transfer RAMs

1 As ASCB data is received by the SCC and the A--processor, it is stored at


the same time in the bus random access memory (RAM) where the
B--processor can access it. The A--processor does not read or write to the
bus RAM, but it does specify the start address for each bus RAM message
by means of a presettable counter. The B--processor has read--only access
to the bus RAM.

2 The transfer RAMs are used to exchange data between the two processors.
The B--to--A transfer RAM is write--only by the B--processor and read--only
by the A--processor. The A--to--B transfer RAM is write--only by the
A--processor and read--only by the B--processor. Data transfer occurs every
25 ms real--time cycle. Discrete signals exist between the processors to
strobe them into activity. All data transferred between them is by way of the
transfer RAMs.
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(d) Memory Devices

1 Both the A-- and B--processors have dedicated memory. The A--processor
has eight erasable programmable read only memories (EPROMs) and two
static RAMs for memory storage. The B--processor has six EPROMs and
four static RAMs for storage. The four bus RAMs and eight transfer RAMs
are additional storage devices.

(e) D/A Converters

1 The A--processor uses two digital--to--analog (D/A) converters to drive the


pitch and roll command bars.

(f) A/D Converters

1 There is an analog--to--digital (A/D) converter for each processor.

(g) Serial Data RAMs

1 Two types of discretes are processed by the computer: direct and serialized.
Each processor has a serial data input RAM which is used as a memory
device for serial data inputs. Each processor has a different group of direct
discrete inputs. Each discrete input and output is addressable as a word in
memory. The state of each discrete input is read on data bit 15 of the word.
The state of each discrete output is written on data bit 15 only of the word.
The state of data bits 0 thru 14 does not matter.

2 The A--processor latches the serialized discrete inputs. After latching, both
processors have independent access to the inputs.

3 The serialized discrete outputs are from the A--processor serial data output
RAM and is under the control of the A--processor.

(h) Timers

1 The A--processor sets the time for bus transactions with two counters it can
set. The bus counter and the pre--bus interrupt counter are located on CCA
A3. The bus counter controls the length of time the A--processor writes to
the ASCB bus. The pre--bus interrupt counters allow the A--processor to
write to the bus.

(i) Heartbeat Monitor

1 The processors receive a reset as a function of power--up and from a


heartbeat failure. Each processor is required to issue a heartbeat pulse
periodically. Each processor has a heartbeat monitor. Should either
processor fail to issue the required pulse within the necessary time, the
monitor will time out and drop to the invalid state.
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Figure 2. I/O Function Diagram


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Figure 3. Data Transfer

(j) Power Supply

1 The power supply consists of a main supply, isolated supply, monitoring


circuitry, power--valid logic circuitry, and a power--down timer.

2 A 28 V input is filtered through EMI and transient suppressors. The filtered


+28 V feeds a switching regulator which provides the power supply outputs:
+14.2 V dc, --14.2 V dc, +5 V main, and a +5 V standby. Hold--up circuitry is
provided to keep power valid for a short time after loss of power. The
undervoltage monitor causes a supply shutdown if input power drops below
a certain level.

3 An isolated +5 V supply is included which powers monitor and interlock


circuitry.

(k) Servo Power Relays

1 The engage logic and servo drive interface block diagram is shown in
Figure 4.

2 Servo power (+28 V) is connected to the autopilot, yaw damper, and trim
engage circuitry through the servo power relay. This relay acts as a master
power disconnect in case of a stuck relay condition within any of the engage
logic blocks. Power--off signals are fed back to both processors to indicate
the state of the relay.
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3 An interlock on the relay engagement requires that power be valid (PV


signal from the power supply monitor) and that both processors have their
servo power enable discretes set. A second interlock requires that the
heartbeat monitoring be enabled and that the heartbeat monitor for each
processor be valid.

B. Power Supply CCA A1

(1) Refer to 22--11--92, Honeywell Pub. No. A09--1147--056 for the schematic sheets
referenced in the following paragraphs. The Power Supply CCA, Part No.
7013181--902 has the following functions:
• Power supply input filtered, schematic sheet 1
• Power supply control circuit, schematic sheet 2
• Power supply outputs, schematic sheet 3
• Power supply monitors, schematic sheet 4.
(a) Power Supply Input Filtered

1 The voltages developed on this sheet are as follows:

a 28 V dc Filtered (See schematic sheet 1.)

(1) The basic aircraft power of 28 V dc comes in through the rear


connectors. The capacitor network filters the voltage for EMI. The
28 V goes through the L4 inductor to CR34 which prevents power
from going back to the aircraft bus. Going off--card throughout the
FGC is 28 VDC FIL.

b 13.6 V dc Supply

(1) The 28 V dc filtered also goes to a constant current source


consisting of Q19, R127, and VR15. The two 6.8 V diodes, VR16
and VR17, in series develop the 13.6 V supply.

c Two 5 V References

(1) Two 5 V references are developed from the voltage regulator circuit.
Constant current driving VR1, a controlled Zener diode, provides an
accurate voltage of 2.5 V to the two operation amplifiers, U2--C and
U3--B. The power supply is calibrated by selecting resistors R29
and R45 to obtain reference voltages of +5.3 V at U2--C--8 and +4.7
V at U3--B--7.
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Figure 4. Engage Logic Interlock Diagram


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(b) Power Supply Control Circuit (See schematic sheet 2.)


1 The pulse--width modulator, U9, controls the power supply and the outputs.
Figure 5 is a logic diagram of U9.
2 The square--wave output at U9--15 is a square wave that goes through the
current--amplifying circuit of Q22, Q18, Q20, and Q21 to drive the field effect
transistors (FETs) on schematic sheet 3.
3 At U9--2 is an internally--generated stabilized output voltage of 8.4 V.
4 The inputs to U9 and their functions are as follows:
• The feedback voltage at U9--3 goes to an internal operation amplifier with
an output to the pulse--width modulating circuit and to U9--4.
• U9--4 is an input from the feedback information so that the required gain
can be set by selecting the value of R151.
• U9--6 provides the voltage input to the pulse--width modulator which sets
the maximum duty cycle percentage.
• U9--7 and U9--8 are the oscillator control pins that set the frequency for
the pulse--width modulator. R158 between U9--7 and ground determines
the constant current that charges C104. The value of C104 determines
the oscillator frequency.
• U9--10 is the REMOTE ON/OFF input for the CRRNTSENSE from
schematic sheet 3 which is the current through the transformers. If the
current going into the transformers gets too high, the output of U7--A will
decrease, pulling U7--A--1 to ground and shutting the pulse-- width
modulator down.
• U9--13 is the shutdown pin. Overvoltage of the 28 V filtered source at
U8--C will shut the pulse--width modulator down. U6--C monitors the boost
circuit on schematic sheet 3 and will shut the pulse-- width modulator off
when the voltage from C24 at U6--C--10 goes too low.
• U9--16 is the feed--forward function. The duty cycle becomes inversely
proportional to this voltage.
(c) Power Supply Outputs
1 See schematic sheet 3. The output of the pulse--width modulator on
schematic sheet 2, U9--15, comes in to drive Q15. This makes a ground for
the 28 V filtered power source going through the primary coils of T1, T2, and
L2 which are in series. The CRRNTSENSE signal that goes to the
pulse--width modulator comes off T2.
2 The rectified outputs from the T1 secondary transformer windings are:
• +5 V dc through CR20
• +5 V dc standby through CR24
• +14.2 V dc through CR23
• --14.2 V dc through CR19.
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Figure 5. Power Supply Control


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3 The L2 flyback winding dumps energy through:


• CR27 for +5 V dc
• CR26 for +5 V standby
• CR21 for +14.2 V dc
• CR22 for --14.2 V dc.
4 Resistor and capacitor snubber networks come off L2--11, L2--12, L2--9,
L2--6, T1--10, T1--11, T1--12, T1--6, and T1--8.

5 The boost circuit coming off T1--8 through CR18 maintains a steady 28 V
input for the unit.

6 Under normal operation of the boost circuit:


• Q7 is on and capacitors C23 through C27 are charged to approximately
100 V
• U6--B and U8--D are high
• Q11 is on
• Q8 is off
• Approximately 100 V on signal C24 goes to U6--C on schematic sheet 2.
7 When the signal Q17 from sheet 1 drops to more than 0.6 V below 28 V
filtered:
• Q7 is turned off
• U6--B and U8--D are low
• Q11 is off
• Q8 is on
• Capacitors discharge through L1 to supplement 28 V filtered until it
returns to a level that will turn Q7 on again.
8 With the complete loss of 28 V filtered, the capacitors will continue to
discharge to keep the voltage up until it drops so low that it turns the
pulse--width modulator off through U6--C.

(d) Power Supply Monitors (See schematic sheet 4.)

1 Each voltage is monitored and compared with the 5V HI REF or 5V LO REF


voltages that were created on schematic sheet 1.
• 5 V is buffered then monitored by the top two operation amplifiers.
• +14.2 V is monitored by the next two operation amplifiers.
• --14.2 V is inverted at U4--C then monitored.
• 5 V STBY is monitored by the bottom two operation amplifiers.
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2 If any comparator outputs go low because the voltage goes out of tolerance:
• Test point TP3B goes low
• FET Q4, which creates 5 V ISO, is turned off
• 5 V ISO falls to approximately 4.5 V and is shunted immediately to
ground by Q3 and Q6.
3 Undervoltage discrete (UV DISC) and overvoltage discrete (OV DISC) are
test signals from the B--processor. If the processor turns either discrete high:
• 5 V ISO is lost
• PV is lost
• All discretes in the box are pulled LOW, including the UV DISC and OV
DISC
• 5 V ISO, PV, and all discretes return to a high
• B--processor checks to see if it was only a test.
4 The purpose of the PV monitor is to pull the PV signal low if the 5 V ISO is
lost. During the power valid monitor’s basic operation:
• U5A--2 is open
• Q9 is on
• Q12 is on
• Q10 is off
• 5 V ISO keeps 5 V dc on PV.
5 If 5 V ISO goes below 4.5 V:
• U5--A is ground
• Q9 is open
• Q12 is open
• Q10 is on
• PV is 0 V.
C. Servo Drive CCA A2 (7007585--901, --902)

(1) Refer to 22--11--92, Honeywell Pub. No. A09--1147--056, for the schematic sheets
referenced in the following paragraphs. The Servo Drive CCA, Part No. 7007585--901
and --902 contain the logic that directs power to the servo amplifiers and to the servo.
The other Servo Drive A2 CCAs described in this publication operate in an equivalent
manner; however, the other A2 CCAs can possibly contain different reference
designators.

(a) Servo Power Logic (See schematic sheet 1.)

1 Where the reference designation differs between 7007585--901 and --902,


--901 appears first with the --902 in parentheses afterwards.
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2 This card contains two relays, K2 and K3. They provide the power to
energize aileron, elevator, and elevator trim servo relays on this card and
yaw damper and rudder servo relays on CCA A7. Other logic signals are
developed on the A2 card.

a Relay K2
(1) 28 V filtered yaw damper power comes in from the motherboard.
When K2 is energized, the 28 V goes through K2--5 to CCA A7 as
+28 V switched yaw damper servo power. When K2 is not
energized, the 28 V goes through K2--4 and off--card as yaw
damper servo power off and servo power off out discretes that are
used by software.
(2) K2 is energized by emergency disconnect power. When the
emergency disconnect button is pushed in the aircraft, this circuit is
opened, K2 is opened, and yaw damper servo power is
disconnected.
(3) The ground path that completes the circuit to energize K2 is
through transistors Q7 (Q8) and Q6 (Q7). Q7 (Q8) is turned on
when power valid, B servo power enable, and A servo power
enable are high. Q6 (Q7) is turned on when CPU valid is high.
U1--7 and U1--8 switch from --13 V dc to +13 V dc when U1--5 and
U1--10 are high, and turn on transistors Q5 (Q6) through Q8 (Q9) if
Q9 (Q5) is off. Diodes CR1 and CR5 protect Q5 (Q6) through Q8
(Q9) when U1 switches from a positive to a negative voltage.
b Relay K3
(1) 28 V autopilot power at K3--2 and K3--6 creates two signals.
(a) 28 V switched autopilot signal that goes to:
-- Schematic sheet 3 to energize K7 relay for elevator servo
drive
-- Schematic sheet 4 to energize K6 for aileron servo drive
-- Schematic sheet 5 to energize K5.
(b) 28 V switched trim that goes to schematic sheet 7 (8) to:
-- Energize K4 for elevator trim servo relay
-- Energize K1 for elevator trim servo drive.
(2) When K3 is not energized, the 28 V autopilot power completes two
signals, trim servo power off and autopilot power servo off. These
signals go to a second box, when used, to tell when the servos are
off.
(3) The ground path that completes the circuit and energizes K3 is the
same as the K2 ground path.
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c Other Logic Signals


• The servo power enable signal comes from +13 V at U1--8 and is
clamped to logic level signals (0--5 V dc) by CR9 and CR10. This
signal goes off--card and to U35 (U34) on schematic sheet 2.
• The switch trim power OK, switched yaw damper power OK, and
switched autopilot power OK signals come off the open collectors in
U6 and are logic high when K2 and K3 are energized. The
comparators in U6 monitor the level of power that goes out to
J2A--42 and --44. When K2 and K3 are not energized and the voltage
at U6--4, --6, and --8 is greater than 2.1 V, U6 logic will be low.
• The +28 V autopilot power coming onto the card to the K3 relay, also
goes to the servo amplifiers shown on schematic sheets 3 and 4 as
28 V elevator signal and 28 V aileron signal.
• Q10, Q11, and Q12 form a circuit that functions as an AND gate to
monitor when the servo power relays are not energized. When yaw
damper servo off, elevator trim servo off, and autopilot servo off
signals are all 28 V dc; Q10, Q11, and Q12 are turned on which turns
Q13 on, allowing the 28 V filtered input to be output as servos off out.
(b) Digital--to--Pulse--Width Converter (See schematic sheet 2.)
1 The circuitry on this sheet commands the servo amplifier from the processor
data bus. The circuitry to drive the elevator servo is shown at the top of
schematic sheet 2. The circuitry to drive the aileron servo is shown at the
bottom of the schematic sheet. The function of the aileron servo circuitry is
the same as that for the elevator. The sequence that drives the elevator
servo is as follows:
a Data bits D7 through D14 input to U18 (U23) set the duty cycle of the
pulse width selected by the B--processor.
b Data bit D15 input to U19 (U21) flip--flop as the D input determines the
direction of travel of the elevator servo:
• When U19--5 (U21--9) is low, the direction is counterclockwise
• When U19--5 (U21--9) is high the direction is clockwise.
c The data bits are clocked into the U18 (U23) latch and the U19 (U21)
flip--flop by the elevator servo address signal, BF770*, coming in at A61.
d U22 (U24) synchronizes the direction--of--travel change with the start of
a new pulse--width cycle.

e This synchronized clock input to U33 (U35) is applied to the U21 (U27)
and U26 (U29) counters and clocks in the data bits to set the number
where the counters will start counting.
f The outputs of U33 (U35) are ANDed with the 125 kHz to set the
counter in an up--count mode or a down--count mode.
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g The counters pulse--width signal output is ANDed at U36 (U34) with the
directional signal from data bit 15 and the servo drive enable signal
which is valid if the following signals are valid:
• A/P disconnect switch off
• A/P drive enable
• CPU valid
• Switched A/P power OK
• Servo power enable.
h The output of U36 (U34) goes to the elevator servo amplifier which
provides a signal to drive the elevator servo in a clockwise or
counterclockwise direction.
i The output of the counters go low causing:
• U34--6 to go high (--U25--8 to go low)
• U34--8 to go low
• Loss of the pulse--width signal at U36 (U34)
• The counters to be inhibited until the beginning of the next cycle
when 488 Hz phase2* clocks U22--9 (U24--9) low and loads U26
(U29) and U21 (U27) with duty cycle information.
(c) Elevator Servo Drive Amplifier (See schematic sheet 3.)
1 Either of the two direction inputs from schematic sheet 2 (CWE or CCWE)
can be on or they can both be off. An on signal turns on one pair of the
FETs.
2 The +28V ELEV (+28 A/P PWR) signal from schematic sheet 1 goes directly
into the servo amplifiers.
a When the pulse--width signal created on schematic sheet 2 for
clockwise travel is applied at U39--5:
• The output at U39--7 is a square wave with an amplitude of ±13 V dc
• The output at U39--8 is --13 V dc
• Q45 is turned off
• Q46 is turned off
• Q47 conducts to K7--2
• Q44 conducts to K7--6
• K7 is energized by the 28 V SW autopilot signal from schematic
sheet 1 through the relay servo drive lo signal from schematic
sheet 5
• The square--wave duty cycle created on schematic sheet 2 is applied
to elevator servo drive hi and lo to drive the elevator servo in the
clockwise direction as determined by the processor.
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b When the pulse--width signal created on schematic sheet 2 for


counter--clockwise travel is applied at U39--10:
• The output at U39--8 is a square wave with an amplitude of ±13 V dc
• The output at U39--7 is --13 V dc
• Q44 is turned off
• Q47 is turned off
• Q46 conducts to K7--6
• Q45 conducts to K7--2
• K7 is energized by the 28 V SW autopilot signal from schematic
sheet 1 through the relay servo drive lo signal from schematic
sheet 5
• The square--wave duty cycle created on schematic sheet 2 is applied
to elevator servo drive hi and lo. This drives the elevator servo in the
counterclockwise direction as determined by the processor.
c U39--14 is the elevator motor voltage that goes back to the processor to
be monitored.

d U40 measures differential current across R160 (R168) and R162


(R170). The processor looks at this current as a means to limit the servo
motor torque.

(d) Aileron Servo Amplifier (See schematic sheet 4.)

1 The aileron servo amplifier operates the same as the elevator servo amplifier
described in paragraph 2.C.(1)(c).

(e) 200 Millisecond Timer (See schematic sheet 5.)

1 The circuitry for the 200 ms timer is at the top of the schematic.

a When PVC is valid at --14.2 V dc:


• Q21 (Q22) and Q25 (Q24) are turned off
• 10 V D/A REF comes in through CR21 (CR24) and charges
C26 (C30).
b When PVC is not valid:
• Q21 (Q22) and Q25 (Q25) turn on
• C26 (C30) discharges through R86 (R97) and Q21 (Q22) to ground
• At the end of 200 ms, the voltage at U9--10 drops below the voltage
at U9--11, the voltage determined by the voltage divider formed by
R84 (R102) and R83 (R98) across the 10 V REF signal
• The <200 ms discrete normally low signal at P1--B76 becomes high.
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c When the A--processor resets, it looks at the <200 MS DISC* signal.


• If <200 MS DISC* is high, the processor has been off for more than
200 ms so it does a cold start to restore the memory.
• If <200 MS DISC* is low, the processor has been off less than 200
ms so it reads a test word out of memory to verify the memory is still
good.
• The Q discrete input to Q24 (Q23) prevents PVC from charging back
up until the processor has had time to check the <200 MS DISC*.
(f) The Four Phases of the 488--Hz Frequency (See schematic sheet 5.)
1 The B--1953 Hz signal is divided twice by U28 (U20) to derive the 488--Hz
timing signal used by each servo. These signals combine at the U27 (U30)
decoder to give the four different phases of the 488--Hz signal. The four
phases are necessary so that all the servos do not come on at the same
time.
(g) Servo Relay
1 When the A/P ENG CMD and the A/P DISC SW OFF signals are high at
U37--12 (U38--12):
• U37--14 (U38--14) is high
• Q30 and Q31 are turned on
• Relay K5 is energized
• RELAY SVO DR LO signal energizes K6 on schematic sheet 4 and K7 on
schematic sheet 3
• +28 V SW A/P is routed through the relay to provide:
-- A/P SVO BRK DR
-- A/P SVO CL DR
-- A/P SVO RLY ON.
(h) Heartbeat Monitor Circuits (See schematic sheet 6 (6) and 7.)
1 The A--processor issues pulses to the U13 (U12) one--shot multivibrator. As
long as the pulses continue:
• U13--13 (U12--13) is high
• Q29 is turned on
• U16--14 (U15--14) high signal goes to
-- U8 where it is gated with F/D ANN DISC and LPV to provide computer
valid which goes to the flight--director--bars driver
-- U8 where it is gated with LPV and ASCB EN to provide A--bus enable
-- U14 (U13) where it is gated with LPV and B--heartbeat to provide CPU
valid
-- U14 (U13) where it is gated with LPV and ASCB EN to provide B--bus
enable.
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2 When the A--processor fails to send a pulse to U13 (U12):


• U13--13 (U12--13) goes low
• Q29 turns off
• U16--14 (U15--14) low causes the loss of:
-- COMPUTER VLD which biases the flight director bars from view
-- A--BUS EN
-- CPU VALID
-- B--BUS EN
-- A--heartbeat monitor interrupt.
3 The B--heartbeat monitor circuitry at the bottom of schematic sheet 6 is the
same as the A--heartbeat monitor circuitry except a high at U12--2 (U11--2)
enables only the CPU VALID and a low disables it.

4 When the B--processor comes on, the first activities are the nonreal--time
functions. Then it writes out to the address F77C*, connector pin B61, at
U7--11 with the LPV reset probe. This latches the +5 V ISO voltage out to
U7--9 (high) and U7--8 (low) that goes to the U10 (U9) comparator to pull the
heartbeat monitors invalid until LPV is set.

D. Servo Drive CCA A2 (7007585--922)

(1) Refer to 22--11--92, Honeywell Pub. No. A09--1147--056, for the schematic sheets
referenced in the following paragraphs. The Servo Drive CCA, Part No.7007585--922
contains the logic that directs power to the servo amplifiers and to the servo. The
other Servo Drive A2 CCAs described in this publication operate in an equivalent
manner to the 7007585--922; however, the other A2 CCAs can possibly contain
different reference designators.

(a) Servo Power Logic (See schematic sheet 1.)

1 This card contains two relays, K1 and K2. K1 and K2 provide the power to
energize aileron, elevator, and elevator trim servo relays on this card and
yaw damper and rudder servo relays on CCA A7. Other logic signals are
developed on the A2 card.

a Relay K1

(1) 28 V yaw damper power I comes in from the motherboard. When


K1 is energized, the 28 V goes through K1--5 to CCA A7 as +28 V
switched yaw damper servo power. When K1 is not energized, the
28 V goes through K1--4 and off--card as yaw damper servo power
off and servo power off out discretes that are used by software.

(2) K1 is energized by emergency disconnect power. When the


emergency disconnect button is pushed in the aircraft, this circuit is
opened, K1 is opened, and yaw damper servo power is turned off.
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(3) The ground path that completes the circuit to energize K1 is


through transistors Q22 and Q25. Q22 is turned on when power
valid, B servo power enable, and A servo power enable are high.
Q25 is turned on when CPU valid is high. U5--7 and U5--8 switch
from --13 V dc to +13 V dc when U5--5 and U5--10 are high, and
turn on transistors Q22 thru Q25 if Q18 is off. Diodes CR9 and
CR17 protect Q22 thru Q25 when U5 switches from a positive to a
negative voltage. If Q18 is on, Q25 and Q23 are off which sends
the CPU VALID signal to protection.
b Relay K2
(1) 28 V autopilot power at K2--2 and K2--6 creates two signals.
(a) 28 V switched autopilot servo power signal that goes to:
• Schematic sheet 3 to energize K6 relay for elevator servo
drive
• Schematic sheet 4 to energize K7 for aileron servo drive
• Schematic sheet 5 to energize K3 for autopilot servo drive.
(b) 28 V switched trim servo power that goes to schematic sheet 8
to:
• Energize K4 for elevator trim servo relay
• Energize K5 for elevator trim servo drive.
(2) When K2 is not energized, trim servo power off and autopilot servo
power off are high. If these signals are on, the cross--side autopilot
knows that the servos are off.
(3) The ground path that completes the circuit and energizes K2 is the
same as the K1 ground path.
(b) Other Logic Signals
1 The following describes the other logic signals and circuitry on the CCA.
a The servo power enable signal comes from +13V at U5--8 and is
clamped to logic level signals (0 to 5 V dc) by CR11 and CR12. This
signal goes off--card and to U31 on sheet 2.
b The switched trim power OK, switched yaw damper power OK, and
switched autopilot power OK signals come off the open collectors on U4
and are logic high when K1 and K2 are energized. The comparators of
U4 monitor the voltage that goes out to J2A--42 and --44. When K1 and
K2 are not energized and the voltage at U4--4, --6, and --8 is greater
than 2.1 V, U4 logic will be low.
c The +28 V autopilot power that enters the card and goes to the K2 relay
also powers the servo amplifiers shown on sheet 3 and sheet 4. These
amplifiers feed the HI_ELEV_SVO_DR and LO_ELEV_SVO_DR signals
on sheet 3 and the HI_AIL_SVO_DR and LO_AIL_SVO_DR signals on
sheet 4.
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d Q19, Q15, and Q16 form a circuit that functions as an AND gate to
monitor when the servo power relays are not energized. When yaw
damper servo off, elevator trim servo off, and autopilot servo off signals
are all 28 V dc; Q19, Q15, and Q16 are turned on, which turns Q20 on,
and allows the +28 V to the servos off out.

(c) Digital--to--Pulse--Width Converter (See schematic sheet 2.)

1 The circuitry on this sheet commands the servo amplifier’s pulse width from
the processor data bus. The circuitry to drive the elevator servo is shown at
the top of schematic sheet 2. The circuitry to drive the aileron servo is shown
at the bottom of the schematic sheet. The function of the aileron servo
circuitry is the same as that for the elevator. The sequence that drives the
elevator servo is as follows:

a Data bits D7 thru D14 input to U19 set the duty cycle of the pulse width
selected by the B--processor.

b Data bit D15 input to U27 and U34 flip--flops as the D input determines
the direction of travel of the elevator servo:
• When U34--9 is low, the direction is counterclockwise
• When U34--9 is high the direction is clockwise.
c The data bits are clocked into the U19 latch and the U27 flip--flop by the
elevator servo address signal, BF770*, coming in at A61.
d U18 synchronizes the direction--of--travel change with the start of a new
pulse--width cycle.

e This synchronized clock input to U34--11 is applied to the U32 and U28
counters and loads in the data bits to set the number where the
counters will start counting.
f The outputs of U34 are ANDed with the 125 kHz to set the counter in an
up--count mode or a down--count mode.

g The counters pulse--width signal output is ANDed at U21 with the


directional signal from data bit 15 and the servo drive enable signal,
which is valid if the following signals are valid:
• A/P disconnect switch off
• A/P drive enable
• CPU valid
• Switched A/P power OK
• Servo power enable.
h The outputs of U21 go to the elevator servo amplifier, which provides a
signal to drive the elevator servo in a clockwise or counterclockwise
direction.
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i The output of the counters go low causing:


• The active gate, either U21--8 or U21--12, to go low
• Loss of the pulse--width signal at U21
• The counters to be inhibited until the beginning of the next cycle
when 488 Hz phase2* clocks U18--9 low and loads U28 and U32 with
duty cycle information.
2 The sequence that drives the aileron servo is as follows:
a Data bits D7 thru D14 input to U20 for the aileron servo set the duty
cycle of the pulse width selected by the B--processor.
b Data bit D15 input to U27 and U34 flip--flops as the D input determines
the direction of travel of the elevator servo:
• When U34--5 is low, the direction is counterclockwise
• When U34--5 is high the direction is clockwise.
c The data bits for the aileron servo address signal, BF772* coming in at
A60, are clocked into the U20 latch and the U27 flip--flop.
d U22 synchronizes the direction--of--travel change with the start of a new
pulse--width cycle.
e This synchronized clock input to U34--3 is applied to the U24 and U33
counters, and loads in the data bits to set the number where the
counters will start counting.
f The output rotational directions of U34 are ANDed with the 125 kHz
signal through U26 and U25 to set the counter U33 in an up--count
mode or a down--count mode.
g The counters pulse--width signal output is ANDed at U31 with the
directional signal from data bit 15 and the servo drive enable signal,
which is valid if the following signals are valid:
• A/P disconnect switch off
• A/P drive enable
• CPU valid
• Switched A/P power OK
• Servo power enable.
h The output of U31 goes to the aileron servo amplifier, which provides a
signal to drive the aileron servo in a clockwise or counterclockwise
direction.
i The output of the counters go low causing:
• The active gate, either U31--6 or U31--12, to go low
• The counters to be inhibited until the beginning of the next cycle
when 488 Hz phase3* clocks U22--5 low and loads U33 and U24 with
duty cycle information.
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(d) Elevator Servo Drive Amplifier (See schematic sheet 3.)


1 Either one of the two direction inputs from sheet 2 (CWE or CCWE) can be
on or they can both be off. An on signal turns on one pair of the FETs.
2 The +28V A/P POWER from schematic sheet 1 goes directly into the servo
amplifiers.
a When the pulse--width signal created on schematic sheet 2 for
clockwise travel is applied at U37--3:
• The output at U37--1 is a square wave with an amplitude of ±13 V dc
• The output at U37--14 is --13 V dc
• Q40 is turned off
• Q42 is turned off
• Q43 conducts to K6--2
• Q41 conducts to K6--6
• K6 is energized by the 28V SW A/P SVO PWR from schematic
sheet 1 through the relay servo drive lo signal from schematic
sheet 5.
• The square--wave duty cycle created on schematic sheet 2 is applied
to elevator servo drive hi and lo to drive the elevator servo in the
clockwise direction as determined by the processor.
b When the pulse--width signal created on schematic sheet 2 for
counter--clockwise travel is applied at U37--12:
• The output at U37--14 is a square wave with an amplitude of
±13 V dc
• The output at U37--1 is --13 V dc
• Q41 is turned off
• Q43 is turned off
• Q42 conducts to K6--6
• Q40 conducts to K6--2
• K6 is energized by the 28V SW A/P SVO PWR from sheet 1 through
the relay servo drive lo signal from schematic sheet 5
• The square--wave duty cycle created on schematic sheet 2 is applied
to elevator servo drive hi and lo. This drives the elevator servo in the
counterclockwise direction as determined by the processor.
c U35--6 is the elevator motor voltage that goes back to the processor to
be monitored.
d U38 measures differential current across R206 and R207. The
processor looks at this current as a means to limit the servo motor
torque.
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(e) Aileron Servo Amplifier (See schematic sheet 4.)

1 The aileron servo amplifier operates in an equivalent manner to the elevator


servo amplifier.

a When the pulse--width signal created on schematic sheet 2 for


clockwise travel is applied at U37--5:
• The output at U37--7 is a square wave with an amplitude of ±13 V dc
• The output at U37--8 is --13 V dc
• Q44 is turned off
• Q46 is turned off
• Q47 conducts to K7--2
• Q45 conducts to K7--6
• K7 is energized by the 28V SW A/P SVO PWR from schematic sheet
1 through the relay servo drive lo signal from schematic sheet 5
• The square--wave duty cycle created on schematic sheet 2 is applied
to aileron servo drive hi and lo to drive the aileron servo in the
clockwise direction as determined by the processor.
b When the pulse--width signal created on schematic sheet 2 for
counter--clockwise travel is applied at U37--10:
• The output at U37--8 is a square wave with an amplitude of ±13 V dc
• The output at U37--7 is --13 V dc
• Q45 is turned off
• Q47 is turned off
• Q46 conducts to K7--6
• Q44 conducts to K7--2
• K7 is energized by the 28V SW A/P SVO PWR from sheet 1 through
the relay servo drive lo signal from schematic sheet 5
• The square--wave duty cycle created on schematic sheet 2 is applied
to aileron servo drive hi and lo. This drives the aileron servo in the
counterclockwise direction as determined by the processor.
c U36--6 is the aileron motor voltage that goes back to the processor to
be monitored.

d U39 measures differential current across R209 and R208. The


processor looks at this current as a means to limit the servo motor
torque.
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(f) 200 Millisecond Timer (See schematic sheet 5.)


1 The circuitry for the 200ms timer is at the top of the schematic.
a When PVC is valid at --14.2 V dc:
• Q7 and Q8 are turned off
• 10 V D/A REF comes in through CR8 and charges C23.
b When PVC is not valid:
• Q7 and Q8 turn on
• C23 discharges through R51, R55 and Q7 to ground
• At the end of 200 ms, the voltage at U3--10 drops below the voltage
at U3--11, the voltage determined by the voltage divider formed by
R52, R73 and R72 across the 10 V REF signal
• The <200 ms discrete normally low signal at P1--B76 goes high.
c When the A--processor resets, it looks at the <200 MS DISC* signal.
• If <200 MS DISC* is high and the processor has been off for more
than 200 ms, so it does a cold start to restore the memory.
• If <200 MS DISC* is low and the processor has been off less than
200 ms, it reads a test word out of memory to verify if memory is still
good.
• The Q discrete input to Q11 prevents PVC from charging back up
until the processor has had time to check the <200 MS DISC*.
(g) The Four Phases of the 488--Hz Frequency (See schematic sheet 5.)
1 The B--1953 Hz signal is divided twice by U29 to derive the 488--Hz timing
signal used by each servo. These signals combine at the U30 decoder to
give the four different phases of the 488--Hz signal. The four phases are
necessary so that all the servos do not come on at the same time.
(h) Servo Relay
1 When the A/P ENG CMD and the A/P DISC SW OFF signals are high at
U2--3:
• U2--1 is high
• Q27 and Q30 are turned on
• Relay K3 is energized
• RELAY SVO DR LO signal energizes K7 on sheet 4 and K6 on
sheet 3
• +28 V SW A/P servo power is routed through the relay to provide:
-- A/P SVO BRK DR
-- A/P SVO CL DR
-- A/P SVO RLY ON.
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(i) Heartbeat Monitor Circuits (See schematic sheets 6 and 7.)


1 The A--processor issues pulses to the U16 one--shot multivibrator (sheet 7).
As the pulses continue:
• U16--13 is high
• Q26 is turned on
• U6--14 high signal goes to:
-- U8 where it is gated with F/D ANN DISC and LPV to provide
COMPUTER VLD, which goes to the flight--director--bars driver
-- U8 where it is gated with LPV and ASCB EN to provide A--bus enable
-- U9 where it is gated with LPV and B--heartbeat to provide CPU valid
-- U9 where it is gated with LPV and ASCB EN to provide B--bus enable.
2 When the A--processor fails to send a pulse to U16:
• U16--13 goes low
• Q26 turns off
• U6--14 low causes the loss of:
-- COMPUTER VLD which biases the flight--director--bars from view
-- A--BUS EN
-- CPU VALID
-- B--BUS EN
-- A--heartbeat monitor interrupt.
3 The B--heartbeat monitor circuitry at the bottom of schematic sheet 7 is
equivalent to the A--heartbeat monitor circuit except that a high at U7--2
enables the CPU VALID signal only and a low disables the CPU VALID
signal. The B--heartbeat monitor circuit has no effect on the COMPUTER
VLD signal. See schematic sheets 6 and 7. The B--processor issues pulses
to the U16 one shot multi--vibrator (sheet 7). As the pulses continue:
• U16--5 is high
• Q29 is turned on
• U7--2 high signal goes to:
-- U9 where it is gated with B--F77C* and B--heartbeat (B--HBM_PULSE)
to provide CPU valid
-- U9 where it is gated with B--F77C* and ASCB EN to provide B--bus
enable.
• When the B--processor comes on, the first activities are the
non--real--time functions. Then it writes out to the address B--F77C*,
connector pin B61, at U11--11 with the LPV RESET STROBE.
• This latches the +5 V ISO voltage out to U11--9 (high) and U11--8 (low)
that goes to the (U3) comparator to pull the heartbeat monitors invalid
until LPV is set.
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4 When the B--processor fails to send a pulse to U16:


• U16--5 goes low
• Q29 turns off
• U7--2 low causes the loss of:
-- CPU VALID
-- B--BUS EN
-- B--heartbeat monitor interrupt.
(j) Elevator Trim Servo Amplifier (See schematic sheet 8.)

1 This servo amplifier is similar to the ones shown on sheets 3 and 4 for the
elevator and the aileron, with the following differences:

a The elevator trim servo amplifier is written to directly with discretes from
the B--processor, CW at B42, and CCW at B43.

b There are two relays controlled by trim discrete switch off and elevator
trim engage command:
• K4 provides the +28V to the elevator trim servo clutch drive and
elevator trim servo relay when it is energized and the elevator trim
servo off signal when it is not energized.
• K5 provides power to the elevator trim servo drive when it is
energized.
c +28 V is input to T1 transformer for the power to the servo amplifier.

E. B--Processor CCA A3

(1) Refer to 22--11--92, Honeywell Pub. No. A09--1147--056, for the schematic sheets
referenced in the following paragraphs. The B--processor CCA, Part No.
7007587--904 performs the following functions:
• Processor inputs and outputs -- schematic sheet 10
• Processor controls -- schematic sheet 1
• EPROM memory -- schematic sheets 2 and 3
• Decoding -- schematic sheet 4
• Interrupts -- schematic sheet 6
• Bus counters -- schematic sheet 7
• ASCB -- schematic sheets 5 and 8
• Static RAMs -- schematic sheet 9.
(2) Figure 6 shows the bus diagram. Data and addresses from the processor are
multiplexed onto the bus lines. The bus goes to four transparent latches and four
transceivers. Data can be transmitted from off--card to the processor through the
transceivers.
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(3) Addresses demultiplexed by the transparent latches U57 and U64 go off--card.

(4) Transceivers U69 and U58 take data off the multiplexed bus coming out of the
processor and send it off--card when they transmit from A to B. When U69 and U58
are transmitting from B to A, the transceivers are putting data onto the bus and the
processor is taking information off the bus.

(5) U51 and U65 latch the addresses out to the EPROMs and the RAMs. The output of
the EPROMs go through transceivers U53 and U68 in the direction B to A and back
onto the multiplexed bus. When the processor is doing a WRITE to the RAMs, U53
and U68 transmit from A to B.

(a) B--Processor (See schematic sheet 10.)

1 The B--processor is U61. The outputs from the processor are on the right
(looking at the schematic) or bus side. The left side of the processor is the
input side.

a B--Processor Outputs

(1) Multiplexed lines (addresses and data multiplexed) are as follows:


• B--M0 through B--M15 go throughout the card
• Address lines B--A0 through B--A15 go off--card after U64 and
U57 latch the addresses.
(2) Control lines that enable all devices are written to or read from on
the multiplexed bus:
• AS* (address strobe), low whenever address information on the
bus is valid, gets inverted at U48 and latches data that was set
up in U64, U57, U51, and U65
• DS* (data strobe), low whenever data on bus is valid
• B--WR* created when B--R/W* is ORed with DS* for controls that
indicate data is valid and the processor is doing a write function
• B--RD* created when B--R/W* is inverted and ORed with DS* for
controls that indicate data is valid and the processor is doing a
read function
• B--B/W* (byte/word), low for full word (16 bit) READ or WRITE;
high for byte (8 bit) READ or WRITE.
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Figure 6. CCA A3 Bus Diagram

b B--Processor Inputs
• RESET*, generated on schematic sheet 1 from the heartbeat monitor
and power valid signals, resets the processor in the absence of either
signal.
• CLK comes through the Y1 crystal, AND gates, and four inverters to
meet the rise and fall time specification to generate the 4--MHz clock
for the processor.
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• WAIT signal through AND gate U59 will put the processor into a
WAIT state during any of the following:
-- Transfer RAM enable
-- D to A output
-- A to D output.
• B--MREQ* (memory request), output that goes low during a
MEMORY READ and used in some of the timing to enable memory
that is slower.
• ST0 through ST3 (status), gated at U46 for the B--VIACK* (vector
interrupt acknowledge) signal; B--ST3 goes off--card.
(b) B--Processor Control Signals and Bus Timer Clock Signals (See schematic
sheet 1.)

1 Figure 7 shows the signals that control the B--processor.

a WAIT*

(1) When the processor tries to write to the addresses for the transfer
RAMs, the A/D converter, or the D/A converter on other cards, or
tries to read from those addresses, one WAIT pulse is started. The
address input to U38 flip--flop is clocked by B--CLK and cleared by
DS* to generate a 1--clock cycle wait.

b RESET*

(1) Whenever PVB (power valid buffered) goes low or B--HBMONINT


(B--processor heartbeat monitor interrupt) is tripped, the processor
is reset.

2 Bus timer clock signals, generated by B--CLK input to binary counter U45
and shown in Figure 7, are:
• B--1 MHz
• B--125 kHz
• B--1953 Hz
• A 2--MHz signal that clocks flip--flops U18 and U38 for these Q outputs:
-- BUSTMRUP (bus timer up) used on schematic sheet 7 sets bus timers
to count up
-- BUSTMRCK (bus timer clock) used on schematic sheet 7 clocks data
out of bus timers.
• Binary counter U66 generates B8.320 MSEC--RTI used on schematic
sheet 6 for interrupt control.
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(c) EPROMs (See schematic sheets 2 and 3.)

1 The six EPROMs can be put in parallel. The multiplexed lines that carry
both data and addresses, B--M0 through B--M15, come from the
B--processor and go to all of the EPROMs. The addresses for the EPROMs
are latched by U51 and U65 which are controlled by AS* and PV as shown
in Figure 8.

2 When the processor reads from the EPROMs, data outputs B--DM0 through
B--DM15 go through bidirectional buffers U53 and U68. During the READ,
OE* for the EPROMs is active low and U53 and U68 are transmitting from B
to A. This places the data from the EPROMs onto the multiplexed bus B--M0
through B--M15. When the processor writes to the RAMs, U52--6 will be high
and U53 and U68 will transmit from A to B.

3 U53 and U68 are enabled as shown in Figure 8. When the processor is
doing a memory operation, the signals coming into U46 will be high. B--ST3
is high anytime the processor is doing a memory operation. B--ONBDIS
(onboard discrete) stays high except during external test.

4 The chip select lines that control each EPROM are decoded on schematic
sheet 4.

(d) Static RAMs (See schematic sheet 9.)

1 The address lines coming into the four RAMs are B--AM1 through B--AM11.
Figure 8 shows the control lines to the RAMs. When B/W* is low, two RAMs
at a time are enabled so that a full word address can be read and output to
the data bus B--DM0 through B--DM15.
• RAMs U49 and U62 are selected for address range C000 through CFFF.
• RAMs U55 and U43 are selected for address range D000 through DFFF.
2 If a byte read is done, B/W* must be high. B--AM0 (on schematic sheet 4)
selects either upper or lower byte.

3 The RAMs are write enabled when the B--processor is doing a WRITE. The
RAMs are output enabled when the B--processor is doing a READ.
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Figure 7. B--Processor Controls


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Figure 8. EPROM, RAM, Transceiver and Latch Controls


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(e) Decoding (See schematic sheet 4.)


1 The U60 dual decoder is enabled by ST3*. This line is low during a
processor memory operation. The decoder also brings in the four most
significant bits from the address bus, B--A12 through B--A15, and decodes
the B--EXXX and B--FXXX addresses. The B--PGSEL0 (page select ZERO)
comes in from the A5 card and is used to create the chip selects used as
EPROM controls.
2 Decoding of the RAM chip select lines are shown on this schematic sheet.
Decoded addresses go to gates U72 and U74 with PVB brought in to
maintain RAM memory during the 200 ms power down. U72 and U74 are
powered by +5 V standby to maintain RAM memory during the power down.
3 PVB is also used with B--RD and B--WR* to create B--RDPVB* and
B--WRPVB*.
4 Decoder U26 receives bits B--A1 and B--A3 from the B--processor along with
B--DS* and B--F77X* to decode some specific addresses.
5 U31 receives address lines A1 thru A3 from the A--processor along with
A--DSB*, A--R/W*, and A--F98X*. U31 decodes bus and pre--bus interrupt
counter and an interrupt address.
(f) ASCB and Bus Select (See schematic sheets 5 and 8.)
1 The bus select circuitry decides whether the A--processor or the
B--processor has access to the bus RAM located on CCA A4.
2 Figure 9 shows the ASCB controls. B/A* BUS SEL comes from the
A--processor to the four--bit digital multiplexer U6. It determines whether
A--BUS DATA and A--BUS CLK or B--BUS DATA and B--BUS CLK are
selected as the Rx DA (receive data) transmit line and RTx CA* (receive
transmit clock) signals that go to the serial communications controller on
CCA A4.
3 U2 and U3 are bus--busy detectors. U3 looks at the A--bus and sends an
ACTV BUS BUSY signal to CCA A6. U2 looks at the B--bus and sends a
STBY BUS BUSY signal to CCA A6. This prevents transmitting on top of
another signal.
4 The 4/3 MHz signal comes from off--card. It is divided by two at U4, creating
TRxCA*, the 2/3 MHz (660 kHz) basic ASCB frequency.
5 The ASCB system for the A--processor or active bus has two inductors T1
and T2 driven by U10 which isolate the bus from the computer. Manchester
data comes through U10 to the inductors and onto the ASCB bus. The data
also goes to U11 receiver where A BUS DATA and A BUS CLK is output.
The ASCB system for the B--processor or standby bus is shown at the
bottom of Figure 9. The B--bus system uses the U7 receiver, powered by 5 V
ISO, to transmit to the U14 driver in case something happens to the 5 V
supply.
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6 Manchester encoded data is output by the J--K flip--flop U17 which is


clocked by the 4/3 MHz signal.
7 The ASCBEN (ASCB enable) line is a discrete from the processor that
enables the ASCB bus.
8 A--BUSEN and B--BUSEN enable the U10 and U14 drivers that drive the
A--bus and B--bus.

9 PVC (power valid complement) comes from CCA A1 into Q2 which will short
to ground without the PVC signal present. If PVC is lost, the computer goes
off both buses.
10 The A--DRIVENWA and B--DRIVENWA (drive enable wrap around) are input
discretes (CCA A6) back to the processor to verify the drivers have been
enabled and are putting data on the bus.
(g) B--Processor Interrupts (See schematic sheet 6.)
1 The CCA A3 interrupt inputs get masked after they are latched. The inputs
are:
• A--HB MON INT
• B--8.320 MSEC RTI*
• A--F98E* address (clock)
• SPARE INT.
2 The interrupt mask register, U71 hex D--type flip--flop, controls the masking.
The B--data bus writes to U71 with six bits. Four are used to select the
interrupt it wants to enable or disable. The interrupt numbers (e.g., Int 8)
adjacent to the NAND gates in Figure 10 are associated with U79, the
priority encoder which selects the highest interrupt number first.
a A--Processor Heartbeat Monitor Interrupt

(1) When the A--heartbeat monitor is tripped:


• The B--processor clocks a 1 into U73--5 and latches it
• If the B--processor is in a sequence that cannot be interrupted, it
masks the interrupt at the hex D--type flip--flop U71
• When the sequence ends, the B--processor writes to U71 which
enables U80
• The signal is ANDED with the heartbeat monitor interrupt, still
latched at U73
• The transparent latch U78 latches the interrupt signals when
B--VIACK* goes low
• The latched interrupt signals go to the 10--line to 4--line encoder,
U79, and produces a four--bit code representing the highest
priority vectored interrupt
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Figure 9. ASCB Controls


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Figure 10. Interrupt Controls


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• The four--bit code pulls U52--11 low and creates the vectored
interrupt (B--VI*) signal to the B--processor to tell it there is an
interrupt
• The B--processor goes through a vectored--interrupt--
acknowledge sequence, pulling the B--VIACK* line low to shut off
the U78 latch and hold the data until the processor can
determine the source of the interrupt
• The code from U79 also goes to the U70 buffer
• The B--processor now looks for the interrupt, and the READ
signal from the processor gets ANDED with an inverted
B--VIACK* and DS* to enable U70
• U70 places the vectored interrupt code on the data bus where
the B--processor reads it and looks the number up in a table to
obtain the address where the corrective action is stored in
memory
• The same vectored interrupt code goes to U84 to produce a low
at pin 10 which combines with B--INT CLEAR to clear the U73
flip--flop where the interrupt started
• INT 2 is cleared by CL INT 5 (see Figure 10) because the
CLEAR signal at U84 is inverted (2 complemented = 5).
b The B--processor processes B--8.320 MSEC RTI*, A--F98E* address
signal, and SPARE INT the same as A--HB MON INT, except for the pin
numbers.

c Transceivers U58 and U69 create data bus signals B--D0 through
B--D15 as shown in Figure 6. When the processor does an I/O READ or
WRITE, B--FXXX* and B--EXXX* are low and the transceivers are
enabled. (See Figure 8.)

(1) The direction of U58 and U69 is set by B--RD/WR* and DS* as
shown in Figure 9:
• Direction A to B creates the data bus signals
• Direction B to A puts data on the multiplexed bus and directs it to
the processor.
(h) Bus and Pre--Bus Interrupt Counters (See schematic sheet 7.)

1 The A--processor writes to the bus--timer carryout counters U23, U24, U30,
and U35 at address F984 (see Figure 11). The A--processor loads the
counters with the amount of time it needs to write to the ASCB. The length
of the message will determine the time of the count. If the counters ripple
over before the A--processor is through writing to the bus, U23--12 goes low
and creates the signal BUSTMRCO* (bus timer carryout) to the A--processor
as an interrupt. Figure 12 shows the bus counter control lines.
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2 BUSTMRLD loads the counters with data from the A--data bus and keeps
U18--9 cleared so that BUSTMRUP does not begin counting until after the
loading is completed.

3 BUSTMRCK clocks data out of the counters into flip--flops U21 and U29 and
onto the A--data bus.

4 BUSTMREN* enables the flip--flops to place data on the A--data bus during
an A--processor READ.

5 A second set of counters, U19, U20, U28, and U33, and flip--flops U22 and
U34 determine when the A--processor is allowed to write on the ASCB bus.
The A--processor writes to these counters at address A--F986*. When the
counters ripple over, the PREBUSINT* (pre--bus interrupt) signal is created
to allow the A--processor to write to the bus.

6 U21, U22, U29, and U34 latch the counter outputs onto the A--data bus.

Figure 11. Bus Interrupt Synchronous Up--Counter Bus Diagram


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Figure 12. Bus Counter Controls


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F. A--Processor CCA A4
(1) See schematics in 22--11--92, Honeywell Pub. No. A09--1147--056, for Part No.
7007589--907. This CCA is primarily the A--processor card. The functions of CCA A4
and the schematic sheets on which the functions can be found are:
• A--processor -- schematic sheet 2
• A--to--B transfer RAMs -- schematic sheets 3 and 4
• Serial communication controller -- schematic sheet 5
• EPROMs -- schematic sheets 6, 7, and 10
• B--to--A transfer RAMs -- schematic sheet 8
• Bus RAMs -- schematic sheet 12
• Up counters -- schematic sheet 13.
(2) The bus diagram for CCA A4 is shown in Figure 13. The multiplexed bus from the
A--processor mixes data and addresses. The bus goes to two transparent latches,
two transceivers, a bus RAM, and a serial communications controller.
(3) The transparent latches U19 and U26 latch the addresses from the multiplexed bus.
The addresses go off the card at P1 connector pins B54 -- B69 and to the U66 and
U88 multiplexers. U19 and U26 are enabled by AS* (address strobe). The latched
addresses from the second set of latches, U33 and U35, are used for the decode on
the memory group of EPROMs and static RAMs. U33 and U35 are enabled by AS*
and PV.
(4) Data transmitted through the transceivers U11 and U16 from B to A, go to the A--to--B
transfer RAMs U51, U61, U69, and U77. Data received through the transceivers from
A to B comes from the B--to--A transfer RAM or from the onboard memory in the
EPROMs and the SRAMs.
(5) A second pair of transceivers, U8 and U30, transmit data from the A--processor to the
up counters or off the card at connector pins B46 -- B53 and B70 -- B77. The B--to--A
direction in the transceivers receives data that the A--processor is reading from
off--card.
(6) The data bus also goes to the serial communications controller which transmits and
receives ASCB data from off the card.
(7) The address bus from the A--processor and the address bus from the B--processor,
shown coming on--card at connector pins B10 through B24, are multiplexed by U66
and U88 and input to the transfer RAMs over the STRAMA (static RAM address) bus.
The addresses selected decide whether the A--processor or the B--processor controls
the transfer RAMs.
(8) Data transmitted from one processor to the other processor must go through the
transfer RAMs or the bus RAMs. Both processors can write to the transfer RAM and
are able to read what the other processor writes. The U70 and U82 transceivers
transmit from B to A when the B--processor writes data to the B--to--A transfer RAM,
and from A to B when the B--processor reads data from the A--to--B transfer RAM.
The A--processor reads data from the B--to--A transfer RAM over the same lines it
uses to write to the A--to--B transfer RAM.
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(9) A starting address from the A--processor is loaded into the up counters. The counter
offloads the processor and increments the address a byte at a time. When the
B--processor reads data from the bus RAM, multiplexers U58 and U75 select a
B--address.

(a) A--Processor

1 The A--processor on the 7007589--907 unit is a 6--MHz CPU.

a A--Processor Inputs
• VI* (vectored interrupt) comes from off--card.
• NMI* (nonmaskable interrupt) line comes from to CCA A8 and is
used only for test.
• WAIT* comes from three sources (see Figure 14). Table 5 shows the
WAIT states needed for the CPU.
-- A--WAIT 3 comes from the A/D on CCA A5
-- A--WAIT 2 comes from the WAIT circuitry on schematic sheet 9
-- A--WAIT 1 comes from the serial communications controller on
schematic sheet 5.

Table 5. WAIT States for the A--Processor


Wait States
Address Description
(Clock Cycles)
Range
--907
F000--F3FF Transfer RAM Enable 1
F400--F8FF I/O Enable 1
F900--F90F D to A Output 2
F910--FDFF I/O Enable 1
FE00--FFFF Bus RAM Enable 2

• Reset comes from schematic sheet 15. The processor is reset by a


low power valid or from an incoming high heartbeat signal to the
flip--flop U46 which starts the U48 binary counter. If the heartbeat
signal is lost for some specified length of time, the counter sends a
reset signal, U48--11, that is gated with PV. Either signal is able to
reset the processor.
• Clock comes through the Y1 crystal, AND gates, and four inverters to
meet the rise and fall time necessary for the right frequency.
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Figure 13. CCA A4 Bus Diagram


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Figure 14. Transceiver and Microprocessor Controls


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b A--Processor Outputs

(1) In addition to the multiplexed bus, the outputs from the A--processor
are control lines that go throughout the card as well as being
buffered before going off the card as follows:
• A--AS*, low whenever address information on bus is valid
• A--DS*, low whenever data on bus is valid
• A--MREQ*, used as a control line for memory devices
• A--RD*, processor READ combined with DS* to indicate data is
valid and processor is reading it
• A--WR*, processor WRITE combined with DS* to indicate the
processor is writing valid data
• A--B/W*, indicates a byte or a word function
• STATUS 0, 1, and 2 are combined with ST 3 inverted for
A--VIACK
• ST 3, used to decode memory operations.
(b) A--to--B Transfer RAMs (See schematic sheets 3 and 4.)

1 Four transfer RAMs, U51, U61, U69, and U77 have four input pins each to
handle the A--DM0 through A--DM15 bus from the A--processor. The four
output pins on each RAM send the data to the B--processor over BB--D0
through BB--D15.

2 The input address lines to the RAMs, STRAMA0 (status RAM address)
through STRAMA7 are A--processor and B--processor addresses
multiplexed by U66 and U88. The A--processor controls the RAMs when the
A--processor is writing to them, and the B--processor controls the RAMs
when the B--processor is reading from them. The two 2--to--1 multiplexers
are enabled by a B/A* SELECT signal coming from the B--processor at
connector pin A74.

3 The control lines to the RAMs are multiplexed by U85. These lines have to
be controlled by the processor that controls the addressing to the RAMs. For
that reason, this multiplexer is enabled by the same B/A* SELECT signal
that enables the address multiplexing. Figure 15 shows the control lines to
the RAMs and their origin.

(c) B--to--A Transfer RAMs (See schematic sheet 8.)

1 Four transfer RAMs, U56, U65, U73, and U81 have four input pins each to
handle the BB--D0 through BB--D15 bus from the B--processor. The four
output pins on each RAM send the data to the A--processor over A--DM0
through A--DM15. Figure 15 shows the control lines to the RAMs and their
origin.
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2 The input address lines to the RAMs, STRAMA0 through STRAMA7 are
A--processor and B--processor addresses muxed by U66 and U88. The
B--processor controls the RAMs when the B--processor is writing to them
and the A--processor controls the RAMs when the A--processor is reading
from them. The two 2--to--1 muxes are enabled by a B/A* SELECT signal
coming from the B--processor at connector pin A74.

3 The control lines to the RAMs are muxed by U89. These lines have to be
controlled by the processor that controls the addressing to the RAMs. For
that reason, this mux is enabled by the same B/A* SELECT signal that
enables the address muxing.

(d) Bus RAMs (See schematic sheet 12.)

1 The four bus RAMs, U52, U57, U74, and U78 are the same devices as the
transfer RAMs and operate much the same way. The four--pin inputs each
combine in pairs to handle eight bits from the A--processor multiplexed bus,
A--M0 through A--M7. Data comes from the ASCB bus a byte at a time, but it
is stored in the RAMs as 16--bit words, made up of upper and lower bytes.
The outputs go off--card to the B--processor data bus 16 bits wide.

2 The input address lines to the bus RAMs, BSRAMA0 (bus RAM address)
through BSRAMA7, are B--processor addresses muxed by U58 and U75
with the output of the up counters, U53, U54, and U67. The A--processor
controls the RAM addresses when the ASCB is writing to them and the
B--processor controls the RAM addresses when the B--processor is reading
from them. The two 2--to--1 multiplexers are enabled by the B/A* SELECT
signal coming from the B--processor at connector pin A74.

3 The control lines to the RAMs are multiplexed by U83. The first byte of data
from the ASCB gets loaded into one pair of RAMs and the second byte will
be loaded into a second pair of RAMs. The chip enables are as follows.
• The A--processor address range (FEOO--FEFF) and MREQ* are ANDed
at U86 with the Z0 signal from the up counter to enable U52 and U57 for
the upper byte, and U74 and U78 for the lower byte.
• The B--processor is from the address range E800--E9FF, MREQ*, and
B--processor READ. The B--processor cannot do a byte access, it can
only read a full word.
• These lines have to be controlled by the processor that controls the
addressing to the RAMs so U83 is enabled by the same B/A* SELECT
signal that enables the address multiplexing.
4 Figure 15 shows the control lines to the RAMs and their origin.
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Figure 15. RAM Control Lines


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(e) Transceivers U70 and U82 (See schematic sheet 12.)

1 These transceivers are enabled to allow data to be transferred from one


processor to the other. The controls, shown in Figure 15, come from the
B--processor. The B--processor address ranges are gated with B--MREQ*,
B--DS*, and B--RD/WR* to enable the transceivers. Direction of the devices
is controlled by the B--processor READ and WRITE signal, B--RD/WR*.

2 The decoded B--FOXX* address goes to another CCA.

(f) Serial Communications Controller (See schematic sheet 5.)

1 The serial communications controller interfaces directly with the A--processor


multiplexed bus and does not require demultiplexing into addresses and
data. Inputs RxDA and RTxCA are generated on CCA A3 by the
B--processor. TxDA and TRxCA are the clock and data outputs to the ASCB
bus. Figure 16 shows the signals that control the serial communications
controller from the A--processor.

Figure 16. Serial Communications Controller Controls

(g) EPROMs (See schematic sheets 6, 7, and 10.)

1 CCA A4 contains eight EPROMs, two with 64K (8K X 8) and six with 128 K
(16K X 8) memory components. Figure 17 is a memory map with addresses
for each EPROM. Each EPROM has two control functions which must be
low in order to obtain data at the output. EPROM controls shown in
Figure 18 are as follows.
• OE* (output enable) controls the output of the selected device by a READ
(RD/WR) command and a DS* gated at U44.
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Figure 17. Memory Map CCA A4 Memory Devices


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• CE* (chip enable), one for each pair of EPROMs, selects the memory
device to be read.
-- The two 64K EPROMs are selected by the correct address range and
ST3.
-- The three pairs of 128K EPROMs are selected by outputs from the
3--to--8 demultiplexer U18.
2 The processor writes to the A6 card with address bits 13, 14, and 15. The
signals coming back from the A6 card, the three PAGE SELECTS, go to the
3--to--8 demultiplexer U18 and select the memory page to be accessed. The
enable at U18--5 comes from address range 4000--BFFF and ST3. Table 6 is
the function table for the U18 demultiplexer.

3 Other outputs of the demultiplexer going off--card are CS1P3 (chip select
one page three) and CS1P4. The CS1P4 comes from an output which is
ANDed with the address 8000--BFFF for accessing or writing to the NVRAM
on the A6 card for units that have an NVRAM. The NVRAM is
READ/WRITE; all the other pages, 0, 1, 2, and 3, are READ only.

Figure 18. EPROM Controls


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Table 6. Function Table U8 Demultiplexer


Input Output
5 3 2 1 15 14 13 12 11
H X X X H H H H H
X X X X H H H H H
X X X X H H H H H
L L L L L H H H H
L L L H H L H H H
L L H L H H L H H
L L H H H H H L H
L H L L H H H H L
L H L H H H H H H
L H H L H H H H H
L H H H H H H H H

(h) Transceivers U11 and U16 (See schematic sheet 10.)

1 These transceivers are buffers between the microprocessor, the EPROMs,


and the transfer RAMs. When the transceivers are enabled, the processor
can read from the EPROMs, read from the B--to--A transfer RAM, or write to
the A--to--B transfer RAM. Transceiver controls shown in Figure 19 are as
follows:
• Enable (which requires high inputs at U14 from the ST3 signal), two test
signals (always high during operation), and the output from U3--11, which
has inputs of:
-- 0000--EFFF memory locations for the EPROMs
-- F200--F3FF address range of the A--to--B transfer RAM, ANDed at
U63 with WRITE (the processor is trying to write to the A--to--B transfer
RAM) and MREQ*
-- F000--F1FF address range of the B--to--A transfer RAM, ANDed at
U59 with READ and MREQ*.
• DIRECTION is determined by the READ\WRITE* and DS* at U44.
2 When the processor is doing a READ, the transceiver direction is A to B;
when the processor does a WRITE, the direction is B to A.
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Figure 19. Transceiver Controls

(i) Up Counters (See schematic sheet 13.)

1 The data inputs to the counters are off the A--data bus, A--D0 through
A--D8. The address of the counters A--F988* comes from the A--processor
and load input on U67. The count--up (carry) output of U67 is rippled to
counter U53 which then ripples to U54.

2 The A--processor knows what will be on the ASCB next and the address for
it, and where it needs to go in the bus RAM. Everytime the A--processor
reads a byte, the counters are incremented and the data on the bus is
stored in the RAMs.

3 The clock controls on the counter are shown in Figure 20.

4 The output of the counters go to digital multiplexers U58 and U75. The
multiplexers select one of the following:
• The output of the counters if data is being stored in the RAMs
• The B--address lines for BSRAMA if the B--processor is reading data from
the RAMs.

Figure 20. Counter Controls


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(j) SRAMs (See schematic sheet 7.)

1 Two 8K x 8 SRAMs (static RAMs) are located on CCA A4. Address inputs
are from the A--processor multiplexed bus, A--AM0 through A--AM13. SRAM
memory is accessed for a READ or a WRITE from the processor as follows:
• Output enable requires a READ signal from the processor, a DS*, and a
PV
• Write requires PV, a processor WRITE (WR), and a DS*.
2 When the processor is doing a byte read, the address A--0 signal will
determine whether the upper byte (SRAM U29) or the lower byte (SRAM
U32) is being accessed. When the processor is doing a word read, both
SRAMs are accessed so that the whole word, both bytes, can be read.
Figure 21 shows the SRAM controls.

Figure 21. SRAM (NVRAM) Controls

G. Serial Data Interface CCA A5

(1) Refer to 22--11--92, Honeywell Pub. No. A09--1147--056, for the schematic sheets
referenced in the following paragraphs. The bus diagram for this CCA is shown in
Figure 22. The Serial Data Interface CCA, Part No.7007591--903 performs the
following functions:
• D/A conversion
• Processor interrupts
• Address decoding
• A/D conversion
• Serial data control.
(a) D/A Conversion (See schematic sheet 2.)

1 This sheet shows the D/A conversion for the vertical steering command
which consists of the pitch flight director steering command and the roll flight
director steering command. U29 and U30 are 12--bit D/A converters.
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Figure 22. CCA A5 Bus Diagram


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2 The circuitry for the pitch flight director steering command can be traced
through as follows:

a Address A--F900* is input to U29 D/A converter.

b A 12--bit digital command with the most significant bit inverted is input to
U29.

c U29 current outputs:


• Require U7 to convert the outputs to a bipolar analog voltage
• Drive the flight director bars with current buffered output at U7--14
• Provide a feedback that comes off U7--14 that goes off--card to the
A--processor at P1--C48 (PITCH D/A FB).
d If either PITCH 0V BIAS* or COMPUTER VLD is low:
• The input to U7--5 goes low
• The output at U7--7 is biased to approximately 8.2 V causing U7--1 to
be low turning Q20 off.
• The pitch flight director bar is driven out of view.
3 A 10 V reference voltage is created by U9 voltage regulator for use by the
D/A converters. This voltage also goes off--card.

4 The roll flight steering command circuitry works the same as the pitch at the
input address of A--F902*.

(b) Interrupts (See schematic sheet 3.)

1 CCA A5 has five interrupt inputs:


• HB MON INT
• BUS RAM XFR
• SPARE INT
• PRE BUS INT*
• BUS TMR CO*.
2 The A--processor data bus brings six data lines into the U20 Hex D--type
flip--flop, one for each interrupt. U20 controls the masking for all of the
interrupts. Figure 23 shows an interrupt number (e.g., Int 5) adjacent to the
NAND gates. These are priority numbers associated with U2, the priority
encoder that selects the highest number interrupt first.
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a B--Processor Heartbeat Monitor Interrupt

(1) When the heartbeat monitor is tripped:


• The B--processor clocks a 1 into U21--5 where it is latched.
• If the A--processor is in a sequence that cannot be interrupted, it
will mask the interrupt by outputting a low to gate U45--9.
• When the sequence ends, the A--processor writes to U20, which
enables U45.
• The signal is gated with the heartbeat monitor interrupt, still
latched at U21.
• The signal goes to the transparent latch U3 where it will be
latched when A--VIACK* goes low.
• The latched interrupt signals go to the 10--line to 4--line encoder,
U2, producing a 4--bit code representing the highest priority
vectored interrupt.
• The 4--bit code pulls U32--6 low, and that is the A--VI* line to the
A--processor telling it there is an interrupt.
• The A--processor goes through a vectored--interrupt--
acknowledge sequence, pulling the A--VIACK* line low, which
shuts off the U3 latch, holding the data there until the processor
can determine the source of the interrupt.
• The code from U2 also goes to the U5 buffer.
• The A--processor looks for the interrupt.
• The processor READ (A--R/W*) is gated with an inverted
A--VIACK* to make a signal called A--VECTEN to enable U5.
• U5 places the vectored interrupt code on the data bus where the
A--processor reads it and looks the number up in a table for the
address where the corrective action is stored in memory.
• The same vectored interrupt code goes to U1, producing a low at
U1--13, which resets the U21 flip--flop where the interrupt
started.
• In Figure 23, INT 5 is cleared by CL INT 2 because the CLEAR
signal is inverted in U1 (5 complemented = 2).
b The BUS RAM XFR Interrupt

(1) This interrupt is similar to the heartbeat monitor interrupt except for
the pin numbers.

c The A SPARE INT Interrupt

(1) This interrupt is similar to the two previous interrupts except for pin
and gate numbers.
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Figure 23. Interrupt Controls


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Figure 24. Address Decoding


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d The PRE BUS INT* Interrupt

(1) This interrupt differs from the previous three in that the processor is
able to mask the interrupt from being latched by the U67 flip--flop.

(2) When the PRE BUS INT* goes low and then high indicating an
interrupt the following will occur:

(a) If the signal at U67--12 from U20 is low:


• U67--8 will be high and will not change when the clock signal
at U67--11 goes high
• The interrupt will not be latched.
(b) If the signal at U67--12 is high, meaning the processor is ready
to accept an interrupt:
• U67--8 will go low
• The rest of the process is similar to the previous three
interrupts.
e The B BUS TMR CO* Interrupt

(1) This interrupt is similar to the pre--bus interrupt except for different
pin numbers and gates.

(2) The VECTEN* signal goes to U47 on schematic sheet 9. It is one of


the inputs that enables transceivers U106 and U114 so the
A--processor can read the interrupts off the bus.

(3) The A--RESET* signal resets everything on power--up.

(c) Address Decoding (See schematic sheet 4.)

1 The inputs shown in Figure 24 are as follows.

a WR*, DS*, and MEMEN* from the A--processor to decode the address
ranges.

b Address lines A--A0 thru A--A15 from the A--processor that go:
• To U110 and U113 for buffering
• To U70 (bits one thru six) to be latched
• Off--card as the least significant bits, A--LA1, A--LA2, and A--LA3, to
decode the analog MUX addresses
• To U68 for decoding, then off--card as the analog MUX select lines,
A--M1SEL thru A--M8SEL (These lines get inverted by U46 and U48
because they are going to analog MUX that are high--true enabled)
• To U14 and U19, serial data output RAM address multiplexer.
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c A--ALST, which comes from U27--6 (sheet 5) D type flip--flop, to the


clock input of U70, latches data from the A--processor, which is decoded
by U68 and used to select analog inputs to the A/D converter. It also
creates the pulse for starting A/D conversions.

d During an A/D conversion, the addresses have to be held valid for the
entire conversion cycle. The latched addresses hold the analog MUX in
that state until the conversion is complete and another analog input is
selected.

e A--PREZERO* signal, which is used to enable the U68 decoder. At the


proper time the A--PREZERO* causes the address to be decoded to the
MUX.

2 The decoded address outputs shown in Figure 24 and where they go are as
follows:
• A--F9XX* and A--F98X* go to the A6 card for further decoding
• A--F98C* at decoder U72--9 goes to the binary counter U66 to clear the
counter
• A--F98A* is the clock signal that goes to the U20 flip--flop, which is used
in the interrupt control circuitry
• A--F900* at U73--15 and A--F902* at U73--14 are the transfer (XFR*)
signals that go to the U29 and U30 D/A converters
• All the other addresses go off--card.
(d) Address Decoding for the B--Processor (See schematic sheet 9.)

1 Address decoding for the B--processor, is shown in Figure 25, and is done in
an equivalent manner to the decoding for the A--processor. The address
F7XX* at C37 goes to the A6 card for further decoding before returning to
decode the B--F700*, B--F702*, and B--704* addresses.

(e) A--Processor A/D Conversion (See schematic sheet 5.)

1 The U76 and U116 buffers allow converted digital data coming from the A/D
U51 to be placed on the data bus. These buffers are enabled, as shown in
Figure 26, whenever the processor is doing a READ and a MEMEN*, and
the address range of F800--F8FF is on the address bus.
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Figure 25. B--Processor Address Decoding


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Figure 26. A/D Controls


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2 Figure 27 is the timing diagram for the A/D conversion cycle. As the diagram
shows, the address range of F800--F8FF will be valid for the entire
conversion. The address is ANDed with A--MEMEN* B and becomes an
input to D--type flip--flop U27.

Figure 27. A/D Conversion Timing Diagram


3 The signals in the timing diagram and their functions are as follows.
a RD* B
(1) When the A--processor is in a READ cycle, the U76 and U116
buffers are enabled and the processor can read data that was
converted previously by the A/D. During the processor READ, the
low A--RD*B signal coming on--card at B76 provides a clock signal
to the U27--3 flip--flop.
(2) The last conversion is read by the processor and the next
conversion begins. When the processor addresses the D/A for the
next read, it always reads the conversion that was initiated by the
previous read.
b LOAD Pulse
(1) The LOAD pulse shown in the timing diagram is created when the
low A--RD*B at U27--3 clocks in the F8XX address line at U27--2.
The function of the U28 up counter is shown in Table 7.
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(2) When the LOAD signal to U28--11 goes low, the counter is loaded
with a logic of 1010 and the signal at U26--10 begins to toggle up
and down at 1 MHz, and that starts clocking the counter. As soon
as the data is loaded into the U28 counter, output pin 7 goes high
and is gated to U27--4, and clears the LOAD pulse away. This
makes the LOAD pulse very narrow. U28--12 is high, which sends a
READ signal to U51--5. The clock continues to count until U28--7
goes low.

Table 7. U28 Up--Counter Function Table


U28 Input Pin No. Output Pins

Operating Mode 14 11 5 4 15 1 10 9 6 7 12
Clear H X X L X X X X L L H
H X X H X X X X L L H
Load L L X L L L L L L L H
L L X H L L L L L L H
L L L X H H H H H H L
L L H X H H H H H H H
Count L H L H X X X X Count H

c PREZERO

(1) After the narrow LOAD pulse occurs, the output from U28--7 and
the inverted output from U28--6 are gated at U24 to create an
A--PREZERO*.

(2) The analog circuit puts zero volts on the analog input of the A/D
converter to create a window before data goes into the converter.
This allows any offsets between CCAs A5 and A7 to be corrected.
U24--8 is low for 1 to 2 microseconds going off--card to CCA A7. It
will be low any time U28--7 is high and U28--6 is low. As soon as
U28--6 toggles high, PREZERO goes away.

d READ/CONVERT*

(1) The clock input U28--5 to the counter has to be low and all the
outputs high for the ripple carryout U28--12 to be low. U28--12 is the
READ/CONVERT* line sent to the A/D converter pin U51--5 that
initiates the conversion. As soon as the READ/CONVERT* goes
low, the conversion starts.

(2) As soon as the clock pulse U28--5 goes high, some of the outputs
ripple over to zero. When U28--7 is low, the output from U26--10 is
low and no more clock pulses can come through.
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e STATUS

(1) While the A/D converter is doing a conversion, the STATUS line
U51--28 will be low. This is gated at U25 with F8XX* and results in a
low A--WAIT3* A/D at B69. While the STATUS line is low and the
WAIT line is low, the output data lines, DB0 thru DB11 from the A/D
converter U51, are toggling back and forth and the data is not valid.
When the conversion is complete, the STATUS line goes high and
returns low 300 ns after the output data to the buffers is valid.

f WAIT

(1) As long as the address F8XX* is latched and the STATUS line is
high, A--WAIT3* A/D will be low. During conversion, the WAIT line is
sampled by the processor and if it is low, the processor inserts extra
clock cycles, which allows more time for conversion.

(f) B--Processor (A/D) Conversion (See schematic sheet 6.)

1 A/D conversion for the B--processor is similar to the A--processor


conversion. The address range for the B A/D conversion is F600--F6FF. The
reference designations in the timing diagram shown in Figure 27 are also
different. See schematic sheet 6 for differences.

(g) Serial Data Control (See schematic sheets 7, 8, 10, 11, and 12.)

1 Sheet 7 is where serial data control starts. The serial data RAMs on sheet 8
contain serial data going to other cards. Three sets of differential lines are
created through U38 on sheet 7 that go out of the unit through the J1 and J2
connectors to the guidance controller.

2 The bus diagram in Figure 28 shows the input addresses to the serial data
RAMs come from binary counters or A-- and B--processor addresses. Input
data comes from serial data out of the shift registers on sheets 11 and 12.

3 The signal PSINH* is the Q output of U40--10 flip--flop on sheet 7. This


signal is used to:
• Select the RAM input addresses through 2--to--1 multiplexers U14, U19
on sheet 8 and U13, U36 on sheet 10
• Select the controls for the serial data RAMs through 2--to--1 multiplexer
U42 on sheet 8 and U10 on sheet 10
• Buffer serial data from the shift registers to the serial data RAMs.
4 PSINH, the Q* output of U40--9, is also used as a control signal for serial
data devices. Refer to Table 8 for the state of the serial data devices when
PSINH* is 0 and PSINH is 1.
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Table 8. Discrete RAM Function Table


PSINH = 1
PSINH* = 0 PSINH = 0

SHIFT CLOCK = 250 kHz H


REGISTERS
SHIFTING = YES NO
LOADING = NO YES
CLK INH = NO YES
A SERIAL DATA ADDRESSES = COUNTERS ADDRESS BUS (A)
OUTPUT RAM
CHIP ENABLE = RAME F500--F7FF (A)
CHIP SELECT = YES WRITE OR F600--F7FF (A)
WRITE ENABLE = NO A -- R/W
CYCLE = READ
A SERIAL DATA ADDRESS = COUNTERS ADDRESS BUS (A)
INPUT RAM
CHIP ENABLE = RAME F400--F5FF (A)
CHIP SELECT = RAME F400--F5FF (A)
WRITE ENABLE = YES A -- R/W
CYCLE = WRITE
B SERIAL DATA ADDRESS = COUNTERS ADDRESS BUS (B)
INPUT RAM
CHIP ENABLE = RAME F400--F5FF (B)
CHIP SELECT = RAME F400--F5FF (B)
WRITE ENABLE = YES B -- R/W
CYCLE = WRITE
BUFFERS U33--3 = YES NO
U33--11 = YES NO
U33--6 = NO YES
U39--8 = NO YES
U39--11 = A--READ & F400--F5FF (A SERIAL INPUT RAM)
U39--3 = A--READ & F600--F7FF (A SERIAL INPUT RAM)
U33--8 = B--READ & F400--F5FF (B SERIAL INPUT RAM)
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5 The procedure of shifting serial data through the serial data RAMs and
off--card is started by the A--processor address A--F98C*. Figure 28 shows
the controls for the serial state devices on sheet 7. When PSINH* is active
or at the 0 state:
• Address A--F98C* clears counter U66 and clocks U64 flip--flop
• U66 divides the 1--MHz input to create a 250--kHz output. This clocks
flip--flops U40, U50, and U64; clocks binary counters U37 and U43; and
goes off--card as PCLK*
• RAME*, created at U50--8, is shifted a half--clock pulse to ensure the data
is valid before it gets stored into the RAMs
• U64--9 is low, clearing binary counters U37 and U43
• U37 and U43 begin counting when U40--13 goes high
• Ripple carryout from U37--15 and U43--15 is brought into AND gate
U41--12 and U41--13 to provide the J signal U40--14
• PSINH* becomes 1, PSINH becomes 0.
6 Serial data RAM control lines are shown in Figure 29. These RAMs are used
as memory devices for the serial data that comes onto the card as discrete
signals.
7 Shift registers U79, U84, U89, U93, U97, and U101 on sheets 11 and 12 are
serially connected together. Discrete signals are filtered and input to the
parallel input pins on the shift registers. Serial data is input to U79--10 from
CCA A6. The inputs are latched when pin U79--1 and PSINH from U40--9
J--K flip--flop is high and shifted through when the 250--kHz signal PCLK* is
toggled.
8 Shift registers controls are shown in Figure 28.
(h) B--Processor Serial Data Input RAM (See schematic sheets 9 and 10.)
1 Data input to the U12 input RAM comes from two sources:
• Data bit 15 from the B--data bus through U33--5 and U33--6, an
active--low enabled buffer that transmits when PSINH is low.
• SDI at U33--2 and U33--3 that transmits when PSINH* is low.
2 Multiplexers U13 and U36 select one of two sets of address lines to U12:
• The B address bus lines B--A1B thru B--A8B are selected when PSINH*
at U13--1 and U36--1 is high.
• The counter control lines, CCA0 thru CCA7, generated by binary counters
U37 and U43 (sheet 7), are selected when PSINH is high.
3 U10 multiplexes the control lines that place U12 in a WRITE cycle when
PSINH is high as shown in Figure 29:
• WRITE ENABLE* (U12--20) is low when PSINH* is low.
• CHIP SELECT* and CHIP ENABLE* are low when RAME* is low.
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Figure 28. Serial Data Control


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Figure 29. Serial Data RAM Controls


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H. Direct Discretes CCA A6


(1) Refer to 22--11--92, Honeywell Pub. No. A09--1147--056, for the schematic sheets
referenced in the following paragraphs. The description contains reference
designations for all A6 CCA part numbers as follows:
• 701083--903 and --904 are in plain text
• 7007593--904 reference designations are in parentheses
• 7007593--913 and --914 are in square brackets.
(2) The direct discretes CCA, Part No. 7007593--904, --913, --914, and 7010683--903
and --904 perform the following functions:
• Creating the page selects for memory devices
• Processing direct discretes (input and output)
• The interface for parallel--to--serialized discretes
• Page 3 of program memory (EPROMs)
• Page 4 of program memory (static nonvolatile RAMs).
(3) Block diagrams for CCA A6 are shown in Figure 30 and Figure 31 with the reference
designators for each device. Figure 32 and Figure 33 are block diagrams showing the
static nonvolatile RAMs (NVRAM) for the CCA A6.
(a) Page Selects (See schematic sheet 1.)
1 Data bit 15 is buffered on CCA A6 (Figure 34 and Figure 35) by U4 and U23
(U28 and U35) [U14 and U5]. When the processor looks at a discrete input,
it only looks at data bit 15. The exception is the page select 1, which uses
data bit 14, and page select 2 on 7003974--717, which uses data bit 13.
2 If the direction of the transceiver is correct when address F982* clocks the
flip--flops, page selects A--PGSEL 0 and A--PGSEL 1 (and A--PGSEL 2 on
7003974--717) are latched out to CCA A4 to determine which portion of
EPROM gets read. PVB clears the flip--flop at each power--up.
3 The transceiver that buffers A--D14 and A--D15 gets enabled as a function of
A--processor addresses, A--R/WB*, and A--DSB*. The direction is
determined by whether the processor is doing a READ or a WRITE.
4 Another transceiver (shown in Figure 35) buffers B--D15, data bit 15 from the
B--processor, by the use of B--processor addresses, B--R/WB*, and B--DSB*.
(b) A--Processor Direct Discretes (See schematic sheet 2.)
1 A--processor address lines A--A0 through A--A7 are buffered onto the CCA
by U20 (U29) [U39] and decoded by U25 (U24) [U29]. A different decoded
address goes to each of the three addressable latches (output discrete) and
to each of the two multiplexers (input discretes) to enable them. Address
data bits A1, A2, and A3 provide the address inputs to the latches and the
selects to the multiplexers.
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2 When one of the decoded addresses enables a latch, the latch’s output is
whatever is on data bit 15 at the D input to the latch. The data bits on the
address inputs determine which of the eight output lines is selected.
Figure 36 shows the control signals for the latches.

3 The two multiplexers, U2 and U5 (U15 and U18) [U2 and U6], multiplex the
discrete inputs onto data bit 15. The signals that enable and select the
addresses each multiplexer dumps onto data bit 15 are shown in Figure 37.

(c) Serial Data Output (See schematic sheets 3 and 4 [schematic sheets 3, 4,
and 5].)

1 Serial data comes into U29 (U46--D) [U22] differentially and out on pin 13 to
the serial--in port of the first shift register in the string. Discretes are brought
in here, in parallel, and shifted out serially. The serial output goes off--card
on schematic sheet 4 [schematic sheet 5] as SDI.

2 The six shift registers are clocked by the PCLK coming from CCA A5 and
are loaded and shifted by PSINH, also from CCA A5.

(d) B--Processor Direct Discretes (See schematic sheet 5 [6].)

1 The functions here are the same as those on schematic sheet 2, except the
inputs and the outputs are B--processor addresses.

(e) EPROM Page 3 Program Memory for 7003974--713 (See schematic sheet 8 [9].)

1 Figure 30 thru Figure 34 show the address bus, with bits 0 thru 14 going to
the EPROMs, U11 and U17 (U16 and U21) [U11 and U17]. U7 and U21
(U27 and U32) [U15 and U35] buffer the data coming out of the EPROMs
before it goes onto the data bus. U7 and U21 (U27 and U32) [U15 and U35]
have two enable pins, both tied to the CS1P3 (chip select one page three)
signal which comes from CCA A4.

2 The 4--MHz crystal, Y1, is shown on schematic sheet 8. The 4--MHz signal is
clocked through U53 (U58) [U7] for a 4/3--MHz signal to CCA A3.

(f) Static Nonvolatile RAM for the 7003974--717 Unit (See schematic sheet 9.)

1 Figure 38 shows the controls for the transceivers on schematic sheet 9, (U1
and U3) [U44 and 52], and the two nonvolatile static RAMs, (U6 and U11)
[U47 and U56].
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Figure 30. CCA A6 Bus Diagram (7003974--708 and --713)


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Figure 31. CCA A6 Bus Diagram for Part No. 7007593--913 (7003974--708)
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Figure 32. CCA A6 Bus Diagram (7003974--708) with NVRAM


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Figure 33. CCA A6 Bus Diagram (7003974--713, --717, --724, --725, --728, and --732)
with NVRAM
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Figure 34. CCA A6 U4 (U28) [U14] A--Data Transceiver Controls

Figure 35. CCA A6 U23 (U35) [U5] B--Data Transceiver Controls


2 The transceivers have two control lines, one to enable and one for direction.
a Enable
(1) The three signals used to enable the transceivers are as follows:
• The CS1P4* (chip select one page four) is low when the
A--processor wants to access one or both of the NVRAMs.
• A--A0 enables one or the other transceiver. When A0 is 1,
transceiver (U1) [U44] is enabled; when A0 is 0, transceiver (U3)
[U52] is enabled.
• A--B/W* is high when the A--processor is doing a byte, and low
when it is doing a word. When the processor does a byte, only
one transceiver and one NVRAM will be enabled, but when it
does a word, both transceivers and both NVRAMs will be
enabled. When the processor does a word, the low signal to (U7)
[U51] will produce a low at (U1--19 and U3--19) [U44--19 and
U52--19] which will enable both transceivers to select both
NVRAMs.
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Figure 36. CCA A6 U2, U5 (U15, U18) [U2, U6] Multiplexer Controls

Figure 37. CCA A6 Addressable Latch Controls


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Figure 38. SRAM (NVRAM) and Transceiver Controls for 7007593--904, --913 and --914

b Direction

(1) When the A--processor is doing a READ, A--RD*B will be low,


making U1--1 and U3--1 high. When these pins are high, and when
PV is high, the direction of the Transceivers will be from A to B as
shown in Figure 36 and the processor will be reading data out of
the NVRAMs.

(2) When the processor is doing a write, A--WR*B will be low, pins
U1--1 and U3--1 will be low, the direction will be from B to A, and the
processor can write data into the NVRAMs.

(3) The controls for the NVRAM are as follows:


• CHIP SELECT 1 is active for (U6) [U47] when transceiver (U1)
[U44] is enabled. CHIP SELECT 1 is active for (U11) [U56] when
transceiver (U3) [U52] is enabled.
• CHIP SELECT 2 is active for both NVRAMs whenever CS1P4 is
low, indicating the processor wants to access one or both
NVRAMs.
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• OUTPUT ENABLE is active for both NVRAMs when the


processor is doing a READ and the direction of the transceivers
is A to B.
• WRITE ENABLE is active for both NVRAMs when the processor
is doing a WRITE and the direction of the transceivers is B to A.
I. Analog Inputs CCA A7 (7007595--908, --928)

(1) Refer to 22--11--92, Honeywell Pub. No. A09--1147--056, for the schematic sheets
referenced in the following paragraphs. Analog inputs come into this CCA, Part No.
7007595--908 and --928. Reference designations for the 7007595--928, appear in
parentheses. The analog inputs CCA, Part No. 7007595--908 and --928, performs the
following functions:
• Elevator trim servo command logic
• Yaw damper (Y/D) amplifier
• Analog inputs to the A--A/D converter and the B--A/D converter.
(a) Elevator Trim Servo Command Logic (See schematic sheet 1 or (3).)

1 The trim logic that creates servo motor clockwise and counterclockwise
command is shown on schematic sheet 1 (2).

2 In order for the elevator trim servo to be driven in either direction, these
signals must be valid:
• Trim disconnect switch off (TRM DISC SW OFF)
• Elevator trim drive enable (ELEV TRIM DR EN)
• Trim switched power OK (TRIM SW PWR OK)
• Servo power enable (SVO PWR EN)
• CPU valid.
3 The direct discrete signals controlling the direction of travel of the elevator
trim servo are:
• ELEV TRM ARM UP CMD drives the servo counterclockwise
• ELEV TRM DN ARM CMD drives the servo clockwise.
4 These signals get clocked into the U48 (U56) flip--flop with the 488--Hz
signal. Two annunciator signals come off the arm up and arm down
commands, and go off--card at A14, A15, B7, and B8.

(b) Yaw Damper Servo Direction Commands (See schematic sheet 2 (3).)

1 The circuitry on this sheet commands the direction of the Y/D servo from
inputs from the B--processor data bus. The sequence to drive the elevator
servo is as follows:
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a Data bits D7 through D14 are input to U40 (U36) from the B--processor
(these eight bits set the pulse width for the duty cycle that has been
selected by the processor).
b Data bit D15 is input to U37 (U51) flip--flop as the D input and sets the
direction of travel of the Y/D servo:
• When B--D15* is low the direction is clockwise
• When B--D15* is high the direction is counterclockwise.
c The data bits are latched by the U40 (U36) flip--flop and clocked by the
inverted address of the Y/D servo, B--F774*.
d U28 (U62) synchronizes any direction of travel change with the start of a
new pulse--width cycle.
e This synchronized direction--input is also applied to the U36 (U44) and
U47 (U50) counters to clock in the data bits and set the number from
where the counters will start counting.
f The outputs U37--8 (U51--8) and U37--9 (U51--9) are ANDed with the
125 kHz to set the counter in an up--count mode or a down--count
mode.
g The counters start counting at the number set by the data bits and count
at a rate of 125 kHz until the end of the 488--Hz pulse--width duty cycle.
h The pulse--width signal duty cycle produced by the counters is ANDed
at U49 (U48) with the direction signal from data bit 15 and the following
signals which must be valid to have a servo drive enable signal:
• SVO PWR EN
• SW Y/D PWR OK
• Y/D SW OFF
• Y/D DR EN
• CPU valid.
i The output of U49 (U48) goes to the Y/D servo amplifier and provides a
signal to drive the servo in a clockwise or counterclockwise direction.
j When the counters time out and the outputs go low, U49--6 (U43--3)
goes low, and the pulse--width output at U49--8 (U48--8) or U49--12
(U48--12) is removed.
k The counters are now inhibited until the beginning of the next 488--Hz
cycle.
(c) Yaw Damper Servo Amplifier (See schematic sheet 3 (4).)
1 The Y/D servo amplifier circuitry contains two relays, K4 and K5 (K6 and
K7). The relays are energized by +28 V dc SW Y/D PWR. Q29 is turned on
(U64--15, 16 low) when Y/D ENG CMD from CCA A6 and Y/D SW OFF from
schematic sheet 2 are both high.
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a K5 (K6) Relay
(1) When not energized, K5 (K6) routes +28 V dc SW Y/D PWR to Y/D
SVO OFF signal.
(2) When energized, K5 (K6) routes +28 V dc SW Y/D PWR to Y/D
SVO RELAY ON and RUD CLUTCH.
b K4 (K7) Relay
(1) When not energized, K4 (K7) Y/D servo amplifier output stops at
the relay.
(2) When energized, K4 (K7) +28 V dc Y/D power routed from T1
through the rudder servo drive.
2 The clockwise and counterclockwise yaw damper signals created on sheet
2, Y/D CW and Y/D CCW, come into U52 (U70). Either one can be high but
not both. Both can be low.
a When the pulse--width signal created on sheet 2 for clockwise travel is
applied at U52--3 (U70--10):
• The output at U52--1 (U70--8) is a square wave with an amplitude of
±13 V dc
• Q25 (Q25) turns on
• Q32 (Q27) turns on and +28 V dc Y/D goes to K4--2 (K7--2) and out
K4--5 (K7--5) to RUD SVO DR LO
• Q31 (Q20) turns on and connects ground through K4--1 (K7--1) and
K4--6 (K7--6) to RUD SVO DR HI
• The rudder servo drives in the clockwise direction.
b When the pulse--width signal created on schematic sheet 2 for
counterclockwise travel is applied at U52--5 (U70--5):
• The output at U52--7 (U70--7) is a square wave with an amplitude of
±13 V dc
• Q27 (Q21) turns on
• Q33 (Q19) turns on and +28 V dc Y/D goes to K4--6 (K7--6) and out
K4--1 (K7--1) to RUD SVO DR HI
• Q30 (Q28) turns on and connects ground through K4--2 (K7--2) and
K4--5 (K7--5) to RUD SVO DR LO
• The rudder servo drives in the counterclockwise direction.
c Q24 (Q26) and Q26 (Q22) monitor the --13 V dc and, if it is lost, they will
ground the signals that turn on Q25 (Q25) and Q27 (Q21).
3 U52--14 (U70--1) is the Y/D motor voltage that goes to the analog multiplexer
on schematic sheet 7, to the A/D converter, and back to the processor to be
monitored.
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4 U50 (U71) measures differential current across R236 (R395) and R237
(R376). It is monitored by the processor in the same manner as the Y/D
motor voltage.

(d) Analog Inputs (See schematic sheet 4 and 5 for Part No. 7007595--908.)

1 On this schematic sheet, the first of a series of 10 analog multiplexers select


the signals to the A and B--A/D converters. Six of the multiplexers are
controlled by the A--processor and go to the A--A/D converter. Four are
controlled by the B--processor and go to the B--A/D converter.

2 The multiplexers are enabled by multiplexer select lines from the processors,
A--M1SEL through A--M8SEL and B--M1SEL through B--M4SEL. The
multiplexers select which analog signals go to the A/D converters by the
logic of the latched address lines LA1, LA2, and LA3 from either the A-- or
the B--processor.

3 Analog multiplexer U18 (U14), shown on schematic sheet 4 (10), is different


from the others on succeeding schematic sheets by having the multiplexer
select lines and the latched address lines going through a 2--to--1
multiplexer, U31 (U41), instead of directly into the eight--channel multiplexer
U18 (U14). The logic has U18 (U14) enabled by three multiplexer select
lines, A--M6SEL, A--M7SEL, and A--M8SEL.

4 There are eight direct analog inputs to U18 (U14). The No. 2 radio altimeter
lines are differentially sensed at U17 (U17 on schematic sheet 6) before
input to U18 (U14). Table 9 lists the analog inputs to U18 (U14) and the logic
of the latched addresses to select each analog signal.

Table 9. Analog Inputs to Multiplexer U18 (U14)


(Enabled by A--M6SEL, A--M7SEL, and A--M8SEL)
Mux
Selected Input
Analog Signal Pin A/D--A0 A/D--A1 A/D--A2
Pin 1 Pin 16 Pin 15
A--F850 4 0 0 0
A--F852 5 1 0 0
A--F854 6 0 1 0
A--F856 7 1 1 0
A--F858 12 0 0 1
A--F85A 11 1 0 1
A--F85C RAD ALT 2 10 0 1 1
A--F85E MUX INPUT 9 1 1 1
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5 On schematic sheet 5 (6 and 8), there are 2 more multiplexers and 16 more
analog inputs. Multiplexer U21 (U24) is enabled by A--M2SEL. Multiplexer
U19 (U23) is enabled by A--M4SEL. The analog signal select lines, A/D--A0,
A/D--A1, and A/D--A2, come from schematic sheet 4 (10) to U21 (U24) and
U19 (U23).

6 FLAP POS, TRIM RATE INPUT, RUD SVO TACH, and CRS PITCH THMB
WHL signals go to differential amplifiers and then to the multiplexer U21
(U24).

7 An AC signal coming in that has to be demodulated is 26 VAC REF 2. A


DEMOD REF 2 line comes off the 26 V ac line, goes to schematic sheet 6
(11) and back to control the FET Q7 (Q14) in demodulating the AC signal.

8 Table 10 lists the analog inputs to U21 (U24) and the logic of the
latched addresses to select each analog signal. Table 11 does the same for
U19 (U23).

9 Some of the signals on schematic sheet 5 (6 and 8) go over to schematic


sheet 9 (12 and 13) as B--addresses. These are input to analog multiplexers
that select analog signals to be converted by the B--A/D converter.

10 The outputs of U21 (U24) and U19 (U23) go to schematic sheet 8 (10)
where the outputs of all the analog multiplexers are combined for an A/D
ANALOG INPUT to the A--processor.

Table 10. Analog Inputs to Multiplexer U21 (U24) (Enabled by A--M2SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
A--F810 FLAP POS 4 0 0 0
A--F812 TRIM RATE INPUT 5 1 0 0
A--F814 RUD SVO TACH 6 0 1 0
A--F816 CRS PITCH TMB WHL 7 1 1 0
A--F818 (GROUND)* 12 0 0 1
A--F81A (GROUND)* 11 1 0 1
A--F81C +5 V DC ISO 10 0 1 1
A--F81E 26 V AC REF 2 9 1 1 1
NOTE: * Open for --908
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Table 11. Analog Inputs to Multiplexer U19 (U23) (Enabled by A--M4SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
A--F830 ELEV SVO I 4 0 0 0
A--F832 ELEV SVO TACH 5 1 0 0
A--F834 ELEV MTR V 6 0 1 0
A--F836 PITCH D/A 7 1 1 0
GROUND 12 0 0 1
A--F83A 11 1 0 1
A--F83C 10 0 1 1
A--F83E ROLL D/A 9 1 1 1

(e) Lateral Steering Command (See schematic sheet 6 (11).)

1 Long range navigation lateral steering command (LRN LAT STR CMD for
--908 and LRN_LT_S_CD for --928) No. 1 and No. 2 come in as AC signals.
They go to differential amplifiers U13 (U8) and U17 (U5) before they are
input to the 4--to--1 multiplexer U30 (8 to --1 multiplexer U10 for --928).

2 DEMOD REF 1 and DEMOD REF 2 are gated at U34 (U61) with data bits
A--D0 and A--D1 which are clocked in through U35 (U60) by the NAV STR
address, A--F980*. This creates a square wave at 400 Hz at U30--2 (U10--2)
to enable U30 (U10) 50 percent of the time and to demodulate the AC
inputs. A--D0 and A--D1 select one of the two LAT STR CMD signals.
Table 12 lists the analog inputs to U30 (U10) and the logic of the latched
addresses to select each analog signal.

3 The selected command signal is buffered by U13 (U8) and goes to U16
analog multiplexer on schematic sheet 7.

Table 12. Analog Inputs to Multiplexer U30 (U10) (Enabled by A--D0 and A--D1)
Mux
Selected Input A/D--A0 A/D--A1
Analog Signal Pin Pin 1 Pin 16
LRN LAT STR CMD 1 4 0 0
LRN LAT STR CMD 2 5 1 0
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(f) Analog Multiplexers (See schematic sheets 7 and 8 (9 and 7).)

1 Two analog multiplexers, U15 (U25) and U16 (U12), are shown on
schematic sheet 7 (7 and 9). U15 (U25) is enabled by A--M3SEL and U16
(U12) is enabled by A--M5SEL. Table 13 lists the analog inputs to U15 (U25)
and the logic of the latched addresses to select each analog signal.

2 Table 14 lists the analog inputs to U16 (U12) and the logic of the latched
addresses to select each analog signal. Table 15 does the same for U14
(U13).

3 All of the outputs of the analog multiplexers going to the A--processor are
combined with the output of U14 (U13) on schematic sheet 8 (5). Forty--nine
analog signals including a PREZERO* line are combined on one line and
buffered by U39 (U19 on schematic sheet 10) before going to the A--A/D
converter.

4 The A--PREZERO* applies a ground to the A--A/D_INPUT signal at U14--8


(U14--8). The A processor measures the value of ground and subtracts this
value from the value of multiplexed signals to obtain their true value when
performing A/D conversions.

Table 13. Analog Inputs to Multiplexer U15 (U25) (Enabled by A--M3SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
A--F820 AIL SVO I 4 0 0 0
A--F822 AIL SVO TACH 5 1 0 0
A--F824 AIL MTR V 6 0 1 0
A--F826 Y/D MTR 1 7 1 1 0
A--F828 12 0 0 1
A--F82A Y/D MTR VOLTS 11 1 0 1
A--F82C 10 0 1 1
A--F82E 9 1 1 1
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Table 14. Analog Inputs to Multiplexer U16 (U12) (Enabled by A--M5SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
A--F840 --13.8 V DC 4 0 0 0
A--F842 LRN_LTS_CM 5 1 0 0
A--F844 (GROUND)* 6 0 1 0
A--F846 (GROUND)* 7 1 1 0
A--F848 (GROUND)* 12 0 0 1
A--F84A (GROUND)* 11 1 0 1
A--F84C (GROUND)* 10 0 1 1
A--F84E PITCH THUMBWHEEL 9 1 1 1
NOTE: * Open for --908

Table 15. Analog Inputs to Multiplexer U14 (U13) (Enabled by A--M1SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
A--F800 FLAP EXC 4 0 0 0
A--F802 (GROUND)* 5 1 0 0
A--F804 RAD ALT 1 6 0 1 0
A--F806 (GROUND)* 7 1 1 0
A--F808 (GROUND)* 12 0 0 1
A--F80A (GROUND)* 11 1 0 1
A--F80C B--10 V REF 10 0 1 1
A--F80E 26 VAC REF 1 9 1 1 1
NOTE: * Open for --908

(g) Analog Signals to B--A/D Converter (See schematic sheet 9 (12 and 13).)
1 Four analog multiplexers are shown on schematic sheet 9 (12 and 13) that
select the analog signals for the B--A/D converter. These signals are
selected in the same manner as the ones on the previous sheets were for
the A--A/D converter. The multiplexers are enabled by multiplexer select
lines from the B--processor. The analog signals are selected by latched
address lines from the B--processor.
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2 The outputs of all four multiplexers are connected together and buffered by
U45 (U16) before going off--card to the B--A/D converter.

3 Table 16 through Table 19 list the analog inputs to U24 thru U27 (U11, U15,
U21, and U22) and the logic of the latched addresses to select each analog
signal.

4 The U41 (U31) test DAC receives a word from the B--processor, converts the
word and reads it back to check out the A/D conversion loop.

Table 16. Analog Inputs to Multiplexer U24 (U21) (Enabled by B--M3SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
B--F620 ELEV SVO I 4 0 0 0
B--F622 ELEV SVO TACH 5 1 0 0
B--F624 ELEV MTR VOLTS 6 0 1 0
B--F626 (GROUND)* 7 1 1 0
B--F628 GROUND 12 0 0 1
B--F62A (GROUND)* 11 1 0 1
B--F62C TEST DAC 10 0 1 1
B--F62E 26 VAC REF 1 9 1 1 1
NOTE: * Open for --908

Table 17. Analog Inputs to Multiplexer U25 (U11) (Enabled by B--M1SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
B--F600 FLAP EXC 4 0 0 0
B--F602 (GROUND)* 5 1 0 0
B--F604 FLAP POS 6 0 1 0
B--F606 TRIM RATE INPUT 7 1 1 0
B--F608 RAD ALT 1 12 0 0 1
B--F60A (GROUND)* 11 1 0 1
B--F60C (GROUND)* 10 0 1 1
B--F60E A--10 V DC REF 9 1 1 1
NOTE: * Open for --908
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Table 18. Analog Inputs to Multiplexer U26 (U15) (Enabled by B--M2SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
B--F610 --13.8 V DC 4 0 0 0
B--F612 AIL SVO I 5 1 0 0
B--F614 AIL SVO TACH 6 0 1 0
B--F616 AIL MTR V 7 1 1 0
F--F618 Y/D MTR I 12 0 0 1
B--F61A RUD SVO TACH 11 1 0 1
B--F61C Y/D MTR VOLTS 10 0 1 1
B--F61E (GROUND)* 9 1 1 1
NOTE: * Open for --908

Table 19. Analog Inputs to Multiplexer U27 (U22) (Enabled by B--M4SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
B--F630 (GROUND)* 4 0 0 0
B--F632 (GROUND)* 5 1 0 0
B--F634 (GROUND)* 6 0 1 0
B--F636 RAD ALT 2 7 1 1 0
F--F638 B TEST A/D NO. 1 12 0 0 1
B--F63A B TEST A/D NO. 2 11 1 0 1
B--F63C (GROUND)* 10 0 1 1
B--F63E (GROUND)* 9 1 1 1
NOTE: * Open for --908

(h) Flight Director Command

1 See schematic sheet 10 (1). The A/P ENG DR signal comes into Q9 (Q7)
where it will turn on Q8 (Q8) and Q9 (Q7) to annunciate the A/P ENGAGE
light.

2 The MAINT ALERT ANNUN DR operates in the same manner to turn on the
MAINT ALERT light.
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J. Analog Inputs CCA A7 (7007595--913, --933)

(1) Refer to 22--1--92, Honeywell Pub. No. A09--1147--056, for the schematic sheets
referenced in the following paragraphs. Analog inputs come into this CCA, Part No.
7007595--913 and --933. Reference designations for the 7007595--933 appear in
parentheses. The analog inputs CCA, Part No. 7007595--913 and --933, performs the
following functions:
• Elevator trim servo command logic
• Yaw damper (Y/D) amplifier
• Analog inputs to the A--A/D converter and the B--A/D converter.
(a) Elevator Trim Servo Command Logic (See schematic sheet 2 (2).

1 The trim logic that creates servo motor clockwise and counterclockwise
command is shown on schematic sheet 2 (2).

2 In order for the elevator trim servo to be driven in either direction, these
signals must be valid:
• Trim disconnect switch off (TRM DISC SW OFF)
• Elevator trim drive enable (TRIM DR EN)
• Trim switched power OK (TRIM SW PWR OK)
• Servo power enable (SVO PWR EN)
• CPU valid.
3 The direction of trim is determined by data bit 15 at A59. The data bit is
clocked through flip--flop U42 (U63) by address A--F970*. The pulse width of
the trim signals at A44 and A46 is determined by data bits A--D11 through
A--D14. These data bits are clocked through latch U36 (U54) by the
A--F970* address. They determine the point at which counter U33 (U59)
starts counting, and thus the width of the pulse. When the counters overflow,
a signal fed back from the inverter U40 (U57) shuts the counter off until the
next cycle. The frequency of the cycles are set by the 488--Hz signal through
U39 (U53). The clock input is the 7.8 kHz input from schematic sheet 3 (16)
to U30 (U58).

(b) RVT Excitation (See schematic sheet 3 (16).)

1 The rotary variable transformer (RVT) excitation circuitry generates an


excitation signal for the rotary variable transformer that is synchronized to a
1.953 kHz rate. The frequency rate is derived from a 125 kHz clock signal
which clocks a 12--bit binary counter. The counter functions as a frequency
divider to divide the 125 kHz signal to produce three frequency outputs:
7.8 kHz, 3.9 KHz, and 1.953 kHz. The 7.8 kHz signal clocks counter U33
(U59) on schematic sheet 2 (2).
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2 The 3.9 kHz signal is inverted and then NAND gated with the 7.8 kHz and
1.953 kHz signals to produce an enable input (EN2) to one of the analog
switches in analog mux U11 (U39). When the output of NAND gate U38
(U66) is low, the analog switch is enabled, allowing data at the switch input
(S2) to pass through the switch. Differential amplifier U16 (U5 on schematic
sheet 11) amplifies the differences between the high and low sides of
differential signal RVT_POS to produce an ac signal at the switch input. By
turning the analog switch on and off at the frequency rate of the enable
input, this ac signal is converted to a dc signal at the output (D2) of the
analog switch. The dc signal is then amplified by U12 (U35) to produce two
analog inputs (A--TRIM POS, B--TRIM POS) for the analog multiplexers on
schematic sheets 10 and 12 (7 and 12), which goes to the A/D converter for
the A and B processors.
3 The enable input (EN1) of the other active analog switch in U11 (U39) is
controlled by the 1.953 kHz signal. When the enable input is low, the +10V
REF at the switch input (S1) passes through the switch and places +10 V dc
at the D1 output of U11 (U39). This + 10 V dc signal is then summed with
the --5 V dc output at pin 6 of U13 (U1 on schematic sheet 9) to produce a
+5 V dc input at pin 2 of U15 (U6 on schematic sheet 9). When EN1 of U11
(U39) is high, the output at pin 6 of U13 (U1) is a --5 V dc, resulting in a
±5 V dc square wave. Since the switch turns on and off at 1.953 kHz rate,
the output (D1) of the switch is a squarewave signal limited to a 5--volt level
by the +5--volt reference output of U13 (U1). The squarewave signal is
amplified by U15 (U6) to produce a sawtooth signal with a frequency of
1.953 kHz. The sawtooth signal is amplified further by U14 (U20) to produce
a LVDT excitation signal (1953HZ_HI) with a peak--to--peak voltage of
±13 volts. This excitation signal drives the rotary variable transformer in the
aircraft.
(c) Yaw Damper Servo Direction Commands (See schematic sheet 4 (3).)
1 The circuitry on this sheet commands the direction of the Y/D servo from
inputs from the B--processor data bus. The sequence to drive the elevator
servo is as follows:
a Data bits D7 through D14 are input to U24 (U36) from the B--processor
(these eight bits set the pulse width for the duty cycle that has been
selected by the processor).
b Data bit D15 is input to U31 (U51) flip--flop as the D input and sets the
direction of travel of the Y/D servo:
• When B--D15* is low the direction is clockwise
• When B--D15* is high the direction is counterclockwise.
c The data bits are latched by the U24 (U36) flip--flop and clocked by the
inverted address of the Y/D servo, B--774*.
d U27 (U62) synchronizes any direction of travel change with the start of a
new pulse--width cycle.
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e This synchronized direction--input is also applied to the U26 (U50) and


U29 (U44) counters to clock in the data bits and set the number from
where the counters will start counting.

f The outputs U31--5 (U51--9) and U31--6 (U51--8) are ANDed with the
125 kHz to set the counter in an up--count mode or a down--count
mode.

g The counters start counting at the number set by the data bits and count
at a rate of 125 kHz until the end of the 488--Hz pulse--width duty cycle.

h The pulse--width signal duty cycle produced by the counters is ANDed


at U37 (U48) with the direction signal from data bit 15 and the following
signals which must be valid to have a servo drive enable signal:
• SVO PWR EN
• SW Y/D PWR OK
• Y/D DISC SW OFF
• Y/D DR EN
• CPU VALID.
i The output of U37 (U48) goes to the Y/D servo amplifier and provides a
signal to drive the servo in a clockwise or counterclockwise direction.

j When the counters time out and the outputs go low, U37--12 (U43--3)
goes low, and the pulse--width signal at U37--6 (U48--8) or U37--8
(U48--12) is removed.

k The counters are now inhibited until the beginning of the next 488--Hz
cycle.

(d) Yaw Damper Servo Amplifier (See schematic sheets 5 and 6 (4).)

1 The Y/D servo amplifier circuitry contains two relays, K1 (K6) and K2 (K7).
The relays are energized by +28 V dc SW Y/D PWR. Q9 is turned on
(U64--15, 16 low) when Y/D ENG CMD from CCA A6 and Y/D SW OFF from
sheet 4 are both high.

a K1 (K6) Relay

(1) When not energized, it routes +28 V dc SW Y/D PWR to Y/D SVO
OFF signal.

(2) When energized, it routes +28 V dc SW Y/D PWR to Y/D SVO ON


and RUD CLUTCH.

b K2 (K7) Relay

(1) When it is not energized, Y/D servo amplifier output stops at the
relay.
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(2) When it is energized, +28 V dc Y/D power routed from T1 through


the rudder servo drive.

2 The clockwise and counterclockwise yaw damper signals created on sheet 4


(3), Y/D CW and Y/D CCW, come into U46 (U70). Either one can be high but
not both. Both can be low.

a When the pulse--width signal created on sheet 4 (3) for clockwise travel
is applied at U46--3 (U70--10):
• The output at U46--1 (U70--8) is a square wave with an amplitude of
±13 V dc
• Q12 (Q25) turns on
• Q17 (Q27) turns on and +28 V dc Y/D goes to K2--6 (K7--2) on sheet
6 (4) and out K2--1 (K7--5) to RUD SVO LO
• Q16 (Q20) turns on and connects ground through K2--2 (K7--6) and
K2--5 (K7--1) to RUD SVO HI
• The rudder servo drives in the clockwise direction.
b When the pulse--width signal created on sheet 4 (3) for
counterclockwise travel is applied at U46--5 (U70--5):
• The output at U46--7 (U70--7) is a square wave with an amplitude of
±13 V dc
• Q14 (Q21) turns on
• Q18 (Q19) turns on and +28 V dc Y/D goes to K2--2 (K7--6) and out
K2--5 (K7--1) to RUD SVO HI
• Q15 (Q28) turns on and connects ground through K2--6 (K7--2) and
K2--1 (K7--5) to RUD SVO LO
• The rudder servo drives in the counterclockwise direction.
c Q11 (Q26) and Q13 (Q22) monitor the --13 V dc and, if it is lost, they will
ground the signals that turn on Q12 (Q25) and Q14 (Q21).

3 U23--8 (U70--1)is the Y/D motor voltage that goes to the analog multiplexer
on sheet 10 (7), to the A/D converter, and back to the processor to be
monitored.

4 U3 (U71) measures differential current across R156 and R161 (R376 and
R395). It is monitored by the processor in the same manner as the Y/D
motor voltage.

(e) Analog Inputs (See schematic sheets 7 thru 10 (5 thru 10).)

1 On schematic sheet 7 (5), the first of a series of seven analog multiplexers


select the signals to the A and B--A/D converters. Four of the multiplexers
are controlled by the A--processor and go to the A--A/D converter. Three are
controlled by the B--processor and go to the B--A/D converter.
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2 The multiplexers are enabled by multiplexer select lines from the processors,
A--M1SEL through A--M4SEL, A--M7SEL, and A--M8SEL, and B--M1SEL
through B--M3SEL. The multiplexers select which analog signals go to the
A/D converters by the logic of the latched address lines LA1, LA2, and LA3
from either the A-- or the B--processor.

3 Analog multiplexer U19 (U13), shown on schematic sheet 7 (5), is different


from the others on succeeding schematic sheets by having the multiplexer
select lines and the latched address lines going through a 2--to--1
multiplexer, U45 (U41 on schematic sheet 10) instead of directly into U19
(U13). The logic has U19 (U13) enabled by three multiplexer select lines,
A--M1SEL, A--M7SEL, and A--M8SEL.

4 There are eight direct analog input pins to U19 (U13). The pitch thumbwheel
lines are differentially sensed at U7 (U2) before input to U19 (U13). Table 20
lists the analog inputs to U19 (U13) and the logic of the latched addresses to
select each analog signal.

Table 20. Analog Inputs to Multiplexer U19 (U13)


(Enabled by A--M1SEL, A--M7SEL, and A--M8SEL)
Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
A--F800 PITCH TW 4 0 0 0
A--F802 GROUND 5 1 0 0
A--F804 GROUND 6 0 1 0
A--F806 --13V DC 7 1 1 0
A--F808 GROUND 12 0 0 1
A--F80A GROUND 11 1 0 1
A--F80C B--10 V REF 10 0 1 1
A--F80E 9 1 1 1

5 On schematic sheets 8, 9, and 10 (5, 7 thru 10), the analog inputs go to


multiplexer U6 (U24) which is enabled by A--M2SEL, and multiplexer U18
(U23) which is enabled by A--M4SEL. The analog signal select lines,
A/D--A0, A/D--A1, and A/D--A2, come from schematic sheet 7 (10) to U6
(U24) and U18 (U23).

6 CRS PITCH TW, TRIM SVO TACH, and RUD SVO TACH signals go to
differential amplifiers then to the multiplexer U6 (U24).

7 Table 21 lists the analog inputs to U6 (U24) and the logic of the latched
addresses to select each analog signal. Table 22 does the same for U18
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Table 21. Analog Inputs to Multiplexer U6 (U24) (Enabled by A--M2SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
A--F810 GROUND 4 0 0 0
A--F812 B--TRIM SVO I 5 1 0 0
A--F814 RUD SVO TACH 6 0 1 0
A--F816 CRS PITCH TW 7 1 1 0
A--F818 B--TRIM SVO TACH 12 0 0 1
A--F81A GROUND 11 1 0 1
A--F81C +5 V DC ISO 10 0 1 1
A--F81E GROUND 9 1 1 1

Table 22. Analog Inputs to Multiplexer U18 (U23) (Enabled by A--M4SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
A--F830 ELEV SVO I 4 0 0 0
A--F832 ELEV SVO TACH 5 1 0 0
A--F834 ELEV MTR V 6 0 1 0
A--F836 PITCH D/A 7 1 1 0
A--F838 GROUND 12 0 0 1
A--F83A 11 1 0 1
A--F83C 10 0 1 1
A--F83E ROLL D/A 9 1 1 1

8 Some of the signals go over to schematic sheet 12 (13) as B--addresses.


These are input to analog multiplexers that select analog signals to be
converted by the B--A/D converter.
9 The outputs of U6 (U24) and U18 (U23) go to schematic sheet 7 (10) where
the outputs of all the analog multiplexers are combined for an A/D ANALOG
INPUT to the A--processor.
10 Analog multiplexer U17 (U25) is shown on schematic sheet 10 (7). U17
(U25) is enabled by A--M3SEL. Table 23 lists the analog inputs to U17 (U25)
and the logic of the latch addresses to select each analog signal.
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11 All of the outputs of the analog multiplexers going to the A--processor are
connected together with A--PREZERO* and buffered by U20 (U19) before
going to the A--A/D converter.

12 The A--PREZERO* applies a ground to the A--A/D_INPUT signal at U19--8


(U14--8). The A processor measures the value of ground and subtracts this
value from the value of multiplexed signals to obtain their true value when
performing A/D conversions.

Table 23. Analog Inputs to Multiplexer U17 (U25) (Enabled by A--M3SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
A--F820 AIL SVO I 4 0 0 0
A--F822 AIL SVO TACH 5 1 0 0
A--F824 AIL MTR V 6 0 1 0
A--F826 Y/D MTR I 7 1 1 0
A--F828 GROUND 12 0 0 1
A--F82A Y/D MTR VOLTS 11 1 0 1
A--F82C A--TRIM POS 10 0 1 1
A--F82E TRIM MTR V 9 1 1 1

(f) Analog Signals to B--A/D Converter

1 See schematic sheets 11 and 12 (12 and 13). Three analog multiplexers are
shown on schematic sheets 11 and 12 (12 and 13) that select the analog
signals for the B--A/D converter. These signals are selected in the same
manner as the ones on the previous sheets were for the A--A/D converter.
The multiplexers are enabled by multiplexer select lines from the
B--processor. The analog signals are selected by latched address lines from
the B--processor.

2 The outputs of all three multiplexers are connected together with


B--PREZERO* and buffered by U4 (U16) before going off--card to the B--A/D
converter.

3 Table 24 through Table 26 list the analog inputs to U8 (U15), U9 (U11), and
U21 (U21), and the logic of the latched addresses to select each analog
signal.

4 The U22 (U31) test DAC receives a word from the B--processor, converts the
word and reads it back to check out the A/D conversion loop.
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Table 24. Analog Inputs to Multiplexer U21 (U21) (Enable by B--M3SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
B--F620 ELEV SVO I 4 0 0 0
B--F622 ELEV SVO TACH 5 1 0 0
B--F624 ELEV MTR V 6 0 1 0
B--F626 GROUND 7 1 1 0
B--F628 GROUND 12 0 0 1
B--F62A GROUND 11 1 0 1
B--F62C TEST DAC 10 0 1 1
B--F62E GROUND 9 1 1 1

Table 25. Analog Inputs to Multiplexer U9 (U11) (Enabled by B--M1SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
B--F600 4 0 0 0
B--F602 5 1 0 0
B--F604 B--TRIM MTRV 6 0 1 0
B--F606 B--TRIM SVO I 7 1 1 0
B--F608 B--TRIM SVO TACH 12 0 0 1
B--F60A GROUND 11 1 0 1
B--F60C GROUND 10 0 1 1
B--F60E A--10 V DC REF 9 1 1 1
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Table 26. Analog Inputs to Multiplexer U8 (U15) (Enabled by B--M2SEL)


Mux
Selected Input A/D--A0 A/D--A1 A/D--A2
Analog Signal Pin Pin 1 Pin 16 Pin 15
B--F610 --13.8 V 4 0 0 0
B--F612 AIL SVO I 5 1 0 0
B--F614 AIL SVO TACH 6 0 1 0
B--F616 AIL MTR V 7 1 1 0
F--F618 Y/D MTR I 12 0 0 1
B--F61A RUD SVO TACH 11 1 0 1
B--F61C Y/D MTR VOLTS 10 0 1 1
B--F61E B--TRIM POS 9 1 1 1
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TESTING AND FAULT ISOLATION


1. Overview
A. General

(1) The function of the test procedures is to find if there is a failure in the operation of the
FGC. If corrective steps are necessary, you must make sure the product is in
serviceable condition.

(2) Use the test procedures in this section to test and fault isolate the FGC.

(3) Refer to the ATS TPOS+ Report (Test Program and Operating Software) website for
the current revision status of test software and hardware adapter MOD status at:
https://pubs.cas.honeywell.com/.

(4) Table 1001 is a list of test procedures and gives the revision status, applicability, and
location of each procedure. Use the applicable procedure to make an analysis of
performance of the FGC.

Table 1001. Test Procedures

Procedure Part Number Revision Used On Table

Procedures for troubleshooting FGC D FGC FZ--600/800/820 Table 1003


(EB7016886)
FZ--NVRAM initialization and data G Valid only for uses on STZ--100 with Table 1004
retrieval (EB7019295) MOD G or higher for FZ--800
IT7003974--708 Y Test procedure for the FGC Table 1005
7003974--708, --713, --728, --732
IT7003974--717 F Test procedure for the FGC Table 1006
7003974--717, --724, --725
FZ--800 Burn--in System (EB7014484) B For FZ--800 Table 1007
IT Procedures Test Descriptions C Reference schematic part numbers Table 1008
(EB7016995)
IT Procedures Test Descriptions B Reference schematic part numbers Table 1009
(EB7019293)
Fluke 9010 Tests on the FZ--600/800 -- Tests the FZ--600/800 Table 1010
(EB7016776)
IT7013181 A Test procedure for the FZ--800 power Table 1011
supply card Part No. 7013181--901,
--902

(5) Table 1002 is a list of equipment for fault isolation not used in Table 1004,
Table 1005, Table 1006, or Table 1010.
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(6) Table 1003 is an aid to troubleshooting the FGC, and includes the procedures to do
temperature and vibration tests.

(7) Table 1004 gives the procedures to initialize and retrieve data from the nonvolatile
RAM on the 7003974--713, 7003974--717, 7003974--724, 7003974--725,
7003974--728, and 7003974--732 units.

(8) Table 1005 and Table 1006 are the test specification for the FGC. Procedures in
Table 1005 are used to test the 7003974--708, --713, --728, and --732 units.
Procedures in Table 1006 are used to test the 7003974--717, --724 and --725 units.

NOTE: The latest revision of the Integrated Test Specification (IT) will give the
revision of the floppy diskettes used for testing the FGC on the STZ--100
Series Test System (STZ). Original and revised copies of the IT and the
diskettes will be distributed by Honeywell to all users.

NOTE: All nonapplicable aircraft information in Appendix G has been removed.


• Appendix A Calibration Procedures
• Appendix B Debug Utility Functions
• Appendix C Card Edge Adapter Debug Tests
• Appendix D FGC Individual Card Descriptions
• Appendix E Error Messages
• Appendix F Power Supply Measurement Information
• Appendix G Software Power--Up Test Implementation
• Appendix H Flight Software Verification Information
(9) Table 1007 is the user manual for the FZ--600/800 Burn--in System. The burn--in
process in Table 1007 is an alternative to the temperature test in Table 1003.

(10) Table 1008 gives the description of the tests that make up the end item test in
Table 1005.

(11) Table 1009 gives the description of the tests that make up the end item test in
Table 1006.

(12) Table 1010 gives the procedure to do a test on the FGC with the Fluke 9010 if
the processors in the unit do not respond when you try to do an end item test.

(13) Table 1011 is the card level test for the FGC power supply using the (optional) power
supply card test adapter.

B. Equipment and Materials

(1) Refer to the applicable test procedure for equipment.

(2) Refer to Table 1002 for fault isolation not listed in Table 1004, Table 1008, or
Table 1010.
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WARNING: BEFORE YOU USE A MATERIAL, REFER TO THE MANUFACTURERS’


MATERIAL SAFETY DATA SHEETS FOR SAFETY INFORMATION. SOME
MATERIALS CAN BE DANGEROUS.

(3) Refer to the applicable test procedure for materials.

(4) Equivalent alternatives are permitted for equipment and materials. It is the
responsibility of the user to determine equivalent alternatives.

Table 1002. Equipment for Fault Isolation


Item Description Source Table
Gyro vibration fixture Part No. T321693 Honeywelll, Aerospace Table 1003
Electronic Systems,
Phoenix, AZ
(CAGE 58960)
Mounting tray fixture Part No. 7009050--901 Honeywelll, Aerospace Table 1003
Electronic Systems,
Phoenix, AZ
(CAGE 58960)
Aluminum adapter plate Part No. 7003303--901 Honeywelll, Aerospace Table 1003
Electronic Systems,
Phoenix, AZ
(CAGE 58960)
FZ--800 Burn--in fixture Part No. T335531 Honeywelll, Aerospace Table 1007
Electronic Systems,
Phoenix, AZ
(CAGE 58960)
CCA A8 Burn--in test Part No. 7014173--901 Honeywelll, Aerospace Table 1007
PWB Electronic Systems,
Phoenix, AZ
(CAGE 58960)
Card edge adapter A--processor Part No. Honeywelll, Aerospace Table 1005, Table 1006
7009492--903 Electronic Systems,
Phoenix, AZ
(CAGE 58960)
Card edge adapter B--processor Part No. Honeywelll, Aerospace Table 1005, Table 1006
7009502--902 Electronic Systems,
Phoenix, AZ
(CAGE 58960)
Syntron paper jogger Model J50 FMC Technologies, Table 1003
Materials Handling
Division, Homer City, PA
(CAGE 58849)
Multimeter Model 87 Fluke Corp, Everett, WA Table 1003
(CAGE 89536)
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Table 1002. Equipment for Fault Isolation (cont)


Item Description Source Table
Fluke logic analyzer Model 9010 Fluke Corp, Everett, WA Table 1009, Table 1010
(CAGE 89536)
Variable ac transformer Model 3PN1510 Staco Energy Products Table 1003
Co, Dayton, OH
(CAGE 83008)
Temperature chamber Range of +50 to --40_C Optional source Table 1003
IBM Compatible PC with Optional source Table 1007
printer and PROCOMM
software program

2. Procedure
CAUTION: THE FGC CONTAINS ESDS ITEMS. USE PROTECTIVE PROCEDURES.
A. Test Setup
(1) Refer to STZ--100 Series Test Systems Ground Equipment Manual, Honeywell Pub.
No. A31--1146--04, Volume l, Operating Procedures, to make the STZ test setup.
(2) Load the applicable program diskette, MT7003974--708 REV Y, and do the tests in
accordance with the instructions in Table 1005 of this manual.
(3) Load the applicable program diskette, MT7003974--717/724/725 REV F, and do the
tests in accordance with the instructions in Table 1006 of this manual.
B. Test Procedure
(1) Do the procedures that follow to make a printed copy of the FGC test program.
NOTE: The files on the diskettes are condensed, i.e., all comments have been
removed and all MATEL code has been abbreviated. For detailed comments
and MATEL codes, refer to the printed copy of the IT test program that is
supplied with the test diskettes.
NOTE: Each diskette can contain many different files of a program of many different
programs. Each file or different program must be loaded and printed one at
a time.
(a) Turn on the STZ and the printer. Load the interpreter and program diskettes into
the STZ memory. A colon (:) prompt will come into view.
(b) Type DIR and push RETURN. This will give a directory of all filenames on the
diskette.
(c) Type R and push the space bar. Type the correct program name that is to be
printed (refer to the directory). Push RETURN. The program is now loaded into
memory.
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(d) Type B and push RETURN. This puts the program pointer at the beginning of the
program.

(e) Type ED and push RETURN. This puts the STZ into the edit mode. The colon
prompt will change to a number symbol (#) prompt.

NOTE: After step (e), the STZ will show on the screen the number of lines of
test in the program.

NOTE: After the RETURN key is pushed in step (f), the printout of the test
program cannot be stopped until it is completed.

(f) Type .--2,$SPP and push RETURN. This prints the program stored in the STZ
memory.

(g) Type Q and push RETURN. This removes the STZ from the edit mode. The
number symbol prompt will be replaced by the colon prompt.

(h) Repeat steps (a) thru (g) for each file or program to be printed.

C. Fault Isolation

(1) For 700397--708, --713, --728, and --732 units, retrieve the data from the NVRAM.

(2) For 700397--717, --724, and --725 units, retrieve the data from the NVRAM.

(3) Use Figures 1, 1.1, and 1.2 of Table 1003 to find the route of the units returned for
repair.

(4) When a failure message appears during the end--item test, refer to the following to
aid in fault isolation:

• Printed copy of the test program


• Appendix G in Table 1005 and Table 1006 if the failure occurred during the
preflight or power--up tests
• Table 1008 for a description of the end--item tests
• Appendix D of Table 1005 or Table 1006 for CCA descriptions and functions
• ATA 22--11--92, Honeywell Pub. No. A09--1147--056, for schematics on each CCA
• DESCRIPTION AND OPERATION in this manual
• STZ--100 Series Test Systems Ground Equipment Manual, Honeywell Pub. No.
A31--1146--004, for information to help interpret the test program.

(5) When a repair or replacement of parts is necessary, refer to ILLUSTRATED PARTS


LIST in this manual for complete item description. If the repair is to any of the CCAs,
refer to the ILLUSTRATED PARTS CATALOG in 22--11--92, Honeywell Pub. No.
A09--1147--056.
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Table 1003. Troubleshooting Procedures

TITLE: Procedure for Troubleshooting Flight Guidance Computers (FZ-600/800/820) at Repair


Facilities

1.0 SCOPE

This Engineering Bulletin is to aid the technicians in troubleshooting Flight Guidance


Computers, and to reduce unverified failures in the field.
THIS BULLETIN SUPERSEDES SIB 89-21.

2.0 REFERENCE DOCUMENTS

TBD.

3.0 PROCEDURE

3.1 Routing Procedure

When an applicable Flight Guidance Computer is received for repair or modification, it is


to be routed per Figure 1 of this procedure if MOD CS or MOD DD is installed, or per
Figure 1.2 if MOD CS or MOD DD is not installed.

NOTE: Unit should not be opened until incoming test has been performed
using the preflight test in the end item test or using the system
bench.

This procedure is usable on all FZ-600, -800, and -820 Flight Guidance Computers.

3.2 Definitions for Use of Figure 1 and Figure 1.1

3.2.1 Bad Actor Criteria - Bad actor units are defined in the "Bad Actor Elimination Process"
document generated by customer engineering.

3.2.2 Squawk Verified

• YES--Failure identified directly relates to squawk.

• NO--No Integrated Test failures related to squawk.


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Table 1003. Troubleshooting Procedures (cont)

3.2.3 Temperature Test

• Place unit in the oven and connect the adapter cable to it.

• Set temperature of oven to +50 degrees Celsius (hot).

• After 1 to 1.5 hours, apply power and test unit on the STZ-100 using the Customer
Test in a loop for 6 to 10 times.

• Set temperature of oven to -40 degrees Celsius (cold) while unit is still testing in
a loop.

• After oven has stabilized at -40 degrees Celsius, run the Customer Test one time.

NOTE: Power may be removed from unit after this test.

• After 0.5 hours, apply power and test unit on the STZ-100 using the Customer Test in
a loop for 6 to 10 times.

NOTE: Burn-in, per User Manual for FZ-600/800 Burn-In System, EB7014484, may be
used if available in lieu of the above temperature test. The FZ-800 burnin
fixture referenced in that EB is the single channel fixture, Part No. T335531.
This fixture can be used for all applications of FZ as long as the necessary
LRU wiring exists in the wiring harness. In general, units built after June
of 1988 will have the necessary wiring.

3.2.4 DELETED.

3.2.5 DELETED.
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Table 1003. Troubleshooting Procedures (cont)

3.2.6 LRU Test

• Test unit per the Integrated Test Specification.

3.2.7 Vibration Test - The test equipment consists of:

• Either System bench or STZ-100 with Flight Guidance Test Adapter, Part No.
7007894-901.

• T321639--Gyro vibration fixture per Figures 3 and 4, or modified Syntron Jogger per
Figures 5 and 6.

• Mounting tray assembly, Part No. 7009050-901, modified with a six-foot cable.

• Aluminum adapter plate, Part No. 7003303-901 (modified), or equivalent.

NOTE: The vibration fixture provides a low level vibration to reveal mechanical
problems.

3.2.8 STZ-100 Vibration Setup

• Set up equipment at room temperature per Figure 3 or 5 of this EB.

NOTE: If equipment per Figure 5 is used, monitor paper jogger's input voltage with
FLUKE 87 multimeter (or equivalent). Use STACO variac model 3PN1510 (or
equivalent with a load rating of at least 1 kVA) to set input voltage to
80 volts. Set control knob to position 10 corresponding to
approximately 1.5 g.

• Start vibration.

• Power up Flight Guidance Computer.

• Maintain power and vibration for 15 minutes while running the preflight portion of
the Integrated Test in a loop or Customer Test.

• Verify preflight test for any occurred failures.


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Table 1003. Troubleshooting Procedures (cont)

3.2.9 System Bench Vibration Setup

• Set up equipment at room temperature per Figure 4 or 6 of this EB.

NOTE: If equipment per Figure 6 is used, monitor paper jogger's input voltage with
FLUKE 87 multimeter (or equivalent). Use STACO variac model 3PN1510 (or
equivalent with a load rating of at least 1 kVA) to set input voltage to
80 volts. Set control knob to position 10 corresponding to
approximately 1.5 g.

• Start vibration.

• Power up system bench.

• Test Flight Guidance Computer on the system bench per Production Audit Bench Test
Procedure.

3.2.10 Final Inspection

• Final inspector is to put a yellow dot on the unit when it has been completed per
this EB. It will be located per Figure 2 of this EB.

• Inspection is to make sure that a statement has been written on the SUMAR that this
Engineering Bulletin has been accomplished.
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Table 1003. Troubleshooting Procedures (cont)

Routing Procedure for FGC With MOD CS or MOD DD


Figure 1
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Table 1003. Troubleshooting Procedures (cont)

Routing Procedure for FGC With MOD CS or MOD DD


Figure 1.1
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Table 1003. Troubleshooting Procedures (cont)

Routing Procedure for FGC Without MOD CS or MOD DD


Figure 1.2
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Table 1003. Troubleshooting Procedures (cont)

Front of Unit
Figure 2
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Table 1003. Troubleshooting Procedures (cont)

STZ-100 Vibration Setup


Figure 3
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Table 1003. Troubleshooting Procedures (cont)

System Bench Vibration Setup


Figure 4
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Flight Guidance Computer / Part No. 7003974

Table 1003. Troubleshooting Procedures (cont)

STZ-100 Vibration Setup


Figure 5
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Table 1003. Troubleshooting Procedures (cont)

System Bench Vibration Setup


Figure 6
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Table 1003. Troubleshooting Procedures (cont)

Table of Known Bad Date Code PWBs and Components

Printed Wire Boards


CCA PWB Date Code Vendor
A3 7010215 89-32 Quality Printed Circuits
A6 7010214 90-14 Quality Printed Circuits
90-20 Quality Printed Circuits
Components
CCAs Generic Part Number Date Code Vendor
A7 DG508A 7000822-125 87-14 Siliconix
87-32 Siliconix
A7,A2 Relay 7007316 Any HI-G

Table of Identifying Marks

II
III QUALITY
Quality Printed Circuits
94V - 0

89 - 32 <- Date Code

Siliconix

HI-G HI-G written on the relay


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Table 1004. NVRAM Initialization and Data Retrieval

TITLE FZ--NONVOLATILE RAM INITIALIZATION AND DATA RETRIEVAL

1.0 SCOPE
This document describes procedures to initialize and retrieve data from the MOD CC or MOD DF
Nonvolatile RAM (NVRAM).
This procedure is only valid for use on the STZ--100 with MOD G or higher in conjunction with the
required interpreter and adapters as listed in Section 5.
This procedure is based on Engineering Bulletin EB7019295, Revision G.

2.0 REFERENCE DOCUMENTS


DELETED.

3.0 GENERAL INFORMATION


The FZ--600/800/820 with MOD CC/DF installed has NVRAM on the A6 card, which contains
information that needs to be retrieved. This data must be retrieved before unit undergoes End Item
testing. After the unit has passed End Item testing, the NVRAM must be initialized with the proper
configuration provided. The data retrieval is done through the STZ--100 via the ASCB, data is first
written to STZ RAM, then dumped to floppy disk. The initialization procedure also makes use of
the STORE function on the Card Edge Adapter, therefore, the Card Edge Adapter cards must be
installed during this procedure.
This EB will be called out at the beginning of each IT before power is applied to the unit. There are
two types of floppy disks associated with the EB. One contains the MATEL code necessary to
perform the data retrieval and initialization of the NVRAM, it will also contain the current
configuration data required. This disk will be unique to each IT. The second disk is a formatted
blank disk used to store the retrieved data.
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Table 1004. NVRAM Initialization and Data Retrieval (cont)

4.0 POWER AND SIGNAL REQUIREMENTS


All power and signal requirements for this procedure are supplied by the STZ through the adapters
as listed in Section 5.

5.0 TEST EQUIPMENT


The following test fixtures and equipment are required in the performance of this procedure:
Part Name Part Number

STZ--100 7006326--902 MOD G or higher


FZ--800 End Item Adapter 7007894
J100 Jumper Plug 7007893--XXX as stated in software
J101 Jumper Plug 7007893--XXX as stated in software
EIT -- Card Edge Adapter -- A 7009492--903/904 MOD J or higher
EIT -- Card Edge Adapter -- B 7009502--902 MOD F or higher
Rev. 5.2 or later STZ--100 Interpreter D7008737--902
FZ--800 NVRAM Init and Download Disk MT7019296 (see TPOS website for
revision status)
Blank 360 K Byte Disk 4052497--1
NOTE: User must format blank disk prior to use.

6.0 TEST SETUP (SEE FIGURE 1)

6.1 STZ--100
Connect the test adapter, patch plugs, and adapter cable to the STZ--100 as shown in figure 1.

6.2 Operation
Follow the instructions in the STZ--100 Operator’s Guide to start up the STZ--100. Read in the
AUTOLOAD file, which supplies a menu to choose from. All other instructions will be supplied
on the CRT terminal as needed.
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Table 1004. NVRAM Initialization and Data Retrieval (cont)

Figure 1. Block Diagram of Test Setup


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Table 1004. NVRAM Initialization and Data Retrieval (cont)

7.0 PROCEDURE

7.1 Data Retrieval


The data retrieval procedure will consist of running the MATEL code, NVRDUMP, or G4DUMP
for the G--IV models, on the STZ. This procedure will be performed before any testing of the
unit takes place. The NVRDUMP will begin by requesting the user to remove the card edge
adapters if they are installed. The program will then begin retrieving data from the units NVRAM
starting at address 8000 hex and ending at BFFE hex. This data is loaded into the STZ RAM
starting at address C0000 hex. The data will also be printed onto the terminal screen to show
that the program is working. Once all the data is transferred to the STZ RAM, the user will be
prompted to insert the blank floppy disk. The file that is loaded onto the floppy will be a binary
file of data only, which will be titled NVRAM.STZ. This floppy should then be labeled with the
unit’s product number, serial number, SUMAR identification number, date and place of retrieval.
The floppy will then be mailed to customer support engineering at the address given below. In
those cases where the unit will not bring up the ASCB, the procedure can either be ignored, or
the data can be retrieved by replacing the A6 CCA in a known good unit of the same end item
number and running the above procedure.
The information listed in Appendices A through E may be retrieved by accessing the information
on the STZ.
Honeywell Inc.
Nonvolatile RAM Support
Commercial Support Engineering
5353 West Bell Road
Glendale, AZ 853083

7.2 Initialization
The initialize NVRAM will consist of running the MATEL code, NVRINIT on the STZ. This
procedure will be performed after the final preflight portion of the EIT. The NVRINIT program
will begin by requesting the user to install the card edge adapters stated in the above equipment
list. The program will then load the NVRAM with the appropriate configuration data provided.
Only those addresses provided in the configuration file will be loaded. The current address and
data being loaded will be printed to the terminal screen to show that the procedure is running.
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Table 1004. NVRAM Initialization and Data Retrieval (cont)

8.0 CONFIGURATION DATA


The configuration data file is a 68000 executable binary file providing the NVRAM address and
data. This file is loaded into the STZ--100 memory starting at address C0000. A QUICKBASIC
program has been written (see Appendix B for listing) which converts a ASCII format file into
defined word assembly statements. The ASCII file contains the address and data desired for
initialization. There is one address and data separated by a space per line. This defined word file
is then combined with a 68000 header and trailer assembler files. The header file (see Appendix C)
provides some title information and the ORG statement. The ORG statement sets the programs
assembly starting address to C0000. The trailer file (see Appendix D) provides the INIT flag needed
by the flight software and the C000 address. The C000 address tells the NVRINIT matel code to
stop the initialization of the NVRAM. The INIT flag at address BFDC, when set equal to A3A3 hex,
states that NVR has been initialized. The combined output file is then assembled and linked by the
2500AD SOFTWARE INC. 68000 MACRO ASSEMBLER. The executable file (NVRDATA.TSK)
created by the assembler is merged with a STZ header file (LASM.HDR). The STZ header is 32
bytes of data used by the STZ and then stripped off when loaded into memory. This header was
provided by the STZ engineering group. The merged file (NVRDATA) is the 68000 executable file
that can be loaded onto the floppy disk. There is a version number associated with each
configuration. This version number will stored in two words at location BE5E and BE60 hex and
should be included in the ASCII format file. The G--IV versions has several words reversed on A
and B processors for use with the flight fault summary display. Therefore, the addresses shown
below must remain in their default state.
A CPU ADDRESSES B CPU ADDRESSES
BF00 BFA8
BF02 BFAA
BF04 BFAC
BF06 BFAE
BF10 BFB0
BF14
BF16
BF18
BF1A
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Table 1004. NVRAM Initialization and Data Retrieval (cont)

APPENDIX A
MATEL CODE LISTINGS FOR NVRINIT, NVRDUMP AND GIVDUMP
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Table 1004. NVRAM Initialization and Data Retrieval (cont)

APPENDIX B
QUICKBASIC CODE FOR ASSEMBLING NVR ADDRESS AND DATA
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Table 1004. NVRAM Initialization and Data Retrieval (cont)

APPENDIX C
NVR ASSEMBLE HEADER FILE
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Table 1004. NVRAM Initialization and Data Retrieval (cont)

APPENDIX D
NVR TRAILER ASSEMBLE FILE
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Table 1004. NVRAM Initialization and Data Retrieval (cont)

APPENDIX E
CLNVR ADDRESS AND DATA ASCII FILE
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Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732

END ITEM TEST FOR DIGITAL FLIGHT CONTROL SYSTEM, (DAFCS) FZ--800 PART
NO. 7003974--708/713/728/732

1. SCOPE
This test specification contains procedures and requirements needed to insure that the Digital
Flight Guidance Computer (FGC) is in proper operating condition at the End Item Level.
This document also contains in the appendices additional information which, in most cases, will
support failure diagnosis to the card level.
This procedure is only valid for use on a Honeywell STZ--100 automatic test system in conjunction
with the required adapters as listed in Section 5.
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Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

2. GENERAL INFORMATION
The FZ--800 is a dual processor digital computer system and is tested as a digital computer with
I/O. Software in the card edge adapters on top of the processor cards in the Autopilot
communicates with the STZ--100 to achieve the level of testing necessary. The STZ--100 is the
master, and the two processors in the Autopilot are slaves. The STZ--100 sequences through the
test and requests information from the Autopilot as needed or requests the Autopilot to run internal
tests and report the results. All communication is accomplished via the ASCB and the dedicated
words for the FTIU. To simplify the reading of the main test program and to optimize its size and
execution, the communication routines and other common I/O routines in the STZ--100 test
program are subroutines located at the end of the program listing.

3. POWER AND SIGNAL REQUIREMENTS


All power and signal requirements for this test are supplied by the STZ--100 through the adapters
as listed in Section 5.

4. TEST EQUIPMENT
The following Honeywell Flight Systems Test Fixtures and equipment are required in the
performance of this test:
Part Number
STZ--100 7006326--901
FZ--600/800/820 End Item Adapter 7007894
J100 Jumper Plug 7007893--905
J101 Jumper Plug 7007893--915
Y FZ--800 End Item Diskette MT7003974--708 (see TPOS
website for revision status)
EIT -- Card Edge Adapter -- A 7009492--903 MOD J or later
EIT -- Card Edge Adapter -- B 7009502--902 MOD F or later
Debug Card Edge Adapter -- A 7009492--901
Debug Card Edge Adapter -- B 7009502--901
Power Supply Calibration 7009920
Card Edge Adapter
Oscilloscope With Compensated Probes and 100 MHz
Bandwidth
Calibrated External Power Supply
(Recommended Power Designs Inc. Model 2010)
Edge Connector for A1 Card Recommended
Power Supply Test Adapter Optional) 7016621
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5. TEST SETUP (SEE FIGURE 1)

5.1 STZ--100
Connect the test adapter, patch plugs, and adapter cable to the STZ--100 as shown in Figure 1.

5.2 Printer
Be sure there are at least 30 pages of paper for the printer to use.

5.3 Operation
Follow the instructions in the STZ--100 Operator’s Guide to start up the STZ--100. Read in the
test file and execute. The name of the test file is located on the first page of the program listing.
All other instructions will be supplied on the CRT terminal as needed.

6. TEST REQUIREMENTS
Calibration procedures are required on the power supply (card 1) and the A/Ds (card 5) at the
production level on all units, and may be required for servicing return units if the power supply
voltages fail the end item test verifications. Refer to Appendix A for the calibration procedures.
The ‘FINAL’ End Item Test must be run in its entirety and is not to be entered except at the
beginning. If failures occur during the test, there are debug functions available to the user.
To run the UTILITY debug functions, see Appendix B.
To run the CARD EDGE ADAPTER debug functions, see Appendix C.
After a successful (no failures) ‘complete End Item Test’ run, the resident software in the Autopilot
must be verified. This is done by removing the card edge adapter (if and only if, power is not
applied to the FGC) entering and executing the ‘pre--flight test’ portion of the EIT. If there were no
errors in the main portion of the EIT, the ‘pre--flight’ test is automatically entered and the test
operator will be instructed to remove the card edge adapters.

7. AIRWORTHINESS/PRODUCT SAFETY INFORMATION


The following tests are design and production critical:
5.3.32, 5.3.33, 5.3.34, 5.3.35, 5.3.36, 5.3.37, which test the aircraft configuration identification
discretes and tests 8.10.0, 8.10.1, 8.10.2, 8.10.3, 8.10.4, 8.11.0, 8.11.1, 8.11.2 which test the flight
software to insure that the correct software is being used.
100% compliance with these tests is required.
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Figure 1. Block Diagram of Test Setup


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APPENDIX A
CALIBRATION PROCEDURES
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APPENDIX A
CALIBRATION PROCEDURES
A1. APPLICABILITY
The two items needing calibration are the power supply (card 1) and the A/Ds (card 5). Calibration
procedures are required only at the production level. However, recalibration of the power supply
may be necessary when servicing returned units if the power supply voltages fail the end item test
verifications.
Reference designators and voltages for the power supply calibration will be for mod “CR” supplies.
Information for pre--mod “CR” will be enclosed in brackets (i.e. {}).

A2. POWER SUPPLY CALIBRATION PROCEDURE


This section defines procedures for calibrating the FGC power supply. A special card edge adapter
to provide loads, for the power supply, is required.
The power supply may be calibrated in one of two ways:

1. Installed in the FGC rack with all other cards present, or

2. Installed in the FGC rack with all other cards removed.

Method 1
This method uses the real load of the rack and is the preferred method of calibration.

1.1 With cards A2 through A7 inserted in the rack, place card A1 (power supply card) on an
extender and insert in rack.

1.2 Connect a resistor decade box in place of R151 {R95} on the power supply assembly. Set the
decade box to a value of 3K {1k} ohms.

1.3 Apply 28.0 ± 1.0 V dc power to the rack by using the ‘power’ routine in the normal fashion.
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1.4 Monitor the voltage at the +5 V dc test points provided on the card edge connector (B23).
Make sure that signal ground (B16) is used as a reference for these measurements. Adjust
the value of R151 {R95} until the +5 V dc output reads +5.00 ±0.010 {+5.00 ± 0.25} V dc.
Measure the +14.2 {+13.8} V dc and +5 V dc Standby outputs and verify that these outputs are
within the tolerance specified below.

+14.2 V dc supply +14.2 ± 0.75 V dc


{+13.8 V dc supply +13.8 ± 0.75 V dc}
--14.2 V dc supply --14.2 ± 0.75 V dc
{--13.8 V dc supply --13.8 ± 0.75 V dc}
+5 V dc Standby +5 V dc ± 0.42 V dc
{+5 V dc Standby +5 V dc ± 0.42 V dc}

{ Note that the +5 V dc output may be adjusted anywhere within the allowed range in order to
make the other outputs be within the tolerance specified.}

Install select resistor (nearest value to decade box setting) from the applicable resistor
selection called out on CCA drawing number 7013181 {7007583}.

1.5 Calibrate the monitors by selecting R29 {R70} and R45 {R76} as follows:

Connect a decade resistor in place of R29 {R70} while monitoring the voltage on TP--6B.
Adjust the value of R29 {R70} until the voltage at TP--6B is 4.70 ± 0.010 V dc {TP--5B is 4.51 ±
0.02 V dc}. Install select resistor (nearest value to decade box setting) from the applicable
resistor selection called out on CCA drawing number 7013181 {7007583}.

Connect a decade resistor in place of R45 {R76} while monitoring the voltage on TP--7B.
Adjust the value of R45 {R76} until the voltage at TP--7B is 5.30 ± 0.010 V dc {5.49 ± 0.02 V
dc}. Install select resistor (nearest value to decade box setting) from the applicable resistor
selection called out on CCA drawing number 7013181 {7007583}.

Method 2

This method uses an artificial load provided by the Power Supply Calibration Card Edge
Adapter.

2.1 Remove all cards from the rack and place the Power Supply Calibration Card Edge Adapter
on the top connector of the A1 (power supply card). Make sure that the component side of
the Power Supply Calibration Card and the component side of the A1 (power supply card)
face in the same direction.

2.2 Perform Steps 1.2 through 1.5 of Method 1.

NOTE: After calibration of the power supply using Method 2, the voltage values of the power supply
should be rechecked using the real rack load as described in Method 1.
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Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

APPENDIX B
DEBUG UTILITY FUNCTIONS
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APPENDIX B
DEBUG UTILITY FUNCTIONS
B1. ENTERING THE UTILITY

The UTILITY is an interactive program which prompts the user with a menu of functions that can be
performed. UTILITY is entered via MENU selection from EIT.

B2. AVAILABLE FUNCTIONS

The UTILITY will provide a menu of functions and prompt the user for the number of the function
requested. The functions and their uses are as follows:

0 -- Return to ‘MAIN’ selection menu

This is the exit path from the UTILITY routine. It will return the user to the beginning of the
End Item Test with the ‘MAIN’ selection menu.
1 -- Initialize the FZ--600/800/820 (power up/down and bring up the ASCB)
2 -- Write to an FZ--600/800/820 memory location (single processor test)
This will allow the user to write to any FZ location upon demand.
3 -- Read from an FZ--600/800/820 memory location (single processor test)
This will allow user to read from any (many) FZ location(s) upon demand.
4 -- Do a READ scope loop.
This will allow the user to continually read from a given FZ location for the purpose of provid-
ing a discernable scope trace.
5 -- Do a WRITE scope loop.
This will allow the user to continually write to a given FZ location for the purpose of providing
a discernable scope trace.
6 -- Test flight test hardware (card 8)
This will check the Flight Test card 8 if installed in the FZ.
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APPENDIX C
CARD EDGE ADAPTER TESTS
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APPENDIX C
CARD EDGE ADAPTER TESTS

The diagnostic capability of the STZ--100 is severely limited whenever failures in the UUT result in an
inoperative ASCB since the ASCB is used as the primary communication link with the STZ.
The card edge adapters provide the required diagnostic capability by allowing the operator to exercise a
set of test programs.
These test programs are intended to exercise specific portions of the hardware, provide a standard set of
test signals to points in the UUT circuits, and give a visual indication of fail/pass. In addition, a logic
analyzer interface is provided to allow in depth troubleshooting.
To use these adapters, remove power from the UUT by typing “GOTO POWER” and then “CO”
(continue).
Refer to the User Manual for Card Edge Adapters (EB7010001) contained in, Pub. No. A31--1146--10
(VOL II), for complete instructions on how to perform the individual tests.
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APPENDIX D
FGC INDIVIDUAL CARD DESCRIPTIONS
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APPENDIX D
FGC INDIVIDUAL CARD DESCRIPTIONS

At times, when executing the various tests, failures will occur. In order to troubleshoot the
reason(s) for the failures, a description of the different functions of each card is included in this
section. When a test fails, refer to these card descriptions in order to know which of the cards to
troubleshoot to find the cause of the failure.

CARD FUNCTIONS
A1 Power supply
P.V. circuitry

A2 SVO engage logic


AIL SVO drive & amplifier & engage logic
ELEV SVO drive & amplifier & engage logic
ELEV TRIM SVO amplifier & engage logic
H.B. monitors
CPU valid logic
200 ms timer

A3 B--CPU / ROM / RAM


B--CPU interrupts
A--CPU addr decoding
B--CPU addr decoding
ASCB interface
Bus timer
Pre--bus timer
B--CPU freq division

A4 A--CPU / ROM / RAM


A to B transfer ram
B to A transfer ram
Bus Ram
A--CPU’s ASCB bus controller chip
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CARD FUNCTIONS
A5 A--CPU D/A
A--CPU interrupts
A--CPU addr decoding
B--CPU addr decoding
A--CPU A/D
B--CPU A/D
FGC guidance panel serial output interface
A--CPU serial output ram
A--CPU serial input ram
B--CPU serial input ram
Parallel to serial interface

A6 A--CPU page select logic


A--CPU direct discretes
B--CPU direct discretes
FGC guidance panel serial input interface
Parallel to serial interface
A--CPU 4th page of memory
NVRAM

A7 ELEV TRIM SVO drive


B--CPU D/A
YAW DAMPER SVO drive & amplifier & engage logic
A--CPU analog inputs
B--CPU analog inputs
Misc. unique aircraft I/O functions
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APPENDIX E
ERROR MESSAGES
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APPENDIX E
ERROR MESSAGES

The following is a list of the error messages that the End Item Test return and their meanings:
INVALID CODE
This means that a non--existent test number was requested. The display will return to the menu after
about 1 second.
THE PACKET (DATA) WAS NOT SENT AND, THEREFORE, ‘X’ PROCESSOR TEST ‘Y’ TIMED OUT.
This means that the autopilot did not return any type of handshake to the STZ--100 calling program after
the STZ--100 had made 4 tries to interact with the Autopilot. ‘X’ indicates which processor (A or B), and
‘Y’ indicates which test # was currently being requested.
THE PACKET (DATA) WAS SENT, BUT NO RESPONSE (LOST SYNC) AND ‘X’ PROCESSOR TEST ‘Y’
TIMED OUT.
This means that the autopilot sent back the initial handshake that the information or request was received
but that it never completed the task or made any further response within the allowed 20 seconds. ‘X’
indicates which processor (A or B), and ‘Y’ indicates which test # was currently being requested.
SYNTAX ERROR IN ‘VALUE’ SPECIFICATION
This means that an invalid character was typed instead of the requested number input.
All other error messages indicate a system failure. For reference see the STZ--100 error code listing.
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APPENDIX F
POWER SUPPLY MEASUREMENT INFORMATION
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APPENDIX F
POWER SUPPLY MEASUREMENT INFORMATION
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APPENDIX G
FZ--600/800/820 SOFTWARE POWER--UP
TEST IMPLEMENTATION
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APPENDIX G
FZ--600/800/820 SOFTWARE POWER--UP
TEST IMPLEMENTATION

G1. PURPOSE
The purpose of this Appendix is to provide a detailed description of the FZ--600/800/820 software
power--up test implementation, with specific reference to the hardware tested. It was designed to
be used in conjunction with the data recorded, using the STZ end--item test. Included is a how--to
section useful in sorting out and isolating failures, using recorded fault data.

G2. FZ--600/800/820 POWER--UP TEST DESCRIPTION


Diagnostic and failure flags are generated as a result of performing power--up tests. These tests
are performed automatically whenever power is applied to the FZ. The tests are divided into two
major parts and are shown below in the order in which they are performed.
Non--Real Time Tests
• Strapping logic verification (aircraft configuration)
• Interprocessor communication (transfer status RAM)
• Storage memory (RAM)
• Program memory (ROM)
• Power supply monitor
• Flight director interface tests
• Latched power valid (LPV)
• Hardware interlocks via power monitor resets
• Heartbeat monitor
• Hardware interlocks via heartbeat monitor resets
Interrupt Driven Tests
• Controller interface verification
• A/D calibration verification
• D/A and A/D converter end--around
• Servo switching and control verification
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The non--real time tests are always performed whether on the ground or in the air, whenever a cold
reset occurs (i.e., computer power interrupts greater than 200 ms). In Dash 8, CL601, ATR72,
F900, CIT III, and BAe--900, these cold resets can also be forced by the processors (via monitor
recoveries).
The interrupt driven tests are performed under the following conditions:
• Weight--on--wheels and
• Airspeed is less than 50 kt (80 kt for CL601, GIV, and CIT III) and
• Cross--FZ was powered--up at the same time (synchronized) or not installed
In Dash 8, CIT III and F900, the interrupt driven tests are performed under the following conditions:
• Weight--on--wheels and
• Airspeed is less than 50 kt for Dash 8, less than 80 kt for F900 and CIT III.

G2.1 Program Sequencing and Execution

G2.1.1 Test Sequence

The following list shows the order in which tests are performed during the power--up
(on--ground) sequence. Also shown are all the fault flags which could be set during the
performance of each given test, in addition to the test module that performs the test.

Part 1, or the first 11 tests are done in non--real time. The rest (Part 2) are
interrupt driven.
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PART 1 -- NON--REAL TIME TESTS

-- -- -- -- -- A--Processor -- -- -- -- -- -- -- -- -- -- B--Processor -- -- -- -- --

Module Fault Flag Test Fault Flag Module


MONTSTA MAIN2A,#9 Aircraft Configuration MAIN2B,#2 MONTSTB
PRAMCKA ------------------ Transfer RAM MAIN2B,#7 PRAMCKB
PRAMCKA MAIN2A,#12 RAM MAIN2B,#12 PRAMCKB
CKSUMA MAIN2A,#13 Checksum MAIN2B,#13 CKSUMB
MONTSTA MAIN2A,#10 Over and Under Voltage MAIN2B,#9 MONTSTB
MAIN2B,#10
MONTSTA MAIN2A,#5 Discrete Inhibit Test MAIN2B,#5 MONTSTB
MAIN2A,#7

MAIN2B,#6
MAIN2A,#6
MONTSTA MAIN2A,#14 LPV MAIN2B,#14 MONTSTB
MONTSTA MAIN3A,#15 200 ms Power Down Timer MAIN3B,#15 MONTSTB
MONTSTA MAIN3A,#10 Power Interlocks MAIN3B,#9 MONTSTB
MAIN2A,#10 MAIN2B,#10
MAIN3A,#14 MAIN3B,#14
MAIN2A,#5 MAIN3B,#10
MAIN2A,#7 MAIN2B,#5
MAIN2A,#6 MAIN2B,#6
MONTSTA MAIN3A,#9 Heartbeat Monitor MAIN3B,#8 MONSTB
MAIN3A,#13 Interlocks MAIN3B,#13
MAIN3A,#12 MAIN3B,#12
MAIN3A,#11 MAIN3B,#11
MAIN2A,#5 MAIN3B,#10
MAIN2A,#7 MAIN2B,#5
MAIN2A,#6 MAIN2B,#6

MONTSTA MAIN3A,#7 Test Status MAIN3B,#7 MONTSTB


MAIN3A,#4
MAIN3A,#3
MAIN3A,#2
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

PART 2 -- INTERRUPT DRIVEN TESTS

-- -- -- -- -- A--Processor -- -- -- -- -- -- -- -- -- -- B--Processor -- -- -- -- --

Module Fault Flag Test Fault Flag Module


RETESTA MAIN1A,#12 Servo Power Relay MAIN1B,#4 RETESTB
(Cold Test) MAIN1B,#5
MAIN1B,#15

PFLTTSTA MAIN2A,#8 Serial End--around MAIN2B,#8 PFLTTSTB

PFLTTSTA MAIN2A,#4 A/D Calibration MAIN2B,#4 PFLTTSTB

PFLTTSTA MAIN2A,#3 D/A End--around MAIN2B,#15 PFLTTSTB


MAIN2A,#15
MAIN2A,#2

PFLTTSTA MAIN1A,#7 Shorted Resistor MAIN1B,#7 PFLTTSTB


MAIN1A,#5 MAIN1B,#6
MAIN1A,#6 MAIN1B,#8
MAIN1A,#12 MAIN1B,#9
MAIN1A,#0 MAIN1B,#10
MAIN1A,#5 MAIN1B,#4
MAIN1A,#0 MAIN1B,#5
MAIN1B,#6
MAIN1B,#0
MAIN1B,#1

PFLTTSTA MAIN1A,#6 Servo Engage MAIN1B,#9 PFLTTSTB


MAIN1A,#10 Relay Test MAIN1B,#10
MAIN2A,#0 MAIN1B,#13
MAIN1A,#7 MAIN1B,#7
MAIN2B,#0
MAIN1B,#14
MAIN2B,#1

PFLTTSTA MAIN1A,#15 Servo Amplifier MAIN3B,#0 PFLTTSTB


MAIN3B,#1

PFLTTSTA MAIN1A,#8 Stuck Relay Test MAIN1B,#8 PFLTTSTB


MAIN1A,#2 MAIN1B,#9
MAIN1B,#10
MAIN1B,#2
MAIN1B,#3
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

PART 2 -- INTERRUPT DRIVEN TESTS


-- -- -- -- -- A--Processor -- -- -- -- -- -- -- -- -- -- B--Processor -- -- -- -- --

Module Fault Flag Test Fault Flag Module


-------------------- Linear Actuator MAIN1B,#10 PFLTTSTB
Recentering Test MAIN1B,#3
MAIN3B,#2
MAIN3B,#4
MAIN3B,#3
MAIN3B,#6
MAIN3B,#5

PFLTTSTA MAIN2A,#0 Shorted Diode Test MAIN2B,#0 PFLTTSTB


MAIN2B,#1

RETESTA MAIN3A,#6 Fault Message MAIN2B,#11 RETESTB


MAIN3A,#5 Display MAIN2B,#3

G2.1.2 Relay Tests and Program Timing

Whenever power is applied to an FZ, the noise generated while the relays are exercised forms
a very specific pattern. This pattern differs slightly depending on configuration (single versus
dual) and application.
After power is applied to the FZ, the first cacophony of clicks is generated when the servo
power relay is tested during the overvoltage, undervoltage, power interlocks and heartbeat
reset tests (five clicks). These clicks complete in less than 0.5 seconds. In Dash 8, F900, and
CL601, these tests start 0.9 seconds after power is applied. In CIT, BAe, and ATR, they start
after 2.9 seconds, while GIV begins these tests 10.8 seconds after power is applied.
The sixth click generated is very singular and distinctive. This click is produced 0.4 second
after the initial cacophony, again by the servo power relay, as tested by the modules RETESTA
and RETESTB (cold test).
The next series of clicks begin 3 to 11 seconds later depending on configuration and
application. This marks the start of the servo switching verification, beginning with the shorted
resistor test. Depending on the program, this can either last 2 or 7 seconds. The test start
time and its length are shown below.

In dual configurations, the servo tests begin with the pilot’s FZ, followed by the
copilot’s.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Dash 8 and CL601


• Single pilot -- servo tests start after 3 seconds and last 7 seconds
• Single copilot -- servo tests start after 11 seconds and last 7 seconds
• Dual -- servo tests start after 3 seconds, completing 20 seconds later
BAe, CIT, F900 and GIV
• Single pilot -- servo tests start after 6 seconds and last 2 seconds
• Single copilot -- servo tests start after 13 seconds and last 2 seconds
• Dual -- servo tests start after 3 seconds completing 4 seconds later
ATR
• Servo tests starting after 2 seconds, completing 2 seconds later
The final pattern of clicks is generated when the Avionics Standard Communication Bus
(ASCB) tests are performed. These ASCB controller tests last about 10 seconds, and are
performed only when configured dual.

G3. FAILURE DATA ANALYSIS


There is no cookbook procedure to follow when it comes to isolating failures. To successfully
troubleshoot a problem requires knowledge of the circuit design and its intended function,
experience, and sometimes luck.
Using the Power--up Test to Isolate Failures
Unfortunately, the power--up test was designed to only detect functional failures. It was not
designed to isolate or troubleshoot. Troubleshooting using only the fault data is not straight
forward. Single point failures could trigger the setting of a multitude of fault flags. When analyzing
data, you must keep two thoughts in--mind:
(1) what actually failed, and (2) how accurate is the data.
G3.1 What Actually Failed
Look through all the fault flags that are set. This will give you a general idea of the hardware
functions that are failing. Now, compare the detected faults with the order in which they are
tested in paragraph 2.1. If there are a lot of flags set, split them into two groups, non--real time
tests and interrupt driven tests. What you want to zero in on is the first detected failure. Since
the non--real time tests are done first, this would be your starting point. Concentrate on fixing
these tests first.
Read the description of what the software is doing to test this function. This will tell you which
inputs are measured or initialized (see paragraph G3.1.3), and its pass/fail criteria. It will also
tell you what other status flags are stored, which could help zero in on the specific signal at
fault.
Remember, when testing the hardware, the circuits controlling any given function may be
spread out between several cards. The actual fault could lie on any one of these cards.
As an example, here are the actual fault codes of a failure detected in Citation software:
MAIN1A: 1000 MAIN1B: 0000
MAIN2A: 0000 MAIN2B: 0020
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

MAIN3A: 0000 MAIN3B: 1800


Running through the list of failures shows that:
A--Processor B--Processor
Servo Power Relay Fail Processor Valid Failure
Heartbeat Monitor (HBM) Fail (Long)
HBM Reset Interlocks Fail

Separate the faults in the order that they are performed. One quick way of doing this is to
separate them into two groups, non--real time and interrupt driven tests. All non--real time
tests are done before the interrupt driven ones.
Returning to our example, the A--processor servo power relay test is done after the three
B--processor tests have completed, so we will concentrate on the latter. After correcting
these, the A--processor servo power relay failure may disappear.
Using the failure titles alone, you can tell that the fault has something to do with the heartbeat
monitor in the B--processor. Next, carefully read through the test description for each one of
these failures. Cross reference the description with its associated functional hardware
schematic (see Figure 7).
In our example, the processor valid failed. From its test description, this fault flag can be set
after any one of three tests: the inhibit test, the power reset test, and/or the heartbeat monitor
test.
Again, there is something having to do with the heartbeat.
Reading on, the heartbeat monitor itself failed long. It did not reset within 100 ms. The
heartbeat interlocks test also failed. Processor valid is part of this interlocks test, the
interlocks test is part of the heartbeat test. It all ties together. The software was expecting
processor valid to transition as part of its HBM interlocks test, but since the HBM did not reset,
processor valid could not transition causing the HBM interlocks test to also fail. With a little
reasoning, we’ve concluded the actual cause of the failure was not processor valid, but lack of
a HBM reset.
Tracking the hardware malfunction is the next step. The heartbeat monitor itself is located on
the A2 ECA (only the one--shot is tested, not the monostable). It is possible that the heartbeat
monitor is generating the reset pulse, but the CPU is not receiving it. If this is so, the fault
would be on the A3 ECA. It’s also possible that the monitor is not generating its output
because of excessive reset pulses. Then the problem would be on the A6 ECA. There is
always the possibility these signals are being corrupted because of opens/shorts in the
motherboard.
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Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

G3.2 How Accurate is the Data

When reading through the list of failures, you have to ask yourself, how accurate is this data?
Obviously, you know that a fault has been detected, because flags were latched, but how
much can you really trust the data?
The only reason for feeling the data is suspect is that you are relying on the box to tell you
what it thinks is wrong with itself. This is the job of self--test, but self--test has its own inherent
limitations. It assumes that a certain core of hardware is operational, as it must be, before
valid data can be reported. For example, the write enable line to one 6116L RAM chip failing
active will prevent the processor from storing data. The FZ will undoubtedly fail. You know
that it fails (it doesn’t sound right, see paragraph 2.1.2), the FZ knows that it failed, but either it
cannot reliably tell you about it, or it can’t execute enough of its program to tell you about it.
Either way, the data is garbage, and cannot be trusted.
Correlating redundant data between the two processors can help. Unfortunately, not all tests
are done by both processors. For the tests that are done by both processors, be sure to check
the corresponding fault flag in the cross processor. It will help lead you to the actual cause.
For example, MAIN2A=0200, or bit 9=1=Aircraft Configuration Pin fail. Did the corresponding
test in the B--processor fail? If it did not, the fault lies within the FZ, probably on the A5 ECA.
Also keep in mind that all Part 2 tests are interrupt driven. During this phase, the power--up
test is essentially running in background. The only function running in foreground is the
Input/Output software, the
most essential being the ASCB software. Errors detected by the ASCB software monitors will
cause a wide variety of error symptoms, from faults latched only in the B--processor’s first
interrupt driven test (MAIN1B, 4, 5 or 15), to complete FZ latch--ups.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Tests Performed By Both Processors


Test A--Processor Fault Flags B--Processor Fault Flags

Aircraft Configuration MAIN2A,#9 MAIN2B,#2

FD/Annunciator Valid MAIN2A,#5 MAIN2B,#10

Power Monitor Test MAIN2A,#10 MAIN2B,#9


MAIN2B,#10

Latched Power Valid MAIN2A,#15 MAIN2A,#14

Servo Power Pre-- MAIN1A,#12 MAIN1B,#15


engage Conditions

Servo Power Relay MAIN1A,#12 MAIN1B,#5


MAIN1B,#4

High Trim Rate MAIN1A,#14 MAIN1B,#12


Command End--around

A/D Calibration* MAIN2A,#4 MAIN2B,#15

*Although the A/D hardware is unique between processors, some signals that are converted are the
same. If this test fails in both processors, the common signals could be the fault.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

G3.3 Signal Names

The signal name referenced in each test description is the actual software label assigned for
that particular signal. The labels represent either a signal which is directly accessed (e.g.,
memory mapped I/O address) or a software filtered signal. Typically, the non--real time tests
use the directly accessible input signal, while the interrupt driven tests use the software filtered
signals. For example, the ASCB drivers test uses two directly accessible discretes. These
are the driver enable wraparound feedbacks (ABUSENWA--F91C, BBUSENWA--F91E). In all
cases where directly accessible discretes are used, the corresponding memory mapped
addresses are specified. In the servo power relays test, prior to testing the servo power
relays, AP servo power is examined. The software filtered, or debounced signal (APPWRFB)
is used. Note that the memory mapped addresses of filtered discretes are not specified
because the addresses can change from one software version to another. A description of
these filtered signals is contained in paragraph 8.

G4. A--PROCESSOR FAILURE FLAG DESCRIPTIONS

G4.1 MAIN1A
MAIN1A -- Bit 15 -- Elevator Trim Servo Amplifier Fail

The elevator trim servo amplifier is verified at the same time the B--CPU verifies the aileron and
elevator servo amplifiers. This test is performed by AMPTSTA in module PFLTTSTA and is
interrupt driven. This test is done only on the ground.

Software Description -- Dash 8, F900, GIV, and ATR

1. Verify that the elevator trim relay is engaged (ELTRELAY=1).


2. Command elevator trim up (ELTUP--F940=1).
3. Enable trim servo amp (ELTDRIV--F932=1).
4. Initialize the trim servo amp fail flag to fail.
5. Wait 200 ms. During this time, verify that the servo voltage feedback (ELTRIMV--F82E)
exceeds 10 volts. If it reaches this threshold, clear the trim up command and the failure flag.
The hardware tested is shown in Figure 1.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Figure 1. Elevator Trim Servo Amplifier Test,


Dash 8, F--900, GIV, and ATR

Software Description -- CIT III, BAe--800, CL601

1. Verify that the elevator trim relay is engaged (ELTRELAY=1).

2. Command elevator trim up (ELTUP--F940=1).

3. Enable trim servo amplifier (and elevator trim valid for CL only; (ELTDRIV--F932=1).

4. Initialize the elevator trim servo amplifier fail flag to fail.

5. Wait 200 ms. During this period, verify that the elev trim up command feedback
(ELTUPFB=1) is set. If it does, clear the failure flag.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

The hardware tested is shown in Figure 2.

Figure 2. Elevator Trim Servo Amplifier Test,


CIT III, BAe--800, CL601

• MAIN1A -- Bit 14 -- High Trim Rate Command End--around Fail

This applies to CL601 only.

The elevator high trim rate command requires synchronization with the B--CPU, and is
verified during the relay engage tests (ENGTSTA) called by module PFLTTSTA. This is an
interrupt driven test done only on the ground.

Software Description

1. Command and verify that the servo power relay is engaged.

2. Set the high trim rate command (ELTHRATE--F93A=1).

3. Set the trim driver enable (ELTDRIV--F932=1).

4. Wait 200 ms.


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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

5. Verify that the high trim rate feedback (QELTHRFB--F444=1) is set. If not, set the
failure flag.

6. Clear both discrete outputs.

• MAIN1A -- Bit 13 -- Elevator Trim Quick Disconnect Fail


This fault flag is applicable only to Dash 8.
Prior to running any of the relay tests, the state of the elevator trim quick disconnect
(TRMDISC1=1) is verified to be not pushed. If it indicates “pushed” this failure flag is set.
• MAIN1A -- Bit 12 -- AP or YD Servo Power Relay Fail
The AP and YD servo power relays are engaged and disengaged several times during the
power--up test. The modules RETESTA and PFLTTSTA perform the tests shown below.
The RETESTA tests are done after any cold start. PFLTTSTA tests are done only on the
ground. Both are interrupt driven. Both tests are performed by each processor (see
MAIN1B -- bits 15, 5, and 4). See Figure 3, for a description of the hardware tested.
Software Description -- RETESTA (Submodule COLDTST)

1. Delay 150 ms.

2. Verify that AP servo power is present (APPWRFB=1). If not, set bit in STATWDA (see
Miscellaneous, paragraph 4.4) and return.

3. .Verify that YD servo power is present (YDPWRFB=1). If not, set bit in STATWDA
(see Miscellaneous, paragraph 4.4) and return.

4. Verify that the AP servo power relay is open by reading AP Power off feedback
discrete (APPWROFB=1). If not, set this failure flag.

5. Verify that the YD servo power relay is open by reading YD power off feedback
discrete (YDPWROFB=1). If not, set this failure flag.

6. .Verify that the servos off feedback discrete is set (SRVOFFB=1). If not, set this
failure flag.

7. Enable the servo power relay by setting the servo power relay engage command
(APWREN--F94C=1).

8. Verify that the relay closes within 300 ms by confirming that the following feedback
discretes are clear:

• AP power off feedback (APPWROFB=0)


• YD power off feedback (YDPWROFB=0)
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

9. If the emergency quick disconnect is active (EMERGD1=0), then bypass setting this
failure flag. If inactive (=1), set this flag.

This emergency disconnect bypass is used only for this test.

• PFLTTSTA (Submodule RESTST)

1. With the servo power relay engaged, the relay is commanded to open
(APWREN--F94C=0).

2. Verify that the relay opens by monitoring AP power off feedback (APPWROFB=1).
This must transition low within 225 ms. If not, set this failure flag.

Figure 3. Servo Power Relay Tests


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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN1A -- Bit 11 -- Elevator Trim Rate Relay Fail

This test is applicable only to CL601.

The elevator trim rate relay is tested only by the A--CPU. This is done in the relay test
(ENGTSTA) by module PFLTTSTA. This is an interrupt driven test done only on the
ground.
Software Description

1. With the elev trim relay verified to be open, the elev trim rate relay is verified to be
open (TRATERFB=1). If not, set the fail flag.

2. The elev trim relay is commanded and verified to be engaged. If not, set MAIN1A -- bit
10 and bypass the remainder of this test.

3. The elev trim rate relay is verified to be closed (TRATERFB). If not, set the failure
flag.

• MAIN1A -- Bit 10 -- Elevator Trim Engage Test Fail


The elev trim relay is tested at the same time the B--CPU tests the AP and YD clutch relays.
This is done in the engage test (ENGTSTA) called from PFLTTSTA. This is an interrupt
driven test performed only on the ground. Figure 1 shows the hardware tested.
Software Description

1. The servo power relay is enabled and verified to be engaged (see MAIN1A -- bit 12).

2. Verify that the conditions are valid for relay engagement (see MAIN1A -- bit 6).

3. Command the elev trim relay to engage (ELTENCMD--F930=1).

4. Verify that the relay engages (ELTRELAY=1) within 225 ms. If not, set the failure flag.

• MAIN1A -- Bit 9 -- Spare


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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN1A -- Bit 8 -- Elevator Trim Pre--Drive Test Conditions Fail

Prior to testing for stuck closed relays (RLYTSTA), the elev trim pre--drive conditions are
validated. This routine is called within PFLTTSTA and is performed at the same time that
the B--CPU tests for stuck relays. This is an interrupt driven test done only on the ground.
Software Description

1. Verify that the trim clutch relay is not closed (ELTRELAY=0).

2. Verify that the AP servo power relay is not open (APPWROFB=0).

3. Verify that the trim quick disconnect switch is not pushed (TRMDISC1=1).

4. Verify that no X--FZ servos are engaged (XSRVOFF=0). If cross servos are engaged,
verify that it is because either the X--YD brake is engaged or X--Mach trim is selected.
If X--FZ servos are engaged and X--AP servo power (XAPPWR=0) or X--YD servo
power (XYDPWR=0) is not present, disregard the state of X--FZ servos.

5. If any of the above conditions are not met, this failure flag is set. The condition that
caused the failure is not latched.

• MAIN1A -- Bit 7 -- Servos Off ‘AND’ Gate Fail

The servos off AND gate is tested in both the shorted resistor test (RESTST) and in the
relay engage test (ENGTST) which are both called by PFLTTSTA. This discrete is tested
by both processors under the same conditions (see MAIN1B -- bit 7). This is an interrupt
driven test done only on the ground. See Figure 1.
Software Description -- RESTST

1. All servo clutch relays are disengaged, and the servo power relay is engaged.

2. The servos off AND gate feedback is verified to be set (SRVOFFB=1). If not, this
failure flag is set.

ENGTST

1. The elev trim relay is verified to be engaged (see MAIN1A -- bit 10). If it is not
engaged, the servos off AND gate is not tested.

2. The servos off AND gate feedback discrete is verified to be low (SRVOFFB=0). If it is
not, the failure flag is set.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN1A -- Bit 6 -- Elevator Trim Pre--Engage Conditions Fail

This failure flag can be set in one of two places: prior to running the relay engage test
(ENGTST) and prior to running the shorted resistor test (RESTST). This flag is set only if
the conditions for running these tests are not valid. The conditions are examined using a
subroutine (ELTSTAT). This test is called by PFLTTSTA, is interrupt driven, and is done
only on the ground.
Software Description

1. Verify that the trim clutch relay is not closed (ELTRELAY=0).

2. Verify that the AP servo power relay is not open (APPWROFB=0).

3. Verify that the trim quick disconnect switch is not pushed (TRMDISC1=1).

4. Verify that no X--FZ servos are engaged (XSRVOFF=0). If cross servos are engaged,
verify that it is because either the X--YD brake is engaged or X--Mach trim is selected.
If X--FZ servos are engaged and X--AP servo power (XAPPWR=0) or X--YD servo
power (XYDPWR=0) is not present, disregard the state of X--FZ servos.

5. In GIV only, the elev trim brake (ELTBRKFB=0) is verified to be open.

6. If any of the above conditions are invalid, the failure flag will be set. The condition
causing the failure will not be latched.

• MAIN1A -- Bit 5 -- Servo Power Off ‘OR’ Gate Fail

The servo power off OR gate is tested when the servo power relay is engaged and when it
is disengaged. This is done in the shorted resistor test (RESTST) called from the module
PFLTTSTA. This is an interrupts driven test done only on the ground. See Figure 3.
Software Description

1. With the servo power relay engaged, the servo power off OR gate (SRVPOFFB=0) is
verified to be cleared after a 400 ms discretes settling delay. If not, this failure flag is
set.

2. The servo power enable is cleared, and the servo power relay is verified to open (see
MAIN1A -- bit #12).

3. After this relay is verified to be open, the servo power off OR gate is validated to be
high. If it is not, this failure flag is set.

• MAIN1A -- Bit 4 -- Spare


• MAIN1A -- Bit 3 -- Elevator Trim Brake Fail
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

This test is performed only in GIV. It is done as part of the engage tests (ENGTST) called from
PFLTTSTA. This is an interrupt driven test done only on the ground.
Software Description
− After the elev trim relay (see MAIN1A -- bit 10) and the elev trim clutch (see MAIN2A -- bit 0)
are verified to be engaged, the elevator trim brake (ELTBRKFB=1) is examined. If it is not
high, this failure flag is set.
• MAIN1A -- Bit 2 -- Elevator Trim Servo Engage Relay Fail
This test verifies that the elev trim servo engage relay is not stuck closed (see Figure 1).
This test (RLYTST) is called from PFLTTSTA. It is an interrupt driven test executed only on
the ground.
Software Description

1. Conditions for enabling the driver are first verified (elev trim relay not engaged, servo
power relay engaged, see MAIN1A -- bit 8).

2. The trim up command is cleared, followed by a 500 ms delay.

3. The servo amp is initialized with a full--scale up command, and its driver enabled.

4. The elev trim servo motor feedback (ELTRIMV--F82E) is monitored for 200 ms. If the
voltage exceeds 10V within this period, the command is immediately cleared and the
failure flag set.

5. The drive enable is cleared.

• MAIN1A -- Bit 1 -- Spare


• MAIN1A -- Bit 0 -- Elevator Trim Pull--up Resistor Fail

This test is done by the submodule RESTST called from PFLTTSTA. This is an interrupts driven
test done only on the ground. See Figure 1.
Software Description
− With the servo power relay open, the elev trim clutch relay is commanded to engage
(ELTENCMD--F930=1). After a 225 ms delay, the relay is examined. If it closed
(ELTRELAY=1), which means that power is being applied to the relay, possibly through a
shorted pull--up resistor, the fail flag is set.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

G4.2 MAIN2A
MAIN2A -- Bit 15 -- D/A End--around Fail
The A/D converter is exercised through its complete operational conversion range via
end--around, using the D/A converter. Control of all data conversions is done by the real--time
process. Output command and end--around verification is performed by submodule IOWRAP
called by PFLTTSTA.
The software control flow is described below.

1. The flight director annunciator valid is initialized valid (FDANNVAL--F95C=1).

2. In Dash 8 and ATR, the pitch and roll bias--out--of--view command is verified (see MAIN2A,
bit 3). Any detected failures cause additional end--around testing to be aborted.

3. The pitch and roll flight director commands are both initialized with the first entry as shown
in Table 1.

4. The test waits 225 ms for the conversion to complete.

5. The feedbacks (DAFBP--F836 and DAFBR--F83E) are compared with their corresponding
inverted command, and verified against the tolerances shown below:

GIV, ATR 42, ATR 72, BAe--800 -- Conversion tolerance: ±156 mV


All others -- Conversion tolerance: ±300 mV
NOTE: FDWAERR is defined in module PUCONA.

6. If no failures are detected, the Flight director output command is verified. Its expected
nominal for each given output command is show in Table 1. The tolerance applied to the
FD output (PWAERROR) is shown below. Failures of this end--around will be latched in
MAIN2A -- bit 2.

ATR 42, ATR 72 -- Conversion tolerance: ±240 mV


Dash 8 -- Conversion tolerance: ±300 mV

PWAERROR is defined in module PUCONA.


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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Table 1. D/A End--around Test Commands -- A--Processor

COMMAND VOLTAGE FD NOM FB


8CCD --9.00 --2.25
C000 --5.00 --1.25
E000 --2.50 --0.63
F000 --1.25 --0.31
F800 --0.63 --0.16
FC00 --0.31 --0.08
FE00 --0.16 --0.04
0000 0.0 0.0
0200 +0.16 +0.04
0400 +0.31 +0.08
0800 +0.63 +0.16
1000 +1.25 +0.31
2000 +2.50 +0.63
4000 +5.00 +1.25
7330 +9.00 +2.25

• MAIN2A -- Bit 14 -- Latched Power Valid Fail

This failure flag is initialized by the module MONTSTA prior to waiting for latched power
valid (LPV--F910) to transition from invalid to valid (1 -->0). The software is configured as
an infinite loop waiting for LPV to transition (LPV reset is controlled by the B--processor). If
it does not correctly transition (A2 ECA), or if its direct discrete feedback processing fails
(A6 ECA), the software will remain in this loop (see MAIN2B -- bit 14).
• MAIN2A -- Bit 13 -- Memory Checksum Fail

The module CKSUMA, called by MONTSTA, sums the data at every address on every page
of ROM memory. The data is summed as long words, or 32 bits. The test is considered to
pass if the 32 bit sumcheck, for all of memory, equals zero. This is a non--real time test.

This test is performed a second time if it fails the first time.

One of the last steps in the software verification process, (prior to certification) is to patch
or imbed a 32--bit calculated constant in each page of memory. This patched constant
allows each page, when summed, to equal zero.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN2A -- Bit 12 -- RAM Fail

The module PRAMCKA, called by MONTSTA, exercises each RAM address between
C000--F000. This non--real time test is configured in two parts, (1) address/data bus test
(ADDRTST) and (2) write/read test (PRAM). The first test will verify that no two address or
data lines are shorted together, the second will verify that each cell will toggle. This test is
performed after any cold start.
Software Description -- Address/Data Bus Test

1. The starting address of RAM is initialized in a software loop that:

a. Saves the data contained in the 16 bit cell to be tested.

b. Writes a unique word into the test cell, the unique word being the test address.

c. Updates the next address of the next cell to be tested, finally looping back to step
a. The address and data written are shown in Table 2.

2. After all writes have been completed, another loop is executed. This loop:

a. Reads the data at each test cell and verifies that the data read was what was
written.

b. Replaces the original contents.

c. Sets a temporary fault flag if mismatches are detected.

3. If any failures were detected, the entire test is performed once more. Detected failures
will set this fault flag.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Table 2. RAM Address/Data Bus Test

Address Data Write


C000 C000
C002 C002
C004 C004
C008 C008
C010 C010
C020 C020
C040 C040
C080 C080
C100 C100
C200 C200
C400 C400
C800 C800
D000 D000
E000 E000

Write/Read Test
This test subdivides RAM into a series of 400H word blocks. A detected failure will set a bit in a
word (RAMFLG). This bit corresponds to its 400H word block of addresses, indicating that
Table 3.

1. Initialize starting RAM address.

2. Initialize the test pattern to ‘5555’.

3. Initialize block counters.


a. Store the original contents of test cell.
b. Write pattern into test cell.
c. Read the data from the test cell and compare with the written pattern.
d. If a fault is detected, redo steps b and c. If faults are again detected, latch failure flags.
e. Complement the test pattern (AAAA).
f. Execute steps b through d.
g. Restore the original test cell contents.
h. Continue until all of RAM is tested.
i. Set this failure flag if RAMFLG bits 0--11 are not all zero.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Table 3. RAM Write/Read Failure Locations

RAMFLG Address range


bit 15 Spare
bit 14 Spare
bit 13 Spare
bit 12 Spare
bit 11 EC00H--EFFEH
bit 10 E800H--EBFEH
bit 9 E400H--E7FEH
bit 8 E000H--E3FEH
bit 7 DC00H--DFFEH
bit 6 D800H--DBFEH
bit 5 D400H--D7FEH
bit 4 D000H--D3FEH
bit 3 C000H--CFFEH
bit 2 C800H--CBFEH
bit 1 C400H--C7FEH
bit 0 C000H--C3FEH

• MAIN2A -- Bit 11 -- Spare


• MAIN2A -- Bit 10 -- Power Supply Monitor Reset Fail

The B--processor simulates an over-- and under--voltage condition (see MAIN2B -- bits 10
and 9) in order to verify operation of the power supply monitors. A trip in either monitor will
cause both processors to be reset. This flag indicates that the A--CPU was not reset with
each B--CPU simulated failure (this flag can also be set during PWRLOCKA test; see
MAIN3A -- bit 14).

This test is performed by MONTSTA. It is done in non--real time after any cold start. See
Figure 4.
• MAIN2A -- Bit 9 -- Aircraft Configuration Pin Fail

This fault flag is set if the aircraft configuration or strapping pins do not agree with the
aircraft ID stored in ROM. This verification is executed in non--real time by MONTSTA after
any cold start. The ground/open discretes used to determine these configurations are as
follows:
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

MNEMONIC No. ADDRESS PINOUT


QACID6 ID6 F44A J1B--81
QACID5 ID5 F46C J1B--80
QACID4 ID4 F46A J1B--79
QACID3 ID3 F468 J1B--78
QACID2 ID2 F466 J1B--77
QACID1 ID1 F464 J1B--76

The software verifies this configuration only once.

1. It does so by:
-- loading QACID6 into a register.
-- rotating left the register into carry.
-- rotating carry into another register.
-- repeating for the other discretes.
2. The final register contains the state of the packed discretes, where QACID6 is represented
by bit 5, and QACID1 by bit 0.

3. This packed register is compared against the software constant ACFTID (defined in
PUCONA).

• MAIN2A -- Bit 8 -- Serial End--Around Fail

The real--time I/O processing is used by this test to control serial data to and from the
guidance controller. In this test, only one bit is available to verify this interface: the output,
SOWRAP, and its corresponding input, SOWRAPFB. This real--time test is done only on
the ground.
Software Description

1. Set the serial test discrete (SOWRAP--F7D0=1).

2. Enable the flight director annunciator valid (FDANNVAL--F95C=1).

3. Delay 100 ms (four transfers).

4. Verify that the serial test discrete feedback is set (SOWRAPFB=1).

5. Clear the serial test discrete (SOWRAP--F7D0=0).

6. Delay 100 ms (four transfers).

7. Verify that the serial test discrete feedback is clear (SOWRAPFB=0).

8. Set the serial test discrete (SOWRAP--F7D0=1).


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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

9. Disable the flight director annunciator valid (FDANNVAL--F95C=0).

10. Delay 100 ms (four transfers).

11. Verify that the serial test discrete feedback is clear (SOWRAPFB).

12. Clear all discrete outputs.

• MAIN2A -- Bit 7 -- Bus Enable Inhibit Fail

This test is performed in all programs except GIV (which has version B ASCB in which the
FZ is user only, not controller). In these programs, both ASCB bus drivers are tested,
except in ATR 42 and 72, which use only one bus driver.

This non--real time test verifies the operation of the drivers in three submodules called from
MONTSTA. This test is performed after every cold start. See Figure 4.
Software Description -- Inhibit Test (called by DSCTST)
NOTE: LPV is invalid (MSB=1).

1. Clear all serialized discrete outputs (F600--F7FE).

2. Synchronize the two processors.

3. Enable the ASCB driver (BUSEN--F95C=1).

4. Wait 24 ms.

5. Update the serial strobe (SERSTRB--F98C) and wait until completed


(SERINPRG--F920=0).

6. Verify that both drivers remain disabled (ABUSENWA--F91C, BBUSENWA--F91E)


(MSB=1=disabled).
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Power Reset Tests (PWRLOCKA)

NOTE: These tests are done only if the power reset tests passed (e.g. MAIN2A -- bit
10≠1), after LPV has been set valid (MSB=0).

1. Synchronize the A and B--CPUs.

2. Enable the ASCB bus driver (BUSEN--F95C=1).

3. Delay 8 us.

4. Verify that both driver feedbacks are enabled (see MAIN3A,


-- bit 10) (MSB=0=enabled). If not, set this failure flag (isolated by subroutine INTFAIL).

5. Sync the CPUs and wait up to 1 ms for the reset to occur. If no reset occurs, set
MAIN2A -- bit 10.

6. Verify that the drivers are disabled after the reset has occurred (isolated by subroutine
INTFAIL). See MAIN3A -- bit 14.

Heartbeat Reset Test (HBMLOCKA)

1. Prior to testing the Heartbeat monitors, ABUSENWA and BBUSENWA are both verified to
be disabled (MSB=0). This is isolated by the subroutine INTFAIL (see MAIN3A -- bit 9).

2. Upon completion of the HB test, the ASCB driver is enabled. Since the HBM will remain
invalid until it is reset, the driver is verified to remain disabled. This check is done by
MONTSTA.

NOTE: There is no direct test to verify that an HBM trip will invalidate the ASCB driver
enable. It is done this way because, when the ASCB drivers are enabled, they
transmit. Since the Z8030 is not enabled, only noise is transmitted, possibly
blinding the bus. Due to the length of time needed to run the HBM test, the
duration that noise is transmitted becomes excessive (two or more frames).
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Figure 4. Bus Driver Interface Test


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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN2A -- Bit 6 -- Servo Power Enable Fail

This non--real time test verifies operation of the servo power enable commands based on
operation of the servo power relays. These enable commands are tested as processor
pairs and verified in three ways: while LPV is invalid, after power resets, and after heartbeat
monitor trips. This test is done after every cold start. See Figure 5.
Software Description -- Inhibit Test (called by DSCTST)

NOTE: LPV is invalid (MSB=1).

1. Clear all serialized discrete outputs (F600--F7FE).

2. Synchronize the two processors.

3. Command the servo power enable (APWREN--F94C=1).

4. Wait 24 ms.

5. Update the serial strobe (SERSTRB--F98C) and wait until completed


(SERINPRG--F920=0).

6. If AP and YD servo power are present (QAPPWRFB--F400, QYDPWRB--F414=1), then


verify that the AP and YD servo power relays (QAPPWROF--F402, QYDPWROF--F416)
remain disabled. The logic is as follows:

If QAPPWRFB=QYDPWRFB=1, then
QAPPWROF=QYDPWROF must =1

7. If this test fails, perform the test one more time.


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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Power Reset Tests (PWRLOCKA)

NOTE: These tests are done only if the power reset tests passed (e.g. MAIN2A -- bit
10≠1), after LPV has been set valid (MSB=0).

1. Synchronize the A and B processors.

2. Command the servo power enable (APWREN--F94C=1) (done in subroutine INTLOCKA).

3. Update serialized data 10 times, waiting 1 ms prior to each update request. Verify that the
update completes prior to each request (about 20 ms total).

4. Verify that the servo power relays are not open (QAPPWROF=QYDPWROF=0). If open,
set this failure flag (isolated by subroutine INTFAIL). See MAIN3A -- bit 10.

5. Sync the CPUs and wait up to 1 ms for a reset (triggered by the B--processor) to occur. If
no reset occurs, set MAIN2A -- bit 10.

6. Reset processing delays 8 ms prior to updating the serialized data 10 times, while waiting
1.5 ms between each request, providing a total of over 23 ms from the power monitor reset.

7. Verify that the relays are open after the reset has occurred (isolated by subroutine
INTFAIL). See MAIN3A -- bit 14.

Heartbeat Reset Test (HBMLOCKA)

1. The A-- and B--CPUs are synchronized.

2. The servo engage relays are commanded and verified to engage (done by submodule
INTLOCKA). Failure isolation is done by the subroutine INTFAIL (see MAIN3A -- bit 9).

3. The HB monitor is allowed to trip, causing a reset.

4. Reset processing delays 8 ms prior to updating the serialized data 10 times, while waiting
1.5 ms between each request providing a total of over 23 ms from the HBM reset.

5. Verify that the relays are open after the reset has occurred (isolated by subroutine
INTFAIL). See MAIN3A -- bit 13.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Figure 5. Servo Power Relay Interlocks Test


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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN2A -- Bit 5 -- FD/Annunciator Valid Fail

This non--real time test verifies operation of the flight director/annunciator valid based on
the end--around signal through the Guidance Controller. The valid is tested after all cold
starts, in three ways; while LPV is invalid, after power resets, and after heartbeat monitor
trips. See Figure 6.
Software Description -- Inhibit Test (called by DSCTST)

NOTE: LPV is invalid (MSB=1).

1. Clear all serialized discrete outputs (F600--F7FE).

2. Synchronize the two processors.

3. Set the FD/annunciator valid (FDANNVAL--F95C=1).

4. Wait 24 ms.

5. Update the serial strobe (SERSTRB--F98C) and wait until completed


(SERINPRG--F920=0).

6. Verify that the annunciator valid feedback (QANNUNFB--F508=0) remains low. If not, set
this failure flag.

Power Reset Tests (PWRLOCKA)

NOTE: These tests are done only if the power reset tests passed (e.g. MAIN2A -- bit
10≠1), after LPV has been set valid (MSB=0).

1. Synchronize the A and B--CPUs.

2. Set the FD/annunciator valid (FDANNVAL--F95C=1).

3. Update serialized data 10 times, waiting 1 ms prior to each update request. Verify that the
update completes prior to each request (about 20 ms total).

4. Verify that the annunciator valid feedback is valid (QANNUNFB--F508=1). If not, set this
failure flag (isolated by subroutine INTFAIL). See MAIN3A -- bit 10.

5. Sync the CPUs and wait up to 1 ms for the B--processor to generate a reset. If no reset
occurs, set MAIN2A -- bit 10.

7. Reset processing delays 8 ms prior to updating the serialized data 10 times, while waiting
1.5 ms between each request, providing a total of over 23 ms from the power monitor reset.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

8. Verify that the feedback is low (QANNUNFB--F508=0) (isolated by subroutine INTFAIL).


See MAIN3A -- bit 14.
Heartbeat Reset Test (HBMLOCKA)
1. The A and B--CPUs are synchronized.

2. The FD/annunciator valid is set and verified (done by submodule INTLOCKA). Failure
isolation is done by the subroutine INTFAIL (see MAIN3A -- bit 9).

3. The HB monitor is allowed to trip, causing a reset.

4. Reset processing delays 8 ms prior to updating the serialized data 10 times, while waiting
1.5 ms between each request, providing a total of over 23 ms from the HBM reset.

5. The feedback is verified to be low (isolated by subroutine INTFAIL). See MAIN3A -- bit 13.

Figure 6. FD/Annunciator Interface Test


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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN2A -- Bit 4 -- A/D Calibration Fail

The real--time I/O processing is used by this test to control analog signal conversions. This
test is designed to detect gross failures in the conversion process. It is done by the
submodule ADCAL called from PFLTTSTA. The A/D calibration test verifies conversion of
specific references, using the tolerances shown in Table 4. This is an on--ground test.

Table 4. A/D Calibration Test -- A--Processor

Voltage
Signal Nominal Tolerance
Ground (SIGGND--F838) 0V ±100 mV (SIGGNDER) (3)
±300 mV (4)
+10V (REF10VB--F80C) +7.5 V ±100 mV (REF10VER) (3)
±200 mV (4)
--15V (NEG15V--F802) --6.65 V (1) ±1 V (NEG15VER)
--6.9 V (2)
+5Viso (ISO5V--F81C) +5v ±500 mV (ISO5VER)
NOTES: (1) Applies to D8--300, D8--100, GIV, F900, CL601.
(2) Applies to CIT III, ATR42, ATR72, BAe--800, BAe--900.
(3) Applies to GIV, ATR42, BAe--800.
(4) Applies to D8--300, D8--100, F900, CL601, BAe--900, ATR72.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN2A -- Bit 3 -- FD Bar Bias Fail

The Flight Director command bars bias out--of--view voltage is verified prior to running the
A/D end--around test (see MAIN2A -- bit 15). It is done by the same calling routines. This
test is applicable to only Dash 8 and ATR for all installations (analog or EFIS). The levels
and tolerances used are shown below:

Tolerance
ATR 42/72 >7.5 volts
Dash 8 >7.0 volts

Software Description

1. After an on--ground cold start, the FD annunciator valid in enabled (FDANNVAL--F95C=1).

2. The pitch (FDFBP--F83C) and roll (FDFBPR--F83A) FD feedbacks are verified against their
minimum limits.

3. The pitch (PITBAR--F952) and roll bar (ROLLBAR--F954) bias is removed (bit 15=1), and
the pitch (FDCMDP--F900) and roll (FDCMDR--F902) flight director commands zeroed.

4. After a 225 ms delay, the pitch and roll FD feedbacks are verified to be zero.

• MAIN2A -- Bit 2 -- FD Amplifier Fail

The flight director pitch and roll bar drive amplifiers are verified for proper operation. This
test is performed in ATR and Dash 8. It is performed regardless of instrumentation (analog
or EFIS). See MAIN2A -- bit 15 for a complete description.
• MAIN2A -- Bit 1 -- Spare
• MAIN2A -- Bit 0 -- Elevator TrimClutch Isolation Diode Fail

The Elevator trim clutch isolation diode is tested for both opens and shorts. This diode is
verified for opens during the relay engage test (see MAIN1A -- bit 10). When the elev trim
relay is verified to be closed, the trim clutch feedback (ELTCLTCH) is also examined and
verified to be high. See Figure 1.

The diode is tested for shorts by the subroutine MONTST called from PFLTTSTA (not done
in ATR 42/72). This interrupt driven test is done only on the ground and only with valid
synchronization with the cross FZ. Synchronization is done by using the direct cross
channel discretes (XSYNCOUT--F95E, XSYNCIN--F922) and the test status transmitted on
the ASCB in WSP1.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Software Description

1. During the entire period that the cross--FZ is in test, this side monitors the trim clutch line
(ELTCLTCH).

2. If the clutch line goes high, the relay feedback (ELTRELAY) is verified to be low.

3. Normal test completion is based on a low input of the cross sync signal (XSYNCIN).
Abnormal completion is based on a maximum test timeout counter. Abnormal completion
will clear any latched failures flags.

X--FZ Synchronization
The inability to synchronize with the X--FZ will not result in failures. It will cause certain tests to
be bypassed, including this shorted diode test and the ASCB preflight test. Synchronization is
used only to determine which FZ starts its relay tests first. It is not used for any other tests.
With valid synchronization, the left FZ will always start its relay tests, while the right monitors.
When the left completes, the right FZ starts its relay tests.
Synchronization is done prior to the start of the relay tests by the submodule ENSYNC called
from PFLTTSTA. This routine will output the flag DOMONTST. If set, perform the shorted diode
test. Otherwise, do the relay tests. The B--CPU is slaved to the A’s decision.
Synchronization problems will cause various bits to be set in the byte flag CHANSYNC. The
specific bit set will depending on pilot versus copilot installation. Table 5 shows the bit
definition.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Table 5. CHANSYNC

Bit No Description
7 The L--FZ saw that the R--FZ ASCB self--test flag was set, but XSYNCIN was not
cleared. This will occur if the L--FZ is powered--up with the R--FZ in ground mainte-
nance test.
6 The R--FZ did not see XSYNCIN transition low after the L--FZ cleared its ASCB self--
test flag.
5 The L--FZ saw XSYNCIN set, and not cleared.
4 The R--FZ saw XSYNCIN set, and not cleared.
3 The R--FZ read valid ASCB data, but did not see the L--FZs self--test flag set. This is
indicative of the R--FZ powered--up with the L--FZ on--line.
2 The L--FZ read valid ASCB data, but did not see the R--FZs self--test flag set. This is
indicative of the L--FZ powered--up with the R--FZ on--line.
1 The L--FZ did not see valid R--FZ ASCB data. Indicative o the R--FZ not installed.
0 The R--FZ did not see valid L--FZ ASCB data. Indicative of the L--FZ not installed.

G4.3 MAIN3A
• MAIN3A -- Bit 15 -- 200 ms Power Down Timer Fail

The 200 ms power down RC timer is verified to properly discharge after LPV is reset. After
LPV is verified to transition valid (see MAIN2A -- bit 14), the timer (DWN200MS--F912) is
monitored. It must transition (MSB=0) within a 4 ms period. If it does not, this failure flag is
set.

This test is performed by both CPUs before real time after any cold start.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN3A -- Bit 14 -- Power Interrupt Interlocks Test Fail

Specific hardware signal interlocks with PV and LPV are tested. These include the flight
director annunciator valid, the bus driver enables, and the servo power relays interlocks
(see Figure 4, Figure 3, and Figure 6).

The signals are initialized to their active state. The power supply monitor is tripped, using
the undervoltage discrete (controlled by B--CPU). The signals are then verified to be
inactive. If any failures are detected, the functional fault is isolated and the appropriate
MAIN failure flag latched.

Whenever any fault is detected, the status of the hardware causing the fault is latched in
the word PLOCKF (address C00E). This data is shown in Table 6.

If no failures are detected, nothing is latched in PLOCKF. Only if a failure is detected will
data be latched. When this test passes, the status of the post--test conditions will equal:
007FH. If it does not equal this, the discrete signals corresponding to the missing bits will
be at fault. For example, if the data recorded equalled 007DH, the signal at fault was
QAPPWROF. This implies that the AP servo power relay did not open after the simulated
power reset.

Table 6. PLOCKF -- A--Processor

Bit No. Description


15--8 Spare
7 FD/Annunciator Valid FB (QANNUNFB--F508)
6 A--Bus Driver Enable FB (ABUSENWA--F91C)
(GIV -- Spare)
5 B--Bus Driver Enable FB (BBUSENWA--F91E)
(GIV and ATR -- Spare)#
4 AP Servo Power FB (QAPPWRFB--F400)
3 YD Servo Power FB (QYDPWRFB--F414)
2 Emergency Disconnect not pushed FB
(QEMERGD1--F410)
1 AP Servo Power Off FB (QAPPWROF--F402)
0 YD Servo Power Off FB (QYDPWROF--F416)
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN3A -- Bit 13 -- HBM Failure (Timer Too Short)

The heartbeat monitor (HBM) timeout period is measured using software loops. This failure
indicates that the heartbeat timeout was measured to be less than 40 ms. This test is
executed during non--real time by the submodule HBMLOCKA called from MONTSTA. It is
performed after any cold start.
Software Description

1. The A--CPU HBM test is first performed. It is done in conjunction with the hardware
interlocks test (see MAIN3A -- bit 11). The heartbeat timeout test will always be performed
regardless of the synchronization status.

2. The heartbeat monitor is strobed (AHBEAT--F95A) for 20 µs.

3. This failure flag is initialized to indicate failed.

4. A 40 ms software timeout is executed. If a reset does not occur within this period, the
failure flag is reset. If it does, the fault flag remains set. The heartbeat test continues (see
MAIN3A -- bit 12).

Since the real--time executive resets the heartbeat monitor every 50 ms, use of the ASCB to
extract this failure will be useless.
• MAIN3A -- Bit 12 -- HBM Failure (Timer Too Long)

As a continuation of the heartbeat tests (see MAIN3A -- bit 11) the HBM timeout period is
verified to be less than 100 ms.
Software Description

1. After completion of the HBM timer too short test (40 ms already accumulated), a 60 ms
software timeout period is executed. A CPU reset should occur sometime within this period
(typically after another 24 ms at room temperature).

2. The CPU will verify, upon recovery from the HBM reset, that the actual cause was the HB
monitor and not by an external power reset (differentiated using LPV). If the cause was an
external power reset, all tests are performed again.

3. If the HBM did not reset after 100 ms (total), the HBM is strobed again (AHBEAT--F95A)
and this failure flag is latched.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN3A -- Bit 11 -- HBM Reset Interlocks Test Fail

Specific hardware signal interlocks with the heartbeat monitor valid are tested. These
include the bus driver enables, the servo power relays, and the Flight director annunciator
valid interlocks (see Figure 4, Figure 3, and Figure 6).

The signals are initialized to their active state. The heartbeat test is then performed. With
a valid HB reset, the state of these signals is examined. If any failures are detected, the
functional fault is isolated and the appropriate MAIN failure flag latched.

Whenever any fault is detected, the status of the hardware causing the fault is latched in
the word HLOCKF (address C010). If no faults are detected, nothing is latched. This data
is shown in Table 7.

When this hardware is initialized to their active states, their feedback signals should
equal 00FCH. After the heartbeat monitor reset, the signal feedbacks are verified to
transition to their proper state. This post--test state should equal 007FH. If it does not
equal this, the discrete signal(s) corresponding to the missing bit(s) will be at fault. For
example, if the data recorded equalled 006FH, the signal at fault was QAPPWRFB. This
implies that AP servo power was either not on or could not be read by the CPU. However,
since the AP servo power relay seemed to operate correctly, it implies that power was on,
but could not be read by the CPU (A5 ECA failure).

Table 7. HLOCKF -- A--Processor

Bit No. Description


15 Pre--test Conditions Fail
14--8 Spare
7 FD/Annunciator Valid FB (QANNUNFB--F508)
6 A--Bus Driver Enable FB (ABUSENWA--F91C)
(GIV -- Spare)
5 B--Bus Driver Enable FB (BBUSENWA--F91E)
(GIV and ATR -- Spare)
4 AP Servo Power FB (QAPPWRFB--F400)
3 YD Servo Power FB (QYDPWRFB--F414)
2 Emergency Disconnect not pushed FB
(QEMERGD1--F410)
1 AP Servo Power Off FB (QAPPWROF--F402)
0 YD Servo Power Off FB (QYDPWROF--F416)
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN3A -- Bit 10 -- Power Interrupt Pre--test Conditions Fail

Specific hardware signals are initialized to their active state prior to power interrupt testing.
These include the Flight director annunciator valid, the bus driver enables, and the servo
power relays (see Figure 6, Figure 4, and Figure 3).

The flight director annunciator valid (FDANNVAL--F95C=1) and servo power relay enable
(APWREN--F94C=1) are commanded to their active state in submodule INTLOCKA, called
from MONTSTA. Updating the data encompasses writing to the serial strobe and verifying
its completion 10 times, with a 1 ms wait between requests. The ASCB driver is enabled
(see MAIN2A -- bit 7) and the submodule PACKER packs the MSB of each of the discrete
feedbacks shown in Table 6. The resultant 16 bits are verified to equal 009CH. If they do
not, this failure flag is set and test discrete status is latched.
• MAIN3A -- Bit 9 -- HBM Reset Pre--test Conditions Fail

Specific hardware signals are initialized to their active state prior to HBM reset testing.
These include the Flight director annunciator valid and the servo power relays (see Figure 6
and Figure 3).

The flight director annunciator valid (FDANNVAL--F95C=1) and servo power relay enable
(APWREN--F94C=1) are commanded to their active state in submodule INTLOCKA and
called from MONTSTA. Updating the data encompasses writing to the serial strobe and
verifying its completion 10 times, with a 1 ms wait between requests. The submodule
PACKER packs the MSB of each of the discrete feedbacks shown in Table 7. The resultant
16 bits are verified to equal 00FCH. If they do not, this failure flag is set, and test discrete
status is latched. (See MAIN2A -- bit 7 for ASCB driver enable testing).
• MAIN3A -- Bit 8 -- Spare
• MAIN3A -- Bit 7 -- Preflight Test Ticket Fail

The following tests are required to be performed, and verified not to have been bypassed,
after all cold starts:
− Aircraft configuration (strapping logic) test
− Storage memory (RAM) test
− Program memory (ROM) test
− Heartbeat monitor test
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

One word (MONSYNCA--C008) is used to latch the completion status of all tests. After
completing each given test, a bit corresponding to the given test is set. The definition of each of
these bits is shown in Table 8.
If all tests shown in this table are performed, the status of MONSYNCA is FFBCH. This test
verifies that the following bits are set: 10, 9, 5, 4, 3, and 2 (063C). If these bits are not set, this
failure flag is latched. This test is performed in the submodule TESTSTAT and is called from
MONTSTA. This is a non--real time test done after every cold start.

Table 8. MONSYNCA

Bit No. Test Completed


15 Reserved (non--real time tests started)
14 Status transfer RAM wraparound 1 complete
13 Status transfer RAM wraparound 2 complete
12 Status transfer RAM wraparound 3 complete
11 Status transfer RAM wraparound 4 complete
10 Scratch RAM write/read test complete
9 ROM checksum test complete
8 B--Processor voltage monitor tests complete
7 Discretes test complete
6 Spare
5 HBM interlock test complete
4 Scratch RAM address/data bus test complete
3 ACFT configuration test complete
2 Power interlock test complete
1 Spare
0 Spare
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN3A -- Bit 6 -- A/B Processor Synchronization Fail

This failure flag applies only to Dash 8 and CIT III.

Failure of the two processors to properly synchronize implies that some sort of internal fault
has occurred. This failure flag is set based on the 8--bit word PINVSYNC (C022). Bit 7 of
PINVSYNC will be set if any synchronization failures occur during the interrupt driven tests
(PFLTTSTA or RETESTA). The bit definition is shown in Table 9.

Table 9. PINVSYNC -- A--PROCESSOR

Bit No. Description


7 Part 2 test Sync Failure
6 Shorted resistor test bypassed
5 Shorted resistor test complete sync failed
4 Clutch engagement test bypassed
3 Clutch engagement test complete sync failed
2 Recentering test complete sync fail
(Dash 8 and CL601)
1 Spare
0 Stuck relay test complete sync fail
*Dash 8 and CL601 only

The synchronization method employed by these tests is based on flags transferred between
CPUs using the status transfer RAM. Synchronization is done at the start, and end of each test.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

The words SWTIKETA (A--CPU output) and SWTIKETB (input from B--CPU) are used for
synchronization. These words are defined in Table 10.

Table 10. SWTIKETA/SWTIKETB

Bit No. Description


15 Recentering test start (1)
14--10 Spare
9 Recentering test complete (1)
8 Stuck relay test complete
7 Servo amp test complete (5)
6 Power--up BIT test complete (3)
5 Diode test complete (2)
4 Engage test complete
3 Engage test start
2 Resistor test done
1 Resistor test start
0 Shorted diode test start (2) (4)
NOTES: (1) Applicable to Dash 8 and CL600

(2) Spare in ATR


(3) Spare in ATR SWTIKETB
(4) Spare for SWTIKETB
(5) Spare in BAe SWTIKETA
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

MAIN3A -- Bit 5 -- A/B Processor Synchronization Failure


This failure flag applies only to Dash 8 and CIT III.
Failure of the two processors to properly synchronize implies that some sort of internal fault has
occurred. This flag is a copy of another flag, INVSYNC (C01B). It is used to latch a sync failure
occurring during the non--real time tests (MONTSTA, PRAMCKA, CKSUMA).
The synchronization method used by these tests is based on the direct sync discretes
(ASYNCOUT--F934, BSYNCIN--F914). Prior to the start of each given test, the processor sets
ASYNCOUT and waits a predetermined amount of time for BSYNCIN to transition high. When
this occurs, the processor clears ASYNCOUT, and waits up to 100 µs for BSYNCIN to transition
low. Synchronization is considered valid whenever this occurs.
Any timeouts will latch the sync failure in INVSYNC. This flag is examined in the module
RETESTA, where the fault is recorded in this maintenance word.

MAIN3A -- Bit 4 -- YD Servo Power Fail


This flag is applicable only to Dash 8 and CIT III.
This fault is recorded by both CPUs (see HLOCKF and PLOCKF), but latched in the
maintenance words by the A--CPU only.
This fault is isolated by the non--real time submodule TESTSTAT, which uses the subroutine
PWRFAILS. This will be done whenever a pretest conditions failure is detected (see
MAIN3A -- bits 9 and 10). Isolation is based on the status conditions stored in HLOCKF and
PLOCKF (bit 0).

MAIN3A -- Bit 3 -- AP Servo Power Fail


This flag is applicable only to Dash 8 and CIT III.
This fault is recorded by both CPUs (see HLOCKF and PLOCKF), but latched in the
maintenance words by the A--CPU only.
This fault is isolated by the non--real time submodule TESTSTAT, which uses the subroutine
PWRFAILS. This will be done whenever a pretest conditions failure is detected (see MAIN3A --
bits 9 and 10). Isolation is based on the status conditions stored in HLOCKF and
PLOCKF (bit 1).

MAIN3A -- Bit 2 -- Emergency Disconnect Fail


This flag is applicable only to Dash 8 and CIT III.
This fault is recorded by both CPUs (see HLOCKF and PLOCKF), but latched in the
maintenance words by the A--CPU only.
This fault is isolated by the non--real time submodule TESTSTAT, which uses the subroutine
PWRFAILS. This will be done whenever a pretest conditions failure is detected (see
MAIN3A -- bits 9 and 10). Isolation is based on the status conditions stored in HLOCKF and
PLOCKF (bit 2).
MAIN3A -- Bits 1--0 -- Spare
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

G4.4 Miscellaneous
STATWDA-- This byte is used internally to latch status general conditions. Its bit definition is
shown below:

Bit No. Description


7--5 Spare
4 Channel Status (1= L--FZ, 0= R--FZ) (Spare -- ATR)
3 Priority Channel Select Fail (Spare -- ATR). The left/right con-
figuration pins (LTKEY1/LTKEY2) are either both grounded, or
both open (JIB--102, J1B--103)
2 AP and/or YD servo power was not on.
1 Spare
0 Elev Trim Fail -- a failure was detected, affecting the Elev Trim
function.

G5. B--PROCESSOR FAILURE FLAG DESCRIPTIONS

G5.1 MAIN1B
MAIN1B -- Bit 15 -- Servo Power Pre--Enable Conditions Fail
The submodule COLDTST, called from RETESTB, examines the conditions necessary to test
the servo power relays. If both AP and YD servo power are present and both AP and YD servo
power relays open, the servos off feedback is verified to be high. If it is not, this failure flag is
set (see Figure 3).
This test is done after any cold start, and is interrupt driven. The same test is performed in the
A--CPU (see MAIN1A -- bit 12).
Software Description

1. Delay 150 ms.

2. Verify that AP servo power is present (APPWRFB=1). If not, set bit in STATWDB (see
Miscellaneous, paragraph 5.4) and return.

3. Verify that YD servo power is present (YDPWRFB=1). If not, set bit in STATWDB (see
Miscellaneous, paragraph 5.4) and return.

4. Verify that the AP servo power relay is open by reading AP Power off feedback discrete
(APPWROFB=1). If not, set MAIN1B, bit 4 and return.

5. Verify that the YD servo power relay is open by reading YD power off feedback discrete
(YDPWROFB)=1. If not, set MAIN1B, bit 5 and return.
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Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

6. Verify that the servos off feedback discrete is set (SRVOFFB=1). If not, set this failure flag.

7. Enable the servo power relay by setting the servo power relay engage command
(BPWREN--F740=1).

8. .Verify that the relay closes within 300 ms by examining the AP power off feedback
(APPWROFB=0). If it does not transition low and the emergency disconnect is not active,
set MAIN1B -- bit 4. Verify that the YD power off feedback (YDPWROFB=0) transitions low
within this same period. If it does not transition low, and the emergency disconnect is not
active, set MAIN1B -- bit 5.

• MAIN1B -- Bit 14 -- YD Engage Test Fail

The YD brake (clutch) relay is tested at the same time the B--CPU tests the AP clutch relay
and the A--CPU tests the elev trim relay. This is done in the engage test (ENGTSTB) called
from PFLTTSTB. This is an interrupts driven test performed only on the ground. See
Figure 8.
Software Description

1. The servo power relay is enabled and verified to be engaged.

2. Verify that the conditions are valid for relay engagement (see MAIN1B -- bit 10)

3. Command the YD relay to engage (YDENCMD--F734=1).

4. Verify that the relay engages within 225 ms. If not, set the fail flag.

• MAIN1B -- Bit 13 -- AP Engage Test Fail

The AP clutch relay is tested at the same time the B--CPU tests the YD brake (clutch) relay
and the A--CPU tests the elev trim relay. This is done in the engage test (ENGTSTB) called
from PFLTTSTB. This is an interrupt driven test performed only on the ground. See Figure
8.
Software Description

1. The servo power relay is enabled and verified to be engaged.

2. Verify that the conditions are valid for relay engagement (see MAIN1B -- bit 9)

3. Command the AP relay to engage (APENCMD--F730=1).

4. 4.Verify that the relay engages within 225 ms. If not, set the fail flag.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN1B -- Bit 12----

This fault flag is defined differently between applications as follows:

Application Definition
CL601 High Trim Rate Command End--around Fail
Dash 8 YD Quick Disconnect Input Fail
All Others Spare
High Trim Rate Command End--around Fail
The elevator high trim rate command is output from the A--processor (see MAIN1A -- bit 11), and
the feedback (ELTHRFB) is verified to be enabled. This interrupts driven test is performed only
on the ground.
Software Description

1. Command and verify that the servo power relay is engaged.

2. Set this failure flag, and monitor the trim rate command feedback (ELTHRFB).

3. If the feedback transitions high within 200 ms, the failure flag is cleared.

YD Quick Disconnect Off Input Fail


The state of the YD quick disconnect pushbutton is examined prior to each relay test. If the
input (YDDISC1=0) indicates “pushed” or on, this fault flag is set (see MAIN1B -- bit 10).
The YD quick disconnect input is verified by both CPUs. This failure flag is latched only by the
B--CPU.
This input ties directly into the YD relay engage logic. It must be active for the relays to properly
operate. In Dash 8 only, this input is 28 V/open. (Logic: 28 V = not pushed = off = high). For all
other applications, this input is ground/open.
• MAIN1B -- Bit 11----

This fault flag is defined differently between applications.

Application Definition
CL601 and GIV AP Brake Relay Fail
Dash 8 AP Quick Disconnect Input Fail
All Others Spare
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

AP Brake Relay Fail


This interrupts driven test verifies the operation of the AP Brake Relay. It is tested only on the
ground by the submodule ENGTST called from PFLTTSTB.
Software Description

1. The AP clutch relay is verified to be engaged (see MAIN1B -- bit 13). If not, this test is
aborted.

2. The AP Brake feedback (APBRKFB=1) is then examined to be active. If it is not, this flag is
set.

AP Quick Disconnect Input Fail


The state of the AP quick disconnect pushbutton is examined prior to each relay test. If the
input (APDISC1=0) indicates “pushed” or on, this fault flag is set (see MAIN1B -- bit 9).
The AP quick disconnect input is verified by both CPUs. This failure flag is latched only by the
B--processor.
This input ties directly into the AP relay engage logic. It must be active for the relays to properly
operate. In Dash 8 only, this input is 28 V/open. (Logic: 28 V = not pushed = off = high). For all
other applications, this input is ground/open.
• MAIN1B -- Bit 10 -- YD Pre--Engage Conditions Fail

This failure flag can be set in any one of three places: prior to running the shorted resistor
test (RESTST); prior to running the relay engage test (ENGTST); and lastly, prior to
executing the shorted relay test (RLYTST). This flag is set only if the conditions for running
these tests are not valid. The conditions are examined using a subroutine (YDSTAT). This
test is called by PFLTTSTB, is interrupt driven, and is done only on the ground.

Several minor differences exist between various applications and are called--out in the
implementation described below:

1. Verify that the YD relay is not closed (YDRELAY=0).

2. Verify that the YD servo power relay is not open (YDPWROFB=0).

3. Verify that the YD quick disconnect switch is not pushed (YDDISC1=1).

4. Examine the YD brake (YDBRKFB) signal. If it is active, verify it is because the X--FZ
is either engaged (status transmitted via ASCB -- TAFCSST2, bit 13) or recentering
(OFFCENT). Either case will prevent this FZ from testing its YD servos without
latching any faults. This condition is examined only in F900 and Dash 8.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

5. Verify that no X--FZ servos are engaged (XSRVOFF=0). If cross servos are engaged,
verify that it is because X--Mach trim is selected (status transmitted via ASCB --
TAFCSST2, bit 9). The Mach trim verification is done only in F900.

6. If any of these conditions are incorrect, this fault flag is set, and will cause all YD servo
tests to be bypassed.

• MAIN1B -- Bit 9 -- AP Pre--Engage Conditions Fail

This failure flag can be set in any one of three places: prior to running the shorted resistor
test (RESTST); prior to running the relay engage test (ENGTST); and finally, prior to
executing the shorted relay test (RLYTST). This flag is set only if the conditions for running
these tests are not valid. The conditions are examined, using a subroutine (APSTAT). This
test is done by PFLTTSTB and is interrupt driven. This test is executed only on the ground.

Several minor differences exist between various applications and are called--out in the
implementation described below:

1. Verify that the AP relay is not closed (APRELAY=0).

2. Verify that the AP servo power relay is not open (APPWROFB=0).

3. Verify that the AP quick disconnect switch is not pushed (APDISC1=1).

4. Verify that the AP clutch (APCLTCH=0) signal is inactive.

5. Verify that no X--FZ servos are engaged (XSRVOFF=0). In Dash 8, if cross servos are
engaged, verify that it is because YD brake is active. Also, in F900, verify that X--Mach
trim is selected (Mach trim status transmitted via ASCB -- TAFCSST2, bit 9).

6. If any of these conditions are incorrect, this fault flag is set and will cause all YD servo
tests to be bypassed.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN1B -- Bit 8 -- Recentering Failure (Active Too Long)

This test is done only in CL601 and Dash 8.

Prior to testing for shorted resistors (RESTST) or stuck relays (RLYTST), the status of the
recentering hardware is examined. If this status indicates that the recentering hardware
has remained active for greater than 6--seconds, this flag is set. This test is done only on
the ground by the module PFLTTSTB. It is an interrupt driven test.
Software Description -- Dash 8

1. Examine the recentering active discrete feedback (QOFFCENT--F42C). If inactive,


then exit this test.

2. If recentering is active, then check the X--FZs YD engage status (transmitted via
ASCB; TAFCSST2--bit 13). If normal engagement (=1), then return.

3. If normal engagement is not indicated, and recentering remains active


(QOFFCENT=1) for 6--seconds, set this fault flag.

CL601

1. Examine the recentering active (QYDRCENT--F42C) and the YD brake feedback


(QYDBRKFB--F428) discretes.

2. If either remain active for greater than 6--seconds, then set this fault flag.

3. If both are inactive, then exit this test.

• MAIN1B -- Bit 7 -- Servos Off AND Gate Failure

The servos off AND gate is tested in both the shorted resistor test (RESTST) and in the
relay engage test (ENGTST). Both are called by PFLTTSTB. This discrete is tested by
both processors under the same conditions (see MAIN1A -- bit 7). This is an interrupt
driven test done only on the ground. See Figure 8.
Software Description -- RESTST

1. All servo clutch relays are disengaged, and the servo power relay is engaged.

2. The servos off AND gate feedback is verified to be set (SRVOFFB). If not, set this
failure flag is set.

ENGTST

1. The AP clutch relay is verified to be engaged (see MAIN1B -- bit 13). If it is not
engaged, the servos off ‘AND’ gate is not tested.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

2. The servos off AND gate feedback discrete is verified to be low (SRVOFFB). If it is
not, this failure flag is set.

• MAIN1B -- Bit 6 -- Servo Power Off ‘OR’ Gate Failure

The servo power off OR gate is tested when the servo power relay is engaged, and when it
is disengaged (see Figure 3). This is done in the shorted resistor test (RESTST) in the
module PFLTTSTB. This is an interrupt driven test done only on the ground.
Software Description

1. With the servo power relay engaged, the servo power off OR gate (SRVPOFFB=0) is
verified to be cleared after a 400 ms settling delay. If not this failure flag is set.

2. The servo power enable is cleared, and the servo power relay is verified to open (see
MAIN1B bits 4 and 5).

3. When this relay is verified to be open, the servo power off OR gate is validated to be
high. If it is not, this failure flag is set.

• MAIN1B -- Bit 5 -- YD Servo Power Relay Fail

The AP and YD servo power relays are engaged and disengaged several times during the
power--up test (see Figure 3). The modules RETESTB and PFLTTSTB perform the tests
shown below. The RETESTB tests are done after any cold start. PFLLTSTB tests are
done only on the ground. Both are interrupt driven. Both tests are performed by each
processor (see MAIN1A -- bit 12).
Software Description -- RETESTB (Submodule COLDTST)

1. Delay 150 ms.

2. Verify that AP servo power is present (APPWRFB=1). If not, set bit in STATWDB (see
Miscellaneous, paragraph 5.4) and bypass all further testing.

3. Verify that YD servo power is present (YDPWRFB=1). If not, set bit in STATWDB (see
Miscellaneous, paragraph 5.4) and bypass all further testing.

4. Verify that the AP servo power relay is open by reading AP Power off feedback
discrete (APPWROFB=0). If not open, set MAIN1B -- bit 5.

5. Verify that the YD servo power relay is open by reading YD power off feedback
discrete (YDPWROFB=0). If not open, set this failure flag.

6. Verify that the servos off feedback discrete is set (SRVOFFB=1). If not, set MAIN1B --
bit 15.

7. Enable the servo power relay by setting the servo power relay engage command
(BPWREN--F740=1).
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

8. Verify that the relay closes within 300 ms by making sure that the following feedback
discretes are clear:

-- AP power off feedback (APPWROFB)


-- YD power off feedback (YDPWROFB)

9. If the emergency quick disconnect is active (EMERGD1=0), then bypass setting this
failure flag. If inactive (=1), then set this flag.

NOTE: This emergency disconnect bypass is used only for this test.

PFLTTSTB (Submodule RESTST)

1. With the servo power relay engaged, the relay is commanded to open
(BPWREN--F740=0).

2. Verify that the relay opens by monitoring AP power off feedback (APPWROFB). This
must transition high (=1) within 225 ms. If not, set this failure flag.

• MAIN1B -- Bit 4 -- AP Servo Power Relay Fail

The AP and YD servo power relays are tested at the same time and in the same manner.
See MAIN1B -- bit 5 above.
• MAIN1B -- Bit 3 -- YD Servo Engage Relay Fail

This test verifies that the YD servo engage relay is not stuck closed. This test (RLYTST) is
called from PFLTTSTB. It is an interrupt driven test executed only on the ground. Both the
YD and AP servo engage relays are tested concurrently. See Figure 8.
Software Description

1. Conditions for enabling the driver are first verified (YD relay not engaged, servo power
relay engaged, see MAIN1B -- bit 10) in order to determine if this test should be
bypassed or not.

2. The YD command is cleared (YDCMD), followed by a 500 ms settling delay.

3. The servo amp is initialized with a full--scale up command (7F00H), and its driver
(YDDRIV--F736=1) enabled.

4. YD servo voltage feedback (YDVOLT--F61C) and YD brake (Dash 8 only) are


monitored for 50 ms. If the voltage exceeds 10v within this period, and YD brake
feedback is low, the command is immediately cleared, and the failure flag set.

5. All output commands are then cleared.


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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN1B -- Bit 2 -- AP Servo Engage Relay Fail

This test verifies that the AP servo engage relay is not stuck closed. This test (RLYTST) is
called from PFLTTSTB. It is an interrupt driven test executed only on the ground. Both the
YD and AP servo engage relays are tested concurrently. See Figure 8.
Software Description

1. 1.Conditions for enabling the driver are first verified (AP relay not engaged; servo
power relay engaged, see MAIN1B -- bit 9) to determine if this test should be bypassed
or not.

2. The AP commands are cleared (AILOUT, ELOUT), followed by a 500 ms settling delay.

3. The servo amplifier is initialized with a full--scale up command (7F00H) and its driver
(APDRIV--F732=1) enabled.

4. The AP servo voltage feedbacks (AILVOLT--F616, ELVOLT--F624) are monitored for


50 ms. If the voltage exceeds 10 V within this period, the command is immediately
cleared and the failure flag set.

5. The drive enable is cleared in addition to all output commands.

• MAIN1B -- Bit 1 -- YD Pull--up Resistor Failure

This test is done by the submodule RESTST and is called in PFLTTSTB. This is an
interrupt driven test done only on the ground. Both the YD and AP pullup resistors are
tested at the same time. See Figure 8.
Software Description
With the servo power relay open, the YD relay is commanded to engage
(YDENCMD--F734). After a 225 ms delay, the relay is examined. If it closed
(YDRELAY=1), which means power is being applied to the relay, possibly through a shorted
pull--up resistor, this failure flag is set.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN1B -- Bit 0 -- AP Pull--up Resistor Failure

This test is done by the submodule RESTST and is called in PFLTTSTB. This is an
interrupt driven test done only on the ground. Both the YD and AP pull--up resistors are
tested at the same time. See Figure 8.
Software Description
With the servo power relay open, the AP relay is commanded to engage
(APENCMD--F730). After a 225 ms delay, the relay is examined. If it closed
(APRELAY=1), which means that power is being applied to the relay, possibly through a
shorted pullup resistor, this failure flag is set.

G5.2 MAIN2B
• MAIN2B -- Bit 15 -- D/A End--around Fail

The A/D converter is exercised through its complete operational conversion range via
end--around, using the D/A converter. Control of all data conversions is done by the
real--time process. Output command and end--around verification is performed by
submodule IOWRAP called by PFLTTSTB.

The software control flow is described below:

1. The D/A (YD command DAC in applications with linear actuators) is initialized with the
first entry shown in Table 11.

2. The test waits 125 ms for the conversion to complete.

3. The feedbacks (YDCMDFB=TDACFB--F626) are compared with their corresponding


inverted command, and verified against the tolerances shown below.

GIV, Dash 8, ATR42, CL601, F900 and BAe--800 -- Conversion tolerance: ±156 mV

All others -- Conversion tolerance: ±300 mV

NOTE: YDWAERR is defined in module PUCONA.


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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Table 11. D/A End--around Test Commands -- B--Processor

COMMAND VOLTAGE
8CCD --9.00
C000 --5.00
E000 --2.50
F000 --1.25
F800 --0.63
FC00 --0.31
FE00 --0.16
0000 0.0
0200 +0.16
0400 +0.31
0800 +0.63
1000 +1.25
2000 +2.50
4000 +5.00
7330 +9.00

• MAIN2B -- Bit 14 -- Latched Power Valid Failure

This failure flag is initialized by the module MONTSTB prior to setting bit 15 of latched
power valid reset (LPVRESET--F77C). A tight loop is then executed, waiting for latched
power valid (LPV--F710) to transition from invalid to valid (1 --> 0). No other processing will
be done until this transition. If it does not correctly transition (A2 ECA), or if its direct
discrete feedback processing fails (A6 ECA), the software will remain in this loop (see
MAIN2A -- bit 14).
• MAIN2B -- Bit 13 -- Memory Checksum Failure

The module CKSUMB, called by MONTSTB, sums the data at every address on every page
of ROM memory. The data is summed as long words or 32 bits. The test is considered to
pass if the sumcheck of memory, as a whole, equals zero. This is a non--real time test.

NOTE: This test is repeated once if it fails the first time.

One of the last steps in the software verification process, (prior to certification) is to patch a
32--bit calculated constant in each page of memory. This patched constant allows each
page to sum to zero.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN2B -- Bit 12 -- RAM Failure

The module PRAMCKB, called by MONTSTB, exercises each RAM address between
C000--F000. This non--real time test is configured in two parts, (1) address/data bus test
(ADDRTST) and (2) write/read test (PRAM). The first test will verify that no two address or
data lines are shorted together, the second will verify that each cell will toggle. This test is
performed after any cold start.
Software Description -- Address/Data Bus Test

1. The starting address of RAM is initialized in a software loop that:


a. Saves the data contained in the 16--bit cell to be tested.
b. Writes a unique word into the test cell, the unique word being the test address.
c. Updates the next address of the next cell to be tested, finally looping back to step a.
The address and data written are shown in Table 12.
2. After all writes have been completed, another loop is executed. This loop:
a. Reads the data at each test cell and verifies that the data read was what was written.
b. Replaces the original contents.
c. Sets a temporary fault flag if mismatches are detected.
3. If any failures were detected, the entire test is performed once more. The fail flag is
set if the test fails the second time.

Table 12. RAM Address/Data Bus Test

Address Data Write


C000 C000
C002 C002
C004 C004
C008 C008
C010 C010
C020 C020
C040 C040
C080 C080
C100 C100
C200 C200
C400 C400
C800 C800
D000 D000
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Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Read/Write Test
This test subdivides RAM into a series of 400H work blocks. A detected failure will set a bit in a
word (RAMFLG). This bit corresponds to its 400H word block of addresses indicating that a
write/read failure occurred within this address range. These failure flags are defined Table 13.

1. Initialize starting RAM address.

2. Initialize the test pattern to ‘5555’.

3. Initialize block counters.

a. Store the original contents of test cell

b. Write pattern into test cell.

c. Read the data from the test cell and compare with the written pattern.

d. If a fault is detected, re--do steps b and c. If faults are again detected, latch failure
flags.

e. Complement the test pattern (AAAA).

f. Execute steps b through d.

g. Restore the original test cell contents.

h. Continue until all of RAM is tested.

i. Set this failure flag if RAMFLG bits 0--7 are not all zero.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Table 13. RAM Write/Read Failure Locations

RAMFLG Address Range


bit 15 Spare
bit 14 Spare
bit 13 Spare
bit 12 Spare
bit 11 Spare
bit 10 Spare
bit 9 Spare
bit 8 Spare
bit 7 DC00H--DFFEH
bit 6 D800H--DBFEH
bit 5 D400H--D7FEH
bit 4 D000H--D3FEH
bit 3 CC00H--CFFEH
bit 2 C800H--CBFEH
bit 1 C400H--C7FEH#
bit 0 C000H--C3FEH#

• MAIN2B -- Bit 11 -- B/A Processor Synchronization Failure

This failure flag applies only to Dash 8 and CIT III.

Failure of the two processors to properly synchronize implies that some sort of internal fault
has occurred. This failure flag is set based on the 8--bit word PINVSYNC (C022). Bit 7 of
PINVSYNC will be set if any synchronization failures occur during the interrupt driven tests
(PFLTTSTB or RETESTB). The bit definition is shown in Table 14.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

Table 14. PINVSYNC -- B--CPU

Bit No. Description


7 Part 2 Test Sync Failure
6 A--processor X--FZ (TESTSYNC) Failed
5 Shorted Resistor Test Bypassed
4 Shorted Resistor Test Completed Sync Failed
3 Clutch Engagement Test Bypassed
2 Clutch Engagement Test Complete Sync Fail
1 Shorted Diode Test Sync Fail
0 Stuck Relay Test Complete Sync Fail

The synchronization method employed by these tests is based on flags transferred between
CPUs using the status transfer RAM. Synchronization is done at the start, and completion of
each test.
The words SWTIKETB (B--CPU output) and SWTIKETA (input from A--CPU) are used for
synchronization. These words are defined in Table 10.
• MAIN2B -- Bit 10 -- 5 Volt Undervoltage Monitor Fail

The B--processor can directly simulate an undervoltage condition by writing to UVDISCR


(F74A) found on the A6--ECA. This, in turn, generates a pulse to the A1--ECA. The pulse
drives the +5 V main power supply monitor low, thereby forcing a PV reset. PV (PVB1) also
clears the pulse.

This test is performed by MONTSTB. It is done in non--real time after any cold start. The
flag can be set in one of two places. The first is described below, the second is described
in the power interlock test (see MAIN3B -- bit 14).
Software Description

1. Initialize software restart pointers.

2. Wait 50 us (A--processor setup time).

3. Set the UVDISCR.

4. In Dash 8, ATR42, and BAe--800, wait up to 400 us for the reset to occur. In all others,
wait 950 us.

5. If the reset does not happen, set this fault flag, and clear the UVDISCR discrete.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

• MAIN2B -- Bit 9 -- 5 Volt Overvoltage Monitor Test Fail

The B--processor can directly simulate an overvoltage condition by writing to OVDISCR


(F748) found on the A6--ECA. This, in turn, generates a pulse to the A1--ECA. The pulse
drives the +5 V main power supply monitor high, thereby forcing a PV reset. (PV (PVB1)
also clears the pulse.)

This test is performed by MONTSTB. It is done in non--real time after any cold start.
Software Description

1. Initialize software restart pointers.

2. Wait 50 us (A--processor setup time).

3. Set the OVDISCR.

4. In Dash 8, ATR42, and BAe--800, wait up to 400 us for the reset to occur. In all others,
wait 950 us.

5. If the reset does not happen, set this fault flag and clear the OVDISCR discrete.

• MAIN2B -- Bit 8 -- Serial End--around Failure

The B--processor verifies operation of the controller’s serial interface hardware internal to
the FZ. This test is performed only on the ground by the submodule SERIALWA. It is
called from PFLTTSTB, and is interrupt driven.
Software Description

1. Set BWRAP (F73E).

2. Wait 50 ms.

3. Check BWRAPFB (F460).

4. Verify that BWRAPFB is set.

5. Clear BWRAP.

6. Wait 50 ms.

7. Verify that the feedback is clear.

8. Any mismatches will abort this test, and set this fault flag.
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Flight Guidance Computer / Part No. 7003974

Table 1005. Integrated Test Procedure for 7003974--708, --713, --728, --732 (cont)

MAIN2B -- Bit 7 -- Status Transfer RAM Failure


The module PRAMCKB, called by MONTSTB, verifies all transfer RAM addresses between
F000--F400. This non--real time test is configured in three parts: (1) write/read test (TRAM), (2)
address/data bus test (TADTST), and (3) zeros test. The first test will verify that each cell will
toggle, the second will verify that no two address or data lines are shorted together, and the last
verifies that all locations can be cleared. This test is performed after any cold start.
Software Description -- Read/Write Test

1. This test verifies the transfer RAM as a whole.

2. The Priority Request discrete (BRAMPRI--F73C) is set, giving the B--processor access to
transferred data.

3. Initialize every B--processor output address (F200--F400) with a test pattern of 5555, then
clear the Priority Request discrete.

4. Wait for up to 2 ms for the A--processor to end--around this data. This synchronization is
performed using the direct sync discretes (see MAIN2B -- bit 3).

5. Set the priorit