International Conference on Advances in Computing, Communication Control and Networking (ICACCCN2018)
Design and Implementation of CMOS Full Adder
Circuit with ECRL and Sleepy Keeper Technique
Aaina Nandal
University School of Information, Communication and
Technology, Guru Gobind Singh Indraprastha University,
New Delhi, India
aaina.92@gmail.com
Abstract—In this paper ECRL with sleepy keeper technique
have been presented. The proposed adder shows less power
dissipation and less power delay product (PDP). The circuits have
been simulated in 0.18µm CMOS technology using Mentor
Graphics. The proposed Full adder indicates power dissipation of
129.819pW with a delay of 135.97ns at supply voltage of 1.8V.
Simulations have been completed with different supply voltages [1.0
– 1.8] V. Power dissipation of proposed full adder circuit have been
contrasted with earlier reported full adder designed circuits and
proposed approach indicates better outcomes.
Keywords— Adiabatic logic; CMOS; ECRL; Full adder; Low-
power; Power dissipation; PDP; Sleepy Keeper .
I. INTRODUCTION
Portable devices with low power design techniques are leading
the today’s electronic industries, because of expanding
demand of compact gadgets like laptops, cellphones and
various handheld devices etc. There is a huge evolution in
microelectronics industry since the invention of transistors that
set the foundation for low-power consuming devices. Many of
digital devices are designed and implemented using large
number of logic gates. Area of these devices is also a major
concern as portables devices demands more number of logic
gates on a single integrated chip. At present, around 1,00,000
or more logic gates can be fabricated on single IC chip in what
is known as VLSI (very large scale integration) [1]. One of the
most important measure of logic circuits is the Power
dissipation. In the initial period of VLSI technology its major
concern was speed optimization and sacrificed the portability
but nowadays, portability has become an important issue.
There are number of ways to improve the portability. One
approach to enhance the compactness is to decrease the chip
area but that result in high power dissipation. Customer
demands a gadget which is fast, portable, has all features
generation of heat is less and has low power dissipation. Some
different power reduction techniques are discussed in this
paper and full adder of 28 transistors is implemented and
analyzed using different power reduction techniques.
The three main types of Power dissipation in CMOS VLSI
circuits [2]: 1) Static Power due to leakage currents, 2)
Dynamic capacitive power due to charging and discharging of
various load capacitances, 3) Short-circuit power due to short-
circuit currents that arises when PMOS and NMOS transistors
conducts simultaneously.
ISBN: 978-1-5386-4119-4/18/$31.00 ©2018 IEEE
Manoj Kumar
University School of Information, Communication and
Technology, Guru Gobind Singh Indraprastha University,
New Delhi, India
manojtaleja@ipu.ac.in
As CMOS technology results in high speed devices but it
dissipates power so in order to reduce power dissipation
adiabatic logic technique is used. In writing different types of
adiabatic logic circuits have been introduced [3-8]. In
adiabatic methodology, charging and discharging the node
capacitances is done so that energy consumed during charging
is recovered or reused for the next cycle during discharging
phase [9]. In order to further reduce the power dissipation, a
new approach known as ECRL with Sleepy Keeper technique
is introduced in this paper. This is the combination of energy
efficient charge recovery logic (ECRL) which is an adiabatic
logic technique and sleepy keeper approach which uses
leakage feedback technique [11] [14]. Here, in current work
full adder with 28 transistors based on combination of ECRL
and sleepy keeper approach has been presented. Full Adder
based on CMOS technology, Sleepy keeper and ECRL
adiabatic logic technique using 28 transistors have also been
simulated and compared with proposed design. Rest of the
paper is sorted as: section II describes the system description
of full adder circuit mention in this paper. In section III,
results of power dissipation, delay and power delay product
have been obtained. In section IV, conclusions have been
drawn.
II. SYSTEM DESCRIPTION
Conventional CMOS full adder using 28 transistors is
implemented as shown in Fig. 1. It consists of equal number of
NMOS and PMOS transistors. Sum and carry output is
generated for various combinations of inputs. To reduce the
power dissipation of circuit sleepy keeper approach is used.
CMOS based sleepy keeper full adder is executed as appeared
in Fig. 2.
In Fig. 3 and Fig. 4 ECRL sum and carry circuit of full adder
is shown. It has two PMOS cross-coupled transistors in pull up
network and pull down network have NMOS transistors which
will carry out the logic of the circuit. ECRL adiabatic logic
technique utilizes ac power supply in place of dc supply for
the recovery of energy [10].
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Fig. 1. Conventional CMOS full adder
Fig. 2. CMOS sleepy keeper full adder
Fig. 3. ECRL sum circuit
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Fig. 4. ECRL carry circuit
In proposed Full Adder design, length of gate of all transistors
being taken as 0.18µm. Width (Wn) of NMOS transistors
being taken as 0.5µm. Width (Wp) of PMOS transistors have
been taken as 1µm. In the proposed design full adder is
realized with three inputs A, B and C. The Sum and Carry
generations circuits are demonstrated in Fig. 5 and Fig. 6
respectively. The full adder circuit is realized using
conventional 28 transistors mirror adder CMOS structure with
additional sleepy keeper transistors.
The Boolean expression for Sum and Carry can be expressed
as:
Sum = (A XOR B) XOR C (1)
Carry = A.B + C (A XOR B) (2)
Toward the start of cycle when supply clock PCK ascends
from 0 to VDD "OUT" stays at ground level and "OUTB"
finishes P1. At the point when PCK achieved VDD the output
holds the legitimate logic levels. These values are kept in hold
stage and will be utilized as inputs for the next stage. At the
point when PCK tumbles down from VDD to 0 “OUTB”
restores its energy to PCK with the goal that delivered charge
is recouped. At the point when there is no need of logic, extra
sleep transistors S and S' turns off the circuit and keeper
transistors which are set parallel to sleep transistors S and S'
keeps the already calculated condition of the circuit, since
keeper transistors are the main source of power supply to pull-
up system and GND to pull-down system in sleep mode.
These sleepy keeper transistors lessened the leakage power
dissipation of the circuit.
Fig. 5. ECRL sleepy keeper approach sum circuit
 International Conference on Advances in Computing, Communication Control and Networking (ICACCCN2018)

TABLE II Power dissipation, delay and PDP of ECRL Sleepy Keeper Carry
Circuit
Supply Power Delay Power
voltage Dissipation (ns) delay
(V) (pW) product
(PDP)*10-
21

1.8 143.614 197.00 28.17

1.6 109.743 99.388 10.82
1.4 81.727 49.618 4.01
1.2 58.869 99.398 5.75
1.0 40.556 99.441 3.96

Fig. 6. ECRL sleepy keeper approach carry circuit

The feasibility of operation of full adder is verified for various

combinations of inputs. Let us consider all the inputs
(A=B=C=1) are at logic high then “OUTB = 1” that is logic
high and “OUT = 0”, energy is consumed during this phase.
When all the inputs (A=B=C=0) are at logic low then “OUTB
= 0” that is logic low and “OUT = 1”, energy is recovered and
will be reused for the next cycle.

III. RESULTS AND DISCUSSION

Fig. 7. Input and output waveforms of ECRL sleepy keeper sum circuit
Table I and table II demonstrated outcomes for power
dissipation, delay of sum and carry circuit and power delay
product (PDP) of proposed ECRL Sleepy Keeper full adder
Sum and carry circuits. Simulations have been performed
utilizing all the possible input combinations. Input and output
waveform has been depicted in Fig. 7 and Fig. 8 respectively.
Circuit of adder is simulated in Mentor graphics using CMOS
0.18µm technology with supply voltage of [1.8 - 1] V. Power
of full adder sum circuit varies from [129.819 – 37.126] pW
with variety of supply voltage [1.8 – 1] V. Delay shows a
variation of [135.97 – 136.74] ns and power delay product
(PDP) shows variation of [17.53 – 5.05] *10-21 J. Power of
full adder carry circuit varies from [143.614 – 40.556] pW
with variety of supply voltage [1.8 – 1] V. Delay shows a Fig. 8. Input and output waveforms of ECRL sleepy keeper carry circuit
variation of [197.00 – 99.441] ns and power delay product
(PDP) varies from [28.17 – 3.96]*10-21 J. Table III demonstrates the Power dissipation, delay and power
delay product (PDP) of conventional Complementary MOS
TABLE I Power dissipation, delay and PDP of ECRL Sleepy Keeper Sum
Circuit full adder. Results have been obtained in Mentor Graphics
Supply Power Delay Power with same input pattern as for proposed full adder circuit. The
voltage Dissipation (ns) delay input and output waveforms of conventional CMOS full adder
(V) (pW) product are shown in Fig. 9. Power dissipation of CMOS full adder
(PDP)*10- varies from [260.355 – 85.446] pW with variety of supply
21 voltage [1.8 – 1] V. Delay and power delay product (PDP)
1.8 129.819 135.97 17.53 varies from [149.92 – 149.87] ns and [39.03 – 12.80]*10-21 J
1.6 99.433 136.48 13.50 respectively.
1.4 74.304 106.25 7.85
1.2 53.664 136.83 7.25
1.0 37.126 136.74 5.05

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1.2 95.795 149.86 99.862 14.24

1.0 68.325 149.82 99.821 10.18
TABLE III Power dissipation, delay and PDP of CMOS Full adder

Supply Power Delay of Delay Power

voltage Dissipation Sum of delay
(V) (pW) circuit Carry product
(ns) circuit (PDP)
(ns) *10-21
1.8 260.355 149.92 49.886 39.032
1.6 205.731 149.92 49.892 30.843
1.4 158.728 149.91 49.891 23.794
1.2 118.843 149.90 49.889 17.814
1.0 85.446 149.87 49.885 12.805

Fig. 10. Input and output waveforms of CMOS Sleepy Keeper Full Adder

Table V and table VI shows the Power dissipation, delay and

Fig. 9. Input and output waveforms of conventional CMOS full adder
power delay product (PDP) of ECRL Full Adder circuit.
Results have been obtained with same input pattern as for
proposed adder circuit. The input and output waveforms of
ECRL sum and carry circuit are shown in Fig. 11 and Fig. 12
respectively. Power dissipation of ECRL sum circuit varies
from [149.604 – 43.750] pW supply voltage [1.8 – 1] V. Delay
and power delay product varies from [149.69 – 134.66] ns and
[21.34 – 5.89]*10-21 J respectively.
Power dissipation of ECRL carry circuit varies from [170.758
– 49.420] pW with variation of supply voltage [1.8 – 1] V.
Delay and power delay product varies from [97.375 – 75.188]
ns and [166.26 – 37.15]*10-21 J respectively.

Table IV shows the Power dissipation, delay of sum and carry

TABLE V Power dissipation, delay and PDP of ECRL Sum Circuit
circuit and power delay product (PDP) of CMOS sleepy
keeper Full Adder. Simulations have been performed in
Supply Power Delay Power
Mentor graphics with same input pattern as for proposed adder
voltage dissipation (ns) delay
circuit. The input and output waveforms of CMOS sleepy
(V) (pW) product
keeper are shown in Fig. 10. CMOS sleepy keeper power
(PDP) *10-
consumption varies from [213.688 – 68.325] pW supply 21
voltage [1.8 – 1] V. Delay and power delay product (PDP)
1.8 149.604 142.69 21.34
varies from [149.88 – 149.82] ns and [31.90 – 10.18]*10-21 J
1.6 115.040 136.94 15.75
respectively.
1.4 86.296 134.85 11.63
TABLE IV Power dissipation, delay and PDP of CMOS Sleepy Keeper Full 1.2 62.735 134.75 8.45
adder 1.0 43.750 134.66 5.89

Supply Power Delay of Delay of Power

voltage dissipation Sum Carry delay TABLE VI Power dissipation, delay and PDP of ECRL Carry circuit
(V) (pW) circuit circuit product
Supply Power Delay Power
(ns) (ns) (PDP)
voltage dissipation (ns) delay
*10-21
(V) (pW) product
1.8 213.688 149.88 99.808 31.90
(PDP) *10-
1.6 167.909 149.89 99.785 25.01 21
1.4 128.811 149.88 99.746 19.17 1.8 170.758 97.375 166.26

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1.6 131.130 97.359 127.66

1.4 98.190 75.319 73.95 300 Conventional

Power dissipation (pW)

1.2 71.238 75.299 53.64 250 CMOS
1.0 49.420 75.188 37.15
200 CMOS Sleepy
keeper
150
100 ECRL

50
ECRL Sleepy
0 keeper
1.8 1.6 1.4 1.2 1
Supply voltage (V)
Fig. 13. Power dissipation variation of adders with supply voltage

45 Convention
40 al CMOS

Power delay product

35

(PDP)*10-21 J
30 CMOS
25 Sleepy
20 keeper
Fig. 11. Input and output waveforms of ECRL Sum circuit 15 ECRL
10
5
0 ECRL Sleepy
1.8 1.6 1.4 1.2 1 keeper
Supply voltage (V)

Fig. 14. Power delay product (PDP) variation of adder with supply voltage

Fig. 12. Input and output waveforms of ECRL Carry circuit
Fig. 13 demonstrates the power dissipation variation with
supply voltage of all the full adders design and proposed
ECRL sleepy keeper full adder. ECRL sleepy keeper full
adder has the minimum power dissipation among all other
designed full adder. Fig. 14 shows the graph of power delay
product (PDP) with supply voltage of all the simulated full
adders and proposed adder. Proposed ECRL Sleepy keeper
full adder shows minimum power delay product (PDP) among
all other adders.
IV. CONCLUSION
A new design technique, energy efficient charge recovery
(ECRL) with sleepy keeper for low power full adder has been
introduced in this paper. ECRL with Sleepy Keeper Full
Adder design has been simulated using 0.18µm CMOS
technology in Mentor Graphics. Proposed circuit has power
dissipation of 129.819 pW with delay of 135.97 ns. Power
delay product (PDP) of proposed full adder circuit has been
calculated. Among all the different techniques reported in this
paper, power and power delay product (PDP) of proposed full
adder circuit is least.
References
[1] Prolay Ghosh, Tanusree Saha and Barsha Kumari,
“Aspects of low power high speed CMOS VLSI design: A
review,” in S.bhattacharyya, Industry interactive innovations
in science, engineering and technology, pp. 385-394, 2018.
[2] Sung-Mo Kang and Yusuf Leblebici, CMOS Digital
Integrated Circuits—Analysis and Design, McGraw-Hill,
2003.
[3] W.C. Athas, J.G. Koller, L. Svensson, “An Energy-
Efficient CMOS Line Driver using Adiabatic Switching,”

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Fourth Great Lakes symposium on VLSI, California, pp. 1-16,

March 2005.
[4] J.Fischer, E. Amirante, A.B. Stoffi, and D.S. Landsiedel,
“Improving the positive feedback adiabatic logic family,” in
Advances in Radio Science, pp. 503-506, 2004.
[5]A. Blotti, M. Castellucci, and R. Saletti, “Designing Carry
Look-Ahead Adders with an Adiabatic Logic Standard-cell
Library,” PATMOS, pp. 118-127, 2002.
[6] M. Alioto and G. Palumbo, "Analysis and comparison on
full adder block in submicron technology," in IEEE
Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 10, no. 6, pp. 806-823, Dec. 2002.
[7] Nazrul Anuar, Yasuhiro Takahashi, and Toshikazu Sekine,
“Two Phase Clocked Adiabatic Static CMOS Logic and its
Logic Family,” Journal of Semiconductor Technology and
Science, vol. 10, no. 1, 2010.
[8] A. K. Bakshi and M. Sharma, "Design of basic gates using
ECRL and PFAL," 2013 International Conference on
Advances in Computing, Communications and Informatics
(ICACCI), Mysore, 2013, pp. 580-585.
[9] Teichmann, Phillip “Adiabatic Logic, Future Trend and
System Level Perspective,” XVII, 166p, Springer, 2012. [10]
Yong Moon and Deog-kyoon Jeong, “An efficient charge
Recovery Logic Circuit,” IEEE JSSC, vol. 31, no. 04, pp. 514-
522, April 1996.
[11] Md. Asif Jahangir Chowdhury, Rizwan, Islam, “An
efficient VLSI design approach to reduce static power using
variable body biasing,” World Academy of Science,
Engineering and Technology, pp. 263-267, 2012.
[12] Manoj Kumar, Sujata Pandey and Sandeep K. Arya,
“Design of CMOS Energy Efficient Single Bit Full Adder,”
International conference on high performance and Grid
Computing, pp. 159-168, Jul. 2011.
[13] Manoj Kumar, Sujata Pandey and Sandeep K. Arya, “A
new low power single bit full adder design with 14 transistors
using novel 3 transistor XOR gate.” International Journal of
Modeling and Optimization, vol. 2, no. 4, pp. 544-548, August
2012.
[14] S. H. Kim and V. J. Mooney, "Sleepy Keeper: a New
Approach to Low-leakage Power VLSI Design," IFIP
International Conference on Very Large Scale Integration,
Nice, 2006, pp. 367-372.
[15] Y.Sunil, Gavaskar Reddy, V.V.G.S.Rajendra Prasad,
“Power Comparison of CMOS and Adiabatic Full Adder
Circuits,” International Journal of VLSI design &
Communication Systems (VLICS) vol.2, no.3, September
2011.
[16] Minakshi Sanadhya, M.Vinoth Kumar, “Recent
development in efficient adiabatic logic circuits and power
analysis with CMOS logic,” Proc. Computer Science, vol. 57,
pp. 1299-1307, 2015.
[17] Manoj Kumar, Sandeep K. Arya and Sujata Pandey,
“Low Power CMOS full adder design with body biasing
approach,” Journal of Integrated Circuits and Systems, Brazil,
Vol.6, no. 1, pp. 75-80, March 2011.

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