Electronic Devices and Integrated Circuits, 2nd Edition PDF

ELECTRONIC DEVICES
AND
INTEGRATED CIRCUITS
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ELECTRONIC DEVICES
AND
INTEGRATED CIRCUITS
B. P. Singh
Professor
Department of Electronics and Communication Engineering
Madan Mohan Malaviya Engineering College
Gorakhpur, Uttar Pradesh
India
Rekha Singh
Group Leader
Delphi Automotive
Michigan, USA.
To
the sweet and sacred memory
of
our parents
Preface
The wealth of the natural sciences no longer consists in the
abundance of facts, but in the way they are linked together.
Alexander Von Humboldt
Electronic Devices and Integrated Circuits enters a market in which there is no dearth of books on the
same subject. The natural question, then, is why write another?
Each person views problems differently, emphasizing different aspects and describing them in unique
styles. A student, very often, finds certain books more helpful than others. I believe in having a variety
of presentations from which the most appropriate, for every individual case, can be chosen. Such
variety also allows students to appreciate the diversity and scope present in the field of study.
This book has evolved from the class notes prepared for teaching students of undergraduate courses
in electronic devices and integrated circuits at institutions such as the Birla Institute of Technology,
Mesra, Ranchi; the Indian School of Mines, Dhanbad; Regional Engineering College, Silchar (Assam);
and M.M.M. Engineering College, Gorakhpur. Apart from B.E./B. Tech. students, this book can also be
used by students prepearing for A.M.I.E., GATE, U.P.S.C. and other competitive examinations.
Electronic Devices and Integrated Circuits emphasizes the basic working principles of semiconduc-
tor devices and circuits. A large number of Integrated-Circuits (ICs), both analog and digital, are avail-
able in todays commercial market. Various circuits can be configured with ICs using manufacturers
data sheets and application notes. Therefore, a thorough understanding of the operation and properties
of the devices and circuits inside a package is all the more important for the intelligent interfacing of
these devices and the development of more efficient future generation circuits. Keeping this point in
view, this book has been developed to start right from the basic principles of the atomic model of solids
and move to its zenith in the development of electronics so far.
Every effort has been made to present the text in an easy flow for readers. Fundamental concepts
have been illustrated by physical examples. A larger number of solved problems have been included at
the end of each section and chapter to help students absorb concepts and formulae. Apart from this, a
number of objective questions and answers have also been included at the end of each chapter to infuse
confidence in the subject matter among readers.
Preface
LEEE
In spite of my best efforts, it is possible that errors of omission and commission might have crept in.
I shall thankfully acknowledge any mistakes pointed out and welcome suggestions to enrich the contents
of the book.
B. P. SINGH
Acknowledgements
Since a husband and wife, in our society, are so often considered one inseparable unit, expressing
gratitude publicly to ones wife is almost unheard of. But if that is the case, this book is as much my
wifes work as mine and hence I owe a deep sense of appreciation to her Smt. Bimla Singh. I also
thank my children and grandchildren for their support during the preparation of the manuscript. So
thank you Upendra & Rita, Rita & Sanjay, Renu & Ashok, Rajesh, Kaushik, Kinshuk, Honey, Happy,
Rishan, Rachit, and Rishav.
I thank my student Anirban Nandy for helping me with the proofs of the manuscript.
I thankfully acknowledge the contributions of various authors of different books, magazines, data
manuals, journals etc. from where materials have been collected to enrich the contents of the book.
B. P. SINGH
I thankfully acknowledge the help and cooperation of my husband Mr. Rajesh Singh. I would also
like to thank my children (Rishan and Rachit) and my in-laws for sparing me from the daily routine of
work so I could prepare the text of the book.
REKHA S INGH
Contents
1. Physics of Semiconductors 1
1.1 Introduction 1
1.2 Current Flow and Concept of Holes 5
1.3 Free CarriersExcitation and Doping 6
1.4 Intrinsic and Extrinsic Semiconductor 7
1.5 Tetravalent Elements 10
1.6 Effect of Temperature on Intrinsic Conductivity 12
1.7 Conduction of Current 13
1.8 Extrinsic Semiconductor 18
1.9 Energy Distribution 24
1.10 Electron Emission from Metal 27
1.11 Carrier Concentration in Intrinsic Semiconductor 30
1.12 Fermi Level in Intrinsic Semiconductor 34
1.13 Fermi Level in Extrinsic Semiconductor 36
1.14 Hall Effect 38
Solved Problems 39
Questions for Practice 47
Multiple Choice Questions 49
Answers to Multiple Choice Questions 56
2. Physical Phenomenon in Homojunction 57

2.1 Introduction 57
2.2 Qualitative Analysis of Homojunction 59
2.3 Biasing of Homojunction 61
2.4 Quantitative Analysis of Homojunction 63
2.5 Depletion Width across Homojunction 66
Contents
N
2.6 Depletion/Transition Layer Capacitance Across Homojunction 72

2.7 Continuity Equation 74
2.8 Graded Homojunction 80
2.9 Types of Diodes 82
2.10 Types of Homojunctions 91
2.11 Heterojunction 93
Solved Problems 99
3. Diode as Circuit Element 107

3.1 Introduction 107
3.2 Forward Bias Characteristic 107
3.3 Reverse Bias Characteristic 110
3.4 Equivalent Circuit of Semiconductor Diode 110
3.5 Load Line Analysis of Diode 113
3.6 Use of Zener Diode 115
3.7 Clamper 117
Solved Problems 118
4. Junction Diode Rectifier 136

4.2 Half-wave Rectifier 136
4.3 Full-wave Rectifier 142
4.4 Bridge Rectifier 146
4.5 Transformer Utilization Factor 147
4.6 Passive Filter 149
4.7 Voltage Multiplier 158
4.8 Voltage Regulation 160
Solved Problems 161
5. Physical Phenomenon in BJT 171

5.2 Physical Structure 172
5.3 Operation of BJT 173
5.4 Transport Phenomenon 174
Contents
NE
5.5 DC Equivalent Circuit 177

5.6 Static Characteristics of BJT 178
5.7 Common-emitter (CE) Configuration 181
5.8 DC Load Line 184
5.9 Ebers-Moll Model 186
5.10 Charge Control Model of BJT 189
5.11 Approximate Analysis of Current Flow in BJT 195
Solved Problems 198
6. Physical Phenomenon in JFET and MOSFET 215

6.2 Fabrication 217
6.3 Operation of JFET with Small VDS 217
6.4 Operation Beyond Linear Range 218
6.5 Operation of JFET with Small VDS and VGS = V1 220
6.6 Derivation of ID 220
6.7 Transfer Characteristics 227
6.8 FET Parameters 228
6.9 MOSFET Construction 230
6.10 Derivation of MOSFET Drain Current 235
6.11 MOSFET Inverter 239
6.12 pMOSFET 242
6.13 MESFET (GaAs device) 243
6.14 CMOS 247
Solved Problems 249
7. Biasing 261
7.2 Fixed Base Bias 264
7.3 Self Bias 267
7.4 Voltage Divider Emitter Bias 277
7.5 Effect of Bypass Capacitors on Biasing 280
7.6 Stability Factor Analysis 281
7.7 Diode Compensation 284
7.8 IC Biasing 287
Solved Problems 300
Contents
NEE

8. BJT Amplifiers 313

8.2 Qualitative Comparison of BJT Configurations 316
8.3 Current Amplification Factor 317
8.4 Physical Explanation for ICBO and I CEO 318
8.5 BJT Ratings 319
8.6 Input Resistance 320
8.7 Output Resistance 322
8.8 Voltage Gain 323
8.9 Power Gain 324
8.10 Why is CE Widely Used ? 325
8.11 Small Signal Model of BJT 327
8.12 CE Amplifier 333
8.13 CB Amplifier 336
8.14 CC Amplifier 339
8.15 BJT Phase Splitter 342
8.16 Darlington Configuration 346
8.17 Bootstrap Amplifier 350
Solved Problems 353
9. FET Amplifiers 366

9.2 Common Source (CS) Amplifier 367
9.3 FET Phase-Splitter 369
9.4 Common Drain Amplifier 370
9.5 Common Gate Amplifier 372
9.6 High frequency model 373
9.7 Frequency Response of CS Amplifier 376
9.8 Frequency Response of CD Amplifier 380
9.9 Common Gate Amplifier 385
9.10 BiCMOS 394
Solved Problems 398
Contents
NEEE
10. Frequency Response of BJT Amplifiers 421

10.2 RC Coupled Amplifier Analysis 426
10.3 Factors Affecting Frequency Response 426
10.4 Low-pass High-cut RC Circuit 428
10.5 High-pass Low-cut RC Circuit 429
10.6 Hybrid-p Model of BJT 430
10.7 Effect of Bypass Capacitor in CE 449
Solved Problems 451
11. Multistage Amplifiers 472

11.2 Decibel 473
11.3 CE-CE Cascaded Stages 478
11.4 CE-CC Cascade Stage 480
11.5 Cascode Amplifier 482
11.6 Differential Amplifier 483
11.7 Balancing Differential Amplifier 491
11.8 Long Tail Differential Amplifier 492
11.9 Emitter Coupled Differential Amplifier 495
11.10 CS-CB Amplifier 497
11.11 CS-CE Amplifier 498
11.12 CS-CE (Emitter Coupled) Amplifier 499
11.13 FET-BJT Darlington 500
11.14 FET-BJT Cascode Amplifier 501
11.15. CS Differential Amplifier 503
11.16. FET-BJT Coupled Amplifier 505
Solved Problems 507
12. Feedback in Amplifiers 514

12.2 Classification of Feedback 519
12.3 Practical Circuit of Voltage Series Feedback 526
Solved Problems 534
Contents
NEL
13. Oscillators 560

13.2 RC Oscillators 563
13.3 Weinbridge Oscillator 568
13.4 Radio Frequency Oscillators 572
13.5 Crystal Oscillators 580
13.6 Unijunction Transistor (UJT) 584
Solved Problems 592
Questions For Practice 599
Multiple Choice Question 600
14. Power Amplifiers 605

14.2 Classification of Power Amplifier 606
14.3 How Do Power Amplifiers Differ from Voltage Amplifiers? 609
14.4 Single-ended Transformer Coupled Stage 617
14.5 Integrated Circuit Class A Amplifier 619
14.6 Double-ended Amplifier 623
14.7 Class B Push-pull 627
14.8 Complementary Symmetry Output Stage 631
14.9 Class AB Push-pull Stage 635
14.10 Biasing of Class AB Circuit 637
14.11 Power Transistors 639
Solved Problems 641
15. Operational Amplifier 652

15.2 Ideal Characteristics of Operational Amplifier 660
15.3 Frequency Response of Op-amp 662
15.4 Offset Voltage 668
15.5 Inverting Op-amp Circuit 668
15.6 Summing Op-amp Circuit 670
15.7 Op-amp Integrator and Differentiator 673
15.8 Nonlinear Applications of Op-amps 679
15.9 Precision Rectifier 700
15.10 Square Waveform Generation 704
15.11 Analog Multiplier 708
15.12 Filters 712
Contents
NL
15.13 Simulated Inductance Approach 729

15.14 DVCVS/DVCCS 743
15.15 BiFET and BiMOS Circuits 747
15.16 Analog Computer 747
Solved Problems 760
16. Regulated Power Supplies 786

16.2 Classification of Voltage Regulators 789
16.3 Series Voltage Regulator 793
16.4 Shunt Regulator 797
16.5 Current Limiting Techniques 799
16.6 Linear Voltage Regulators : First Generation 802
16.7 Dual IC Power Supply 814
16.8 Switched Mode Power Supply 815
16.9 Step-up Switching Regulator 821
Solved Problems 826
17. Integrated Circuit Timers 833

17.2 Monostable Multivibrator Using 555 837
17.3 Astable Multivibrator using 555 842
17.4 VCO With 555 849
17.5 Phase Lock Loop (PLL) 850
Solved Problems 857
18. Special Two Terminal Devices 864

18.2 Light Dependent Resistance (LDR) 864
18.3 Phototransistor 875
18.4 Photovoltaic Cell 876
18.5 IR Emitter 878
18.6 Solar Cell 878
18.7 Light Emitting Diodes (LEDs) 884
18.8 LED Fabrication 900
18.9 Liquid Crystal Displays (LCDs) 904
Contents
NLE

19. Tuned Amplifier 910

19.2 Single Tuned Amplifier 914
19.3 Input Side Single Tuned Amplifier 914
19.4 Impedance Transformation 919
19.5 Output Side Single Tuned Amplifier 920
19.6 Multistage Tuned Amplifier 924
19.7 Integrated Circuit Tuned Amplifier 926
Solved Problems 926
Bibliograbhy 937
Index 938
1
Physics of Semiconductors
1.1 Introduction
An understanding of the electrical properties of semiconductors is a prerequisite to the study of electronic
devices, both bipolar and Metal Oxide Semiconductor (MOS). This chapter explains the electrical behaviour
of a semiconductor.
Materials are grouped under the following three categories depending on their ability to conduct
electricity:
∑ Conductors (silver, copper, aluminum, etc.)
∑ Semiconductors (germanium, silicon, aluminum-galium-arsenide, etc.)
∑ Insulators (glass, ceramic, bakelite, rubber, air, element sulphur).
1.1.1 Conductors
Metals such as silver, copper, aluminum, etc. that contain free electrons which are responsible for
electrical conduction through them are called conductors. The number of available free electrons
determines the amount of conduction of electric current through it. If the proportion of free electrons in
a material is high, the material conducts large current. They offer very low resistance (< 108 Wm ) to
electric current flow.
1.1.2 Insulators
Solids in which valence electrons are very tightly bound to the nucleus of the parent atom and require a
very large electric field to remove them from the force of attraction of the nucleus are called insulators.
Materials like glass, ceramic, quartz, bakelite, rubber, air and the element sulphur are insulators having
high resistance (> 1010 Wm). They are poor conductors of electricity.
Electronic Devices and Integrated Circuits
1.1.3 Semiconductors
Solids having conductivity between metals and insulators are called semiconductors. Materials such as
germanium and silicon neither offer high resistance as insulators nor offer low resistance like conductors
(metals). Their resistivity is approximately 102 Wm. Some important semiconductors are silicon (Si),
germanium (Ge), gallium-arsenide (GaAs), zinc-selenide (ZnSe) and alloys such as aluminum-gallium-
arsenide (AlxGa1xAs). However, silicon-based semiconductors totally dominate the present commercial
market due to their advanced manufacturing technology. Silicon is the second most abundant element in
the earths crust. It is never found in a pure single-crystal form. It has to be extracted from impure
SiO2. The rotating electrons around the nucleus in the outermost orbit are called valence electrons. The
four small lines around the periphery of the circle inscribed Si (Fig. 1.1) represent the valence electrons
in the outer-most orbit of the tetravalent elements (Si/ Ge/ Sn/C).
Figure 1.1 Representation of tetravalent element Si
1.1.4 Energy Band

An isolated atom has distinct energy levels represented by its orbit as indicated in Fig. 1.2. All isolated
atoms of the same element have the same energy level as indicated in Fig. 1.3. As atoms get close
enough to interact, the outermost orbit interacts first as demonstrated in Fig. 1.4.
As per Paulis exclusion principle, no two electrons can have all four quantum numbers equal. Thus,
when two identical atoms are brought closer, their electrons in two different orbits with equal four
quantum numbers align themselves with different energy levels as shown in Fig. 1.4. In other words,
equal energy levels of the interacting electrons split. For example, atom-1 and atom-2 of the same
element are brought closer. The energy level E11 of atom-1 and energy level E21 of atom-2 interact first
resulting in either shifting of the energy level E11 up or down with respect to E21 as illustrated in Fig. 1.4.
Thus, a gap is created between the same energy levels of two identical isolated atoms of the same
element if they are close enough to interact.
Figure 1.2 Two isolated atomic orbits

!
Figure 1.3 Energy levels in two isolated atoms
Figure 1.4 Shifting of energy level
Thus, one energy level splits into N-levels when N-atoms are brought together, and these N-levels
F 1 I
can accommodate at most 2 N - electrons due to spin degeneracy ± spin . Fig. 1.5 shows a Si atom
H 2 K
having four-electrons in its outermost orbit. When atoms are brought close together their valence electrons
get shared and form bonds between the two atoms called covalent bonds. This type of diamond crystal
lattice bonding can be seen in the silicon semiconductor as shown in Fig. 1.6. It is interesting to analyze
energy-related aspects rather than spatial aspects such as bonds. Therefore, the concept of energy
bands is used to describe the semiconductors.
Figure 1.5 Silicon atom with orbits and available states

"
Figure 1.6 Covalent bonding of tetravalent element
Remember, N is a huge number! Now, since the separation between the energy levels within the band
is much smaller than the thermal energy possessed by an electron at room temperature, the band can be
viewed as continuous. The energy EC is the lowest possible conduction band energy, while the energy
EV is the highest possible valence band energy as depicted in Figs. 1.7 and 1.8. The bandgap energy EG,
is defined as EC EV. The energy gap EG is the energy it takes to break a bond in the spatial view of the
crystal. The bandgap energies for some semiconductors at room temperature T = 27°C + 273 = 300 K
are, EG = 1.42 eV in GaAs and 1.12 eV in Si. We known that 1 eV = 1.602 ¥ 1019 J. The typical energy
band diagram of insulators, semiconductors and metals is shown in Fig. 1.8. The bandgap in insulators
is very high, i.e. of the order of 8 eV, whereas bandgap in the case of metals is either very low or valence
and conduction bands overlap.
Figure 1.7 Energy band due to huge number of atoms close together
Figure 1.8 Energy band diagram of insulators, semiconductors, and metals

#
It is evident from Fig. 1.8 that the forbidden band is very large, i.e. 8 eV in case of insulators, a
moderate 1.1 eV in case of semiconductors, and overlapping valence and conduction bands in case of
metals. As the energy bandgap between the valence band and the conduction band is very large in the
case of insulators, almost no free electrons will be available in the conduction band for conduction of
current. As the energy gap between the valence band and the conduction band is low, the probability
exists that some electrons will be lifted to the conduction band and will become free for conduction of
current in semiconductors. In metals there is no forbidden energy gap between the valence and conduction
bands and an enormous amount of free electrons are available for the conduction of current without any
external supply of energy.
1.2 Current Flow and Concept of Holes

Using the concept of energy bands, the pure semiconductor (ideally, T = 0 K) contains a completely
filled (with electrons) valence band and a completely empty conduction band. Completely filled bands
have plenty of electrons but do not contribute to the conductivity of the material. This is due to the fact
that the electrons cannot gain energy since all energy levels are already filled. As semiconductors are of
primary interest in this text, we now introduce a simplified energy band diagram for semiconductors
and define some key parameters. The diagram is shown in Fig. 1.9. The band diagram includes bandgap
(EG), Fermi level (EF), work function (fW), and electron affinity (c). The work function of a
semiconductor is defined as the energy required in removing an electron from Fermi level EF to a
position just outside the material (vacuum). Similarly, electron affinity is the energy required in removing
an electron from the bottom of the conduction band EC to the vacuum level.
Figure 1.9 Simplified energy band diagram to describe semiconductor
The band diagram identifies the almost-empty conduction band represented simply by a line that
indicates the bottom of the conduction band and is labeled as EC. Similarly, the top of the valence band
is indicated with a line labeled EV. It is important to note that the actual bandstructures of semiconductors
is more complex than the reader is led to believe by the discussion. So, semiconductors distinguish
themselves from metals and insulators by the fact that they contain almost-empty conduction band
and almost-full valence band. This also means that we will have to deal with the transport of carriers
in both bands.
$
To facilitate the discussion of the transport in the almost-full valence band we will introduce the
concept of holes in a semiconductor. It is important for the reader to understand that one could deal
with only electrons (since these are the only real particles available in a semiconductor) if one is willing
to keep track of all the electrons in the almost-full valence band.
The concept of holes is introduced based on the notion that it is easier to keep track of the missing
particles in almost-full band, rather than keeping track of the actual electrons in that band. We will first
explain the concept of a hole and then point out how the hole concept simplifies the analysis.
Holes are missing electrons. They have the same properties as the electrons occupying the same
states would have, except that they carry an equal and opposite charge, i.e. positive charge.
In the absence of an electric field no current can flow, i.e. there are no electrons at all in the conduction
band and no holes in the valence band to which electrons inside this band can move. A hole is now
defined as an empty state in the valence band. The holes move in the direction of the field (since they are
positively charged particles).
1.3 Free Carriers—Excitation and Doping

If there exist free electrons or holes (so-called charge carriers) charge transport can occur and current
can flow. If a semiconductor is excited by energy in the form of light, temperature or electric fields,
electrons in the valence band can jump to the conduction band and take part in current flow. This way
a covalent bond is broken and electrons move to the conduction band whereas the holes move to the
valence band as indicated in Fig. 1.10. This process is known as electron-hole pair generation or sometimes,
intrinsic generation. Another way to create (almost) free charge carriers is to contaminate a material
with impurities that occupy lattice sites in place of the atoms of the pure semiconductors. This is called
doping. The amount of doping, the doping density or concentration is usually given as impurities/cm3.
1.3.1 Doping
If pure Si is doped with atoms from group V, they have one more valence electron. The ND impurity
atoms are called donors. Since four of the valence electrons from the impurity atom are enough to
create the covalent bond, its fifth electron is almost free to move around. However, the fifth electron is
weakly bound to the impurity atom by the excess positive charge of the nucleus and thus, it needs a
small amount of energy to become fully free. When it becomes free, only this carrier is created and the
positively charged dopant ion cannot move. A donor-doped material where there are more electrons
than holes, is called an n-type material.
Figure 1.10 Thermal excitation of a semiconductor doped with donor

%
Instead, if pure Si is doped with atoms from group III, i.e. they have one less valence electron, the Na
impurity atoms are called acceptors. Since there are only three valence electrons in the impurity atom
instead of the four needed to create the covalent bond, the fourth electron has to be borrowed from a
nearby bond and in this way a hole is created. Thus, a hole is almost free to move around. Similar to the
case of the donor impurity, only a small amount of energy is needed to lift the electron from the valence
band into the energy level of the vacant bond, but when it becomes free only this carrier has been
created, the negatively charged acceptor ion cannot move.
An acceptor-doped material where there are more holes than electrons is called a p-type material. The
majority carrier is the most abundant carrier in a given semiconductor sample; electrons in n-type and
holes in p-type materials. Similarly, the minority carrier is the least abundant carrier in a given semiconductor
sample, holes in n-type materials and electrons in p-type materials.
1.4 Intrinsic and Extrinsic Semiconductor

A semiconductor material with no impurities added is called an intrinsic (pure) semiconductor. In this
material the number of electrons in the conduction band must equal the number of holes in the valence
band. This is due to the fact that the electron in the conduction band has been excited and has left a
vacant state, a hole, in the valence band (electron-hole pair generation). We usually refer to the density
of electrons and holes in the intrinsic semiconductor as ni and pi respectively, and give these values as
carriers/cm3. It is important to remember that ni and pi, depend strongly on temperature since these
densities are due to electron-hole pair generation. A sample of pure silicon (Si) or germanium (Ge), by
dynamic equilibrium, has intrinsic concentration n = p that increases rapidly with increase in temperature.
The widely accepted expression for ni (T) is
- E go /( 2 kT )/ q
ni (T ) = 3 . 86 ¥ 10 16 ¥ T 3/ 2 e
where T is in Kelvin, K = 1.38 ¥ 1023 Joules/K is Boltzmanns constant and Ego = 1.21 (a physical
constant) for silicon.
At 300 K (27°C), ni @ 1.41 ¥ 1010/cm3 (practically it is assumed as 1.5 ¥ 1010/cm3).
At 398 K (125°C), ni @ 6.80 ¥ 1012/cm3.
Typical values of ni are 2 ¥ 106/cm3 in GaAS, 1.5 ¥ 1010/cm3 in Si and 2.5 ¥ 1013/cm3 in Ge at room
temperature i.e. T = 27 + 273 = 300 K. Comparing Si with 5 ¥ 1022 atoms/cm3 and four bonds (valence
electrons) per atom yield a total of 5 ¥ 1022 ¥ 4 = 2 ¥ 1023 valence electrons/cm3. With an ni of 1.5 ¥
1010/cm3 (2 ¥ 1023/1.5 ¥ 1010 = 1.33 ¥ 1013), less than one (1/1.33 = 0.75) bond in 1013 is broken in Si
at room temperature. When impurities are added, by doping, to a semiconductor it is said to be an
extrinsic semiconductor. At equilibrium the extrinsic semiconductor is said to have carrier concentra-
tions n0 and p0, both different from ni. At T = 0 K, n0 = p0 = ni = 0. This exceptional state is sometimes
called freeze-out.
We know that at room temperature pure silicon and germanium behave as insulators. Thus, the
manufacturing material to be used in semiconductor devices must be modified electrically to produce
enough charge carriers (electrons or holes). The crystalline piece of semiconductor is doped (doping is
the process of making a pure material impure) with atoms of neighbouring group of elements. Generally,
the pure crystalline structure has poor current carrying capabilities. A very small amount of impurity
(1:1013 impurity/ host) is added with an atomic structure that is different than that of the host atom to
&
obtain free charge carriers (electrons or holes). This impurity will modify the crystal lattice so that
current carriers are developed. Usually the amount of impurities added are in a very small proportion to
that of the host, but even this small amount is sufficient to unbalance the number of holes and electrons
in the host materials.
A hole is just the opposite of an electron. It is defined as the vacancy of an electron. Thus, hole is also
a charge carrier. We now can consider a hole as an electric positive charge carrier, equal but opposite to
that of the electron. There are two main classes of impurities (dopants).
These are:
∑ Acceptor
∑ Donor
The acceptor atom when mixed as impurity accepts electrons and creates holes. A semiconductor
material made after adding the acceptor atoms is called p-type material. Similarly, each donor atom
donates one free electron. A semiconductor material made after adding the donor impurity is called
n-type material. The conductivity and resistivity of some conductors, semiconductors, and insulators
are shown in Fig. 1.11.
Figure 1.11 Resistivity and conductivity of some conductors, semiconductors, and insulators
The conductivities of a few commonly used conductors, semiconductors and insulators are shown
in Table 1.1.
Table 1.1 Classification of materials based on conductivity, resistivity, and bandgap
Material Conductivity(S/m) Resistivities Bandgap Classification

(W m)
Silver 6.25 ¥ 107 1.6 ¥ 108
Copper 5.88 ¥ 107 1.7 ¥ 108 Overlaps Conductors
Aluminium 3.82 ¥ 107 2.7 ¥ 108
Germanium 1.5 0.60 0.7 eV Semiconductors
Silicon 5 ¥ 104 2 ¥ 10 3 1.2 eV
Porcelain 3.33 ¥ 1010 3 ¥ 109
Glass 5.88 ¥ 1012 1.7 ¥ 1011 Very large Insulators
Hard Rubber 1016 1016
On one hand, good conductors have high conductivity while, on the other, good insulators have high
resistivity. The word semiconductor is broken as semi + conductor. Semi means half and conductor
means metal. Thus, semiconductor is a material whose behaviour is halfway between that of metals and
insulators. So its conductivity and the resistance falls halfway between a metal and an insulator. The
semiconductor family can be represented as shown in Fig. 1.12.
'
Figure 1.12
The Ge/Si element lies in the fourth group of the periodic table and hence is known as a tetravalent
element lies with four valence electrons in the outermost orbit. These valence electrons are responsible
for the chemical behaviour of the elements. There is a general tendency of an element to enter into
chemical reaction in such a way as to acquire a stable state. According to the rule of octet, the most
stable state of matter contains eight electrons in the outermost orbit. Hence, each atom of Si/Ge crystal
has eight electrons, four of its own and the rest four shared with neighbouring atoms in its outermost
orbit. Useful assorted semiconductor elements are shown in Table 1.2 with their atomic numbers and
weights.
Table 1.2 Periodic table of useful materials

III-group IV-group V-group
5 Boron (B) 6 Carbon (C) 7 Nitrogen (N)
10.82 12.01 14.008
13 Aluminum (Al) 14 Silicon (Si) 15 Phosphorus (P)
26.97 28.09 31.02
31 Gallium (Ga) 32 Germanium (Ge) 33 Arsenic (As)
69.72 72.6 74.91
49 Indium (In) 50 Tin (Ti) 51 Antimony (Sb)
114.8 118.7 121.8
Important physical properties of both Si and Ge semiconductors are given in Table 1.3.
Table 1.3 Physical properties of silicon and germanium

Ge Si
Atomic number 32 14
Density (gm/m3) 5.32 ¥ 106 2.33 ¥ 106
Atomic weight (gm/gm·atom) 72.6 28.09
Relative dielectric constant 16 12
Atomic density (atom/m3) 4.41 ¥ 1028 5 ¥ 1028
EG (eV) at 0 K 0.785 1.21
EG (eV) at 300 K 0.72 1.1
(Contd.)

Ge Si
3
Intrinsic concentration ni /m at 300 K 2.5 ¥ 1019 1.5 ¥ 1016
Intrinsic resistivity at 300 K (Wm) 0.45 2300
mn (m2 / Vs) at 300 K 0.38 0.135
mp (m2 / Vs) at 300 K 0.18 0.048
Dn (m2 /s) at 300 K 0.01 0.0035
Dp (m2 /s) at 300 K 0.0045 0.0012
Electronic charge (q) 1.6 ¥ 10 19 Coulomb
Electronic mass (me) at rest 9.108 ¥ 1031 kg
Proton mass (mp) at rest 1.672 ¥ 10 27 kg
Neutron mass (mn) at rest 1.672 ¥ 10 27 kg
Permittivity of free space (eo) 8.854 ¥ 10 12 F/m
Permeability of free space (mo) 4p ¥ 10 7 H/m
Boltzman constant (KB) 1.38 ¥ 10 23 J/K
Plancks constant (h) 6.625 ¥ 10 34 Js
Avogadro number 6.025 ¥ 10 23per gm mole
1Å = 1010m, l mil = 103 inch, lmicron = 106 m 1 eV = 1.6 ¥ 10 19 J.
Velocity of light = 3¥108 m/s
Universal gas constant (R) = 8.314 J/K · mol KT/q = T/11,600 = 25 mV
Mobilities of holes and electrons in intrinsic silicon and germanium at room temperature having the
dimensions in m2/Vs are
Mobility mn mp
Si 0.13 0.048
Ge 0.38 0.18
Why n-type material is mainly used in manufacturing the semiconductor devices?

The answer to this question becomes clear from the mobilities of electrons and holes in Si. The
mobility of electrons (mn= 0.13) in Si is roughly two and half times more than that of holes (mp = 0.048).
The main reason why n-type material is preferred over p-type for manufacturing the semiconductor
devices is this high mobility of the electron w.r.t. the hole.
The atoms of semiconductors like Ge and Si are arranged in an orderly manner known as crystal
lattice. We know that the typical value of concentration of charge carriers in intrinsic Si and Ge at room
temperature (300 K) are ni @ 1.5 ¥ 1016/m3 and 2.5 ¥ 1019/m3 respectively.
The difference in concentration of Ge and Si materials is primarily due to the energy gap. Band gap
for germanium is approximately 0.72 eV while for silicon is 1.1 eV. The factor of energy gaps of Ge is
almost two times that of the Si that results into factor of almost 2.5 ¥ 1019/1.5 ¥ 1016 = 1.7 ¥ 103 of the
free carrier concentration between them. Hence, less number of electron-hole pairs will be generated in
Si than in Ge at any temperature. Thus, the conductivity of Si will be lesser than that of Ge at room
temperature.
1.5 Tetravalent Elements

We know that valence electrons provide the cohesive binding force among different atoms of Si/Ge
crystal. Since the bond is shared by valence electrons, it is named covalent bond as shown in Fig. 1.13.

The covalent bond results from the sharing of a pair of the valence electrons of anti parallel spin between
neighbouring atoms (similar or dissimilar).
Figure 1.13 Covalent bonds in intrinsic Si
Electrons in the outermost orbit (valence shell) are tightly bound by valence bond having no free
charge carriers either in Si or Ge at absolute zero temperature (0 K = 273°C). So electrons of Si/Ge are
unable to take part in the conduction process and hence behave as insulators. The energy levels of these
valence electrons are called valence band and in this band electrons cannot conduct any current. If
sufficient amount of energy is supplied under the influence of external factors (such as temperature,
light, etc.), the covalent bond may break open and electron-hole pair may be generated as shown in
Fig. 1.14.
The band diagram representation of the intrinsic Si/Ge is illustrated in Fig. 1.15. These free electrons
under the influence of electric field move in a particular direction and conduct current. The band in
which these free elections move is known as conduction band. Different semiconductor elements
require different amounts of energy to break open the covalent bond. The same situation can be explained
using Fig. 1.15.
Figure 1.14 Thermal generation of electron-hole pair


Figure 1.15 Intrinsic semiconductor energy band
The Si and Ge atoms approximately require 1.1 eV and 0.72 eV energy to break open their covalent
bond and elevate electrons from valence band to conduction band. An electron in the valence band (filled
band) jumps to the conduction band (empty band) as soon as it receives the amount of energy required
to overcome the energy gap. Each electron transferred from valence band to conduction band leaves
behind a vacancy similar to a physical hole. This physical hole is associated with a positive charge equal
but opposite to the charge of an electron. This is in accordance to the principle that electrons and holes
are generated in pairs as shown in Fig. 1.15. Therefore, the concentration of free electrons and holes
will always be equal in an intrinsic semiconductor.
1.6 Effect of Temperature on Intrinsic Conductivity

At absolute zero temperature any semiconductor (Si or Ge) behaves as an insulator. Some electron-hole
pairs may get generated due to thermal energy at room temperature (300 K). A sample of Si or Ge at
room temperature has the intrinsic carrier concentration (concentration of free electrons or holes) of
1.5 ¥ 1016/m3 or 2.5 ¥ 1019/m3 respectively. At higher temperature, more electron-hole pairs are generated.
The concentration of charge carriers will be higher at higher temperature. The conductivity of intrinsic
semiconductor increases with increasing temperature. The resistivity decreases with increase in the
temperature. Thus, semiconductors have negative temperature coefficient of resistance. Electrons
experience a force of attraction towards the positive terminal and holes experience a force of attraction
towards negative terminal as shown in Fig. 1.16 of the battery. Thus, there is a net movement of
particular type of charge carriers in a particular direction. This is called drift. The electrons drift in
conduction band whereas the holes drift in the valence band. Hence, both electrons and holes have drift
velocities.
Figure 1.16 Forces due to drift of holes and electrons

!
The process of covalent bond rupture caused either by increasing temperature or supply of light
energy accompanied by formation of a free electron and a free hole, is called electron-hole pair generation.
The number of free electrons is equal to the number of free holes and the semiconductor in which
number of free electrons is equal to the number of free holes is called an intrinsic semiconductor.
Intrinsic semiconductor is the trade name of pure semiconductor. The whole crystal structure of the
intrinsic semiconductor is replica of one section of the structure. So, in an intrinsic semiconductor,
conduction is due to the two separate and independent particles carrying equal and opposite charges and
drifting in opposite directions under the influence of applied electric field. Thus, in an intrinsic semicon-
ductor, the probability of getting electrons and holes is equal, i.e. 50 : 50. Hence, Fermi-level in intrinsic
semiconductor lies in the middle of energy gap (EG) as depicted in Fig. 1.15.
1.7 Conduction of Current

The conduction of current in a semiconductor takes place by:
∑ Drift, and
∑ Diffusion.
1.7.1 Drift Current

Figure 1.17 shows a crystal lattice wherein the free electrons move randomly in Brownian motion. They
collide with the stationary atoms and get deflected in a different direction. The average distance travelled
between two collisions is called the mean free path. In absence of any electric field, no net movement
in any direction takes place as shown by solid arrows in Fig. 1.17.
With application of the electric field, electrons get accelerated in opposite direction of the electric
field and hence, although the motion is still random, the net movement takes place as indicated by arrow
from left to right. This movement is called drift. Similarly, holes drift in the same direction of the
electric field. The drift velocity is proportional to the electric field and related as,
vµE
or, v = mE (1.7.1)
m V m2
where, m = mobility of carriers = / = (1.7.2)
s m Vs
Figure 1.17 Brownian motion of electrons

"
The motion of charge particles constitutes electric current. Total charge of moving electrons in a
volume (Ax) of the semiconductor is
Q = (Axqn) (1.7.3)
where, A = cross sectional area perpendicular to the flow of electrons
n = number of electrons/volume
x = length of semiconductor in the direction of flow of electrons
q = electric charge of an electron = 1.6 ¥ 1019coulombs
Thus, current due to drift of electron as shown in Fig. 1.18(a) can be expressed as
In =
dQ
=
d ( Axnq )
= A(nq)
dx F I
= Anqvn = AnqmnE (1.7.4)
dt dt dt H K
I Anq n E
Electron drift current density = Jn = = = nqmnE = snE (1.7.5)
A A
where, sn = conductivity = nqmn (1.7.6)
In a semiconductor both electrons and holes act as charge carriers and hence current density of
drifting holes as shown in Fig. 1.18(b) can be expressed as
Jp = nqmpE = spE (1.7.7)
where, sp = nqmp = conductivity of p-type semiconductor (1.7.8)
Figure 1.18 (a) Drift of electrons (b) Drift of holes
Now total current densities due to drifting electrons and holes as indicated in Fig. 1.18(c) is
J = Jn + Jp = nqmnE + nqmpE = snE + spE = sE (1.7.9)
Hence, conductivity of the material = sn + sp = s = q nm n + pm p d i (1.7.10)
Figure 1.18 (c) Drift of holes and electrons

#
The intrinsic conductivity of pure Ge at room temperature is approximately 2.2 mho/m, while the
pure Si may approach as low as 4 ¥ 104 mho/m. The resistivity r is
1 1
r= = (1.7.11)
s q(nm n + pm p )
rx x
Resistance of the material R= = (1.7.12)
A d
Aq nm n + pm p i
1.7.2 Recombination/Generation and Lifetime
Carriers (electrons and holes) are generated in pairs due to thermal agitation or absorption of radiations.
Some of the free electrons come near the empty covalent bond (hole) and fall into it. For such
recombination, momentum of electrons and holes must be conserved. Since the momentum after collisions
is zero, it is imperative that electrons and holes must be moving with equal and opposite velocities before
collisions. Such direct method of recombination is a rare possibility and hence, very less amount of
recombination takes place. Normally recombination takes place through traps or recombination centres.
There are atoms having energy states in the forbidden band. Such condition exists due to imperfection.
This condition can also be created artificially by doping the material with impurity atoms. These traps
act as third body in collision and absorb the residual momentum. Thus, the rate of recombination
increases. The lifetime of carriers denoted by t (tau) is defined as the average time elapsed between two
generations or recombinations. In fast recovery diodes, the lifetime of a carrier is kept very low by
doping with gold.
Force on an electron = qE
The minus sign is due to negative charge of electron.
F = qE = me f (1.7.13)
dvn d2x qE
acceleration = f = = 2 = (1.7.14)
dt dt me
where, me = effective mass of electron.
Hence, on integrating, electron velocity comes out to be
z dvn
dt
dt =
z dqE
m
e
dt =
qE
me
t n = mnE (1.7.15)
q
where, mn = tn (1.7.16)
me
Equation 1.7.16 indicates that the mobility of electron is related with its lifetime (tn). The lifetime of
the carrier is defined as the time taken by the carrier to transfer the energy from excitation to recombination.
The motion of the carriers in semiconductor is retarded by lattice vibration, impurities and crystal
defects. At higher temperature carriers are scattered randomly by lattice vibrations, while at lower
temperature Coulomb interaction between carriers and impurity ions dominates over scattering mechanism.
When an electric field is applied across it, electrons and holes are accelerated in opposite directions till
$
they are scattered by impurities or photons. Special feature of this interaction or collision is that the
velocity of carriers after each encounter becomes essentially random once again and their acceleration
in the direction of the field starts afresh. Thus, for moderate field intensities carriers never go far-off
from the thermal equilibrium. Inspite of the presence of electric field, the carrier energy remains essentially
thermal.
1.7.3 Diffusion Current

Let us consider a sample semiconductor material as shown in Fig. 1.19 wherein concentration of
carriers (holes) is much high on the left side of the surface YY¢. Since the holes are in Brownian motion,
they cross over the surface YY ¢ randomly from left to right and right to left. But as the concentration of
holes on the left side is much higher than that on the right side, the average number holes going from left
to right is more than number of holes going from right to left of the surface YY¢. This constitutes a net
flow of holes (carriers) from left to right, i.e. a net current flow due to flow of holes from left to right.
This is called diffusion current because it results from diffusion of carriers. Thus, diffusion current is
due to flow of charge carriers from higher concentration to lower concentration region.
Figure 1.19 Diffusion of holes in Brownian motion
The diffusion current is proportional to the concentration gradient, i.e. rate of change of concentration
with distance is expressed as
dp
I p = AqDp (1.7.17)
dx
where, A = cross sectional area,
Dp = proportionality constant = diffusion constant of holes,
dp
= concentration gradient of holes.
dx
Ê 1 ˆ dx
Dp = - Á ˜
FG IJ
Ip = -
1 F I FG m IJ F coulomb I = m /s
2
(1.7.18)
Ë Aq ¯ dp H K 2
m ¥ coulomb H K H1/ m K H s K
3
Here, negative sign means that the current flows from left to right for decreasing concentration with
distance. Similarly, diffusion current density for electrons (negative charge carrier) is
%
d ( - nq)
Jn = Dn = + qDn
dn F I (1.7.19)
dx dx H K
Hence, total electron current density due to drift and diffusion is
J = J n(Drift) + J p(Diffusion) = qnm n E + qDn F dn I = qm |RSnE + FG D IJ F dnI |UV

n
(1.7.20)
H dx K |T H m K H dx K |W
n
n
These charges can be assumed as gas molecules. For gas in steady state
P = n KT (1.7.21)
where, P = pressure
K = Boltzmann constant.
6.023 ¥ 10 26
n = concentration or number of gas molecules at STP =
22.4
The pressure gradient that provides force to expand the gas is
dP
= KT
dn F I (1.7.22)
dx dt H K
The excess density of electrons in a semiconductor with non-uniform excess electrons at a certain
distance from the injecting point is Dn/m3. The internal electric field at the same point E provides the
force on one electron = qE and hence force on Dn electrons
vn
= DnqE = Dnq (1.7.23)
mn
Dividing Jn = qDn RS d(Dn) UV by m yields

n
T dx W
J n
=G
F qD IJ RS d(Dn) UV = FG qD IJ v
n n
n (1.7.24)
m n H m K T dx W H m K
n n
This force corresponds to the pressure gradient of gas = force of the charge gradient and hence
Eqns. 1.7.22 and 1.7.24 are similar. Thus,
qDn
KT = (1.7.25)
mn
Dn KT
= = VT (1.7.26)
mn q
Dp KT
Similarly, for holes =
mp q
Dn KT Dp
= = VT = (1.7.27)
mn q mp
&
KT T
At room temperature (300 K) VT = = = 0.0259 V (1.7.28)
q 11600
Hence, total hole current due to drift and diffusion of holes is
R| F D I F dp I U| = Aqm R pE F KT I FG dp IJ U
p
= Aqm p pE S| GH m JK H dx K V|W ST GH q JK H dx K VW
p (1.7.29)
T p
Similarly, total electron current due to drift and diffusion is

FG
= Aqm n nE +
Dn dn IJ
= Aqm n nE +
RS
KT FG IJ F dn I UV (1.7.30)
H m n dx K Tq H K H dx K W
Another definition required for the explanation of energy band diagram of solids is Fermi level that is
indicated in Fig. 1.20. Fermi level (intrinsic) of any solid may be regarded as the reference energy level
from which all other energies may be measured conveniently.
Figure 1.20 Intrinsic semiconductor energy band
1.8 Extrinsic Semiconductor

The extrinsic semiconductor is the trade name of impure semiconductor and they are of two types;
namely,
∑ n-type, and
∑ p-type.
After mixing very small amount (say 1 part in 108) of impurity atoms either from pentavalent elements
or from trivalent elements in pure silicon or germanium atoms, the resulting Si or Ge crystal is said to be
doped semiconductor and the process of making a pure semiconductor an impure one is known as
doping.
1.8.1 n-type Material

If extremely small amount of impurity from pentavalent elements (antimony, phosphorus or arsenic) is
added to intrinsic Si or Ge at the time of crystal growing and the semiconductor is allowed to crystallize
so that the lattice remains intact, then each arsenic atom displaces one of the silicon atoms from its
regular site and forms covalent bonds with the neighbouring silicon atoms as shown in Fig. 1.21, using
four of its five valence electrons.
'
Figure 1.21 Tetravalent crystal with one As atom
The fifth electron of the pentavalent element does not fit into 4-bonds and so left loosely dangle to the
arsenic atom with relatively low binding energy. In fact, with the addition of just little thermal energy
these electrons can break free to move about in the crystal. This excess electron constitutes a mobile,
localized negative charge. The Arsenic atom, on the other hand, is an immobile, localized positive
charge. This way the Arsenic impurity atom adds an excess electron to the crystal but does not disturb
the overall electrical neutrality of the crystal.
The amount of conduction current depends upon the amount of impurity added into it. In addition to
the existing large number of free electrons, a few thermally generated electron-hole pairs also exist. The
thermally generated electrons join the large numbers of free electrons forming the majority carriers
whereas the thermally generated holes, become the minority charge carriers. Thus, it can be inferred
that conduction can be controlled by proper addition of impurity. As the conduction is mainly due to
negative charge carrier, the semiconductor is said to be n-type.
In n-type semiconductor, the conduction is primarily due to electrons and hence electrons are in
majority and holes can be thought of in minority.
The n-type semiconductor is neutral, because by way of doping (pentavalent atoms) equal amount of
negative charge (in the form of electrons) and positive charge (in the form of protons) have been made
available as illustrated in Fig. 1.21. In Fig. 1.22 only one hole and four electrons are deliberately shown
to indicate minority and majority carriers respectively, though this proportion of majority and minority is
much smaller here than the exact position.
Figure 1.22 Current due to electron (majority carriers)


The presence of donor impurity from the point of view of energy level diagram creates extra-local-
ized energy levels just below the conduction band as shown in Fig. 1.23. Such level is termed as donor
level and the gap between this level and conduction band is approximately 0.01 eV and 0.05 eV for Ge
and Si respectively. The estimation of ED can be similar to that of the hydrogen atom. The fifth electron
is bound to the parent atom of the impurity only without forming any covalent bond. The ionization
energy of hydrogen atom is 13.6 eV. Here slight difference does exist as the electrons move in the solid.
Hence, the effective mass of the electron, me* should be used instead of the rest mass. The relative
permittivity of the semiconductors must be taken into consideration. Under such conditions, the excita-
tion energy ED is expressed as
ED = 13.6
FG m IJ FG 1 IJ eV
*
n
(1.8.1)
H mKHe K 2
Very small amount of arsenic/antimony greatly increases the number of conduction electrons in
addition to intrinsically available electrons and holes. Hence, concentration of electrons in conduction
band exceeds the concentration of holes in the valence band. This is the reason why Fermi level of n-
type material shifts upward (towards the bottom of conduction band) as demonstrated in Fig. 1.23.
The experimental values of donor levels created by various donors in Ge are given as
As = 0.0127 eV, P = 0.012 eV, Sb = 0.0097 eV
Figure 1.23 Band diagram in n-type
Example
Calculate excitation energy required to excite the electrons from donor levels to the conduction band in
a Si crystal having effective mass me* = 0.26 me and relative permittivity er = 12.
Ed = 13.6 ¥ 0.26(12)2 = 0.025 eV.
1.8.2 Representation of n-type Material

Figure 1.24 shows an n-type semiconductor with large number of electrons (majority charge carriers),
a few holes (minority charge carriers) and sufficiently large number of immobile positive ions. These

types of charges are represented with the symbols shown in legends and it will be followed in the
discussion. Electrons, holes and immobile ions are represented by black circle, white circle and encircled
positive sign respectively as shown in Fig. 1.24.
Figure 1.24 Representation of m-type material
1.8.3 p-type Semiconductor

The opposite effect to that of the pentavalent element occurs if a trivalent impurity such as boron,
aluminum, gallium, indium (having three valence electrons per atom) is added to intrinsic Ge or Si. Since
the impurity ratio is one part in 106, the host silicon or germanium atoms surround each impurity atom.
The trivalent atom has only three valence electrons. These valence electrons from boron (trivalent
impurity) atom does not have the fourth electron, the fourth bond cannot be completed as depicted in
Fig. 1.25.
The thermal energy at room temperature is sufficient to provide this energy so as to complete the
covalent bonds around the trivalent atoms available. This process of filling a vacancy around the trivalent
atom creates a vacancy of one electron in that particular position from where the electron must have
jumped as shown in Fig. 1.26. The vacancy of electron must have opposite charge, i.e. positive and
since it goes on moving from one atom to another, there is creation of a movable (mobile) positive
charge named hole.
Figure 1.25 Si crystal with one B atom

Figure 1.26 Incomplete bond representation and movement of hole
The boron atom becomes an immobile, localized negative charge as in Fig. 1.26. Since the holes are
created in the valence band and in p-type material concentration of holes in valence band are much more
than concentration of electrons in conduction band, the Fermi level lies immediately above the binding
energy EA as indicated in Fig. 1.27.
Figure 1.27 Band diagram of p-type material
The binding energies Ea for various acceptors in Ge are B = 0.0104 eV, Al = 0.0102 eV,
Ga = 0.0108 eV, In = 0.0112 eV. In silicon these values are of the order of 0.046 eV.
An extra-localized energy level of acceptor element on the energy level diagram is termed acceptor
level in the forbidden gap just above the top of the valence band as shown in Fig. 1.27. Electrons that
occupy these levels leave behind in the valence band, vacancies (holes) that permit the electric current
to flow. The estimation of excitation energy can be done using Eqn. 1.8.1 (assuming the effective mass
of hole in the Si crystal to be 0.33 me ) as
EA = 13.6 ¥ 0.33 ¥ 122 = 0.0312 eV
Once again we note that though p-type semiconductor has excess of holes for conduction processes, as
a whole it is electrically neutral. Only one electron in Fig. 1.28 has been shown deliberately to indicate
the minority carrier and four holes to represent the majority carriers, though this proportion of majority
and minority is much smaller than the exact position.
!
Figure 1.28 Drift current due to holes (majority carriers)
1.8.4 Representation of p-type Material

Figure 1.29 shows p-type semiconductor with white circles representing holes, black dot representing
electrons and encircled negative sign representing immobile ions. In a p-type semiconductor holes are
majority charge carriers and there are a few thermally generated electron-hole pairs. Hence, the thermally
generated holes join with the already present large number of free holes giving the picture of majority
carriers as holes and few thermally generated minority charge carriers as electrons as depicted in
Fig. 1.29.
Figure 1.29 Two-dimensional view of p-type semiconductor
1.8.5 Carrier Concentration

Mixing of any type of impurity increases the concentration of one type w.r.t. the other. This phenomenon
gives the idea of majority and minority charge carriers. A typical dose of phosphorus might be ND = 1016
atoms/cm3 in a Si crystal with 1023 atoms/cm3. Thus, ND augments n by 1016 atoms/cm3 but ni is only
1010 approximately. This gives a million to one increase! The new n value describes excellent conducting
properties. The phosphorus atoms are referred to as donors since each phosphorus atom donates one
electron to the conduction band. The large increase in n gives a boost to recombination so that p falls to
quite a low level. Eventually, the equilibrium is reached in a manner such that
ni2 (T ) = np (1.8.2)
It is true for both doped as well as intrinsic semiconductors. This is called law of mass action. In this
situation, electrons are the majority charge carriers and holes are the minority charge carriers. The latter
contributes very little to the current flow. The approximation that is valid is n = ND and p = ni2 / n
= ni2 / N D . Since the majority carriers carry negative charge, the conduction mechanism and the material
is called n-type.
"
Doping with trivalent atoms (boron) in similar proportion to tetravalent atoms results in an acceptor
material. Since a trivalent element accepts an electron in order to form a stable bond, it is called acceptor.
The concentration NA of boron acceptor contributes directly to p to a very large amount. The large hole
population leads to short-lived increase in recombination so that electron population falls and equilibrium
is reached when p = NA and n = ni2 / p = ni2 / N A .
If an n-type sample is subsequently doped with an equal concentration of acceptor atoms, i.e. NA =
ND = 1016 atoms/cm3, their effects cancel out and the sample becomes intrinsic again. As the electrical
conductivity must be conserved,
ND + p = NA + n (1.8.3)
This is true for any doping condition.
Thus, in an n-type semiconductor majority charge carriers = nn = ND and in p-type semiconductor
majority charge carriers = pp = NA.
1.9 Energy Distribution

The number of free electrons dnE per unit volume within energy range E to E + dE at temperature T can
be obtained using Fermi-Dirac statistics. The number of free electrons per cubic metre of a metal whose
energies lie in the interval E to E + dE is given by
dnE = r(E)dE (1.9.1)
Here r(E) represents the density of electrons in the energy interval dE. We can safely assume in the
case of free electrons that there is no potential variation within the metal. Each cubic metre of the metal
must contain the same number of electrons. Although electron density (electrons per cubic metre)
remains constant within the metal, electrons in each unit volume have all possible energies. The function
N(E) represents this distribution in energy. This represents the number of electrons per electron volt per
cubic meter of the metal. The function r(E) may be expressed as
r(E) = N(E) f (E) (1.9.2)
Here, N(E) is the density of states (number of states per electron volt per cubic meter) in the conduction
band and f(E) is probability that an electron occupies a quantum state with energy N(E) f (E) which is
called Fermi-Dirac probability function.
The density of states N(E) is found to be proportional to the half power of energy E, i.e.
N(E) µ E1/2 = g E1/2 (1.9.3)
3/ 2
where, g = 4p
FG 2m IJ*
e
= 1.22 ¥ 1056 (1.9.4)
2
Hh K
me* = effective mass of electron in kg,
h = Planks constant in Joules-sec (6.625 ¥ 1034 Js)
The Fermi-Dirac probability function is expressed as
#
1
f (E) = E EF
(1.9.5)
1 + exp KT
Let us now examine the Fermi-Dirac probability function at T = 0 K
1
f (E) = (1.9.6)
1 + exp • ( E E F )
Three possibilities results from Eqn. 1.9.6
(a) E < EF. In this case exponential term of Eqn. 1.9.6 becomes zero and hence
f(E) = 1. It suggests that all quantum (energy) levels with energies less than EF will be occupied
at absolute zero.
(b) E > EF. In this case exponential term of Eqn. 1.9.6 becomes infinite and hence,
f(E) = 0. This reveals that there is no probability of finding an occupied quantum state for
energy greater than EF at absolute zero.
(c) E = EF. In this case exponential term of Eqn. 1.9.6 becomes unity and hence
f(E) = 1/2(at all temperatures), Eqn. 1.9.2 simplifies as (1.9.7)
g E 1/ 2 g E1/ 2
r(E) = E EF and dnE = E EF dE (1.9.8)
1+ exp KT 1+ exp KT
From Eqn. (1.9.8), r(E) = g E1/ 2 for E < EF
=0 for E > EF. (1.9.9)
Equation 1.9.9 reveals that there are no electrons having energies more than EF. The Fermi level
energy EF may be defined as the maximum energy that electrons may possess at absolute zero. Eqn.
1.9.8 is referred to as the completely degenerate distribution. The variation of f(E) with energy (E EF)
at absolute temperatures 0 K, 300 K and 2500 K is shown in Fig. 1.30. Figure 1.31(a) shows the plot of
E EF versus f(E) at absolute temperatures.
Classically all particles should have zero energy at 0 K. It can be observed from Fig. 1.31(b) that the
electrons actually have energies extending from 0 to EF at absolute zero. This is due to Pauli exclusion
principle which states that no two electrons may have the same set of quantum numbers, i.e. all the
electrons cannot have the same energy at 0 K. So absolute zero is the condition of lowest possible
energy but not the zero energy. As the temperature is raised, more thermal energy is stored in electrons
and their average kinetic energy is increased. Now some of the electrons acquire energies higher than
EF.
The distribution function changes only very slightly with temperature inspite of large temperature
changes from 0 K to 2500 K as shown in Fig. 1.31(b). The effect of high temperature is to give still
higher energies to those electrons that are having high energies at absolute zero (in the neighbourhood of
EF), i.e. only outermost or high-energy valence electrons are affected by increased temperature. The
lower energy electrons are left practically undisturbed. Further, the curve for T = 2500 K is asymptotic
with the energy axis and hence, only few electrons have large values of energy.
$
Figure 1.30 f (E) versus E – EF
Figure 1.31 (a) (E – EF) versus f (E) (b) Energy distribution
1.9.1 Fermi Level

The expression for EF can be obtained from energy distribution curve in Fig. 1.31.b at T = 0 K. The area
under the curve represents the total number of free electrons.
EF 2
n= z 0
g . E1/ 2 dE =
3
g EF3/ 2 (1.9.10)
%
2/ 3 2/ 3
Ê 3n ˆ
EF = Á
FG 3n IJ
=
Ë 2g ˜¯ H 2 ¥ 1.22 ¥ 1056 K
-54 2 /3 2/3 36
= d0.0123 ¥ 10 i n = 0.05 ¥ 10 ¥ n2/3 (1.9.11)
We know that the density n varies from metal to metal and hence, EF also varies as per Eqn. 1.9.11.
The density of electrons n may be calculated by knowing specific gravity, atomic weight, and the
number of electrons per atom. The Fermi energy EF for most of the metals is numerically less than
10 eV. Fermi level is a characteristic energy of the material. We know that number of electrons and
holes are equal in an intrinsic semiconductor. The concentration of electrons increases above the bottom
of conduction band. Similarly, the concentration of holes increases below the top of the valence band as
indicated in Fig. 1.32(a).
The centre of gravity of electrons and holes in Fig. 1.32(a) lies exactly at the middle of forbidden gap.
This central level is known as Fermi level. The Fermi level is the energy that corresponds to the centre
of gravity of the conduction electrons and holes weighted according to their energies. Fermi level is a
concept like a hollow body having a centre of gravity where there is no matter. When a donor impurity
is added to an intrinsic semiconductor, it becomes n-type. Now it has more conduction electrons than
holes as shown in Fig. 1.32(b). Thus, if the centre of gravity is moved up. Fermi level shifts towards the
conduction band. Similarly, when an acceptor impurity is added to an intrinsic semiconductor, it becomes
p-type. Now, it has more holes than electrons. This shifts the Fermi level towards the valence band as
shown in Fig. 1.32(c).
Figure 1.32 (a) Intrinsic Semiconductor (b) n-type (c) p-type
1.10 Electron Emission from Metal

The energy of free electrons (eV) as a function of distance is shown in Fig. 1.33(a). The conduction
electrons move freely in the interior of the metal but no electrons can come out the surface unless it
&
acquires energy at least equal to barrier height fB of the material. We can say that an electron can escape
from the surface of the metal provided it has energy atleast equal to the barrier height fB. We have
shown the energy of electrons inside the metal (energy distribution curve) in Fig. 1.33(b).
1.10.1 Work Function

The maximum energy possessed by an electron is only EF (Fermi energy) that is less than potential
barrier energy fB as illustrated in Fig. 1.33(b) at 0 K. Hence, electrons cannot escape from the metal
surface. To make the escape possible, an additional energy (fB EF) should be applied. The energy
difference (fB EF) is known as work function and is denoted by f w. Thus, the work function is
written as
f w = fB EF (1.10.1)
Figure 1.33 (a) Energy w.r.t. distance (b) Energy w.r.t. distance
The work function of a metal fw represents the minimum amount of energy that must be given to the
fastest moving electron at zero Kelvin to enable the electrons to escape from the metal.
1.10.2 Thermionic Emission

Figure 1.33(b) indicates that no electron can escape from the metal surface at 0 K as its energy is less
than Fermi energy EF.
The thermal energy is supplied to the electrons from the lattice of heated metal crystal. The shape of
the curve assumes a form as shown in Fig. 1.33(b) at temperature of 2500 K. Some of the electrons
represented by the tail of the curve (shaded portion) now have energies exceeding EF and so these
electrons escape from the metal. The number of electrons that strike the surface of metal per second on
heating the metallic surface is called thermionic. The emission of electrons constitutes the emission
current. Richardson and Dushman developed an expression for thermionic emission current given by
- fw
2
I th = SA0T e KT (1.10.2)
where, S = Surface area of the filament in m2

A0 = Constant of emitting material whose dimension is A/m2K2
'
T = Temperature of emitter in K
K = Boltzmann constant in eV/K
fw = Work function in eV.
We observe from Eqn. 1.10.2 that the thermionic current is very sensitive to temperature. For tungsten
(fw = 4.5 eV), it is found that 1% change in temperature results in 24% change in Ith at operating
temperature of 2400 K.
1.10.3 Energies of Emitted Electrons

Let a retarding potential be established between a plane parallel emitter and collector (emitter positive
w.r.t collector). The current of all the electrons leaving the cathode with the same energy would remain
constant until a definite voltage is reached and then it would fall abruptly to zero. Experimentally no such
sudden fall is found but there is an exponential decrease of current I with voltage. Equation 1.10.2 gives
thermionic current Ith for zero retarding voltage. When the barrier height is increased by Er, then the
work function becomes fw + Er in place of fw and we have
- Ff + E I
w r
I = SA0T 2 exp
H KT K (1.10.3)
Substituting Eqn. 1.10.2 in Eqn. 1.10.3 yields
Er
-
I = I th exp KT (1.10.4)
Let this increase in barrier height be caused by the application of a retarding voltage Vr, then,
qVr = 1.6 ¥ 1019Er (1.10.5)
Er qVr V
= = r (1.10.6)
KT 1.6 ¥ 10 -19 KT VT
where, the dimension of VT is Volt defined by
KT T 1.38 ¥ 10 -23 ¥ 300
Thermal voltage = VT = = = = 25.9 mV (1.10.7)
q 11,600 1.6 ¥ 10 -19
K = Boltzmann constant in joules per Kelvin = 1.381 ¥ 1023 J/K
= 1.381 ¥ 1023/1.6 ¥ 1019 = 8.62 ¥ 105 eV/K
Equation 1.10.4 now reduces to
Vr
-
VT
I = I th exp (1.10.8)
Thus, distribution of energy of emitted electrons from the metal looks the same as that inside the
metal.
!
1.11 Carrier Concentration in Intrinsic Semiconductor

It is essential to know the concentration of free electrons n in conduction band and the concentration of
holes p in valence band to evaluate the conductivity of a semiconductor.
1.11.1 Population of Electrons in the Conduction Band

The product of the number of existing states at any energy E and the probability of its occupancy gives
the population of occupied states by an electron. The electron population at any energy level is defined
as
dnE = N(E) f (E)dE (1.11.1)
= number of states at level E × probability of occupancy, i.e.
The electron population n in a band extending from energy level E1 and E2 is given by
E2 E2
n= z z
E1
dnE =
E1
N ( E ) f ( E )dE (1.11.2)
Ideally no states are available in the forbidden gap EG, i.e. N(E) = 0. Hence, population of electron in
the band gap = 0. Here, N(E) is the density of states (number of states per electron volt per m3) and f (E)
is Fermi-Dirac probability function.
1.11.2 Density of States

The density of states N(E) is found to be proportional to the half power of the energy E, i.e.
N(E) µ E1/2 = g E1/2 (1.11.3)
3/ 2 -31 3/ 2
where, g = 4p
FG 2m IJ*
e
= 4p
FG 2 ¥ 11. ¥ 9.1 ¥ 10 IJ = 1.22 ¥ 1056
2 -34 2
Hh K H (6.625 ¥ 10 ) K
The bottom of the conduction band in deriving Eqn. 1.11.3 was assumed to be at zero potential. Here,
the lowest energy in the conduction band is EC and hence, the Eqn. 1.11.3 is modified as
N(E EC) = g (E EC)1/2 (1.11.4)
The Fermi function f(E) is given by
1
f (E) = E - EF (1.11.5)
1+ e KT
EF = Energy level of Fermi function.
In conduction band (E EF) >> KT, i.e. for energy E >EC. The exponential term in the denominator
of Eqn. 1.11.5 for (E EF) >> KT becomes very large w.r.t. unity. So Eqn. 1.11.5 reduces to
E - EF
-
f(E) = e KT (1.11.6)
!
The energy band diagram of an intrinsic semiconductor is shown in Fig. 1.34. The top of energy level
of the valence band is designated as EV and the bottom of the energy level of conduction band is
designated as EC. The EF is the energy of Fermi level. The variation of Fermi function f (E) versus E,
both for 0 K and room temperature (T = 300 K) is shown in Fig. 1.34. It is obvious from this figure that
the probability of finding an electron in the conduction band is zero i.e. f (E) = 0, while the probability
of finding holes in the valence band is zero i.e. 1 f (E) = 0.
Figure 1.34 Intrinsic semiconductor band picture, Fermi function f(E)
At room temperature (300K), a few electrons get excited to higher energies and few states near the
bottom of conduction band are filled as shown in the figure. Further, at room temperature, in the upper
region of valence band, the probability of occupancy of states gets decreased slightly below unity. This
is due to the fact that some of electrons have escaped from the covalent bonds and have shifted to the
conduction band. A plot of N(E) versus E and density of electrons N(E) f (E) are shown in Fig. 1.35.
Figure 1.35 Density of states in conduction and valence bands
The concentration of electrons in conduction band is the area under the curve shown in Fig. 1.35 and
is expressed as
•
n= z
EC
N ( E - EC ) f ( E )dE (1.11.7)
!
We are interested in concentration of electrons in the conduction band and hence N(E) is changed to
N(E EC) = g (E EC)1/2 and f(E EC) = e
b
- E - EF /KT g . Now substituting these in Eqn. 1.11.7 yields
•
n= z
EC
g ( E - EC )1/ 2 ¥ e - (
E - EF )/ KT
dE (1.11.8)
Rearranging Eqn. 1.11.8 as

• 1/ 2 E - EC - EF + EC
Ê E - EC ˆ -
n = g (KT )1 2 Ú ÁË KT ˜¯ ¥e KT dE
EC
• 1/ 2 - ( E - EC ) - ( EC - EF )
12 Ê E - EC ˆ
= g (KT ) Ú ÁË KT ˜¯ ¥ e KT e KT (1.11.9)
EC
Ê E - EF ˆ • 1/ 2 Ê E - EC ˆ
1/ 2
-Á C
Ë KT ˜¯
Ê E - EC ˆ -Á
Ë KT ˜¯
= g (KT ) e Ú ÁË KT ˜¯ e dE (1.11.10)
EC
E - EC
Let, =x
KT
dE = KTdx (1.11.11)
Also, E = EC for x = 0 and E = • for x = •. Hence, Eqn. 1.11.10 is rearranged as
Ê EC - EF ˆ •
Á -
˜ 1/ 2 - x
n = g (KT )1 2 e Ë KT ¯ Úx e (KTdx )
0
Ê E - EF ˆ •
-Á C
3/ 2 Ë KT ˜¯ 1/ 2 - x
= g (KT ) e Úx e dx (1.11.12)
0
•
p
The definite integral Ú x1/ 2 e- x dx = (1.11.13)
0
2
Ê EC EF ˆ Ê E - EF ˆ
p ËÁ -Á C
3/ 2 KT ¯
˜ Ë KT ¯˜
n = g ( KT ) e = NC e (1.11.14)
2
3/ 2
NC
F 2pm KT IJ = 2 F 2p K I dm T i
= 2G
*
e
3/ 2
* 3/ 2
H h K 2 Hh K 2 e
-23 3/ 2 3/ 2
F 2p ¥ 1.38 ¥ 10 IJ (m T ) = 2 FG 8.67 ¥ 10 IJ
= 2G *
e
3/ 2
44
(me*T )3/ 2
-34 2
H (6.625 ¥ 10 ) K H 4.3.89 K
!!
= 2 (1.97 ¥ 10 44 )3/ 2 (me*T )3/ 2 = 2 ¥ 2.776 ¥ 10 66 (me*T )3/ 2

= 5.55 ¥ 10 66 ( me*T )3/ 2
and ( me*T )3/ 2 = (11
. ¥ 9.1 ¥ 10 -31 ¥ 300)3/ 2 = (300.3)3/ 2 ¥ 10 - 45 = 5.2 ¥ 10 - 42
Hence, NC = 5.55 ¥ 1066 ¥ 5.2 ¥ 10 - 42 = 28.8 ¥ 10 24 = 2.88 ¥ 10 25 / m3 (1.11.15)

The quantity NC is called the effective density of states in the conduction band edge and in silicon it
is numerically NC @ 2.9 ¥ 1025/m3 at room temperature.
where, mn = mass of electron in kg (9.109 ¥ 1031 kg) and mn* @ 1.1mn,
h = Planks constant in Joules-sec (6.625 ¥ 1034 Js)
q = 1.602 ¥ 1019 coulomb
K = 1.381 ¥ 1023 J/K
Here, k is in electron-volt per Kelvin while K is expressed in joules per Kelvin. The relationship
between joule and electron-volt is
1eV = 1.6 ¥ 1019 J
1.11.3 Number of Holes in Valence Band

The concentration of holes in the valence band can be derived. The following points must be kept in
mind.
(a) The density of states is given by
N(EV E) = g (EV E)1/2 for E < EV (1.11.16)
(b) Since a hole is nothing but a vacancy created by the removal of an electron (empty level), the
Fermi function of hole is [1 f (E)]. Here f (E) represents the probability that an electron
occupies the level. Thus, the probability function for hole is
Ê E - EF ˆ
Á ˜
KT ¯
1 eË 1
1 f (E) = 1 - E - EF
= = (1.11.17)
Ê E - EF ˆ Ê E EF ˆ
-Á
1 + e KT
ÁË KT ˜¯ Ë KT ˜¯
1+ e 1+ e
Ê E - EF ˆ
Á ˜
Ë KT ¯
As (EF E) >> KT, e > 1, Eqn. 1.11.17 reduces to
Ê E - EF ˆ EF - E
ÁË KT ˜¯ -
[1 f(E)] = e = e KT (1.11.18)
3
The number of holes/m in the valence band is the area under the lower curve in Fig. 1.35 and is given
by
!"
EV
p=
-•
z N ( E - E ) 1 - f ( E ) dE
V
(1.11.19)
Substituting the values of N(E) and [1 f(E)] from Eqns. 1.11.16 and 1.11.18 in Eqn. 1.11.19 yields
EV Ê E - Eˆ EV Ê E - EV + EV - E ˆ
-Á F -Á F
1/ 2 Ë KT ˜¯ 1/ 2 KT
˜¯
Ú g ( EV - E ) Ú g ( EV - E )
Ë
p= e dE = e dE
-• -•
Ê E - EV ˆ EV 1/ 2 Ê E - Eˆ
-Á F Ê EV - E ˆ -Á V
1/ 2 Ë KT ˜¯ Ë KT ˜¯
= ( KT ) e Ú g ÁË KT ˜¯ e dE
-•
ÊE E ˆ E
-Á F V˜ V
1/ 2 Ë KT ¯ 1/ 2 - x
= ( KT ) e Ú g ( x) e KTdx
-•
Ê E - EV ˆ •
-Á F
3/ 2 Ë KT ˜¯ 1/ 2 - x
= ( KT ) ge Ú (x) e dx
0
Ê E - EV ˆ Ê EF - EV ˆ
-Á F p -Á
3/ 2 Ë KT ˜¯ KT ˜¯
= ( KT ) ge = NV e Ë (1.11.20)
2
F 2 m KT I 3 / 2 F 2p ¥ 1.38 ¥ 10
*
-23 I 3/ 2
= 2G
GH h2 JJK = 2 GGH d6.625 ¥ 10 i JJ
p
where, NV (m *pT )3/ 2 = 5.55 ¥ 1066 (m *pT )3/ 2
-34 2
K
3/ 2
and (m *p T )3/ 2 = ( 0.56 ¥ 9.1 ¥ 10 -31 ¥ 300)3/ 2 = 152.88 ¥ 10 - 30 d i = 1.89 ¥ 1042
Hence, NV = 5.55 ¥ 1066 (m *pT )3/ 2 = 5.55 ¥ 10 66 ¥ 1.89 ¥ 10 - 42 = 10.5 ¥ 10 24
= 1 ¥ 10 25 / m 3 (1.11.21)
The quantity NV is called the effective density of states in the valence band and in silicon it is numeri-
cally NV @ 1025 /m3 at room temperature.
1.12 Fermi Level in Intrinsic Semiconductor

Equations 1.11.14 and 1.11.20 are valid for both types of semiconductors, i.e. intrinsic (pure) and
extrinsic (impure). In case of intrinsic material the subscript i will be added to n and p. Thus ni, and pi
refers to concentration of electrons and holes in intrinsic semiconductor. Since the semiconductor
crystal is electrically neutral, it is written as
ni = pi (1.12.1)
!#
Ê E - EF ˆ Ê E - EV ˆ
-Á C -Á F
Ë KT ˜¯ Ë KT ˜¯
n i = NC e = pi = NV e (1.12.2)
( EC EF ) / KT
NV ( E E ) / KT
=1= e F V = e - ( EC + EV - 2 EF ) / KT (1.12.3)
NC
b g a f FGH IJK
EC + EV 2 EF = KT ln V
N
NC
(1.12.4)
E =
F KT I ln FG N IJ + F E
V C + EV I (1.12.5)
FH 2 K HN K H C 2 K
Equation 1.12.5 indicates that the Fermi level in an intrinsic semiconductor lies in the band gap. Now,
substituting values of NC and NV from Eqns. 1.11.14 and 1.11.5 in Eqn. 1.12.5 yields
3/ 2
EF =
FE C I F I FG * IJ
+ EV
+
KT
ln
mp
H K H K H K
2 2 *
mn
=
F E + E I + F 3KT I lnFG m**p IJ
C V
(1.12.6)
H 2 K H 4 K H mn K
Here, m*p and mn* are effective mass of hole and electron respectively. Since m*p π mn* , expansion of
Eqn. 1.12.6 results in exponential form and NC π NV. However, we may presume for all practical
purposes that
(NC NV)1/2 @ NC @ NV (1.12.7)
Substituting Eqn. 1.12.7 in Eqn. 1.12.5 yields as
EC + EV
EF = (1.12.8)
2
Equation 1.12.8 reveals that the Fermi level lies in the center of forbidden energy band as shown in Fig.
1.34.
EC EV = EG, EC + EV = 2EF
then, 2EC = EG + 2EF
EG
EF = EC (1.12.9)
2
2EV = EG 2EF
EG
EF = EV + (1.12.10)
2
Ê E EV ˆ EG
Á F -
Ë KT ˜¯ 2KT
pi = NV e = NV e
!$
Ê E - EF ˆ Ê E ˆ
-Á C -Á G ˜
Ë KT ˜¯ Ë 2 KT ¯
and n i = NC e = NC e (1.12.11)
1.12.1 Intrinsic Concentration

We know that the product of concentration of electrons and holes remains constant at all temperatures,
i.e.
Ê E EV ˆ ÊE ˆ
Á C Á G˜
Ë KT ˜¯
= NC NV e
Ë KT ¯
np = ni2 = NC NV e (1.12.12)
EG
1/ 2
(
ni = NC NV ) e 2 KT
(1.12.13)
This product depends on the temperature and the energy gap EG = EC EV but independent of the Fermi
level. Equation 1.12.12 is valid for both types of semiconductors i.e. intrinsic and extrinsic. Now
substituting numerical values for physical constants in Eqn. 1.11.15 we get
NC = 5.55 ¥ 1066 (me*T )3/ 2 (1.12.14)
3
The dimension of NC is that of the concentration, i.e.number/m . The equation of NV is similar to
Eqn. 1.12.14 except substituting m *p in place of mn* i.e.
NV = 5.55 ¥ 1066 (m *pT )3/ 2 (1.12.15)

EG
2 -
np = ni = 5.55 ¥ 1066 ( me*T )3 / 2 ¥ 5.55 ¥ 1066 ( m*pT )3 / 2 e KT
EG
66 2 3 - KT
(
= 5.55 ¥ 10 ) * * 3/ 2
(me m p ) (T ) e (1.12.16)
Equation 1.12.6 indicates that ni is very sensitive function of temperature and bandgap EG.
The energy gap decreases with increasing temperature that is expressed as
EG(T) = 1.21 - 3.6 ¥ 10 - 4 T for Si at room temp. = 1.1 eV (1.12.17)
-4
EG(T) = 0.785 - 2.23 ¥ 10 T for Ge at room temp. = 0.72 eV (1.12.18)
Equations 1.12.17 and 1.12.18 can be generalized as
EG = EGO bT (1.12.19)
where, EGO = energy band gap at 0K. Now substituting the relationship from Eqn. 1.12.19 in Eqn.
1.12.16 yields
- Ego /( 2 KT )/ q
ni(T) = 3.86 ¥ 1016 ¥ T 3/ 2 e (1.12.20)
Equation 1.12.20 was experimentally verified and values of ni and EGO are available as material
constants.
!%
1.13 Fermi Level in Extrinsic Semiconductor

Equations 1.12.13 and 1.11.5 are applicable to extrinsic semiconductor also. It is obvious from these
equations that the only parameter that changes with impurities is Fermi level EF. The Fermi level EF of
an intrinsic semiconductor lies in the middle of energy gap. This shows that free electrons and holes
have equal concentrations. Let us examine how the Fermi level changes in an extrinsic semiconductor.
1.13.1 Fermi Level in n-type Semiconductor

We assume that all donor atoms of an n-type semiconductor get ionized at a given temperature to get
estimation of Fermi level. Now the first ND states in conduction band will be filled. It becomes difficult
for the valence band electrons to bridge the energy gap by thermal agitation due to these filled states. We
can say that the number of electron hole-pairs thermally generated at that temperature is reduced. We
know that Fermi level is a measure of the probability of occupancy of the allowed energy states. Hence,
the Fermi level must move closer to the conduction band to indicate that many energy states in that band
are filled by the donor electrons and fewer holes exist in valence band. This situation is shown in
Fig. 1.36.
The n-type semiconductor is almost entirely due to extrinsically supplied electrons from the donors.
Hence, n = ND is the concentration of donor atoms. Substituting n = ND in Eqn. 1.12.11 we get
- FE -E I
C F
n = ND = NC e H KT K (1.13.1)
EC - EF
ln ND = ln NC (1.13.2)
KT
l
EC EF = KT ln NC - ln N D = KT ln q FG N IJ
C
(1.13.3)
HN K
D
Figure 1.36. Band diagram and Fermi level in n-type semiconductor
1.13.2 Fermi Level in p-type Semiconductor

Following assumptions must hold good for calculating the Fermi level in p-type semiconductor:
∑ The density of acceptor atoms far exceeds the density of donor atoms.
∑ Every acceptor atom has accepted one electron from the valence band.
!&
∑ The density of electrons in the conduction band is much smaller than that of the holes in the
valence band.
Similar arguments as in n-type semiconductor leads to the conclusion that the Fermi level must move
from the centre of the forbidden gap closer to the valence band for a p-type material. The situation is
shown in Fig. 1.37.
Figure 1.37. Band diagram and Fermi function in p-type semiconductor
- FE -E I
F V
In this case, n = NA = NV exp

H KT K (1.13.4)
Solving Eqn. 1.13.4 yields, EF = EV + KT ln

FG N IJ
V
(1.13.5)
HN K A
1.14 Hall Effect

Let us consider a semiconductor bar of uniformly doped n+ material of dimensions L, W, and d. The
voltage V is applied between two ends of the semiconductor length L as indicated in Fig. 1.38. This sets
up an electric field E = V/L in the direction from left to right. A magnetic field is applied perpendicular
to the electric field directing upward. The tip of the arrow (∑) of the magnetic field can be treated as
electrons and tails of the arrow (¥) can be treated as positive charge carriers. Hence, electrons moving
from right to left will be deflected towards the front face of the semiconductor because on the front side
+ charges due to flow of electrons and charges present due to electric field cancel as indicated in
figure on left side of the semiconductor bar. Similarly, the positive charge carriers will be deflected
toward the back face of the bar. Thus, an electric field is developed between the front face and the back
face of the semiconductor bar resulting into a Hall voltage VH = VBF. This VH is negative for n+ type
material and positive for holes as majority carriers. The Hall effect can be used to determine the type of
majority charge carriers as well as carrier concentration and mobility.
Force exerted on electron due to magnetic field = B ¥ qvn
Electric force due to Hall field = qEH
!'
Figure 1. 38 Hall effect
Hence, at equilibrium eEH = B ¥ qvn, where, vn = velocity of electron,

B = magnetic field density, and EH = Hall electric field
I dQ d ( nqxA) dx J J
J= = = = nq = nqvn and qEH = Bq =B
A dt A ◊ dt dt nq n
EH 1 1
= = RH = Hall co-efficient, and rn =
BJ nq nqm n
EH 1 mn R
RH = = = = rnmn, Hence, mobility = mn = H
BJ nq nqm n re
1. Estimate the density of Si. lion silicon atoms, calculate the resistivity
Solution : The density of states in Si can of the doped silicon.
be expressed as No. of silicon atoms = Ni = 4.5 ¥ 1028/m3
Intrinsic carrier concentration = ni
mass of atoms in unit cell = 1.5 ¥ 1016/m3
r(Si) =
volume of unit cell Electron mobility mn = 0.135 m2/Vs
(no.of atoms/ unit cell)(at. wt.)(proton mass) Hole mobility mp = 0.048 m2/Vs
= (Winter-91 AMIE)
lattice constant 3
Solution.: The conductivity of the intrin-
8 ¥ 281. ¥ 1.66 ¥ 10 - 24
= -8 3 = 2.33 gm/cm3 sic silicon = si = ni q( m n + m p )
( 5.43 ¥ 10 )
= 2.33 ¥ 103 kg/m3 a
si = 1.5 ¥ 1016 ¥ 1.6 ¥ 10 -19 0.135 + 0.048 f
2. Find the resistivity of intrinsic silicon. = 2.4 ¥ 10- 3 ¥ 0.183
When it is doped with a pentavalent impu- = 0.439 ¥ 10 - 3 mho / m
rity of one impurity atom for each 60-mil-
1 104
resistivity ri = =
si 4.39
"
= 2.3 ¥ 103 Wm In n qv A nv nn ¥ 3v p
= n n = n n =
Ip qpn v p A pnv p pnv p
ni
If ND = number of donor atoms =
60 ¥ 10 6 3nn (3 / 4) I
= = =3
pn (1/ 4) I
4.5 ¥ 10 28 20 3
= 6 = 7.5 ¥ 10 / m nn = pn
60 ¥ 10
Hence, number of free electrons = nn = ND The ratio of electrons to holes present in
20
= 7.5 ¥ 10 / m 3 the semiconductor is equal.
4. Find the density of impurity atoms that
ni2 (1.5 ¥ 1016 )2 must be added to an intrinsic crystal in or-
Number of holes = =
nn 7.5 ¥ 1020 der to obtain (a) a p-type silicon with its
resistivity of 0.1 Wm, (b) an n-type silicon
= 3 ¥ 1011 / m3 with the same resistivity of 0.1 Wm. Cal-
Thus, the number of holes (3 ¥ 1011/m3) in culate the concentration of the majority
the doped semiconductor are much carriers in each case.
smaller than the numbers of electrons (7.5
Solution: For a p-type silicon,
¥ 1020/m3). Hence, the semiconductor is
of n-type and its conductivity will be 1
rp =
sn = qnn m n qN A m p
= 1.6 ¥ 10 -19 ¥ 7.5 ¥ 10 20 ¥ 0.135 1 1016

NA = =
= 0.162 W/m 1.6 ¥ 10 -19 ¥ 10 ¥ 480 7.6
Hence, resistivity of doped semiconductor = 1.316 ¥ 1015 / cm 3 = 1.316 ¥ 10 21 / m 3
1 1000
= rn = = = 6.173 Wm Assuming all the acceptor atoms ionized,
sn 162 the majority charges carrier concentration
3. In a semiconductor it is observed that three
= 1.316 ¥ 10 21 / m 3 .
quarter of the current is carried by elec-
The minority charge carrier concentration
trons and one quarter by holes. If at this
temperature the drift speed of electrons is n2 (1.5 ¥ 1016 )2
= i = = 1.71 ¥ 1011/m3
three times that of the holes, determine the NA 1.316 ¥ 1021
ratio of electrons to holes in the semicon- 1
For an n-type Silicon, ND =
ductor. qm n r n
(Winter-91 AMIE) 1
=
Solution: Total current = I = In + Ip 1.6 ¥ 10 -19 ¥ 0.135 ¥ 0.10
3I I = 4.63 ¥ 1020 / m3
As per question In = and Ip =
4 4 Hence, minority carrier concentration
vn = 3vp ni2 (1.5 ¥ 1016 )2
= pn = =
In = nnqvA and Ip = pnqvpA ND 4.63 ¥ 1020
= 4.86 ¥ 10 / m 3
11
"
5. Calculate the diffusion current in a piece b

n = p N A ND g
of germanium having concentration gradi-
ent of 1.5 ¥1022 electrons/m3 and = 1.035 ¥ 10 - ( - 5 ¥ 1019 )
19
Dn = 0.0012 m2 / s. = 6.035 ¥ 1019 / m 3
Solution: J = qDn F dn I amp/ m 2 J = J n + J p = ( nm n + pm p ) qE

H dx K = (6.035 ¥ 0.2778 + 1.035 ¥ 0.1389)1019
= 1.6 ¥ 10 -19 ¥ 0.0012 ¥1.5 ¥10 22 ¥ 1.6 ¥ 1019 ¥ 0.02
= 2.28 A/m 2 a f
= 1.677 + 0.144 0.032 = 0.0582A/ m 2
6. A sample of germanium is doped with
7. The resistivity of the copper at 20o C is
10 20 donor atoms/ m 3 and 5 ¥ 1021 accep-
tor atoms/m3. Find the total conduction 1.73 ¥ 108 Wm . Obtain the average drift
current density if the resistivity of intrinsic velocity in the copper conductor with its
germanium at 300 K is 0.6 Wm with an cross sectional area of 10 -6 m 2 carrying a
applied field of 0.02 V/m. Determine the current of 2 A.
ratio of electrons and holes if the mobility Solution: The density of copper with an
of electrons is two times the mobility of
atomic weight 63.6 is 8.9 ¥ 10 6 g/ m 3 .
holes at 300 K .
Hence, using Avagadros law, the number
Solution: s i = ni q( m n + m p ) of atoms/ m3 is
= 2.5 ¥ 1019 ¥ 1.6 ¥ 10 -19 (2 m p + m p ) 6.022 ¥ 10 23atoms/g ◊atom
1 1 ¥ 2.33 ¥ 10 6g/m 3
3m p = = nA =
0.60 ¥ 2.5 ¥ 1.6 2.4 28.09 g/g ◊ atom
1 = 0.499 ¥ 10 29 atoms / m 3
mp = = 0.1389 m2 /Vs
7.2
Assuming all atoms are ionized i.e. one
m n = 2 ¥ 0.1389 m2 /Vs
electron per atom, n = NA
= 0.2778 m2 /Vs
I
19 20 J= = nqvn
Also, p n = N A N D = 5 ¥ 10 - 10 A
= - (10 - 5) 1019 = 5 ¥ 1019/m3 2
vn =
0.499 ¥ 10 29 ¥ 1.6 ¥ 10 -19 ¥ 10 - 6
np = ni2 = ( 2.5 ¥ 1019 )2 = 6.25 ¥ 1038
6.25 ¥ 1038 2 ¥ 10 - 4
p = - 5 ¥ 10 19 = = 2.5 ¥ 10 4 m/s
p 0.799
8. Find the ratio of concentration of silicon
or, p 2 + 5 ¥ 1019 p - 6.25 ¥ 1038 = 0 atoms and electron-hole pairs at 300 K.
p = 1.035 ¥ 1019 / m3 Determine the intrinsic resistivity.
"
Solution: The concentration of atoms by 5 ¥ 1021

Avagadros law is Hence, number of holes = p =
1.5 ¥ 1016
6.022 ¥10 23atoms/g ◊atom = 3.3 ¥ 10 5
The new concentration of electrons
¥ 2.33 ¥ 10 6 g/m 3
nA = ni2
28.09 g/g ◊ atom n2 2.25 ¥ 1032
np = @ i =
pp NA 5 ¥ 10 21
= 0.499 ¥ 10 29 atoms/ m 3
= 4.5 ¥ 1010 / m 3
The intrinsic concentration at 300 K = 1.5 The electron concentration has been re-
¥ 1016 electron-hole pair/m3. Hence,
1.5 ¥ 1016
NA 0.499 ¥ 10 29 duced by the factor =
= 4.5 ¥ 1010
ND 1.5 ¥ 1016
= 1.5 ¥ 1022 / m3
= 3.33 ¥ 1012 silicon atoms per electron- Hence, new conductivity s
hole pair. = q( nm n + pm p ) @ qN A m p
1 = 1.6 ¥ 10 -19 ¥ 5 ¥ 10 21 ¥ 0.048
The intrinsic resistivity ri =
si = 38.4 mho/ m
1 The intrinsic conductivity is only
=
( m n + m p ) qni = 0.00044 mho/m
Hence, the resistivity of the doped silicon
si = 1.5 ¥ 1016 ¥ 1.6 1 1
19
=r= = = 0.026 Wm
¥ 10 (0.1350 + 0.0480) s 38.4
= 2.4 ¥ 0.1830 ¥ 10 - 3 = 0.439 ¥ 10 -3 The intrinsic resistivity r i = 2300 Wm.
10. Find the resistivity of extrinsic silicon
ri = 2.28 K Wm doped with the donor impurity to the ex-
9. What are changes in the electrical proper- tent of 1 in 108 atoms. Use standard values
ties of silicon at 300 K if doping rate is one of silicon.
indium atom for every 10-million silicon Solution.: Density of Si atoms
atoms.
= 5 ¥ 10 28 / m 3
Solution: Since there are 5 ¥ 1028 Si
atoms/m3, the concentration of acceptor 5 ¥ 10 28
ND = 8
= 5 ¥ 10 20 atoms/ m 3
atom is 10
5 ¥ 10 28 np = ni2 = (1.5 ¥ 1016 )2 = 2.25 ¥ 10 32 ,
NA = = 5 ¥ 1021 @ pp
10 ¥ 10 6 n = ND
The corresponding intrinsic concentra- 2.25 ¥ 1032
16 3 p= = 4.5 ¥ 1011 / m3
tions ni = pi = 1.5 ¥ 10 / m . 5 ¥ 10 20
"!
Since, n = ND (= 5 ¥ 10 20 /m3 ) which is = 1.5 ¥ 1016 ¥ 1.6 ¥ 10 -19 (2 m n )

much larger than p (= 4.5 ¥ 1011 / m3 ), the = 2.4 ¥ 103 ¥ 2mn
material is n-type and electrons are the
si
majority carriers. Hence, mn =
2.4 ¥ 2 ¥ 103
s = nqm n = N Dqm n
1
= 5 ¥ 10 20 ¥ 1.6 ¥ 10 -19 ¥ 0.135 = -3 +3
= 0.104 m2 /Vs
4.8 ¥ 10 ¥ 2 ¥ 10
= 10.8 mho/m
(b) Conductivity of extrinsic semiconduc-
1 tor = sn = nqm n
Resistivity = r n = = 0.0926 W m .
sn Since doping concentration >> minority
Thus, it is seen that the resistivity of the concentration only doping concentration
intrinsic semiconductor is brought down will be used. Hence, sn = 1020 ¥ 1.6 ¥
drastically from 2.3 ¥ 103 Wm to 0.0926 1019 ¥ 0.1042 = 1.67 mho/m Hence, re-
Wm. 1
sistivity = = 0.6 Wm
11. In a semiconductor at room temperature sn
(300 K) the intrinsic carrier concentration
and resistivity are 1.5 ¥ 1016 / m 3 and (c) EF Ei = KT ln
FG n IJ
o
2 ¥ 103 Wm respectively. It is converted to Hn Ki
an extrinsic semiconductor with doping
concentration of 10 20 / m3 . For the extrin- Ê 10 20 ˆ
= 26 ¥ 10 -3 ¥ ln Á 16 ˜
sic semiconductor calculate (a) minority Ë 1.5 ¥ 10 ¯
carrier concentration (b) resistivity (c)
shift in the Fermi level due to doping (d) = 0.026 ln(6.67 ¥ 10 2 ) = 0.23 eV
minority carrier concentration when its (d) Minority carrier concentration
temperature is increased to a value at ( 2 ¥ 1.5 ¥ 1016 )2
which the intrinsic concentration ni =
1020
doubles. Assume (i) mobility of majority
and minority carriers to be the same (ii) = 9 ¥ 1012 atoms/ m 3
KT 12. A 25 gm p-type Ge crystal exhibits a resis-
= 26 mV at room temperature.
q tivity of 0.05Wm at 300 K. By uniform an-
(GATE) timony doping it is converted into n-type
semiconductor having 0.01Wm resistivity
Solution: (a) minority ¥ majority carrier
at 300 K. If each atom of the initial accep-
concentrations = ni2 tor impurity is exactly neutralized by one
Hence, minority carrier concentration = atom of antimony, find the amount of anti-
mony in micrograms required.
(1.5 ¥ 1016 )2
= 2.25 ¥ 1012 atoms/ m3 Given :
1020 Density of Ge = 5.32 gm/cm3
si = ni q( m n + m p ) = 5.32 ¥ 106 gm/ m3
""
Number of Sb atoms per gm 0.30 ¥ 10 20

0.3 ¥ 10 20 atoms =
= 5 ¥ 10 21 / cm 3 = 5 ¥ 10 27 /m 3 5 ¥ 10 27
Electron mobility in Ge = 0.38 m2 /Vs = 0.006 ¥ 10 -6 gm = 0.006 mgm.
Hole mobility in Ge = 0.18 m2 /Vs
Intrinsic carrier concentration in Ge 13. The donor concentration in n-type silicon
is 1 atom per 108 atoms. Find the tempera-
= 2.5 ¥ 1019 / m3 ture at which the Fermi level coincides
Electronic charge = 1.6 ¥ 10 -19 Coulomb with the edge of the conduction band as-
suming that the effective mass is equal to
Solution:
the true mass.
Concentration = nA
5 ¥ 1028
6.022 ¥ 10 23 atoms/(g ◊ atom)
n s Solution.: ND =
3 6
1 ¥ 108
=
d5.32 ¥ 25g/ m i ¥ 10
72.6g/atom = 5 ¥ 1020 atoms/ m3
The Fermi level EF = EC for ND = NC
= 11.03 ¥ 10 29 atoms/m3
It is known that NC = 4.82 ¥ 10 21 T 3/ 2 / m3
Doped Resistivity = 0.01 Wm, Intrinsic
Resistivity = 0.05 Wm 5 ¥ 1020 = 4.82 ¥ 10 21 T 3/ 2
1 5 ¥ 10 20
= qm n N D = ND ¥ 1.6 ¥ 10 -19 ¥ 0.38 T 3/ 2 = = 0.1037
rn 4.82 ¥ 10 21
1 a
T @ 0.1073 f 2 /3
a
= 0.1073 f 0.666
= 0.226 K
= = 100
0.01 14. An aluminium rod of dimension 5 mm ¥
100 ¥ 1019 0.03 mm ¥ 0.025 mm has the resistivity of
ND = = 16.45 ¥ 10 20 /m 3
1.6 ¥ 0.38 0.45 ¥ 10 -7 Wm . (a) What would be the
1 voltage across it, if the current of 5 mA
si = ni qm n = flows through it? (b) What is the amount
ri
of current that will flow if a voltage of
1 5mV is applied across it?
ni = - 19
0.05 ¥ 1.6 ¥ 10 (0.38 + 0.18) rl
Solution: R =
A
= 2.23×10 23 atoms/m 3
n2 0.45 ¥ 10 -7 ¥ 5 ¥ 10 -3
Hence, acceptor impurity = p = i = = 0.3 W
ND 0.03 ¥ 10 -3 ¥ 0.025 ¥ 10 -3
( 2.23 ¥ 10 20 ) 2 Hence, voltage drop = 5 ¥ 10 -3 ¥ 0.3
= = 0.30 ¥ 1020 holes/ m3
16.44 ¥ 10 20 = 1.5 mV
5 ¥ 1027 atoms of Sb = 1 gm 5 ¥ 10 -3
The current flow = = 16.7 mA
0.30
"#
15. Show that the ratio of maximum resistivity Since p > n, the semiconductor must be
r doped with acceptor impurities for mini-
to intrinsic resistivity is expressed as max mum resistivity.
ri
mn + m p Substituting this condition, the ratio be-
= . Find out the doping level for comes
2 mnm p
mn = 3mp that results in the rmax. r max 4 mp 2
= =
Solution: Intrinsic conductivity = si ri 2 mp 3 3
1 16. Obtain the energy difference between the
= qni ( m n + m p ) =
ri intrinsic level and the Fermi level in intrin-
Hence, the conductivity at any other dop- sic Si at 300 K (me = 1.1m, mp = 0.59 m).
ing level is expressed as
Ê 3ˆ Ê mp ˆ
s = q( nm n + pm p ) Solution: EF Ei = Á ˜ KT ln Á
Ë 4¯ Ë me ˜¯
R|S
= q nm n +
FG n IJ m
2
i
U|V = 1 Ê 3ˆ Ê 0.59 ˆ
|T H nK p
|W r = Á ˜ 1.38 ¥ 10 - 23 ¥ 300 ln Á
Ë 4¯ Ë 1.1 ˜¯
It is evident that resistivity will be maxi-
mum when the conductivity will be mini- = 3105
. ¥ 10 -21 ln(0.5364 )
mum. This maxima or minima can be ob-
tained after differentiating it and equating it = 3105
. ¥ 10 - 21 ( - 0.623) = - 1.9 ¥ 10 - 21
to zero, i.e.
1.9 ¥ 10 - 21
=
ds FG
= q mn - m p
ni2 IJ = 0, 1.6 ¥ 10 -19
2
dn n H K = 1.209 ¥ 10 -2 = 12.09 ¥ 10- 3 eV
mp mn
n = ni , p = pi The Fermi level is 12.09 meV below the
mn mp band gap centre of intrinsic Si.
17. Calculate the effective density of states in
s min = qni e m nm p + m n m p j the valence band for a semiconductor at
1 (a) typical maximum operating tempera-
= 2qni m n m p = , r max ture for a silicon device, and (b) typical
r max
maximum operating temperature for sili-
1 con chip fabrication.
=
2qni m n m p
Solution: It is known that the typical maxi-
r max qni ( m n + m p ) mn + m p mum operating temperature of silicon de-
= = Q.E.D vice is 175°C and that of the silicon chip
ri 2qni m n m p 2 m nm p
manufacturing operating maximum tem-
ni perature is 1000°C. Hence, these calcula-
If m n = 3m p , then n = , and p = 3ni tions are to be made based on these two
3
temperatures.
"$
NV (300 K) = 2.5049828 ¥ 10 22 /m3, 175°C 19. An n-type semiconductor has its Fermi
level at 0.25 eV below the conduction band
= 273 + 175 = 448 K, 1000°C = 1273 K.
edge. Estimate its dopant, majority, and
Ê 448 ˆ
3/ 2 minority carrier concentrations in equilib-
NV (175∞C) = NV (300 K) Á rium at room temperature. Assume ni =
Ë 300 ˜¯
1.6 ¥ 1016/m3.
3/ 2
= NV (300 K) (1.4933) - FE -E I
C F
Solution.: nn = NC e H KT K ,
= NV (300 K) (1.82488)
3/ 2
= 2.5049828 ¥ 10 22
a1.82488f NC = 2
F 2p mKT I ,
H h K 2
= 4.57 ¥ 1022 / m 3 EC EF = 0.25 eV, NC(300 K)

3/ 2 = 2.9 ¥ 1025/m3
Ê 1273 ˆ
NV (1000∞ C) = NV (300 K) Á
Ë 300 ˜¯ -
0.25
25 8.62 ¥ 105 ¥ 300
nn = 2.9 ¥ 10 e
= NV (300 K)(4.2433) 3/ 2
0.25
-
8.62 ¥ 10 -5 ¥ 300
= NV (300 K)(8.74) = 2.9 ¥ 10 25 e
= 2.5049828 × 1022(8.74) -
0 .25
= 2.9 ¥ 1025 e 8.62 ¥ 10 -5 ¥ 300
= 2.19 × 1023/m3
2.9 ¥ 10 25
18. Calculate the effective density of states in = 2.9 ¥ 10 25 e - 9.66744 =
the conduction band for a semiconductor e9.66744
at (a) typical maximum operating tempera- 2.9 ¥ 10 25
ture for a silicon device, and (b) typical = = 1.83 ¥ 1021/m3
1.5795 ¥ 10 4
maximum operating temperature for sili-
con chip fabrication. ni2 2.56 ¥ 10 32 11 3
pn = = 21 = 1.39 ¥ 10 /m .
Solution: nn 1.83 ¥ 10
F 448I 3/ 2 20. A p-type semiconductor has its Fermi level

NC (175∞C) = NC(300 K) at 0.25 eV above the valence band edge.
H 300 K Estimate its dopant, majority, and minority
= NC (300 K) (1.825) carrier concentrations in equilibrium at
room temperature. Assume ni = 1.6 ¥
a f
= 2.51 ¥ 1025 1.825 = 4.58 ¥ 1025 / m 3 1016/m3.
3/ 2
Ê 1273 ˆ Solution: pp = NV e
b
- EF - EV /KT g ,
NC (1000∞C) = NC (300 K) Á
Ë 300 ˜¯ 3/ 2
= NC (300 K )(8.741) NV = 2
F 2p m K T I
*
p
, EC EF = 0.25 eV,
GH h JK 2
a f
= 2.51 ¥ 1025 8.741 = 2.194 ¥ 10 26 / m 3 . NV (300 K) = 1 ¥ 1025/m3
"%
pp = 1 ¥ 10 25 e - 0.25 0.02586 = 2.56 ¥ 1010/m3.
= 1 ¥ 1025 e - 9.66744 2.56 ¥ 10 32

(c) ND = 1025/m3, pn =
10 25
1 ¥ 10 25 1 ¥ 1025
= = = 2.56 ¥ 107/m3.
e 9.66744 1.5794862 ¥ 10 4
= 0.63 ¥ 1021/m3 22. A semiconductor has the intrinsic carrier
concentration of 1.6 ¥ 1016/m3 and band
ni2 2.56 ¥ 10 32 11 3 gap 1.25 eV at room temperature. Estimate
np = = 21 = 4.04 ¥ 10 /m .
pp 0.63 ¥ 10 NC and NV for the effective mass ratio of
21. Estimate the majority and minority carrier mn* / m*p = 4.
concentrations in an intrinsic semiconduc-
tor with intrinsic concentration of 1.6 ¥ Solution.: ni2 = nn pn
1016/m3 and donor doping concentrations of = NC NV exp ( EV EC )/ KT , EC - EV = 1.25 eV,
-
(a) 1018/m3, (b) 1022/m3, and (c) 1025/m3.

KT = (8.62 × 105 eV/K) 300 K
Solution: The donor doping concentrations
of 1018/m3, 1022/m3, and 1025/m3 corre- = 0.0258 eV
spond roughly to a light, medium and
2.56 ¥ 10 32 = NC NV exp 1.25/ 0.2586
heavy doping in silicon.
(a) ND = 1018/m3, NA = 0 = NC NV exp - 48.3372
3/ 2
n= 2 x +
FG IJ = N
1 ni2
- NA +
ni2 NC mn*F I = 43/2 = 2 2
3/ 2
= 23 = 8,
2 xH K D
ND - N A NV
= GH JK
m *p
d i
ni2
@ ND + @ ND, NC = 8NV and 8N2V
ND
ni = 1.6 ¥ 1016/m3. = 2.56 ¥ 1032 exp48.3372
ni2 = 2.56 ¥ 1032, ND = 1018/m3 NV2 = (0.32 ¥ 1032 exp48.3372)
n2 2.56 ¥ 10 32 NV = (0.566 ¥ 1016 exp24.1696)

pn = i = = 2.56 ¥ 1014/m3
ND 1018 = 0.566 ¥ 1016 ¥ 3.14 ¥ 1010 = 1026/m3
2.56 ¥ 10 32 NC = 8NV = 8 ¥ 1026/m3.
(b) ND = 1022/m3, pn =
10 22
Questions for Practice semiconductor? What is the importance of

valance shells and valance electrons? What
1. Give examples of good conductors. What is energy gap? Differentiate between semi-
is an insulator? What is the mechanism by conductors, conductors, and insulators on
which conduction takes place inside the the basis of band gap.
"&
2. What is covalent bond? Under what condi- electrons in the conduction band? Are n-
tion do atoms form covalent bonds? What type and p-type materials neutral? How
are intrinsic semiconductors? What is dop- does a semiconductor differ from a con-
ing? What is the name of the impurity that ductor? What is meant by doping?
makes semiconductor n-type? What are 9. What are donor and acceptor impurities?
minority carriers in n-type and in p-type? What proportion of impurity should be
Why? What are the impurities that make a mixed in an intrinsic Si or Ge for manufac-
semiconductor p-type? What are majority turing junction diode or BJT?
and minority charge carriers in p-type ma- 10. What is meant by Fermi level in semicon-
terial? ductor? Where does the Fermi level lie in
3. What are the two conduction processes in an intrinsic semiconductor? Prove that the
semiconductor? What are the approximate Fermi level in an n-type material is much
voltages required to break open the cova- closer to the conduction band. Prove that
lent bonds in Ge and Si? What are majority the Fermi level in a p-type material is much
and minority carriers in n-type and p-type closer to the valence band.
materials? Name three elements that are 11. Show the donor and acceptor levels on the
used as n-type and p-type impurities. What band diagram of n-and p-type materials.
is the main factor for controlling the ther- Define diffusion constant of electrons and
mal generation and recombination? holes. Define mean life-time of a carrier.
4. What is the meaning of intrinsically neu- 12. Define mobility of a carrier. Show that
tral? What is the forbidden energy gap? mobility constant of electron is larger than
How does it come in? How much is its that of a hole? The Fermi level of intrinsic
magnitude in Ge and Si? semiconductor lies in the middle of the
5. What happens to the conductivity of the band gap but in an n-type semiconductor it
semiconductor with the rise in the tem- is nearer to the conduction band. What is
perature? Do metals also exhibit the same the effect of temperature on the position of
behaviour? Fermi level of a semiconductor?
6. Which of the two semiconductor materials 13. In an n-type Si the donor concentration is
Si or Ge has larger conductivity/ resistivity 1 atom per 2 ¥ 108 silicon atoms. Assum-
at room temperature? How does the con- ing that the effective mass of electron is
ductivity or resistivity of the semiconduc- equal to the mass of electron at rest. Find
tor materials vary with temperature? In the value of temperature at which the
which bands the movement of electrons Fermi level will coincide with the edge of
and holes take place? the conduction band.
7. Can both types of current flow, i.e due to 14. The current of p-n junction is expressed as
holes and electrons, take place in one par-
ticular type of semiconductor? What is the
Ï Ê qV ˆ ¸
I = I o Ìexp Á - 1˝ . The diode cur-
ratio of majority and minority charge carri- Ó Ë h K T ˜¯ ˛Ô
ers in intrinsic and extrinsic semiconduc- rent is 0.5 mA at V = 0.34 V and 15 mA at
tors? 0.44 V. Calculate the value of h assuming
8. Why does the fifth valent element not lib- KT/q = 25 mV.
erate as many holes in the valence band as 15. Calculate the conductivity of an n-type
semiconductor having electron density
"'
1021/m3 and mobility 1200 cm2 /Vs (d) four valence electrons.
(IETE June, 1996) 2. Two atoms of the semiconductor are held
(Hints: s = ( nm n + pm p )q , as n >> p, together by
(a) valance bond
s = nm nq = 10 21 ¥ 1200 ¥ 1.6 ¥10 -19 (b) ionic bond
(c) metallic bond
= 1.92 ¥ 105 / W cm ) 3. Intrinsic semiconductor at absolute zero
16. The resistivity of intrinsic Ge at 300 K is behaves as
0.47 W. The electron and hole mobilities (a) insulator
are 0.38 and 0.18 m2/Vs, calculate the in- (b) metal
trinsic carrier density at 200 K. (c) semiconductor
(IETE Dec., 1996) 4. An electron in conduction band has
1 1 (a) no charge
(Hints: r = = = ni ( m n + m p ) q (b) higher energy than electron in the val-
s 0.47 Wm
ance band
= ni ( 0.38 + 0.18)1.6 10 19 (c) lower energy than the electron in the
valance band
= 0.896ni ¥ 10 -19 5. At room temperature when voltage is ap-
1019 plied to the intrinsic semiconductor
ni = = 2.38 ¥ 1019/m3.) (a) electrons move towards the positive
0.42 terminal and holes move towards the
17. If the carrier mobility in a sample is negative terminal
3 m2/V sec at 0°C, what is the diffusion (b) both holes and electrons move to-
constant of carrier at that temperature wards the positive terminal
given that Boltzmann constant is 1.38 ¥ (c) booth holes and electrons move to-
1021J/K. wards the negative terminal
(IETE Dec., 1996) 6. With the increase in the temperature of the
FGHints: V D KT 1.38 ¥ 10 -21T intrinsic semiconductor
T = = = (a) energy of atom increases
H m q 1.6 ¥ 10 -19
(b) holes are generated in the conduction
T 273 band
= = , (c) resistance of the semiconductor in-
11600 11600
creases
273 ˆ (d) atomic radius decreases
D =3¥ = 0.076 m2/s˜
11600 ¯ 7. Fifth group elements are called
(a) donor impurity
(b) acceptor impurity
Multiple Choice Questions (c) none
8. The p-type impurities create
1. A Ge atom contains (a) excess number of electrons
(a) four orbits (b) excess number of holes
(b) two orbits (c) excess number of ionized positive
(c) five valence holes charges
#
9. If small amount of antimony is added to 17. When an atom is ionized, it releases

silicon (a) negative charge carrier
(a) its resistance increases (b) positive charge carrier
(b) the silicon will become p-type (c) negative ion
(c) it contains more free electrons than (d) positive ion
holes 18. When an atom loses an electron it be-
10. If small amount of gallium is added to ger- comes
manium (a) positively charged
(a) it becomes p-type material (b) negatively charged ion
(b) it has more number of electrons (c) electrically neutral
(c) it becomes an insulator
(d) positive charge carrier
11. Conduction band is
19. Resistivity of semiconductor depends
(a) the same as valance band
upon
(b) always located at the top of the crystal
(c) is called forbidden band (a) shape and its length
(d) the energy band above forbidden (b) its carrier concentration
band (c) neither shape nor carrier concentration
12. Forbidden band is 20. A n-type material induces an impurity en-
(a) above conduction band ergy level in
(b) below valance band (a) the energy gap
(c) between valance and conduction (b) conduction band
band (c) valance band
13. The concentration of minority carriers in (d) none of these
the n-type semiconductor depends on 21. The process of doping
(a) doping technique (a) increases conductivity
(b) temperature of the material (b) decreases conductivity
(c) quality of intrinsic Ge or Si (c) neither increases nor decreases con-
(d) number of donor atoms ductivity
14. A neutral semiconductor 22. Resistivity of a good conductor is
(a) has no free charge carrier (a) 10 8 Wm (b) 10 8 Wm
(b) has equal number of electrons and 6
holes (c) 10 Wm (d) 10 12 Wm
(c) has no minority carrier 23. Resistivity of a good insulator is
(d) has no majority carrier (a) 10 8 Wm
15. A p-type material is (b) 10 8 Wm
(a) neutral
(c) 1010 or 1012 Wm
(b) negatively charged
(c) positively charged (d) 10 -10 or 10 -12 Wm
(d) insulator 24. Semiconductor material includes
16. A n-type material has (a) only elements
(a) electrons as majority carriers (b) only intermetallic compounds
(b) holes as majority carriers (c) both elements and intermetallic com-
(c) both positive and negative charge car- pounds
riers are equal in number
#
25. Every time a covalent bond is broken it re- 33. At higher temperature conductivity is bet-
sults in ter in
(a) free electron (a) semiconductor
(b) free hole (b) metal
(c) electron hole pair (c) insulator
26. Intrinsic semiconductor contains 34. Temperature coefficient of semiconductor
(a) more number of electrons is
(b) more number of holes (a) positive
(c) equal number of electrons and holes (b) negative
(d) equal number of negative and positive (c) neither positive nor negative
immobile charges (d) zero
27. On an average at 25∞ C in a Si crystal, out 35. Extrinsic semiconductor is
of 1019 bonds (a) pure semiconductor
(a) one is broken (b) impure semiconductor
(b) no bond is broken (c) neither pure nor impure
(c) infinite bonds are broken 36. Conductivity of a semiconductor can be
controlled by
28. At room temperature in silicon, out of 1010
(a) adding impurity
bonds
(b) increasing size
(a) one bond is broken
(c) changing temperature
(b) infinite bonds are broken
37. A semiconductor is called intrinsic even if
(c) no bonds are broken
impurity is
29. Normally used semiconductor materials (a) one part in hundred million parts of
are semiconductor
(a) C, Na (b) 100 in 100 million parts of semicon-
(b) Si, Ge ductor
(c) GaAsP (c) 1000 in 100 million parts of semicon-
30. Good conductors are ductor
(a) silver, aluminium, copper etc. 38. In an intrinsic silicon the band gap is
(b) glass, quartz (a) 1.12 eV (b) 0.7 eV
(c) Ge, Si (c) 2 eV (d) 0.2 eV
31. With the increase in temperature resistivity 39. In an intrinsic Ge the band gap is
of a conductor (a) 1.12 eV (b) 0.7 eV
(a) increases (c) 0.2 eV (d) 0.6 eV
(b) decreases 40. Conductivity of pure Ge is approximately
(c) remains constant (a) 2.2 S/m (b) 5 ¥ 10 4 S/m
4
32. With the increase in temperature the resis- (c) 5 ¥ 10 S/m
tivity of the semiconductor 41. Conductivity of pure Si is nearly
(a) increases
(a) 2.3 ¥ 109 S/m (b) 5 ¥ 10 4 S/m
(b) decreases
(c) neither increases nor decreases (c) 3.85 ¥ 107 S/m
#
42. Conductivity of Al is 51. Resistivity of intrinsic Si is nearly

(a) 3.85 ¥ 10 S/m 7 (a) 2300 Wm (b) 23 Wm
(c) 0.23 Wm
(b) 6.25 ¥ 107 S/m 52. Resistivity of intrinsic Ge is nearly
(c) 5 ¥ 10 4 S/m (a) 0.46 Wm (b) 46 Wm
(c) 460 Wm (d) 1000 Wm
43. Conductivity of glass is 53. The value of q / KT at room temperature is
(a) 1.54 S/m approximately
(b) 5.88 ¥ 1012 S/m (a) 40/ V (b) 400/V
(c) 110 16 S/m (c) 0.40/V
44. Conductivity of hard rubber is 54. The conduction band in intrinsic semicon-
ductor is
(a) 5 ×10-4 S/m (a) above the valence band
(b) 5.88 ×10 -12 S/m (b) below the valence band
(c) in the valance band
(c) 10-16 S/m 55. Mobile electrons are found in
45. Mobility of holes in intrinsic Si is (a) conduction band
(b) valence band
(a) 0.048 m2 /Vs (b) 0.135 m2 /Vs
(c) below the valence band
(c) 1350 m2 /Vs (d) 480 m2 /Vs (d) in the band gap
46. Mobility of electrons in intrinsic Si is 56. Mobile hole are found in
(a) conduction band
(a) 0.135 m2 /Vs (b) 0.048 m2 /Vs (b) valence band
(c) 480 m2 /Vs (d) 13.5 m2 /Vs (c) below the valence band
47. Mobility of electrons in intrinsic Ge is (d) in the band gap
57. Fermi level in the intrinsic Si/Ge is
(a) 0.39 m2 /Vs (b) 0.19 m2 /Vs (a) in the middle of the band gap
(c) 390 m2 /Vs (d) 190 m2 /Vs (b) near the valance band
48. Mobility of holes in intrinsic Ge is (c) near the conduction band
58. The energy required to dislodge electrons
(a) 0.39 m2 /Vs (b) 0.19 m2 /Vs
from n-type Si is
(c) 3900 m2 /Vs (d) 1900 m2 /Vs (a) 0.05 eV (b) 5 eV
49. Carrier density in intrinsic Si is (c) 50 eV
(a) 1.5 ¥ 1016 /m 3 (b) 15 ¥ 1016 /m 3 59. The donor energy band is available in n-
type material in the
(c) 150 ¥ 1016 /m 3 (a) conduction band
50. Electron hole pair in intrinsic Ge crystal at (b) valance band
300K is nearly (c) in the band gap
(a) 2.5 ¥ 1019 /m3 60. The acceptor energy band is available in
p-type material in the
(b) 240 ¥ 1019 /m3 (a) band gap
(c) 2400 ¥ 1019 /m3 (b) conduction band
(c) in the valance band
#!
61. The diffusion constant of electron in Si is 69. The minority carrier in n-type material are
(a) 35 ¥ 10 -4
m /s 2 (a) electrons
-4
(b) holes
(b) 0.34 ¥ 10 m 2/s (c) ionized negative charge
(c) 3400 ¥ 10 -4 m2/s 70. The majority carriers in p-type material are
62. The diffusion constant of holes in Si is (a) holes
(a) 12 ¥ 10-4 m 2/s (b) electrons
(c) immobile positive charge
(b) 0.13 ¥ 10-4 m2 /s 71. In order to get excess electrons from the
(c) 1300 ¥ 10-4 m2 /s intrinsic semiconductor one can add to tet-
63. The diffusion constant of electrons in Ge ravalent element
is (a) pentavalent element
(b) trivalent element
(a) 100 ¥ 10-4 m2 /s
(c) tetravalent element
(b) 99 ¥ 104 m2/s 72. In order to get excess holes from the in-
trinsic semiconductor one can add to tetra
(c) 9900 ¥ 10-4 m2 /s
valent element
64. The diffusion constant of holes in Ge is
(a) pentavalent element
(a) 49 ¥ 10 -4 m 2/s (b) trivalent element
(b) 0.47 ¥ 10 -4 m 2/s (c) tetravalent element
73. Electrons in the outermost orbit are called
(c) 4700 ¥ 10 -4 m2/s
(a) valence electrons
65. The density of Ge at 25°C is (b) conduction electrons
(a) 5.3 ¥ 109 kg/m3 (c) donor electrons
74. Energy of electrons in bigger orbit is
(b) 533 ¥ 109 kg/m 3 (a) higher (b) lower
(c) constant
(c) 0.53 ¥ 109 kg/m 3
75. The forces holding the Si/ Ge atoms to-
66. The density of Si at 25°C is gether in a crystal are called
(a) 2.33 ¥ 10 9 kg/m 3 (a) valance bond (b) ionic bond
(c) metallic bond
(b) 233 ¥ 109 kg/m 3 76. Doped crystal is called
(c) 0.0233 ¥ 109 kg/m 3 (a) intrinsic (b) extrinsic
(c) both
67. The intrinsic carrier concentration of elec-
77. Velocity of electron is
tron in Ge at 25°C is
(a) proportional to its mobility
(a) 2.5 ¥ 1010 atoms/m 3 , (b) inversely proportional to its mobility
(b) 0.025 ¥ 1019 atoms/m 3 (c) constant
78. Velocity of holes/electrons are propor-
(c) 250 ¥ 1019 atoms/m3
tional to
68. The majority carrier in n-type material are (a) electric filled
(a) electrons (b) magnetic field
(b) holes (c) inverse of magnetic field
(c) ionized positive charge
#"
79. Ionization energy of As, P and Sb in Ge are (a) L / qA( nm n + pm p )

arranged in sequence as
(b) qA( nm n + pm p ) / L
(a) 0.045 eV, 0.049 eV, 0.039 eV
(b) 0.049 eV, 0.039 eV, 0.045 eV (c) AL / qA( nm n + pm p )
(c) 0.039 eV, 0.045 eV, 0.049 eV (d) qA(nmn + pm p)/L
80. Ionization energy of As, P and Sb elements 89. The resistivity of a material is expressed as
in Si crystal are (a) L / qA( nm n + pm p )
(a) higher than that in Ge (b) qA( nm n + pm p )/ L
(b) lower than that in Ge
(c) equal to Ge (c) 1/ qA(nìn + pì p )
81. Ionization energy decreases slightly with 90. The conductivity of a material is expressed
(a) increasing impurity contents as
(b) decreasing impurity contents
(c) remains constant (a) q( nm n +p m p )
82. An intrinsic semiconductor is (b) qA / ( nm n + p m p )
(a) pure
(b) impure (c) 1/ q( nm n + pm p )
(c) free from impurity 91. The Fermi level of an intrinsic semicon-
83. The intrinsic semiconductor has ductor lies
(a) more electrons (a) near conduction band
(b) more holes (b) near valence band
(c) none of the two (c) in the middle of the valence and con-
84. At room temperature the intrinsic semi- duction band
conductor behaves as 92. The Fermi function is expressed as
(a) metal
(b) semiconductor { b
(a) 1/ 1 + exp
g
E - EF / KT
}
(c) insulator
85. The extrinsic semiconductor at room tem- (b) 1/ {1 + exp
b g
- E - EF / KT
perature has
}
(a) free charge carriers (c) exp -( E - EF )/ KT
(b) no free charge carriers 93. The primary bonds are
(c) qA = (nm n + pm p) (a) ionic, metallic, and vander Waal bonds
86. An n-type material has more numbers of (b) ionic, covalent, and vander Waal
(a) free electrons bonds
(b) free holes (c) ionic, covalent, and metallic
(c) none of the above. 94. The mean free path in an ideal crystal
87. An p-type material has more numbers of without imperfections and impurities is
(a) free electrons (a) infinite at 0 K
(b) free holes (b) zero at 0 K
(c) none of the above (c) infinite at all temperatures
88. The resistance of a material is expressed (d) zero at all temperatures
as
##
95. Glass and Bakelite are (a) J n = {qnmn E + qDn ( dn / dx)}

(a) crystalline
(b) amorphous (b) Jn = {qnm n E - qDn ( dn / dx )}
(c) solid solution (c) J n = {qnmn E - AqDn ( dn / dx)}
96. With increase in temperature, average ve- 104. The drift plus diffusion current density of
locity of atom
(a) increases holes in amp/ m 2 is expressed as
(b) decreases (a) J p = qnm p E + qDp ( dp / dx )
(c) remains constant (b) J p = qnm p E - qDp ( dp / dx )
97. The Fermi level in a n-type material is ex-
pressed as (c) J p = qnm p E qDp A( dp / dx )
(a) EC - KT ln( NC / nn ) 105. Electron population in silicon is not
(b) EC + KT ln( NC / nn ) (a) zero in the forbidden band
(b) zero in the conduction band at 0 K
(c) EC - KT ln( N D / nn )
(c) zero at the conduction band edge EC
98. The Fermi-level in a p-type material is ex- (d) zero in the conduction band at room
pressed as temperature.
(a) EV - KT ln( NV / p p ) Explanation:(d) The carrier concentration
(b) EV + KT ln( NV / p p ) is zero in the forbidden band. At 0 K, elec-
trons are filled in the available states only
(c) EV KT ln( N D / pn )
upto the Fermi level, which lies below the
99. The VT is expressed as conduction band edge (EC) and hence, the
(a) KT / q (b) q / KT concentration is zero in the conduction
(c) KTq (d) nKTq band. Also from density-of-state function,
100. The diffusion constant and the mobility of the number of available states at the band
electron are related as edges is always zero. Hence, conduction
(a) Dn / m n = KT / q electrons in the conduction band due to
thermal generation from the valence band
(b) Dn / m n = q / KT
as well as due to dopants are present in the
(c) Dn / m n = KTq silicon at all temperatures.
101. The diffusion constant and the mobility of 106. The density of states function for holes is
electron and hole are related as (a) zero in the valence band edge (EV)
(a) Dn / m n = KT / q (b) zero in the forbidden band edge
(b) Dn / m n = q / KT = m p / Dp (c) zero in the complete conduction band
(d) zero in all bands other than the valence
(c) Dn / m n = KTq = m p / Dp band. Explanation is presented in
102. The diffusion current is influenced by Q.105.
(a) concentration gradient 107. The Fermi-Dirac statistics is based on
(b) electric field (a) electron and photons
(c) electrostatic field (b) photons and protons
103. The drift plus diffusion current density of (c) electrons and holes
electron in amp/ m 2 is expressed as (d) Gas molecules
#$
Explanation : Fermi-Dirac statistics are clusion principle, i.e. the concept of finite
valid for particles which obey the Pauli ex- limited occupancy of state applies.
Answers to Multiple Choice Questions

1. (d) 2. (a) 3. (a) 4. (b) 5. (a) 6. (a)
7. (a) 8. (b) 9. (c) 10. (a) 11. (d) 12 (c)
13. (b) 14. (b) 15. (a) 16. (c) 17. (a) 18. (a)
19. (b) 20. (a) 21. (a) 22. (a) 23. (c) 24. (c)
25. (c) 26. (c) 27. (b) 28. (a) 29. (b) 30. (a)
31. (a) 32. (b) 33. (a) 34. (b) 35. (b) 36. (a)
37. (a) 38. (a) 39. (b) 40. (a) 41. (b) 42. (a)
43. (b) 44. (b) 45. (a) 46. (a) 47. (a) 48. (b)
49. (a) 50. (a) 51. (a) 52. (a) 53. (a) 54. (a)
55. (a) 56. (b) 57. (a) 58. (a) 59. (c) 60. (a)
61. (a) 62. (a) 63. (a) 64. (a) 65. (a) 66. (a)
67. (a) 68. (a) 69. (b) 70. (a) 71. (a) 72. (b)
73. (a) 74. (a) 75. (a) 76. (b) 77. (a) 78. (a)
79. (a) 80. (a) 81. (a) 82. (a) 83. (c) 84. (c)
85. (b) 86. (a) 87. (b) 88. (a) 89. (c) 90. (a)
91. (c) 92. (a) 93. (c) 94. (a) 95. (b) 96. (a)
97. (a) 98. (b) 99. (a) 100. (a) 101. (a) 102. (a)
103. (a) 104. (b) 105. (d) 106. (a) and (b) 107. (c)
2
Physical Phenomenon in
Homojunction
2.1 Introduction
All semiconductor devices contain one or more p-n junctions. The junction family is shown in Fig. 2.1.
Figure 2.1 Family of p-n junctions

#&
A homojunction is the junction formed between p- and n-type semiconductors of the same material.
Since, the material of the junction is the same, both p-type and n-type semiconductors have the same
bandgap. Hence, homojunction is formed between semiconductors of the same bandgap. A heterojunction
is the junction formed between two types of semiconductors having different bandgaps. An abrupt
junction is one in which the impurity type changes abruptly at a plane within the semiconductor bulk. On
the other hand, a grown or graded junction is one in which impurity type changes linearly through zero
concentration from one type to the other.
The working of one p-n homojunction under different conditions has been taken up here, in order to
understand the behaviour of any semiconductor device. Practical examples of semiconductor device
with number of homojunctions are,
∑ One homojunction device fi Semiconductor diodes, UJT, etc.
∑ Two homojunction devices fi BJT/FET families
∑ Three homojunction devices fi SCR family
The two separate pieces of p-type and n-type semiconductor materials are shown in Figs. 2.2a and b.
The p-type semiconductor in Fig. 2.2a has holes in majority where one or two electrons have also been
shown. Since, a p-type material has a large number of acceptor impurities and all of them are assumed
to be ionized, holes are majority carriers in it and electrons are minority carriers. Similarly, the n-type
semiconductor has many electrons and one or two holes.
Figure 2.2 Sample of p- and n-type materials

When one type of charge carriers is more than the other type it is called majority charge carrier and
the other is called minority charge carrier. For example, holes represented by pp are majority charge
carriers and electrons represented by np are minority charge carriers in p-type material. Similarly, nn and
pn are majority and minority charge carriers in the n-type material. These levels of concentrations of
carriers have been demonstrated in Fig. 2.3. In the representation of pp and np, subscript p represents
p-type material. Similarly, in the representation of nn and pn, the subscript n represents n-type material.
Physical Phenomenon in Homojunction
#'
Figure 2.3 Carrier concentration representation

The top of the valence band of most semiconductors occur at k = 0 i.e. at effective momentum equal
to zero. A typical band structure of the semiconductor near the top of the valence band is shown in
Fig. 2.4. The bottom of the conduction band in some semiconductors occur at k = 0. Such semiconductors
are called direct bandgap materials. Semiconductors Such as GaAs, InP, In GaAs, etc. are direct bandgap
semiconductors. In other semiconductors, the bottom of the conduction band does not occur at k = 0.
Such semiconductors (Si, Ge, AlAs etc) are indirect bandgap semiconductors.
Figure 2.4 Energy levels in p- and n-materials
2.2 Qualitative Analysis of Homojunction

Here we will first analyze what happens when a p-type material is brought in contact with an n-type
material qualitatively as shown in Fig. 2.5. The diffusion of majority carriers (holes) from left to right
and of electrons from right to left of the homojunction starts as indicated by the arrows in this figure.
Figure 2.5 Momentary diffusion across homojunction

$
The movement of electrons from one side to the other is much more than the number of holes, i.e. nn
> np or ND > NA (as the mobility of electrons is much higher than that of holes). But for simplicity the
number of holes have been shown equal to that of the electrons in Fig. 2.2(a). Hence, the current due to
electrons will be higher than that due to holes for the same value of voltage. Also, thermally generated
hole (one) and electron (one), as an example, have been shown in Figs. 2.2(a) and (b). Figure 2.6
indicates the deptetion region across a junction.
Figure 2.6 Carriers near homojunction diffused away
Figure 2.7 Formation of concentration gradient
The majority carriers holes (pp) on the left of the homojunction interface in the p-type material are
much larger than holes (pn) in the n-type material on the right side of the homojunction interface. This
way the holes of p- and n-materials form a concentration gradient between them as depicted in Fig. 2.7
and diffuse from p-type towards n-type material. Similarly, large number of electrons (nn) in the n-type
material diffuse towards the p-type material as electrons (np) in the p-type material are much less than
those in n-type material. So formation of concentration gradient of n-type carriers from n-type towards
p-type material also takes place.
It is but natural that the electrons and holes nearer to the homojunction interface will diffuse first
from one side to the other leaving behind ionized atoms on both sides of the homojunction as shown in
Fig. 2.3. Now the electrons and holes which are farther away from the homojunction interface will
diffuse. This process of diffusion is a momentary phenomena. As soon as they diffuse to the other side,
they recombine due to the large number of majority charge carriers of opposite polarity already present
there. Thus, the probability of collisions with opposite types of charge carriers, i.e. holes with electrons
$
in the n-type and electrons with holes in p-type become very high and they recombine immediately.
Each diffusing electron leaves behind a bound positive immobile charge represented by an encircled
positive sign . Similarly, each diffusing hole leaves behind one negatively bound immobile charge
represented by an encircled negative sign . These bound immobile charges stay on the opposite
faces of the homojunction interface as shown in Fig. 2.8. This process of diffusion of either type of
charge carriers does not continue indefinitely. It stops as soon as the force due to concentration gradient
of charge carriers equals the force of repulsion by the immobile charges on the opposite faces of the
homojunction interface.
The region having the immobile charges (no charge carriers) of width Wo in Fig. 2.8, is called space
charge region. This region is also called depletion region as it is depleted of the charge carriers. Since
this region is devoid of charge carriers, it behaves as an insulator. Thus, on two-faces of an insulator
two opposite types of charges are established that result in a capacitance similar to a parallel plate
capacitor. This charged capacitance is equivalent to a battery that depletes the mobile charge carriers of
both sides of the homojunction and hence, the field created due to the two opposite types of immobile
charges is called potential barrier or depletion barrier.
We can conclude that the chance of diffusion and recombination of holes and electrons present near
the boundary is much higher than those far away from the homojunction interface. It is evident that as
soon as the homojunction formation takes place, net opposite types of immobile charges (ionized atoms)
are formed on both sides of the homojunction interface. These immobile negative and positive charges
form an insulator of length Wo that essentially behaves as a battery. Thus, formation of potential barrier
is an inherent phenomenon across any p-n homojunction. This potential barrier does not allow either
type of the majority carriers to cross the homojunction without any external influence on it. Hence, no
carrier can cross the homojunction and no current can flow without any external influence.
Figure 2.8 p-n homojunction with depletion width Wo
2.3 Biasing of Homojunction

We know that the application of external voltage (V) can control the depletion width Wo and the depletion
barrier voltage yo. This type of external voltage is applied as per the need of the working of a p-n
homojunction as a device. Application of the external voltage is called biasing. The name biasing has
$
been derived from the similar type of behaviour of one driven by the opinion or idea of the other. When
one starts following others ideas or statements, we often say one is biased by the ideas of the other.
Thus, if the external voltage applied adds to the polarity of inherent potential barrier present across the
homojunction, it is called reverse bias. While on the other hand if the externally applied voltage reduces
the magnitude of the inherent potential barrier present across the homojunction, it is called forward bias.
Forward bias enhances the flow of carriers across the homojunction and hence the current. The reverse
bias increases the depletion region width from Wo to W¢o and the depletion voltage from yo to y o¢ as
shown in Fig. 2.9.
2.3.1 Forward Biasing of p-n Homojunction

The externally applied d.c. voltage V across the homojunction opposes the inherent barrier potential y o¢
as in Fig. 2.10. It is called forward bias. The other type of explanation for the forward bias can be given
as p-type material connected with positive polarity and n-type material connected with negative type of
polarity .It is evident that the application of external forward bias decreases both the potential barrier
voltage Y ¢o to y ≤o and the depletion region W¢o to Wo≤ as shown in Fig. 2.10.
Figure 2.9 Depletion width with reverse bias
Figure 2.10 Depletion width with forward bias

$!
Figure 2.10 has two batteries (the inherent barrier potential battery yo≤and the external forward bias
voltage V ) connected in parallel. If such types of connection exist in physical world, the smaller battery
gets fused immediately. Hence, application of the external forward bias of larger magnitude nullifies the
existence of the inherent potential barrier across the homojunction and allows either type of carriers to
cross the homojunction resulting in the electric current flow.
With increasing forward bias, more electrons and holes cross the homojunction. This reduces the
depletion width and hence, reduces the depletion barrier. Further increase in the forward bias increases
the crossing of more number of carriers across the homojunction. The increase in carriers is very rapid
for very small increase in the forward bias voltage.
2.4 Quantitative Analysis of Homojunction

Figure 2.11 shows isolated pieces of p- and n-type materials with the positions of Fermi level, valence
band, conduction band, vacuum level, electron affinity energy (c), work function energy (fsn, fsp) and
the formation of p-n homojunction. The electron affinity is defined as the energy difference between
conduction band and vacuum level. The work functions fsn and fsp are defined as the energy difference
between Fermi level and vacuum level.
Electrons and holes combine at the homojunction interface leaving behind ionized acceptor atoms in
the p-region equal to the number of ionized donor atoms in the n-region. Figure 2.12 represents the
abrupt homojunction and a rough demonstration of the charge density diagram is shown in Fig. 2.13.
Figures 2.14 and 2.15 depict the corresponding potential and field across the homojunction. The areas
in Fig. 2.13 enclosed on each side of the homojunction interface must be equal.
Figure 2.11 Isolated pieces of p- and n-type along with homojunction

$"
Hence, qNAxp = qNDxn

Here, ND is the donor density in n-type material and NA density of acceptor in p-type material. As ND
is considerably larger than the NA , the depletion region extends farther into p-region. Here, voltages yp
and yn are the work functions of the p-type and n-type materials respectively. The difference in the fall
of energy yD = yp yn from p-type to n-type material is due to the alignment of the Fermi levels in the
two materials. In an unbiased p-n homojunction, both hole and electron currents are zero.
Figure 2.12 Abrupt p-n homojunction
Figure 2.13 Space charge
Figure 2.14 Electrostatic potential
Figure 2.15 Electric field variation

$#
The Poissons equation relates the gradient of the electric field to the local space charge at any point
as
dE( x ) q
= ( ND - N A ) (2.4.1)
dx e
where, ND and NA are ionized donor and acceptor impurities forming space charges.
Let us now express total hole current density without any forward bias across the homojunction as
dp ( x) ¸
{
Jp(x) = q m p p( x) E ( x) - Dp
"" "" ! " dx"!˛
˝ =0 (2.4.2)
Drift Diffusion
or,
FG 1 IJ F dp( x) I = mp
E(x) (2.4.3)
H p( x) K H dx K D p
Dp KT
Using Einstein relation: = (2.4.4)
mp q
Combining Eqns. 2.4.3 and 2.4.4 yields
FG 1 IJ F dp( x) I = m E( x) = FG m IJ F -dy ( x) I = F q I F -dy ( x)I

p p
(2.4.5)
H p( x) K H dx K D p H D K H dx K H KT K H dx K
p
or,
F KT IJ FG dp( x)IJ
dy (x) = G (2.4.6)
H q K H p( x) K
Equation 2.4.6 can be integrated to yield the built in voltage from p-side to n-side having impurity
densities as pp and pn in two-sides and potentials yp and yn
yn pn
Ê KT ˆ dp( x )
Ú
yp
d y ( x) = Á
Ë q ˜¯ z
pp
p( x )
dx (2.4.7)
Ê KT ˆ Ê pn ˆ Ê KT ˆ Ê p p ˆ
or, yn yp = Á ln = ln (2.4.8)
Ë q ˜¯ ÁË p p ˜¯ ÁË q ˜¯ ÁË pn ˜¯
Ê KT ˆ Ê p p ˆ
The depletion voltage = yD = yn yp = Á ln (2.4.9)
Ë q ˜¯ ÁË pn ˜¯
The limits of integration set potentials yn and yp in the neutral n-side and neutral p-side. ND and NA
(equal to the doping levels of donor and acceptor impurities) denote electron and hole densities in n-type
and p-type materials respectively. In other words,
pp = NA and nn = ND
$$
We can now write the equivalent expression as

q
pp VD nn
= exp KT = (2.4.10)
pn np
From law of mass action nn pn = ppnp = ni2. Hence, Eqn. 2.4.9 reduces to
Ê KT ˆ Ê N A ˆ Ê KT ˆ Ê N A ˆ Ê KT ˆ Ê N A N D ˆ
yD = Á ln Á = Á ln = ln (2.4.11)
˜
Ë q ¯ Ë pn ¯ ˜ Ë q ˜¯ ÁË ni2 / N D ˜¯ ÁË q ˜¯ ÁË ni2 ˜¯
Example
The intrinsic carrier concentration in Ge at room temperature is = ni = 2.5 ¥ 1019/m3 and that of the Si
= ni = 1.5 ¥ 1016/m3. If doping levels in both types of materials are the same to the extent of ND = NA =
1021/m3, the built-in voltage is
yD(Ge) = 0.025 ln
FG 10 42
IJ = 0.025 lnFG 10 IJ = 0.025 ln (1600) = 0.025 ¥ 7.38 = 0.184 V
4
2 38
H 2.5 ¥ 10 K H 6.25K
yD(Si) = 0.025 lnG
F 10 42
IJ = 0.025 lnFG 10 IJ = 0.025 ln (10 ) 0.025 ln (2.25)
10
10
2 32
H 1.5 ¥ 10 K H 2.25K
= 0.25 ln(10) 0.025 ln (2.25) = 0.25 ¥ 2.3026 0.025 ¥ 0.02
= 0.576 V 0.02 V = 0.556 V
2.5 Depletion Width across Homojunction

Depletion region is also called the transition region. The space charge is expected to diminish gradually
and not abruptly with the distance, but for ease, abrupt approximation is considered, which very closely
describes the actual situation assumed here. The electrostatic potential y (x), electric field and charge
density present inside the depletion region are related by Poissons equation as follows:
d 2y ( x )
=
dE x af =0 xn < x < •
dx 2 dx
d 2y ( x) dE( x ) qN Charge density
2 = = D = 0 < x < xn
dx dx e oe s e oe s
d 2y ( x) dE ( x) qN A
2
= = xp < x < 0
dx dx e oe s
d 2y ( x ) dE( x )
= =0 • < x < xp
dx 2 dx
dE( x ) qND
En = zdx
dx = z e oe s
dx 0 < x < xn (2.5.1)
$%
qN A
Similarly, Ep = z
e oe s
Integrating Eqn. 2.5.1 results in
dx xp < x < 0 (2.5.2)
En =
FG qN IJ x + C
D
1
He e K
o s
Applying initial condition at x = xn, E = 0,
Hence,
FG qN IJ x + C
0= D
n 1
He e K o s
or, C = G
1
F qN IJ x D
n
He e K o s
Now, E =Gn
F qN IJ x FG qN IJ x = FG qN IJ ( x - x )
D D
n
D
n (2.5.3)
He e K He e K He e K
o s o s o s
Similarly, integrating Eqn. 2.5.2 we get

qNA qN A FG IJ
Ep = z e oe s
dx =
e oe s
x + C2
H K
Applying initial condition at x = xp, Ep = 0, we get
FG qN IJ (- x ) + C
0= A
p 2
He e K o s
or C = G
2
F qN IJ x A
p
He e K o s
Now, E = G
p
F qN IJ x FG qN IJ x
A A
p =
FG qN IJ (x + x )
A
p (2.5.4)
He e K He e K
o s o s He e K
o s
Here, Ep, En, yn and yp are electric fields and voltages on p- and n-side of the homojunctions.
x is positive in n-region and negative in the p-region. We see from the plot of the electric field that it
changes its slope from negative to positive at x = 0 and hence, its magnitude must be maximum at x = 0
only. Thus, electric fields derived for the two regions become equal at x = 0 and are expressed as
En(max)at x = 0 =
FG qN IJ (x ) and E
D
n p(max)at x = 0 =
FG qN IJ (x )
A
p (2.5.5)
He e K
o s He e K
o s
Hence, equating these maximum fields yield

NDxn = NAxp (2.5.6)
$&
or, xn =
F N I x , and x = F N I x
A D (2.5.7)
GH N JK
D
p GH N JK p
A
n
2.5.1 Potential Barrier

The potential barrier of a p-n homojunction can be obtained by integrating the electric fields on both
sides of the homojunctions. The voltage and electric fields are related as
qN A qN A FG IJ FG x + xx IJ + C
2
z z
yp(x) = Edx =
e oe s
( x + x p )dx =
e oe s H KH 2 K p 3 (2.5.8)
Applying initial condition at x = xp, yp(x) = yp
2
Ê qN ˆ Ê x p ˆ
Now, yp = Á A ˜ Á - x2p ˜ + C3
Ë eoe s ¯ Ë 2 ¯
or,
FG qN IJ F x I
C3 = yp + A
2
p
H e e K GH 2 JK
o s
Now
F qN IJ FG x + xx IJ + y + FG qN IJ F x I
y (x) = G A
2
A
2
p
(2.5.9)
p
He e K H 2 K
o s H e e K GH 2 JK
p p
o s
or,
F qN IJ F x + xx + x I + y
y (x) = G A
2 2
p
x <x<0 (2.5.10)
p
H e e K GH 2
o s 2 JK
p p p
qN D
Similarly, z
yn(x) = Edx = z e oe s
( x - xn )dx xn < x < 0 (2.5.11)
or, yn(x) =
FG qN IJ FG x - x xIJ + C
D
2
n 4
He e K H 2 K
o s
At, x = xn, yn(x) = yn
Ê qN ˆ Ê x2 ˆ
yn = Á D ˜ Á n - xn2 ˜ + C4
Ë eo e s ¯ Ë 2 ¯
or,
FG qN IJ FG x IJ
C4 = yn D
2
n
He e K H 2 K o s
Now,
F qN IJ FG x - x xIJ + y FG qN IJ FG x IJ
y (x) = G
n
D
2
n n
D
2
n
He e K H 2 K
o s He e K H 2 K o s
$'
or, yn(x) =
FG qN IJ FG x - x x + x IJ + y
D
2
n
2
n
n 0 < x < xn (2.5.12)
He e K H 2
o s 2K
The maximum value of voltages in both sides can be obtained by differentiating and equating it to
zero, i.e.
dy n ( x )
=
qND FG
(x xn) = 0
IJ
dx e oe s H K
Hence, yn(x) is maximum at x = xn that can be obtained by putting this value in Eqn. 2.5.12 that results
in
yn(x = xn)max =
FG qN IJ FG x - x
D
2
n 2
n +
xn2 IJ + y n = yn (2.5.13)
He e K H 2
o s 2 K
Similarly, yp(max) can be obtained by differentiating Eqn. 2.5.10 and equating it to zero, i.e.
dy p ( x )
=
FG qN IJ (x + x ) = 0
A
p
dx He e K
o s
or, x = xp
Hence, yp(x = xp)max =

FG qN IJ F x - x
A
2
p 2 x 2p I +y =y (2.5.14)
H e e K GH 2
o s
p +
2 JK p p
From Eqn. 2.5.10 the potential difference between xp and 0 is

qN A x 2p
yp(o) = yp + and
2e oe s
qN A x 2p qN A x 2p qN A x 2p
yp (xp) = + + yp = yp
2e oe s e oe s 2e oe s
qN A x 2p qN A x 2p
Hence, yp (xp) yp(o) = yp yp = (2.5.15)
2e oe s 2e oe s
Similarly potential difference between xn and 0 is obtained as
FG qN IJ FG x IJ
yn(o) = yn D
2
n
He e K H 2 K o s
and
F qN IJ FG x - x + x IJ + y = y
y (x ) = G
n n
D
2
n 2
n
2
n
n n
He e K H 2 o s 2K
Now, y (x ) y (o) = y y + G
n n n
F qN IJ FG x IJ = FG qN IJ FG x IJ
n n
D
2
n D
2
n
(2.5.16)
He e K H 2 K He e K H 2 K o s o s
%
Hence, potential barrier present across the homojunction is

yD = yn (xn) yn(o) {yp (xp) yp(o)}
=
FG qN IJ FG x IJ + FG qN IJ F x I = q
D
2
n A
2
p
( N D xn2 + N A x2p ) (2.5.17)
H e e K H 2 K H e e K GH 2 JK 2 e e
o s o s o s
We know that xnND = xpNA, and |xp| + |xn| = Wo (2.5.18)
Wo = xn + xp = xn +
FG N IJ x
D
n = xn
FG N + N IJ
A D
HN K A H N K A
Hence,
FG N IJ W , and
xn = A
o
HN +N K D A
x =G
F N IJ FG N IJ W = FG N IJ W
p
D A
o
D
o (2.5.19)
HN KHN +N K HN +N KA D A D A
Ê q ˆÊ N2 ˆ
Hence, built in voltage = yD = Á ˜ Á N D xn2 + N A D2 x2n ˜
Ë 2 e¯ Ë NA ¯
Ê q ˆÊ N2 ˆ Ê q ˆ Ê N ˆ Ê q ˆ Ê N + ND ˆ 2
= Á ˜ Á N D xn2 + D xn2 ˜ = Á ˜ N D Á 1 + D ˜ xn2 = Á ˜ N D Á A xn
Ë 2 e ¯Ë NA ¯ Ë 2 e ¯ Ë NA ¯ 2
Ë ¯e Ë N A ˜¯
2
or,
Ê q ˆ
yD = Á
Ê N + ND ˆ
ND Á A
NA FG IJ Ê q ˆ
Wo2 = Á
Ê N AND ˆ 2
Ë 2 e ˜¯ ˜ N H K Ë 2 e ˜¯ ÁË N + N ˜¯ Wo
Ë N A ¯ D + NA A D
Ê N A + ND ˆ Ê 2eˆ
or, Depletion width = Wo = ÁË N N ˜¯ y D ÁË q ˜¯ (2.5.20)
A D
FG N
xn = A IJ Ê N N ˆ y Ê 2 e ˆ =
A + D
D
NA Ê 2 ey D ˆ
HN +N D A K ÁË N N ˜¯ ÁË q ˜¯ (N
A D
Á q ˜¯
A + ND ) ND Ë
x =G
F N IJ W = FG N IJ ( N N )y D A + D Ê 2eˆ ND Ê 2 e o e sy D ˆ
ÁË q ˜¯ =
D
p
K HN +N K N N ( N A + N D ) N A ÁË ˜¯
o D
HN +N D A D A A D q
In the case when a forward bias voltage V is applied externally, the electrostatic potential barrier
becomes (yD V) and hence, depletion width xp, xn, and Wo become
1/ 2
xn =
FG N A IJ W = ÔÌÏ 2 e e (y o s D - V ) Ê ND ˆ Ê 1 ˆ Ô¸
(2.5.21)
HN +N o
K ÓÔ q ÁË N ˜¯ ÁË N + N ˜¯ ˝
D A A D A Ô ˛
1/ 2
xp =G
F N D IJ W = ÔÌÏ 2 e e (y o s D -V ) Ê NA ˆ Ê 1 ˆ Ô¸
HN +N o
K ÔÓ q ÁË N ˜¯ ÁË N + N ˜¯ ˝
D A D D A Ô ˛
%
1/ 2
ÏÔÊ 2 e e ˆ Ê N + N A ˆ ¸Ô
Wo = ÌÁ o s ˜ (y D - V ) Á D ˝ (2.5.22)
ÔÓË q ¯ Ë N D N A ˜¯ ˛Ô
The band diagram plots of unbiased, forward biased, and reverse biased p-n homojunctions are
shown in Figs. 2.162.18.
Examples
1. If the dielectric constant of Ge is es = 16, ND = NA = 1021/m3, eo = 8.854 ¥ 1012 F/m,
jD = 0.184 V, then obtain the depletion width.
Solution
1/ 2
ÏÔ 2 e e Ê N + N A ˆ ¸Ô
Wo = Ì o s (y D - V ) Á D ˝ = 0.808 ¥ 106 m = 0.808 micron
ÓÔ q Ë N D N A ˜¯ Ô˛
Figure 2.16 Unbiased p-n homojunction band diagram
Figure 2.17 Forward biased p-n homojunction band diagram
Figure 2.18 Reverse biased p-n homojunction band diagram

%
2. If an n-type Si bar has a donor density of 1022 atoms/m3 and an electron-hole density (ni)
1016/m3 at room temperature. Justify that the holes in the bar of Si are much less than the
electrons in it.
Solution
ni = 1016/m3, ND = 1022/m3, nn ¥ pn = ND ¥ pn = ni2
ni2 1032
Hence, pn = = 22 = 1010/m3
ND 10
ND 10 22
The ratio of electrons to holes = 10 = 1012/m3
pn 10
Thus, for every hole there are 1012 electrons present in the n-type Si bar. Hence, electrons are
majority while holes are minority charge carriers.
2.6 Depletion/Transition Layer Capacitance Across Homojunction

The depletion layer capacitance CT per unit area of the homojunction is written as the ratio of the change
in the charge per unit area to the change in the barrier potential.
dQ
Thus, CT = (2.6.1)
dy D
The charge on each side of the homojunction interface is
1/ 2
Ï ND N A ¸
Qp = qNA (xp)A = A Ì2 qe o e sy D ˝ and (2.6.2)
Ó ND + N A ˛
1/ 2
Ï ND N A ¸
Qn = qND (xn)A = A Ì2 qe oe sy D ˝ (2.6.3)
Ó ND + N A ˛
In Eqns 2.6.2 and 2.6.3, Q is equal in magnitude but opposite in sign. Hence |Q| under forward biased
condition is
1/ 2
ÏÔ Ê ND N A ˆ ¸Ô
|Q| = A Ì2 qe oe s Á ˜ (y D - V ) ˝ (2.6.4)
ÓÔ Ë ND + N A ¯ Ô˛
1/ 2
dQ A ÔÏÊ 2 qe o e s ˆ Ê N D N A ˆ Ô¸
Hence, CT = = ÌÁ ˝ (2.6.5)
d (y D - V ) 2 ÔÓË y D - V ˜¯ ÁË N D + N A ˜¯ Ô˛
The range of the value of transition capacitance CT is from 10 to 100 pF. It is called voltage variable
capacitance, as it is proportional to (yD V)1/2. There are several important applications of variable
capacitance including the case of the tuned circuits. The p-n homojunction device that makes the use of
voltage variable properties of C is called varactor.
%!
For an n +p homojunction, ND > NA and hence, Wo = xp, i.e. almost whole depletion region shifts into
the p-type material. Under such circumstances
1/ 2
Ê Aˆ Ï 2 qe o e s N A ¸
CT = Á ˜ Ì ˝ (2.6.6)
Ë 2¯ Ó yD -V ˛
The value of CT depends on the applied voltage, dielectric constant, area and the doping levels. The
depletion barrier potential is increased to the voltage yD + V with the application of the external reverse
bias V. Hence, the homojunction capacitance Cj under reverse bias condition is expressed as
CT2 =
A2 R|S
qe oe s FG
ND NA IJ U|V (2.6.7)
T| H
2 (y D + V ) N D + N A K W|
1 2 A-2 ( N D + N A )
or, = (V + y D ) (2.6.8)
CT2 q ( N D ¥ N A )e o e s
The CT2 in a homogeneously doped crystal is a linear function of the externally applied voltage. The
extrapolation of the line of CT2 to the zero value gives the value of the depletion voltage yD. The plot of
1/ CT2 versus V (external reverse bias) is shown in Fig. 2.19.
Figure 2.19 Homojunction capacitance versus reverse bias
2.6.1 Diffusion Capacitance

The diffusion of minority carriers with distance from the homojunction point in a forward biased p-n
homojunction assuming NA >> ND , (x = 0) is shown in Fig. 2.20.
Figure 2.20 Diffusion of minority carriers

%"
Most of the diffusing charges are due to diffusion of the holes on n-side as concentration of holes is
much more than the concentration of electrons on p-side.
The diffused charges stored in thickness of Dx at a distance x from the homojunction point is given
as
dQ = A(dx)qpn (0)e x/Lp = Aqpn (0)e x/Lp dx
= A(dx)qpn(x) = A(dx)qpn(0)ex/Lp = Aqpn(0)e x/Lp dx
•
= Aqpn(0) e z
o
- x / Lp
dx = Aqpn(0)(Lp) exp
- x / Lp •
0
= Aqpn(0)L p (2.6.9)
This can be expressed in terms of the forward current I as

dp d -x / Lp qAD p pn (0) - x / L p
I = Ip = qADp = qADp pn (0)e = e
dx dx Lp
qADp pn( o) L p Dp Dp Q
= = qApn (0) L p = Q= (2.6.10)
Lp Lp L2p Dpt p tp
dQ d ( It p ) dI F I
Diffusion capacitance = CD = = = tp (2.6.11)
dV dV dV H K
dI I
=
dV hVT
t pI
Hence, CD = (2.6.12)
hVT
The range of diffusion capacitance is 0.1 mF to 1 mF. Thus, diffusion capacitance is many times
higher than the transition capacitance.
2.7 Continuity Equation

We know that total current contributed by any type of carrier is influenced by two factors: Drift and
Diffusion. The movement of charge carriers per unit time (time dependent) contributes the drift current
and diffusion current is contributed due to concentration gradient existing between two regions (space
dependent). Hence, for analysis of diode and transistor characteristics, we are required to determine the
concentration of carriers both w.r.t. time and space. This is done by solving a partial differential equation
called the continuity equation. Formation of the continuity equation is described as in Fig. 2.21.
Figure 2.22 shows several components of hole and electron concentrations under forward biased
condition. The hole and electron concentrations, both, decrease exponentially and settle down to the
thermal equilibrium pno and npo.
%#
Figure 2.21 Continuity Equation
The hole concentration in n-type = pn(x) = pno + pn¢ (o)ex/Lp (2.7.1)

The excess hole concentration in n-type at x = xn = pn¢ (o) = pn(xn)pno (2.7.2)
x/L n
Similarly, electron concentration in p-type = np(x) = npo + np¢ e (2.7.3)
The excess electron concentration in p-type at x = xp = n ¢p = np(xp) npo (2.7.4)
Let us consider for simplicity that the flow of carriers is only one-dimensional, i.e. in x-direction only
in the n-type semiconductor bar. The variation of concentration in y- and z-direction are assumed to be
zero.
Figure 2.22 Minority carrier’s variations
Let the hole current Ip enter the thin specimen slice dx at a distance x of the semiconductor shown in
Fig. 2.21 and Ip + dIp leaves the specimen. There are three factors that contribute to the change in the
concentration of holes p. They are
1. Due to additional current generated (dIp), dIp coulombs are taken away per second,
dI p Charge taken away dI p

i.e. (per unit volume) = = (2.7.5)
dt Unit charge ¥ Volume q ¥ ( A ¥ dx)
%$
dI p / A dJ p
= = (2.7.6)
q ¥ (dx) q(dx )
d
dJ p F dp d2 p
I
Now, qpm p E - qDp
= = qDp 2 (2.7.7)
dx dx H dx dxK
2. Thermal agitation generates holes at a rate g holes/second. The value of g can be estimated from
the thermal equilibrium condition where generation = recombination and concentration stabilizes
to po. If the lifetime of the hole is tp, then po holes will vanish in tp seconds, i.e. the rate of
po p
recombination is . Thus, in steady state g = o .
tp tp
p
3. If the concentration is p, then the recombination rate is per seconds. Combining these three
tp
conditions yields,
dp d2 p p p p - po d2 p
= Dp 2 + o = + Dp 2 (2.7.8)
dt dx tp tp tp dx
Since, we are considering holes in n-type material, we change po to pno and p to pn in Eqn. 2.7.8,
then
dpn p - pno d2 p
= n + Dp 2n (2.7.9)
dt tp dx
This is called the continuity equation. Its solution is in two interdependent variables and hence,
complicated. Fortunately, it is not required in most of the situations. We take up the two
conditions separately.
Case I: Variation with time only

Let us consider a situation when an n-type wafer of silicon bar is illuminated by light as in Fig. 2.23. The
light is switched off at t = 0. The hole concentration will return to equilibrium value pno. After substituting
dpn
= 0 in continuity Eqn. 2.7.9, it reduces to
dx
dpn p - pno
= n (2.7.10)
dt tp
dpn dp¢ p¢
Let pn pno = p¢, then = = (2.7.11)
dt dt tp
or,
F D + 1 I p¢ = 0,
GH t JK p
%%
Hence, p¢ = C1ex/tp (2.7.12)
Figure 2.23 Carrier variation w.r.t. time
Initial condition : t = 0, p¢ = p¢no pno = C1

Hence, p¢ = (p¢np pno)et/tp (2.7.13)
At t = tp, the excess minority carriers reduces to (1/e) times its original value.
Case II: Variation with Distance

Let us consider a long n-type silicon bar with light falling on its left end. We will consider steady state
dp
distribution of holes along the bar. Since, it is in the steady state, n = 0, hence continuity Eqn. 2.7.9
dt
reduces to
pn - pno d2 p
0= + Dp 2n (2.7.14)
tp dx
d 2 pn pn - pno
or Dp 2 =
dx tp
2
d pn pn - pno p -p
or 2 = = n 2 no (2.7.15)
dx t p Dp Lp
Let pn¢ = pn pno (2.7.16)
dpn¢ dp
or = n (2.7.17)
dx dx
d 2 pn¢ p¢
= 2n
dx 2 Lp
or,
FD
2 1 I pn¢ = 0 (2.7.18)
GH - JK
L2p
%&
x / Lp - x / Lp
Hence, pn¢ = Ae + Be (2.7.19)
At, x = •, pn¢ = pno
pno = Ae• + Be• (2.7.20)
Equation 2.7.20 can be satisfied only when A = 0, Hence, Eqn. 2.7.19 reduces to
- x / Lp
pn¢ = Be (2.7.21)
At x = xn, pn¢ = pn¢ ( o)
- xn / L p
Therefore, Eqn. 2.7.21 becomes pn¢ (o) = Be
xn / L p
Thus, B = pn¢ ( o) e
( x x )/ L
and pn¢ = pn¢ ( o) e n p
(2.7.22)
Similarly, for electrons the continuity equation w.r.t. distance is expressed as
d 2 np n p - n po n p - n po
2 = = (2.7.23)
dx t n Dn L2n
np npo = n¢p
The solution of Eqn. 2.7.23 is
( x + x p )/ Ln
np¢= n ¢p (o) e (2.7.24)
where, np and pn are functions of distance and hence, can be represented as np(x) and pn(x). The tn and
tp are the lifetimes of electron and hole diffusing in the p- and n-type regions and npo and pno are
equilibrium concentrations of the minority carriers in the p- and n-regions.
The diffusion current due to concentration gradient of holes pn¢ = Ipn(x)
dp dp¢ d
= AqDp = AqDp n = AqDp ( pn¢ )
dx dx dx
( x xn )/ L p AqDp ( x xn )/ L p
= pn¢ ( o) e = pn¢ ( o) e (2.7.25)
Lp
Similarly, diffusion current due to concentration gradient of electrons = Inp(x)
d ( - n) dn¢p d R| x + xp
Ln
U|
= AqDn = AqDn = AqDn n ¢p = n¢p ( o) exp S| V|
dx dx dx
T W
AqDn ( x + x )/ L
n¢p (o) e p n
= (2.7.26)
Ln
Thus, electron current due to diffusion of electrons in p-type material from Eqn. 2.7.26 at x = xp is
= Inp(xp)
%'
AqDn ( x + x )/ L AqDn
= n p¢ (o) e p p n = n¢p ( - x p ) (2.7.27)
Ln Ln
AqDn AqDn
Inp (xp) = n¢p ( - x p ) = {n p (- x p ) - n po} (2.7.28)
Ln Ln
Similarly, hole current due to diffusion of holes in p-type material at x = xn from Eqn. 2.7.25 is
AqDp - ( x n - xn )/ L p AqDp
Ipn(xn) = pn¢ ( o)e pn¢ ( xn ) (2.7.29)
Lp Lp
AqDp AqDp
Ipn(xn) = pn¢ ( xn ) = {pn ( xn ) - pno} (2.7.30)
Lp Lp
We know that under effective forward bias voltage V (= V VD), the hole concentration in n-type and
p-type respectively are expressed as
V / VT
pn(xn) = pno exp (2.7.31)
V / VT
np(xp) = npo exp (2.7.32)
Substituting Eqn. 2.7.31 in Eqn. 2.7.30 results in
V
Ipn
F AqD I{p ( x ) - p } = F AqD I{p
(x ) = G
p p VT
exp - pno}
n
H L JK p
n GH L JK
n no
p
no
V
F AqD I p (exp - 1)
=G
p VT
(2.7.33)
H L JK p
no
Similarly, substituting Eqn. 2.7.32 in Eqn. 2.7.28 results in

V
Inp p
F AqD IJ{n (- x ) - n } = FG AqD IJ{n
(x ) = G n
p p po
n
po
VT
exp - n po}
H L K n H L K n
=G
F AqD IJ n (exp - 1)
n
po
VT
(2.7.34)
H L K n
Total current crossing the homojunction due to diffusion of both holes and electrons is Inp (xp) +
Ipn(xn) that is equal to the sum of Eqns. 2.7.33 and 2.7.34 i.e.
V V
F AqD I p p VT F AqD IJ n n VT
I=G no (exp - 1) + G po (exp - 1)
H L JK p H L K n
&
V
FD
= Aq G
p D I
pno + n n po (exp VT - 1) (2.7.35)
HL p Ln JK
Hence, the total current density crossing the homojunction J = Jp(+xn) + Jn (xp)
V
FD
J = AqG
p D I
pno + n n po (exp VT - 1) = Jo (exp KT -1)
qV
(2.7.36)
HL p Ln JK
This is the expression of current density of a p-n homojunction diode in which the first bracket
contains the constants = Jo
where, Jo = reverse saturation current density.
In the case of a practical p-n homojunction, pn > np. If the external applied voltage is reverse bias and
less than 0.026V, then for example, even if V = 1V, then
qV 1
- -
exp KT = exp 0.026 = e -38. 46 @ 0 and
Hence, Eqn. 2.9.36 reduces to
F qD n
n po qDp pno I
Jo = GH L n
+
Lp JK (1) (2.7.37)
2.8 Graded Homojunction

We know that practical p-n homojunction made by diffusion are seldom abrupt in nature because of the
profile of the diffusing species. Hence, a graded region is practically created on both sides of the
metallurgical homojunction. This difficulty could be overcome by ion-implantation using greater control
of the implant profile and hence, nearly abrupt behaviour can be achieved. The epitaxial techniques such
as molecular beam epitaxy allow us to realize ideal diodes. However, we must know the important
parameters for graded homojunction. Here we assume that the net doping on both sides including the
ionized charge in the depletion region of the metallurgical homojunction vary linearly. The electrostatic
field, potential barrier, and charge distribution of graded homojunction depletion width W are shown in
Fig. 2.24.
Poissons equation for graded homojunction is written as
d 2y dE r q q W W
= = = ( p - n + ax ) @ ax £x£ (2.8.1)
dx 2 dx e oe s e oe s e oe s 2 2
where, a Æ impurity gradient in cm4
Integrating Eqn. 2.8.1 yields field as
dE q qa x 2 W
z dx
dx = E = z e oe s
axdx =
e oe s 2
+ C1 , Initial condition E = 0 at x =
2
&
qa (W / 2)2
Hence, C1 =
e oe s 2
dy qa (W / 2)2 - x 2
Now, E= = (2.8.2)
dx e oe s 2
Figure 2.24 Graded homojunction
The maximum of the electrostatic field is developed at the point where the field changes from positive
to negative or vice versa. In this the field changes from positive to negative at x = 0.
dy qa (W / 2)2 qaW 2
Hence, |Emax| = - x =0
=- =
dx e oe s 2 8e oe s
dy qa (W / 2)2 - x 2 qa RS x3 UV
or, z dx
dx = y = z e oe s 2
dx + C2 =
2e oe s
(W / 2 ) 2 x -
T 3
+ C2
W
W
Initial condition y = 0 at x =
2
qa (-W / 2)3
Now, y=0= {(W / 2) 2 ( -W / 2) - } + C2
2e s e o 3
&
3
qa ÔÏ W W 3 Ô¸ qaW 3 -2
RS UV
= Ì- + ˝ + C2 = + C2
2 e s eo ÔÓ 8 24 ˛Ô T W
2e oe s 24
qaW 3
Hence, C2 =
24e oe s
qaÏÔ 2 x3 ¸Ô qaW 3 qa ÏÔW 2 x3 ¸Ô qaW 3
or, y = Ì (W /2) x - ˝ + = Ì x - ˝+
2 eo e s
ÓÔ 3 Ô˛ 24 e o e s 8 e o e s ÓÔ 4 3 ˛Ô 24 e o e s
W qa ÔÏW 3 W 3 Ô¸ qaW 3 qaW 3
Hence, y at x = is the potential barrier = Ì - ˝+ = (2.8.3)
2 2 e o e s ÔÓ 8 24 ˛Ô 24 e o e s 12 e o e s
1/ 3
Ê 12 e o e sy ˆ
Now, W= Á (2.8.4)
Ë qa ˜¯
W W
The value of impurity concentration at the edges of the depletion region - and are equal to
2 2
W
a . The built in potential in the graded homojunction can be approximated as
2
2
KT (aW / 2)( aW / 2) KT Ê aW ˆ
y = ln = ln Á (2.8.5)
q 2
ni q Ë 2ni ˜¯
1/ 3
dQ e e es e o Ê qae s2 e o2 ˆ
The depletion capacitance CT = = s o = = Á ˜ F/m (2.8.6)
dt W Ê 12 e s e oy ˆ
1/ 3
Ë 12y ¯
ÁË qa ˜¯
1/ 3
Ê qae s2e o2 ˆ
Under application of external voltage, CT = Á ˜ F/m (2.8.7)
Ë 12(y ± V ) ¯
Here, + stands for reverse bias and stands for forward bias.
2.9 Types of Diodes

It has been observed that by adjusting the doping levels and gradients as well as the geometry of a
semiconductor crystal, we can modify the behavior of the device. We now list a wide range of diodes
whose properties have been deliberately controlled to produce specific capabilities.
Each of these specialized diodes has its own schematic symbol. The symbols are all specific so that
the nature and function of the device becomes clear by schematic diagram. Also the diodes are named
as per their uses. A few of important types of diodes are Signal Diode, Power Diode, Varactor Diode,
Schottky Diode, Zener Diode, Back Diode, LED, Photo diode, Tunnel Diode.
2.9.1 Signal Diodes
The manufacturers list signal diodes in their data books as the general-purpose diodes. This diode does
not handle either large current or large voltage. The main requirement of these diodes is low forward to
reverse resistance. It can be used as rectifier in power supplies; demodulator in amplitude modulated
&!
RF carrier in radio receiver, electronic switch in logic circuits, etc. The peak inverse voltage (PIV) of
most of the diodes is in the range of 20 V to 300 V. The maximum forward current is in the range of
20 mA to 300 mA. The homojunction capacitance of these diodes is very low. The OA75, OA79 are
examples of signal diodes.
2.9.2 Power Diodes

Generally power diodes are used to convert ac to dc in case of power supplies. Its PIV ranges between
5 V to 1200 V. The maximum current may be as high as 30 A to 40 A or even more. Development in the
semiconductor technology is so fast that the production of very high power ratings of diodes is announced
every year. Power diodes are silicon diodes only. The forward resistance of power diodes must be as
small as possible. This takes care of the voltage drop across the diode when large current should flow
through it. At the same time, reverse bias resistance of the diode must be as high as possible. Almost no
current should flow through the diode when reverse biased.
2.9.3 Varactor Diode
The depletion region (an insulator) across a p-n junction exists that is of the order of 5 ¥ 103 m. An
insulator (dielectric) that separates the 2-conducting plates of p and n materials result into formation of
a capacitor. This is an important characteristic of any p-n junction that provides an inherent capacitance.
When the junction is reverse biased, increasing the applied voltage will cause the depletion region to
widen, thus increasing the effective distance between the 2-plates of the capacitor and decreasing the
effective capacitance. Thus a voltage variable capacitor (VVC), varicaps or voltacaps is available across
the p-n junction. Altering the reverse bias applied across the diode that varies its junction capacitance
can vary the resonant frequency, if a diode is used in the resonant circuit. No moving part is required in
changing the resonant frequency. The symbol of Varactor diode is shown in Fig. 2.25.
This way adjusting the doping gradient and junction width, we can control the capacitance range and
the way capacitance changes with applied reverse voltage. A four-to-one capacitance range is no problem;
a typical varactor diode (sometimes called a varactor diode) might vary from 60pF at zero bias down to
15 pF at 20 V. Very careful manufacturing can get a capacitance range of up to ten-to-one, although this
seems at present to be a practical limit. Varactor diodes are used in electronic tuning systems, to
eliminate the use and need of moving parts.
Figure 2.25 Varactor diode characteristics

The advantages of mechanically tuned VVC over the other types of variable capacitors are:
∑ Small in size, ∑ Rugged, ∑ Reliable,
∑ Have no moving part, ∑ Operate over wide frequency range,
∑ Have fast response, ∑ Permits remote tuning, and,
∑ Tuned electrically rather than mechanically.
&"
The transition capacitance across the junction of the p-n diode is expressed as
eA 2 eV j 2 e (y o + VR )
CT = , Vj = yo VR, and W2 = = (2.9.1)
W qN D qN D
eA eA(qND )1/ 2 K
Thus, CT = = 1/ 2 = (2.9.2)
W {2e (y o + VR )} (y o + VR )1/ 2
where, K = constant and function of junction area, dielectric constant, permitivity of free space, doping
level in the active region and charge of an electron.
VR = externally applied reverse bias voltage
yo = junction barrier potential
It is designed in the popular plastic package for high volume requirements of FM radio or TV tuning
and AFC, general frequency control and tuning applications.
2.9.4 Schottky Diode

When we get into high-speed applications for electronic circuits, one of the problems exhibited by
semiconductor devices is a phenomenon called charge storage. This term refers to the fact that both
free electrons and holes tend to accumulate inside a semiconductor crystal while it is conducting, and
must be removed before the semiconductor device will turn off. This is not a major problem with free
electrons, as they have high mobility and will rapidly leave the semiconductor device. However, holes
have another story. Electrons jumping from bond to bond must fill them more gradually. Thus, it takes
time for a semiconductor device to completely stop conducting. This problem is even worse for a
transistor in saturation, since then by definition the base region has an excess of minority carriers,
which tend to promote conduction even when the external drive is removed.
The solution is to design a semiconductor diode with no p-type semiconductor region, and therefore
no holes as current carriers. Such a diode, known as a Schottky Barrier Diode, places a rectifying metal
contact on one side on an n-type semiconductor block. For example, an aluminium contact will act as
the p-type connection, without requiring a significant p-type semiconductor region. Figure 2.26 shows
the symbol, construction, and V-I characteristics of the Schottky diode.
Since minority carriers must be removed from the junction for a p-n junction diode, to be OFF, there
is always a delay due to the minority carriers lifetime when a p-n junction diode is OFF. Having no
minority carriers to be cleared from the junction, Schottky diode can be turned OFF considerably faster
than its p-n junction counterpart. Since, the voltage across a forward biased Schottky diode is only
about one half that of the silicon p-n junction diodes, the Schottky diode is a better approximation to the
ideal diode. Schottky diodes are called hot carrier diodes also. Forward bias increases energy of the
electrons on n-side to a higher level than that of the electrons on the metal side of the junction. For this
increase in energy on n-side of electrons, it is called hot carrier.
This diode construction has two advantages in certain types of circuits. First, they can operate at
very high frequencies, because they can turn off as fast as they can turn on. Second, they have a very
low forward voltage drop. This is used to advantage in a number of ways, including as an addition to
TTL ICs. When a Schottky diode is placed across the collector-base junction of a transistor as shown
to the right, it prevents the transistor from becoming saturated, by bypassing the excess base current
around the transistor. Therefore, the transistor can turn off faster, thus increasing the switching speed
of the IC. The full power versions of these TTL ICs are the 74S00 series, and have switching speeds
&#
Figure 2.26 Schottky Diode Symbol, Equivalent Circuit, layout, and V–I characteristic
similar to ECL, and similar power requirements. The low power versions, the 74LS00 series, have
switching times comparable to standard TTL, but with a much lower power requirement.
It has few special properties such as the high speed and low voltage drop across it. The small voltage
drop across it is used to advantage in certain digital logic families. It is used in high frequency mixers,
rectifiers, modulators, detectors, waveform generators, and in fast pulse processing circuits. It has
almost zero minority carrier storage time. Its physical recovery time is 0.15 ms. The symbolic
representation and the approximate equivalent circuit of Schottky diode are shown in Fig. 2.26. Also the
V-I characteristics of a p-n junction and Schottky diodes are shown in this figure.
The electrons from n-type semiconductor rush towards the junction with high KE and move into the
metal. Since, these electrons have high KE than the electrons of the metal, it is called hot carrier and the
diode is called hot carrier diode. As the threshold voltage is much less as compared to a junction diode,
even less forward bias results into a large current flow.
2.9.5 PIN Diode

The p-i-n diode does not actually have a junction at all. Rather, the middle part of the silicon crystal is
left undoped. Hence the name for this device: p-intrinsic-n, or p-i-n. Because his device has an intrinsic
middle section, it has a wide forbidden zone when unbiased. However, when a forward bias is applied,
current carriers from the p- and n-type ends become available and conduct current even through the
intrinsic center region. The end regions are heavily doped to provde more current carriers.
The p-i-n diode is highly useful as a switch for very high frequencies. They are commonly used as
microwave switches and limiters.
The end contacts in PIN diode are separated by region of relatively high resistivity. So PIN diode
consists of adding a layer of intrinsic silicon between the heavily doped p- and n-type silicon materials
shown in Fig. 2.27.
They are able to withstand a large back bias as it
contains an intrinsic layer. For this reason they are
useful as power rectifiers at low frequencies but at Figure 2.27 p-i-n Diode Constructions
sufficiently high frequencies it ceases to rectify. Its impedance becomes substantial due to that of the i
region. This is high in absence of forward bias or with p-n junction reversed biased, but will become
low when forward bias is applied to flood the i region with the injected carriers.
It is used as a voltage controlled attenuator, power limiter, phaseshifter, square wave modulator, etc.
&$
2.9.6 Zener Diodes

When the reverse voltage applied to a diode exceeds the capability of the diode to withstand it, one of
two things will happen, yielding essentially the same result in either case. If the junction is wide, a
process called avalanche breakdown occurs, whereby the current through the diode increases as much
as the external circuit will permit. A narrow junction will experience Zener breakdown, which is a
different mechanism but has the same effect.
The useful feature here is that the voltage across the diode remains nearly constant even with large
changes in current through the diode. In addition, manufacturing techniques allow diodes to be accurately
manufactured with breakdown voltages ranging from a few volts up to several hundred volts. Such
diodes find wide use in electronic circuits as voltage regulators.
The Zener diodes are very popular among diode family. The most important use of Zener diode is in
the regulated power supply circuits as the voltage reference element, surge protection, arc suppression,
and other consumer product applications. The Zener diodes are also called breakdown diodes. It is a
class of specially doped p-n homojunction diodes to produce controlled breakdown characteristics
without damage. The typical breakdown voltage of the Zener diode falls in the range 2.4 V to 200 V with
an accuracy of 5% to 20%.
The breakdown mechanism in Zener diodes are influenced by two phenomena:
∑ Zener effect ∑ Avalanche effect
The Zener effect goes to the credit of the inventor C.E. Zener. He discovered the theory of reverse
breakdown in the year 1934. The second effect called the avalanche effect. The real Zener effect is only
formed in diodes that breakdown below 5 V of reverse bias. In this region of voltage, the depletion
region is very thin compared to what it is at 200 V. As a result, the minority carriers do not have enough
distance in which it can gain sufficient K.E. to cause effective collisions to knock out the covalent
electrons. Hence, avalanche effect is not possible in voltage region below 5 V. However, a very high
electric field of the order of 106 V/m exists across the homojunction due to extremely narrow depletion
width 150 Å to 200 Å (1 Å = 1010 m). This field provides high electrical force that tears off the covalent
electrons directly rather than by collision. This is Zener effect. For more than 5 V, the breakdown is
predominantly due to avalanche multiplication. The diodes breaking down above 5 V should be properly
called avalanche or breakdown diodes. However, the word Zener has been used for all diodes having
sharp breakdown characteristics. The avalanche effect is due to the cumulative action. The externally
applied voltage accelerates the minority charge carriers in the depletion region. The minority carriers
attain large K.E. to ionize the atoms by collision, which in turn produce electron-hole pairs. These pairs
are then accelerated to produce more ionization, producing more electron-hole pairs and hence, more
current. The increase in current tends to occur suddenly at a particular voltage 5 V. The 5 V avalanche
diodes have approximately zero temperature coefficients, which becomes positive for higher voltage
devices.
The knee is sharper for an avalanche diode than that of Zener diode. The Zener diodes are used as
voltage reference in precision equipments, simple voltage regulators, etc. They are also used in clamping,
clipping, dc coupling, surge protection, etc.
2.9.6.1 Mechanism of Zener Breakdown
When a homojunction is formed with heavily (more than 1026 atoms /m3) doped n- and p-type
semiconductors, it results in a greatly reduced depletion width of the order of 100 Å. This depletion
&%
1
width is th of a typical semiconductor diode. Hence, electric field in the depletion width reaches a
100
value higher than 1 V/100 nm = 107 V/m that is really large.
The Fermi level in a lightly doped n-type material is described as
N
EFn = ECn KT ln V (2.9.3)
NA
In an n-type material, nn = ND, hence
N
EFn = ECn KT ln C (2.9.4)
ND
N
For lightly doped semiconductor ND << NC so that ln C is a positive number.
ND
Hence, EFp = EC (some energy) (2.9.5)
The donor concentration in excess of the amount ND > 1025/m3 corresponds to a doping-level of 1
N
part in 103, resulting in ln C a negative number and hence,
ND
EFn = EC + some energy (2.9.6)
Thus, the Fermi level in a heavily doped n-type material lies in the conduction band as depicted in
Fig. 2.28.
Figure 2.28 Energy levels in heavily doped n- and p-type semiconductors

Similarly the energy levels in a lightly doped p-type material is described as
N
EFp = EVp + KT ln V (2.9.7)
NA
N
For lightly doped p-type material, NV > NA, hence ln V is a positive number resulting in the expression as
NA
EFp = EVp + some energy N (2.9.8)
FG IJ
For a heavily doped p-type semiconductor, NA > 1025/m3 and NA > NV and hence, ln V becomes
negative number leading to NA H K
EFp = EVp some energy (2.9.9)
In other words, the Fermi level in a heavily doped p-type material lies in the valence band as shown
in Fig. 2.28.
When heavily doped p-n homojunction is reverse biased, the energy bands becomes crossed at
relatively low voltage as shown in Fig. 2.29. In between Zener voltage to avalanche voltage, both
mechanisms are present. The V-I characteristics of Zener diode are shown in Fig. 2.30.
Figure 2.29 (the R.H.S) indicates that crossing of band aligns a large number of empty states in the
n-side conduction band opposite to many filled states on the p-side valence band. Since, the barrier
&&
separating the two bands is very thin, tunneling of electrons occur. Tunneling of electrons from p-side
valence band to the n-side conduction band contribute to reverse current from n to p. This effect is
known as Zener effect.
Figure 2.29 Reverse biased band structure and characteristic of Zener breakdown
The current flows from cathode to anode in normal operation of Zener diode and the cathode is
positive w.r.t. anode. So IZ and VZ have positive values as indicated in the symbolic representation of the
Zener diode.
The manufacturers define VZK, VZo, and VZ with the relation
VZ = VZo + rZ IZ (2.9.10)
where, VZo = point on the voltage axis where the slope of the curve cuts it.
Theoretically, though, slight difference occurs in between VZ and VZo, but practically VZo = VZK. The
manufacturers specify the Zener drop VZ (working voltage) at certain test current IT (called Q-point) as
Figure 2.30(a) Avalanche and Zener diodes characteristics

Back Diode
With higher doping level, the Zener effect can occur near 0 V. The forward conduction still occurs at
0.7 V but reverse bias breakdown starts approximately at 0.1 V. The V-I characteristic of the back
diode is shown in Fig. 2.30(b).
&'
Figure 2.30(b) V-I characteristic of back diode Figure 2.30(c) LED and Photo diode circuit
Light Emitting Diode (LED)

One of the questions semiconductor manufacturers asked themselves was, What happens if we increase
the doping levels in the silicon crystal? Trying this gave rise, among other things, to the tunnel diode.
Then they took the process even further, to the point where they skipped the silicon completely, and
produced what is called a III-V device, named after the fact that p-type dopants are from column III
of the Periodic Table (aluminum, gallium, indium) and n-type copants are from column V (phosphorus,
arsenic).
The resulting Gallium Arsenide (GaAs) crystal had the interesting property of radiating significant
amounts of infrared radiation from the junction. By adding Phosphorus to the equation, they shortened
the wavelength of the emitted radiation until it became visible red light. Further refinements have given
us yellow and green LEDs. More recently, blue LEDs have been produced, by putting nitrogen into the
crystal structure. This makes full-color flat-screen LED displays possible.
The mechanism of emitting light is interesting. The atomic structure of the LED is carefully designed
so that as free electrons cross the junction from the n-type side to the p-type side, the amount of energy
each electron releases as it drops into a nearby hole corresponds to the energy of a photon of some
particular color. Therefore, that photon is released as a visible photon of that color.
The term LED stands for light emitting diode. Free electrons in forward biased LED recombines with
holes. These electrons move from higher energy level to lower energy level and hence they radiate
energy in the form of light. In ordinary diodes, this energy is dissipated in the form of heat. LEDs are
available that radiates red, green, yellow, blue, orange or infrared (invisible) light. The typical voltage
drop across the LEDs falls in the range of 1.5 V to 2.5 V for currents between 10 mA to 15 mA.
However, the exact voltage drop across the LED depends upon its current, colour, tolerance, etc. A
current source drive can control the brightness of the LED. Its reverse break down voltage typically is
in the range of 3 V to 5 V and hence it is very easily destroyed in reverse bias with more voltage. The
symbolic representation of the LED is shown in Fig. 2.30(c).
Photo Diode
The light energy falling on the pn-junction dislodges valence electrons. The reverse current in a p-n
junction increases with more light striking the junction. A window is normally created to pass light through
the package to the pn-junction. The arrangement of a photo diode working is explained in Fig. 2.30(c).
'
Laser Diode
We know that free electrons falling from higher energy level to lower energy level in LED radiate light.
The free electrons fall randomly and continuously that result into light waves with phase differences
from 0° to 360°. The light waves having many phase differences are called non-coherent light and
hence an LED produces non-coherent light waves.
On the contrary, the Laser diode is a coherent light source. This means that all light waves from a
laser have the same phase. The laser diodes are also called semiconductor lasers. The laser diodes are
used in compact disk (CD) player and laser printers. The laser diodes are available in visible light of red,
green, or blue colours and invisible range (infrared). In broadband communication it is used with fiber
optic cables to increase the speed of data communication.
Tunnel Diode
As we mentioned in our discussion, the addition of either p-type or n-type impurities causes the Fermi
level in the silicon crystal to shift towards the valence band (p-type impurities) or the conduction band
(n-type impurities). The higher the doping level, the greater the shift. In the tunnel diode, the doping
levels are so high that the Fermi levels in both halves of the crystal have been pushed completely out of
the forbidden zone and into the valence and conduction bands.
As a result, at very low forward voltages, electrons do not have to gain energy to get over the Fermi
level or into the conduction band rather they can simply tunnel through the junction and appear at the
other side. Furthermore, as the forward bias increases, the applied voltage shifts the levels apart and
gradually back to the more usual diode energy pattern. Over this applied forward voltage range, diode
current actually decreases as applied voltage increases. Thus, over part of its operating range, the tunnel
diode exhibits a negative resistance effect. This makes it useful in very high frequency oscillators and
related circuitry.
We know that the breakdown with high doping level in reverse biased back diode can occur at 0V.
The symbolic representation and forward characteristic of a tunnel diode are shown in Fig. 2.30 (d).
This V-I characteristic exhibits a negative resistance region. This negative resistance is used in high
frequency circuits called oscillators. In contrast to the ac generator, the tunnel diode converts mechanical
energy to sinusoidal signal.
Figure 2.30(d) Symbol and V- I characteristic of Tunnel diode

'
2.10 Types of Homojunctions

Just pressing together a section of n-type material to a p-type material cannot produce a rectifying
homojunction. In order to produce a proper p-n homojunction, both types of semiconductors should be
a single crystal, but divided into p-type and n-type impurity regions. This can be done in various ways.
The semiconductor diodes are classified depending upon the method of constructions as:
∑ Grown homojunction ∑ Alloy homojunction ∑ Diffused homojunction ∑ Epitaxial plannar
2.10.1 Grown Homojunction

This method of homojunction fabrication was popular in the early days of semiconductor device
development. This is done by mixing p-type and n-type impurities into a single crystal during the
manufacturing process. A grown homojunction is formed by first growing a semiconductor crystal of
one type, say n-type from extremely pure (impurity less than 1 in 109) molten Ge and then changing the
impurity from n-type to p-type by adding p-type impurity by large amount. In this process a continuous
crystal is formed that is partly n-type and partly p-type. Then a thin slice containing p- and n-type
material with a p-n homojunction in between is cut. Each section is polished and etched to remove
surface impurity and then non-rectifying (ohmic) electrodes are deposited to each end of the bar.
Figure 2.31 Grown homojunction
2.10.2 Alloy/ Fused Homojunction

Another way to produce a p-n homojunction is to melt one type of impurity into a semiconductor of the
opposite type of impurity. For example, a pellet (dot) of trivalent/ acceptor impurity (indium) is put on
a thin wafer of n-type Ge inside a furnace of temperature 500°C. This temperatue is more than melting
point of indium but less than that of the Ge. Due to heating, the indium pellet dissolves within the Ge just
below it and forms a saturated solution. On cooling, the saturated solution recrystallizes with sufficient
indium content so as to change the impurity of the recrytallized region from p-type to n-type. Thus, a
p-type Ge along with the main n-type Ge wafer forms a p-n homojunction. Non-rectifying contacts are
taken out from the pellet and the wafer as indicated in Fig. 2.32. This process of manufacturing p-n
homojunction was used in 1950s to produce diodes and transistors.
'
Figure 2.32 Alloy homojunction
2.10.3 Diffused Homojunction

A thin layer of SiO2 is thermally grown over
the entire surface of a thin wafer (typical
thickness = 0.3 mm) of Si. The SiO2 is
photo-etched using a mask and p-type
impurity is diffused through the opening as
indicated in Fig. 2.33. The diffusion process
is achieved by placing the Si wafer in a
furnace at temperature of 1000°C having
high concentration of boron gas. A sharp Figure 2.33 Diffused homojunction
concentration gradient results at the surface
of the wafer and hence, boron gets diffused
into the silicon wafer. Several Si atoms at
such high temperature (1000°C) move out
of their lattice sites leaving vacancies for
impurity atoms to move in it. An aluminium
metallic contact is taken out from p-type
region. A metallic layer at the bottom of the
wafer forms the n-electrode as shown in
Fig. 2.33.
2.10.4 Epitaxial Planar

The epitaxial growth means growing of
material upon a substrate (base) material such Figure 2.34 Epitaxial planar homojunction
that the material so grown form a continuation of the base material crystal structure maintaining the
same orientation as indicated in Fig. 2.34.
In a epitaxial planar device, a very thin (single crystal) high impurity layer of Si (Ge) is grown on a
heavily doped substrate of the same material. This complete structure then forms the n-region on which
a p-region is diffused. This technique is popularly used in fabrication of IC chips.
Example
Calculate the reverse saturation current density across an abrupt Si p-n homojunction with ND = 1022
atoms/m3, NA = 1021 atoms/m3, ni = 1.5 ¥ 1016 atoms/m3, Dn = 0.0035 m2/s, Dp = 0.0012 m2/s, Lp =
0.00035m, Ln = 0.00071 m. Assume that all impurities have been ionised.
'!
Solution
nn ¥ pn = ND ¥ pn = n2i = 1.52 ¥ 1032
2.25 ¥ 1032
or, pn = = 2.25 ¥ 1010 atoms/m3
10 22
2.25 ¥ 1032
Hence, np = = 2.25 ¥ 1011 atoms/m3
10 21
Jo =
F qD n
n po qDp pno I
GH Ln
+
Lp JK
Ê 3.5 ¥ 10 -3 ¥ 2.25 ¥ 1011 1.2 ¥10 -3 ¥2.25 ¥10 10 ˆ -19
= Á
7.1 ¥ 10 -4
+
3.5 ¥10 -4 ˜ 1.6 ¥ 10
Ë ¯
= 1.6 ¥ 2.25 ¥ 108 (5 + 0.343) = 1.9234 ¥ 107 A/m2.

The typical cross sectional area of a homojunction of a discrete transistor = 106 m2 and the
reverse saturation current Io is
Io = Jo A = 1.9234 ¥ 107 A/m2 ¥ 106 = 1.9234 ¥ 1013 A.
2.11 Heterojunction
A heterojunction is formed between two semiconductors of different bandgaps having almost same
lattice constants. The usual method for forming the heterojunction is by epitaxy. Shockley in 1951 and
Kroemer in 1957 proposed this type of high efficiency junction. The heterojunctions form essential
constituents of almost all eletronic and optoelectronic devices. The formation of heterojunction in BJT
drastically improves the emitter injection efficency and hence, the current transfer ratio also increases.
A heterojunction forms two-dimensional channel of carriers at the interface with superior transport
properties that have been exploited to achieve high-performance field-effect transistors. A heterojunction
is formed by chemical bonding at the interface. In general, the lattice constants of the two semiconductors
are different. If the heterojunction is formed by epitaxy, as usual case, a misfit exists between the two
semiconductors, A and B. We are interested in a heterostructure in which the lattice constants of
semiconductors A and B are perfectly matched. The alloy AlxGa1xAs in its entire composition range 0 £
x £ 1, is almost lattice matched to GaAs. Therefore, it forms an important and useful heterostructure
system. Other method of lattice matching can be achieved by growing the appropriate semiconductor
with right composition. For example, In 0.53 Ga0.47 As P (EG = = 0.74 eV) and In0.52 Ga 0.48 As
(EG = 1.45 eV) are lattice matched with InP (EG = 1.35 eV). In an another, for x = 0, the GaAs produces
bandgap of 1.42 eV with lattice constant of 5.6533 Å. Also x = 1, the Al As produces bandgap of
2.17 eV with lattice constant of 5.6605 Å. Thus, we see that though the bandgap of ternary alloy A1xG1
xAs increase with x, the lattice constant remains essentially constant. Even for extreme cases x = 0 and
x = 1, the lattice constant mismatch is only 0.1%. Therefore, heterojunctions are very useful for opto-
electronic devices working in the range of 1.3 1.6 mm and can be formed with these semiconductors.
'"
One way of classifying heterojunctions is according to the distance during which the transition from
one material to the other is completed near the interface as
∑ abrupt
∑ graded.
In abrupt, the transition occurs within a lesser atomic distances (£1 mm), whereas in graded, it takes
place over a distance of the order of several diffusion lengths.
Another classification, often used in books, is based on conductivity present on either side of the
heterojunction, i.e.
∑ isotype
∑ anisotype.
If both type of semiconductors have similar type of conductivities (n-n or p-p), it is called isotype of
heterojunction. On the other hand, if the two types of semiconductors have dissimilar conductivities
(n-p or p-n), the junction formed between them is called anisotype heterojunction. It is customary to
denote the wider bandgap material by upper case letter and the smaller bandgap material by lower case
letter. The four types of heterojunctions are:
∑ n-n
∑ p-p
∑ p-n
∑ n-p
Each may be expected to show a different behaviour. The difference in behaviour may arise as a
result of relative magnitudes of the electron affinities of the two materials.
Kroemer suggested that anisotype heterojunction might exhibit extremely high injection efficiencies
in comparision to the isotype homojunctions. Anderson in 1960, fabricated both isotype and anisotype
heterojunctions and studied their properties. Since then, these junctions have attracted the attention of
physicists and engineers because of their interesting properties arising out of discontinuities in the
energy band at the junction.
If the band gap of the emitter shrinks by DEG due to doping, then the amount of electron density for
the same doping can be evaluated using the change in the intrinsic carrier concentration. This is expressed
as
DEG
nie(EG DEG) = nie(EG ) exp (2.11.1)
k BT
The corresponding change in the value of Peo is
DEG
Peo (EG DEG) µ ni2(EG DEG ) = Peo (EG) exp (2.11.2)
2 K BT
Also the corresponding decrease in the band gap with doping ND/cm3 is described as
1/ 2
DEG = 22.5
FN 300
D
¥ m eV
I (2.11.3)
H 10 18
T K
Equation 2.11.3 holds good reasonably up to a doping level of 1019/cm3. At higher doping levels,
bandgap shrinkage is not so large. For an example, with doping level of 1020/cm3, the bandgap shrinkage
is
'#
1/ 2 1/ 2
FN D 300 I Ê 1020 300 ˆ
DEG = 22.5 ¥ meV = 22.5 Á 18 ¥ me V = 225 meV = 0.225 eV
H 1018
T K Ë 10 300 ˜¯
But practically it was found to be 0.160 eV.
As the band gap shrinks, the current amplification factor (b) also decreases (L b >> Wbn) as
nbo DB Le DE N DE DB Le DE
b= exp G = exp G (2.11.4)
Peo DE Wb kB T N AB DEWbn k BT
nbo N
where = DE (2.11.5)
Peo N AB
Here NAB and NDE are acceptor and donor levels in the base and emitter regions respectively. This
indicates that for a fixed base doping, as the emitter doping is increased, initially the current amplification
factor increases and then amplification factor starts decreasing as the shrinkage in the bandgap starts
decreasing as heavy doping goes on increasing.
2.11.1 Abrupt Isotype Heterojunction

Before analysing a heterojunction, let us first examine some interesting features of an isotype nN
heterojunction, formed by n-type GaAs and N-type AlGaAs with a large bandgap. Figure 2.35 shows
the band diagrams of two isolated pieces of semiconductors, assumed to have different bandgaps (EGn
and EGN), different Fermi engergies EFN1 and EFN2,different work functions fN1 and fN2, and different
electron affinities cn1 and cN2. The work function is defined as the energy required to remove an
electron from Fermi level EF to a positon just outside the material (vacuum). Similarly, electron affinity
is energy required to remove an electron from the bottom of the conduction band EC to the vacuum
level.
The n-n heterojunction in GaAs/GaAlAs were found to result into the ohmic characteristic. Non-
ohmic behaviour was occasionally observed, but such junctions are found to be unstable. The explanation
of ohmic behaviour may lie in the fact that the formation of junction in practice is not abrupt but is
graded over a distance that may be comparable to the thickness, accumulation and depletion regions. In
this case the potential spikes would be submerged into more general variations and electrons and holes
would be able to flow freely across the junction in either direction in response to very less applied
voltage. A lattice mismatch as little as 0.1% is sufficient to produce considerable strain at the junction
and give rise to high concentration of trapping levels. The lattice-mismatched epitaxy is called the
strained layer epitaxy. The two basic requirements in the construction of energy band diagram are (1)
Fermi level of one material must be aligned to Fermi level of the other material under thermal equilibrium,
and (2) the vaccum level must be continuous and parallel to the band edges. Because of these requirements,
the discontinuities in conduction band edge DEC and valence band edge DEV will remain unaffected by
doping as long as the band gap EG and elctron affinity qc are not functions of doping (as in non-
degenerate semiconductor).
'$
Figure 2.35 Energy band diagram before and after an abrupt n-N heterojunction
The recombination velocity, v in m/s at the junction is defined as

a ao Da
v = 2 ¥ 105 = 2 ¥ 105 m/s (2.11.6)
ao ao
Where, ao fi substrate lattice constant
a fi epitaxial layer
2.11.2 Abrupt Anisotype Heterojunction

The type of junction that includes n-p or p-n heterojunctions are similar to the minority carrier device
like n-p or p-n homojunction. None of the models proposed by various researches for heterojunction are
able to explain all the physical phenomena like the model proposed by Shockley for homojunction. It is
because the properties of the interface vary greatly from material to material and depend largely on the
'%
method of formation. The existing models for the anisotype heterojunctions can be considered as an
extension of the model for the homojunctions.
A typical energy band diagram profile of two isolated pieces of p- and n-type semiconductors and
equilibrium energy band diagram of an abrupt p-n heterojunction are shown in Fig. 2.35. The spike and
notch shown in figure occur for the case cp>cn. In this figure it has been assumed that the anisotype
heterojunction of two semiconductors have different band gaps (EGP, EGn), different dielectric constants
(epeo, eneo), different work functions (fp, fn), and different electron affinities (cp, cn). Here, the p n
anisotype heterojunction junction is considered consisting of a small bandgap of p-type and large bandgap
n-type semiconductor layers.
The EV represents the top of the valence band. It is evident from Fig. 2.36 that discontinuity in the
conduction band edges (DEC) is equal to the difference in electron affinity of the two semiconductors.
The Fermi levels of the two semiconductors equalise when junction is formed. Similar to the homojunction,
heterojunction also introduces a depletion region on either side of the junction.
Figure 2.36 Energy band diagram before and after an abrupt p-n heterojunction
'&
The total built-in potential (yo) is due to the difference in the work function (fpfn) and is equal to the
sum of the built-in voltages on both(yo = Dyp + Dyn). If we assume the coordinate of the discontinuity
in the figure to appear at xo, then the transition width on either side of the interface for an abrupt p-n
junction are xn and xp.
Similar to the homojunction, the eletrostatic potential y(x), is constrained by the one dimensional
Poisson equation.
d 2y r
2 = - (2.11.7)
dx e oe s
where, r = local net charge concentration
eo and es = permitivity of air and semiconductor material
x = position of co-ordinate perpendicular to the junction
The depletion region voltages similar to the homojunction are defined as
e n N Dy o e p N Ay o
Dyp = and Dyn = (2.11.8)
e n ND + e p N A e n ND + e p N A
e n N Dy o e p N Ay o
Hence, Dyp + Dyn = + = yo (2.11.9)
e n ND + e p N A e n ND + e p N A
where q is the electronic charge, ep and NA are dielectric constant and concentration of acceptors in
p-type semiconductor, en and ND are dielectric constant and concentration of donors in n-type
semiconductor.
The corresponding depletion layer thickness in p- and n-type regions in a heterojunction are
1/ 2 1/ 2
ÔÏ 2 e n e p N Dy o Ô¸ ÔÏ 2 e n e p N Ay o Ô¸
xp = Ì ˝ and xn = Ì ˝ (2.11.10)
ÓÔ q(e n N D + e p N A ) N A Ô˛ ÓÔ q(e n N D + e p N A ) N D ˛Ô
xp ND ND ND
Hence, = ¥ = (2.11.11)
xn NA NA NA
The bending of the band at the heterojunction is equal to the built-in potiential yo that is expressed as
qyo = fp fn = (EGP + cp DEFp) (cn + DEFn) = EGP + Dc EFp DEFn (2.11.12)
According to Anderson model, the conduction band offset, DEC is
DEC = cp cn = Dc (2.11.13)
Similarly valence band offset is
DEv = (cn + EGn) (cp + EGP) = DEG Dc (2.11.14)
Hence, DEc + DEv = DEG (2.11.15)
If cp = cn, a very important and interesting application of heterojunction BJT is achieved. In such
condition, the offset in the conduction bands disappear and DEV = DEG. Hence
NC N
qyo = EGp EFp DEFn = EGP kBT ln kB T ln V (2.11.16)
n p
''
when n and p are the free carrier concentration in the n- and p-type semiconductors respectively.
However, there is one important difference in this case. The barrier to hole injection is increased by
DEV = DEG, as compared to a homojunction. Therefore, the elctron injection over the barrier is a more
efficient process than hole injection. This characteristic has been utilized in the design of heterojunction
BJT and phototransistors.
The continuity in displacement perpendicular to the junction surface requires
NAxp = NDxn (2.11.17)
Dy p N A x 2p en N A ND2 x n2 en N e
Hence, = ¥ = ¥ = D n (2.11.18)
Dy n ep ND x 2n e p N A2 N D x 2n N Ae p
The depletion widths in p- and n-type semiconductors across the heterojunction in Fig. 2.36 are
written as
1/ 2 1/ 2
R| 2 N e e e y
D p n o o U| R| 2 N e e e y A p n o o U|
xo xp = S| qN ( N e + N e V| and xn xo = S| qN ( N e + N e V| (2.11.19)
T A A p D n W T D A p D n W
Equation 2.11.19 is exactly the same as Eqn. 2.11.10.
The junction capacitance can be obtained as
A x p xn
= + (2.11.20)
C e p en
where A = area
1/ 2
The transition/depletion capacitance CT =

R| A N N e e e ¥ 1 U|
q A D p n o
(2.11.21)
S| 2( N e + N e ) y V|
T A p W D n o
Equation 2.11.21 changes on application of the external forward bais voltage V across the
heterojunction as
1/ 2
CT
R| A N N e e e ¥
=S
q A D p n o 1 U|
|T 2( N e + N e ) (y o V)
V| (2.11.22)
A p D n W
1. Calculate contact potential of a Ge diode Solution:

having donor impurity concentration N D = ND N A 10 22 ¥ 10 24
y D = VT ln = 0.026 ln
10 22 / m 3 , acceptor impurity concentration ni2 6.25 ¥ 10 38
N A = 10 24 / m 3 , and intrinsic concentration 10 8
= 0.026 ln = 0.026(ln 10 8 - ln 6.25)
2.5 ¥ 1019 / m 3 . 6.25

= 0.026(8 ¥ ln 10 - ln 6.25) = 2 ¥ 10-7 ¥ 16.83 ¥ 10-5

= 0.026(8 ¥ 2.3 - 1.83)
= 33.66 ¥ 10 -12 = 33.66 pF
= 0.026 ¥ 16.57 = 0.431 V
3. Calculate the saturation current density in
2. What is the value of depletion capacitance an abrupt junction having data like : N D =
across an abrupt p + - n junction of Si 10 21 /m 3 , N A = 10 22 / m 3 ,
with and without reverse bias of 4 V hav- Dn = 3.4 ¥ 10 -3 m 2 /s ,
21 3
ing y D = 0.8 V, N D = 4 ¥ 10 / m , e s = D p = 1.2 ¥ 10-3 m 2 /s ,
12, junction area = 4 ¥ 10 -7 m 2 ?
Ln = 7.1 ¥ 10-4 m ,
Solution:
L p = 3.5 ¥ 10 -4 m ,
In p + - n junction N A >> N D , hence CT =
ni = 1.5 ¥ 1016 / m 3 ,
1/ 2
A Ï 2 qe s e o N D ¸ junction area = 10 -6 m 2 .
Ì ˝ ,
2Ó yD ˛ Solution:
1/ 2 Since, nn pn = ni2 , pn = ni2 / nn

A ÏÔ 2 qe s e o N D ¸Ô
CT = Ì ˝ = 2.25 ¥ 1011 / m 3 .
2 ÔÓ y D - V Ô˛
Now, J 0 = q
FD n
np +
Dp
pn
I
=
4 ¥ 10 -7 GH L
n Lp JK
2
1/ 2
R| 2 ¥ 1.6 ¥ 10 -19
¥ 12 ¥ 8.854 U| = 1.59 ¥ 10 -7 A / m 2
¥ 10 -12 ¥ 4 ¥ 10 21 4. Calculate the depletion width and maxi-
S| 0.8
V| mum field at zero bias for a p + - n abrupt
|T |W junction with N A = 10 25 / m 3 , N D =
-10 ¸1/ 2
ÔÏ 2 ¥ 1.6 ¥ 12 ¥ 8.854 ¥ 4 ¥10 Ô 10 22 / m 3 , ni = 1.5 ¥ 1016 / m 3 , and built-in
= 2 ¥ 10 -7 Ì ˝
ÔÓ 0.8 Ô˛ potential = 0.576 .
1/ 2 Solution:
{
= 2 ¥ 10 -7 1699.97 ¥10 -10 }
2ey D
= 2 ¥ 10-7 ¥ 41.23 ¥ 10-5 W=
qN D
= 82.46 ¥ 10 -12 = 82.46 pF
CT (4 V) = 2 ¥ 12 ¥ 8.854 ¥ 10 -12 ¥ 0.576
=
1/ 2 1.6 ¥ 10 -19 ¥ 10 22
Ï 2 ¥ 1.6
7 Ô ¥ 12 ¥ 8.854 ¥ 4 ¥10 10 Ô¸
2 ¥ 10 Ì ˝
ÔÓ 0.8 + 4 = 76.5 ¥ 10 -15 = 7.65 ¥ 10 -14
˛Ô
1/ 2 = 2.76 ¥ 10 -7
{
= 2 ¥ 10 -7 283.32 ¥10 -10 }

= 0.276 micron
2 ¥ 12 ¥ 8.854 ¥ 10-12 ¥ 1.5 ¥ 1022 ¥ 1.5
qN D W =
Maximum field = E m = 1.6 ¥ 10-19 ¥ 9 ¥ 1050
es
1.6 ¥ 10 -19 ¥ 10 22 ¥ 2.76 ¥ 10 -7 2 ¥ 12 ¥ 8.854 ¥ 1.5 ¥ 10 -21 ¥1.5
= =
12 ¥ 8.854 ¥ 10 -12 1.6 ¥ 9
1.6 ¥ 108 ¥ 2.76 = 33.203 ¥ 10-21 = 3.3203 ¥ 10-20

= = 0.042 ¥ 10 8
12 ¥ 8.854
= 1.82 ¥ 10 10 m
6
= 4.2 ¥ 10 V/m
2e ne p N Ay D
5. Obtain electrostatic potential and depletion xn =
width in each material having an ideal qN D (e n N D + e p N A )
abrupt anisotype heterojunction with built-
in potential of 15 V, impurity concentra- 2e n N Ay D
=
tion in p-type = 3 ¥ 1025 acceptors/m3 qN D ( N/ D + N A )
and in n-type 1.5 ¥ 1022 donors/m3. The
dielectric constant of Si is 12 . 2e n N Ay D 2e ny D
= =
Solution: qN D ¥ N A qN D
e n N Dy D N Dy D = 11.52 ¥ 106 m
yp = =
e n ND + e p N A N/ D + N A 6. Calculate depletion width and maximum
N Dy D field in case of graded junction of Si with
= impurity concentration gradient =
NA
10 28 / m 3 , contact potential = 0.645V , ni
1.5 ¥ 10 22 ¥ 1.5
= = 0.75 ¥ 10 3 V = 1.5 ¥ 1016 / m 3 .
3 ¥ 10 25
Solution:
e p N Ay D N Ay D
yn = = 2 2
e n ND + e p N A N/ D + N A
y = V lnG
F aW I = 0.026 ln F 10 W I 28
=
N Ay D
= y D = 15 V
D
H 2n JK
T
i
GH 2n JK i
NA F 10 W IJ = 0.645 = 24.8
28 2
= 0.645V , lnG
Depletion width = xp H 2n K 0.026 i
2e ne p N Dy D 2
F 10 W I = e = 5.89 ¥ 10 ,
28
= 24.8 10
qN A (e n N D + e p N A ) GH 2n JK i
2
=
2e n N Dy D
=
2e n N Dy D FG 10 W IJ = 2.43 ¥ 10
28
5
qN A ( N D + N A ) qN A ( N/ D + N A ) H 2n K i
2e n N Dy D 2.43 ¥ 10 5 ¥ 2 ¥ 1.5 ¥ 1016

= W=
qN A2 10 28

= 2.43 ¥ 2 ¥ 1.5 ¥ 10 -7 1.6 ¥ 10 -19 ¥ 10 28 ¥ 53144

. ¥ 10 -14
=
= 7.29 ¥ 10 -7 = 0.73 micron 8 ¥ 12 ¥ 8.854 ¥ 10 -12
qaW 2 1.6 ¥ 53144

. ¥ 10 -7
Maximum field = Em = = = 0.01 ¥ 10 -6 V/m
8e s 8 ¥ 12 ¥ 8.854
Questions for Practice or recombinations take place in the space

charge region?
1. Show that the capacitance across a graded 9. Why is the space charge region also called
junction is inversely proportional to the the depletion region?
one third power of effective voltage ap- 10. What is the size of the depletion width
plied across it. (micron, milli metre, and centimetre)?
2. How does the concentration gradient of the 11. What is the size of inherent potential barrier
impurity affect the value of junction ca- across the homojunctions of Ge and Si
pacitance of graded junction diode? diodes? What does their polarity look like?
3. Show that the depletion layer capacitance 12. What is the effect of the external voltage
of an abrupt n + - p junction (CT) can be applied across the homojunction? Explain
1/ 2
forward and reverse bias.
|R N |UV
approximated as K S A
.
13. What do you understand by reverse
1
|T by - V g |W saturation current? What gives rise to it?
D
What is the ratio of forward and reverse
4. Draw the band diagram for a forward biased current in a homojunction diode?
p-n homojunction showing clearly the quasi 14. When does the homojunction diodes offer
Fermi-levels Fn(x) and Fp(x) throughout the very high resistance?
homojunction and for several diffusion lengths 15. What proportion of impurity should be mixed
on either side of the homojunction. Explain in an intrinsic Ge or Si for manufacturing a
qualitatively the variations in Fn and Fp. homojunction diode?
5. Explain why the charge storage capacitance 16. Show that the diffusion capacitance across
is not important for a reverse biased a forward biased abrupt junction is given
homojunction.
gt
6. Sketch energy band diagrams to distinguish as CD = , where g is the diode incre-
between a metal, an insulator and a h
semiconductor. mental conductance.
7. Which types of charges are present on the 17. What happens to the diffusion capacitance
two opposite faces of the homojunction in the reverse bias case? (CD neglected
(electrons, holes, immobile negative charge, w.r.t. CT)
immobile positive charge)? 18. How do the CT and CD compare in for-
8. What types of carriers are present in the ward bias case? (CT <<< CD).
space charge region? Do carrier generation
!
19. Calculate the value of diffusion capaci- (a) forward bias

tance across the abrupt junction of a for- (b) reverse bias
ward biased Ge diode ( h = 1) if 26 mA (c) without forward and reverse biases
current passes through it. (26 mA/26 mV 4. Depletion width has
= g = 1 / W , CD = t ). (a) negative charge carriers
20. What is the value of diffusion capacitance (b) positive charge carriers
if the lifetime of the minority carrier is (c) no charge carriers
20 ms? (20 mF). 5. Depletion width with forward bias
21. What would be the time constant of the (a) increases
diode in Problem-7? (time constant = (b) decreases
C D /g = very small due to very small dy- (c) remains constant
6. Homojunction capacitance with increasing
namic conductance of the diode).
reverse bias
22. Obtain donor concentration in an abrupt Si
(a) increases
p-n junction with electrostatic potential of
(b) decreases
0.774 V , N A = 10 24 / m 3 , (c) remains constant
ni = 1.5 ¥ 1016 / m 3 at 300 K. 7. Forward bias across p-n homojunction
means
ND N A (a) only positive terminal connected to p-
y D = VT ln ( N D = 1.9 ¥ 10 21 / m 3 )
ni2 type
23. How is a varactor diode used for tuning a (b) positive terminal connected to p and
TV? negative to n
24. How is a Schottky diode callled hot carrier (c) positive terminal connected to n and
diode? negative to p
25. How is a Schottky diode different from a 8. In an unbiased p-n homojunction current
singal diode? does not flow because
26. How do you distinguish between two leads (a) carriers do not cross the homojunction
of an LED? (b) equal and opposite charge carriers
cross the homojunction
(c) same type of charge carriers cross the
Multiple Choice Questions homojunction in opposite direction
9. Diffusion current is due to
1. The potential barrier across a p-n homojunc-
(a) different concentrations of the two
tion is due to
(a) negative and positive charge carriers types of charge carriers in the same
region
on the same side
(b) different concentrations of same type
(b) immobile donor and acceptor ions
of charge carriers in different regions
(c) negative and positive charge carriers
(c) same concentration in two regions
on opposite sides
10. Total current through any p-n homojunction
2. Depletion voltage is
is only due to
(a) more for Ge
(a) drift of charge carriers
(b) more for Si
(b) diffusion of charge carriers
(c) equal in Si and Ge
(c) both types of charge carriers
3. Depletion voltage increases with
"
11. The forward current in p-n homojunction 20. With rise in temperature reverse saturation
increases rapidly current
(a) from zero onwards (a) increases linearly
(b) only after the value of potential barrier (b) increases exponentially
(c) when the depletion area becomes (c) decreases linearly
equal to space charge area 21. With increasing temperature, the
12. Zener breakdown refers to homojunction voltage
(a) forward bias region (a) increases
(b) reverse bias region (b) decreases
(c) no bias region (c) remains constant
13. Avalanche breakdown voltage is 22. The current of a semiconductor diode is
(a) lower than Zener expressed as
(b) higher than Zener
(c) equal to Zener breakdown voltage
F qV
(a) Io, exp KT 1
I
14. Zener breakdown depends on
GH JK
(a) electric field created across the deple- (b) Io, KT
tion region
(b) velocity of the carries I
(c) o
(c) no. of donor ions KV
(d) no. of acceptor ions F qV
I
15. Both avalanche and Zener breakdowns are (d) Io, exp KT 1
GH JK
commonly known as
(a) Zener breakdown 23. The dynamic resistance of a diode is ex-
(b) avalanche breakdown pressed as
(c) current breakdown
25 mV 1(mA)
16. Zener diodes are (a) (b)
(a) specially doped p-n homojunction 1(mA) 25 mV
(b) normally doped p-n homojunction V
(c) lightly doped p-n homojunction (c)
1(A)
17. Zener diodes are used as
(a) reference voltage elements 24. Potential barrier for Ge p-n homojunction is
(b) reference current elements (a) 0.2 V (b) 0.02 V
c) reference resistance (c) 0.7 V
25. Potential barrier across Si diode is
18. The reverse saturation current with increas-
(a) 0.2 V (b) 0.7 V
ing reverse bias
(c) 1 V
(a) increases
26. The voltage drop across an ideal diode is
(b) decreases
(a) 0.2 V (b) 0.7 V
(c) remains constant
(c) 0 V
19. The magnitude of reverse saturation current
27. Resistance of an ideal diode is
is
(a) very large (b) zero
(a) less than forward current
(b) larger than forward current (c) small.
(c) equal to forward current
#
28. The current flow in a diode is 37. The reverse saturation current Ico of Si di-
(a) unidirectional ode varies as
(b) bi-directional (a) T2 (b) T3
1/2
(c) none of these (c) T (d) T3/2
29. Diode is a 38. Schottky diode is
(a) polar sensitive device (a) a p-n homojunction device formed by
(b) non-polar sensitive device using two-different semiconductors
(c) bipolar sensitive device (b) a metal semiconductor device formed
30. Diodes can be used as by using materials of opposite work
(a) amplifier functions
(b) rectifier (c) a device consisting of a semiconduc-
(c) filter tor and a noble metal
31. V-I characteristics of diode can result in (d) an ordinary point contact diode
(a) static resistance only 39. If the reverse bias applied across a step p-n
(b) dynamic resistance only homojunction diode is increased four-times,
(c) none of these then the depletion layer capacitance of the
32. Diffusion current in a p-n homojunction is diode becomes
influenced (a) half (b) double
(a) by concentration gradient of carriers (c) one-third (d) one-fourth
(b) applied voltage 40. A Schottky diode has
(c) concentration of carriers (a) a larger voltage drop than that of an
33. Drift current is influenced by ordinary diode
(a) magnitude of voltage (b) good ohmic resistance
(b) concentration of carriers (c) a negligible storage time
(c) concentration gradient of carriers (d) mainly minority carrier current
34. Increasing reverse bias 41. The ECL gates are basically meant for
(a) decreases the homojunction capacitor (a) low power
(b) increases the homojunction capacitor (b) high power
(c) has no effect on its capacitor (c) high speed
35. Homojunction capacitance is related with (d) high voltage
barrier potential as 42. In a p-n homojunction diode
(a) C = KV1/2 (a) the depletion capacitance increases
(b) C = KV1/2 with increase in the reverse bias
(c) C = KV (b) the depletion capacitance decreases
K with dicrease in the reverse bias
(d) C = (c) the diffusion capacitance increases
V
36. Reverse break down in p-n homojunction with increase in the forward bias
at high temperature occurs (d) the diffusion capacitance is much
(a) at higher reverse bias higher than depletion capacitance
(b) at lower reverse bias when forward biased
(c) at forward bias
$

1. (b) 2. (b) 3. (b) 4. (c) 5. (b) 6. (a)
7. (b) 8. (a) 9. (b) 10. (c) 11. (b) 12. (b)
13. (b) 14. (a) 15. (a) 16. (a) 17. (a) 18. (a)
19. (a) 20. (b) 21. (b) 22. (a) 23. (a) 24. (a)
25. (b) 26. (c) 27. (b) 28. (a) 29. (a) 30. (b)
31. (a) 32. (a) 33. (a) 34. (b) 35. (a) 36. (c)
37. (d) 38. (b) 39. (a) 40. (c) 41. (c) 42. (a) and (d)
3
Diode as Circuit Element
3.1 Introduction
The basic structure and circuit symbol representation of a p-n junction diode is shown in Fig. 3.1. The
VI characteristics of a diode are a plot of dc diode current I versus the external dc voltage applied
across plate to cathode of the diode.
Figure 3.1 p-n junction representation
The entire VI characteristic can be divided into two regions:

∑ Forward characteristic
∑ Reverse characteristic.
3.2 Forward Bias Characteristic

The p-n junction is a two-terminal unidirectional semiconductor device. It is polarity sensitive. The
current flows through it offering negligible resistance for one type of polarity of voltage applied across
the semiconductor diode. If the applied polarity of the voltage is reversed, almost no current flows
&
through the diode. The ideal situation would have only two values either zero or infinity. Hence, ideal
diode will not pass any current through it or will pass infinite current. In an ideal diode under forward
bias condition, infinite current flows through it as shown in Fig. 3.2.
Figure 3.2 Ideal diode characteristic
The amount of current that flows through the diode can be obtained by the value of external voltage
and external resistance connected across it. No current flows through the diode in reverse bias condition.
Thus, an ideal diode should behave as a switch, i.e. either it is open (does not conduct) or closed (fully
conducts) depending on the polarity of voltage applied across it.
The basic shape of the VI characteristic for both forward as well as reverse biases of any homojunction
diode is shown in Fig. 3.3. A glance at VI characteristic reveals that the current is almost zero for
V < 0.2 V/0.5 V and at V = 0.2 V/0.5 V the diode just starts conducting. This value is referred to as cut-
in voltage. The voltage drop across a fully conducting Si diode lies in the narrow range of 0.6 V to
0.8V. Normally, the voltage drop for a fully conducting Si diode is assumed to be 0.7 V.
Figure 3.3 Circuit and V–I characteristic of junction diode
The circuit symbol of the diode looks like an arrow indicating the direction of flow of the conventional
current through it, under forward biased condition. The load resistance RL is included in the circuit to
limit excessive current flow through the diode. Potentiometer is used to adjust very small variation of
voltage to be applied across the diode.
The junction current voltage relationship is of the form
( ) (
I = I o expqV / h KT - 1 = I o expV / hVT - 1 ) (3.2.1)
Diodes as Circuit Element
'
where, Io = reverse saturation current

K = Boltzmann constant
h = ideality factor = 1 or 2 depending upon material and physical structure.
T = Absolute temperature
KT
VT = @ 25 mV
q
Examples
1. The saturation current density of a pn junction Ge diode is 1 mA/m2 at 300 K. Calculate the
voltage required to be connected across it to cause the current of density 10 5 mA/ m 2 to flow
through it.
Solution:
J = Jo exp qV /KT - 1 ,
d i
J 105 qV
exp qV / KT = 1 + = 1+ = 105, = ln 10 5 = 11.52 d i
Jo 1 KT
V = 25 mV × 11.52 = 288 mV ∫ 0.3 V.
2. Determine the ideality factor h from the V I relationship
F qV
hKT
I
I= I G exp JJ
- 1 of the semiconductor diode. This relationship yields 0.5 A at 0.34 V and
o
GH K
15 mA at 0.44 V.
Solution:
qV qV
hKT hKT
As V >> 25 mV, 1 << exp and hence I = Io exp
V 40V 40 ¥ 0.34 13.6

h0.025
0.5 A = I exp = Io exp h = I exp h
= Io exp h
o o
40V 40 ¥ 0.44 17.6
h h h
15 mA = Io exp = Io exp = Io exp
17.6
4
15 exp h
Now, = 30 = = exp h
0.5 13.6
exp
h
4 4
h= = = 1.18
ln 30 3.4

A more elaborate VI characteristic of pn homojunction diode curve is shown in Fig. 3.4. No current
flows through the diode if externally applied voltage across it is less than the depletion voltage (0.2 V for
Ge and 0.6 V for Si). Above this voltage, current increases very rapidly with slight increase in the
forward voltage across the diode as shown in Fig. 3.4. The large current through the diode may destroy
the diode junction due to excessive heat. For this reason a manufacturer specifies the maximum current
that a diode can handle safely. For example, BY126 can deliver a maximum current of 1 A.
Figure 3.4 Characteristics of Ge/Si diodes
3.3 Reverse Bias Characteristic

The diode becomes reverse biased if the polarity of the battery connection is reversed in Fig. 3.3. In
reverse bias condition very small current flows. This current is called leakage or reverse saturation
current of the diode. The reverse bias is increased to a high value V, a new phenomenon called breakdown
of crystal occurs. In this region high current may be passed through the diode and the external circuit
resistance limits it. The high current may generate enough heat to destroy the junction and hence, diodes
have maximum reverse voltage ratings also. In normal condition this is avoided.
We see from Fig. 3.4 that a single equivalent circuit for the diode would be extremely complicated
and therefore cumbersome to use as a circuit element. In order to avoid this complexity, we break up
the diode characteristic in three regions as shown in Fig. 3.4 and use the piece-wise linear model for
each region.
3.4 Equivalent Circuit of Semiconductor Diode

The diode in region-1 is forward biased and its linear model in this region is shown in Fig. 3.5. The
straight line shown in Fig. 3.5 approximates the actual VI characteristics of the diode. The actual
characteristic curve of the diode must be used if its approximate linear equivalent circuit does not
provide an accurate result for its analysis.

The diode will not turn ON unless voltage between plate to cathode is more than VDO. Here, diode
resistance rd is the dynamic resistance. Now, each linear equivalent circuit of the diode can be represented
mathematically by a straight line as
y = mx + C
or, ID = VD /rd + C
where, y = ID = diode current
x = VPK = VD = plate to cathode voltage
0 = VDO /rd + C
or, C = intercept on the diode current axis = VDO / rd
m = 1/rd = slope of the load line
Figure 3.5 Linear model of diode characteristic
The equivalent circuit of the diode is shown in Fig. 3.5. The diode current and voltage is now expressed
as
ID = (VD VDO)/rd
Thus, an actual or real or practical p-n junction diode deviates from an ideal diode in the manner that
it has a diode resistance rd and a voltage drop VDO inherent in it. The dynamic diode resistance can be
obtained from the diode equation as
ID = Io (exp qV/KT 1) @ Io (exp qV/KT)
dID q q
= Io exp qV / KT =
d i ID (3.4.1)
dV KT KT
dV KT 1 26 mV
= rd = ¥ = W (3.4.2)
dID q ID ID(mA)
The current in the reverse bias region-2 is essentially equal to the reverse saturation current Io and seems
to be independent of the applied reverse bias. The equivalent circuit in region-2 is just a constant current
source of magnitude Io as shown in Fig. 3.6. The dynamic resistance in this region-2 is essentially
infinite and the current remains almost constant at the value Io. Hence, the diode in region-2 can be
equated as a constant current source as indicated in Fig. 3.6.

Figure 3.6 Equivalent circuit in region-2
Figure 3.7 Equivalent circuit in region-3
We know from Fig. 3.3 that an abrupt change in current takes place at one voltage called breakdown
voltage, when very large current starts flowing through it that can damage the normal diode. In other
words, the breakdown voltage remains constant for large change in current in region-3. The equivalent
circuit of diode in reverse bias region-3 is just a bettery (constant voltage VZ ) as shown in Fig. 3.7. In
breakdown diodes this characteristic is utilized with proper design or providing adequate dissipation in
this region to avoid damage of the diode. The PIV of the p-n junction must be less than or equal to half
of the breakdown voltage for its safe operation.
Example
3. Obtain the static and dynamic resistance of the p-n junction Ge diode if the temperature is 27°C
and Io = 1 mA for an applied forward bias of 0.2 V. Assume K = 1.38 ¥ 10 23 J/K.
Solution: The pn junction diode equation is written as
ID = Io exp qV /KT - 1
d i
-6
F 1.6 ¥10 -19 ¥ 0.2
1.38¥10-23 ¥ 300
I
= 1 ¥ 10 GG exp JJ
-1
H K
F 32
I
= exp 4.14 - 1 mA = (exp7.7295 - 1) m A
GH JK
= 2274.4 mA = 2.2744 mA
V 0.2
Thus, static resistance = = = 88 W
I 2.27 mA
DV
The dynamic resistance rd = ,
DI
qV
and
DI
= Io
q F Ie KT
DV KT H K
!
=I
F q I = I (mA)
H KT K 25 mV
DV 25 mV
Hence, rd = =
DI I (mA)
25 mV
= = 11.45 W.
2.27 mA
3.5 Load Line Analysis of Diode

The actual characteristic curve of the diode must be used if its approximate linear equivalent circuit does
not provide an accurate result for its analysis.
3.5.1 Analysis for dc Voltage

The circuit of Fig. 3.8 is considered here for dc load line. The amount of current that will flow through
the circuit of Fig. 3.8 and voltage developed across the load will depend on the static resistance of the
diode. Diode resistance also depends on the current flow through it. Since the diode resistance and
current are interdependent parameters, we will assume the first as independent variable. The second
parameter can be automatically taken care of, if it is analyzed on the static VI characteristic of the p-n
junction diode shown in Fig. 3.8.
Equation 3.5.1 relates two variables of the diode, i.e. diode current ID and diode voltage VD. These
represent a number of pairs of co-ordinates for given V and RL. Two such pairs can be obtained. One
pair of such co-ordinates is ID = 0, VD = V and the other is VD = 0, ID = V / RL). A line joining these two
points will satisfy all possible combinations of the variables ID and VD that will satisfy the initial conditions.
This line is called the load line. Intersection of the load line with the static characteristic curve of the
diode gives the operating point or quiescent point (Q-point). This is the point of equilibrium at which just
enough current flows in the circuit to cause the correct voltage drop to occur across the diode so that
the output voltage is the balance of the input voltage. In other words total input voltage is divided into a
part across the diode and a part across the load as illustrated in Fig. 3.8.
Figure 3.8 dc load line

"
In this example the diode current seems to be 8 mA, diode voltage drop is 1.2 V and load voltage is
0.8 V. The total resistance in the circuit = rd + RL = 250 W. This amount of resistance will allow
(2/0.250 K) = 8 mA of current to flow through the diode that checks the result.
3.5.2 Load Line Equation
As, V = VAK + ID RL (3.5.1)

ID = (V VAK)/RL (3.5.2)
Since VAK and RL are fixed when diode starts conducting, then VAK/RL = C. (3.5.3)
Hence, ID = V / RL + C (3.5.4)
This can be compared with the standard equation of straight line
y = mx + C (3.5.5)
where, y = ID = diode current
x = VAK = VD = plate to cathode voltage
C = intercept on the diode current axis
m = 1/RL = slope of the load line
For a given input voltage V the lower value of the load resistance RL will have steeper load line and result
in the higher value of quiescent current.
Example
4. Obtain the voltages (VL) across the load resistance RL and across the diode VD for the symmetrical
trapezoidal waveform of the source voltage V shown in Fig. 3.9. The equivalent circuit in Fig. 3.9
represents the diode characteristic.
Figure 3.9
Solution:
Vi - VD 5-2 3
ID = = =
rs + rd + RL 0 + 100 + 1 K 1.1 K
(Vi - VD ) RL (5 - 2) ¥ 1 K
(a) For rd π 0, VL = RL ID = = = 2.72
rs + rd + RL 1.1 K
#
(5 2) ¥ 0.1 K
ID rd = = 0.273 V
1.1 K
(5 - 2)1 K
(b) For rd = 0, VL = RL ID = =3V
1K
3.6 Use of Zener Diode

There are a variety of diodes that are used for special purposes. Some of the most important amongst
them are described here in brief. The basic functions and characteristics of different types of diodes
have been described in Article 2.9.6. We would like to discuss here only the behaviour of the diode as
the circuit element. The signal diodes have been used as demodulators for RF signals, the power diodes
are used mainly for rectification. The Zener diode is used as a reference element. Very often we will be
using Zener diodes and hence, its behaviour as circuit element is taken up here.
The main function of the Zener diode is to provide constant output voltage Vo= VL irrespective of
either change in the input voltage VI or change in the load current IL for the circuit shown in Fig. 3.10.
Hence, line regulation and load regulation are two requirements of the Zener regulator.
Figure 3.10 Zener regulator
DVL
Line regulation = V/V
DVI
DVL
Load regulation = mV/1
DI L
II = IZ + IL
VI - VL V - VZO
= L + IL
R rz
V1 V V V
or, = L + L ZO + IL
R R rz rz
or,
F
V1 = V 1 + 1 I FV I + I
ZO
= VL
FG R + r IJ FG V IJ + I
Z ZO
R
L GH
R rz JK GH r JK
Z
L
H Rr K H r K
Z Z
L
$
or, VL =
VI rz V R
+ ZO
FGrz R IJ
IL
R + rz R + rz H
rz + R K
DVL r DVL rR
Line regulation = = Z and load regulation = = Z
DVI R + rZ DI L rZ + R
Example
5. The circuit diagram of a regulated power supply is shown in Fig. 3.11. The Zener diode charac-
teristic is given as VL = 8 + RID, where, VL and ID are the load voltage and diode current respectively
with RL = 10 W. If the minimum rated current of the diode is 0.2 A, calculate the minimum value
of Rs. Find the range of RL so that load voltage is maintained at the Zener voltage with IZK = 5 mA.
Figure 3.11 Regulated power supply
Solution:
For maximum rated current of 0.2 A, the load voltage = VL = 8 + 10 ¥ 0.2 = 10 V.
The maximum current is drawn for unregulated voltage of 15 V and regulated load voltage of
10
10 V. Hence, load current = IL = = 1 A.
10
Now, the current drawn from the unregulated power supply = 1A + 0.2 A = 1.2 A
15 - 10 5
The minimum value of Rs = = = 4.17 W.
1.2 1.2
The maximum load current = ILm = 1.2 0.005 = 1.195 A
The minimum value of load resistance is equal to the load (Zener) voltage upon maximum load
current = 1.195 A, i.e.
10
RL(min) = = 8.369 W.
1.195
Hence, load resistance can range from 10 W to 8.4 W.
117
3.7 Clamper
Figure 3.12(a) is a diode positive clamper. In the first negative half cycle of the input voltage diode turns
ON as indicated by shorting of a switch in Fig. 3.12(b). The capacitor charges to the peak value of the
input voltage Vp instantly. In the positive half cycle of the input voltage, diode turns OFF as indicated by
the switch in Fig. 3.12(c). The time constant RLC w.r.t. to the time period T of the input signal is kept
very large. For this reason the capacitor remains fully charged during OFF time of the diode. Thus, we
can assume that the capacitor is acting as a battery of Vp volts. This is the reason the output voltage is
positively clamped in Fig. 3.12(a). Figure 3.12(d) is the circuit of non-ideal positive clampper.
If we turn the diode of Fig. 3.12(d) up side down, Fig. 3.12(e) results. This is the circuit of a negative
clamper. We see from Figs. 3.12(a) and 3.12(e) that the output waveshapes shift in the direction the
diode points toward.
Figure 3.12 Positive and negative clampers
Clipper
In the positive half cycle of the input voltage diode D starts conducting if VI > V. For VI > V, Vo is held
constant at voltage V. Thus, positive voltage more than V is clipped off as indicated in Fig. 3.13. In the
118
negative half cycle, the diode does not conduct, and hence output voltage developed across the load
resistance RL is equal to the input voltage.
Figure 3.13 Diode positive clipper
The diode of Fig. 3.14 in positive half cycle of the input voltage does not conduct and output voltage
is equal to the input voltage. However, in the negative half cycle, the diode conducts when the input
voltage is more negative than V. Hence, for VI < V, VRL = V and negative input voltage less than V is
clipped off.
Figure 3.14 Diode negative clipper
1. Two Ge diodes are connected as shown in Solution:

Fig. 3.15(a) to protect a milli ammeter (i) Since 1 mA is full-scale deflection, total
from damaging due to an overload to di- IT = 1 mA will flow through the milli
vert the current in either direction. These ammeter and its deflection will be 1mA.
diodes provide shunting effect when it be-
comes excessive. The resistance of milli
ammeter is 100 W and full-scale deflection
is 1 mA. The diode is represented by its
equivalent circuit shown in Fig. 3.15(b)
with its Vo = 0.2 V. The resistance of the
diode, rd = 25 /rd.
(i) When IT = 1 mA, how much current
flows through the milli ammeter?
(ii) When IT = 5 mA, how much current
flows through the milli ammeter?
(iii) When IT = 10 mA in the opposite
direction how much current flows
through the milli ammeter?
119
Solution:
The diode D2 is connected in reverse
biased mode, the reverse biased
saturation current Io will flow through
both diodes.
For diode D1, ID1 = Io
Figure 3.15 = I o (exp qV1 / KT - 1)

For diode D2, Io = - Io (exp - qV2 / KT - 1)
The equivalent circuit for conditions (ii)
qV1
and (iii) are in Figs. 3.15(b) and(c).
Thus, Io (exp KT - 1)
Ê 25 mV ˆ -
qV2
From Fig. 3.15(b), Á 0.2 V + ID ˜ = Io (exp KT - 1)
Ë ID ¯
qV1 qV
- 2
b g
= 0.10 5 - I D and exp KT + exp KT = 2 (proved)
0.225 Since, D2 is reverse biased,
= 5 ID qV2
0.1 -
exp KT << 1
or, ID = 5 2.25 = 2.75 mA
qV1
IA = 2.25 mA exp KT = exp 40V1 = 2, 40V1 = ln 2
From Fig. 3.15(c),
= 0.693,
(0.2 V + 25 mV) = 0.10(10 ID) 0.693
ID = 10 2.25 = 7.75 mA and V1 = = 0.0173 V.
40
IA = 2.25 mA 3. Two identical diodes having Io = 0.1 mA,
2. Two ideal diodes with ideality factor h = 1 VT = 25 mV, and h = 2 are connected as
are connected back to back as in Fig. 3.16. shown in Fig. 3.17. The externally con-
qV1 qV2
- nected voltage is 15 V and RL = 100 K.
(i) Show that exp KT + exp KT = 2, where Calculate the current in the circuit and volt-
V1 and V2 are voltages drops across age across each diode.
diodes.
(ii) Assuming that the reverse biased diode Solution:
is saturated at Io, calculate the voltage Since diode D2 is connected in reverse bi-
drop across the forward biased diode ased mode, the current flows in the circuit
(KT/q = 25 mV). = Io = 0.1 mA.
(GATE)
Figure 3.17
Figure 3.16
120
Voltage drop across forward biased diode VD = I K ¥ 4.496 mA + 0.5

qV
1 -
qV
2 = 0.505 V.
hKT hKT 5. Obtain the resistance offered across the AB
is obtained from exp + exp = 2.
qV
2
in Fig. 3.19.
-
hKT
In this expression exp << 1 and
qV1
+
h KT
hence, exp = 2.
40V1
exp 2 =2, 20V1 = ln 2 = 0.693 and
0.693
hence V1 = = 0.03465 V.
20
Voltage drop across the load = 100K ¥
0.1mA = 0.01 V
Voltage drop across reverse biased diode
D2 = 15 (0.0346 + 0.01) = 14.955 V.
4. The diode used in Fig. 3.18(a) has the
threshold voltage of 0.5 V and a forward
resistance of 1W. Calculate the current
flow ID through and voltage drop VD
across the diode.
Figure 3.19
Solution:
For positive half cycle the circuit of Fig.
3.19(a) reduces to Fig. 3.19(b) and in
negative half cycle it reduces to Fig.
3.19(c). Resistance across AB = 1 K in
both Figs. 3.19(b) and(c).
6. The Zener diode VZ1 in Fig. 3.20(a) has the
saturation current of 20 mA and reverse
breakdown voltage of 100 V whereas the
Figure 3.18 corresponding values for diode VZ2 are
Solution: 40 mA and 40 V. Determine the current
through the circuit.
Writing KVL,
5 = (1 K + 1) I D + 0.5 ,
4.5
ID = = 4.496 mA and
1.001
121
Figure 3.20
Solution:
In Fig. 3.20(a) the Zener diode VZ2 is re-
verse biased and VZ1 is forward biased. As
both zener diodes VZ1 and VZ2 are con-
nected in series, the reverse saturation cur-
rent 50 mA of VZ2 will flow clock-wise in
the circuit as 50 V reverse bias appears Figure 3.21
across the VZ2 diode.
7. Obtain plot of output voltage for various 8. Obtain and plot the transfer function of the
diode circuits shown in Figs. 3.21. diode circuits shown in Fig. 3.22(a) as-
suming both diodes to be ideal.
Figure 3.22
Solution:
For V2< VI < V1, both diodes are not con-
V ¥1
ducting and hence, Vo = I = 0.5 VI
2
122
For VI > VI , diode D1 conducts and Vo = 100 - 25

V1 . Hence, Vo = 75 V, ID1(max) =
5K
For VI < V2, diode D2 conducts and Vo =
V2 . 75 - 25
= 15 mA, ID2(max) = = 5 mA
These conditions have been plotted in Fig. 10 K
3.22(b).
9. Obtain the output voltage of clipper circuit
shown in Fig. 3.23(a) for the sinusoidal
input voltage with its peak voltage of
100 V, assuming both diodes ideal. What is
the maximum current through each diode?
Solution:
For VI < 25 V, diode D1 cuts-off and D2
conducts as in Fig. 3.23(b).
Ê 75 - 25 ˆ
Hence, Vo = 75 - Á 5K
Ë 10 K ˜¯
= 75 5 mA ¥ 5 K = 50 V
Figure 3.23 (c) and (d)
10. The circuit of Fig. 3.24 assumes that the

diodes are ideal and the meter is an average
indicating ammeter. The meter will read
(a) 0.4 2 mA , (b) 0.4 mA,
0.8 0.4
(c) mA, (d) mA .
p p
I 4 0.4
Iav = IDC = m = = mA
p 10 K ¥ p p
Figure 3.23 (a) and (b)
For 50 V < VI < 75 V, both diodes D1 and D2

will conduct as in Fig. 3.23(c). Hence,
Vo = VI.
For VI > 75 V, diode D1 conducts as in Fig. Figure 3.24
3.23(d) and hence, voltage at the cathode of 11. Two identical diodes, D 1 and D 2 are
D2 will be = VI that is sufficient to reverse connected back to back as in Fig. 3.25(a).
bias diode D2.
123
The reverse saturation current Io of each (b) 5 mA, 110 mA (c) 10 mA, 55 mA
-8
diode is 10 A and the breakdown voltage (d) 60 mA, 180 mA.
VBR is 50 V. Evaluate the voltage dropped 9-6 3
across each diode assuming KT/q = 25 mV. IS = = = 60 mA
50 W 50 W
300 mW
IZ(max) = = 50 mA
6
IL(min) = 10 mA
The maximum load current = 60 5
= 55 mA
Hence, option(c) is correct.
Figure 3.25
Figure 3.26
Solution: 13. The 6 V Zener diode shown in Fig. 3.27

Diode D1 is reverse biased and diode D2 is has zero Zener resistance and a knee cur-
forward biased, but as both diodes form a rent of 5 mA. The minimum value of R so
close loop, the reverse saturation current that the voltage across it does not fall be-
flows through both diodes. low 6 V is (a) 1.2 KW (b) 80 W, (c) 50 W,
(d) 0 W
F V2
VT
I F V2
VT
I
Io = I G exp - 1J , 1 = G exp JJK
-1 Solution:
o
GH JK GH 10 - 6 4
IS = = = 80 mA
V2 = VT ln 2 = 25 mV ¥ 0.693 = 17.33 mV 50 W 50 W
= 0.01733 V The maximum load current = 80 5
Voltage drop across diode = 75 mA
D1 = 5 0.01733 = 4.983 V 6
Hence, minimum load resistance =
12. A Zener diode in the circuit of Fig. 3.26 75 mA
has a knee currents of 5 mA and a maxi- = 80 W
mum allowed power dissipation of
300mW. What are the minimum and maxi-
mum load currents that can be drawn
safely from the circuit, keeping the
output voltage Vo constant at 6 V ? Choose
the correct option (a) 0 mA, 180 mA
Figure 3.27
124
14. Draw the transfer curve of the circuit of VI - Vo V - 1 Vo

Fig. 3.28(a), assuming both diodes D1 and (ii) For rd1 = 10 W, = o +
1K 10 W RL
D2 to be ideal. How would the curve
change if D1 is ideal and D2 is non-ideal in VI Vo V V 1
which it has forward resistance of 10 W = + o + o -
1K 0.010 K 1 K 1 K 0.010 K
and a reverse resistance of infinity?
100Vo + 2Vo 100 102Vo 100
Solution: = - = -
(i) For 2 V < V1 < 1 V, neither diode D1 1K 1K 1K 1K
nor diode D2 are conducting. In such Vi = 102Vo 100
case,
VI + 100 VI + 100
Ê 1Kˆ Vo = @ = 1 +0.01VI
Vo = Á VI = 0.5 VI 102 100
Ë 2 K ˜¯ Now, the slope of the curve after 1 V =
VI - 2 2 0.01
For VI < 2V, Vo = 2V, = 15. In the circuit of Fig. 3.29, the current ID
1K 1K
through the ideal diode (zero cut-in voltage
and hence VI = 4 V, Vo = 2 V, and forward resistance) equals(a) 0 A,
(b) 4 A, (c) 1 A, (d) 10 A.
Figure 3.29
Solution:
Applying superposition theorem, from
Figure 3.28 Fig. 3.29(b),
125
10 FI
4 10 4 FI 10 17. Obtain the values of V and I in each case
ID = = = A
4+
HK
4 5 24 5 HK 6 of Fig. 3.31 (a e), assuming the drop
5 5 across the diode of 0.7 V.
2A ¥ 1 4 Solution:
From Fig. 3.29(c), ID = = A
3 6 (a) V = 5 V, I = 0,
10 4
Hence, net diode current = A- A = 4.3 + 5
6 6 (b) V = 4.3 V, I = = 1.86 mA,
1 A. Option c is correct. 5K
16. Obtain the value of V and I in each case of 1.8
Figs. 3.30 (a f), assuming the drop (c) V = 2.5 0.7 = 1.8 V, I =
10 K
across the diode of 0.7 V.
= 0.8 mA
(d) V = 2.5 V, I = 0,
(e) V = 0.7 V, I = 0.
Figure 3.30
Solution:
(a) Diode reverse biased I = 0, V = 5 V
- 5 + 0.7 - 4.3
(b) I = = = 0.86 mA,
5K 5K
V = 0.7 V
(c) I = 0, V = 5 V
5 - 0.7
(d) I = = 0.86 mA, V = 0.7 V
5K
(e) I = 0, V = 0 V
5 - 0.7
(f) I = = 0.86 mA, V = 5 K ¥
5K
0.86 = 4.3 V Figure 3.31
126
18. Obtain the values of V and I in Fig. 3.32, other two not to appear through diodes D1
assuming the drop across the diode of and D2. Hence, V = 2.3 V and I = 2.3 mA.
0.7 V. 19. Obtain the values of V and I in Fig. 3.33,
assuming the drop across the diode of
0.7 V.
2.3 - ( - 5) 7.3V
V = 2.3V, I =
1K
= 7.3mA,
Figure 3.32
Solution:
Three voltages (2.3 V, 1.3 V, and 0.3 V)
try to appear at the point V, but at a node
no more than one voltage can appear.
Hence, one voltage will appear forcing the
Figure 3.33
127
20. Obtain the values of V and I in Fig. 3.34, and D2. Thus, V = 1.7 V that will reverse
assuming the drop across the diode of 5 - 1.7
0.7 V. bias diodes D2 and D3 and I = =
1K
3.3 mA.
21. Obtain the values of V and I in Fig. 3.35,
0.7 V.
Solution:
5 + 1.3
V = 1.3 V, I = = 6.3 mA
1K
Figure 3.34
Solution:
Three voltages (3.7 V, 2.7 V, and 1.7 V) try
to appear at the point V, but at a node no
more than one voltage can appear. Hence,
one voltage will appear forcing the other
two not to appear through the diodes D3 Figure 3.35
128
22. Obtain the values of V and I in Fig. 3.36 23. Obtain the values of V and I in Fig. 3.37,
assuming the drop across the diode of assuming the drop across the diode of
0.7 V. 0.7 V.
Solution:
If the diode D1 conducts, the current I
must flow from plate to cathode as indi-
cated.
Hence,
5 - 0.7 5 + 0.7 - 0.7

I = - = 1.72 1 =
2.5 K 5K
0.72 mA. It means D1 conducts. Hence, V
= 0.7 0.7 = 0 V.
Figure 3.36
Solution:
5 - 1.4 3.6
(a) V = 1.4 V, I = =
5K 5K
= 0.72 mA,
(b) V = 0 V, I = 0,
(c) V = 0 V, I = 0,
Figure 3.37
5 - 1.4 3.6
(d) V = 0.7 V, I = =
5K 5K 24. Obtain the values of V and I in Fig. 3.38(a),
= 0.72 mA, assuming the drop across the diode of
0.7 V.
5 - 0.7 4.3
(e) V = 0.7 V, = = 0.43 mA
2 ¥ 5 K 10 K
129
Solution:
If the diode D1 conducts, the current I
must flow from plate to cathode as indi-
cated.
5 - 0.7 5 + 0.7 - 0.7
Hence, I = -
5K 2.5 K
= 0.86 1 = 0.14 mA.
Figure 3.38 Figure 3.39
It means D1 does not conduct. Hence,

2.3 - ( -5) 7.3
V = 2.3 V, I = = = 3.3 mA
(10 - 0.7) ¥ 2.5 1K 1K
V = -5+
7.5 K
26. Obtain the values of V and I in Fig. 3.40,
9.3 ¥ 2.5 0.7 V.
= -5+ = 1.9 V
7.5 K
Solution:
25. Obtain the values of V and I in Fig. 3.39, 5 - 1.7 3.3
assuming the drop across the diode of V = 1.7 V, I = = = 3.3 mA
1K 1K
0.7 V.
130
27. Obtain the value of V assuming ideal diode Solution:

in Fig. 3.41(a). 10 10
Solution: I= - = 0.125 mA, V = 0 V
40 K 80 K
V = 0V
Figure 3.41(a)
Figure 3.41(b)
Figure 3.40 29. Figure 3.42 is the circuit of a magnitude
28. Obtain the values of V and I assuming ideal limiter. Draw its output waveform for the
diode in Fig. 3.41(b). sinusoidal input voltage shown.
Figure 3.42
131
30. Draw and explain the circuit of a diode

clamper where the output voltage is
clamped to zero volt.
31. All diodes in Fig. 3.43 are ideal. Plot the
piece-wise output wave shape indicating
each region and corresponding diodes
condition in those regions.
Figure 3.43(d)
Vi - VO V -6
I1 = , I1 I2 = O ,
2.5 5
V V - VO VO VO - 6
I2 = O , i =
5 2.5 5 5
or, 2Vi 2VO VO = VO 6 6,
Figure 3.43(a) 4VO = 2Vi + 6, For Vi = 9 V, VO = 6 V
Case III: When Vi > 9 V, D1 = ON, D2 =
OFF, D3 = OFF, Fig. 3.43(a) reduces to
Fig. 3.43(d).
Vi ¥ 5
VO = ,
7.5
for Vi = 15 V,
Figure 3.43(b) 15 ¥ 5
VO = = 10 V
Case I: When Vi < 6 V, D1 = OFF, D2 = 7.5
ON, D3 = OFF and hence circuit reduces Case III: when Vi > 20 V, D1 = ON, D2 =
to Fig. 3.43(b). OFF, D3 = On, Fig. 3.43(a) reduces to Fig.
3.43(e).
6V ¥5
VO = = 3 V, thus
10
VO = 3 V for Vi = 6 V.
Case II: When Vi > 6 V, D1 = ON, D2 =
ON, D3 = OFF and hence circuit reduces
to Fig. 3.43(c).
Figure 3.43 (e)
Vi - VO V - 20
I1 = , I1 I2 = O ,
2.5 10
V V - VO VO V - 20
I2 = O , i = O
Figure 3.43(c) 5 2.5 5 10
132
or, 4Vi 4VO 2VO = VO 20 For Vi = 30 V,

or, 7VO = 4Vi + 20 VO = (4 ¥ 30 + 20)/7 = 20 V
Figure 3.43(f)
32. Draw the circuit of a reverse biased diode clamper and draw its output waveform w.r.t. the
input waveform shown in Fig. 3.44(a).
Figure 3.44 Positive biased clamper
33. Draw the output waveform for a sinusoidal input to Fig. 3.45.
Figure 3.45
133
34. The input to a two level clipper shown in Fig.

3.46 increases linearly up to 150 V. Sketch
output voltage VO to the same time scale as
the input voltage. Assuming all diodes ideal.
Figure 3.46(b)
Figure 3.46(a)
Case I: 25 V ≥ Vi ≥ 0 V, diode D1 Case IV: Vi > 100 V diode D1 = ON,

= OFF, D2 = ON, Fig. 3.46 (a) reduces D2 = OFF. Hence, VO = 100 V.
to Fig. 3.46 (b)
100 - 25
VO = 100 - 200
300
75
= 100 - 200 = 50 V (D1 will be OFF
300
till Vi > 25 V)
Case II: Vi up to 50 V, diode D1 = OFF,
D2 = ON. Hence VO = 50 V for Vi = 50 V.
Up to Vi =50 V, diode D1 = OFF, D2 = ON.
Hence VO = 50 V for Vi = 50 V, up to Vi 50
V, diode D1 = off, D2 = ON. 35. Why is the clamper called dc inseter?
Case III: 50 V < Vi <, 100 V diode D1 = The input voltage of a clamper is clamped
ON, D2 = ON. Hence, VO = Vi a dc value which is equivalent to inserting
a dc voltage.
Multiple Choice Questions (c) PIN diode

(d) power diode
1. The PIN diode is used as 3. Most suitable diode for a phase shifter is
(a) rectifier (a) power diode
(b) voltage controlled attenuator (b) avalanche diode
(c) amplifier (c) PIN diode
2. The diode used for a power limitter is 4. The PIN diode is used as
(a) signal diode (a) square wave modulator
(b) Zener diode (b) triangular wave modulator
(c) sine wave modulator
134
5. No moving part is associated with the 14. The PIN diode works as rectifier at
change in capacitance of (a) low frequency
(a) gang capacitor (b) high frequency
(b) trimmer (c) all frequencies
(c) varicap 15. The PIN diode has
6. The diode which permits remote tuning, is (a) an intrinsic layer between heavily
(a) power diode doped p and n-layers
(b) varactor (b) an n-layer between heavily doped p
(c) Zener diode and n-layers
7. The Zener effect is valid (c) and an p-layer between heavily doped
(a) below 5 V p and n-layers
(b) above 5 V 16. The Schottky diode turns OFF
(c) equal to 5 V (a) faster w.r.t p-n junction
(d) none of the above (b) slower w.r.t. p-n junction
8. The avalanche effect is valid (c) at the same speed as p-n junction
(a) below 5 V 17. The minority carrier storage time in the
(b) above 5 V Schottky diode is
(c) equal to 5 V (a) infinite (b) zero
(d) none of these (c) 0.15 ms
9. The electron-hole pairs are generated in 18. Very close to the ideal diode is
(a) Zener mechanism (a) Zener diode
(b) avalanche mechanism (b) signal diode
(c) none of the two (c) Schottky diode
10. The diode which is preferred for dc cou- 19. The function of diode D1 in Fig. 3.47 is to
pling is (a) allow full-wave current to flow
(a) signal diode through the galvanometer G
(b) power diode (b) allow source current to flow during
(c) LED negative half cycle of Vs
(d) Zener diode (c) avoid excess voltage appearing across
11. Power diodes are used in diode D2
(a) rectifier (d) none of these
(b) amplifier
(c) mixer
12. The power diodes are made of
(a) silicon
(b) germanium
(c) aluminium
13. Signal diodes are called
Figure 3.47
(a) general-purpose diodes
(b) special purpose diodes 20. The states of the diodes D1 and D2 in Fig.
(c) high power diodes 3.48 under extremely high negative Vs >>
V is
135
(a) both D1 and D2 OFF

(b) D1 OFF and D2 ON
(c) both D1 and D2 ON
(d) D1 ON and D2 OFF
Figure 3.48

1. (b) 2. (c) 3. (a) 4. (d) 5. (c) 6. (b)
7. (a) 8. (b) 9. (b) 10. (d) 11. (a) 12. (a)
13. (a) 14. (a) 15. (a) 16. (a) 17. (b) 18. (c)
19. (b) 20. (d)
4
Junction Diode Rectifier
4.1 Introduction
All electronic devices require external dc voltage to bring them from inactive state to active state. The ac
voltage available in India is 230 V, 50 Hz. Hence, the dc is obtained from this 230 V ac by converting the
ac to dc. The process of conversion from ac to dc is called rectification and the circuit that converts it
is known as rectifier. The rectifier family is shown in Fig. 4.1.
Figure 4.1 Rectifier family
4.2 Half-wave Rectifier

A circuit of half-wave rectifier is depicted in Fig. 4.2. A diode conducts only when the plate is positive
w.r.t. the cathode. The plate in Fig. 4.2 will become positive w.r.t. the cathode only in the positive half
!%
cycle of the input voltage Vi connected across its input terminals 1-1¢. The different types of waveforms
available at various points of the half-wave rectifier have been drawn in Fig. 4.3.
Figure 4.2 Half-wave rectifier
As the desired dc voltages for electronic devices are much lower, i.e. +4.5 V, +5 V, +6 V, +9 V, +12 V,
+22.5 V, +30 V etc. accordingly the input voltage to the rectifier input should be much less than
230 V ac. Hence, a step down power transformer is used to fabricate a more practical circuit of half-
wave rectifier as drawn in Fig. 4.2.
The output voltage and current of half-wave rectifier from Fig. 4.3 is not perfect dc but pulsating dc.
The output voltage (current) is present in the alternate half cycle as illustrated in this figure. The output
voltage remains zero till the input voltage does not exceed the depletion voltage. The drop across the
diode is very small in the forward bias region and is approximated as
VI rd
VD = (4.2.1)
rs + rd + RL
Figure 4.3 Wave shapes of half-wave rectifier

!&
Figure 4.4 Equivalent circuit of half-wave rectifier
4.2.1 Analysis
We would like to obtain the dc output voltage, dc output current, R.M.S. output voltage, R.M.S. output
current, Ripple factor, efficiency and regulation of half-wave rectifier.
From Fig. 4.3, Input voltage = VI = Vm sin w t (4.2.2)
Output current = iD= iL= Im sin w t 0 < wt < p (4.2.3)
= 0 0 < w t < 2p (4.2.4)
where Vm = maximum input voltage across the secondary winding
Vm
Im = (4.2.5)
RL + rd + rs
Here, rs = resistance of secondary winding
rd = forward biased resistance of diode
RL = load resistance
Assumption
The cut in voltage has been assumed to be negligible w.r.t. the input voltage VI . This assumption does
not hold good for very small magnitude of the input voltage, i.e. when the input voltage becomes
comparable w.r.t. the cut in voltage. The dc voltage or current is defined as,
area under one complete cycle
Idc = Iav = (4.2.6)
time period of one cycle
1 2p 1 2p 1 Èp 2p ˘
= i
Ú d d (w t ) = I
Ú m sin w td (w t ) = Í I
Ú m sin w td (w t ) + Ú (0)(w t ) ˙ (4.2.7)
2p 0 2p 0 2p ÎÍ 0 p ˚˙
p
1 I p I
or, Idc = I sin w td (w t ) = m [- cos w t ]0 = m (4.2.8)
2p Ú0 m 2p p
Vm
Idc = (4.2.9)
p(rs + rd + RL )
!'
Vdc = IdcRL =
Vm RL V
= m ¥ 1-
FG
rs + rd IJ (4.2.10)
p (rs + rd + RL ) p H
rs + rd + RL K
As rd and rs are few ohms, (rs + rd) << RL and hence Eqn. 4.2.10 reduces to
V
Vdc = m = 0.318Vm (4.2.11)
p
A dc voltmeter measures the average value of a complete cycle of the input voltage waveform.
4.2.2 RMS Current

The rms stands for is "root mean square". In other words, take the root of the mean of the square of the
signal. Hence, it is expressed as
2p 2p p
1 1 2 I m2
Irms = Ú iD2 d (w t ) = Ú ( I m sin w t ) d (w t ) = Ú 2sin 2
w td (w t) (4.2.12)
2p o
2p 0
4p
0
2 p 2 p
Im Im È sin 2w t ˘ I
= Ú (1 - cos 2w t )d (w t ) = Íw t-
˙ = m (4.2.13)
4p 4p Î 2 ˚0 2
0
Vm
Thus, Irms = (4.2.14)
2(rs + rd + RL )
We know that the ac voltage measured across the load is nothing but the rms value of the voltage and
hence the rms value of the load voltage is
Vrms = IrmsRL =
Vm RL V
= m ¥ 1-
FG
rs + rd IJ (4.2.15)
2(rs + rd + RL ) 2 H
rs + rd + RL K
Since (rs + rd) << (rs + rd + RL), Eqn. (4.2.15) reduces to
V
Vrms = m (4.2.16)
2
4.2.3 Ripple Factor

We know that no rectifier converts ac to perfect dc. It produces pulsating dc. Hence, the output dc is
wavy in nature as indicated in Fig. 4.5.
Figure 4.5 Ripple voltage over dc voltage

"
This wave over a perfect dc voltage is similar to the ripples of water in a pond when, wind blows. This
wavy voltage is given the name ripple as it is an unwanted voltage that appears over and above the
desired dc voltage. The ripple factor is a measure of this waviness in the rectifier output. It is expressed
as
ripple voltage rms of ac components vr, rms ir , rms
r= = = = (4.2.17)
dc voltage dc voltage Vdc I dc
As rectified output has both dc and ac (ripple) components, the voltages associated with it can be
expressed as the vector sum to result in the total rms voltage as indicated in Fig. 4.5.
2 2 2 2 2
irms = I dc + iac = I dc + ir(rms) (4.2.18)
or, 2 - I2 1 / 2
ir(rms) = irms (4.2.19)
e dc j
Hence, r=
F irms I 2 - 1 = F p - 1I
2 1/ 2
= (2.47 1)2 = 1.21 (4.2.20)

GH Idc JK GH 4 JK
The unwanted ripple present in the output along with the dc voltage is 121% of the dc magnitude. This
indicates that half-wave rectifier is not an efficient ac to dc converter.
4.2.4 Ratio of Rectification

The ratio of rectification is a measure of conversion of ac input power to dc power. It is expressed as
the ratio of the dc output power to the ac input power, i.e.
dc power delivered to load
h= (4.2.21)
ac power of secondary winding
Pac = total power supplied by secondary winding
2
= Pdiode + Pload = irms 2
rd + irms 2
RL = irms (rd + RL ) =
FG I IJ (r
2
m
d + RL ) (4.2.22)
H 4K
2
2 ÊI ˆ
Pdc = I dc RL = Á m ˜ RL (4.2.23)
Ë p ¯
I m2 RL
/p 2 4 0.46
h= 2 = = (4.2.24)
RL )/ 4 p 2 (1 + rd / RL ) 1 + rd / RL
I m (rd +
It is clear from Eqn. 4.2.24 that even under ideal conditions (diode losses neglected), only 40.6% of the
power conversion is possible from ac to dc.
4.2.5 Regulation
The regulation is a measure of deviation in the nominal value of the output voltage w.r.t. variation in the
load current as indicated in Fig. 4.6. It is defined as the ratio of variation in the output voltage under
variation of load current to the full load voltage, i.e. open circuit voltage.
"
Figure 4.6 Regulation due to load current
The regulation is expressed from Fig. 4.6 as

Vdc(no load) - Vdc(full load)
Regulation = (4.2.25)
Vdc ( full load)
Vm RL V rs + rd V
Vdc = IdcRL = = m (1 - ) = m - I dc (rs + rd ) (4.2.26)
p (rs + rd + RL ) p rs + rd + RL p
V
Vdc(no load) = m for no load Idc = 0 (4.2.27)
p
Vm R
Vdc(full load) = L = IdcRL (4.2.28)
p ( rs + rd + RL )
V
Vdc(no load) Vdc (full lodad) = m
F r +r I
d s
(4.2.29)
p
GH r + r + R JK
s d L
Vm ( rs + rd ) / p ( rs + rd + RL ) rs + rd r
% Regulation = = @ d ¥ 100 (4.2.30)
Vm RL / p ( rs + rd + RL ) RL RL
Example 1
A diode with its dynamic resistance of 1 W is connected in a half-wave rectifier with a trans-
former whose secondary voltage is 12 V, 60 Hz and 2 W resistance. What (a) are the peak, rms
and dc output voltages of the rectifier at no load? (b) is the dc output voltage when it draws full
load current of 100 mA? (c) is the % regulation of this power supplies, and (d) is the internal
resistance of the power supplies?
Solution:
Vm 16.97
(a) Vrms = 12 V, Vm = 12 2 V = 16.97 V and Vdc = = = 5.4 V
p p
Vm
(b) Vdc = Idc (rs + rd) = 5.4 100 × 103 × 3 = 5.1 V
p
5.4 - 51
.
(c) % regulation = = 5.8 %
5.1
(d) internal resistance = rs + rd = 3 W
"
Example 2
Show that the maximum transfer of power take place for rd = RL.
22 2 2
Ê 2I ˆ Ê 2 ˆ Ê Vm ˆ Ê 2V ˆ RL
PDC = I2DC RL = Á m ˜ RL = Á ˜ Á ˜ RL = Á m ˜
Ë p ¯ Ë p ¯ Ë rd + RL ¯ Ë p ¯ ( rd + RL ) 2
2 2 2 2 2
dPDC Ê 2Vm ˆ RL Ê 2Vm ˆ ( rd + RL ) - 2( rd + RL ) RL Ê 2Vm ˆ rd - rd RL
=Á = = =0
dRL Ë p ˜¯ (rd + RL )2 ÁË p ˜¯ (rd + RL )4
ÁË p ˜¯
(rd - RL ) 4
Hence, rd = RL.
4.3 Full-wave Rectifier

The disadvantages of very low dc voltage,
rectification efficiency and poor regulation
of half-wave rectifier can be overcome
using two-diode circuit shown in Fig. 4.7.
Its waveforms are shown in Fig. 4.8.
Figure 4.7 Two diode full-wave rectifier
Figure 4.8 Wave shapes of full-wave rectifier

"!
Input voltage = VI = Vm sin w t (4.3.1)

Output current iD = i L (4.3.2)
iD1 = iL = Im sin wt 0 < wt < p (4.3.3)
iD2 = iL = Im sin wt p < wt < 2p (4.3.4)
where, Vm = maximum value of voltage across the secondary
Vm
Im = (4.3.5)
rs + rd + RL
The dc voltage or current for full-wave rectifier is obtained as those obtained for half-wave rectifier.
Using Eqn. 4.2.7
1 2p 1 2p 2 p Im p
Idc = Ú iD d (w t ) = Ú I m sin w td (w t ) = Ú I m sin w t d (w t ) = Ú sin w t d (w t ) (4.3.6)
2p 0 2p 0 2p 0 p 0
Im p 2I
Idc = [ - cos w t ]0 = m (4.3.7)
p p
Ê 2ˆ Ê Vm ˆ
Hence, Idc = Á ˜ Á (4.3.8)
Ë p ¯ Ë rs + rd + RL ˜¯
Ê 2 ˆ Ê Vm RL ˆ Ê 2Vm ˆ Ê rs + r f ˆ
Vdc = IdcRL = Á ˜ Á = Á ˜ 1 - (4.3.9)
Ë p ¯ Ë rs + rd + RL ˜¯ Ë p ¯ Ë rs + rd + RL ˜¯
Á
As rd and rs are few ohms, (rs + rd) << (rs + rd + RL),
Hence, Vdc=
2Vm
= 0.636Vm =
FG 2 2 IJ V rms (4.3.10)
p HpK
4.3.1 RMS Value
The rms value of current in a full-wave rectifier is obtained using Eqn. 4.2.12
p 2p p p
1
irms=
1
2p z
0
iD2 d (w t ) +
2p
1
z
p
2
iD d (w t ) =
2
2p z
0
2
iD d (w t ) =
2p
0
zb 2
g
2 Im sin w t d (w t ) (4.3.11)
I m2 p I m2 È sin 2w t ˘p I m 2irms
= Ú (1 - cos 2w t) d (w t) = Íw t - ˙ = = = irms (4.3.12)
2p 0 2p Î 2 ˚0 2 2
Vm
Thus, irms = (4.3.13)
2(rs + rd + RL )
""
The ac voltage measured across the load is nothing but the rms value of the voltage and hence, the rms
value of the load voltage is
vrms = irms RL =
Vm RL V
= m 1-
FG
rs + rd IJ (4.3.14)
2 (rs + rd + RL ) 2 H
rs + rd + RL K
Since (rs + rd) << (rs + rd + RL), Eqn. 4.3.14 reduces to
Vm 2vrms pVdc V
vrms = = = = dc = 1.11Vdc (4.3.15)
2 2 2 2 0.9
4.3.2 Ripple Factor

The ripple factor in a full-wave rectifier is obtained using Eqn. 4.2.17. Since rectified output has both dc
and ac (ripple) components, the voltages associated with it can be expressed as the vector sum to result
in the total rms voltage as
2 2 2
2
irms = I dc + iac = I dc + ir2(rms) (4.3.16)
1/ 2
(
2
ir(rms) = irms 2
- I dc ) (4.3.17)
1/ 2 1/ 2
Hence,
Fi
r= G
2
rms I
- 1J
F p - 1IJ
=G
2
@ 0.48 (4.3.18)
HI 2
dc K H8 K
Thus, the unwanted ripple present in the output along with the dc voltage is only 48% of the dc output.
This indicates that full-wave rectifier is a more efficient ac to dc converter than the half-wave rectifier.
4.3.3 Ratio of Rectification

The ratio of ac input power to dc output power in a full-wave rectifier is obtained using Eqn. 4.2.25 as
I m2
Pac = ( rd + RL ) (4.3.19)
2
2 4 Im2
Pdc = I dc RL = RL (4.3.20)
p2
4 Im2 RL / p 2 8 0.812
h= 2 = 2 = (4.3.21)
I m (rd + RL )/ 2 p (1 + rd / RL ) 1 + rd / RL
Equation 4.3.21 reveals that under ideal conditions the rectification efficiency is only 81.2%.
4.3.4 Regulation
The regulation is the property of the rectifier to hold its dc output voltage constant w.r.t. variation in the
load current. Hence, for a full-wave rectifier it is expressed from Fig. 4.6 as
"#
Vdc(no load) - Vdc(full load)

Regulation = (4.3.22)
Vdc(full load)
2Vm
Vdc = for no load means Idc= 0 (4.3.23)
p
2Vm
Vdc (full load) = = IdcRL (4.3.24)
p(rs + rd + RL )
2Vm (rs + rd )
Vdc (no load) Vdc(full load) = (4.3.25)
p (rs + rd + RL )
Vm ( rs + rd ) / p ( rs + rd + RL ) rs + rd r
% Regulation = = @ d ¥ 100% (4.3.26)
Vm RL / p ( rs + rd + RL ) RL RL
Eqn. 4.3.26 indicates that the regulation is the same to that of the half-wave rectifier derived in
Eqn. 4.2.32.
4.3.5 Peak Inverse Voltage (PIV)

The voltage across the diode during non-conduction period is called the reverse bias voltage or the peak
inverse voltage. The diode D1 in Fig. 4.9 conducts, whereas diode D2 does not conduct in the positive
half cycle. Hence, the open circuit voltage appearing across the diode D2 would be equated by writing
the loop equation from centre tap point of the transformer through the diode D2 to the ground point of
the load resistance RL.
Figure 4.9 PIV in two diodes full-wave rectifier
As the centre tap of the transformer secondary is also connected to the ground, the loop closes and
hence
Vm VD + Vm = 0 (4.3.27)
or, VD = 2Vm (4.3.28)
Exercise
Prove that the percentage regulation in both half-wave and full-wave rectifier is the same.
"$
4.4 Bridge Rectifier

The main disadvantage of two-diodes full-wave rectifier lies in the construction of centre tapped trans-
former. The price of the centre tapped transformer becomes prohibitively high. This can be avoided by
using the bridge configuration as shown in Fig. 4.10.
Figure 4.10 Bridge rectifier
Diodes D1 and D3 conduct in the positive half-cycle as shown in Fig. 4.11. Diodes D2 and D4 conduct
in the negative half-cycle as indicated in Fig. 4.12. The bridge rectifier works similar to the two-diode
full-wave rectifier.
In bridge rectifier two diodes work in series hence, the PIV of each diode becomes half, i.e. only Vm.
The power output rating of the transformer required here for this case must be at least 4% higher than
that used as centre tapped one.
Figure 4.11. Bridge rectifier in positive half-cycle
Figure 4.12 Bridge rectifier in negative half-cycle
All equations derived for two-diode full-wave rectifier are valid for the bridge rectifier.
"%
4.5 Transformer Utilization Factor

The power supplied by the transformer must be arranged in terms of the dc power, i.e. VdcIdc= Pdc for
obtaining the transformer utilization factor. It is defined as the ratio of dc output power to ac power
supplied to it by the secondary winding and is expressed as
Pdc
TUF = (4.5.1)
Pac(rated)
As the rating of the transformer is different than the actual power delivered by the secondary, the TUF
is entirely a different quantity than the efficiency.
4.5.1 TUF for one Diode Half-wave Rectifier
The rated voltage of the secondary is Vm / 2 , but the actual rms value of current flowing through the
secondary winding is I m / 2 and not Im / 2.
2
FI I Rm
TUF =
HpK L
(4.5.2)
FG V IJ F I I
m m
H 2KH 2 K
F 2 2 I F R IJ
TUF = G 2 J G L as Vm = Im(rd + RL), (4.5.3)
H p K H R + rd K L
TUF = 2 2 / p 2 = 0.287 also RL>> rd, (4.5.4)

The dc power delivered to a resistive load without over heating would be = 0.287 × 1 KVA = 287 W, if
a 1 KVA transformer is used in the half-wave rectifier circuit. The dc current flowing through the
transformer secondary causes the saturation effect.
4.5.2 TUF for a Bridge Rectifier
Pdc (2I m / p ) 2 RL 8 I m ( I m RL ) 8 I mVm 8

TUF = = = 2
= 2
= 2 = 0.812 (4.5.5)
Pac(rated) (Vm / 2)( I m / 2) p I mVm p I mVm p
Hence, TUF for a bridge rectifier = 0.812.
4.5.3 TUF for Two-diode Full-wave Rectifier

The two-diode full-wave rectifier can be thought of as equivalent to two half-wave rectifiers feeding to
a common load. Hence, TUF w.r.t. two half secondary can be written as
TUF(full secondary) = 2 × TUF(half-wave) = 2 × 0.287= 0.574 (4.5.6)
We know that the dc current in two halves of the secondary cancel out for obtaining the TUF of
primary. Hence,
"&
(2I m / p )2 RL 8 I m ( I m RL ) 8 I m2 RL
TUF(primary) = = ¥ = ¥
(Vm / 2)( I m / 2) p 2 I m * I m (rs + rd + RL ) p 2 I m2 (rs + rd + RL )
RL
= (0.812) @ 0.812 (as RL >> rs + rd) (4.5.7)
rs + rd + RL
TUFprimary + TUFsecondary 0.574 + 0.812
Average TUF = = = 0.693 (4.5.8)
2 2
Table 4.1 Comparison of rectifiers
Half-wave Full-wave Bridge

DC current Im /p 2Im /p 2Im /p
DC voltage Vm /p 2Vm /p 2Vm /p
RMS current Im /2 Im / 2 Im / 2
RMS voltage Vm /2 Vm / 2 Vm / 2
Ripple voltage 1.21 0.48 0.48
Efficiency 40.6% 81.2% 81.2%
PIV Vm 2Vm Vm
TUF 0.287 0.693 0.812
4.5.4 Advantages of Bridge Rectifier

∑ No centre tap transformer required.
∑ Suitable for high voltage rectification.
∑ PIV = Vm as two-diodes are in series.
∑ Small transformer used as currents in primary and secondary flow for the whole cycle.
Example
1. Determine the rating of transformer to deliver 100 W of dc power to a load for (a) half-wave
rectifier, (b) full-wave rectifier, (c) bridge rectifier and (d) three phase full-wave rectifier
Solution
Pdc
(a) TUF for a half-wave rectifier = 0.287 =
Pac( rated )
100
Pac(rated) = = 348.43 VA @ 348 VA
0.287
100
(b) TUF for full-wave rectifier = 0.693, Pac(rated) = = 144.3 VA = 144 VA
0.693
"'
100
(c) TUF for a bridge rectifier = 0.812, Pac(rated) = = 123 VA
0.812
(d) TUF for a three phase full-wave rectifier = 0.955,
100
Pac(rated) = = 104.7 VA= 105 VA
0.953
4.6 Passive Filter

We know that the output voltage of both half-wave and full-wave rectifiers is pulsating and not pure dc.
An ac component of voltage in the form of ripple overrides the dc output voltage. This ripple voltage
disturbs the working of the equipment wherever the ac to dc converter in the form of either half-wave
or full-wave is used. This disturbance of ripple voltage can be avoided if it is filtered out. Many types of
passive filters are available:
∑ RC filter
∑ RL filter
∑ LC filter and
∑ p filter
4.6.1 RC Filter
The output voltage of a full-wave rectifier is expressed in form of Fourier series as
2Vm 4Vm 4V
v= - cos 2w t - m cos 4w t + . . . . . . . (4.6.1)
p 3p 15p
Equation 4.6.1 reveals that the dc contains ac components in the form of harmonics. The magnitude of
the ac component goes on decreasing for increasing value of harmonics. The magnitude of ripple (ac)
voltage of second harmonics is much larger than that of the fourth harmonics. The second harmonic
component voltage present as the second term in Eqn. 4.6.1 disturbs the dc component voltage present
as the first term, which should be filtered out effectively. The simplest circuit for effective filtering of
the second harmonics is implemented by shunting the load with a large capacitor as shown in Fig. 4.13.
The lowest harmonics present in the output of the full-wave rectifier can be filtered only when the
capacitive reactance is much less than the load resistance, i.e. XC << RL. If this condition is not satisfied,
the wave shape becomes that of a differentiator.
Figure 4.13 Two-diodes full-wave rectifier with C-filter

#
During conduction, the supply of current to the capacitor and load is expressed as
dVC VC
iD1 = iD2 = iC + iRL = C+ (4.6.2)
dt RL
If the diode drop is neglected, then the voltage VC is simply the voltage across the secondary winding of
the transformer. Hence,
VC = Vm sinwt (4.6.3)
During the conduction period the capacitor is charged to the peak value of the voltage Vm. Thereby
energy is stored in the shunt capacitor as in Fig. 4.13. The capacitor delivers energy to the load during
the time the input voltage is less than that of the capacitor voltage shown in Fig. 4.14. For large value of
C, i.e. RLC >> 1, wt1 = p/2 and vo = Vm at t = t1. Also, for large value of C, the exponential decay can
be represented by linear fall. Hence, if the total discharge voltage (ripple voltage) is vr, then the average
value of voltage is approximated as
vr
Vdc = Vm - (4.6.4)
2
The charging and discharging curves seem approximately identical to the sawtooth waveform. As the
capacitor starts discharging from its peak value, the next output voltage waveform starts increasing. As
soon as its voltage magnitude becomes larger than the voltage existing on the capacitor, it starts charging
again. The better filtering action dictates that the conduction time T1 should be the smallest and the
discharge time T2 should approach closest to the half-period time of the input voltage. Hence, under
such condition we can assume that T2 = T/2 = 1 /2f where f is the frequency of the input voltage. Thus,
the half-cycle of the sawtooth waveform is T/2 as shown in Fig. 4.15. The sawtooth waveform is
idealized as in Fig. 4.16.
Since the shape of the Fig. 4.15 is approximated as the perfect sawtooth wave, its shape is identical in
the duration 0 to T/4 and T/4 to T/2. The rms value in the duration 0 to T/2 will be equal to twice the rms
value in the duration from 0 to T/4. The sawtooth waveform is represented as f (t) =
vr ( pp)/ 2 FG
t . Hence,
IJ
T /4 H K
it is written as
2
1
T/4 2
{vr ( pp) / 2} 2 evr( pp) / 2j aT 4f3 = vr( pp)
Ripple voltage = vr(rms) =
(T / 4 ) z0 a f
T /4
2
t dt =
3aT 4f
3 2 3
(4.6.5)
where, f = 1/T (4.6.6)
Figure 4.14 Charge-discharge of capacitor

#
Figure 4.15 Ripple voltage
Figure 4.16 Ideal charge discharge curve
Assuming that the average load current is equal to the average discharge current during T/2 interval. The
charge lost by the capacitor is expressed as
ÊT ˆ
Qlost = I dc Á ˜ (4.6.7)
Ë 2¯
This lost charge is replaced in short duration wT1. In this duration the voltage across the capacitor C
changes by peak to peak value of the ripple voltage vr(pp) (sawtooth voltage).
Qcharged = vr(pp)C (4.6.8)
Qlost = Qcharged (4.6.9)
vr(pp) =
F I I T = F I I F T I = FG I IJ
dc dc dc
(4.6.10)
H C K H C K H 2 K H 2 fC K
2
Combining Eqns. 4.6.6 and 4.6.10 results in

Idc
vr(rms) = (4.6.11)
4 3 fC
Vdc
Idc= (4.6.12)
RL
Now combining Eqns. 4.6.11 and 4.6.12 yields
Vdc
vr(rms) = (4.6.13)
4 3 fCRL
Hence, ripple factor is defined as
vr (rms) 1
r= = (4.6.14)
Vdc 4 3 fCRL
#
2887
For f = 50 Hz, r = (4.6.15)
CRL
Here, C is in mF.
Equation 4.6.15 indicates that for higher load resistance RL, i.e. low load, the ripple factor is less. The
average dc value from Fig. 4.15 is written as
vr ( pp)
Vav = Vdc = Vm - (4.6.16)
2
I dc
Vav = Vdc = Vm (4.6.17)
4 fC
Vdc
Vav = Vdc = Vm (4.6.18)
4 fCRL
Vm 4 fCRL
Thus, Vdc = (4.6.19)
1 + 4 fCRL
4.6.2 Choke Input Filter

The working of the choke input filter is based on the inherent property of the inductor that opposes any
change in current that intends to take place. Thus, inductor stores energy in its magnetic field when the
current is above its average value and releases the field when the current is below this value. Consequently
the sudden change in the current that might otherwise take place in the circuit is smoothened out by the
choke. The inductor filter is shown in Fig. 4.17.
The output voltage of a full wave rectifier is expressed as
2Vm 4Vm 4V
v=
- cos 2w t - m cos 4w t (4.6.20)
p 3p 15p
Equation 4.6.20 contains dc voltage 2Vm/p and the dominant ac voltage (ripple) of second harmonics
(4Vm/3p) cos 2 wt.
Figure 4.17 Full-wave rectifier with inductor input filter

#!
4Vm
The maximum ac (ripple) current passing through the load = Imax= (4.6.21)
3pZ
4V R
The maximum ac (ripple) voltage present across the load = Vmax= m L (4.6.22)
3pZ
Vmax 4Vm RL
The rms of ripple voltage present across the load = vr(rms) = =
2 3 2pZ
2Vm 2 RL 2
= ¥ = Vdc ¥ (4.6.23)
2 2 2
p 3 2 RL + 4w L 3 2 1 + 4w 2 L2 / RL2
The dotted wave shape in Fig. 4.18 indicates that the current through the inductor has been delayed due
to its property of opposing the change in the current. The impedance of the circuit at the frequency of
interest, i.e. second harmonics is
Z = [ RL2 + (2w L)2 ]1/ 2
Figure 4.18. Inductor input filter effect on iL
vr (rms) Vdc 2
Ripple factor is now expressed as r = = ¥
Vdc Vdc 3 2 1 + 4w 2 L2 / RL2
2
= (4.6.24)
3 2 1 + 4w 2 L2 / RL2
Since reactance of the inductor (choke) is quite high,
4w 2 L2 / RL2 >> 1
Hence, the ripple factor is
r=
FG 1 IJ F 2 R I = FG 1 IJ FG R IJ = FG 1 IJ F R I
L L L
(4.6.25)
H 3 2 K H 2wL K H 3 2 K H 2pfL K H 6pf 2 K H L K
RL 75RL
For f = 50 Hz, r = = (L in mH and RL in W) (4.6.26)
1333 L L
Equation 4.6.26 reveals that the ripple factor is directly proportional to the load resistance RL and
inversely proportional to the inductor value. Hence, inductor input filter is useful for small value of load
resistance, i.e. for heavy load.
#"
2Vm
The dc voltage Vdc = (4.6.27)
p
rc = resistance of the choke
Total series resistance across its output = R = rs + rd + rc (4.6.28)
Then output voltage = Vdc = F 2V I R m L

(4.6.29)
H p K R+ R L
=
F 2Vm I FG R + R - R IJ = F 2Vm I FG1 - R IJ = 2Vm - Idc R
L
(4.6.30)
H p KH R + R K H p KH R + R K p
L L
2Vm
Idc = (4.6.31)
p ( R + RL )
The output voltage from Eqn. 4.6.31 for high value of R = rs + rd + rc will become very low resulting in
poor regulation. As series resistance is kept small, the output voltage never becomes very low. Eqn.
4.6.15 reveals that the ripple factor is low for high value of load resistance. On the contrary Eqn. 4.6.26
suggests that the ripple factor is high for high value of load resistance. Hence, it is expected that the
combination of the two might work well. Figure 4.18 shows the plot in the variation of dc output voltage
with load current.
We know that inclusion of an inductance in the LC filter does allow the current to cease to zero
theoretically. Practically it does happen that with insufficient value of inductance, the current gets cut-
out. Hence, a minimum value of inductance is required to prevent the current to go to cut out. This
minimum value is called critical inductance. Also we know that the current consists of two components
V
1. dc component = IDC = DC and
RL
4Vm
2. peak value of ac component =
3p X L
V 4Vm 2(2Vm / p ) 2 VDC
For continuous current flow due to 2nd harmonics, DC ≥ = =
RL 3p X L 3X L 3X L
2RL 2 RL R RL RL RL
or, 1≥ = = L = = =
3X L 3 ¥ 2w L 3w L 3 ¥ 2p ¥ 50 L 300p L 942.5L
RL
or, L=
942.5
Normally critical inductance should be 25% more than this value, and hence
RL
Hence, L=
700
##
4.6.3 L-section Filter

Fourier series of full-wave rectified output is
2Vm 4Vm 4V
v= - cos 2w t - m cos 4w t . . . . (4.6.32)
p 3p 15p
Equation 4.6.32 contains dc voltage 2Vm/p and the dominant ac voltage (ripple) of second harmonics
(4Vm/3p) cos 2 wt.
The circuit of a full-wave rectifier with L-section of filter is drawn in Fig. 4.19. In order to suppress the
dominant frequency harmonics (second harmonics) component of ripple voltage from the load, a large
value of inductor must be connected w.r.t. the parallel combination impedance of the capacitor and the
load resistance. Thus, we can assume that the entire ac ripple due to second harmonics is dropped
across the inductor.
4Vm
The maximum ac (ripple) voltage across the load = v(r)max = (4.6.33)
3p
4Vm
The maximum ac (ripple) current of second harmonics through the inductor = ir(max) =
3pX L
ir (max) 4Vm
The rms value of ac (ripple) current through the inductor = ir(rms) = =
2 3 2pXL
2Vm 2 2
= ¥ = Vdc ¥ (4.6.34)
p 3 2 XL 3 2 XL
Figure 4.19 Full-wave rectifier with L-section filter
The reactance XC for second harmonics is assumed to be negligibly small w.r.t RL. Hence, all the ac
components will pass through the capacitor C and only dc current will pass through the load RL. Thus,
2 XC
assuming XC<< RL, the voltage developed across the capacitor = ir(rms)XC = Vdc ¥
3 2 XL
vr ( rms ) Vdc 2 XC 2 XC 2 2
The ripple factor = r = = ¥ = = =
Vdc Vdc 3 2 X L 3 2 X L 3 2 ¥ 4w LC 3 ¥ 4w 2 LC
2
12 ¥ 10 6
= (4.6.35)
LC
#$
It is evident from Eqn. 4.6.35 that the ripple factor is independent of load resistance. The ripple factor
is plotted as a function of w2LC as indicated in Fig. 4.20.
Figure 4.20 Ripple factor
Bleeder resistance
We know that inductor stores energy in its magnetic field when the current is above its average value
and releases the field when the current is below this value. In other words, a minimum current must
flow through the inductor (choke) always. In order to ensure this, a bleeder resistance RB is connected
across the output terminals of the power supply such that even if the load resistance is disconnected, it
will allow a path of minimum current through the inductor. The main functions of bleeder resistance are:
1. Better regulation: The bleeder resistance provides a voltage drop across the output terminals
of the power supply. The connection of load further reduces the output voltage, but the
difference in voltage drop is not much and hence regulation is better.
2. The bleeder resistance provides a discharge path when the power supply is not ON and avoids
hazards such as shock to user.
3. The bleeder resistance can be tapped to provide many different voltages levels.
4.6.4 P -filter
The circuit of a full-wave rectifier along with a p-type LC filter is shown in Fig. 4.21. The waveform of
full-wave including p-type filter is shown in Fig. 4.22.
Figure 4.21 Full-wave rectifier with L-section filter 1

vr ( pp)
From Fig. 4.22 Vdc = Vm - - I dc RL (4.6.36)
2
#%
Figure 4.22 p-filter waveform
The capacitor C1 gets discharged within the half-cycle of the second harmonics i.e.
T = 1/4f (4.6.37)
Q I ¥T I p Ê vr ( pp) ˆ
vr(pp) = = dc = dc ¥ = Á sin 2 w t (4.6.38)
C1 C1 4 fC1 p Ë p ˜¯
p
Hence, dc output voltage Vdc = Vm - ( R + ) Idc (4.6.39)
2w C1
The voltage of sawtooth type waveform of ripple can be expressed as
Ê vr ( pp ) ˆ Ê vr ( pp ) ˆ Ê vr ( pp ) ˆ
vr = Á ˜ sin 2w t - Á ˜ sin 4 w t - Á sin 6 w t (4.6.40)
Ë p ¯ Ë 2p ¯ Ë 3p ˜¯
Since the second harmonics is important for ac, then,
Ê vr ( pp ) ˆ 1/ j 2w C2 Ê vr ( pp ) ˆ 1
v2(rms) = Á ˜ =Á ˜ (4.6.41)
Ë p 2 ¯ jw L + 1/ j 2w C2 Ë p 2 ¯ 1 - 4w 2 LC2
Ê vr ( pp) ˆ 1 p I dc 1 1
v2(rms) = Á ˜ 2
= ¥ ¥ 2
(4.6.42)
Ë p 2 ¯ 1 - 4w LC2 2w C1 p 2 1 - 4w LC2
Vdc= RLI dc (4.6.43)
v2(rms) 1
Hence, the ripple factor = r = = (4.6.44)
Vdc 2 2w C1 (1 - 4w 2 LC2 )RL
2
As 4w LC2 >> 1, Eqn. 4.6.44 reduces to
1
r= 3
(4.6.45)
8 2w LC1C2 RL
For f = 50 Hz, C1 and C2 in mF, L in henry, and RL in ohm. Eqn. 4.6.44 states that the ripple factor is
inversely proportional to the load resistance. The effect of the input capacitor C1 is to obtain higher
voltage for a selected transformer than that possible on other types of filter, but its regulation becomes
poor w.r.t. to the others.
#&
8 2 (2p ¥ 50)3 LC1C2RL = 8 2 ¥ 3.1 ¥ 10 7 LC1C2 RL = 8 2 ¥ 3.1 ¥10 7 LC1C 2 ¥10 -12 R L
= 3.51 × 105 LC1 C2 RL
2.85 ¥ 103 4.03 ¥ 10 3
r= = (4.6.46)
LC1C2 RL 2 LC1C2 RL
4.7 Voltage Multiplier

The voltage multiplier circuits are used to obtain a relatively high peak voltage with very low power
capability stepping up the peak voltage to 2, 3, 4 or more times the peak rectified voltage.
4.7.1 Voltage Doubler

Figure 4.23 is a circuit of a half-wave voltage doubler. The diode D1 conducts but diode D2 remains cut-
off during the positive half-cycle across the transformer secondary. This charges the capacitor C1 to
the peak rectified value of the voltage with the polarity indicated. The diode D2 conducts and D1 remains
cut-off during negative half-cycle as indicated in Fig. 4.23. The input voltage is in series with the voltage
across the capacitor C1 during the negative half-cycle. This charges the capacitor C2 to the value
VC2 = Vm + VC1 = Vm + Vm = 2Vm (4.7.1)
Figure 4.23 Half-wave voltage doubler in positive and negative half-cycle
The capacitor C1 starts discharging in the negative half-cycle. It starts charging again in the positive
half-cycle. Thus, the half-wave voltage doubler supplies the voltage to the load in one half-cycle. Therefore,
regulation of the half-wave voltage doubler is poor.
4.7.2 Full Wave Voltage Doubler

Figures 4.24 and 4.25 are the circuit of a full-wave voltage doubler. The voltage appearing across the
secondary of the transformer forces diode D1 to conduct and diode D2 to cut-off during positive half-
cycle. This charges the capacitor C1 to the peak value of the rectified voltage Vm.
4.7.3 Voltage Tripler and Quadrupler

Figure 4.26 is the typical circuit of a tripler and quadrupler. The diode D1 conducts charging C1 to Vm
with the polarity indicated in first positive half-cycle. Diode D2 conducts in the first negative half-cycle.
The input voltage is in series with the voltage across the capacitor C1, charging C2 to 2Vm in this
#'
negative half-cycle. The charge on capacitor C1 starts decreasing in the process. Diodes D1 and D3 will
conduct in the second positive half-cycle. The capacitor C1 will be charged to Vm whereas the capacitor
C3 will be charged to Vc3 = Vm + VC2 VC1 = Vm + 2Vm Vm = 2Vm. The diodes D2 and D4 will conduct
charging C4 in the second negative half-cycle, to voltage = VC4= V m + VC1 + VC3 VC2 = Vm + Vm + 2Vm
2Vm = 2Vm
Figure 4.24 Full-wave voltage doubler
Figure 4.25 Doubler in +ve and –ve half cycles
Figure 4.26 Tripler and quadrupler
Thus, the circuit of Fig. 4.26 can be used as voltage doubler, trippler, and quadruplar across different
terminals.
$
4.8 Voltage Regulation

The output dc voltage of full-wave rectifier was derived as
2Vm Ê rs + rd ˆ 2Vm
Vdc = Á 1- = - I dc (rs + rd ) (4.8.1)
p Ë rs + rd + RL ˜¯ p
It is observed from this equation that the output dc voltage not only depends on the load resistance but
also on the dynamic resistance rd of the diode and the resistance of the secondary winding of the
transformer rs. Hence, the output dc voltage of any rectifier changes with the load, i.e. current drawn
through it. In order to maintain it constant over a range of load current, voltage regulation circuit must
be included in it. The simplest voltage regulator is a Zener diode. Once its breakdown occurs, its voltage
remains almost constant for very large variation in the current drawn from it. Its reverse bias characteristic
is shown in Fig. 4.27.
The voltage regulation circuit is drawn as Fig. 4.28.
Figure 4.27 Zener characteristic
Figure 4.28 Zener diode regulator circuit
Case I: (Fixed VI and RL )
From Fig. 4.28, Iin = IZ + IL (4.8.2)

Once the Zener breaks down, the voltage across the load becomes a constant. Hence, the series
resistance Rs is
$
VI - Vdc
Rs = (4.8.3)
I in
The power dissipated across the Zener diode is determined by
PZ = V ZI Z (4.8.4)
Case II: (Variable VI and RL )

The minimum value of load resistance to turn the Zener diode ON can be calculated as
RLVI V r r V - VZ
VL = VZ = , I = 1 + s and s = I (4.8.5)
rs + RL Vz RL RL VZ
VZ rs
RL(min) = (4.8.6)
VI - VZ
This condition of minimum RL establishes maximum IL and hence,
V VZ
IL(max) = Z = (4.8.7)
RL RL (min)
1. Determine the peak and rms voltages on the Vdc = IdcRL = 86.56 × 103 × 100 = 8.66 V
secondary of a transformer connected
across a bridge rectifier to provide a no load 2Vm Ê rs + 2rd ˆ
Vdc(full load) = ÁË1 r + 2r + R ˜¯
dc voltage of 9 V. If the secondary winding p s d L
resistance is 3 W and dynamic resistance of = 8.57 V = 8.6 V
each diode is 1 W, determine the dc output
across a load resistance of 100 W and 1 K. 9 - 8.6
Regulation = = 4.06 %
Also determine the regulation. 8.6
Solution : 2. A 220 V, 60 Hz voltage is applied to a centre
tapped step-down transformer of 22 : 1 with
2Vm a load of 1 K connected across the output of
rs = 3 W, rd = 1 W, RL = 100 W, Vdc =
p two-diode full-wave rectifier. Assume diodes
9p to be ideal. If the resistance of half-second-
Vm = = 14.14 V, ary winding is 0.5 W, determine the (a) peak,
2
rms and dc voltages, (b) peak, rms and dc
V 14.14
vrms = m = = 10 V currents, (c) dc power delivered to the load,
2 1.414 (d) VA rating of the transformer secondary,
Vm 14.14 (e) ac input to transformer assuming it to be
Im = = = 0.135 A,
rs + 2rd + RL 105 80% efficient, (f) ac ripple voltage across
2 Im 2 ¥ 0.135 the load and its frequency, (g) How much is
Idc = = = 86.45 mA the PIVof each diode if the circuit is changed
p p
$
to a bridge rectifier using the full secondary 4Vm 4 ¥ 7.07

vrms = = = 3.0 V
winding of the same transformer? (h) How 3p 3p
much are the peak, rms, dc voltages? (g) PIV = 2Vm = 14.14 V
Solution:
2Vm
(a) Vm (between full secondary) = 10 2 = (h) vpeak = 10 2 = 14.14V, V dc =
p
14.14 V
14.14
vrms(full secondary) = 10 V, Vm(half = 4.5 V, vrms = = 10 V
2
secondary) = 7.07 V
DC power across the load
2Vm 2 ¥ 5 ¥ 2
Vdc = = = 4.5 V 2
VDC 4.52
p p = = = 20.25 mW
RL 1K
Vm 5 2 3. Calculate the VDC, IDC, Vr(rms), Irms through
(b) Im = = = 7.06 mA,
rs + rd + RL 1001.5 a 1 KW load connected to a half-wave rectifier
2 I m 2 ¥ 7.06 circuit shown in Fig. 4.29 (a).
and Idc = = = 4.495 mA
p p
2
(c) DC power delivered to the load = I DC RL
2
= (4.495 mA) 1 K = 20.2 mW
(d) VA rating of the transformer can be
found out using TUF.
PDC(out) Figure 4.29(a)
TUF = = 0.693
Pac(rated)
20.2 mW
Pac(rating) = = 29.15 mVA
0.693
PDC Psec ondary

(e) h = = 0.812, = 0.8
Pac Pac(rated) Figure 4.29(b)
20.2 mW Solution:
Pac(secondary) = = 24.88 mW
0.812
Vm 2Vrms 2 ¥ 230
24.88 VDC = = =
and Pprimary = = 31.1 mW p p p
0.8
V
(f) As the ripple voltage under = 103.5 V, IDC = DC 103.5 mA,
RL
consideration would be the second
harmonics because the magnitude of Im 2Vrms V 230
higher harmonics will become much less Irms = = = rms =
2 2 RL 2RL 2 ¥1K
than it. Hence, the ac ripple voltage is
expressed as = 162.6 mA
$!
Vr (rms) Pac(input) = I 2rms(rd + RL) = 15.552(0.001 + 1)

Ripple factor = = 1.21, Vr(rms)
VDC PDC 98
= 242 mW, h = = = 40.1%
= 1.21 ¥ VDC = 125.3 V Pac(input) 242
4. A sinusoidal voltage of 22 V, 50 Hz is applied
to a half-wave rectifier in Fig. 4.29(a) with 2
Ê I rms ˆ Ê 15.55 ˆ
2
dynamic resistance of the diode of 1 W. r= ÁË I ˜¯ 1 = ÁË
9.9 ¯
˜ 1 = 1.21
Calculate the maximum dc and rms currents DC
flowing through the load. Also calculate the 5. A 230 V 0 230 V input voltage is
dc output power developed, ac-input power connected to a full-wave rectifier shown in
supplied, rectification efficiency, and ripple Fig. 4.30. Calculate the dc, ac voltages, dc
factor. and ac power developed across the load. Also
Solution: calculate the dc, rms currents that will flow
Vm = 2 Vrms = 2 ¥ 22 V = 31.1 V, through the load.
Solution:
Vm 31.1 31.1
Im = = = = 31.1 mA 2Vm 2 2 Vrms
rd + RL 0.001+1 1001 2 2 ¥ 230
VDC = = =
p p p
Im 31.1 I
IDC = = = 9.9 mA, Irms = m VDC
p p 2 = 207 V, IDC = = 207 mA,
RL
31.1
= = 15.55 mA, PDC = I 2DC RL = 9.92
2 2 ¥ 230
Im = = 325.3 mA
¥ 1 K = 98 mW 1K
Figure 4.30
I 2Vrms V Pin(ac) = V 2rms RL = 2302 ¥ 1 K = 52.9 W

Irms = m = = rms = 230 mA,
2 2 RL RL 6. Obtain number of turns in the primary and
secondary of a transformer connected in
2 Fig. 4.31 to develop a dc voltage of 10 V
VDC 207 2
PDC = = = 42.85 W across a load off 1 KW. What is the frequency
RL 1K
of the ac voltage present across the load?
$"
If there are 100 turns in the primary, then it

must have 10 turns in the secondary.
Frequency of the ac voltage present across
the load = fin = 50 Hz.
7. Calculate the ripple factor without and with
capacitor filter in Fig. 4.32.
Figure 4.31
Solution:
Solution: 2Vm pVDC 10p
VDC = , Vm = = = 5p
V p 2 2
VDC = m , Vm = pVDC = p ¥ 10 = 31.42 V
p V 15.7
= 15.7 V, Im = m = 15.7 mA,
np 220 2 RL 1K
Turn ratio = = = 9.9 :1 @ 10 :1
ns 31.42
Figure 4.32
15.7 Theoretical ripple factor including filter =

Im 10
Irms = = = 11.1 mA, IDC =
2 2 RL 2887 2887
= = 0.029
= 10 mA CRL 100 ¥ 1000
Ê 11.1ˆ
2 8. What is the value of VDC and Vac developed
Hence, g = ÁË ˜ 1 = 1232 1 across the load in circuit of Fig. 4.33
10 ¯
assuming all diodes to be ideal. What is the
frequency of ac voltage present across load?
= 0.2321 = 0.482
Figure 4.33
$#
Solution:
220 2
Vm on the full secondary side =
Np / Ns
220 2
= = 31.1 V
10
Half secondary voltage = 15.55 V
Vac across the load = 15.55 V Figure 4.34
2Vm Solution:
VDC = = 9.9 V
p From Fig. 4.34, Vr(pp) = 0.6 V, V DC =
Frequency of the ac voltage present across Vr
Vm = 6.4 0.3 = 6.1 V
the load = 2 fin = 100 Hz. 2
9. Design a full-wave rectifier with LC filter to
provide 10 V dc at 100 mA along with Vr (pp) / 2 0.6 / 2 0.3
Vr(rms) = = = = 0.173 V,
maximum ripple of 2%. The frequency of 3 3 3
input voltage is 50 Hz. Determine the ripple
factor of the LC filter. Vr (rms)
Ripple factor from Fig. 4.34 is =
Solution: VDC
1 1 0.173
r = 0.02 = = = = 0.0284
2
6 2w LC 6 2(314) 2 LC 6.1
1 1 Ripple factor from theoretical expression is
= = 2887 2887
6 2(98596) LC 836614.8LC =g = = = 0.02887
CRL 1000 ¥ 100
1 DC voltage from expression = V DC =
or, LC = = 5.97 ¥ 10 5
16732.3 Vm 6.4
=
2RL 2 ¥ 100 1 + 1/4 f CRL 1 + 1/4 ¥ 50 ¥ 1000 ¥ 100
Critical inductance = Lc = =
3w 3 ¥ 314 6.4
= = 6.2 V
= 0.2123 H 1.05
11. Calculate the ripple factor in the case of a
5.97 ¥ 10 5
Hence, C = = 281.5 mF full-wave rectifier with p-filter having the
0.2123 component values C1 = C2 = 500 mF and
10. Figure 4.34 is the output waveform of a half- laod resistance = 100 W.
wave rectifier with capacitor filter. The value Solution:
of the capacitor is 1000 mF and the value of Expression for ripple factor = r =
load resistance is 100 W with frequency of
input voltage equal to 50 Hz. Determine the 2.85 ¥ 10 4 2.85 ¥ 104
=
ripple factor and dc voltage. C1(mF) C2 (mF) RL (W) 500 ¥ 500 ¥ 100
= 0.0057
$$
Show that maximum dc power is transferred voltage, (b) dc current through bleeder
to the load in a full-wave rectifier only when resistance, (c) dc current through the load,
the dynamic resistance of the diode is equal (d) ripple factor?
to the load resistance. Solution:
12. Design a full-wave rectifier with an LC filter Value of bleeder resistance (load resistance
that can yield dc voltage of 9 V at 100 mA is open) = RB = 3w L = 3 ¥ 2p f ¥ L =
with a maximum ripple of 2%. 28.3 KW
Solution:
1.2 ¥ 10 6 1.2 ¥ 10 6
r = 0.02 = , LC =
LC 0.02
= 0.6 ¥ 10 4
9V R 90
RL = = 90 W, LC = L =
0.1 700 700 Figure 4.35
= 0.13 H
1 1 1
If LC is selected to be 0.13 H, Total load resistance = = +
RL RB RL
0.6 ¥ 10 4 1 1 38.3 283 K
C= = 4.6 ¥ 10 4 = 460 mF and = + = , RL =
0.13 28.3 10 28.3 ¥ 10 K 38.3
if LC is selected to be ten times higher than = 7.39 KW
0.13 H i.e. 1.3 H, then C = 46 mF = 50 mF 2Vm 2 ¥ 250
(standard value). (a) VDC = = = 159.2 V
p p
RB = 700 Lmax = 700 ¥ 1.3 H = 910 W 159.2
(b) dc current through R B =
Since RB is ten times higher than the load 28.3 KW
resistance RL = 90 W, it will waste little = 5.63 mA
power with the advantage of using L > LC. 159.2
(c) dc current through R L =
13. A full-wave rectifier uses the LC filter as 10 KW
shown in Fig. 4.35 having the component = 15.92 mA
values as L = 30 H, C = 25 mF. Calculate the
2 1
value of bleeder resistance required for the (d) ripple factor = r = ¥
rectified voltage = 250sin 100p t. If the value 3 4w 2 LC
of load resistance is RL connected in 10 KW, 1.194 1.19
= = 0.0016 = 0.16 %
what would be the value of (a) filter dc output LC 30 ¥ 25
Questions for Practice curs when the load resistance equals the
diode resistance.
1. Show that the maximum dc output power 2. An LC filter is connected to the output of a
in a half-wave single-phase rectifier oc- full wave rectifier with C =100 mF,16 V
$%
and L = 10 mH. The regulated output is only when the dynamic resistance of the
6 V, 600 mA. Find out the value of bleeder diode is equal to the load resistance.
resistance. 4. Figure 4.35 is the circuit of half-wave dou-
3. Show that maximum dc power is trans- bler. Draw the circuit of a full-wave dou-
ferred to the load in a full-wave rectifier bler and show their waveshapes
Figure 4.35(a) Full-wave voltage doubler
Figure 4.35(b) Full-wave voltage doubler
Multiple Choice Questions (a) very large (b) very small

(c) medium
1. Using filter, circuit ripple factor of a recti- 5. Increasing load current makes the dis-
fier is charge time constant in RC filter
(a) decreased (b) increased (a) larger (b) smaller
(c) not affected (c) constant
2. The best filter configuration is 6. Ripple increases in shunt capacitor filter
(a) L-type (b) p-type (a) with decreasing load current
(c) RC-type (b) with increasing load current.
3. Simplest and cheapest configuration of fil- (c) without load current
ter is 7. The maximum value of capacitor used in
(a) shunt capacitor the shunt capacitor filter
(b) L-type (a) depends on the maximum safe value
(c) p-type of the diode current
4. The value of capacitive impedance in com- (b) minimum value of diode current
parison to RL in a shunt capacitor filter is (c) does not depend on diode current
$&
8. Operation of series inductor filter (a) 46% (b) 40.6%

(a) depends on the magnitude of current (c) 80% (d) 120%
through it 17. The percentage regulation in half and full-
(b) is independent of current wave rectifiers are
(c) depends on voltage across it (a) equal (b) unequal
9. Increase in load current for series inductor (c) not of interest
filter 18. For the secondary voltage of Vm sin wt in a
(a) decreases ripple half-wave rectifier the reading of an AC
(b) increases ripple voltmeter across the load is
(c) does not change the ripple (a) Vm / 2 (b) Vm /2
10. Ripple in LC-type filter with increasing (c) 2V m (d) V m/p
load current 19. The internal resistance seen by the load in
(a) increases half-wave rectifier is
(b) decreases (a) rs + rd (b) 2(rd +rs)
(c) remains constant (c) (rs + rd)/2
11. In the case of an inductor filter, a bleeder 20. Output voltage in a half-wave rectifier con-
resistor is sists of
(a) essential (a) dc only (b) dc and ac both
(b) not essential (c) ac only
(c) none of these 21. The ac component of voltage in the output
12. The disadvantages of capacitor input LC of a half-wave rectifier contains
filter is (a) only fundamental frequency
(a) high cost, more weight and external (b) only harmonics of fundamental fre-
field produced by series inductor quency
(b) high cost, less weight (c) both fundamental and its harmonics
(c) low cost, more weight 22. The magnitude of ac voltage for increasing
13. PIV in the case of a half-wave rectifier value of harmonics
with Vm sin wt appearing across the sec- (a) increases
ondary of the transformer is (b) decreases
(a) V m (b) 2V m (c) remains constant
(c) 4V m (d) Vm /2 23. The most significant component of ripple
14. The maximum DC voltage developed voltage in a half-wave rectifier is con-
across the load resistance in a half-wave tained in
rectifier is (a) fundamental frequency
(a) V m/p (b) Vm / 2 (b) second harmonics
(c) 1/Vm (d) 2Vm /3 (c) dc component
15. Ripple factor in a half-wave rectifier is 24. PIV in a full-wave rectifier used in centre
(a) V m/p (b) 1.21 tapped transformer is
(c) 2.42 (d) 2Vm /p (a) V m/p (b) 2Vm /p
(e) V m (c) 2 Vm (d) V m
16. Rectification ratio in the case of a half- 25. Rectification ratio in a full-wave rectifier is
wave rectifier is (a) 40.6% (b) 81.2%
(c) 80%
$'
26. Ripple factor in a full-wave rectifier is 35. The ripple frequency in a full-wave recti-
(a) 0.482 (b) 1.5 fier is
(c) 1.2 (d) 0.3 (a) double the input frequency
27. Reading of a dc voltmeter across the load (b) equal to the input frequency
in a full-wave rectifier with a voltage of (c) half the input frequency
100p sin wt across both half sections of 36. The output frequency of a half-wave recti-
secondary windings is fier is
(a) (100/p) V (b) (200/p) V (a) equal to the input frequency
(c) 200 V (b) two times the input frequency
28. If the input voltage in a bridge rectifier is (c) half the input frequency
Vm sin wt, then PIV is 37. The input to a full-wave rectifier is 50 sin
(a) V m (b) 2V m 100 pt. The ripple frequency is
(c) 2 Vm /p (a) 50 Hz (b) 100 Hz
29. Two diodes full-wave rectifier requires (c) (50/2p) Hz (d) (2p/50) Hz
(a) centre tapped secondary transformer
38. Relationship between the peak voltage Vm
(b) no centre tapped transformer
and the r.m.s. voltage Vrms of a sinusoidal
(c) three tapping in the secondary winding
voltage in a full wave rectifier is
30. The centre tapped transformer for a bridge
rectifier is (a) vrms = Vm (b) Vm = 2v rms
(a) not essential (c) Vm = v rms / 2
(b) essential 39. Relationship between the input and output
(c) some times needed frequencies of a half-wave rectifier is ex-
31. TUF in the bridge rectifier is pressed as
(a) 0.812 (b) 0.287 (a) f = fi/2 (b) f = 2fi
(c) 0.55
(c) f = fi
32. For low voltage rectification
(a) two-diode full-wave rectifier is suit- 40. Relationship between the input and output
able frequencies of a full-wave rectifier is ex-
(b) bridge rectifier is suitable pressed as
(c) both bridge and two-diode rectifiers f
(a) f = i (b) f = 2fi
are equally suitable 2
33. Load current in a half-wave rectifier flows (c) f = fi
for 41. The regulation of an excellent rectifier
(a) complete cycle of the input should be
(b) half cycle of the input (a) infinity (b) zero
(c) less than half cycle (c) negative
(d) more than half and less than full cycle 42. The power supply with the highest per-
34. Load current in full-wave rectifier flows centage of regulation is
for (a) the best (b) the worst
(a) both half-cycles of the input (c) tolerable
(b) one half-cycle 43. The most negative point in a full-wave rec-
(c) less than half-cycle tifier is
%
(a) centre tap of the secondary 44. The ac input to a half-wave rectifier is
(b) chassis ground 28.3V peak. Neglecting the drop across the
(c) either cathode diode, the dc across the load will be
(d) either anode (a) 28.3 V (b) 20 V
(c) 14.15 V (d) 9 V

1. (a) 2. (b) 3. (a) 4. (b) 5. (a) 6. (b)
7. (a) 8. (a) 9. (b) 10. (c) 11. (a) 12. (a)
13. (a) 14. (a) 15. (b) 16. (b) 17. (a) 18. (b)
19. (a) 20. (b) 21. (c) 22. (b) 23. (a) 24. (c)
25. (b) 26. (a) 27. (b) 28. (a) 29. (a) 30. (a)
31. (a) 32. (a) 33. (b) 34. (a) 35. (a) 36. (a)
37. (b) 38. (b) 39. (c) 40. (b) 41. (b) 42. (b)
43. (b) 44. (d)
5
Physical
Phenomenon in BJT
5.1 Introduction
John Bardeen and Walter Brattain of Bell Telephone Laboratory, America, invented the point contact
transistor in the year 1948. Subsequently these two along with William Shockley replaced the point
contact transistor by junction transistor in 1949. They were jointly awarded Nobel Prize in recognition
of this unique work in Physics. The role of semiconductor in electronics technology has assumed much
greater prominence with the advent of the transistor. The invention of the transistor revolutionised the
field of electronics. Since then rapid and continuous development of semiconductor devices such as
FET, MOSFET, SCR, etc. have been taking place. The junction transistor is more appropriately called
Bipolar Junction Transistor (BJT). It is called bipolar as the current carried inside it is caused by two
opposite polarities of charge carriers, i.e. holes (positive charge carriers) and electrons (negative charge
carriers). Since these two types of charge carriers contribute currents inside the transistor it is called
bipolar transistor.
The bulky vacuum tubes for performing different functions such as amplification, switching, wave
shaping, waves generation, etc. have almost been replaced by the BJTs. The special features of BJTs
are as follows:
∑ They are small in size
∑ They are mechanically rugged
%
∑ No power is required for heating a filament. In complex installation such as computers, this can
mean a substantial saving in air cooling equipment which is radiated by large number of vacuum
tubes
∑ They have long life, primarily due to the fact that there is no evaporation of cathode
∑ No warm up-time is required. Instruments made with BJT start instantaneously on being
switched ON, but if vacuum tubes are used warm-up time is required
∑ Low voltage power supplies are sufficient. In many cases batteries are more economical than
rectified power supplies
∑ Complementary existence of n-p-n and p-n-p transistors give more versatility in the circuit
design
∑ They are light in weight
∑ They occupy less space
∑ They are shock-proof
∑ They consume little power that results in greater efficiency.
The limitations of BJTs are
∑ Its characteristics are strong function of temperature. In many special applications compensa-
tion circuit must be employed to prevent excessive drift in overall circuit performance as ambi-
ent temperature changes.
∑ The BJTs are limited in power output as compared to vacuum tubes. However, special transis-
tors are available with very high power ratings.
5.2 Physical Structure

The BJT is a three-layer active device having two p-n junctions connected back to back or forward to
forward as shown in Fig. 5.1. The circuit symbols of p-n-p and n-p-n transistors have been drawn in
Fig. 5.2.
Figure 5.1 Back to back or forward to forward connected BJT
Figure 5.2 Circuit symbol of p-n-p and n-p-n BJT

Thus, if an n(p) type material is sandwiched between two p(n) type materials, the resulting structure is
called the p-n-p (n-p-n) transistor as demonstrated in Fig. 5.1. The first layer from which emission or
(more appropriately) injection of carrier starts is called the emitter, the second layer is called the base
Physical Phenomenon in BJT
%!
and the third layer which collects the injected carriers is called the collector. The relative sizes of the
emitter, base and collector layers have not accurately been shown in Fig. 5.1. The base region is the
thinnest and it is lightly doped so that most of the injected carriers do not recombine in the base region
but diffuse to the collector region. The impurity concentration of emitter and collector regions is from
twenty to hundred times the impurity concentration of the base region. The size of the collector region
is the largest, as it has to collect all the injected carriers and to withstand the large reverse bias voltage.
The size of the emitter falls in between the base and the collector region. Since the concentration of
emitter and collector regions is much higher than the base region, the two depletion widths almost
extend in the base region.
5.3 Operation of BJT

A BJT has two junctions, namely, emitter-base or emitter junction and collector-base junction or collector
junction. Depending upon bias condition (forward or reverse) of these two junctions, different modes
of operation of the BJT are obtained as illustrated in Table 5.1.
The collector works as emitter and the emitter works as the collector in the inverse active operation.
Since the emitter is heavily doped w.r.t. the collector, the current amplification factor is very less in the
inverse active mode as compared to the normal active mode.
Table 5.1 Modes of operation of the BJTs

Cases Emitter-base junction Collector-base junction Region of operation
I Reverse biased Reverse biased Cut-off
II Forward biased Reverse biased Active
III Forward biased Forward biased Saturation
IV Reverse biased Forward biased Inverse active
Figure 5.3 shows the structure of the unbiased n-p-n transistor. The depletion widths at two junctions
in this figure have been exaggerated to indicate its existence clearly.
Figure 5.3 Depletion width of unbiased BJT

The typical depletion widths under forward biased emitter-base junction and reverse biased collector-
base junction of BJT is shown in Fig. 5.4.
Figure 5.4 Depletion width of normal biased BJT

%"
Figure 5.5 indicates the depletion widths for open collector with forward biased emitter-base junction,
while Fig. 5.6 shows depletion width of open emitter with reverse biased collector-base junction.
Figure 5.5 Depletion width for open collector of BJT
The emitter-base junction is forward biased and the collector-base junction is reverse biased for normal
operation of a transistor (BJT) as shown in Fig. 5.4. Forward bias means application of external dc
voltage across the junction to cancel the inherent potential barrier across the junction that does not allow
either type of the carriers to cross the junction. Hence, forward bias is nothing but application of dc
voltage externally with its positive terminal tied to the p-type material and negative terminal to the n-type
material as depicted in Fig. 5.4. In the case of reverse bias, the p-type material is connected to negative
terminal of the battery and n-type material is connected to the positive terminal of the battery. Thus, the
reverse bias (battery) is connected in parallel to the inherent potential barrier across the junction and
hence, it adds to the potential barrier and increases the depletion width.
Figure 5.6 Depletion width for open emitter of BJT
5.4 Transport Phenomenon

With emitter-base junction of a n-p-n (p-n-p) transistor forward biased (VEB > yo) and collector-base
junction reverse biased as shown in Fig. 5.7, the electrons from n(p)-type emitter region are injected
into the p(n)-type base region. The p(n)-type base region has vast majority of holes (electrons). Some
of the injected electrons (holes) as minority carriers in the base collide with majority holes (electrons)
and hence, recombine with the holes(electrons) in the base region. However, as the base region is very
thin, most of the electrons (holes) diffuse to the collector region as illustrated in Fig. 5.7.
%#
Figure 5.7 Carrier motion in normal biased BJT
The electrons (holes) are pulled into the collector region by the electric field existing between the
positive donor ions in the depletion width on the collector side and the negative acceptor ions in the
depletion layer on the base side. Typically 98% or even more of the electrons entering the base region
reach the collector region. The relatively large collector to base bias voltage VCC does rest of the work
by attracting the electrons no sooner than they reach the collector region and forces them to flow
through and deliver power to an external load.
In Fig. 5.8, the total current through the forward biased emitter junction is the sum of the currents
due to the diffusion of electrons and holes. Since the doping concentration is very low in the base
region, few holes are available in the base region than the number of electrons in the emitter region.
Hence, almost 99% current through emitter junction is due to electrons. In this situation it is a
p-n (n-p) junction diode.
IE = IB, (IC = 0). (5.4.1)
Figure 5.8 depicts the reverse biased collector-base junction. The total current through collector
junction is partially due to hole and electron diffusions. Since in reverse biased condition both holes and
electrons of collector junction are minority charge carriers, magnitude of the current passing through
the collector junction is very small and is called collector leakage current ICBO (collector to base current
with emitter open). Figure 5.8 shows the various current components that flow across the forward-
biased emitter-base junction and the reverse-biased collector base junction.
IE = IpE + InE (5.4.2)
where, IE = total emitter current
IpE = component of emitter current due to holes
InE = component of emitter current due to electrons
The emitter injection ratio or the emitter efficiency is defined as the ratio of current injected from
emitter to the base (due to electrons) to total emitter current. It is denoted by symbol g and is expressed
as
I nE I
g= @ nE (5.4.3)
I nE + I pE I E
%$
Figure 5.8 Current components of normal biased BJT
Since, doping concentration of emitter region in commercial transistor is made much higher than the
doping level in the base, the emitter current consists almost entirely of electrons, i.e.
InE >> IpE (5.4.4)
IE = IpE + InE @ InE (5.4.5)
The typical value of g @ 0.995 (5.4.6)
All injected electrons from emitter region do not reach collector junction because some of them
recombine with the holes in the p-type base and disturb the charge neutrality of the base region. For
each recombined electron, the battery connected across emitter-base junction supplies equal number of
holes that were recombined to maintain the charge neutrality of the base region instantly. Thus, the holes
supplied from the base terminal that flows from the battery to the base layer are responsible for the
existence of base current entering into the base lead of the n-p-n transistor. The ratio of number of
injected carriers from emitter (electrons) arriving at the collector to the number of carriers (electrons)
injected into the base is known as base transport factor. It is denoted by symbol b*. Thus b* is
expressed as
I
b* = nC (5.4.7)
InE
The typical value of b* = 0.995
If the emitter-base is kept open
IE = 0 = InC (5.4.8)
The collector-base junction would then act as a reverse biased diode and the current that flows in the
reverse biased collector junction is called the reverse saturation current ICBO or ICO. If IE π 0, then in
that case
%%
IC = InC + ICO = b*InE+ ICO = b*gIE + ICO =(0.995 ¥ 0.995)IE + ICO= 0.99IE + ICO (5.4.9)
Thus Eqn. 5.4.9 can be written as
IC = a IE + ICO (5.4.10)
IE = IC + IB (5.4.11)
where, a = forward current transfer ratio.
It would be appropriate here to indicate that this forward current transfer ratio increases slightly with
the increase in the collector-base voltage VCB. The collector current is less than emitter current. There
are two reasons for this. Firstly, a part of the emitter current consisting of holes (in the case of an
n-p-n transistor) does not contribute to the collector current. Secondly, not all electrons injected into the
base successfully reach the collector. The first factor is represented by g and the second factor by b*.
Thus, gb* =
F InE I F I I =F I I
nC nC
(5.4.12)
GH I nE + I pE
JK GH I JK GH I JK
nE nE
Its typical value comes out to be = gb* = 0.995 ¥ 0.995= 0.99.
5.5 DC Equivalent Circuit

Sometimes it becomes essential to calculate the steady state currents and voltages in the circuit involving
a transistor. Hence, we are required to represent transistor by its dc equivalent circuit. Figures 5.9 and
a 5.10 are equivalent circuits that may be used to represent both n-p-n and p-n-p transistors. Each
equivalent circuit can be characterized by the following two equations
IET = ICT + IBT (5.5.1)
ICT = hFE IBT (5.5.2)
where IET, ICT, and IBT are being used to denote the emitter, collector and base currents of the ideal
transistor used in the equivalent circuit of Fig. 5.9.
Figure 5.9 dc equivalent circuit of IC

%&
The base-emitter voltage VBE or VEB (barrier potential) in Fig. 5.9 is shown as a battery in series with
the emitter lead. The leakage current ICBO = ICO of collector-base junction is shown as constant current
generator across the collector base junction as it is almost constant (it is temperature dependent and is
taken as constant for simplicity).
5.6 Static Characteristics of BJT

The features of BJT are described by two types of its V-I characteristics. These are :
∑ the input characteristic
∑ the output characteristic.
The plot of enforcing input dc current for changing input dc voltage for a fixed output dc voltage is
called the input characteristic. Since the details of CC configuration can easily be obtained from CE
configuration, the static characteristic of CC configuration is not drawn separately.
5.6.1 Common Base (CB) Configuration

The base terminal is made common to both input and output sides in the common base configuration as
shown in Fig. 5.10. Thus, live input terminal is the emitter and the live output terminal is the collector.
Input Characteristic in CB Configuration
The BJT (transistor) is a three-terminal active device. It can be represented as a two-port network by
connecting one of its three-terminals common to both input and output side of the circuit. The voltage
and current relationships describe it. It is common practice to treat the emitter current IE as a function
of base-emitter voltage VEB with collector to base voltage VCB as a parameter, i.e.
IE = f (VEB , VCB) (5.6.1)
Here, in Fig. 5.9, IET = IE
The input V-I characteristic of a transistor in CB configuration is drawn as in Fig. 5.11. Its input
resistance can be derived from the knowledge of semiconductor diode characteristic. For a given value
of VCB, the curve is just like the diode characteristic in forward bias case. For higher value of VCB, the
emitter current IE increases for a fixed value of VEB as depicted in Fig. 5.11.
Figure 5.10 Circuit for static characteristic of BJT
DVEB VEB2 VEB1

r in= reb= hib = @ (5.6.2)
DI E I E 2 I E1 VCB = K
%'
The dynamic input resistance is very low (20 W to 100 W).

The plot in Fig. 5.11 is the exaggerated one for clarity for VCB = 1 V, 10 V, 20 V. The dynamic input
resistance of transistor in CB configuration is defined as in Eqn. 5.6.2.
Figure 5.11 Input characteristics of BJT in CB

Output Characteristic in CB Configuration
The static output V-I characteristic of transistor is called the output characteristic. It is the plot of the
change in the output dc current with the change in the dc output voltage for a fixed value (parameter) of
input current IE as shown in Fig. 5.12. It is customary to represent the collector current as a function of
input, emitter current IE and output voltage, VCB. Mathematically it is expressed as
IC = f (IE, VCB) (5.6.3)
Figure 5.12 Output characteristics of BJT in CB

&
Hence, the output V-I characteristic will be the plot of the output current IC versus the output voltage
VCB with the input current IE as a parameter. The whole output characteristic can be divided into three-
regions, namely,
∑ Cut-off region
∑ Active region and
∑ Saturation region.
These three-regions are clearly indicated in Fig. 5.12.
Cut-off Region
Both emitter-base and collector-base junctions are reverse biased in this region. Under reverse bias
condition IE = 0. That is ICT = 0, hence IC = ICO. This is the reverse saturation (leakage) current ICO. The
characteristic curve passes through the origin for IE = 0.
Active Region
The emitter-base junction is forward biased and collector-base junction is reverse biased in this region.
The curve is almost constant in the entire region. It indicates that the collector current is more or less
independent of collector voltage and depends only on emitter current. The collector current is expressed
as
IC = ICT + ICO = a IE + ICO (5.6.4)
Thus, total collector current has two-parts
∑ leakage current and
∑ input current (emitter current) amplified by amplification factor a.
Saturation Region
Both emitter-base and collector-base junctions are forward biased in this region. From Fig. 5.12 it is
clear that the voltage to the left of the ordinate V is opposite to the right of the ordinate. Since the voltage
to the right of the ordinate is reverse bias the voltage to left of the ordinate is forward bias for the
collector-base junction. For any appreciable value of IE or IC, the emitter-base junction should be
forward biased. Hence, saturation region has both emitter-base and collector-base junctions forward
biased. In this region, change in current is very sharp for change in VCB.
The output characteristic helps to determine the dc and ac amplification factors and the dynamic
output resistance of the transistor. The dc current amplification factor of a transistor in CB configuration
is defined as
ICT
adc= (5.6.5)
IET
The typical value of adc = 0.98. (5.6.6)
Since an amplifier handles ac signals, the ac current amplification factor should only be used in the
design equation of the amplifiers. Under such condition we are interested in the small changes in the
voltages and currents rather than their large (dc) value. One is interested in knowing the change in
&
collector current for a given change in the emitter current. This information is obtained from dc alpha
(adc or hFB). It is expressed as
DICT
a ac = a dc = hFB = (5.6.7)
DIET VCB = K
where, DICT and DIET are changes as small as measurable.

The dynamic output resistance is defined as
1 DVCB
ro= = (5.6.8)
hob DI CT I ET = K
where, DVCB and DICT are maximum possible small change in collector-base voltage for the corresponding
small change in collector current.
We can see from Fig. 5.12 that the collector current curve is almost constant for any change in VCB
beyond VCB = 1 V. Thus, very large change in VCB can result in negligible change in the ICT which means
that output resistance ro is very high of the order of megohms.
5.7 Common Emitter (CE) Configuration

The emitter terminal is connected to both input and output sides of the circuit in common emitter
configuration as shown in Fig. 5.13. The input voltage is applied between base and emitter and the
output voltage is measured between collector and emitter.
Input Characteristics
The input current is the base current in CE configuration and it is expressed as
IB = f (VBE , VCE ) (5.7.1)
The plot of the input current IB versus changing input voltage VBE for three fixed values of VCE = 1 V,
10 V, 20 V are shown in Fig. 5.14. The input dc resistance is the ratio of dc-input voltage and dc input
current.
Figure 5.13 CE circuit

&
Figure 5.14 Input characteristics of BJT in CE

The dynamic input resistance in CE configuration of transistor is defined as
DVBE
rin = hie= (5.7.2)
DI B VCE = K
It is of the order of KW.
Output Characteristic
The output current in CE configuration is the collector current and it is expressed as
IC = f(IB, VCE) (5.7.3)
The dynamic output resistance is written as
1 DV
ro = = CE (5.7.4)
hoe DI C IB = K
The collector current IC is plotted against collector to emitter voltage VCE keeping the base current as a
fixed parameter as shown in Fig. 5.15 the increasing VCE increases collector current IC very rapidly but
it levels off after a few volts (1 V or 2 V) for one value of the base current IB1.
For IB = 0, the collector current is equal to
ICEO = (1 + b) ICBO (constant)
This is the cut-off region current. For each increment in the base current DIB, the collector current is
increased by an amount of bDIB Small change in a produces greater change in b and hence effect of
VCE is here more pronounced. Note that in active region VCB = VCE VBE @ VCE, as VEE is very small
w.r.t. VCE .
As VCC >> VBB in Fig. 5.13 the collector point is more positive than the base point. In other words,
the base terminal is negative w.r.t. collector terminal and hence
VCE = VCB + VBE (5.7.5)
&!
Figure 5.15 Output characteristics of BJT in CE
The dc amplification factor bdc is defined as

I
bdc = C (5.7.6)
IB
Any increase in the base current might shift the Q-point along the load line towards the saturation
region. This allows VCE to fall suddenly below few tenths of a volt (0.2 V) and IC increases rapidly to
saturation. In such circumstances, almost whole VCC is dropped across the load RL. This means collector
terminal becomes less positive than the base terminal. In such a condition, collector base junction is
forward biased like the emitter-base junction which was already forward biased. Thus, both junctions
are forward biased (special case of saturation region).
The VBE can be adjusted to any value by adjusting the variable dc voltage connected between the base
and emitter of the transistor. For each value of VBE, the IC VCE characteristics is plotted as shown in
Fig. 5.16.
For very low value (fraction of a volt) of VBE, the collector voltage drops below the base voltage and
the transistor enters into the saturation region leaving the active region. If we closely observe the
characteristics shown in Fig. 5.16 then we find that each characteristic has certain slope. If these slopes
are extrapolated, they meet at a point on the negative value of VCE i.e. VCE = VA. This voltage VA is
called the Early voltage that falls in the range of 50 V to 100 V.
&"
Fig. 5.16 IC – VCE Characteristics with VBE as a parameter

The linear dependence of IC on VCE can be accounted for by assuming that IS remains constant and
including this factor in the equation for IC results in
Ê V ˆ
IC = IS expVBE /VT Á1 + CE ˜ = IS expVBE /VT (5.7.7)
Ë VA ¯
∂I C VA V
= expVBE /VT ∂VCE , = VBE / VT
= A (5.7.8)
∂VCE VBE = K ∂I C I S exp IC
We know that for a given value of VBE , increasing value of VCE increases the reverse bias voltage on the
collector-base junction and thus increases the base width of the depletion region. This reduces the
effective base-width W of the transistor. We also know from (5.11.4) that IS is inversely proportional
W. The increase in IS increases IC also.
The IC in Eqn. 5.7.8 corresponds to the constant value of VBE near the boundary of the active region.
It is rarely necessary to include the dependence of IC on VCE in dc bias design. However, finite output
resistance ro can have significant effect on the gain of transistor amplifier.
5.8 DC Load Line

We know that the BJT must have a load resistance in order to develop a useful output. The distribution
of the external dc voltage VCC across the ,load resistance and across the transistor can be obtained
graphically by plotting the dc load line on the output characteristics of the BJT as indicated in
Fig. 5.16
Let us again consider the amplifier circuit in Fig. 5.13. There is no signal connected in this figure. This
condition is known as quiescent condition, because there is no instantaneous change in its current and
voltage values. Both voltage and current are static, i.e. dc. Applying KVL in the output loop of Fig. 5.13
yields
VCC = RLIC + VCE
VCC VCE
IC = (5.8.1)
RL RL
Since VCC and RL are fixed, VCC /RL is also a fixed quantity. Hence it can be simulated as an equation of
a straight line and which is known as the load line.
&#
y = mx + C (5.8.2)
where, y = IC, and x = VCE
m = 1/RL = slope of the line
C = intercept at y-axis
Figure 5.16 dc load line of CE

The load line can be plotted on the static V-I characteristic shown in Fig. 5.16 obtaining the intercepts
on both current (y-axis) and voltage (x-axis) axes as
For IC = 0, VCE = VCC. This is a point on the x-axis.
For VCE = 0, IC= VCC / RL. This indicates a point on the y-axis.
These two points can be joined by a line called load line as shown in Fig. 5.16.
If dc base current is known, then distribution of VCC across RL and across the transistor can be
obtained very easily from the load line plot.
Example 5.1
For the output characteristic shown in Fig. 5.16, if the base current IBQ = 30 mA, the Q-point collector
current ICQ = 3 mA for RL = 2 K and VCC = 12 V. Obtain the maximum permissible swing.
Solution:
The quiescent point in Fig. 5.16 is defined as
ICQ = 3 mA, and IBQ = 30 mA
The voltage drop across the load line =RLICQ = 3mA ¥ 2K = 6 V
VCE = 12V 6 V = 6 V.
Hence, Q-point is defined as VCE = 6V, ICQ = 3mA, and IBQ = 30mA. This value of the Q-point
allows maximum symmetrical swing of the input current (base current) and the output voltage (collec-
tor to emitter voltage).
&$
5.9 Ebers-Moll Model

The Ebers-Moll model is a low frequency static model of the BJT based on two p-n junctions connected
back-to-back. The terminal currents of the Ebers-Moll model are shown in Fig. 5.17.
The model consists of two diodes and two controlled current sources. The diode currents IF and IR
are expressed as
Ê V ˆ VFG
IF = IES Á exp BE 1˜ and IR = ICS exp BC - 1
IJ (5.9.1)
Ë VT ¯ H
VT K
where IES and ICS are reverse saturation currents of the two diodes and IF and IR are forward and
reverse mode currents. Since, collector-base is larger in area than emitter-base, the collector-base
saturation current ICS is larger than emitter-base saturation current IES (ICS > IES) by a factor of 2 to 50.
Figure 5.17 BJT symbol and its Ebers-Moll model
A part of the emitter diode IF current appears at the collector as aFIF current source. Similarly, a part
of the collector diode current IR appears at the emitter as aRIR current source in the inverse active mode.
In the inverse active mode, the collector region works as the emitter and the emitter region works as the
collector. Normally inverse current amplification ratio aR is very small 0.02 to 0.5. In inverse active
mode the emitter-base junction is reverse biased and the collector-base junction is forward biased.
Now we can express terminal currents as
IE + aRIR IF = 0, and (5.9.2)
IC + IR aFIF = 0 (5.9.3)
Then IB = IE IC = IF aRIR (IR + aFIF) = (1 aF)IF + (1 aR)IR (5.9.4)
Now, we define the forward and inverse current ratios as
IC I IC I /I aF
aF = and bF = C = = C E = (5.9.5)
IE IB IE IC 1 IC / I E 1 a F
IE I IE I E / IC aR
aR = and bR = E = = = (5.9.6)
IC IB IC I E 1 I E / I C 1 a R
&%
A relationship exists between the four parameters of the Ebers-Moll model as

aFIES = aRICS = IS (= 1014A to 1016A) (5.9.7)
Now, substituting Eqns. 5.9.1 in Eqns. 5.9.2 and 5.9.3 yields
IE = IF aRIR = I ES exp
FG V - 1IJ - a I BE
R R
H V K T
F V - 1IJ - a I FG exp V - 1IJ

= I G exp
ES
BE
R CS
BC
(5.9.8)
H V K T H V K T
I F
S V I I FG exp V - 1IJ
BE S BC
= G exp - 1J - a R
a H F V K a H V K
T R T
I F
S V I F V - 1IJ
BE BC
= G exp - 1J - I G exp S
a H F V K H V K
T T
=
b1 + b gI FG exp V - 1IJ - I FG exp V - 1IJ
F S BE
S
BC
(5.9.9)
b F H V K H V K T T
IC = I + a I = a I G exp
R F F
F V - 1IJ - I
F ES
BE
R
H V K T
F V - 1IJ - I FG exp V - 1IJ

= a I G exp
F ES
BE
CS
BC
H V K H V K T T
I F S V I I FG exp V - 1IJ
BE S BC
= a F G exp - 1J -
a H F V K a H V K T R T
F V - 1IJ - I FG exp V - 1IJ

= I G exp
S
BE S BC
H V K a H V K T R T
F V - 1IJ - I b1 + b g FG exp V - 1IJ

= I G exp
S
BE S R BC
(5.9.10)
H V K b H V K T R T
IB = IE IC
=
b1 + b gI FG exp V - 1IJ - I FG exp V - 1IJ - I FG exp V
F S BE
S
BC
S
BE IJ
-1 +
b
IS 1 + b R g FG exp V
BC IJ
-1
bF H V K H V K H V
T T T K bR H V T K
I F
S V BE I I FG exp V - 1IJ
S BC
IB = G exp - 1J + (5.9.11)
b H
F V T K b H V K R T
where, bF is normally very large and bR is very low.

&&
5.9.1 Normal Active Mode

In the normal active mode, the emitter-base junction is forward biased and the collector-base junction is
reverse biased. Also VBC >> VT, the exponential term containing these becomes negligible and hence
Eqn. 5.9.9 through 5.9.11 reduces to
IE =
b1 + b gI FG exp V - 1IJ + I = b1 + b gI FG exp V IJ I
F S BE
S
F S BE S
(5.9.12)
b F H V K T b H VK b F T F
IC
F V - 1IJ + I b1 + b g = I FG exp V IJ + I
= I G exp
S
BE S R
S
BE S
(5.9.13)
H V K b T H VK b
R T R
IB =
b1 + b gI FG exp V IJ - I I FG exp V IJ - I
F S BE S
S
BE S
b F H VK b H VK b T F T R
=G
F I IJ exp V - I FG 1 + 1 IJ
S BE
S (5.9.14)
Hb K V Hb b K
F T F R
5.9.2 Saturation Mode

In saturation mode, both junctions are forward biased. Thus, VBE and VBC are positive and their values
are much greater than 1. So Eqns. 5.9.10 and 5.9.11 reduce to
Ê V ˆ I (1 + b R ) Ê V ˆ I
IC = I S Á exp BE ˜ S Á exp BC ˜ + S (5.9.15)
Ë VT ¯ b R Ë VT ¯ b R
and IB =
IS FG
V I IJ
V
exp BE + S exp BC
FG IJ (5.9.16)
bF HVT bR K
VT H K
Now, from Eqns. 5.9.15 and 5.9.16,
IC = b forced IB
Ê V ˆ I (1 + b R ) Ê V ˆ Êb I ˆ V Êb I ˆ V
I s Á exp BE ˜ s Á exp BC ˜ = Á forced S ˜ exp BE + Á forced S ˜ exp BC
Ë VT ¯ bR Ë VT ¯ Ë b F ¯ VT Ë bR ¯ VT
Figures 5.18 and 5.19 show the circuit of BJT in the normal saturation and inverse active modes.
Figure 5.18 BJT in normal saturation mode Figure 5.19 BJT in inverse active mode
&'
VBE Ê bforced ˆ Êb 1+ b R ˆ V
IS exp Á 1 ˜ = Á forced + ˜ I S exp BC
VT Ë bF ¯ Ë bR bR ¯ VT
Ê b F b forced ˆ V Êb + 1+ b R ˆ VBC
ÁË ˜ exp BE = Á forced ˜¯ exp V
bF ¯ VT Ë bR T
VBE V V VBC Ê b forced + 1 + b R ˆ Ê bF ˆ Ê 1+ (b forced + 1) / b R ˆ

exp / exp BC = exp BE Á ˜ Á ˜ = Á
VT VT VT Ë bR ¯ Ë b F bforced ¯ Ë 1 b forced / b F ˜¯
1 + (bforced + 1) / b R
VBE VBC = VT In (5.9.18)
1 b forced / b F
1 + (bforced + 1) / b R
VCE(sat) = VBE VBC = VT In (5.9.19)
1 b forced / b F
The typical values of VCE(sat) = 0.2 V.
The plot of VCE(SAT) against current amplification factor b is drawn in Fig. 5.20. The value VCE(SAT)
becomes infinity at bforced = bF.
Figure 5.20 Plot of VCE(SAT) versus b
Inverse Active Mode

The role of emitter and collector is interchanged in the inverse active mode and the transistor has very
low value of inverse current amplification factor bR (0.1) as depicted in Fig. 5.19. Here, iC = I2 and iE
= I1.
5.10 Charge Control Model of BJT

In order to obtain different current components of a BJT, we take the help of p-n junction described in
Chapter 2. Fig. 5.21 shows the equilibrium concentration of holes and electrons with their relative
positions in an n-p-n transistor.
'
Figure 5.21 Equilibrium of concentration of charge carriers
The distances xe, xb, and xc have been shown from the edge of the depletion region. The base width
is Wb, but Wbn is the effective base width. Normally we assume that Wb = Wbn. Here nbo, peo , and pco are
minority carrier equilibrium densities. We assume that the emitter and collector regions are longer than
the hole diffusion lengths Lp so that the hole densities decrease exponentially away from the base region.
Normally peo is very small as it is highly doped w.r.t. the other regions.
The concentration of electrons in the base region can be obtained by solving the continuity equation
as in Article 2.7. The continuity equation for electrons in the base region is written as
d 2dnb ( x b ) dnb ( xb )
- = 0 (5.10.1)
dx 2 L2b
If we make an assumption that the injected minority charge carriers (n-type) in the p-type base region
decays linearly from its value at xb = 0 to its value xb = Wbn, the solution becomes easy. This assumption
is reasonable as the base width is small compared to the diffusion length Lb >> LWn.
The solution of Eqn. (5.10.1) can be obtained by writing the complementary function as
FG D 2
-
1 IJ
dnb ( x ) = 0
H L2b K
or dnb(xb) = B exp
FG x IJ + C expFG - x IJ
b b
(5.10.2)
HL K
b H LK b
Boundary conditions are defined as
d nb(xb = 0) = excess electron density on the base side of EBJ = nbo exp
FG VBE IJ
1 = DnE (5.10.3)
H yT K
d nb(xb = Wb) = excess electron density on the base side of CBJ = nbo exp
FG VCB IJ
1 = DnC (5.10.4)
H yT K
d pe(xe = 0) = excess hole density on the emitter side of EBJ = peo exp
FG VBE IJ
1 = DpE (5.10.5)
H yT K
d pc(xc = 0) = excess hole density on the collector side of CBJ = pco exp
FG -VCB
- 1 = DpC
IJ (5.10.6)
H yT K
'
Substituting Eqn. 5.10.3 and 5.10.4 in Eqn. 5.10.2 yields
dnb ( x b = 0) = B + C = nbo exp

FG VBE IJ
- 1 = DnE, (5.10.7)
H yT K
and d nb ( xb = Wb ) = B exp
FG W IJ + C expFG - W IJ = n FG exp -V
b b
bo
CB IJ
- 1 = DnC (5.10.8)
HL K
b H LK H y b T K
or B = DnE C
or (DnE - C) exp
FG W IJ + C expFG - W IJ = Dn
b b
E exp
FG W IJ - C expFG W IJ + C expFG - W IJ = Dn
b b b
C
HL K
b H LK b HL K b HL K bH LK b
ÊW ˆ ÏÔ ÊW ˆ Ê W ˆ ¸Ô
or DnE exp Á b ˜ - C Ìexp Á b ˜ - exp Á - b ˜ ˝ = DnC
Ë Lb ¯ ÓÔ Ë Lb ¯ Ë Lb ¯ ˛Ô
DnE exp(Wb / Lb ) - DnC
or C= (5.10.9)
exp(Wb / Lb ) - exp(-Wb / Lb )
DnE exp(Wb / Lb ) - DnC
Hence, B = DnE C = DnE
exp(Wb / Lb ) - exp(- Wb / Lb )
DnC - DnE exp( - Wb / Lb )
= (5.10.10)
exp( Wb / Lb ) - exp( - Wb / Lb )
Hence, d nb ( xb ) = B exp
FG x IJ + C expFG - x IJ
b b
HL K
b H LK b
DnC - DnE exp( - Wb / Lb ) x DnE exp(Wb / Lb ) - DnC -x

= exp b + exp b
exp (Wb / Lb ) - exp(- Wb / Lb ) Lb exp (Wb / Lb ) - exp (- Wb / Lb ) Lb
exp(Wb - xb ) / Lb - exp - (Wb - xb ) / Lb exp( xb / Lb ) - exp(- xb / Lb )
= DnE + DnC
exp(Wb / Lb ) - exp(- Wb / Lb ) exp(Wb / Lb ) - exp(- Wb / Lb )
sin h (Wb - xb ) / Lb sin h ( xb / Lb )
= DnE + DnC (5.10.11)
sin h (Wb / Lb ) sin h (Wb / Lb )
For the area of cross section of the device = A and diffusion coefficients DB and DE in the base and
emitter, then diffusion currents in two-regions are described as
dd nb ( xb )
IEn = InEB = qADB (5.10.12)
dxb x b =0
dd pe ( xe )
IEp = I pEB = - qADE (5.10.13)
dxe x b =0
Using Eqns. 5.10.13 and 5.10.2 at Xb = 0 yields

'
qADB x
I nEB =
B exp b - C exp - b =
x qADB FG IJ
(B C)
FG IJ
(5.10.14)
Lb Lb Lb Lb H K H K
Substituting the value of B and C from Eqns. 5.10.10 and 5.10.9 in Eqn. 5.10.14 results in
qADB
InEB = (B C)
Lb
=
qADB RS
DnC - DnE exp(- Wb / Lb ) UV
Lb exp(Wb / Lb ) - exp(- Wb / Lb )
T W
qADB RS
DnE exp(Wb / Lb ) - DnC UV
Lb exp(Wb / Lb ) - exp( - Wb / Lb )
T W
qADB Ï 2DnC - DnE (expWb / Lb ) + exp(- Wb / Lb ) ¸
= Ì ˝
Lb Ó exp(Wb / Lb ) - exp(- Wb / Lb ) ˛
qADB
=
Lb
l
DnC cosech(Wb / Lb ) - DnE cot h (Wb / Lb ) q (5.10.15)
If we neglect the hole crossing from collector to the base when CBJ is reverse biased, the collector
current IC is entirely due to electrons entering the collector depletion region from the base. Hence, at xb
= wb
IC = I n ( x b = Wb ) =
FG IJqADB FG IJ
W W
B exp b + C exp - b
H K Lb H K
Lb Lb
=
qADB RS Dp - Dp exp(- W / L ) UV expFG W IJ Dp exp(W / L ) - Dp expFG - W IJ
C E b b b E b b C b
Lb T exp(W / L ) - exp(-W / L ) W H L K exp(W / L ) - exp(-W / L ) H L K
b b b b b b b b b b
=
qADB RS Dn - Dn exp(- W / L ) UV expFG W IJ Dn exp(W / L ) - Dn expFG - W IJ
C E b b b E b b C b
Lb T exp(W / L ) - exp(- W / L ) W H L K exp(W / L ) - exp(- W / L ) H L K
b b b b b b b b b b
=
qADB RSDn exp (W / L ) + exp(-W / L ) UV qAD Dn RS
C
b b b b 2 UV
B
E
Lb T exp(W / L ) - exp (-W / L ) W L
b b T exp(W / L ) - exp(-W / L ) W
b b b b b b b
qAD B
=
L
lDn cot h (W / L ) - Dn cosec h (W / L )q
b
C b b E (5.10.16)
b b
For g = 1, IE @ IEn
and IB = IE IC = IEn IC
qADB
=
Lb
l
DnC cosec h (Wb / Lb ) - DnE cot h (Wb / Lb ) q
qADB

Lb
l
DnC cot h (Wb / Lb ) - DnE cosec h (Wb / Lb ) q
qADB
=
Lb
l
( DnC - DnE ) cosec h (Wb / Lb ) - ( DnC - DnE )cot h (Wb / Lb ) q
'!
qADB
=
Lb
l
( DnC - DnE ) cosech (Wb / Lb ) - cot h(Wb / Lb ) q
qADB
=
Lb
l
( DnC - DnE ) cot h (Wb / Lb ) - cosec h (Wb / Lb ) q
qADB
= (DnC - DnE ) tan h (Wb / 2 Lb ) (5.10.17)
Lb
In the normal biasing case, CBJ is reverse biased and hence DnC @ 0. Now Eqns. 5.10.15, 5.10.16,
and 5.10.17 reduce to
qADB qADB L qADB
IE = DnE cot h( Wb / Lb ) = DnE b = DnE
Lb Lb Wb Wb
qADB L qADB
IC = DnE cosec h (Wb / Lb ) = DnE b = DnE
Lb Wb Wb
qADB qADB W D DB
IB = DnE tan h (Wb / 2 Lb ) = DnE b = qAWb DnE B2 = qAWb DnE
Lb Lb 2 Lb 2 Lb 2 DBt b
qAWb DnE
= (5.10.18)
2t b
For Wb/Lb £ 1, the terms of hyperbolic expansions of following functions can be restricted to
e x - e- x x3 x5
sin hx = = x+ + +.....
2 3! 5!
e x + e-x x2 x 4
Cos hx = = x+ + + .....
2 2 ! 4!
x3 1 x x3
tan hx = x - + ... and cot hx = + - + ...
3 x 3 45
x 2 5x 4
Sec hx = 1 - + - ...
2 24
x 7x 3
cosec hx = x - + - ...
6 360
Figure 5.22 Approximate hole distribution for VCB = 0

'"
Since, the electron distribution diagram in the base region looks to be triangular as in Fig. 5.22, we
can assume the approximate equivalent stored charge as
1
Qn =
qADnE Wb (5.10.19)
2
If we assume that the charge must be replaced every tb seconds and that it maintains a relationship
between the recombination and supply of electrons by the base current, then
dQb Q qADnE Wb
IB = = b = (5.10.20)
dt tb 2t b
Eqn. 5.10.20 is exactly the same as Eqn. 5.10.18.
Emitter Injection Efficiency
The emitter emission efficiency is defined as the ratio of electron current (n-p-n) due to injection of
electrons from emitter to the total emitter current. It is mathematically expressed as
I En
ge = (5.10.21)
I En + I Ep
Assuming exponential decay of holes in the emitter region, we can express it as in the case of p-n
junction as
ddp( x ) qDe
IEp = I pBE = - qADe and IEp = - A D pC (5.10.22)
dxe x Le
e =0
I En
Hence, ge = (5.10.23)
I En + I Ep
qADB DnE cot h ( Wb / Lb ) / Lb
=
qADB DnE cot h (Wb / Lb ) / Lb + qADE DpC / Le
DB DnE cot h (Wb / Lb ) / Lb

=
DB DnE cot h (Wb / Lb ) / Lb + DE DpC / Le
1
=
1 + ( DE DpC Lb / DB DnE Le ) / cot h (Wb / Lb )
1
=
1 + ( DE peo Lb / DB nbo Le ) tan h (Wb / Lb )
1 1
= =
1 + ( DE peo Lb / DB nbo Le ) (Wb / Lb ) 1 + DE peo Wb / DB nbo Le
DE peo Wb
@ 1- (5.10.24)
DB nbo Le
'#
For g to be close to unity, Wb << Le and nbo >> peo . Thus, for small base width and heavy emitter doping
compared to the base is essential. Of course, the base width can not be reduced arbitrarily as it will invite
problems of punch through and high base region resistance.
Transport Factor
It is known as the base transport factor. It is the ratio of electron current reaching the CBJ to the current
injected at the EBJ. In the process of travelling through the base region, some of the electrons recombine
and hence this ratio is always less than unity. Mathematically, it is expressed as
IC qADb DnE cosec (Wb / Lb ) / Lb 1
b* = = =
IE qADb Dn E cot h ( Wb / Lb ) / Lb cos h (Wb / Lb )
1 W2
= @ 1 - b2 (5.10.25)
1 + Wb / Lb 2 Lb
Collector Efficiency
It is defined as the ratio of actual electron current that reaches the collector to the base-collector
current. As the CBJ is highly reverse biased, all electrons reaching the collector region is swept away
into the collector terminal and hence, this efficiency is equal to unity.
Current Transfer Ratio
The current transfer ratio a, is defined as the collector current to the emitter current and is expressed as
DE peoWb Ê Wb2 ˆ Wb2

a = gb = 1 - 1 - @ 1 - (nbo >> peo) (5.10.26)
DB nboWe ÁË 2 L2b ˜¯ 2 L2b
DE peo Wb
= 1- (Wb << Lb) (5.10.27)
DB nbo We
a 1 - Wb2 / 2 L2b 2 L2b - Wb2 2 L2b
b= = = @ (nbo >> peo) (5.10.28)
1- a 1 - 1 + Wb2 / 2 L2b Wb2 Wb2
1 - DE peo Wb / DB nbo We D n L - DE peo Wb
= = B bo e
1 - 1 + DE peo Wb / DB nbo We DE peo Wb
DB nbo Le
= (Wb << Lb) (5.10.29)
DE peo Wb
5.11 Approximate Analysis of Current Flow in BJT

The total current flow in BJT consists of two components:
∑ Diffusion current
∑ Drift current
'$
Since, the drift current is due to the thermally generated minority carriers, it is very small and neglected.
The forward biased emitter-base junction has two components of currents due to
∑ electrons injected from emitter into the base, and
∑ holes injected from base to emitter.
It is desirable to have the 1st component (injected electrons from emitter) much higher than the 2nd
component (injected holes from base to emitter). Heavy doping of emitter and low doping of base
accomplish it in the manufacturing. Thus, electron density in the emitter region is high and hole density
in the base is low.
Let us assume that electrons injected into the very thin base region under forward bias condition. The
excess minority charge carriers (electrons) in (p-type) thin base form a straight-line concentration
gradient as indicated in Fig. 5.23.
The injected electron concentration in the base region will be highest [np (0)] at the base side and lowest
(zero) at the collector side. The reason for zero concentration at the collector side of the base is that
positive voltage across base-collector junction sweeps away the electrons as soon as they arrive there.
The concentration is proportional to the forward bias and is expressed as
n p (0) = n po expVBE / VT (5.11.1)

where, npo is the thermal equilibrium of the minority carriers (electrons) in the base region.
The diffusion current is is proportional to the concentration gradient i.e. slope in the base i.e.
dn p ( X )
In = Dn qAE (5.11.2)
ax
where, AE is the cross sectional area of the base-emitter junction.
Figure 5.23 Minority carrier profile in the base collector current

'%
Collector Current
The collector current can be expressed as
IC = IS expVBE / VT (5.11.3)
Dn qAE n p0
where, IS = = ( npo = n2i) (5.11.4)
W
Typical value of IS falls in the range of 10l2 A to 10l5A. It doubles every 5°C rise in the temperature.
Base Current
The base current also has two components :
∑ IB1 is the component due to injected holes from base-to-emitter, and
∑ IB2 is the component that flows on account of holes that have to be supplied from the battery to
replace the lost holes in the base due to recombination.
D pqAEni2 Qn
Thus, IB1 = and IB2 = .
Lp N D tn
where, Qn is the minority charge in the base that recombines in t n seconds then
Qn 1 1
IB2 = Qn = area of the triangle = n p (0)WqAE = npo WqAE expVBE / VT
tn 2 2
1 ni2
= WqAE expVBE / VT (5.11.5)
2 NA
Qn 1 ni2
Hence, IB2 = = WqAE expVBE / VT (5.11.6)
tn 2 N At n
D pqAE ni2 1 ni2

Now, total base current = IB = IB1 + IB2 = expVBE / VT + WqAE expVBE / VT (5.11.7)
Lp N D 2 N At n
D p qAE ni2 Ê D p N A W 1 W 2 ˆ VBE / VT

Ê Dp N A W 1 W 2 ˆ VBE / VT
= Á ˜ exp = IS Á ˜ exp
WN A Ë Dn N D Lp 2 Dnt n ¯ D N
Ë n D p L 2 D t
n n¯
1
I Ê Dp N A W 1 W 2 ˆ
Hence, b= C = Á + ˜ (5.11.8)
IB Ë Dn N D L p 2 Dnt n ¯
Emitter current = IE = (b + 1)IB (5.11.9)
'&
1. The collector and base currents of BC107 amplification ratio in CB and CE configu-
transistor are 5 mA and 50 mA respec- rations.
tively. If current amplification factor in
Solution:
common base configuration is 98%, cal-
culate the value of collector leakage cur- IE = (1 + b ) I B + (1 + b ) I CO @ (1 + b ) I B
rent in CE and CB configurations.
= (1 + b )1 mA = 100 mA
Solution:
1 + b = 101
a
a = 0.98, b = = 49, b = 100
1a
The current amplification ratio in CE = b
IC = bI B + (1 + b ) I CO = bI B + I CEO = 100
= 49 ¥ 0.05 mA + ICEO = 2.45 mA + ICEO The current amplification ratio in CB is = a
and it is expressed as
ICEO = (5 2.45) mA = 2.55 mA
b 100
I a= = = 0.990099 = 0.99
ICO = CEO = 0.051 mA 1+ b 101
1+ b
5. A p-n-p transistor shown in Fig. 5.24 has
2. Determine the resulting change in emitter uniform doping in the emitter, base and
current for a change in the collector cur- collector regions wherein the doping con-
rent of 2 mA with its a = 0.98. centrations are 1025/m3, 1023/m3 and 1021/
Solution: m3 respectively. The minority carrier dif-
fusion length in emitter and the base re-
IC = aIE + ICO
gions are 5 microns and 100 microns re-
DIC = aDIE spectively. Assuming low level injection
DIC 2 mA conditions and using law of junction, cal-
DIE = = = 2.04 mA culate the collector current density and the
0.98 0.98
base current density due to base recombi-
3. Obtain IC, b, and ICEO in case a BJT hav- nation. Assume Dp = 8 × 104 m2/sec,
ing IE = 10 mA, ICO= 0.5 mA, and a =0.98. Dn = 10 × 104 m2/sec, ni = 1.5 × 1016/m3,
Solution: KT/q = 0.026 V, q = 1.6 × 1019 C.
b = 49, Solution:
IC = aIE + ICO Minority carriers at the entry point of base
VEB
= (0.98 ¥ 10 + 0.5 ¥ 103) mA = 9.8 mA VT
region = pn(o) = pn exp
ICEO = (1 + b)ICO = 50 ¥ 0.5 ¥ 106
0.78
= 25 mA = pn exp 0.026 = 2.25 × 109 exp30
4. If IB and IC of any BJT are 1mA and = 2.25 × 109 × 1.069 × 1013
100 mA respectively, determine its current = 2.4 × 1022/m3
''
Gradient of charge (hole) diffusion Base current due to recombination

qDp pn (o) Excess holes
= =
Wb Minority life time t p
1.6 ¥ 10 -19 ¥ 8 ¥ 10 -4 ¥ 2.4 ¥ 10 22 L2p (100 ¥ 10-6 ) 2

= tp = =
5 ¥ 10 -6 Dp 8 ¥ 10 4
5
30.72 ¥ 10
= = 12.5 ¥ 106 sec
5
= 6.144 × 105 A/m2 pn (o) ¥ Wb ¥ q
IB =
2t p
Figure 5.24
2.4 ¥ 10 22 ¥ 5 ¥ 10 -6 ¥ 1.6 ¥ 10 -19 = 0.026 × ln 5 × 1012 = 0.026 × 29.23

=
2 ¥ 12.5 ¥ 10 -6 = 0.76 V
= 0768 ¥ 103 A/m2 7. A BJT has been specified with maximum
6. If the quiescent collector current of an and minimum value of current amplifica-
n-p-n transistor for the base-emitter volt- tion factor as bmax = 150 and bmin = 50.
age VBE = 0.7 V is IC = 1 mA, what would Calculate the range of values of a.
be the new value of VBE at IC = 0.1 mA Solution:
and IC = 10 mA ?
β 150 50
Solution: amax = = = 0.9934, amin =
1+ β 151 51
IC = I S expVBE /VT , 1 = ISexp0.7/0.026 = 0.988
= ISexp26.923 = 4.93 × 011IS, 8. The base and emitter currents of an n-p-n
transistor are 0.0145 mA and 1.45 mA for
IS = 2 × 1015A VBE = 0.7 V. Calculate the values of a, b,
and IS.
IC = I S expVBE /VT = 2 × 10−15 expVB / 0.026
Solution:
3 VB / 0.026 12
= 0.1 × 10 , exp = 0.05 × 10 , I C = I E I B = (1.45 0.0145) mA
= 1.44 mA,
VBE = 0.026 × 24.6353 = 0.64 V and VBE
(10 mA) IC 1.44
a= = = 0.99,
IE 145
.

IC 144
. cation factor bmin = 50, and bmax = 150.
= = 99 Obtain the value of resistor that can pre-
IE 0.0145
vent collector voltage falling below 8 V.
IC = I S expVBE /VT = I S exp 0.7 / 0.026
Solution:
0.7 / 0.026
= I S exp The maximum leakage current ICEO
= I S exp 26.923 = I S × 4.93 × 1011 , = (1 + b)ICO = 151 × 2 mA= 302 mA

RCIC = 12 VCE = 12 8 = 4 V,
1.44 mA ¥ 10-11
IS = = 0.293 × 1014 4000
4.93 RC = = 13.3 KW
302
= 2.93 × 1015 A
9. Calculate the values of current amplifica-
tion factor (b) of two different transistors
having a1 = 0.99 and a2 = 0.98 and emitter
currents of both being 10 mA. Calculate its
base currents also.
Solution: Figure 5.25
α1 0.99
b1 = = = 99, 12. What is the minimum base current re-
1 − α1 1 − 0.99 quired so that the transistor shown in Fig.
α2 0.98 5.26 enters the saturation region. The tran-
b2 = = = 49,
1− α 2 1 − 0.98 sistor parameters at room temperature are
a = 0.98, ICO = 2 mA, IEO= 1.6 mA.
10
IB1 = = 0.1 mA, Solution:
1 + 99
When emitter-base junction is forward bi-
10
IB1 = = 0.2 mA ased in the CE configuration, the collector-
1 + 49 emitter junction is reverse biased for ac-
10. Calculate the value of the base-emitter volt- tive region. For saturation to occur the col-
age (VBE) for an N-P-N transistor having b lector emitter junction is also forward bi-
= 100, IC = 1mA, and IS = 1011A. ased i.e. VCE = 0.
Solution: VBE = VCE = 0, VCC = RC IC + VCE,
−11 VBE / 0.026
1.5 mA = 10 exp , 0.98
b= = 49
1 − 0.98
expVBE / 0.026 = 1.5 × 108,
VCC − VCE 12
IC = = = 3 mA,
VBE = 0.026ln 1.5 ×108 RC 4K
= 0.026 × 18.826 = 0.5 V IC 3
IB = = = 0.0612244 mA
11. The BJT in the circuit of Fig. 5.25 has β 49
maximum ICO = 2 mA and current amplifi- As IEO = 1.6 mA < IC = 3 mA.

I C − I EO qADn
Strictly, IC IEO = bIB, IB = IB = ∆nE tanh(Wb / 2 Ln )
β Ln
3 − 0.0016 qADn W qADn W
= = 0.061191 mA = ∆n E b = ∆nE b
49 Ln 2 Ln Dnτ n 2
qAWb
= ∆nE
2τ n
. × 10−19 × 10−5 × 2 × 10−4 × 35
16 . × 1015
=
2 × 10 −7
= 5.6 × 106A
Figure 5.26
13. An n+pn+ transistor having base width WB

= 2 × 104 cm, and an emitter area Ae =
105cm2 is connected in the circuit of Fig.
5.27. The electrons in the base region have
lifetime tn= 107 sec and diffusion constant
Dn = 36 cm2/sec. Assume that the transis-
tor characteristics are completely con-
trolled by the parameters of the base re- Figure 5.27
gion in which low-level condition prevails
14. The parameters of a typical N-P-N transis-
and that the base to emitter voltage is ap-
tor shown in Fig. 5.28 are WC = 20 mm,
proximately 0.7 V. Calculate the base cur-
collector doping = 5 × 1018/cm3, WE =
rent IB determining the electron concentra-
1mm, emitter doping = 1019/cm3, base
tion neo in the base at the emitter side of the
doping = 5 × 1015/cm3, and minority car-
junction.
rier lifetime in the base region is tn = 0.5
Solution: ms. Under punch through the VBC = 10 V +
5.7 - 0.7 fo volts. Here fo is the bult-in voltage of
IE = = 1 mA base-collector junction. The emitter injec-
5K
tion efficiency can be assumed as 1 for
qADB this transistor. Obtain the base width WB
IE = DnE Cot h(Wb / Ln)
Ln and the current amplification factor. Given
Dn = 30 cm2/sec, eSeo = 1012 F/m, ni = 1.5
qADB L
= ∆nE n × 1010/cm3.
Ln Wb
Solution:
WI 2 × 10−4 × 10 −3
DnE = b E = KT N A N D
qADn . × 10 −19 × 10 −5 × 36
16 fo = ln
q ni2
= 0.035 × 1017 = 3.5 × 1015/cm3
5 × 1015 × 5 × 1018
I En DE peoWb = 0.025 ln
ge = 1− . 2 × 1020
15
I En + I Ep DB nbo Le

25 × 1013 Punch through voltage = VPT = 10 + 0.81

= 0.025 ln = 10.81 V = 7.67 × 1016NCW2
2.25
= 0.025(2.4 + 13 × 2.3) Here, NC = concentration of lighter region
= 0.025(2.4 + 29.93) = 0.025(32.33) 5 × 1015/cm3< 5 × 1018/cm3
= 0.81 V
Figure 5.28
−16 2
10.81 V = 7.67 × 10 N CW 6 − x2 6 L2n − WB2
= =
( 3 + x 2 ) 2 ( 3 L2n + WB2 ) 2
10.81
= 7.67 × 10−16 × 5 × 1015 W 2 , W2 =
3835
. 6 ¥ 15 ¥ 10 -6 - 2.82 ¥ 10 -12
=
= 2.819, W = 1.68mm 2(3 ¥ 15 ¥ 10 -6 + 2.82 ¥ 10 -12 )
IC 89.99
Current amplification factor = a = = = 0.99
IE 90
15. The BJT used in the circuit of Fig. 5.29
DnB W W has ICBO = 2 mA at room temperature
qA n pB Co sec h B Co sec h B
LnB Ln Ln i.e. 25°C and doubles every 10°C rise in
= = the temperature. What is the maximum
D W W
qA nB n pB Cot B Cot B value of allowable RB to keep the BJT in
LnB Ln Ln
cut-off state at 75°C? Given VBE(CUT_OFF)
1 x 6 − x2 = 0.1 V.
Cosec hx = − +.. = , Solution:
x 6 6x
The leakage current at 75°C = 2 mA × 25
1 x 3 + x2 = 64 mA
Cothx = + +.. =
x 3 3x 5 V + VBE = RBICBO = 64mARB
. )106
(5 − 01
Ln = Dnτ n = 30 ¥ 0.5 ¥ 10-6 or, RB = = 76.7 KW
64
= 15 ¥ 10-6 = 3.873 ¥ 10-3 cm
WB
Co sec h
IC Ln (6 − x 2 ) / 6x
a= = =
IE W ( 3 + x 2 ) / 3x
Cot B
Ln
Figure 5.29
!
16. What will be the maximum temperature in 19. What would be the value of leakage cur-
Problem 15 to bring the BJT out of cut-off rent of a transistor at 75°C, if the leakage
region, if the VBB is set to 1 V with RB = current is ICBO = 15 nA at 25°C ?
50 KW? Solution:
Solution:
ICO1 = I CO exp K2t1 ,
1 V + VBE = RBICBO = 50KICBO,
ICO2 = I CO exp K2t2 ,
1 V - 0.1 0.9 V
ICBO = = = 0.018 mA
50 K 50 K I CO 2
= exp K2 ( t2 − t1 ) ,
I CO1
18 = 2 × 2(t25)/10, 2(t25)/10 = 9,
ICO2 = I CO1 exp K2 ( t2 − t1 )
t − 25
= log29 = 3.2, t = 32 + 25 = 57°C
10 ICO2 = 15 nAexp 0.07¥50
17. Show that if very small per unit change in
∆α = 15 nAexp 3.5 = 15 × 109 × 33.12
a is given as , then the corresponding
α = 0.5 × 106 A
∆β 20. Accidentally the emitter and collector leads
per unit change in b is expressed as =
β of an npn transistor have been connected
in the inverse mode. The resulting emitter
∆α
(1 + β ) . and base currents from this configuration
α are 5 mA and 1 mA. What would be the
Solution: value of aR and bR2?
β b
∂β 1 + β β∂βg Solution:
a= , ∂α =
1+ β 1+ β b2
g IC I 5
bR = = 5, aR = C = = 0.833
IB IE 5+1
∂β ∂α ∂β (1 + β )
= , = 21. An npn transistor has VBE = 0.8 V and col-
(1 + β ) 2 α (1 + β ) 2 β lector current of 1 A. What would be the
value of VBE for IC = 10 mA and 5 A?
∂β ∂β ∂α
= , = (1 + β ) . Solution:
b g
1+ β β β α
IC = I S expVBE /VT = 1 A
18. If a changes by 0.1%, what would be the
∂β = I S exp 0.8/ 0.026 = I S exp 30.76923
value of for b = 100 ?
β
= 2.3 × 1013 I S , IS = 4.34 × 1014 A
Solution:
∂β 10 mA = 4.34 × 10−14 expVBE / 0.026
= 100 × 0.1% = 10.1%
β expVBE / 0.026 = 2.3 × 1011
"
VBE = 0.026 × 26.16 = 0.68 V 25. The area of emitter-base junction of an

n-p-n transistor is 10 mm ¥ 5 mm with the
5 × 1014 doping concentration in the emitter ND =
expVBE / 0.026 = = 1.152 × 1014,
4.34 1019/cm3, in the base NA = 1017/cm3, in the
VBE = 0.026 ln(1.152 × 1014) collector ND = 1015/cm3, ni = 1.5 ¥ 1010
cm3 at 300 K. The diffusing electrons in
= 0.026 × 32.38 = 0.842 V
the base has Dn = 21.3 cm2/s and Ln =
22. The collector current of a BJT is 12 mA 19 ¥ 10 4cm. For holes diffusing in the
for VBE = 0.7 V. What would be the collec- emitter has Dp = 1.7cm2/s and Lp = 0.6 ¥
tor current if VBE is reduced to 0.5 V ? 104cm. Calculate IS and b for base width
Solution: (a) 1 mm and (b) 5 mm.
IC = I S expVBE /VT = 12 mA = I S exp 0.7 / 0.026 Solution:
= I S exp 26.923 = I S × 4.93 × 1011 qDn AE ni2
IS =
N AW
12 × 10 14
IS = = 2.44 × 10−14 A ,
4.93 1.6 ¥10 -19 ¥ 21.3 ¥ 50 ¥10 -8 ¥2.25 ¥10 20
−14 0.5/ 0.026 =
IC = 2.44 × 10 exp 1017 ¥ W
= 2.44 × 10−14 exp19.23 1.6 ¥ 21.3 ¥ 50 ¥ 2.25 ¥ 10 -7
=
= 2.44 × 10−14 × 2.25 × 108 1017 ¥ W
= 5.48 × 10−6 A 1.6 ¥ 21.3 ¥ 50 ¥ 2.25 ¥ 10-24
23. What would be the output resistance at =
W
collector current of 1mA of a BJT having
Early voltage of 200 V ? 3834 ¥ 10-24
=
Solution: W
V 200 3834 ¥ 10-24
ro = λ = = 200 KW. IS (W = 1mm) =
IC 1 mA 10-4
24. For a p-n-p transistor with IS = 1014A and = 3.834 ¥ 1017 A,
b = 100, calculate IC, IB, and IE for VEB = 3834 ¥ 10-24
0.7 V and VCB £ 0. IS (W = 5mm) =
5 ¥ 10-4
Solution:
= 0.7668 ¥ 1017A.
VBE /VT −14 0.7 / 0.026
IC = I S exp = 10 exp
1
b=
= 10 −14
exp 26.923 Dp N A W 1 W 2
+
Dn N D Lp 2 Dnt n
= 10 −14 × 4.93 × 1011 = 4.93 × 10−3 A
1
=
4.93 × 10 A −3 Dp N A W 1 W2
IB = = 0.0493 × 10 −3 A +
100 Dn N D Lp 2 L2n
#
1 1017
= = 0.026 ln = 0.0261n(0.52 ¥ 1017)
1.7 10 W ¥ 10 4 1
17
W2 1917
.
+
21.3 1019 0.6 2 361 ¥ 10 -8 = 0.026 ¥ 38.493 = 1 V
1 1 qAEWni2 1 qAEWni2 I C
= Qn = expVB /VT =
0.133 ¥ 10 W + 1.385 ¥ 105 W2
2
2 NA 2 N A IS
2
b (W = 5 mm) 1 qAEWni N AW 1 W2
= IC = IC
1 2 NA qDn AE ni2 2 Dn
= -2
0133
. ¥ 10 + 01385
. ¥ 10-2 1 4 ¥ 10-8
= ¥ 10-3 = 0.094 ¥ 1011
1 2 213 .
= = 368
0.272 ¥ 10-2 = 0.94 pC
b (W = 5 mm) 27. Two BJTs of different junction areas, fab-
ricated using the same technology, oper-
1 ated at VBE = 0.7 V yield collector currents
= -2
0133
. ¥ 10 ¥ 5 + 01385
. ¥ 10-2 ¥ 25 of 0.13 mA and 10.9 mA. Obtain IS for
each device. What is the relative junction
1 area?
= = 24.2
( 0.665 + 3.4625)10-2
IC1 = IS1 expVBE / VT = IS1exp0.7/0.026
26. Obtain IE, IB, VBE, and the minority charge = IS1exp26.923 = 4.9262 ¥ 1011IS1
stored in the base in above problem if W = . ¥ 10-3
013 . ¥ 10-14
013
2 mm, and IC = 1 mA. IS1 = =
4.9262 ¥ 1011 4.9262
Solution:
10.9 ¥ 10-3
3834 ¥ 10 -24 -24 = 0.0264 ¥ 1014 A, IS2 =
3834 ¥ 10 4.9262 ¥ 1011
IS = =
W 2 ¥ 10-4 = 2.213 ¥ 1014 A,
20
= 1.917 ¥ 10 A,
IS 2
b(W = 2 mm) Relative junction area =
I S1
1
= 2.213 ¥ 10-14 A
0133
. ¥ 10-2 ¥ 2 + 01385
. ¥ 4 ¥ 10-2 = = 83.8
0.0264 ¥ 10 -14 A
1 100
= -2
= = 122 28. The collector current of an n-p-n transis-
( 0.266 + 0.554)10 0.82
tor are 1mA and 10 mA for base-emitter
IC 1mA voltages of 0.63 V and 0.7 V. Obtain cor-
IB = = = 8.197mA, IE = IC + IB
b 122 responding values of h and IS. What is to-
= 1mA + 0.0082 mA = 1.008 mA tal collector current if two such devices
are connected in parallel as in Fig. 5.30 and
IC 10-3
VBE = VT ln = 0.026 ln base emitter voltage VBE = 0.67 V is ap-
IS 1.917 ¥ 10-20 plied across them?
$
IC1 = I S expVBE 1 / hVT and We know that the VBE decreases linearly
with increasing temperature at a rate =
IC2 = I S expVBE 2 / hVT , 2.5 mV/°C.
IC 2 expVBE 2 /hVT Hence, VBE (0°C) = 0.7 V + 0.0025 ¥
= = exp (VBE 2 - VBE 1) / hVT
I C1 expVBE 1 /hVT 25 = 0.7625 V
10 mA VBE (100°C) = 0.7 V 0.0025 ¥ 75
=
1 mA = 0.5125 V
VBE 2 - VBE1 30. The emitter current of an n-p-n transistor
= ln10 = 2.3,
hVT at VBE = 0.7 V and temperature 20°C is
0.5 mA. What would be the value of base-
0.7 - 0.63 0.07
h= = = 1.2 emitter voltage if the junction temperature
2.3 ¥ 0.026 2.3 ¥ 0.026 rises to 50°C ? What emitter current can
IC1 = I S1 expVB /hVT = IS1exp0.7/1.2 ¥ 0.006 flow for VBE = 0.705 V at temperature 20°C
and 100°C ?
26.923
= I S1 exp 1.2 = 5.5432 ¥ 10 9 IS1 Solution:
VBE changes by 0.0025V in 1°C change.
10 ¥ 10-3 Hence, change in VBE (50°C) = 0.7
IS1 = 9
= 1.8 ¥ 1013A, IC1 +
.
5543 ¥ 10 0.0025(50 20) = 0.625 V. At 20°C, IE =
. ¥ 10-13 exp 0.65/1.2¥0.026
IC2 = 2 ¥ 18 0.5 mA for VBE = 0.7 V, then at 20°C for
VBE = 0.75 V, IE = ?
IC1 + IC2
= 2 ¥ 1.8 ¥ 1013 exp20.833 I C 2 (0.705 V)
= exp(705 - 700)/ 26 = exp5/26
I C1 (0.7 V)
= 2 ¥ 1.8 ¥ 1013 ¥ 1.12 ¥ 109
= 4.02 ¥ 104A = 0.402 mA. = exp0.1923, IC2 = IC1 (0.7 V)exp 0.1923
= 0.5 ¥ 1.212 = 0.6 mA
IC 2 (0.705 V)
= exp(705 700)/26 = exp85/26
IC1(0.625 V)
= exp3.269 = 26.29,
IC2(0.705 V) at 100°C = 0.5 ¥ 26.29
= 13.15 mA
31. An n-p-n transistor operating at IC = 2 mA
Figure 5.30 and VBE = 0.7 V and its IC VCE character-
istic has slope of 5 ¥ 10 5 S. What would
29. The emitter current of an n-p-n transistor be the corresponding values of the output
at VBE = 0.7 V and temperature 25°C is resistance and early voltage? What would
1 mA. What would be the value of base- happen to the output resistance if IC be-
emitter voltage at 0°C and 100°C. comes 20 mA ?
Solution:
%
Solution: 34. Find the values of VE and VC for VB = 3 V,

1 1 V, and 0 V assuming very high value of
ro = = 20 KW, VA = roIC = 20 ¥ 2 current amplification factor b in Fig. 5.31.
slope
VA 40 V
= 40 V, ro = = = 2 KW.
20 mA 20 mA
32. What would be the Early voltage if the out-
put resistance of a BJT at collector current
of 10 mA is 10 MW? How much the output
resistance would become, if the collector
current is raised to 10 mA?
Solution:
VA = roIC = 10 ¥ 10 = 100 V,
VA 100
ro = = = 10 KW
IC 10 mA
33. The base-emitter voltage (VBE) in Fig. 5.31 Figurer 5.32
is adjusted such that it results into IC =
1mA and VCE = 2 V. The VCE is raised to Solution:
10V keeping the VBE constant that results VB VBE = VE = 3 0.7 = 2.3 V,
in IC = 1.1 mA. Obtain VA and ro of the
BJT at IC = 1 mA. IE = 2.3 mA = IC (for very high b),
Solution: VC = 9 V 2.3 V = 6.7 V
11
. -1 VB = 1 V, VE = 0.3 V, IE = 0.3 mA = IC
Slope of the IC VCE curve = =
10 - 2 (for very high b), VC = 9 V 0.3 V
. ¥ 10-3
01 . ¥ 10-3 1 mA
01 = 8.7 V
, ro = 80 KW, =
8 8 VA VB = 0 V, VE = 0.7 V, BJT is reverse
-3 biased and cut-off, IE = 0 = IC, VE = 0 V,
1 ¥ 10
VA = 8 = 80 V VC = 9 V
. ¥ 10-3
01
35. The emitter voltage VE in Fig. 5.32 mea-
sures to be 1V. What are the values of
VB, IB, IC, IE, VC, a and b ?
Solution:
VB = VBE + VE = 0.7 V 1 V = 0.3 V,
0.3
IB = = 0.015 mA,
20 K
5-1
IE = = 0.8 mA,
5K
IC = 0.8 0.015 = 0.785 mA,
Figure 5.31 VC = 5 3.925 = 1.1 V,
&
IC 0.785 IC
a= = = 0.99, gm = = 0.16 S
IE 0.8 VT
iC(t) = IC + gmvbe(t)
0.785
b= = 52.33
0.015 = 4 + 160 ¥ 0.004 sinwt
36. The nominal value of gm of a BJT is 80 mS
= (4 + 0.64 sinwt)mA
whose b falls in the range of 50 to 200.
The actual variation in the collector cur- vC(t) = 10 RCiC(t) = 10 8 1.28sinwt
rent IC is 20%. What would be the extreme
values of resistance looking into the base = (2 1.28 sinwt)V
of the BJT? iC ( t ) (4 + 0.64 sinw t )mA
iB(t) = =
Solution: b 100
The simplest hybrid-p model of the BJT at = (0.04 + 0.006sin wt)mA
low frequency is drawn as in Fig. 5.33.
The resistance seen by the base of the .
-128
Voltage gain = = 320
BJT = rp. 0.004
gm(max) = gm + 0.20 gm = gm(1.2)
= 80 mS ¥ 1.2 = 96 mS
gm(min) = gm 0.20 gm= 0.8 gm = 64 mS
b max 200
rp(min) = = = 3.125 KW
g m (min) 64
b min 50
rp(min) = = = 0.52 KW
g m (max) 96 Figure 5.34
38. In Fig. 5.34 if VCC is fixed at 10 V and input

signal vbe = Vbe (max) Sin wt is applied to
maintain linearity for amplification, then
show that the largest signal at the collector
without the BJT leaving the active region is
Figure 5.33
given by
37. The VBE in the circuit of Fig. 5.34 is ad- RCIC =
justed such that VC = 2 V. Obtain the in- È Vbe (max) ˘
stantaneous quantities such as iC(t), vC(t), {VCC - VBE - Vbe(max) }/ Í1 + ˙
Î VT ˚
and iB(t), if VCC = 10 V, RC = 2 KW, and a
signal of vbe = 0.004 sinwt is applied. Obtain the dc voltage at the collector and
voltage gain of the amplifier.
Solution:
Solution:
VCC - VC 10 - 2 Input voltage = VBE + Vbe(max) sin wt, vC =
IC = = = 4 mA,
RC 2K VCC ICRC gmVbe(max) sin wtRC
'
In order to maintain the BJT in the active 10 - 0.005 - 0.7 9.295

region, vC ≥ vB, then ICRC = = = 7.75V,
5 1.2
1+
VCC ICRC gm Vbe(max) RC ≥ Vbe (max) + VBE 25
VC = VCC RCIC = 10 7.725 = 2.25V
To obtain the maximum output signal the
equality sign in the above equation is Amplitude of output signal
equated = 2.25 (VBE + Vbe(max)) = 2.25 0.705
VCC ICRC RCgmVbe(max) = 1.55V
I
= Vbe(max) + VBE, substituting gm = C - 1.55
VT Voltage gain = = 310
0.005
IC
or, VCC - I C RC - RC Vbe (max) 39. A BJT amplifier in Fig. 5.35 is biased with
VT a constant current source I and has very
Ê Vbe (max) ˆ high b. Obtain dc voltage at the collector
= VCC - IC RC Á1 + and voltage gain of the amplifier. In
Ë VT ˜¯
equivalent circuit, an open circuit should
= Vbe(max) + VBE
replace the current source.
Ê Vbe (max) ˆ
or, IC RC Á1 + Solution:
Ë VT ˜¯
IE = IC = 1mA (high b)
= VCC Vbe(max) VBE
VC = 5 2 = 3V
VCC - Vbe (max) - VBE Ic 1
or, ICRC = (Proved) gm = = = 0.04S
Vbe (max) VT 25
1+
VT vs + vp = 0, us = up
IC
Voltage gain = gmRC = - RC vc = gmRCvp = 0.04 ¥ 2 Kvp
VT
vc = 0.040 ¥ 2 Kvp = 40 ¥ 2vp
VCC - Vbe (max) - VBE Ê 1 ˆ
= ÁË - V ˜¯
VT + Vbe (max) vc v v
T Voltage gain = ¥ p = 80 = c
VT vp vs vs
(VCC - Vbe (max) - VBE )

=
VT + Vbe(max)
Figure 5.35

40. What should be the ac input voltage and 42. Both BJTs in Figs. 5.37 (a) and (b) are
current to develop 1.5 V peak-to-peak identical and current i is set equal to I for
across the output terminals of the circuit VCE = 0.7 V in Fig. 5.37 (a) and in Fig.
shown in Fig. 5.36. Given gm = 100 mS 5.37 (b) for VCE = 0.6 V. Obtain relative
and b = 100 ? size of emitter-base and collector-base
Solution: junction.
vc = gmRC vbe = 100 ¥ 2 vbe = 200 vbe Solution:
1.5 As, VBE = VBC = VCE, From Eqn. (5.9.9),
vbe = = 75 mV. I
200 iE = S (expVCE /VT - 1)
vbe v 75 aF
iB = = be = 100 = 75 mA.
rp b / gm 100 IS( expVBC / VT 1),
I ES I
i= (exp700 / 26 - 1) CS (exp0 - 1)
aF aR
I ES I
ª exp 26.923 = 4.9266 ¥ 1011 S
aF aF
In Fig 5.42, IC = i = IS(exp0/VT 1)
IS
(exp600/ 26 - 1)
aR
Figure 5.36 IS I
i= exp 23.077 = CS 10524
. ¥ 1010
41. The emitter-base junction saturation cur- aR aR
rent of a BJT having aF = 1 and aR = 0.1 is IS I
Hence, 10524
. ¥ 1010 = S 4.93 ¥ 1011
1014 A. What would be the value of its aR aF
collector-base junction saturation current?
What is the relative size of the collector I S /a R a 49.3
or, = F = = 46.85
junction with respect to the emitter junc- I S /a F aR 10524
.
tion? How much is the value of bR? The collector-base junction is 46.85 times
Solution: the emitter-base junction.
aF 1
ISEaF = aRISC, ICS = I SE = 10-14
aR .
01
= 1013A,
I SC
Area of collector junction is =
I SE
= 10-times the area of emitter junction.
aR 01
. 01
.
bR = = = = 0.111
1-a R 1 - 01
. 0.9
Figure 5.37

43. Obtain relationship between iB and iE for a 44. What would be the values of bF and bR of a
diode connected BJT shown in Fig. 5.38. BJT with its fixed base current that pro-
Solution: duces VCE(SAT) = 0.080 V when its emitter
terminal is grounded and collector terminal
VBE = VBC = V > 0, From Eqn. (5.9.11), is left open and produces VCE(SAT) =
iB = 0.001 V when its collector terminal is
IS I grounded and emitter terminal is left open?
(expVBE / VT - 1) + S (expVCE / VT - 1)
bF bR Solution:
I I From Eqn. (5.9.19) VCE(SAT)
iB = S expV /VT + S expV /VT
bF bR
1 + ( b forced + 1)/ b R
= VT ln
FI
=G S I IJ
+ S expV / VT
1 - b forced / b F
Hb F bR K With emitter grounded and collector open
circuited, bforced = 0,
I S (b F + b R )
= expV /VT 1 + ( 0 + 1)/ b R
bFbR VCE(SAT) = 0.080 = 0.026 ln
1 - 0/ b F
IS bR 1 + 1/ b R
or, expV /VT = i B = 0.026 ln , 1n(1 + 1/bR)
bF bR + bF 1
From Eqn. (5.9.9), 80
= = 3.1
IS 26
iE = expV /VT - I S expV /VT
aF 1
or, 1 + = exp3.1 = 22.198,
bR
1 I
= IS ( - 1) expV /VT = S expV /VT
aF bF 1
bR = = 0.047
21198
.
IS bR
or, iE = expV /VT = i B When collector is grounded and emitter is
bF b/ R + b F
left opened, bforced = 0, bF = bR,
bR 1 + ( 0 + 1)/ b F
= iB VCE(SAT) = 0.001 = 0.026 ln
bF 1 - 0/ b F
= 0.0261n(1 +1/bR), 1n(1 + 1/bR)
1
= = 0.0385
26
bF = 25.5
Figure 5.38

Questions for Practice indicate the active, cut-off, and saturation

regions.
1. Discuss the role of emitter, base and col- 22. Discuss briefly the charge transport
lector regions in the operation of BJT mechanism in a BJT.
2. Why is the base width very thin? 23. Derive an expression for the terminal cur-
3. For normal operation how the base emitter rents in a p-n-p transistor
and base collector junctions are biased? 24. Define a and b of a transistor and deduce
4. Draw block diagrams of n-p-n and the relationship between them. Find the
P-N-P transistors with batteries expression for the collector current IC in
5. What is a ? How it is related with transis- terms of the base current IB the reverse
tor currents? saturation current ICO and b.
6. What is the typical value of a? 25. A Ge transistor with a = 0.98 gives ICO=
7. How transistor a and b are related? 12 mA when used in the CB configuration.
8. What is the typical value of b? Obtain IC when the transistor is used in CE
9. What is collector reverse saturation cur- configuration with IB = 0.2 mA
rent? What is the cause of it? 26. Why transistor action cannot be achieved
10. What carrier makes up the largest compo- by connecting two diodes back to back?
nent of current inside p-n-p and n-p-n tran-
sistors?
11. What are the three possible configurations Multiple Choice Questions
of BJT?
12. What is the meaning of symbols ICEO and 1. Current amplification factor in CB con-
ICBO? figuration is
13. What is the relation between ICO and ICEO? (a) a (b) 1 + b
14. Where do you bias transistor? Why do you (c) 1/(1 + b) (d) b
bias it? 2. Current amplification factor in CE con-
15. How can you justify neglecting VBE in figuration is
fixed bias circuit but not in self-bias cir- (a) a (b) 1 + b
cuit? (c) 1/b (d) b
16. What is fixed in the fixed biased circuit? 3. Current amplification factor in CC con-
17. How does the fixed bias circuit biases the figuration is
base emitter junction and collector base (a) a (b) 1 + b
junction? (c) 1/b (d) b
18. What is thermal runaway? 4. Leakage current in CB configuration is
19. How does self bias circuit achieve thermal (a) ICBO (b) IBCO
stability? (c) ICEO (d) IECO
20. How is a DC load line plotted on the output 5. Leakage current in CE configuration is
characteristic of BJT? (a) I C (b) ICBO
21. Draw the output characteristics of an (c) ICEO (d) ICB
n-p-n transistor in CE configuration and
!
6. ICEO and ICOare related as 17. (a) Ro(CB) > Ro(CC)

(a) ICEO = (b + 1)ICO (b) Ro(CB) < Ro(CC)
(b) ICEO = aICBO (c) Ro(CB) = Ro(CC)
(c) ICEO < ICBO 18. Which is correct
7. The value of a is (a) IB < IC < IE
(a) unity (b) IE < IB < IE
(b) very near to unity (c) IB = IC = IE
(c) greater than unity 19. The arrow in a transistor terminal repre-
(d) very much less than unity. sents
8. a is related to b as (a) emitter
(a) a = b/(1 + b) (b) collector
(b) a = b/(1 b) (c) base
(c) a = 1/(1 + b) 20. The arrow in a transistor represents
9. b is related to a as (a) the direction of conventional current
(a) b = a/(1 + a) (b) the opposite direction of conventional
(b) b = a/(1 a) current
(c) b = (1 a)/a (c) the direction of flow of electrons
10. Which one is correct 21. The doping level of emitter region is
(a) IE = IB + IC (a) greater than collector and base region
(b) IC = IB + IE (b) less than collector and base regions
(c) IE < (IB + IC) (c) less than base but greater than collec-
11. Collector current and reverse saturation tor region
collector current are related as 22. The physical dimension of collector region
(a) IC > ICEO is
(b) IC < ICEO (a) largest w.r.t the other two
(c) ICO = ICEO (b) smallest w.r.t the other two
12. (a) Ri(CB) > Ri(CE) (c) equal to the rest of the two
(b) Ri(CB) < Ri(CE) (d) smaller than emitter but bigger than
(c) Ri(CB) = Ri(CE) base
13. (a) Ri(CE) > Ri(CC) 23. For normal amplifier operation
(b) Ri(CE) < Ri(CC) (a) EB junction is forward and CB junc-
(c) Ri(CE) = Ri(CC) tion is reverse biased
14. (a) Ri(CB) > Ri(CC) (b) EB junction is reverse biased and CB
(b) Ri(CB) < Ri(CC) junction forward biased
(c) Ri(CB) = Ri(CC) (c) both are forward biased
15. (a) Ro(CB) > Ro(CE) 24. CB transistor has
(b) Ro(CB) < Ro(CE) (a) lower input and higher output resis-
(c) Ro(CB) = Ro(CE) tances
16. (a) Ro(CE) > Ro(CC) (b) higher input and lower output resis-
(b) Ro(CE) < Ro(CC) tances
(c) Ro(CE) = Ro(CC) (c) low input and output resistances
"
25. CE transistor has (b) collector and base leads

(a) lower input and higher output resis- (c) emitter and base leads
tances 31. In p-n-p transistor the emitter current
(b) higher input and lower output resis- flows
tances (a) out of emitter lead
(c) medium input and output resistances (b) into emitter lead
26. CC transistor has (c) neither out nor in the emitter lead
(a) lower input and higher output resis- 32. In a BJT the
tances (a) base region is sandwiched between
(b) higher input and lower output resis- emitter and collector
tances (b) emitter region is sandwiched between
(c) low input and output resistances base and collector
27. The phase difference between the input (c) collector is sandwiched between base
and output currents in CB configuration and emitter
are 33. The quiescent state of transistor is when
(a) 180° (b) 0° (a) biased but no signal is applied
(c) 90° (d) 45° (b) it is unbiased
28. The phase difference between the input (c) no current flows
and output current in CC configuration are 34. Maximum swing of signals occurs when
(a) 180° (b) 0° Q-point along load line is selected at
(c) 90° (d) 30° (a) middle of the output characteristic
29. ICBO is (b) the saturation point
(a) collector to base current when emitter (c) the cutoff point
is open 35. The emitter efficiency of a junction tran-
(b) collector to base current when base is sistor decreases with
grounded (a) decrease of emitter doping
(c) collector to base current when base is (b) increase of emitter doping
connected to a resistance (c) decrease of base width
30. ICEO flows in (d) decrease of base doping
(a) collector and emitter leads

1. (a) 2. (d) 3. (b) 4. (a) 5. (c) 6. (a)
7. (b) 8. (a) 9. (b) 10. (a) 11. (a) 12. (b)
13. (b) 14. (b) 15. (a) 16. (a) 17. (a) 18. (a)
19. (a) 20. (a) 21. (a) 22. (a) 23. (a) 24. (a)
25. (c) 26. (b) 27. (b) 28. (b) 29. (a) 30. (a)
31. (b) 32. (a) 33. (a) 34. (a) 35. (a)
6
Physical Phenomenon in
JFET and MOSFET
6.1 Introduction
So far we have discussed the functioning of the BJT. The carriers in BJT have to cross the junction(s)
under the influence of externally applied bias that results into the current flow. In contrast to the BJT,
the carriers in unipolar devices (FET) do not cross the junction, rather they flow through only one type
of semiconductor (either n or p), called the channel. The channel thickness is controlled by the external
electric field that in turn controls the flow of carriers. Thus, the Field Effect Transistor (FET) is a
device wherein, the flow of charge carriers between drain and source is under the control of externally
applied electric field. The externally applied electric field penetrates into the conducting channel and
controls its flow. This electric field is established by application of external voltage across another two-
terminals (perpendicular to the flow of carriers) namely gate and source. Since the current flow in FET
is through either a p-type or n-type channel, it is called a unipolar device also. The FET family is
described as the FET tree in Fig. 6.1.
Advantages of FET
(1) In BJT both types of carriers (electrons and holes) contribute to current flow. Where as in FET
either n (n-channel) or p (p-channel) type of carrier contributes to current flow. Hence, FET is
called unipolar device. Vacuums tube is another example of unipolar device.
(2) It is simple to fabricate the FET in IC form and is efficient in working.
216
(3) The FET is smaller in size and hence high density of device fabrication is possible in FET w.r.t.
BJT.
(4) Since in FET only one type of carrier flows through the bulk of material called channel, noise
due to temperature effect in tube and BJT is not present in FET.
(5) Since an insulator isolates the channel from the gate of FET, the input resistance of the FET is
very high (of the order of 100 KW) whereas input resistance of BJT is of the order of few ohms
to hundreds of ohms.
(6) The FET has negative temperature coefficient of resistance and hence has better stability
against temperature.
(7) The BJT is current controlled (driven) device whereas FET is a voltage controlled device.
(8) The FET does not exhibit offset voltage at zero drain current and hence works as an excellent
signal chopper.
Figure 6.1 FET Tree
Disadvantages of JFET
(1) As the FET has high input resistance, the gate voltage has less control over its drain current and
hence the voltage gain of FET amplifier is low w.r.t. the BJT amplifier.
(2) The gain bandwidth product of the FET amplifier is low w.r.t. the BJT amplifier.
Basically there are two types of FETs:
∑ n-channel JFET, and
∑ p-channel JFET
Let us discuss the working principle of the n-channel that would hold good for the p-channel with its
currents and voltages directions reversed. The main advantage is the high input resistance of the order
of 100 MW for JFET and of the order of 1010 W to 1016 W in the case of MOSFET. It exhibits very high
degree of isolation between its input and output. The FET is also a less noisy device. The main disadvantage
of the FET is low gain-bandwidth product.
It is easier to manufacture FETs and MOSFETs than manufacturing BJTs. The MOSFETs play a
dominant role in the digital integrated circuits design and fabrication. The microprocessors, logic circuits,
and memory circuits, etc. are fabricated using VLSI / VVLSI technology mostly employing MOS
transistors.
The design of special amplifiers having very large input resistance uses JFETs/MOSFETs. A practical
example of such a situation arises in the case of an operational amplifier wherein the requirement of very
high input resistance is solved using the JFET in its input stage. The JFETs can be combined with BJTs
for some special purpose high performance linear circuits called BiFET circuits. The practical example
Physical Phenomenon in JFET and MOSFET
217
of such combination is the JFET structure using a metal-semiconductor (Schottky) junction with gal-
lium-arsenide to form the MESFET, a device suitable for use as an amplifier even in gigahertz range.
The JFETs are used in analog switching and variety of other circuit applications.
6.2 Fabrication
Figure 6.2 is a n-type semiconductor bar with highly doped (p+) p-type semiconductors diffused from
both sides can be seen in Fig. 6.2. The n-type semiconductor bar is called the channel. Both p-type
materials are electrically connected together to form a single terminal called the gate. Metal contacts are
taken out from both ends of the channel calling them Source (S) and Drain (D). Similarly, the metal
contact taken out from the gate point is called the Gate (G).
Figure 6.2 Structure and symbols of n- and p-channel JFET

The arrow on the gate indicates the direction of the conventional current flow if the gate-source is
forward biased. The p-n junction, i.e. gate-to-channel is reverse biased in almost all applications and
hence, very small leakage current flows in the gate terminal. This means that the impedance seen at the
gate terminal is very high.
6.3 Operation of JFET with Small VDS

Figure 6.3 is the circuit for the operation of JFET with very small VDS (fraction of volts). For VGS = 0,
the formation of a very narrow depletion width takes place and the maximum drain-source current (IDS
= ID) flows through the channel. The value of ID depends on the value of the VGS and the value of the
channel resistance rd. As the VGS is increased, the depletion width widens and the effective width of the
channel narrows. Since the value of the VDS is a fraction of volts, the depletion width is symmetrical at
both ends of the channel and the channel width is uniform from the source to the drain. The narrowing
of the effective channel width causes the channel resistance to increase but remains constant for one
particular value of the VGS. The ID versus VDS characteristics shown in Fig. 6.4 remains a straight line
with smaller slopes.
218
Figure 6.3 Physical structure and physical pinch-off with small VDS
Figure 6.4 ID–VDS for small VDS
A point is reached with increasing value of VGS (reverse bias) when the depletion region occupies the
complete channel width and physically no channel exists between the drain and the source and hence,
no current can flow. This condition is called the physical pinch-off and is illustrated in Fig. 6.3. The VP
denotes the voltage at which the pinch-off occurs.
VP = VGS ( OFF ) ID = 0, VDS = very small (6.3.1)

Here VP is obviously negative for n-channel FET.
We infer from the VDS ID characteristic shown in Fig. 6.4 that for a very small value of VDS, the
device acts as linear resistance rd whose value can be controlled by the value of the VDS. In fact the
JFETs are used as a voltage-controlled variable resistance (VVR) in some of the applications as auto-
matic-gain control (AGC) circuits which is employed in the communication receivers.
6.4 Operation Beyond Linear Range

Let us keep the value of VGS constant at one particular value more (i.e. less negative) than VP and
increase VDS in the circuit of Fig. 6.5. Since the channel is a semiconductor bar, it exhibits a resistance.
The amount of voltage applied across the channel is distributed uniformly from source to the drain
219
having zero voltage at the source and the VDD at the drain as indicated in Fig. 6.6. When the reverse bias
at drain end VDG falls below the pinch-off voltage VP, the channel is pinched off at the drain end and the
drain current saturates. The reverse bias at the drain end will be VDS = VDD and at the source end the
reverse bias = 0V. Hence the formation of depletion region is of a tapered shape as shown in Figs. 6.5
and 6.7.
Figure 6.5 JFET with VDG ≥ VP
We know that any further increase in the value of VDS will not alter the shape of the channel and
hence, the current ID will remain constant at the value for VDS = Vp. This value of saturated drain-source
current (IDSS) is specified in the data sheet of the JFET. It is defined as
IDSS = I D VGS = 0, VDS = VP (6.4.1)
Figure 6.6 Voltage distribution along channel
Here, it is important to observe the difference between the complete pinch-off (physical pinch off)
and the electrical pinch-off at the drain end. In the previous case of Fig. 6.3, the entire channel is
depleted off the charge carriers and hence, no current can flow, i.e. ID = 0. However, in the other case
of Fig. 6.7, the constant drain current IDSS will continue to flow through the channel. The electrons in
this case simply drift through the pinched off region at the drain end of the channel and ultimately reach
the drain terminal. The voltage across the channel and the current through it remain constant. The
difference of applied voltage VDS and the value VP appears across the depletion region at the drain end
of the channel.
220
Figure 6.7 Channel shape with VGS = 0 and large VDS
6.5 Operation of JFET with Small VDS and VGS = –V1

Let us consider the operation of the JFET in the case when VGS = V1, where V1 is any positive voltage
smaller than VP in Fig. 6.8. The channel is of uniform width for small VDS, as the reverse bias at the
drain end is almost equal to the source end. With increasing value of VDS, the reverse bias at the source
end is constant (zero) whereas, it varies along the channel and is the maximum, (VDS) at the drain end.
Again the channel will be tapered in shape and the channel resistance will increase with increasing value
of VDS. Eventually the channel will look like to be pinched off at the drain end. This will happen for the
drain voltage corresponding to
VDG = VP (6.5.1)
Since in this case VGS = V1, the pinch-off will occur at
VDS = VGS Vpo (6.5.2)
Since the channel is narrower than it was for the VGS = 0, the saturated drain current will be smaller
than the IDSS. The complete VDS ID characteristic can be obtained by varying the value down to VGS =
Vp .
6.6 Derivation of ID
We know that the drain current ID is function of two-variables, i.e. drain-to-source voltage VDS and the
gate-to-source voltage VGS. Thus, the drain currnt ID is expressed as
ID = f (VDS, VGS)
Since, the drain-to-source voltage VDS and the gate-to-source voltage VGS affect the depletion width
of the channel and hence, we have to co-relate the depletion width with these voltages also. In FET the
conductivity of the channel is modulated by transverse electric field.
221
Poissons equation relating transverse voltage and volume charge density is given by
d 2V r qN qN
=- =- D =- D (6.6.1)
dy 2 es es e re o
where, r = volume charge density in coulomb per cubic metre
q = electronic charge in coulomb = 1.6 ¥ 1019 Coulomb = 1 eV
ND = electron concentration per cubic metre
es = permittivity of the material in farad per metre
er = relative dielectric constant
e0 = 8.854 ¥ 1012 F/m = permittivity of the free space
Figure 6.8 Working of JFET

Integrating Eqn. 6.6.1 yields
d 2V qND
z dy z
2 dy = -
es
dy
dV qN
or, = - D y + C1 (6.6.2)
dy es
dV
Now, applying the boundary condition = 0 at y = a, in Eqn. 6.6.2 yields
dy
dV qN
= 0 = - D a + C1
dy es
qND
or, C1 = a
es
dV qN qND qN
Hence, = - D y+ a = - D ( y - a) volts per metre
dy es es es
(6.6.3)
222
Integrating Eqn. 6.6.3 with the boundary condition V = 0 for y = 0 yields

dV qN
z dy
dy = - D ( y - a)dy
es z
or, V=-
FG
qN D y 2 IJ
- ay + C2 (6.6.4)
es 2 H K
Now, V=0=-
qN D 0 F
- a0 + C2 I
es 2 H K
or, C2 = 0
Hence, V=-
qND y2 FG IJ
qN
- ay = - D y 2 - 2ay d i (6.6.5)
es 2 H K
2e s
The pinch-off voltage is obtained for y = a,
qND 2 qND a 2
Vp = - a - 2a 2 =
d i (6.6.6)
2e s 2e s
where, a = height of the channel in metre.
Equation 6.6.6 indicates that the pinch-off voltage is a function of the doping concentration ND and
the channel height a.
The pinch-off voltage under saturation condition can be expressed as
qND a 2
Vp = = VDS + |VGS| + yo (6.6.7)
2e s
where, |VGS| = absolute value of the gate voltage
yo = built-in or barrier voltage at the junction
Hence, saturation drain voltage is expressed as
qNDa 2
VDS = Vp |VGS| yo = - VGS - y o (6.6.8)
2e s
Here, the total transverse voltage = |VGS| + yo and longitudinal voltage is VDS.
6.6 V-I Characteristics

The drain current of a JFET is dependent on the drain-to-gate voltage and the channel resistance. The
channel resistance is expressed as
rL L L L
R= = = = (6.6.9)
A sA m nqND A m n qN D z{a - W ( x)}
where, L = length of the channel in x-direction
z = breadth of the channel in z-direction
223
a = channel height in y-direction

W(x)/2 = depletion layer width from each side
mn = electron mobility
The drain voltage across any elemental section dx of the channel is expressed as
ID dx
dV(x) = IDdR = (6.6.10)
m n qN D z{a - W ( x)}
dV ( x )
ID = m n qN D z{a - W ( x )} (6.6.11)
dx
The channel-to-gate voltage can be written as
qN DW 2 ( x) qN D a 2W 2 ( x) V pW 2 ( x)
V(x) + |VGS| + yo = = =
2 es 2 e s a2 a2
1/ 2
Hence,
R 2e
W(x) = S( s
)(V ( x ) + VGS + y o
U
)V (6.6.12)
T qN D W
1/ 2 1/ 2
dW ( x ) 1È 1 ˘ Ê qN D ˆ dV ( x) Ê 2 e s ˆ
= Í ˙ ÁË 2e ˜¯
dx 2 ÎV ( x) + VGS + y o ˚ s dx ÁË qN D ˜¯
1 Ê 2 e s ˆ dV ( x)
=
2W ( x) ÁË qN D ˜¯ dx
=
FG IJ
1 e s dV ( x)
(6.6.13)
H K
W ( x ) qND dx
dW ( x ) F e I dV ( x )
s
and W( x) =G (6.6.14)
dx H qN JK dx D
dV ( x ) qND dW ( x )
Now, = W( x) (6.6.15)
dx es dx
dV ( x ) m q 2 N D2 z dW ( x )
ID = m n qN D z{a - W ( x )} = n {aW ( x ) - W 2 ( x )} (6.6.16)
dx es dx
m n q 2 ND2 z m q 2 ND2 z
= {aW ( x ) - W 2 ( x )}dW ( x ) = n {aW ( x ) - W 2 ( x )}dW ( x )
e s dx esL
224
L x= L
m q 2 N D2 z 2 m nq 2 N D2 z È W 2 ( x) W 3 (x) ˘
= n {aW ( x ) W ( x )}dW ( x ) = Ía -
e s L Ú0
- ˙
es L Î 2 3 ˚ x=0
x= L
m n q 2 N D2 z È 2 ˘
= Í aW 2 ( x) - W 3 ( x) ˙ (6.6.17)
2 es L Î 3 ˚ x= 0
Boundary conditions are at x = 0, V(x) = 0, and W(x) = W0 and x = L, V(x) = VDS and W(x) = WL
Now, WL2 = a2
F V ( x) + V GS +y o I and W 2
= a2
FV GS +y o I (6.6.18)
GH V p
JK 0 GH Vp JK
m nq 2 N D2 z Ï 2 2 2 3 3 ¸
or, ID = Ìa(WL - W0 ) - (WL - W0 ) ˝ (6.6.19)
2e s L Ó 3 ˛
Substituting W L2 and W o2 in Eqn. 6.6.17 yields
m n q 2 N D2 za3 ÔÏÊ VDS + VGS + y o VGS + y o ˆ

ID = ÌÁ - ˜
2 e s L ÔÓË Vp Vp ¯
F
2 VDS + VGS + y o I 3/ 2
F
2 VGS + y o I 3/ 2
U|
-
3 GH Vp JK +
3GH Vp JK V|
W
3/ 2 3/ 2 ¸
m q 2 N D2 za3 ÏÔVDS 2 Ê VDS + VGS + y o ˆ 2 Ê V + yo ˆ Ô
= n Ì - + Á GS ˝
2 e S L Ô VP 3 ÁË VP ˜
¯ 3Ë VP ˜
¯ Ô˛
Ó
ÏÔV 3/ 2 3/ 2
I 2 Ê VDS + VGS + y o ˆ 2 Ê VGS + y o ˆ ¸Ô
or, ID = DSS Ì
DS
- Á ˜¯ + 3 ÁË ˜¯ ˝ (6.6.20)
2 ÔÓ VP 3 Ë VP VP
˛Ô
m n q 2 N D2 za 3
where, IDSS = (6.6.21)
eL
6.6.2 Linear Range

In the linear range, we assume VDS << (VGS + yO).
ÈV 3/ 2 3/ 2 3/ 2
I 2 ÏÔ VGS + y O ¸Ô Ê V ˆ 2 ÏÔ VGS + y O ¸Ô ˘˙
ID = DSS Í DS
- Ì ˝ Á 1 + DS
+ Ì ˝ (6.6.22)
2 Í VP 3 ÔÓ VP ˛Ô Ë VGS + y O ˜¯ 3 ÔÓ VP ˛Ô ˙˚
Î
225
Under such condition, Eqn. 6.6.22 is modified using Binomial theorem as

ÈV 3/ 2 3/ 2
I 2 ÔÏ VGS + y o Ô¸ Ê 3 V ˆ 2 ÔÏ VGS + y o Ô¸ ˘
ID = DSS Í DS
- Ì ˝ Á1 + ¥
DS
˜+ Ì ˝ ˙
2 Í VP 3 ÔÓ VP ˛Ô Ë 2 VGS + y o ¯ 3 ÔÓ VP Ô˛ ˙˚
Î
È 3/ 2 3/ 2 3/ 2 ˘
Ï ¸Ô 2 ÏÔ V + y o ¸Ô
I
= DSS ÍÊ VDS ˆ - 2 ÔÌ VGS + y o ˝ -
2 ÏÔ VGS + y o ¸Ô
Ì ˝
3
¥ ¥
VDS
... + Ì GS ˝ ˙
2 ÍÁË VP ˜¯ 3 Ô VP 3 ÔÓ VP Ô˛ 2 VGS + y O 3 ÓÔ VP ˙
Î Ó ˛Ô ˛Ô ˚
I
R| VDS VDS
F V +y I 1/ 2 U| I V
R| F V +y I 1/ 2 U|
DSS GS o DSS DS GS o
ID =
2 S| Vp
-
Vp
GG V
JJ V| = 2V S|1- GG V
JJ V| (6.6.23)
T H p K W P
T H p K W
Transconductance in the linear range is obtained from Eqn. 6.6.23 as
dI D I V 1 VGS + y 0 R| F I 1 U|V -1/ 2
gm(linear) = = DSS DS 0 - S| GH JK V |
dVGS 2VP 2 VP
VDS = K T W P
I V R| F
1 VGS + y 0 I -1/ 2
U| I V R| 1 F VP I 1/ 2
U|
= DSS 2DS - S| GH JK DSS DS
V| = 2V S|- 2 GH V2 JK V| (6.6.24)
2VP 2 VP GS + y 0
T W T P
W
dID I R| F V GS + y I U|0
1/ 2
Drain conductance = gd = = DSS S|1 - GH JK V| (6.6.25)

dVDS 2VP V
VGS =K T P
W
6.6.3 Saturation Range
In the saturation range substituting Vp = VDS(sat) + |VGS| + yO in Eqn. 6.6.20 yields
2 2 3 ÏÊ 3/ 2 3/ 2 ¸
m n q N D za Ô VDS + VGS + y o VGS + y o ˆ 2 Ê VDS + VGS + y o ˆ 2 Ê VGS + y o ˆ Ô
ID = ÌÁ - ˜ - Á ˜ + Á ˜ ˝
2e s L Vp Vp 3Ë Vp 3Ë Vp
ÔÓË ¯ ¯ ¯ Ô˛
I V +y 0R| F
2 2 VGS + y 0 I F I 3/ 2
U|
ID(sat) = DSS 1 - GS S| GH
- + JK GH JK V|
2 VP 3 3 VP
T W
I DSS R|1 V GS F
+ y 0 2 VGS + y 0 I 3/ 2
U|
= S| 3 - + GH JK V| (6.6.26)
2 VP 3 VP
T W
226
Mutual conductance in the saturation region is
dID I DSSR| 1 F
V +y 0 I 1/ 2
1 U|
gm(sat) = = 0-
S| + GS
GH JK V|
dVGS 2 VP VP VP
VDS =K T W
I Ï Ê V + y ˆ 1/ 2 ¸
Ô GS 0 Ô
= DSS Ì1 - Á ˜ ˝ (6.6.27)
2 VP Ë VP ¯ Ô
ÓÔ ˛
The cross-sectional area of the channel at pinch-off is extremely thin near the drain end and the
electric field E becomes very large to maintain the current flow which prevents the depletion layers
from meeting each other. Thus, the current density is very large at this point and the electrons approach
their maximum drift velocity as they shoot off through a very narrow gap. Hence, for values of VDS
more than Vp, the drain current is almost independent of voltage as shown in Fig. 6.9. Figure 6.10
shows a set of output characteristics for different values of VGS. The transfer curve is drawn as in Fig.
6.11. VDS at which saturation occurs for VGS = 0 is called the pinch-off voltage Vpo. It is about 4V in
Fig. 6.9. For various values of VGS, the locus of Vpo is drawn as the dotted line.
Figure 6.9 Plot of ID – VDS for VGS = 0
Figure 6.10 Output characteristics of JFET

227
The drain-to-source voltage at which pinch-off occurs can be expressed as

VDS = VGS Vpo
VDS = 0, for Vpo = VGS, and VDS = Vpo for VGS = 0.
From Fig. 6.7 it is clear that a small change in the gate-source voltage near VGS = 0 causes an
appreciable amount of change in the drain current. Hence, FET is called a voltage sensitive device. In the
linear region, i.e. Vpo £ VDS, the FET can be used as a voltage controlled variable resistance.
The drain-to-source voltage at which pinch-off occurs can be expressed as
VDS = VGS Vpo
VDS = 0, for Vpo = VGS, and VDS = Vpo for VGS = 0.
The FET as an amplifier is normally operated in the saturation region (constant current region).
Figure 6.11 ID – VGS (transfer) characteristics
6.7 Transfer Characteristics

The transfer curve of a JFET is a plot of the drain current versus gate-to-source voltage and is obtained
from its output characteristics as depicted in Fig. 6.12. The shape of the transfer curve looks like the
shape of a parabola having its vertex at VGS = Vp. The formula representing the parabola can be written as
y = a (x h)2 + k (6.7.1)
where h and k are the co-ordinates of the vertex of the parabola and its values are
For h = Vp, k = 0 (6.7.2)
Hence, Eqn. 6.7.1 reduces to
y = a (x Vp)2 (6.7.3)
The constant a can be evaluated by substituting the value of VGS = 0. Substituting the boundary
conditions VGS = 0, ID = IDSS in Eqn. 6.7.3 yields
IDSS = a(0 Vp)2 (6.7.4)
IDSS
or, a= (6.7.5)
(-VP )2
228
Figure 6.12 Parabolic transfer curve

Hence, combining Eqns. 6.7.3 and 6.7.4 yields
2
ID =
I DSS
(VGS VP) = I 2
DSS
F V IJ
GS
= G1 - (6.7.6)
2 H VK
( - VP ) P
This transfer equation is known as the Shockley equation in the honour of the developer of the ideas.
Solving Eqn. 6.7.6 for VGS, perhaps results into a more useful equation as
R| F I I U| D
1/ 2
= S1 - G
|T H I JK V|W
or, VGS V p (6.7.7)
DSS
6.8 FET Parameters

The parameters of FET are:
∑ drain resistance, rd
∑ transconductance, gm
∑ amplification factor, m
These parameters can be obtained either analytically from drain current equation derived above or
graphically from its output (VI) characteristics shown in Fig. 6.13.
6.8.1 Drain Resistance

The drain resistance is defined as the ratio of incremental change in the drain-to-source voltage to the
incremental change in the drain current for one fixed value of the gate to source voltage. Hence
mathematically it is expressed as
DVDS
rd = (6.8.1)
DID VGS =K
229
The VI characteristic curve of FET becomes almost flat in the saturation region as demonstrated in
Fig. 6.13. It becomes very difficult to determine its drain resistance graphically because the correspond-
ing incremental change in drain current for incremental change in drain-source voltage is negligibly
small. However, these incremental quantities can be measured quantitatively using metres of different
ranges. The manufacturers data sheets provide this parameter in the form of output admittance yos. The
yos includes the output resistance rd alongwith its output capacitance at high frequency. The output
capacitance at low frequency is not effective and hence, at low frequency the drain resistance is ex-
pressed as
1
@ rd (6.8.2)
yos
The typical value of rd = 20 KW.
Figure 6.13 V–I characteristics of JFET
6.8.2 Mutual Conductance (gm)

The mutual conductance gm is a parameter for the measure of the gain of the FET. Though the gm varies
with the variation in the VGS, we are interested in the value of the gm in the pinch-off region. From
Eqn. 6.7.6
gm =
∂ID F V
= 2IDSS 1 - GS
IF 1 I (6.8.3)
∂VGS GH Vp JK GH -V JK
p
It is clear from Eqn. 6.8.3 that gm is not constant and varies with variation in the VGS and becomes
maximum for VGS = 0.
gmo = 2IDSS
F 1 I = 2I DSS
(6.8.4)
GH -V JK V
p p
Now, combining Eqns. 6.8.3 and 6.8.4 yields

230
gm = 2IDSS 1 -
FG VGS IJ FG 1 IJ = g FG1 - V IJ
mo
GS
(6.8.5)
H VP K H -V K H V K
p P

ID ID
gm = gmo 1 - 1 + = gmo (6.8.6)
I DSS I DSS
The manufacturers data sheets specify the transconductance as gm that includes capacitance at high
frequency also. The capacitive effect at low frequency is not present and hence,
2azqN D mn
gm(max) = gmo = (6.8.7)
L
A typical value of gm lies in the range of 2000mS to 8000mS. Since it is the ratio between incremental
change of output current to input voltage, it is called transconductance.
6.8.3 m)
Amplification Factor (m
The amplification factor m is defined as the ratio of incremental change in the drain-source voltage to the
incremental change in the gate-source voltage for a fixed value of drain current. It is mathematically
expressed as
m=
DVDS
=
F DV I F DI I = r g
DS D (6.8.8)
DVGS ID = K
GH DI JK GH DV JK
D GS
d m
6.9 MOSFET Construction

Though the operation of the MOSFET is similar to that of the JFET, there are few basic differences that
result in the MOSFET having lower capacitance and higher input impedance. A typical n-channel
enhancement type MOSFET structure is shown in Fig. 6.14. It consists of a low doped p substrate
onto which two heavily doped n+ regions have been diffused. The two heavily doped regions form drain
and source. There is no physical channel present in between these two heavily doped n+ regions.
Overlaying a thin layer of silicon dioxide (SiO2) forms the gate covering the drain and the source as
indicated in Fig. 6.14. A metallic layer is deposited on it to take out a metallic contact called the gate.
Two metallic contacts, one from drain and the other from source are taken out. They are called the
source and the drain terminals. The left side of Fig. 6.14 shows the enhancement type cross-sectional
view.
The depletion mode MOSFET structure is shown on the right side in Fig. 6.14. Here, an n-type channel
is physically present between the drain and the source. Figure 6.15 shows the cross-sectional view of
the enhancement and depletion-mode MOSFETs. The metallic contacts and the channel with the dielectric
layer between them form a parallel capacitor resulting in very high value of input impedance (of the
order of 1010W to 1015W). This is the major difference between the JFET and the MOSFET. The
dimensions of Z and L are measured in mm and nm.
231
Figure 6.14 Layout and cross section of enhancement and depletion modes of MOSFET
Figure 6.15 Layout and cross section of enhancement and depletion modes of MOSFET
6.9.1 Symbology
Circuit symbols of both enhancement and depletion type MOSFETs are shown in Figs. 6.16 and 6.17.
Enhancement mode symbols have dotted channel.
Figure 6.16 Enhancement type n- and p-channel MOSFET symbols
Figure 6.17 Depletion type n- and p-channel MOSFET symbols

232
Figure 6.18 Depletion of charge carriers below gate surface
Figure 6.19 Depletion mode characteristic
Figure 6.20 Transfer curve
6.9.2 Depletion Type MOSFET

The two highly doped (low resistivity) n+ -regions, separated by approximately l mil, are diffused onto
a lightly doped (high resistivity) p -substrate. A low doping n channel is diffused between the highly
233
doped n+ drain and source regions as shown in Fig. 6.18. The SiO2 forms an accurately controlled layer.
This thin layer acts as a dielectric.
An aluminium (Al) overlay is deposited over the oxide layer and highly doped n+ regions, called
source and drain. The metallic contacts are taken out from these highly doped n+ regions. A metallic
contact is also taken out from the oxide layer left in between the source and the drain, called the gate.
Since, the gate is isolated through an oxide layer working as an insulator, it offers very high input
resistance of the order of 1015W. This type of MOSFET is known as depletion-mode MOSFET. With
increasing value of the negative voltage VGS, the channel inversion just below the gate increases which
depletes more channel carriers (electrons). Thus, with increasing value of negative VGS, the conductivity
decreases and hence the drain current also decreases. On the contrary, positive value of VGS induces
negative charge carriers that adds to the already existing electrons and enhances the drain current.
Though it is called depletion type, the device can be operated either in enhancement or depletion mode.
Here, the gate is working as the free wheeling gate unlike the JFET gate. As the diffused channel width
and the carriers are depleted off, it is called depletion type MOSFET. Its V-I characteristics and the
transfer curve are shown in Figs. 6.19 and 6.20.
6.9.3 Enhancement Type MOSFET
Fig. 6.21(a) Physical structure of enhancement mode MOSFET
Figure 6.21(a) shows the physical structure of an n-channel enhancement mode MOSFET. The transis-
tor is fabricated on a low doped p-type semiconductor substrate. The substrate is a single crystal silicon
wafer that provides physical support for the device. Two heavily doped n+-type regions are created in
the substrate as shown in Fig. 6.21(a). These two heavily doped regions are known as source (S) and
drain (D). A thin layer (0.02 to 0.11 mm) of silicon dioxide (SiO2), an excellent insulator, is grown over
the substrate surface covering between the source and the drain. Metallic contacts are taken out from
the source (S), drain (D) and oxide layer (G) as indicated in Fig. 6.21(a).
234
Figure 6.21(b) Inversion of channel below the gate surface
The inversion at the top surface of the substrate by application of the external positive voltage
between the gate and the source creates a channel in the enhancement MOSFET as indicated in
Fig. 6.21(b). Also, there is a threshold voltage, Vth, below which not enough electrons will be attracted
to turn the channel region into n-type material, and the channel will not conduct. This threshold voltage
is a function of doping levels and thickness of the oxide layer. With an insufficient voltage on the gate to
establish the channel region as n-type, there can be no conduction between the source and drain. But
when the gate voltage is above the threshold, the channel is established. Then, if we apply a voltage
between the drain and the source, VDS, we will get a current to flow. As long as we keep the drain-
source voltage, low, the MOSFET acts just like a voltage controlled resistor. The resistance of the
channel is controlled by the gate voltage. This region of operation is known as the triode region. As VGS
is increased more, thickness of the inverted channel increases, resulting into more drain current as
demonstrated by Fig. 6.22.
Figure 6.22 V- I Characteristic of enhancement mode
The transfer curve of the enhancement type MOSFET is depicted in Fig. 6.23. The threshold voltage
Vth is approximately 1 V to 4 V. The nMOS is superior to the pMOS as the mobility of electrons is
almost 3 times than that of the holes.
235
Figure 6.23 Transfer curve of enhancement mode MOSFET
6.10 Derivation of MOSFET Drain Current

Figure 6.24 is the structure of the enhancement mode MOSFET. The nMOS is normally operated with
positive gate-source voltage VGS. The positive gate voltage induces negative charge at the top of the
insulator SiO2 and positive charge at the bottom surface of the SiO2. This in turn induces electrons on
the top surface of the substrate just beneath the gate. Thus, accumulation of electrons below the gate
takes place as indicated in Fig. 6.25. This results in conduction of electrons between the drain and the
source. This phenomenon is called surface inversion. The minimum value of VGS at which sufficient
number of mobile electrons accumulate in the channel region to form conducting channel is called the
threshold voltage Vth. Obviously the Vth for n-channel FET is positive. The value of Vth is controlled
during device fabrication and lies in the range of 1 V to 3 V. With increasing gate voltage the number of
conduction electrons increases, increasing the channel width and channel conductivity.
Figure 6.24 Enhancement MOSFET structure

236
Figure 6.25 MOSFET with gate voltage

Another variable that controls the current flow between drain-source is the drain-to-source voltage
VDS. As the VDD is increased, the depletion region around the drain, particularly near the channel-drain
point, widens, constricting the channel. Under this condition, the channel impedance increases till VDS =
VGS Vth = VP when the channel pinches off completely and the impedance becomes infinite. In
practice, the impedance never becomes infinite but becomes very high of the order of few MW. Further
increase in the VDS (VDD) shifts the pinch off point towards the source as indicated in Figs. 6.26 and 6.27.
Figure 6.26 Pinch-off condition VDS > 0
Figure 6.27 Pinch-off shifts towards source VDS > VP

237
The increase in the current is very low. In the operating range of enhancement mode nMOSFET, the
range of gate voltage is always positive. The gate to source voltage VGS must be positive to produce a
channel between the source and the drain as no current can flow until the channel is formed. The
current can flow only when VGS exceeds the threshold voltage. The VI characteristics and a typical
MOSFET circuit are shown in Figs. 6.28 and 6.29.
Figure 6.28 V-I characteristics of nMOS
We notice in the characteristic for VGS = Vth = 2V, the drain current ID = 0 for all values of VDS.
However, for values of VGS greater than Vth, the drain current ID flows. Here, the drain-source voltage
at pinch-off is
VDS(at pinch off) = VP = VGS Vth (6.10.1)
Let the voltage at a distance x from the source due to IR drop in the channel be denoted as V(x). Hence,
voltage across the oxide = VGS V(x). If COX is the capacitance of the oxide layer, then charge per unit
area accumulated in the channel at any point x = Q = CV = COX [VGS Vth V(x)]. If the channel width
is z = W, then total charges per unit area = WCOX{VGS Vth V(x)}
Charge induced in the channel Length of the channel
IDS = , Transit time tn =
Electron transit time Velocity of electron
As velocity is proportional to the electric field, vn = mn EDS
Figure 6.29 Schematic of nMOS

238
where, mn = mobility of the electron and EDS = electric field between drain and source
VDS L L2 L2
EDS =
, tn = = =
L vn mn EDS m nVDS
The charge induced per unit area = EGeins eo,
Ê e Aˆ
Total induced charge = Q = EGeins eo WL Á C =
Ë d ˜¯
VDS
VGS Vth
EG = 2 t = thickness of the channel
OX
tOX
VDS
VGS Vth
Total induced charge in the channel = eins eo WL 2
tOX
V
Charge induced in the channel VGS Vth DS
IDS = = e ins eo WL 2
Electron transit time tOX t ds
Ê VDS ˆ
ÁËVGS Vth 2 ˜¯ mn VDS mn eins eo W Ê VDS ˆ
= e ins eo WL 2
= Á VGS Vth 2 ˜¯ VDS
tOX L tOX LË
Ê V ˆ
= b Á VGS Vth DS ˜ VDS
Ë 2 ¯
mn e inse o m e e WL Ê WLe inse o ˆ 1 1 1
where, b=
tOX
= n ins o 2 = m n Á
tOX L Ë tOX ¯ L ˜ 2 = m n Cg
L2 ( )
= mn (COX WL ) 2
L
WLe inse o e e
where Cg = = COX WL, COX = ins o
tOX tOX
W Ê VDS ˆ Ê VDS ˆ
IDS = COX mn ÁËVGS Vth ˜¯ VDS = kn ÁËVGS Vth ˜ VDS
L 2 2 ¯
There are three distinct regions of operation: cutoff where the gate voltage is below threshold and no
current flows, triode where the current is nearly a linear function of drain voltage, and pinchoff where
the current is constant for fixed gate voltage.
CUTOFF REGION (VGS < VT)
The gate voltage in this case is not high enough to create a conducting channel so no conduction takes
place. A line on the x-axis of the characteristic can represent this case curve with ID = 0.
TRIODE REGION {(VGS VT) > VDS} [Could also be written VGD > VT],
As long as (VGS VT) > VDS, the voltage between the gate and every point in the channel is higher than
the threshold voltage. The approximate drain current under these conditions is
{ 2
ID = k 2(VGS VT ) VDS VDS }
239
This is the equation of a parabola. At (VGS VT) = VDS, equation reaches its maximum value of I D max =
2
kVDS and has a slope of zero. We will also note that, at that voltage, the voltage between the gate and the
channel at the drain end is just equal to VT; in other words, the threshold of pinchoff.
PINCHOFF {(VGS VT) < VDS}
The voltage between the gate and some parts of the channel in this region is less than the threshold
voltage. The current will remain constant as VDS increases.
ID = k (VGS VT)2
Thus, when VGS = Vth, physical pinch-off occurs at Vx (VDS) = 0 and no current can flow. Under this
condition VGD (at pinch-off) = Vth. Thus, the pinch-off is determined from the gate-to-drain voltage.
W
where, kn = COX mn = conductance parameter mA/V2 and ranges between 103 to 102 mA/V2.
L
mn = electron mobility (0.08 m2/V s), es = eo eins
eo = Permitivity of air (8.854 ¥ 1012 F/m),
eins = Permitivity of insulator (SiO2 = 4)
tOX = thickness of the insulator,
W = channel width, L = channel length
For an example, VGS Vth = 2 1 = 1 V, if VDS = 0, the conduction does not occur. For VDS > 1V
(say 2V), the conduction takes place and saturation occurs. In the linear region, the MOSFET looks like
a resistor nomenclatured as rd. An FET designed to have a low drain resistance (rd) has large width-to-
length (W/L) ratio. It is known that the resistance is proportional to the ratio of length to its cross-
sectional area. Since the width W is proportional to the area and the length L to the channel, the drain-to-
source resistance, rd, is inversely proportional to (W/L). Therefore, a FET designed for a high value of
rd has small (W/L) ratio and hence small value of kn.
6.11 MOSFET Inverter

The inverter stage is a basic building block for digital logic circuits and memory cells. A generic inverter
stage is illustrated in Fig. 6.30. It consists of two devices, a pull-up device, which is typically either a
bipolar junction transistor or an enhancement mode field effect transistor, and a pull-down device,
which might be another transistor, or a resistor, current source, diode, etc. The load represents the
input resistance of the following stage, which is typically a stage (or n stages) just like the original stage.
An important piece of information about an inverter stage is its static transfer characteristic, VO
versus VIN. In order to draw this characteristic we sum the currents into the output node of the inverter.
With all of these currents written as functions of VIN and VO, this sum yields the desired relationship
ipu (VIN, VO) = ipd (VIN, VO ) + iL (VO )
As an example, we consider the MOSFET inverter circuit shown in Fig. 6.30 (b) with an n-channel
MOSFET pull-down and a resistor pull-up. The MOSFET is characterized by its K-value and its thresh-
old voltage, VT (we will assume for simplicity that a is 1). To analyze this circuit we note first that with
a MOSFET pull-down, the static input current is zero and if the output is connected to the input of a
similar stage, the static load current will also be zero, and the equation above is simply ipu = ipd. With a
240
Fig. 6.30(a) Generic inverter stage Fig. 6.30(b) Resistive load MOSFET inverter
VDD VO
resistor pull-up, the pull-up current, ipu = and the pull-down current, ipd, is the MOSFET
R
drain current. This current depends on the gate-to-source voltage, VGS, which is the same as VIN, and
the drain-to-source voltage, VDS, which is the same as VO. With VIN less than VT, the pull-down current
is zero and VO is VDD. As VIN increases past VT, VO will initially be larger than (VIN VT), and the device
will be in saturation so that ipd will be k (VGS VT)2/2 = k (VIN VT)2/2. VO is found by setting ipd equal
to ipu :
ipu = ipd
The inverter circuit shown in the Fig. 6.30 (c) consists of a pull up MOSFET (T2) and a pull down
MOSFET (T1). The two transistors T1 and T2 may be thought like two resistors rd1 and rd2 in conduc-
tion. The gain of the amplifier depends on the ratio of these resistors. Transistor T2 acts as resistive load
and the ratio of the resistance of this load to the resistance of the driver transistor T1 can readily be
shown to be proportional to the ratio k1/k2 = c.
k1 (W / L)1 1/ rd 1 r
or, c= = = = d2
k2 (W / L) 2 1/ rd 2 rd 1
rd2 = c rd1.
Thus larger the value of c, larger is rd2 when both transistors are ON. The transfer characteristics of the
k
MOSFET inverter are shown in Fig. 6.31. It takes different form depending not only on c = n1 but
kn2
also on voltages VGG and VDD.
6.11.1 Operation
The gate and drain of transistor T2 are connected together making VGS2 = VDS2. Consequently T2 always
works in the pinchoff region (assuming V1 > VT). As VGS2 = VDS2 = VDD VO, the equation of current
for T2 is
ID2 = k2 (VDD VO VT2)2 (Saturated)
241
∑ VI < Vth (= 2V), T1 is cut-off. ID1 = 0 and hence ID2 = 0 (though T2 is ON but it can not conduct
as loop is not closed).
VO =
FG V r IJ @ V
DD d1
DD (rd1 >> rd2 and rd1 refers to OFF resistance of T1.
Hr +r K
d1 d2
∑ VI > Vth (=2V), T1 becomes ON and T2 is already ON. Now both drain currents ID1 = ID2 = ID
flow which develop a voltage drop across T1 given by
VDDrd1
VO =
rd1 + rd 2
Figure 6.30 nMOSFET inverter
For large value of c, rd2 (= crd1) becomes very large.
Hence, VO =
FG V r IJ @ 0
DD d1
Hr +r K
d1 d2
From above operations it is clear that for VI = VDD (= 1), VO = 0 and for VI < Vth, VO= VDD. Thus, the
circuit of Fig. 6.30 works as an inverter. Note that for large value of c, small value of VO is obtained as
observed from the transfer curve in Fig. 6.31 also.
Figure 6.31 indicates that the transfer curve of
the nMOSFET inverter may be used in linear or
non-linear range. If the inverter is to be used as an
amplifier, its output V0 must be linearly related to
input voltage VI .
If the inverter is to be used as a logic element, its
output voltage should switch from very high value
to very low value for infinitesimal increase in the
input voltage from Vth = 2 V. For different values
of c, the linearity of the curve is different, i.e. for
lower values of c, the linearity range is much more Figure 6.31 MOSFET inverter transfer
than for higher values of c. characteristics
242
6.12 pMOSFET
A schematic of the pMOSFET, its working model, V-I characteristics, and circuit symbol are shown in
Figs. 6.32, 6.33 and 6.34. The substrate voltage in the case of pMOSFET is most positive. Since the
gate voltage is VGG, it induces positive charge on the top surface of the SiO2 and negative charge at the
bottom surface as shown in Fig. 6.33. This in turn induces holes on the top surface of the n substrate
just below the gate contact.
Figure 6.32 pMOSFET schematic Figure 6.33 pMOSFET working model

Thus, formation of a p-type channel takes place between the source and the drain. This process of
enhancing a channel between the drain and the source is called surface inversion. The drain is also
connected to negative potential w.r.t. to the source that collects holes drawn through the channel. The
pinch-off occurs in a MOSFET when the drain-to-gate voltage is equal to a threshold voltage Vth(p). At
this value, the potential of the p-channel at point a is sufficiently negative w.r.t. to the substrate voltage
for the depletion region that forms to cut-off the channel.
The drain current for the pMOSFET is expressed as
2
ID (below pinch-off) = k p {2 VSG - Vth( p)VSS - VDS } VSS < VGS Vth(p) (6.12.1)
ID (above pinch-off) = kp {2(VSG Vth(p))2} VSS > VGS Vth(p) (6.12.2)
where, kp of the pMOSFET for the same geometry as an nMOSFET is approximately one third as large
as kn, while the value of Vth(p) is comparable to that of the Vth(n). Since Vth(n) and Vth(p) are comparable,
the subscript p and n are omitted to refer the threshold voltage Vth.
Figure 6.34 V–I characteristics and circuit symbol of pMOSFET

243
6.13 MESFET (GaAs device)

Silicon devices and circuit technology has been dominating the industry for the last three-decades.
Nevertheless, another semiconductor compound gallium arsenide (GaAs) is making its presence felt in
digital applications that require extremely high speed of operation and in analog circuits for high fre-
quency operations. The compound semiconductor GaAs offers much superior properties w.r.t. the
silicon counter part. The advantages of the GaAs devices are:
∑ High mobility of electrons (5 to 10 times that of silicon) at low electric field, i.e. for same input
voltage, more output current),
∑ High drift velocity (twice that in silicon),
∑ High mobility and high drift velocity contribute to high gm,
∑ High resistivity (up to 10,000 times that of silicon)
The high resistivity of the order of 106W cm to 108W cm suggests GaAs as a substrate useful in
providing isolation between devices with minimal processing steps in highly dense integrated circuits.
Also, the semi-insulating substrate produces very low parasitic capacitance that allows high-speed
propagation of signals. For this reason, GaAs devices have been used in microwave applications (in
gigahertz range). The structure for the GaAs transistors is similar to that of the MOSFET except
without oxide insulation between the gate and the channel as indicated in Fig. 6.35. The applications of
GaAs devices started in the 1975 in digital circuits as SSI frequency divider circuits.
The structure shown in Fig. 6.35 illustrates two-devices, namely, metal semiconductor (MESFET)
and Schottky-barrier diode (SBD). The Schottky-barrier diode is made of metal-semiconductor junc-
tion. The metal used for Schottky-barrier anode and gate of the MESFET is different from other metals.
It is aluminium (Al). The heavily doped n+-type GaAs is used between n-type and cathode metal contact
to keep the series parasitic resistance low. The compound metal AuGe is used to make ohmic contact
from cathode of SBD, source and gate.
The gate of the MESFET made from Schottky-barrier metal in direct contact with the n-type GaAs
forms the channel region. The channel length L is defined by the length of the gate electrode as indicated
in Fig. 6.35. Similarly, the width of the channel is W that is perpendicular to the page. In order to reduce
the parasitic resistance between the drain and source contacts and the channel, the two contacts are
surrounded with heavily doped n+ GaAs.
Since the main reason for using GaAs device lies in achieving high speed/high frequency of opera-
tion, the channel length should be as small as possible. The typical channel length ranges from 0.2 mm
to 2 mm. Transistors on the chip are made of this length, leaving width W to be specified by the
individual designer.
Mostly n-channel MESFETs are available in GaAs technology. This is because the drift velocity of
the electron in GaAs is many times high than that of holes and hence, p-type channel is unattractive. The
MESFET differs from the JFET because the electron velocity saturation occurs throughout the entire
conducting channel, rather than at the pinch-off portion of the channel. The velocity saturation occurs
at lower levels of electric field in GaAs as because the mobility of electrons in it is much higher than that
of the silicon. For manual calculation, we ignore the velocity saturation effect in GaAs. The current flow
in the MESFET depends significantly on VDS, even in constant-current region of the JFET. This phe-
nomenon occurs due to purposely tailored short conducting channel of the GaAs to reduce the switch-
ing response time. For short conducting channel, an effect known as channel-length modulation be-
comes important for all values of VDS as indicated in Fig. 6.36. This effect occurs in most of the
244
transistors, but is negligible. However, the channel length is not negligible in MESFET. Its effect is
accounted by multiplying the triode and constant current region V-I equation by VDS dependent term.
Figure 6.35 Structure of GaAs MESFET and Schottky-barrier diode and its circuit symbol
Figure 6.36 V-I characteristics of n-channel MESFET
6.13.1 Operation
The MESFET operates exactly like the JFET with Schottky-barrier metal playing the role of p-type gate
of the JFET. It forms a depletion region in the channel below the gate surface and the gate voltage (VGS)
controls the thickness of the depletion region. Thus, the source to drain current is a function of VGS as
well as VDS. The channel becomes tapered in shape and pinch-off actually occurs at the drain end of the
drain channel. The typical n-channel MESFET available are depletion type with threshold voltage Vth (ª
VP pinch-off) in the range of 0.5 V to 2.5 V. For the VGS = 0.7 V or so, the Schottky-barrier diode
between gate and channel conducts heavily and the gate voltage no longer controls the drain-to-source
current. The gate does not allow any current through it, and hence, this is also a definite advantage of
MESFET.
245
The enhancementmode MESFET though available, are very uncommon. The enhancement type
devices are normally achieved by extending the depletion through out the channel for VGS = 0V, blocking
the channel causing iD = 0. In order to enhance flow of the drain to source current, applying positive
gate voltage must slowly open the channel. This positive gate voltage reduces the thickness of the
depletion channel below the surface of the gate. The typical threshold ranges between 0.1 V to 0.3 V.
The above description suggests that VDS = VGS Vth as in the silicon FET. However, it has been
observed that the iD vDS characteristic of GaAs MESFET saturates at lower values of vDS and the
saturation voltage vDS(sat) does not depend upon value of vDS. This early saturation phenomenon occurs
because the velocity of the electrons in the channel does not remain proportional to the electric field
(E = VDS/L) as in the case of silicon; rather the electron velocity reaches the peak and then saturates, i.e.
becomes constant (independent of VDS ). The velocity saturation effect is even more pronounced in
short-channel device (L £ 1mm), occurring at values of VDS lower than VGS Vth.
Here, we observe that the forward bias majority (electrons) current of SBD flows through the
Schottky-barrier metal (anode). Unlike the pn-junction diode, minority carriers play no role in the opera-
tion of the SBD. As a result, the SBD does not exhibit minority storage effect that are responsible for the
diffusion capacitance. Thus, the SBD has only one capacitive effect, associated with the depletion-layer
capacitance.
6.13.2 MESFET Model

Curtice and Raytheon models
The drain current-voltage relationship in the Curtice model is expressed as
ID = 0 for VGS < Vth
2
ID = b (VGS Vth) (1 + lVDS) tanh (aVDS) for VGS > Vth (6.13.1)
2
where , b = transconductance parameter (A/V ) per unit area,
l = empirical channel-length modulation factor to account for the increase in ID(sat)
a = slope of ID VDS graph at VDS = 0 and it ranges from 0.3 (for long channel L = 20 mm to about
4 (for L £ 1mm).
The hyperbolic tangent function in Eqn. 6.12.1 may be approximated depending on the argument.
This approximation has been given the name Raytheon. It produces the drain current with VDS < 3/a as
3
1- F aV I
DS
ID = b (VGS - Vth ) 2 (1 + lVDS )

H 3 K (6.13.2)
1 + b(VGS - Vth )
(1 + lVDS )
ID = b (VGS - Vth ) 2 (1 + lVDS ) for VDS £ 3/a, (6.13.3)
1 + b(VGS - Vth )
where, b = doping tail extending parameter (to model velocity saturation).
A first order model of the MESFET that is suitable for manual calculation neglects the effect of
velocity saturation that is expressed as
ID = 0 for VGS < Vth, (cut-off)
2
ID = b{2(VGS - Vth )VDS - VDS}(1 + lVDS ) for VGS > Vth, VDS < VGS Vth (linear)
ID = b (VGS - Vth )2 (1 + lVDS ) for VGS > Vth, VDS > VGS Vth, (Saturation)
(6.13.4)
246
The difference between these expressions and expressions of JFET are :

∑ The channel-length modulation factor, 1 + lVDS is included in the equation of triode region also,
because the l of the MESFET is rather large and allows better fit in measured characteristics.
w
∑ Conductance parameter K µ is renamed b to correspond to MESFET literature.
L
The parameter value; transconductance gm and output resistance ro are expressed as
dID
gm = = 2 b(VGS Vth) (1 + lVDS), (6.13.5)
dVGS
dVDS 1
ro = = (6.13.6)
dI D b (VGS - Vth )2 l
For rather high value of l (0.1 V to 0.3 V), gives rise to small output resistance ro. This is a serious
drawback of the GaAs MESFET resulting into low voltage gain. Also rO decreases at high frequency.
Table 6.1 gives the typical values of device parameters in a GaAs MESFET.
Table 6.1 GaAs MESFET and Schottky diodes parameters
in L = 1mm normalized for w = 1mm
Vth 1 V l 0.1/V n 1.1
b 104A/V2 IS 1014A
Example
Obtain VGS1, b1, b2, VGS2, gm1, ro1, ro2 and small signal voltage gain when both devices T1 and T2 in Fig.
6.37 are driven into saturation with 1mA current.
As b µ W, b1 = 10 ¥ 104 mA/V2 and b2 = 90 ¥ 104 mA/V2
ID = b (VGS Vth)2 (1 + lVDS)
or, 90 ¥ 104(VGS2 + 1)2 (1 + 0 ¥ VDS2) = 90 ¥ 104 (VGS2 + 1)2 = 1 ¥ 103
or, (VGS2 + 1)2 = 1/9
or, VGS2 + 1 = 1/3
1 -2
or, VGS2 = -1 =
3 3
VGS1 =0V
dID
gm1 = = 2b(VGS1 Vth) (1 + lVDS)
dVGS
= 2 ¥ 10 ¥ 104(+1) = 20 mA/V
dVDS1 1
ro1 = = @ •,
dID1 b (VGS1 - Vth )2 l
dVDS 2 1
ro2 = = @• Figure 6.37
dID 2 b (VGS 2 - Vth )2 l
247
6.14 CMOS
CMOS is the abbreviation of the Complementary Metal Oxide Semiconductor. The CMOS arrangement
contains two-MOSFETs complementary to each other. In other words it is a cascaded connection of
one pMOSFET and the other nMOSFET as in Fig. 6.38.
The complementary MOSFET (CMOS) connected as inverter is shown in Fig. 6.39. Both pMOS and
nMOS are enhancement mode type of devices and designed with kn = kp. The pMOS has been labeled
as transistor T2 and nMOS as transistor T1.
6.14.1 Operation
∑ VI = 0, nMOS transistor T1 is cut-off and ID1 = 0. Since both transistors are connected in series;
if one is OFF, the current through the other transistor also does not flow. Hence, ID2 = 0 which
allows open circuit voltage VDD to appear at Vo.
∑ For pMOS VGS(p) = VDD and if VDD > Vth(p), the pMOS will have inversion channel with no
current drawn at the output, i.e. ID1 = ID2 = 0. This condition doubly assures that even though T2
is ON, ID2 does not flow because T1 is OFF. Here, VTP is threshold voltage of the pMOS transis-
tor.
∑ VI = VDD, VGS(p) = 0; pMOS transistor T2 is cut-off and ID2 = 0. If VDD > Vth(n), the nMOS
transistor T1 will have inversion of channel. Under this condition, the nMOS offers low resistance
and hence Vo = 0.
Figure 6.38 CMOS structure Figure 6.39 CMOS as inverter

For quantitative derivation of the transfer characteristic of the CMOS inverter following simplifying
assumptions are made
Vth(n) = |Vth(p)| = Vth, and kn = kp = k (6.14.1)
W
Here, it is to be noted that pMOS and nMOS need not be identical. Making the ratio inversely
L
proportional to the mobility of holes and electrons makes the value of kp and kn equal.
FWI FWI
@ 2.5 (6.14.2)
H LK pMOS H LK nMOS
248
The transfer curve of CMOS inverter is drawn

for Vth(n) = Vth(p = 3V, VDD = 10V, and kn = kp in
Fig. 6.40. For VI < 3 V, T1 is OFF, T2 is ON and
V0 = 10 V; while VI > 7 V, T2 is OFF and T1 is ON
and V0 = 0.
In the region A to D both T1 and T2 are ON. In
region AB, T1 is in saturation while T2 is in the
linear (active) region of operation. Hence (VDS1 =
V0) > (VGS1 Vth1= VI Vth1) and (VDS2 = VDD
V0) < (VGS2 Vth2 VI) = (VDD Vth2 VI).
Thus, the curve between A and B found by
equating Eqns. 6.14.1 and 6.14.2 as Figure 6.40 Transfer curve of the MOS inverter
2
d i V - V o ) - (V DD - V o) 2}
k n VI - Vth( n) = k p {2(VDD - VI - Vth( p) )(" (6.14.3)
"" ""! "" " """ ! DD "! " "!
VGS 1 VGS 2 V V DS 2 DS 2
Using the property of symmetry, T2 is saturated while T1 is in linear region. Hence the curve in the
CD region found as
2
kn 2 VI - Vth( n) Vo - Vo2 = k p VDD - VI - Vth( p)
{e j } e j (6.14.4)
""" """!
VGS 2
In the region BC both transistors T1and T2 are in saturation. The curve in this region is found as
2
kn (VI Vth(n))2 = k p VDD - VI - Vth( p)
e j (6.14.5)
""" """!
VGS 2
For the conditions kn = kp, and Vth(n) = Vth(p), Eqn. 6.14.5 reduces to
VDD
VI =
(both transistors are saturated) (6.14.6)
2
The curve in BC region is a vertical line, indicating an abrupt change in the output voltage as VI moves
across the value VDD/2. In practical circuits, however, the transition is not abrupt but is very steep,
signifying high gain. Important differences between JFET and MOSFETs are shown in Table 6.2.
Table 6.2 JFET and MOSFET parameters
Parameters JFET MOSFET

Input Resistance(rgs) >109 W >1013 W
Transconductance (gm) 1 mS to 2.5 mS 1 mS to 2.5 mS
Drain resistance (rd) 0.1 MW to 50 MW 1 KW to 50 KW
Reverse gate current (IGSS) 0.1 nA to 10 nA 0.1 pA to 10 pA
Capacitance Crss 1 pF to 4 pF 0.001 pF to 1 pF
"'
6.14.2 Dual Gate MOSFET

Some MOSFETs are dual gate devices. This means one MOSFET device has two separate gates as
shown in Fig. 6.41(a). One of the gates can be connected to ground to use the dual gate MOSFET as a
cascode amplifier as depicted in Fig. 6.41(b). For convenience both gates have been given zero bias
voltage. Since the input signal is connected to the lower gate of the dual gate MOSFET, the upper gate
is connected to the ground to form a cascode connection. The internal structure of the dual gate
MOSFETs is such that one MOSFET drives the other. Thus, the upper MOSFET in Fig. 6.41(c) works
as the load to the driving MOSFET (lower one). Figure 6.41(c) is cascode connection as the lower gate
MOSFET is connected in CS configuration and the upper gate is connected in CG configuration. Thus,
the unloaded gain of the cacode connection = gmRL. This way dual gate MOSFETs are very convenient
devices to build cascode amplifier. The cascode amplifiers are particularly useful at high frequencies as
it offers low input capacitance.
Both gates are formed on the same substrate so that both gates control the flow of the current. The drain
of one of them becomes the source of the other. This type of the MOSFET provides very high degree
of shielding of the gate of the 1st FET from the drain of the 2nd FET in comparison to the single gate
MOSFET. This arrangement reduces the input capacitance Cgs to as low as 0.005 pF to 0.03 pF and
hence is used at very high frequencies, say up to 500 MHz. The circuit symbol of dual gate MOSFET is
shown in Fig. 6.41 (a).
Figure 6.41 (a), (b), and (c) Dual gate symbols and circuits
1. Calculate the minimum value of VDS required value of VDS required to keep it in saturation
for an nMOSFET to operate in the pinch- is
off when VGS = 1 V with VP = 2 V, and VDS≥VGS VP = 1 ( 2) = 3 V
I DSS = 10 mA. What would be the 2
corresponding value of ID? F
ID = IDSS 1 -
VGS I F
= 10 ¥ 10 -3 1 -
1 I 2
Solution:
GH VP JK H -2 K
It is known that for an nMOSFET the VP is = 10 ¥ 103 (1 + 0.5)2 = 22.5 mA
a negative number. Hence, the minimum
#
2. Two IGFETs are connected in parallel to Solution:

form a composite IGFET as shown in Fig. For VGS 1 V, VP = VGS VDS = 1 V 3 V
6.42. Obtain the gm of the composite IGFET =`4 V.
if the drain current of each IGFET is Similarly, for VGS = 2 V, VP = 2 V 3 V
described as =` 5 V.
2 2
ID = 10 ¥ 103 1 +
FG VGS IJ ID1 = IDSS
F1 - V I
GS = 10 ¥ 103 1 -
F -2 I 2
H 5 K GH V JK P
H -5 K
Solution: = 102 (1 0.4)2 = 3.6 mA.
Since both IGFETs are connected in parallel,
2
the resulting drain current of the composite
ID2 = IDSS
F1 - V I
GS
= 10 ¥ 103 1 -
F -1 I 2
IGFET is GH V JK P
H -4 K
2
I¢D = 2 ¥ 10 ¥ 10 3 FG1 + V IJ GS = 102 (1 0.25)2 = 5.625 mA.
H 5K ID2 ID1 = 5.625 mA 3.6 mA = 2.025 mA
5. Obtain the pinch-off voltage of a p-channel
d I D¢
Hence, gm = = 2 ¥ 2 ¥ 10 ¥ 103 Silicon FET with its width = 2microns,
d VGS resistivity of 0.1 W m, dielectric constant of
12 and mobility of electrons = 0.05 m2/V.s.
FG1 + V IJ ¥ 1 = 8 ¥ 10 FG1 + V IJ
GS 3 GS
H 5K 5 H 5K Solution:
qNA = qNA
F m I = qN m
p D p
=
sp
GH m JK m
p p mp
1 1
= = = 200
r pm p 0.1 ¥ 0.05
Figure 6.42
a 2 qN A (2 ¥ 10 -6 )2 ¥ 200
3. Obtain the minimum value of VDS of an VP = =
n-channel JFET operating in the pinch-off 2e 2 ¥ 12 ¥ 8.85 ¥ 10 -12
region with Vpo = 4 V, VGS= 2 V, and IDSS 4 ¥ 200 100
= 10 mA. Calculate the corresponding value = = = 3.77 V
2 ¥ 12 ¥ 8.85 3 ¥ 8.85
ID .
6. What would be the pinch-off voltage of a
Solution: p-channel Germanium FET with its width =
VDS ≥ VGS Vpo = 2 ( 4) = 2 V 2micron, resistivity = 0.002 Wm, dielectric
2 constant of 16 and mobility of electrons =
ID = IDSS
F1 - V I GS
= 10 ¥ 103 1 -
F 1 I 2
0.18 m2Vs?
GH V JK P
H -2 K Solution:
3 2
= 10 ¥ 10 (1 + 0.5) = 22.5 mA F m I = qN m
p A p sp
4. Obtain change in the drain current for VDS qNA = qNA GH m JK m =
= 3 V and corresponding change in the VGS p p mp
from 2 V to 1 V.
#
1 1 8. A JFET at 300 K has electron density ND =

= = = 277.8 1023/m3, hole density NA = 1025/m3, relative
r pm p 0.02 ¥ 0.18
permiability er = 12, channel length L = 8 ¥
a 2 qN A (2 ¥ 10 -6 )2 ¥ 277.78 106m, channel height a = 0.2 ¥ 10 6 m,
Vp = = channel width z = 10 ¥ 106 m, electron
2e 2 ¥ 16 ¥ 8.85 ¥ 10 -12
mobility mn = 0.08 m2/V. sec, drain voltage
277.78 277.78 VD = 10 V, and gate VG = 1 V. Calculate;
= = = 3.92 V
2 ¥ 4 ¥ 8.85 8 ¥ 8.85 (a) the pinch-off voltage, (b) the pinch-off
7. An n-channel JFET has channel length L = current, (c) built-in voltage, (d) the drain
10 mm, channel width w = 100 mm, channel current, and (e) the saturation drain current
height without any depletion a = 2.5 mm. at VG = 0.
The donor level of the channel is ND = Solution:
1022/m3 and mobility of the electron mn = qND a 2
0.15 m2/Vs. The depletion width from each (a) The pinch-off voltage = Vp =
2e r e o
side of the gate junction is 0.25 mm. How
does this semiconductor bar behave without 1.6 ¥ 10 -19 ¥ 10 23 ¥ 0.04 ¥ 10 -12
forward biasing of the gate junction between =
2 ¥ 12 ¥ 8.854 ¥ 10 -12
two ends of the channel length? Refer
Fig. 6.43. 1.6 ¥ 10 -19 ¥ 10 23 ¥ 0.04
=
2 ¥ 12 ¥ 8.854
1.6 ¥ 10 2 ¥ 4
= = 3.012 V
2 ¥ 12 ¥ 8.854
m n q2 N D
2 za3
(b) ID = IDSS =
e sL
0.08(1.6 ¥ 10 -19 ) 2 10 46 ¥ 10
¥ 10 -6 ¥ (0.2 ¥ 10 -6 )3
Figure 6.43 =
12 ¥ 8.854 ¥ 10 -12 ¥ 8 ¥ 10 -6
Solution:
rL 0.08 ¥ 2.56 ¥ 10 -38 ¥ 10 46
R= and s = qmnND ¥ 10 ¥ 0.008 ¥ 10 -18
A =
12 ¥ 8.854 ¥ 10 -12 ¥ 8
L L
R= = 0.08 ¥ 2.56 ¥ 10 ¥ 10 ¥ 0.008
rA qm n N D (a - 2d )w = = 1.93 mA
12 ¥ 8.854 ¥ 8
10 ¥ 10 -6 N N
= (c) Built-in voltage = yo = VT ln D 2 A
1.6 ¥ 10 -19 ¥ 0.15 ¥ 10 22 ni
¥ 100 ¥ 10 -6 ( 2.5 - 0.5)10 -6
1023 ¥ 10 25
10 2 = 25 ¥ 10 -3 ln
= = 208 W (1.5 ¥ 1016 )2
0.48
#
1023 ¥ 1025 ÏÔ 1 1 + 0.9 2 Ê 1 + 0.9 ˆ 3/ 2 ¸Ô

= 25 ¥ 10 3 ln
2.25 ¥ 1032 Ì - + Á ˜ ˝
ÔÓ 3 3.012 3 Ë 3.012 ¯ ˛Ô
1016 = 1.93 ¥ 103 {0.33333 0.63 + 0.42}
= 25 ¥ 103 ln
2.25 = 1.93 ¥ 103 ¥ 0.0120 = 0.232 mA
= 25 ¥ 103 ln(0. 44 ¥ 1016) 9. Both n-channel MOSFETs in Fig. 6.44 are
= 25 ¥ 103 {16 ln 10 + ln (0.44)} identical and their V-I characteristics are
= 25 ¥ 103 {16 ¥ 2.303 0.811} expressed as
= 25 ¥ 103 (36.84 0.811)
= 25 ¥ 103 ¥ 36.029 = 0.9 V È V2 ˘
IDS = Í(VGS - 1)VDS - DS ˙ mA for
(d) ID = 1.93 ¥ 103 ÍÎ 2 ˙˚
VDS < (VGS - 1) ,
R| VDS
F
2 VDS + VGS + y 0 I 3/ 2
U|
- GH JK IDS = (VGS - 1)2 mA for VDS > (VGS - 1) .
|S V
P 3 VP
3/ 2
|V How much dc current flows through the
|| +
F
2 VGS + y 0 I | left MOSFET?
T 3 GH
VP JK |W Solution:
= 1.93 ¥ 10 3 For VGS = 2V, IDS = (VGS - 1) 2 mA = 1mA
Hence, dc current that can flow through
Ï 10 3/ 2 ¸
2 Ê 10 + 1 + 0.9 ˆ the left
Ô - Á ˜ Ô
Ô 3.012 3 Ë 3.012 ¯ Ô MOSFET = 2 1 = 1 mA.
Ì 3/ 2
˝
Ô 2 Ê 1 + 0.9 ˆ Ô
+ Á
Ô
Ó 3 Ë 3.012 ˜¯ Ô˛
= 1.93 ¥ 103
Ï 2 3/ 2 2 3/ 2 ¸
Ì3.32 - (3.95 ) + (0.63 ) ˝
Ó 3 3 ˛
Ï 2 2 ¸
= 1.93 ¥ 103 Ì3.32 - 7.85 + 0.50 ˝
Ó 3 3 ˛
= 1.93 ¥ 103 {3.32 5.23 + 0.33} Figure 6.44
= 1.93 ¥ 103 ¥ 1.58 = 3.05 mA 10. Show that the drain current of an nMOS is
(e) ID(sat) = IDSS given by
Ï1 Ê V + y ˆ 2 Ê V + y ˆ 3 / 2 ¸
Ô Ô ID = m nCox
W LM V2
(VGS - Vth )VDS - DS
OP
GS o GS o
Ì Á ˜ + 3Á ˜ ˝ L N 2 Q
ÔÓ 3 Ë VP ¯ Ë VP ¯
˛Ô LM 2
OP
VDS
= 1.93 ¥ 103 = b (VGS - Vth )VDS -
N 2 Q
#!
11. Calculate the drain current of an nMOS VDS = 4 V , eox = 3.97eo, ID = 144 mA, tox
transistor for VGS = 0 V, 1 V, and 2 V with = 400 Å.
the device parameters as W = 5 mm, L = Solution:
1 mm, VDS = 0.1 V, Vth = 1 V, mnCox =
25 mA/V2. e ox 3.97 ¥ 8.854 ¥ 10 -14
Cox = =
Solution: t ox 400 ¥ 10 -8
For VGS = 0 V < Vth = 1 V, channel does = 0.088 × 106
not form, ID = 0 144 mA = 0.088 × 106 mn × (4 1.99)2
For VGS = 1 V = Vth, channel does not = 0.355 × 106 mn,
form, ID = 0
144
For VGS = 2 V > Vth = 1 V, channel forms mn = = 405 cm2/s
0.355
and the equation of ID is
14. In an enhancement mode nMOS the de-
ID = m nCox
W LM V2
(VGS - Vth )VDS - DS
OP vice parameters were given as VGS = 3 V,
L 2 VDS = 5 V, Vth = 1 V, mnCox = 25 mA / V2,
N Q ID = 0.25 mA, find out the value of aspect
= 25 ¥ 10 -6
5 LM
(2 - 1) 0.1 -
0.12 OP ratio of the transistor. Also obtain length
1 2 and width of the channel.
N Q Solution:
= 125 ¥ 10 -6 ( 0.1 - 0.005)
W
0.25 mA = m n Cox (VGS - Vth ) 2
= 125 ¥ 10 -6 (0.1 - 0.005) 11.875mA . L
12. For the device parameters given in prob- W
lem no.11, obtain the transconductance of = 25 ¥ 10 -6 (3 - 1) 2 ,
L
an nMOS in the linear and saturation re-
gion with VDS = 0.1 V and VDS = 4 V W 0.25
= ¥ 10 3 = 2.5
(>>VGS-Vth). L 25 ¥ 4
Solution: If we assume L = 1 mm , then W = 2.5 mm.
W 15. Obtain ON resistance of an NMOS tran-
gm = m n Cox VDS in the linear region
L sistor with VGS = 3 V , Vth = 1 V, m nCox
5 = 25 mA / V2 , W = 3 mm , L = 1 mm.
= 25 ¥ 10 -6 VDS = 125 ¥ 10 -6 VDS Solution:
1
= 12.5 mA ∂I D W
= m n Cox
W ∂VDS VDS Æ 0
L
gm = m nCox (VDS - Vth ) in the saturation
L (VGS - Vth ) - VDS
5
region = 25 ¥ 10 -6 ( 4 - 1) = 375 mA.
1 W
@ m n Cox (VGS - Vth )
13. Calculate the mobility of electron in an L
nMOS transistor with the device param-
∂VDS L
W rd(ON) = =
eters as = 1, VGS = 4 V, Vth = 1.99 V, ∂I DS m n Cox W (VGS - Vth )
L
#"
1 10 6 17. Determine the small signal parameters of

= = = 6.67 KW FET for given value of IDSS = 5 mA, VGS =
25 ¥ 3 ¥ 10 6 (3 1) 150
1 V, Vp = 4 V, Early voltage VA = 90 V.
16. The internal parameters of an nMOS tran-
Solution:
sistor are NA = 1016 / cm3, the concentra- 2
tion of source and drain is ND = 1020 / cm3,
IDQ = I DSS
F1 - V I GS
for constant VDS .
the side wall doping = NA(SW) = 5 × 1016 / GH V JK p
cm3 , oxide layer thickness = tox = 400 Å,
the junction depth = 1 mm. Calculate the ∂ IC - 2 I DSS Ê VGS ˆ
junction capacitance with and without side gm = = Á1 - ˜ ,
∂VGS VDS = K
Vp Ë Vp ¯
wall doping profile.
Solution: VA
rds =
I DQ
ND NA 1020 ¥ 1016
fo = VT ln = 0.026ln 2
ni2 2.25 ¥ 10 20 F 1 I 45
IDQ = 5 1 - = mA ,
1016
H 4 K 16
= 0.026 ln = 0.026 ln (0.44 × 1016)
2.25 gm =
10
1- F
1
=
30
mS ,
I
= 0.026 ln(0.44) +0.026 × 16 ln (10) 4 H
4 16 K
= 0.02 + 0.92 = 0.9 V 90 ×16
rds = KÙ = 32 KW
45
eo q Ê N A ND ˆ 1
CJ = 30
2 ÁË N A + N D ˜¯ fo m = gmrd = ¥ 32 = 60
16
12 ¥ 8.854 ¥ 10 -14 18. An enhancement-type nMOS transistor is
shown in Fig. 6.45 with its threshold volt-
=
FG
¥ 1.6 ¥ 10 -19 10 20 ¥ 1016 1 IJ age Vth = 2 V.
2 H
10 20 + 1016 0.9 K Specify its range of operation for (a) VD =
0.5 V, (b) 1 V, (c) 5 V.
= 94.44 ¥ 10-17 = 9.444 ¥ 10-16
= 3.1 × 10 8 F / cm2
e o q Ê N A ( SW ) N D ˆ 1
CJ =
2 ÁË N A + N D ˜¯ f o
Figure 6.45
12 ¥ 8.854 ¥
=
FG
10 -14 ¥ 1.6 ¥ 10 -19 10 20 ¥ 5 ¥ 1016 1 IJ Solution:
2 10 20 + 5 ¥ 1016 0.9
H K (a) VD = VDS = 0.5 V < (VGS Vth) = 3 2
= 1 V fi Triode region
= 9.444 ¥ 5 ¥ 10-16 (b) VD = VDS = 1 V ≥ (VGS Vth) = 3 2 =
8 2 1 V fi Saturation
= 6.87 × 10 F/cm
##
(c) VD = VDS = 5 V ≥ (VGS Vth) = 3 2 = W

1 V fi Saturation COX mn = 2 mA/V2,
L
19. Obtain the value of drain current in Prob-
1
lem 18 if m nCox = 20 mA/V2, W = 100 mm, VGS = 4 V, VDS = 5 V, ID = ¥ 2{4 2)2
and L = 10 m m neglecting the dependence 2
of ID over VDS. = 4 mA
Solution: DVDS 1
(a) VDS = 0.5 V < VGS Vth = 1 V, rd = =
DI D W
COX mn (VGS Vth )
W V2 L
IDS = COX mn {(VGS Vth )VDS DS }
L 2
1 103
= = = 0.25 KW
100 0.25 2(4 2) 4
= 20 {(3 2)0.5 }
10 2 21. An enhancement-type nMOS transistor
= 200 (0.375) = 75 mA
W
1 with COX mn = 0.2 mA/V2, Vth = 2 V and
(b) VDS = 1V = VGS Vth, IDS = COX mn L
2
l = 0.02/V operates at VGS = 4 V. Obtain
W
= {VGS Vth}2 drain current for VDS = 2 V and 5 V and the
L drain resistance at this value of VGS.
1 100
= ¥ 20 (3 2)2 = 100 mA Solution:
2 10
1 VGS Vth = 4 2 = 2 V = VDS fi Saturation
(c) VDS = 5 V > (VGS Vth) = 1 V, IDS =
2 W
IDS = COX mn (VGS Vth)2 (1 + lVDS)
W 2 2L
COXmn {VGS Vth)
L 0.2 2
= (2) (1 + 0.02 ¥ 2) = 0.4(1.04)
1 100 2
= ¥ 20 (3 2)2 = 100 mA = 0.416 mA
2 10
20. An enhancement-type nMOS transistor W
IDS = COX mn (VGS Vth)2 (1 + lVDS)
with voltage Vth = 2 V conducts drain cur- 2L
rent ID = 1 mA for VGS = VDS = 3 V 0.2 2
neglecting dependence of ID over VDS in = (2) (1 + 0.02 ¥ 5) = 0.4(1.1)
2
saturation. Obtain the value of ID for VGS = = 0.44 mA
4 V and VDS = 5 V. Also calculate the drain
to source resistance rd for small value of Increase in ID = DID = 0.44 0.416
VDS and VGS = 4 V. = 0.024 mA, DVDS = 5 2 = 3 V
Solution: 3V
rd = = 125 KW
1 W 0.024 mA
1 mA = COX mn {VGS Vth)2
2 L 22. An enhancement-type nMOS transistor
1 W 1 W has COX mn = 20 mA/V2, W = 100 mm,
= COXmn {3 2)2 = COX mn
2 L 2 L L = 10 mm, VA = 100 V, Vth = 1 V, l = 0.5
#$
V 1/2, and 2f f = 0.6 V. Calculate the value of a depletion-type nMOS transistor

of Vth at VSB = 4 V and also at VGS = 3 V W
and VDS = 5 V. Obtain drain current ID for having Vth = 2 V and mnCox = 2 mA/
L
VSB = 3 V. What is output resistance ro for
each of the two cases? V2. How much is the corresponding drain
current ID?
Solution:
Solution:
Vth = Vto + l{ 2f f + VSB 2f f }
VGS = 1 V, Vth = 2 V, VGS Vth = 1 +
2 = 3V fi Saturation
= 1+ 0.5{ 0.6 + 4 0.6} = 1.7 V
1
VGS = 3 V, VDS = 5 V, VSB = 0 V, Vth = VDS(min) = VGS Vth = 3 V, IDS = 2 (3)2
W 2
Vto = 1 V, IDS = COX mn (VGS Vth)2 = 9 mA
2L
24. Obtain the voltage that will appear at the
Ê VDS ˆ
ÁË1 + V ˜¯ source neglecting the effect of VDS on ID
A in case of a depletion-type nMOS transis-
100 Ê 5 ˆ tor shown in Fig. 6.46 having Vth = 2V
= 20 (3 1)2 Á1 + ˜ =100 ¥ 4(1.05)
20 Ë 100 ¯ W
= 420 mA and mn COX = 4 mA/V2.
L
At VSB = 4 V, Vth = 1.7 V, Solution:
Ê V ˆ VDG = 5 V > Vth fi Saturation region.

W
IDS = COX mn (VGS Vth)2 Á1 + DS ˜
2L Ë VA ¯ W
IDS = COX mn (VGS Vth)2
2L
100 Ê 5 ˆ
= 20 (3 1.7)2 Á1 + 1
20 Ë 100 ˜¯ = ¥ 4 (VGS + 2)2 = 2 mA
2
= 100 ¥ (1.3)2(1.05) = 177.5 mA
or, (VGS + 2) = ± 1 V, VGS = 1 V, 3 V
V 100
ro = A = 1 100
ID VGS = 3 V will result in cut-off (as VGS
¥ 200 (3 1) 2
2 10 < Vth = 2 V).
100 Hence, VGS = 1 V, VS = VG VS = 0 VS
= = 0.025 KW
1000 ¥ 4 VS = 1 V
VA 100
ro = = 1 100
ID ¥ 200 (3 1.7)2
2 10
100
= = 0.059 KW
1000 ¥ 1.69
23. Obtain minimum rd required to operate in
the saturation region with VGS = 1 V in case Figure 6.46
#%
The channel length modulation is ne-

glected (l = 0)
VDG = 0, MOSFET operates in saturation
region.
W
IDS = COX mn ((VGS Vth)2
2L
100
Figure 6.47 = 20 (VGS Vth)2 = 100(VGS Vth)2
20
25. Design the circuit in Fig. 6.47 to yield a = 0.4 ¥ 103 (VGS Vth)2 = 4, VGS Vth
drain current ID of 0.4 mA. Obtain the dc = ± 2, VGS = 4 V, 0 V
value of VO and the value of R.
VGS = 0 V does not make any sense as it
Solution: is less than Vth. Hence, VGS = 4 V.
For design parameters, let Vth = 2 V, mnCox
= 20 mA/V2, L = 10 mm, and W = 100 mm. 10 4
Thus, VO = 4 V and R =
0.4 mA
= 15 KW
Questions for Practice 5. What is meant by static and dynamic RAM?

Sketch the circuits of (a) a MOS inverter
1. Explain operation of a MOSFET and its use and (b) a 1-bit memory cell using MOSFETs
as an amplifier. and explain how they operate.
2. Draw the sectional-view and the VI-
characteristics of a JFET. What is meant by
pinch-off voltage VP? Give the small signal Multiple Choice Questions
equivalent circuit of a JFET and prove that
the transconductance gm of a FET is given 1. The main types of field effect transistors are
by (a) UJT and FET
2 (b) BJT and FET
gm = I D ¥ I DSS (c) JFET and MOSFET
VP 2. The input impedance of the field effect
3. Draw the h.f. equivalent circuit of a transistor is
MOSFET and explain the significance of the (a) very low w.r.t. BJT
different elements of the circuit. (b) very high w.r.t. BJT
4. With the help of suitable band diagrams, (c) medium w.r.t. BJT
distinguish between conditions of 3. The field effect transistor is an
accumulation, depletion and inversion in (a) unipolar device
relation to a MOS structure. What is the (b) bipolar device
condition of strong inversion? (c) none of the above
#&
4. The doping of substrate is (c) complete short circuit between input

(a) high w.r.t. the source or drain and output
(b) low w.r.t. the source or drain 14. The field effect transistor is
(c) moderate w.r.t. the source or drain (a) less noisy w.r.t. BJT
5. The n-channel field effect transistor has (b) more noisy w.r.t. BJT
(a) p-type substrate 15. For quiet reception the front end of FM tuner
(b) n-type substrate contains
(c) no substrate (a) BJT (b) FET
6. The polarity of the gate w.r.t. the source in (c) UJT (d) SCR
n-channel JFET is 16. The gain-bandwidth of the field effect
(a) positive (b) negative transistor is
(c) neutral (a) high w.r.t. BJT
7. The charge carriers in an n-channel JFET (b) low w.r.t. BJT
are (c) equal to the BJT
(a) electrons (b) holes 17. The IDSS of the FET is
(c) protons (d) neutrons (a) independent of pinch off voltage
8. The drain current of the n-channel JFET (b) dependent on pinch off voltage
increases with 18. At pinch-off, the drain current becomes
(a) increasing positive voltage at the gate (a) zero (b) infinite
(b) decreasing positive voltage at the gate (c) constant
(c) constant voltage at the gate 19. The high frequency gain of the FET is mainly
9. The JFET are normally used in limited by
(a) Ohmic region (a) Cgs (b) Cds
(b) saturation region (c) Cgd
(c) cut-off region 20. In an FET
10. The parameters of JFET are related as (a) both junctions are forward biased
(a) gm = rd/m (b) gm = m/rd (b) both junctions are reverse biased
(c) gm = mr d (c) one junction forward biased and the
11. The input resistance of MOSFET is of the other reverse biased
order of 21. When the reverse bias between the gate and
(a) 100 MW (b) 10 W the source increases, the pinch-off voltage
(c) 1 KW will become
12. The field effect transistors are (a) more (b) less
(a) voltage controlled device (c) remains unaffected
(b) current controlled device 22. For an amplifier, the FET is operated in
(c) neither current nor voltage controlled (a) VVR region
device (b) pinch-off region
13. The field effect transistor offer (c) avalanche breakdown region
(a) low degree of isolation between input 23. If the reverse bias in a FET is increased, its
and output gm will
(b) high degree of isolation between input (a) increase
and output (b) decrease
#'
(c) not be affected (a) 1.5 V (b) 1.4 V

(d) suddenly falls to zero (c) 5 V (d) 0
24. The minimum value of VDS to operate in the 30. The r d(O N) of an n-channel JFET with
pinch-off region with Vpo = 4 V, IDSS = parameters in prob. 29 alongwith L = 20 mm,
8 mA, and VGS = 3 V is Z = 103 m, mn = 0.13 m2/Vs is
(a) 4 V (b) 1 V (a) 1 K (b) 961 K
(c) 4 V (d) 7 V (c) 0.931 K (d) 0.0961 K
(Hint: VDS = VGS Vpo = 3 V ( 4 V) 31. The IDSS of an n-channel JFET with ND =
=1 V) 1022/m, a = 0.5 mm, L = 20 mm, z = 103 m,
25. The drain resistance in Prob.24 is mn = 0.13 m2/Vs, Vpo = 5 V, is
(a) 2.5 K (b) 0.25 K (a) 10.4 mA (b) 100.4 mA
(c) 1 K (d) 4 K (c) 1.04 mA (d) 0.104 mA
26. The minimum value of VDS in problem-24
32. In a MOSFET, a low threshold voltage can
with VGS = 0 V is
be achieved by
(a) 1 V (b) 4 V (a) using the gate dielectric of lower di-
(c) 7 V (d) 1 V electric constant
(e) 4 V (b) increasing the substrate concentration
27. The drain resistance for problem 26 is (c) decreasing the substrate concentration
(a) 0.25 K (b) 1 K (d) using a thick gate oxide.
(c) 4 K (d) 2.5 K
33. In a MOSFET the threshold voltage can be
2 lowered by
FG Hint: I = I FG
D
V
GS
DSS 1 - V
I
JK ,
dI D
= 2IDSS (a) increasing the gateoxide thickness
H H po dVDS (b) reducing the substrate concentration
(c) increasing the substrate concentration
F1 - V I F - 1 I
GS (d) using the dielectric of lower constant.
GH V JK GH V JK
po po 34. JFETs are normally used in
(a) Ohmic region
2
3 Ê0ˆ Ê 1ˆ (b) saturation region
= 2 ¥ 8 ¥ 10 Á1 - - (c) cut-off region
Ë - 4 ˜¯ ÁË - 4 ˜¯
(d) breakdown region.
= 4 mA/V rd =
dVDS
=
1
= 250 W
IJ 35. For values of drain voltage smaller than gate
dID 4 mA/V K voltage, a MOSFET acts as a voltage
controlled
28. The gm of problem-25 is (a) current source
(a) 4 mS (b) 4 mS (b) resistor
(c) 3 mS (d) 0 (c) voltage source
(e) • (d) capacitor.
29. The Vpo of an n-channel JFET with ND =
1016 /cm3, er = 16, eo = 8.854 ¥ 10 14 F/cm,
a = 0.5 mm is
$

1. (c) 2. (b) 3. (a) 4. (b) 5. (a) 6. (a)
7. (a) 8. (a) 9. (b) 10. (b) 11. (a) 12. (a)
13. (b) 14. (a) 15. (b) 16. (b) 17. (b) 18. (c)
19. (a) 20. (b) 21. (b) 22. (b) 23. (b) 24. (b)
25. (c) 26. (b) 27. (a) 28. (b) 29. (b) 30. (d)
31. (a) 32. (c) 33. (b) 34. (a) 35. (b).
7
Biasing
7.1 Introduction
Each of the two junctions of the BJT has a potential barrier across it that does not allow both type of
charge carriers (holes or electrons) to cross the junction and hence, current does not flow through any
of the junctions. This forces the BJT to be considered as an idle device and hence it does not act (work).
In order to bring the BJT from idle to active state, appropriate external dc potential must be applied
across both junctions to allow current carriers to cross the junctions.
The emitter serves as the supplier of current carriers (holes or electrons). The external dc voltage
applied across Emitter-Base Junction (EBJ) must cancel the reverse bias (potential barrier) inherently
present and must force the current carriers from emitter region to cross the EBJ and go to the collector
region. This external dc potential applied across the EBJ is known as forward bias as it enhances the
flow of current carriers across it. As soon as these charge carriers reach the collector region, the
collecter should collect them easily. So the collector terminal should be connected to dc voltage of the
type that should attract these carriers. Thus, a p-type collector region must be connected to the negative
terminal of the battery and an n-type collector region must be supplied with the positive terminal of the
battery. This type of external dc voltage adds to the potential barrier across CBJ and such external dc
potential applied across CBJ is called reverse bias that increases the depletion width also.
The external dc potential applied across the EBJ should always be forward bias and CBJ should
always be reverse biased for normal operation of the BJT. The application of external dc voltage across
the two-junctions of BJT is known as biasing.
By now it is clear that the external dc potential must be applied across two-junctions to bring the
transistor into the conduction region. The dc voltage across the collector emitter (VCE), the dc collector
262
current (IC), and the dc base current (IB) through the BJT define the quiescent Q-point that is decided
by its uses. For example, the Q-point of the BJT must be selected on the two extremity points B and C
in Fig. 7.1 along the dc load line on the output characteristics of the BJT if it is to be used as a switch.
On the other hand for class-A amplification, the Q-point must be in the middle of the linear range of the
output characteristics at point A in Fig. 7.1. This allows maximum fluctuations in the collector current
and collector voltage without exceeding the dissipation power rating of the transistor so that the output
waveform is just the amplified replica of the input signal. If care is not taken, either positive or negative
half-cycle of the signal may be (output waveforms are just the amplified replica of the input) clipped off
and distortion may occur. This is explained in Figs. 7.2 and 7.3.
Figure 7.1 Selection of the best Q-point
Figure 7.2 Q-point near saturation

Biasing
263
We conclude that once the quiescent point is selected, it should remain fixed otherwise transistor
amplifier designed for amplification may start behaving as a switch. It may so happen that due to change
in temperature, manufacturers spread in active parameters, variation in the voltages and tolerance of
resistances, etc may act cumulative and shift the Q-point to B, i.e. from active region to saturation
region. Hence, transistor changes its action as an amplifier to a switch. The stabilization of operating is
most essential since the amplifiers amplitude, phase and frequency responses are dependent on the Q-
point. In Fig. 7.4 dotted lines indicate the change in collector current curve with increase in the temperature.
The Q-point can change with any one or many parameters together. Thus, in order to have a quantitative
analysis of this change, the quiescent collector current must be related with all such types of parameters
that bring in the change.
Figure 7.3 Q-point near cut-off point
Figure 7.4 Variation of output characteristic with temperature

264
7.2 Fixed Base Bias

The simplest biasing circuit with a fixed resistor connected between the base and the external dc supply
voltage VCC can be seen in Fig. 7.5. For linear operation, the Q-point should be chosen such that VCC is
divided equally between VCE and drop across its load resistance RC. In order to find the quiescent
collector current following points must be kept in mind:
∑ Form a close loop including the external battery and the EBJ as shown by dotted line in Fig. 7.5.
∑ Write the KVL equation around the input loop in Fig. 7.5 as
VCC = RB I B + VBE (7.2.1)
The dc equivalent circuit of the BJT is drawn in Fig. 7.6. From Fig. 7.6,
a
IC = bI B + 1 + b ICO f (7.2.2)
Figure 7.5 Fixed bias
Figure 7.6 Equivalent circuit of fixed bias

IC - (1 + b ) ICO
VCC = RB + VBE
b
b(VCC - VBE ) = RB IC - (1 + b ) ICO RB

Biasing
265
b (VCC - VBE ) + (1 + b ) ICO RB

IC = (7.2.3)
RB
Equation 7.2.3 reveals that the quiescent collector current is a function of VBE , b, ICO, VCC, and RB.
The biasing of the BJT should be such that IC = ICQ should not change irrespective of changes in these
quantities either separately or collectively. The amount of change in ICQ due to change in any of the
variables of Eqn. 7.2.3 is defined as the stability factor. Thus, stability factor is a measure of deviation
in the quiescent collector current for the corresponding deviation in VBE, b, ICO, VCC, and RB. Thus,
stability factors against different variables are defined as
DICQ DICQ DICQ DICQ DICQ
SI = , SVBE = , Sb = , SVCC = , SRB = (7.2.4)
DICO DVBE Db DVCC DRB
The VCC is supplied by a stabilized power supply and hence change in VCC is not considered. Selecting
RB of a precision type resistance, change in RB is normally not considered for the change in ICQ. For one
particular transistor, unless unit replacement takes place, change in ICQ due to change in b is assumed to
be negligible. Thus, due to change in temperature usually ICO and VBE change and the stability factors,
for the moment are restricted to changes in ICO and VBE only. Stability factor SI for Fig. 7.5 can be
obtained by differentiating Eqn. 7.2.3 with reference to particular variable such as
DICQ
SI = SI = =1+ b (7.2.5)
CO
DICO
It is clear that a small change in ICO, i.e DICO gets multiplied by (1+b) that becomes a significant
quantity depending upon the value of the b. Thus, the small changes in the ICO brings large change in the
Quiescent collector current ICQ and the Q-point gets shifted from point A to A1. The value of ICO is
negligibly small but (1 + b )ICO is appreciable that brings significant change in the quiescent collector
current. So stability of the bias point-A in Fig. 7.7 for this circuit is very poor as demonstrated by
Eqn. 7.2.5 and Fig. 7.8 because ICO increases with temperature. Thus, operating point-A of Fig. 7.5 is
not stable and shifts as illustrated in Fig. 7.8 and can lead to the thermal runaway.
Figure 7.7 Shift of Q-point

266
Figure 7.8 Thermal runaway in fixed bias
We understand by now that the stability factor is a misnomer. As per the word meaning of stability
factor, higher the value of the stability factor, more should be the stability of the quiescent point. But
actually it is the reverse way. Lower the value of the stability factor, more stabilized is the Q-point.
The value of the stability factor falling in the range of 2 to 9 is supposed to be good. Higher than this
value brings instability in the Q-point. The theoretical best value of stability factor should ideally be zero
that is practically impossible because to set SI = 0 either DICQ = 0 or the change in ICO, i.e. D ICO = •.
For infinite DICO, the appreciable change in ICQ is inevitable. Hence, first statement is not valid and SI
can not be zero rather SI(min) > 1. Thus, the ideal maximum and minimum values of SI could be
∑ SI(max) = µ
∑ SI(min) = 1
SI(min) = 1 means there are equal changes in ICQ and ICO. Since ICO is a very small fraction of ICQ the
magnitude of DICQ and DICO cannot be the same. Hence, we cannot obtain the minimum values of SI = 1
that has been assumed as the ideal value. Thus, for all practical purposes this value of SI will always be
greater than unity.
Example 7.1
Obtain the value of ICQ, VCEQ and RB, if RC = 1 K, VCC = 10 V, and b = 100 are used in the circuit of
Fig. 7.5 containing germanium transistor.
Solution
Assuming equal drops across the transistor and the load,
10 5 ICQ 5 mA
VCEQ = VRL = = 5 V, ICQ = = 5 mA, I BQ = = = 50 m A
2 1K b 100
VCC = 10 V = RB I B + VBE = 50 m ARB + 0.2 V
10 - 0.2
RB = = 196 K W
50 m A
Hence, the quiescent point is defined as
VCEQ = 5V , ICQ = 5mA ,and I BQ = 50 m A
The ICO or ICEO starts rising with increasing temperature that in turn causes ICQ to rise as indicated
in Fig. 7.8. Increase in ICQ heats the junction more and increases the temperature to cause ICO or ICEO
to increase further. This process repeats unless the transistor gets finally damaged. This phenomenon
is known as thermal runaway. This is explained in the Fig. 7.8. Hence, for all practical purposes the
value of S1 will always be greater than unity.
Biasing
267
Advantages of fixed base bias

∑ The biasing circuit is the simplest as only RB is used.
∑ The bias conditions can be fixed easily.
∑ No loading occurs as a large resistor is connected between the base-emitter junction.
Disadvantages of fixed base bias

∑ Very poor stabilization of the Q-point and
∑ Chances of thermal runaway are high as stability factor is high.
7.3 Self Bias

As per the word meaning, self-bias circuit provides appropriate bias to both junctions of the BJT. The
self-bias circuits can be divided into three different categories that are given below:
∑ Voltage feedback type
∑ Current feedback type
∑ Combination of voltage and current feedback types
7.3.1 Voltage Feedback Type

The voltage feedback type of biasing is also called the collector to base bias circuit. If the base bias
resistor RB of Fig. 7.5 is connected between the base and the collector as shown in Fig. 7.9, the
resulting arrangement is called collector to base bias. A part of the output voltage is fed back to the input
through resistance RB. The stability factor of Fig. 7.9 can be shown to have improved to a certain extent
w.r.t. that of Fig. 7.5.
The output loop equation for Fig. 7.9 can be written as
VCC = RC1CQ + VCEQ (7.3.1)
VCEQ = VCC RCICQ = RBIB + VBE (7.3.2)
With increasing collector current ICQ (due to the rise in temperature), RCICQ increases and hence
VCEQ decreases as VCC is constant. Hence, voltage drop across collector to emitter VCEQ = RBIB + VBE
also decreases. Here VBE is assumed to be constant, so decreasing VCEQ decreases the base current IB
and hence ICQ = (VCC VCEQ)/RC also decreases. As soon as the base current is decreased, collector
current also decreases proportionately.
Figure 7.9 Collector to base bias

268
Figure 7.10 Simplified collector-to-base bias
Thus, negative voltage feedback brings down the collector current back to the original value. On the
contrary, decreasing collector current ICQ due to decrease of temperature decreases RCICQ and hence,
VCEQ increases. So voltage drop across RB increases that forces the base current to increase to bring the
collector current back to its original value. The relevant current and voltage relationships are obtained
from Fig. 7.10 as
ICQ = bI B + (1 + b ) ICO
ICQ (1 + b ) ICO
IBQ = - (7.3.3)
b b
VCC = RC ( ICQ + IBQ ) + RB IBQ + VBE = RC ICQ + ( RC + RB ) IBQ + VBE
ICQ (1 + b ) ICO
VCC - VBE = RC ICQ + ( RC + RB ) - ( RC + RB )
b b
b (VCC - VBE ) + (1 + b ) I CO ( RC + RB )
Hence, ICQ = (7.3.4)
RB + (1 + b ) RC
The stability factor for this circuit is
DICQ 1+ b
SI = SICO = = (7.3.5)
DICO 1 + bRC
RC + RB
As the stability factor in Eqn. 7.3.5 is much less than the stability factor in Eqn. 7.2.5, the biasing
circuit of Fig. 7.9 is much more stabilized than the circuit of Fig. 7.5. The process of checking the rising
tendency in ICQ in the case of collector to base bias due to rise in temperature is shown in Fig. 7.11. The
increase in temperature raises ICO or ICEO that causes ICQ to rise. The RCICQ increases forcing VCEQ to
decrease, that means VBE + RBIB is decreased. Here VBE has been assumed to be constant. Hence
decrease in this is caused by decrease in IB only because RB is fixed. As IB decreases ICQ also decreases.
Hence, increasing temperature does not allow ICQ to increase in this case. As VBE decreases with rising
temperature, that brings the ICQ back to its original value again.
Biasing
269
Figure 7.11 Collector-base bias checks thermal instability
7.3.2 Disadvantages of Collector to Base Bias

The collector voltage is 180° out of phase w.r.t. the base voltage. This 180° out of phase voltage from
the collector point is fed back through the collector to base resistance RB to the base point. Hence, it
cancels the input voltage by the fed back amount. Thus, the effective voltage at the base terminal in this
configuration goes down and hence, gain of the amplifier also goes down.
This problem of Fig. 7.12 can be solved using a bypass capacitor C at the junction of R1 /2 and
R1 /2 that can swamp the feedback voltage as shown in Fig. 7.13.
Figure 7.12 Split R1 bias
Figure 7.13 Split R1 with a bypass C bias
7.3.3 Current Feed-back Type

An emitter resistance RE when connected from emitter to the ground in Fig. 7.9 results in the circuit of
Fig. 7.14 that provides current feedback. The circuit of Fig. 7.15 is the equivalent circuit of the current
feedback bias circuit. This circuit provides more stability than the previous circuits. This means that the
270
operating point will tend to remain at the predetermined value in spite of changes in temperature and
variations in other circuit components.
Figure 7.14 Emitter bias
Figure 7.15 Emitter bias equivalent circuit
IC = bI B + (1 + b ) ICO
From Fig. 7.15,
a
VCC = RB I B + VBE + 1 + b I B RE f
ICQ =
b
b (VCC - VBE ) + (1 + b ) ICO RB + RE g (7.3.6)
RB + (1 + b ) RE
The increase in the value of VE = REIE with the increasing temperature has two-fold effects;
∑ The first fold effect can be explained as increase in the quiescent collector current ICQ with
increasing temperature. This increase will result in the increasing drop across the emitter resistance
RE (VE = REIE) that in turn decreases the forward bias and hence, the base current IB decreases.
This decrease in IB counterbalances the increasing tendency in ICQ and hence, the quiescent
collector current ICQ does not shift.
∑ The second fold effect works on the principle of decreasing VBE for increasing temperature that
again brings down the collector current back to its original value. Hence, the stability factor for
the circuit of Fig. 7.14 is obtained as
DICQ 1+ b
SI = SI = = (7.3.7)
CO
DICO 1 + bRE
RE + RB
Biasing
271
The stabilization of Q-point against variations of temperature T and b are demonstrated in Figs. 7.16
and 7.17.
Figure 7.16 Rising ICQ with temperature checked by current feedback
Figure 7.17 Rising ICQ due to b-variation checked with current feedback
From Eqn. 7.3.12 it is clear that ICQ depends on the following:

∑ Current amplification factor b
∑ Collector cut-off current ICO, the leakage current
∑ Base-emitter voltage VBE
∑ Change in supply voltage VCC
We will discuss the effect of each parameter, one at a time, on the quiescent collector current.
7.3.4 Effect of Amplification Factor on ICQ

A simplified amplifier circuit with two-battery bias is drawn as in Fig. 7.18.
Figure 7.18 Two-battery bias
Figure 7.19 Two-battery bias equivalent circuit

272
We know that the quiescent collector current is very strongly dependent on the current amplification
factor b of the transistor. An estimate of approximate variation in the quiescent collector current for
variation in b is analyzed now.
IE = IC + IB (7.3.8)
The reverse saturation current ICO always flows out from the collector lead of the transistor. It is the
current flowing through the collector lead (when IE = 0) ICO. The variation in the quiescent collector
current is also strongly dependent on the variation in the leakage current ICO. The KVL equation in the
input loop of Fig. 7.19 can be written as
VB = RB I B + VBE + RE I E = RB I B + VBE + RE (1 + b ) I B (7.3.9)
b (VB - VBE ) + (1 + b ) ICO ( RB + RE )

IC = ICQ = (7.3.10)
RB + (1 + b ) RE
DICQ 1+ b
SI = SI = = (7.3.11)
CO
DICO bRE
1+
RE + RB
It is also known that usually b(VB - VBE ) >> (1 + b ) I CQ ( RB + RE ) , the second term of Eqn. 7.3.10
is neglected and then this equation reduces to
b (VB - VBE )
ICQ = (7.3.12)
RB + (1 + b ) RE
Now, we can examine the effect of amplification factor b on ICQ. Under such circumstances, the ICQ
quiescent collector current is expressed as
(VB - VBE )
ICQ = IC @ (as b + 1 = b ) (7.3.13)
R
RE + B
b
In Eqn. 7.3.13 if RB /b << RE , then due to change in b, there would not be any change in the
quiescent collector current ICQ. Hence, to stabilize the Q-point, this relationship between emitter resistance
RB/bmin and base resistance RB should remain valid.
In case RB is selected to be very small with respect to the input resistance of the transistor, the signal
is lost in the input bias network. This is undesirable. Hence, the value of RB should be large enough. On
the other hand, in order to keep the inequality relationship
RB / b << RE (7.3.14)
valid and at the same time a high value of RB is not possible. A compromise has to be made from both
sides. This suggests that RB /b should increase from negligible value w.r.t. RE and RB should decrease
to come to a common point where this inequality can be equated. Here, RB /b can be increased to the
maximum by putting the minimum value of b = bmin and RE can be decreased by dividing it by 10 that
holds good for all practical purposes. Thus, Eqn. 7.3.14 reduces to
Biasing
273
RB R
= E
b min 10
b min RE
or, RB = (7.3.15)
10
Example 7.2
Calculate RE, RB and D ICQ if 40 < b < 120 of a silicon transistor with ICQ = 10 mA, VCEQ = 5 V in
Fig. 7.20,
Figure 7.20 Two-battery bias
Solution
10
RL + RE = = 0.5 K
20 mA
If RE is assumed to be 0.1 K, then RL = 0.4 K
Êb ˆ 40
RB = Á min ˜ RE = (0.1 K) = 0.4 K
Ë 10 ¯ 10
Hence, the quiescent collector current is expressed as
b (VCC - VBE ) 1.75 - 0.7 1.05
ICQ = = =
(1 + b ) RE + RB 100 + 400 100 + 400
b b
1.05 1.05
ICQ( b = 40) = = = 9.5 mA and
400 110
100 +
b
1.05 1.05
ICQ (b = 120) = = = 10.1 mA
400 103.3
100 +
b
Now the change in ICQ for the corresponding change in b from 40 to 120 is = DICQ= 10.1 9.5
= 0.6 mA. This example shows that the variation in b from 40 to 120 shifts the collector quiescent
274
current by negligible amount. Thus, the quiescent collector current is almost independent of transistor
replacement for all practical purposes.
7.3.5 Effect of Temperature on the Q-point

In order to analyse the effect of variation of quiescent collector current ICQ due to variation in temperature,
the quiescent collector current must be correlated in terms of parameters that are functions of temperature.
Thus, ICQ is expressed as
ICQ =
b
(VB - VBE ) + ICO RB + RE g (7.3.16)
R
RE + B
b
The VBE and ICO in Eqn. 7.3.16 are two-parameters that are temperature dependent. Hence, change
in ICQ w.r.t. VBE and ICO (that change w.r.t. temperature) is analysed here. We know that VBE decreases
linearly with increasing temperature as shown in Fig. 7.21. It can be expressed mathematically as
VBE1 - VBE 2 DVBE
= = - K1 (as t1 < t2) (7.3.17)
t1 - t2 -Dt
The typical value of K1 for both Si and Ge is 2.5 mV/° C.
We know that ICO increases exponentially with increase in the temperature and for every 10°C rise,
ICO approximately doubles. The natue of change in quiescent collector current for the corresponding
change in the reverse saturation current ICO due to changing temperature is shown in Fig. 7.21.
The change in ICO is mathematically expressed as
ICO1 = ICO exp K2t1 and ICO 2 = ICO exp K2t2 (7.3.18)
ICO 2
= exp K2 (t2 -t1 ) = exp K2 Dt
ICO1
ICO2 I -I DI
- 1 = CO 2 CO1 = CO = exp K2Dt - 1 (7.3.19)
ICO1 ICO1 ICO1
Figure 7.21 Variation of VBE and ICO with temperature

Biasing
275
Hence, DICO = ICO1 (exp K2Dt - 1) (7.3.20)

where, K2 = 0.07 /° C (7.3.21)
Typical value of ICO at room temperature for low power transistors are
ICO(Ge) = I CO1 = 100 m A
ICO(Si) = I CO1 = 1 m A (7.3.22)
Since ICO approximately doubles for every 10°C rise in temperature, Ge transistors are more susceptible
to temperature than Si. This is one of the most important reasons why Si transistors are used in the
conditions where BJTs are left ON continuously for days together. The quiescent collector current for
the circuit of Fig. 7.19 is
ICQ =
b
(VB - VBE ) + ICO RB + RE g (7.3.23)
R
RE + B
b
gFGH exp Dt - 1IJK I

K2 Dt
- DVBE
DICQ Dt
b
+ RB + RE CO
= (7.3.24)
Dt R
RE + B
b
As b is very large, RB /b << RE, under such condition Eqn. 7.3.24 reduces to
- DVBE exp( K2 Dt ) - 1
DICQ + ( RE + RB )
= Dt Dt ICO1 (7.3.25)
Dt RE
K1D t + ( RE + RB ){exp( K 2 t ) - 1}
DICQ = I CO1 (7.3.26)
RE
Example 7.3
Calculate the change in ICQ if temperature increases to 55°C for (a) Si (b) Ge transistors for the circuit
in Fig. 7.20 if RB = 0.4 K, RE = 0.1 K at room temperature, i.e. (25°C),
Solution
Dt = 55 25 = 30°C
K1Dt + ( RE + RB ){exp( K 2 t ) - 1}
DICQ = I CO1
RE
2.5 ¥ 103 ¥ 30 Ê 400 ˆ

=
100
+ Á1 +
Ë 100 ˜¯ (
exp0.07*30 - 1 )
= 0.75 ¥ 10 -3 + 5 ¥ 7.2 ICO = 0.75 ¥ 10 -3 + 36 ICO
276
ICQ(Si) = 0.75 ¥ 10-3 + 36 ¥ 1 ¥ 10-6 = (0.75 + 0.036) mA = 0.786 mA
ICQ(Ge) = 0.75 ¥ 10-3 + 36 ¥ 100 ¥ 10-6 = (0.75 + 3.6) mA = 4.36 mA
The first term 0.75 is much higher than the second term 0.036 of ICQ(Si). Hence, change in quies-
cent collector current is primarily due to change in the VBE for change in temperature in the case of Si
transistor. On the contrary, change in ICQ is primarily due to change in ICO because, 3.6 is much more
than 0.75 in ICQ (in case of Ge transistor). Thus, we conclude that the change in the quiescent
collector current due to changing temperature can be almost 50% that may bring the transistor Q-point
to such a value where amplifier operation is undesirable.
7.3.6 Voltage and Current Feed-back Circuit

Another stable bias circuit is shown in Fig. 7.22. Fig. 7.22 is drawn to analyze its stability factor.
Figs. 7.23 and 7.24 have been included to indicate the effect of voltage and current feedbacks on the
rising tendency of quiescent collector current due to rise in the current amplification factor b. This
circuit of Fig. 7.22 provides two-fold effects to stabilize the Q-point:
∑ negative voltage feedback through RB, and
∑ negative current feedback through the resistance RE.
As the collector current increases due to rise in temperature, base current is decreased by two-fold
actions.
∑ Voltage drop across RB decreases and hence, 0.75 ¥ 10 -3 + 36 ¥ 100 ¥ 10 -6 decreases.
∑ The voltage drop across RE increases that in effect decreases the forward bias across the
EBJ ( VBE = VB - VE ) resulting in decrease of the base current.
The KVL around the input loop in Fig. 7.22 is written as
VCC = RC ( IC + I B ) + RB I B + VBE + RE ( IC + I B ) (7.3.27)
b (VCC - VBE ) + (1 + b ) ICO ( RC + RB + RE )

IC = ICQ = (7.3.28)
RB + (1 + b )( RE + RC )
Figure 7.22 Voltage and current feedback type of bias

Biasing
277
Hence, stability factor from Eqn. 7.3.28 can be expressed as

DICQ 1+ b
SI = = (7.3.29)
DICO
1+
b
b RC + REg
RC + RB + RE
Stability factor by Eqn. 7.3.29 is much less than the stability factors of circuits in Figs. 7.97.14. It
is clear from Fig. 7.23 that the effect of increasing temperature on ICQ is counter balanced by both
current and voltage feedbacks.
Figure 7.23 Voltage + current feedback biasing to check rising IC versus temperature.
Figure 7.24 Voltage + current feedback biasing checks rising ICQ versus b.
7.4 Voltage Divider Emitter Bias

The voltage divider emitter bias circuit shown in Fig. 7.25 is practically used in almost all general-
purpose transistor amplifier biasing. The circuit is adjusted such that the bleeder current through R2 is at
least 10 IB. So IB << I R1 and I R2 and Thevenins theorem can be applied at the base of the transistor in
Fig. 7.25.
The Thevenin voltage VOC = VB can be obtained after opening at the base as in Fig. 7.26. Current I R1
= I R2 is obtained under the condition I R2 = 10 IB as
VCC V R
IR1 = IR2 = , and VOC = VB = CC 2 (7.4.1)
R1 + R2 R1 + R2
278
Figure 7.25 Voltage divider emitter bias circuit
Thevenin theorem is used to find out the equivalent base voltage to forward bias the base-emitter
junction and the effective internal resistance in series with the equivalent voltage of the equivalent
source. Obtain the equivalent resistance by shorting all voltage sources and opening all current sources
with their internal resistances intact as shown in Fig. 7.26.
R1 R2
ROC = RB = = R1 R2 (7.4.2)
R1 + R2
Figure 7.26 Voltage divider emitter bias circuit.
The Thevenins equivalent voltage VOC = VB and ROC = RB is now connected to the base of transistor
as shown in Fig. 7.27. The dc equivalent circuit of BJT is drawn in Fig. 7.27 with its fundamental
equations as
IC = bI B + (1 + b ) ICO
From Fig. 7.27, VB = RB I B + VBE + RE I E = RB I B + VBE + RE ( IC + I B )
IC - (1 + b ) ICO
( RB + RE ) + RE IC = VB - VBE
b
( RB + RE ){IC - (1 + b ) ICO} + b RE I C = b(VB - VBE )

b (VB - VBE ) + (1 + b ) ICO ( RB + RE )
IC = (7.4.3)
RB + (1 + b ) RE
Biasing
279
1+ b
SI = (7.4.4)
bRE
1+
RB + RE
Example 7.4
Obtain the values of R1 and R2 to provide the following bias conditions to a Ge transistor arranged as
in circuit of Fig. 7.27. Given IBQ = 0.3 mA, ICQ = 20 mA, VCEQ = 5 V, b = 100, SI = 10.
The Thevenins equivalent of Fig. 7.27 is shown just beside this figure. Writing the input loop
equation in Fig. 7.27 yields
DICQ 1+ b 1 + 100
SI = = = = 10
DICO b RE 100 ¥ 100
1+ 1+
RB + RE RB + 100
Figure 7.27 Voltage divider emitter bias circuit
100 ¥ 100
or, 1+ = 10 + 0.1 @ 10
RB + 100
100
100 + RB = 100 ¥ @1K
9
VB = RB I B + VBE + RE I E @ RB I B + VBE + RE IC
= RB × 0.3 mA + 0.2 + 100 × 20 mA
= 2.2 + RB ¥ 0.3 mA
VCC R2 12 R2
RB = 1 K 0.1 K @ 1 K , VB = 2.2 × 0.3 + 1 = 2.5V = =
R1 + R2 R1 + R2
12 R2
R1 + R2 = = 4.8R2 and 3.8 R2 = R1
2.5
280
R1 R2 3.8 R22 3.8 R2

= RB = = @ 1 KW
R1 + R2 4.8 R2 4.8
4.8
R2 = = 1.26 K, and R1 = 3.8 × 1.26 K = 4.8 KW
3.8
Hence, actual stability factor
1 + 100 101
= SI = = @ 10.
100 ¥ 100 10.1
1+
1 K + 100
7.5 Effect of Bypass Capacitors on Biasing

The output collector voltage is 180° out of phase with reference to the input voltage in Fig. 7.28 and this
voltage is fed back to the input again through a resistance R41. This is the negative voltage w.r.t to the
original input voltage and the effective input voltage goes down and forces the voltage gain to go down
R R
by an appreciable amount. Splitting R1 in two-equal parts 1 + 1 and connecting a capacitor at the
2 2
junction of the division as shown in Fig. 7.28 can avoid this. The value of Cs is large enough to swamp
all ac feedback voltages and does not disturb the dc bias current.
Figure 7.28 Split RB with emitter bias bypass capacitor
Also the ac voltage drop across RE changes dc voltage across RE and disturbs the quiescent values of
voltage and current. This type of effect can be eliminated completely by connecting a large value of
capacitor CE across RE. This capacitor allows all ac components to pass through it and stops the dc
component through it. Hence, this capacitor CE is known as bypass capacitor. The value of bypass
capacitor can be calculated by the thumb rule as
1 R
XCS = = E (7.5.1)
w Cs 10
Biasing
281
7.6 Stability Factor Analysis

A more rigorous analysis can result into total change in the quiescent collector current ICQ with reference
to change in different variables such as ICO, b, VBE, VCC, RE, etc. For such analysis the quiescent
current is described as function of all parameters that are responsible for its change as
b
ICQ = f ICO , VBE , b , VCC , RE , ... g (7.6.1)
The total change in ICQ due to change in ICO , b , VBE , VCC , RE, etc. can be obtained by adding partial
change due to change in each parameter. Differentiating Eqn. 7.6.1 partially with each component and
then adding them results in
d ICQ d ICQ d ICQ d ICQ d ICQ
DICQ = DICO + DVBE + Db + DVCC + DRE (7.6.2)
d ICO d VBE db d VCC d RE
d ICQ D ICQ d ICQ DICQ d ICQ DICQ

where, SI = = , SVBE = = , Sb = = ,
d ICO D ICO d VBE DV BE db Db
d ICQ DICQ d ICQ DICQ

SVCC = = , and SRE = = (7.6.3)
d VCC DVCC d RE DRE
If the change in the parameters ICO , b , VBE , VCC , and RE are very small, then one can assume that
d ICQ = D ICQ .
DICQ = SI DICO + SVBE DVBE + Sb Db + SVCC DVCC + SRE DRE (7.6.4)
It is clear from Eqn. 7.6.4 that the total change in the quiescent collector current ICQ is proportional
to the change in each of the independent variables and to their stability factors. Thus, to get minimum
change in the quiescent collector current DICQ, the circuit is designed for minimum stability factors.
Example 7.5
1. Calculate the total shift in the quiescent collector current for the circuit shown in Fig. 7.25 due
to change in all parameters at a time that affect the quiescent collector current.
Solution
The quiescent collector current ICQ from Eqn. 7.3.6 is
b (VB - VBE ) + (1 + b ) I/CO ( RB + RE )

ICQ = IC =
RB + ( b + 1) RE
VB - VBE + I/CO ( RB + RE )
= (7.6.5)
RB
+ RE
b
282
b g a
Since, b VCC - VBE >> 1 + b RB + RE ICO fb g (7.6.6)
b (VB - VBE ) (V - VBE )
ICQ = IC = = B (7.6.7)
RB + (b + 1) RE RB
+ RE
b
Let b1 and b2 represent the upper and lower limits and the corresponding quiescent collector
currents are denoted as ICQ1 and ICQ2 and expressed as
b 1 (VB - VBE ) b 2 (VB - VBE )
ICQ1 = and ICQ 2 = (7.6.8)
RB + (b 1 + 1) RE RB + (b 2 + 1) RE
ICQ 2
=
l
b 2 RB + (1 + b 1 ) RE q and I - 1 = b lR + (1 + b )R q - 1
CQ2 2 B 1 E
(7.6.9)
ICQ1 b lR
1 B + (1 + b ) R q
2 IE b lR + (1 + b ) R q
CQ1 1 B 2 E
ICQ 2 - ICQ1 b lR
2 B + (1 + b ) R q - b lR + (1 + b ) R q
1 E 1 B 2 E
= (7.6.10)
ICQ1 b lR + (1 + b ) R q
1 B 2 E
DICQ (b 2 - b 1 )( RB + RE ) Db ( RB + RE )
= = (7.6.11)
ICQ1 l
b 1 RB + (1 + b 2 ) RE q
b 1 RB + (1 + b 2 ) RE l q
DICQ ( RB + RE ) ICQ1 ( RB + RE ) ICQ1
= = (7.6.12)
Db l
b 1 RB + (1 + b 2 ) RE R q
b 1b 2 B + RE
RS UV
b2 T W
There is a large change in ICQ due to large change involved in b. Since, we have to calculate the
actual change, the above calculations for change in ICQ w.r.t. b has been done by a separate
method as an example. The change in the quiescent collector current is expressed as
DICQ =
RB + RE R + RE ICQ1
DICO + B Db -
1 FG
DVBE + ....
IJ (7.6.13)
RB RB b 1b 2 R H K
RE + RE + RE + B
b b2 b2
= SI DICO + Sb Db + SVBE DVBE + ....... (7.6.14)
From the Eqn. 7.6.14 it is clear that the total change in the quiescent current is proportional to
the change in each of the independent variables and to their stability factors. Thus, design must
aim to achieve minimum value of stability factors for small change in the quiescent collector
current ICQ.
2. An amplifier circuit in Fig. 7.29 has been arranged with voltage divider emiitter bias. Obtain the
quiescent collector current ICQ at room temperature and change in ICQ for the following devia-
tions in data with silicon transistor used for the change in temperature from 25°C to 125°C.
Biasing
283
Figure 7.29
Solution
ICO = 0.1 m A , VBE = 0.7 V at 25o C , 50 < b < 125 , b nominal = 75
0.455 4.55
VB = 10 V = = 1.75 V , RB = 0.455 K||2.14 K = 0.375 K
2.14 + 0.455 2.595
VB - VBE 1.75 - 0.7 1.05

ICQ @ = = = 10 mA
RE + RB / b 100 + 375/75 100 + 5
( RB + RE )(1 + b ) RB + RE 475
SI = = = = 4.52 mA/mA
RB + (1 + b ) RE R 105
RE + B
b
1 1 1 1
SVBE = - =- = = = - 9.238 m A/V
RE + RB / b 100 + 370 / 75 100 + 5 105
Ê DICQ ˆ Ê ICQ1 ˆ Ê RB + RE ˆ Ê 10 ¥ 10 3 ˆ Ê 475 ˆ

Sb = Á = =Á ˜Á ˜ = 0.00754 mA/ Db
Ë Db ¯˜ ËÁ b1b 2 ¯˜ ËÁ RE + RB / b 2 ¯˜ Ë 50 ¥ 120 ¯ Ë 105 ¯
Ê R2 ˆ Ê 1 ˆ Ê 0.455 ˆ Ê 1 ˆ
SVCC = Á =Á ˜ ÁË 105 ˜¯ = 1.67 mA / V
Ë R1 + R2 ¯ Ë RE + RB / b ˜¯ Ë 2.595 ¯
˜ Á
{RB + (1 + b ) RE}(0) - b (VOC - VBE )(1 + b ) - b (VOC - VBE )b - (VB - VBE )

SRE = 2 = 2
=
{RB + (1 + b ) RE} {RB + (1 + b ) RE } {RE + RB / b }2
Ê (VB VBE ˆ (1.75 - 0.7) 1.05

= Á ˜= = = 0.105 mA / V
Ë {RE }2 ¯ (100)2 (100)2
DICO = ICO1 (exp K2 Dt - 1) = 0.1 ¥ 10 -6 (exp 7 - 1) @ 0.195mA

284
DVBE = - K1Dt = - 2.5 ¥ 10-3 ¥ 100 = - 0.25 V

The worst case will happen when all the changes will combine to add and shift the Q-point. Hence, the
design is made for the worst as if it can work for the worst case, it will as well work for other
conditions.
DICQ = S I DI CO + Sb Db + SVBE DVBE + SVCC DVCC + S RE DR E
= 4.52 ¥ 0.195 + 0.0075 ¥ 75 + 9.24 ¥ 0.25 + 1.67 ¥ 2 + 0.105 ¥ 2

= 0.8814 + 0.5278 + 2.31 + 3.34 + 0.21 = 7.3 mA = ± 3.65 mA
Hence, the maximum variation from the nominal value of ICQ = (10 ± 3.65) mA . The variation
in ICQ here is mainly due to change in VBE, VCC, and RE.
3. Obtain the value of RB to provide the proper bias conditions for a Ge transistor arranged as
voltage feedback circuit in Fig. 7.30 with IBQ = 0.3 mA , ICQ= 20 mA , VCEQ = 3.4 V, b = 100.
Solution:
Writing the input loop equation for Fig. 7.30 yields
VCC = RC ( IC + I B ) + RB I B + VBE + RE ( IC + I B )
= RB I B + VBE + ( RB + RE )( IC + I B )
a fa
= 0.3 ¥ RB + 0.2 + 0.33 + 0.1 20 + 0.3 f
12 = 0.3 ¥ RB + 0.2 + a0.43fa20.3f
= 0.3 ¥ RB + 0.2 + 8.73 = 0.3 ¥ RB + 8.93
0.3 ¥ RB = 12 - 8.93 = 3.07
3.07
or, RB = = 10.23 K W
0.3 mA
Figure 7.30 Collector to base bias
7.7 Diode Compensation

We know that change in ICQ for a Si transistor is primarily due to change in the value of VBE with change
in the temperature and the effect of ICO is negligible. The change in the value of VBE w.r.t. change in the
Biasing
285
temperature can be controlled by connecting a voltage that works opposite to changing VBE. A diode
compensation circuit shown in Fig. 7.31 is normally used for VBE compensation.
Figure 7.31 Diode compensation
Figure 7.32 BJT used as diode
I EQ
IBB = ID + IBQ = I D + = constant (7.7.1)
1+ b
Also, VD + RD I D = VBE + RE IEQ (7.7.2)
Substituting ID from Eqn. 7.7.1 in Eqn. 7.7.2 results
Ê I EQ ˆ
VD + RD Á I BB = VBE + RE IEQ (7.7.3)
Ë 1 + b ˜¯
VD - VBE + RD I BB
ICQ @ IEQ = (7.7.4)
R
RE + D
b +1
The change in the quiescent emitter current IEQ @ ICQ can be obtained by differentiating Eqn. 7.7.4 as
DVD DVBE
DIEQ - +0
= Dt Dt (7.7.5)
Dt R
RE + D
b +1
286
It is clear from Eqn. 7.7.5 that if diode and transistor in Fig. 7.31 are matched, then the quiescent
emitter current is insensitive to temperature variation. It is very difficult to get matched characteristics
of transistor and diode w.r.t. variation in temperature. Even if it is designed especially, the cost effectiveness
of the circuit becomes improper.
DVD DVB
If - =0 (7.7.6)
Dt Dt
Then the change in the quiescent emitter current from Eqn. 7.7.5 is equated to zero, i.e. DIEQ = DICQ
= 0. In other words, decreasing effect of VBE is compensated by increasing effect of the diode included
in Fig. 7.31.
Using the same transistor as diode can solve the matching problem of diode and transistor. A simple
circuit using transistor as compensating diode is drawn in Fig. 7.32.
VCC - VB V - VD V - VD I EQ
= B + I BQ = B + (7.7.7)
RB RD RD 1+ b
VB - VBEQ
IEQ = (7.7.8)
RE
VB = RE IEQ + VBEQ (7.7.9)

Substituting VB in Eqn. 7.7.7 from Eqn. 7.7.9 results in
FG 1 + 1 IJ dR I + V i = V E EQ BEQ
CC
+
VD I
- EQ (7.7.10)
HR R K
B D R B RD 1 + b
|RSFG 1 + 1 IJ R + 1 |UV I = V
E EQ
CC
+
VD

1FG
+
1
VBEQ
IJ (7.7.11)
|TH R R K 1 + b |W
B D R B RD H
RB RD K
The change in quiescent emitter current, i.e. DIEQ may be obtained after differentiating Eqn. 7.7.11 as
R|SF 1 1
RE +
IJ1 U|V DIEQ
=
1 DVDF 1 I FG
1 DVBE IJ (7.7.12)
T|GH R
+ - +
B RD K
1+ b W| Dt RD DtH K H
RB RD Dt K
As second term in LHS of Eqn. 7.7.12 is much less than the first term, Eqn. 7.7.12 reduces to
FG 1 +
1 IJ FG
RE
DIEQ IJ = FG 1 IJ F DV I - FG 1 + 1 IJ F DV I
D BE
(7.7.13)
HRB RD K H
Dt K H R K H Dt K H R R K H Dt K
D B D
FG DI EQ IJ = 1 R|SF DV I FG R IJ - F DV I U|V
D B BE
(7.7.14)
H Dt K R |TH Dt K H R + R K H Dt K |W
E B D
DVD DVBEQ
If = = - K1 (= 2.5 mV/ ∞ C) (7.7.15)
Dt Dt
Biasing
287
FG DI IJ = 1 |RS- K FG R IJ + K U|V
EQ B
H Dt K R |T H R + R K |W
E
1
B D
1
K R
1 R UV = K RS 1 UV
B 1
= S1- (7.7.16)
R T R + R W R T1 + R / R W
E B D E B D
The change in the quiescent collector current from Eqn. 7.6.7 is

DICQ -b F
DVBE I K1 K
= = @ 1 (7.6.17)
Dt RB + (b + 1) RE H
Dt KRE + RB / b RE
It is clear from Eqns. 7.7.16 and 7.7.17 that change in the quiescent collector current due to change in
the temperature is much higher in Eqn. 7.7.17 than that of Eqn. 7.7.16.
If RB = 5 K, and RD = 0.5 K, then from Eqn. 7.7.16
DICQ K1 Ï 1 ¸ K1
= Ì ˝= (7.7.18)
Dt RE 1
Ó + 5/ 0.5 ˛ 11 RE
Thus Eqn. 7.7.18 indicates that temperature effects are reduced 11-times w.r.t. a circuit without diode
compensation.
7.8 IC Biasing
The technique discussed so far for biasing the BJT is not at all suitable for IC biasing as the discrete
biasing of BJT requires very large values of coupling as well as bypass capacitors and a number of large
value of resistors. It is almost impossible to create large values of capacitors with available IC technology
and it is uneconomical to manufacture large value of resistor. On the contrary, the IC technology
provides the designer with the possibility of using many transistors that can be very cheaply produced.
Further more, it is easy to manufacture transistors with matched characteristics under changing
environment.
7.8.1 Current Source

The biasing technique in IC is based on using constant current source. The collector current of transistor
(BJT) in active mode is relatively independent of the collector voltage, i.e. IC remains constant. On an IC
chip with a number of amplifiers, a constant dc current source is created at one location and is then
reproduced at other locations for biasing various amplifier stages. This approach has the advantage that
the biasing current of the various stages track each other in case of change in the power supply voltage
or temperature.
The simplest current source is a transistor operated with constant base-current in active mode. Such
a circuit is shown in Fig. 7.33. The exaggerated output characteristic for actual change and stabilized
change in collector current is also shown in this figure. The dotted horizontal line is the characteristic of
the source for an infinite Early voltage. The actual output characteristic exhibits a slope resulting in finite
value of its output resistance where as the stabilized output characteristic does not show any slope and
288
hence, provides infinite output resistance ro = rce = DVCE/DIC. Figure 7.33 has the current source
representation of the BJT also with finite value of internal resistance ro.
V1 - VBE
For V1 > VBE, IB =
RB
Figure 7.33
Ê V - VBE ˆ
The corresponding collector current IC = bIB = b Á 1 (7.8.1)
Ë RB ˜¯
In the region VCE > VCE(sat), collector current can be approximated as
IC = ICO 1 +
FG VCE IJ
V /V
exp BE T (7.8.2)
H VA K
where, VA = Early voltage usually in the range of 100V to 150V (ideally •)
1 ∂I
The effective output conductance = = C (7.8.3)
ro ∂VCE VBE = VBEQ
VA -V /V
ro = exp BEQ T (7.8.4)
ICO
VBE / VT
In the region VCE < VA , IC = ICO exp (7.8.5)
VA
ro = (7.8.6)
IC
Equation 7.8.6 results into very high value of ro, ideally •. Fig. 7.33 represents current source with
finite value of output resistance.
From Eqn. 7.8.1 it is clear that such a simple current source circuit in Fig. 7.33, to first approximation,
is susceptible to temperature that changes all internal parameters of the transistor and hence, operating
point does not remain constant. Thus, the resulting current source generator will also vary with changing
Biasing
289
temperature. To second approximation, the current generator produced by a simple BJT does not
provide infinite internal resistance and hence, ICQ changes with change in the VCE. In order to get a
stabilized current ICQ, let us discus its root cause by analysing the biasing circuit using both current and
voltage feedbacks as in Fig. 7.34.
VCC = RB I B + VBE + ( RC + RE )( IC + I B ) , and IC = bI B + (1 + b ) ICO
Now, VCC = ( RB + RE + RC ) I B + VBE + ( RC + RE ) IC ,
b
= RB + RE + RC g FGH Ib - (1 + bb)I IJK + V + b R + R g I
C CO
BE C E C
b(VCC - VBE ) = l( RB + RE + R ) + b ( R + R )q I - ( R + R )(1 + b ) I

C C E C B E CO
b (VCC - VBE ) + (1 + b )( RB + RC + RE ) ICO

or, IC = ICQ =
RB + (1 + b )( RC + RE )
DIC (1 + b )( RB + RC + RE ) 1+ b
SI = = =
DICO RB + (1 + b )( RC + RE ) 1 + b ( RC + RE )
RB + RC + RE
-b
SVBE =
RB + (1 + b )( RC + RE )
b 1 (VCC - VBE ) b 2 (VCC - VBE )
IC1 = and IC2 =
(1 )(
RB + + b 1 RC + RE ) RB + (1 + b 2 )( RC + RE )
IC 2 b { R + (1 + b1 )( RC + RE )}
= 2 B
IC1 b1{RB + (1 + b 2 )( RC + RE )}
IC2 b { R + (1 + b1 )( RC + RE )}
-1 = 2 B -1
IC1 b1{RB + (1 + b 2 )( RC + RE )}
I C 2 - I C1 b { R + (1 + b1 )( RC + RE )} - b1{ RB + (1 + b 2 )( RC + RE )}
or, = 2 B
IC1 b1{RB + (1 + b 2 )( RC + RE )}
DIC (b - b 1 ) RB + (b 2 - b 1 )( RC + RE )
= 2
IC1 b 1{RB + (1 + b 2 )( RC + RE )}
Db ( RB + RC + RE )
=
b 1{RB + (1 + b 2 )( RC + RE )}
DIC RB + RC + RE
Sb = = IC1
Db b 1{RB + (1 + b 2 )( RC + RE )}
1+ b -b -1
For RB = 0, SI = = 1 , SVBE = = @ fraction ,
1+ b (1 + b )( RC + RE ) RC + RE
290
IC1
Sb = @0
b 1 (1 + b 2 )
Figure 7.34
All stability factors SI , SVBE , and Sb are very small. Hence, the Q-point of this circuit will be very
stable. However, the fact that RB = 0 shorts the CBJ and makes the BJT effectively a diode that cannot
be used as an amplifier or in digital circuit as output is shorted to the input. This circuit helped in driving
the idea of a circuit containing two-transistors, one is stabilized with RB = 0 and the other functions as
a normal amplifier and operating point of both transistors ultimately get stabilized. Such a circuit is called
Widlar stabilization circuit shown in Fig. 7.35.
This circuit would not have become so popular had replacing one transistor by two was not economical.
The point of viability was paved by evolution of the IC technology.
Here it is essential that two-transistors must be identical and operate at the same temperature. This
feature is inherent in IC technology as both transistors are fabricated at the same time under identical
environment and both remain in the close proximity. Transistor T1 is highly stabilized with RB = 0 and as
T1 and T2 are in close proximity in IC , the characteristics of both are identical. Under such condition b1
= b2 even if they vary with temperature.
Figure 7.35 Widlar circuit

Biasing
291
Since T1 and T2 are identical,

VBE 1 VBE 2
VT VT
IC1 = a1 I E exp and I C 2 = a 2 I E exp
VBE 2 - VBE1
IC 2
= exp VT
IC1
Applying KVL around the loop containing both transistors base-emitter voltage results as
VBE 2 - VBE1 = 0
or, VBE2 = VBE1 = VBE
IE2 = IE1 = IE and IC2 = IC1 = IO.
7.8.2 Current Sink

We will discuss here the circuit of current source or current sink. Fig. 7.36 is the simple circuit of a
current sink. Since the output current in the collector, terminal IC = Io, is pulled through the load RC
from the positive supply voltage VCC it is called current sink. The transistor must remain in active region
all the time so that it supplies constant current to the load.
b g
VB = RB I B + VBE + RE IC + I B and IC = bI B + 1 + b ICO a f
b g
VB = RB + RE I B + VBE + RE IC = RB + RE b gRST Ib - a1 + bbf I UVW + V
C CO
BE + RE IC
or, b g
b VB - VBE = ( RB + RE ) IC + b RE IC (1 + b ) ( RB + RE ) ICO
b (VB - VBE ) + (1 + b )( RB + RE ) I/CO b (VB - VBE )

IC = Io = @
RB + (1 + b ) RE RB + (1 + b ) RE
b
FG V R 1 2
- VBE
IJ FG b IJ FG V R 1 2
- VBE
IJ
=
HR +R
1 2 K = H1 + b KH R + R 1 2 K
RB + (1 + b ) RE RB
+ RE
1+ b
FG V R 1 2
- VBE
IJ
=
HR +R 1 2 K
RB
+ RE
1+ b
292
Figure 7.36 Current sink
In order to make IC = Io = constant, IC should be independent of VBE and b. This condition can be
achieved only when
RE ≥
FG R R IJ FG 1 IJ , FG V R IJ ≥ V
1 2 1 2
BE
H R + R KH1+ b K H R + R K
1 2 1 2
Ê V1R2 ˆ
ÁË R + R ˜¯ VB
1 2
Hence, IC = Io @ =
RE RE
7.8.3 Current Mirror

Having discussed current source and current sinks, we propose to use them at different locations in IC.
In IC containing many BJT amplifiers (such as a circuit of an op-amp), a constant dc current is
generated at one location and reproduced at many other locations using simple circuit shown in Fig.
7.37. This circuit is called current mirror. The current mirror assumes that both transistors T1 and T2
are matched, i.e. VBE1 = VBE2 and IE1 = IE2.
IC2 = Io =
FG b IJ I = FG b IJ I
2
E2 E
H1+ b K H1+ b K
2
From Fig. 7.37, IR = IC1 + IB1 + IB2

FG b IJ I + FG 1 IJ I + FG 1 IJ I
1
E1 E1 E2 =
FG b + 2 IJ I E
H1+ b K H1+ b K H1+ b K
1 1 2 H 1+ b K
Ê b + 1ˆ
or, IE = Á IR
Ë b + 2 ˜¯
IC2 = Io =
FG b IJ I = FG b IJ FG b + 1 IJ I = FG b IJ I
E R R @ IR
H1 + b K H1 + b K H b + 2K H b + 2K
(for large value of b )
Biasing
293
Figure 7.37 Current mirror

Here, it is worth noting that the current IR created at one location is reflected at the other location, i.e.
through the collector current of transistor T2 (load). Thus, the load current becomes independent of the
load resistance and hence is called constant current. Thus, if IR is stabilized, the IC2 will also be stabilized
and will not depend on VCE. In other words, even if RC and R differ by a great deal, the circuit will
provide good stabilization. Since these two currents IR and IC2 are equal, the circuit is called current
mirror.
Since only transistor T2 is used as an amplifier, this circuit has relatively low gain. As the input
current enters both the bases in parallel, this reduces the ib2 component of current considerably, which
reduces the current amplification factor.
7.8.4 Current Steering Circuit

As discussed, a dc reference current generated at one location in IC biasing is reflected at many locations
for the purpose of biasing many stages of the amplifier stages. The circuit in Fig. 7.38 utilies two-dc
power supplies VCC and VEE.
Figure 7.38 Current steering mirrors

294
VCC + VEE - VBE1 - VBE 5

The dc reference current IR =
R
The base-collector connected (diode) transistor T1 forms current mirror with T2 and hence, T2 will
supply current I2 = IR. Transistor T2 can supply this current to any load so long as the voltage developed
at the collector does not exceed that at the base VCC VBE2.
In order to generate any multiple of the reference current IR, multiple transistors as T3 and T4 are
connected as in Fig. 7.38 to generate two-times the reference current. Hence, I3 = 2IR. We see here that
the parallel combination of two transistors T3 and T4 is equivalent to a transistor with double EBJ area
than that of the T1. This philosophy of multiple area consideration is taken to generate multiple currents
in IC fabrication. This is slightly different in case of MOS transistors where the current transfer ratio of
the W/L ratio is taken and not the area of the device.
Transistor T5 forms current mirror with T6 to provide I4 = IR. Here we must note the difference,
while T2 sources the current to parts of the circuit whose voltage does not exceed VCC VBE2 , T6 sinks
the current from parts of the circuit whose voltage does not decrease below VEE + VBE6. Transistors
T7 , T8 , and T9 are arranged in parallel to reproduce three-times the reference current IR. Hence, the EBJ
junction of the equivalent transistor of T7, T8 , and T9 must be three-times the area of EBJ of T5.
The problem of considerable reduction in gain in Fig. 7.37 can be eliminated for some sacrifice in
Q-point stabilization using Fig. 7.39. The input to the circuit of Fig. 7.39 is through the terminal marked
b. We assume that the impedance of any external generator is greater than the emitte-base impedance so
that the current bias is not substantially changed by the external circuit. The input signal current will
divide into two components, one entering the base of T2 and the other in RB1. However, RB1 can be
chosen to be much higher than the input impedance of T2. Therefore, essentially all the signal current
will flow through the base of T2 and previously discussed loss in gain will not result. Note that the
stabilization of ICQ2 will be less than the circuit of Fig. 7.37 because a non-zero collector-base resistance
is used and the external circuit interacts differently with T1 and T2. Hence, VBE1 is not exactly equal to
VBE2. However good stabillisation is achieved with this circuit because a relatively small value of RB1 can
be used.
In Fig. 7.40, VBE1 = VBE2 + REIE2 @ VBE2 + REIC2
or, VBEI VBE2 = REIC2
Figure 7.39 Improved gain current mirror

Biasing
295
VBE1 - VBE 2
RE =
IC 2
VBE 1 VBE 2
VT VT
IC1 = IR = aIE exp and IC2 = IO = aIE exp
VBE1 - VBE 2 RE IC 2
IC1 I VT VT
= R = exp = exp
IC 2 IO
IC1 I R I
VBE1 VBE 2 = VT ln = VT ln R = E C2
IC 2 IO VT
IR R I
or, VBE1 = VBE2 + VT ln = VBE 2 + E C 2
IO VT
VT I
Hence, RE = ln C1
IC 2 IC 2
Figure 7.40 is also the Widlar current source with an emitter resistance RE. This inclusion allows us
to use less total resistance resulting into less total area of IC for resistance. In addition to this, total
effective output resistance of the resulting current generator also becomes higher than the circuit of
Fig. 7.37.
VCC - VBE1 VCC - 0.7
IR = =
RC RC
IC2 = IC3 = IC4 @ IR (for b very large)
Figure 7.40 Widlar circuit with emitter resistance RE
Such current sources can be cascaded to create current repeaters at multiple places in analog ICS as
indicated in Fig. 7.41.
296
Figure 7.41 Improved Widlar circuit
VC2 = VCC RC2IC2 = VCC RC2IR

VC4 = VCC RC3(IC3 + IC4) = VCC RC3(2IR )
The dependence of IC2 on b of the transistor introduces error in current-gain of the mirror due to
finite value of the b. The second error is due to non-infinite value of the output resistance ro = rce of the
BJT falling in the order of 100K. Hence, we would try to analyze different circuits to avoid finite value
of b and non-infinite value of the output resistance of the current mirror. Figure 7.42 is one of such
circuits that provide certain improvements w.r.t. Widlar circuit in Figure 7.40.
Figure 7.42 Base Current compensated current source
From Fig. 7.42, IR =

F b + 2 I I = F b (1 + b ) + 2 I I , IC 2 =
FG b IJ I
GH 1/ + b a1 + b f JK GH a1 + b f JK
2 E 2 E
H1 + b K E
IC 2 Ê b (1 + b ) ˆ Ê 1 ˆ Ê 1 ˆ
= Á 2 ˜ =Á ˜ = Á ˜
IR Ë b + b + 2 ¯ Ë 1 + 2/ ( b 2 + b ) ¯ Ë 1 + 2/ b 2 ¯
Biasing
297
VCC - VBE 3 - VBE1

IR =
R
Thus, IC2 =
FG 1 IJ I = FG 1 IJ F V CC - VBE 3 - VBE1 I
H1 + 2/ b K H1 + 2/ b K H
2 R 2
R K
From above equation it is clear that the error in IC2 due to finite value of b has been reduced to 2/b2
in Fig. 7.42. The error has become much less in this circuit. The increase in another parameter output
resistance ro = rce can be understood from Fig. 7.43.
Figure 7.43 Output resistance demonstration

Let us suppose RE1 = rp ||RE
From Fig. 7.44

RS
vi = - rce gm +
1 UV m b v
vp - vp = - rce gm RE1 + 1 + RE1 p g r
T RE1 W RE1
ii = gm vp
F 1 IJ v = - FG 1 IJ v
- Gg +m
H R K HR K E1
p
E1
p
Figure 7.44 Simplified circuit for output resistance
Ro =
vi
=
RSb1 + g R g r
m E1 ce + RE1 UVb R g = R + b1 + g R g r
E1 E1 m E1 ce
ii T R E1 W
The modified Widlar current source with emitter resistance in emitter of T2 provides very large
b g
output resistance RE1 + 1 + gm RE1 rce . The output resistance rce of the BJT is multiplied by a factor of
(1 + gm RE1 ) .
298
7.8.5 Three-transistor Current Source (Wilson Source)

An alternative current mirror circuit shown in Fig. 7.45 achieves both base current compensation and
increased output resistance. This circuit is known as Wilson current mirror. Its output resistance is
approximately ( b / 2 )ro , a factor ( b / 2) higher than that of the simple circuit in Fig. 7.42. However, the
Wilson circuit suffers from low output voltage swing. The voltage at the collector of T3 must be slightly
higher than VBE2 + VCE3(sat) that is about a volt.
Figure 7.45 Wilson current source
IE3 = IC 2 + I B2 + I B1
=
FG b IJ I + FG 1 IJ I + FG 1 IJ I = FG 2 + b IJ I
E E E E
H1 + bK H1+ b K H1+ b K H 1+ b K
2+b
IB3 = IE
(1 + b ) 2
IR = I B3 + IC1 =
b +2
2 IE +
bFG IJ
IE =
b 2 + 2b + 2
IE
a f b +1 H K
1+ b b +1
2
a f
2
IC 3 F b IJ ab + 1f =
=G
ab + 1fb
IR H 1 + b K b + 2b + 2 b
2 2
+ 2b + 2
VCC - VBE3 - VBE 2 VCC - 2VBE
IR = =
RC RC
IC3 =
( b + 2 )b
IR = 2
RS
( b + 2 )b UV FG V CC - 2VBE IJ
2
b + 2b + 2 b + 2b + 2
T WH RC K
Biasing
299
=
1 FG V - 2V IJ
CC BE
FG1 + 2 IJ H R K C
H b + 2b K
2
=
1 FG V - 2V IJ
CC BE
FG1 + 2 IJ H R K C
H bK 2
IE2
Here, error due to finite value of is reduced to 2/b2 from 2/b.
1+ b
IC 3 I R = ( b + 2 ) b / ( b 2 + 2 b + 2 ) I R - I R = - 2 I R / ( b 2 + 2 b + 2 )
Example 7.6
Obtain change in IC3 for corresponding change in b from 10 to 100.
Solution
IC3 (b = 10) ( b + 2 )b (10 + 2)10 120
= 2 = = = 0.984
IR b + 2b + 2 100 + 20 + 2 122
IC3 ( b = 100) (100 + 2)100 102 ¥ 100 10200
= = = = 0.999
IR 10000 + 200 + 2 10202 10202
This indicates that the change in collector current IC3 is very small.
7.8.6 Temperature Compensated Current Sink

We have seen in diode compensation of the discrete biasing of BJT that the biasing current can be made
independent of VBE, i.e. independent of temperature. Fig. 7.46 shows such a circuit.
From Figure 7.46, V1 = R1 ( IC + I B + I B ) + VBE1 + VBE 2 + R2 ( IC + I B )
or, V1 = R1 ( bI B + 2 I B ) + VBE1 + VBE 2 + R2 ( bI B + I B ) = R1( b + 2) I B + VBE1 + VBE 2 + R2 ( b + 1) I B
V1 - 2VBE = R1 (2b + 3) I B (for R1 = R2 and identical transistors)
V1 - 2VBE
IB =
(2b + 3) R1
Ê b ˆ Ê V1 - 2VBE ˆ Ê b ˆ Ê V1 - 2VBE ˆ Ê V - 2VBE ˆ

IC = bIB = Á ˜¯ @ ÁË 2(b + 1) ˜¯ =aÁ 1
Ë 2b + 3˜¯ ÁË R1 ÁË R1 ˜
¯ Ë 2 R1 ˜¯
!
Figure 7.46
FG 1 IJ I = FG 2 + b IJ I = FG 2 + b IJ FG b IJ FG V - 2V IJ
IR1 = IC + 2 I B = IC + 2 C C
1 BE
H b K H b K H b K H 2(b + 1) K H R K 1
F 2 + b IJ FG V - 2V IJ @ F 1 I FG V - 2V IJ
=G 1 BE 1 BE
H 2(1 + b ) K H R K H 2 K H R K
1 1
1. In the level shifter circuit shown in Fig. 7.47,

calculate the value of R for Vo to become
zero. Assume the internal drop across each
diode VD = VBE2 = 0.7 V and hfe is very large.
(Engg. Services 2000)
Figure 7.48
Solution:
Writing loop containing two diodes and VBE
results 2VD = VBE + REIE
Figure 7.47
Biasing
!
2VD - VBE 2 ¥ 0.7 - 0.7 or,

IE = =
270 270
( RB + RE )
FG I
C IJ
- (1 + b ) ICO
+ RE IC = VEE - VBE
=
0.7
= 2.6 mA
H b K
270
VE1 = 8.6 VBE = 7.9 V b (VEE - VBE ) + (1 + b )ICO ( RB + RE )
IC =
RB + (1 + b ) RE
7.9
Thus, R = = 3.04 K ∂I C (1 + b )( RB + RE )
2.6 SI = =
2. Calculate Vo in the circuit of Fig. 7.49.
∂I CO RB + (1 + b ) RE
Assume hfe to be very large and VBE = 0.7 V. 1+ b
=
(Engg. Services 2000) 1 + b RE / ( RB + RE )
12 ¥ 2.2 -b
VB1 = = 2.164 V and SVBE =
12.2 RB + (1 + b ) RE
VE1 = 2.166 0.7 = 1.466 V
1.466
IE1 = = 1.466 mA,
1K
VC1 = 12 3.9 × 1.466 = 6.283 V
VE2 = Vo = 6.283 0.7 = 5.583 V
Figure 7.50
4. In the circuit shown in Fig. 7.51 calculate

the value of output current Io for Vin = 5 V.
If V CE(sat) of T2 is 0.3 V, calculate the
maximum value of RL that can be used in
the circuit. (Engg. Services 2000)
Solution:
5V
VE1 = 5 V , IE1 = = 5 mA
1K
Figure 7.49
VC1 = 15 1.8 ¥ 5 = 6 V,
3. Derive an expression for the stability factor 15 - 6 9
of the circuit shown in Fig. 7.50 VE2 = 6 V, IE2 = = = 9 mA
1K 1K
Solution:
IE2 = Io = 9 mA
VEE = RBIB + VBE + REIE
6 - 0.3 5.7
= (RB + RE)IB + REIC + VBE RL(max) = = = 633 W
9 mA 9 mA
!
Figure 7.51
5. Determine the Q-point in the circuit of fixed Solution:
base bias shown in Fig. 7.5. Given RB =
12 = 1 K ¥ I C + 100 K ¥ I B + 0.7
470 K, RC = 2 K , VBE = 0.7 V, VCC = 12 V,
= 1 K ¥ bIB + 100 K ¥ IB + 0.7
b = 100.
= 200 KIB + 0.7
Solution:
11.3
V - VBE 12 - 0.7 IB = = 0.057 mA,
IB = CC = = 0.024 mA, 200 K
RB 470 K
I C = b I B = 100 ¥ 0.057 mA = 5.7 mA
IC = 100 ¥ 0.024 mA = 2.4 mA
VCE = 12 2 K ¥ 2.4 mA = 12 4.8 VCEQ = 12 1 K ¥ 5.07 mA = 6.3 V
= 7.2 V 8. Calculate the value of R1 in the circuit of
6. Obtain the Q-point in the case of collector voltage divider emitter bias shown in Fig.
to base and emitter bias circuit shown in Fig. 7.25. Given VCC = 12 V , R2 = 10 K , RE =
7.22. 1 K, IC = 2 mA , IB = 50 mA , VBE = 0.2 V.
Given RB = 100 K , RC = 1 K = RE , VCC Solution :
= 12 V , VBE = 0.7 V , b = 100. 12 ¥ 10
VB = = 0.2 + 1 K ¥ 2 mA = 2.2 V,
Solution: R1 + 10
12 = 1 K ¥ IC + 100 K ¥ IB + VBB + 1 K ¥ IB 12 ¥ 10
R1 + 10 = = 54.55, R1 = 44.55 KW .
@ 2 KbI B + 100 I B + 0.7 = 300 KI B + 0.7 2.2
11.3 9. Obtain the Q-point in voltage divider with
IB =
300 K emitter bias circuit shown in Fig. 7.25.
= 0.038 mA, and Given: VCC = 12 V , R1 = R2 = 10 K , RC =
1 K, RE = 5 K , VBE = 0.7 V , b = 100.
I C = b I B = 0.038 mA ¥ 100 = 3.8 mA
Solution:
VCEQ = 12 2 K ¥ 3.8 mA = 4.4 V
7. Obtain the Q-point in the case of collector 12 ¥ 10
VB = = 6 V,
to base bias circuit shown in Fig. 7.9. Given 20
VCC = 12 V, VBE = 0.7 V, RC = 1 K, b = 100, RB = 5 K , 6 = 5 K ¥ I B + 0.7 + 5 K ¥ b I B
RB = 100 KW. = 505KI B + 0.7
Biasing
!!
5.3 I C = bI B + (1 + b ) I CO ,
IB = = 0.0105 mA,
505 K b (VCC - VBE ) +
I C = b ¥ 0.0105 mA = 1.05 mA (1 + b ) ICO ( RB + RE )
IC =
RB + (1 + b ) RE
VCEQ = 12 6 K ¥ 1.05 mA
= 12 6.3 = 5. 7 V b K1Dt + (1 + b ) ICO1
10. In fixed base with emitter bias of Fig. 7.14, (eK 2 Dt - 1)( RB + RE )
obtain the variation in the quiescent collector DIC =
RB + (1 + b ) RE
current for the variation of b from 50 to
100. 100 ¥ 2.5 ¥10 -3 ¥150 +
Given VCC = 12 V, RB = 60 K, RE = 1 K, VBE
= 0.7 V, ICO = 0.1 mA. 1.2 K ¥ 10 -7 ¥ 101( e0.07 ¥ 150 -1)
=
1 K + 101 ¥ 0.2 K
Solution:
VCC = RB I B + VBE + RE ( IC + I B ) 37.5 + 1.21 ¥ 32.12 ¥ 10 -2
= RB I B + VBE + RE ( b + 1) I B =
21.2 K
VCC - VBE I (1 + b ) ICO
IB = = C - 37.5 + 0.39 37.89
RB + (1 + b ) RE b b = = = 1.78 mA
21.2 K 21.2 K
b (VCC - VBE ) + (1 + b ) ICO ( RB + RE )
ICQ = 12. Obtain the current I flowing through 2 K
RB + (1 + b ) RE
resistor in Fig. 7.52 if the transistors have
50(12 - 0.7) + 51 ¥ 10 -7 ¥ 61 K high values of b and VBE = 0.65 V.
=
60 K + 51 ¥ 1 K
50 ¥ 11.3
@ = 5.09 mA
111 K
200 ¥ 11.3
ICQ2 (b = 200) =
60 K + 201 ¥ 1 K
2260
= = 8.66 mA
261 K
Change in ICQ = (8.66 - 5.09)mA
= 357 mA
11. In the circuit of two-voltage bias, obtain the
variation in the quiescent collector current
for the variation in the temperature from
25°C to 175°C. Assuming b = 100. Given
VBB = 3 V , ICO = 107A , RB = 1 K , RE Figure 7.52
= 0.2 K.
Solution: Solution:
VBB = RB I B + VBE + RE ( IC + I B ), IB2 = IB1 = 0 ,
!"
Current through 6.5 K + 1.85 K + 1.65 K and VC1 = 3 V assuming VBE = 0.7 V and
very high value of b.
10
= = 1 mA Solution:
10 K
9
VB1 = 1.65 V = 0.65 + 1K ¥ I E1 I= , VB 2 = 3 + 0.7 = 3.7 V ,
R1 + R2 + 18 K
I = IE1 = IC1 = IC2
VB1 = 0.2 + 0.7 = 0.9 V
1.65 - 0.65 0.9 V 3.7 - 0.9
= = 1 mA Hence, I = = 0.05 mA, R2 =
1K 18 K 0.05 mA
13. Determine the values of R1 and R2 in the 2.8
circuit of voltage divider emitter bias shown = = 56 KW
in Fig. 7.25. 0.05 mA
VCC = 12 V, VBE = 0.2 V, ICQ = 18 mA, IBQ 9 3.7 5.3

R1 = = = 106 K W ,
= 0.3 mA, SI = 10, b = 100 0.05 mA 0.05 mA
VCEQ = 4.2 V, RC = 0.33 K, RE = 0.1 K, VBE 96 3
= 0.2 V RL = = = 3 KW
1 mA 1 mA
Solution:
VBB = RB I B + VBE + RE IE
= RB ¥ 0.3 mA + 0.2 + 0.1 K ¥ 18 mA
= 2 + 0.3 RB mA
(1 + b )( RB + RE )
SI = 10 =
RB + (1 + b ) RE
101( RB + 0.1 K)
=
RB + 101 ¥ 0.1 K
RB + 10.1 K = 10.1RB + 1.01 K

or, RB @ 1 K
Now, VBB = 2 + 0.3 mA ¥ 1 K = 2.3 V Figure 7.53
R1 + R2 = 5.22R2 15. In the common-emitter amplifier shown in
or, R1 = 4.22R2 Fig. 7.54, the transistor has a forward gain
of 100 and VBE = 0.6 V . Assume ICO to be
If R2 = 1.2 K, then R1 = 5 K, and if R2 = negligible. Calculate values of R1 and RC
5K, then R1 = 21.1 KW such that the transistor has a collector current
14. In the cascode amplifier circuit in Fig. 7.53, of 1 mA and VCE = 2.5 V.
determine values of R1 , R2 and RL such that Solution:
the quiescent current through transistors
is 1mA and the collector voltage VC2 = 6 V 50
= 0.01
FG
10 R1 IJ
+ 0.6 + 0.3
R1 + 10 H
R1 + 10 K
Biasing
!#
=
FG 0.1R IJ + 0.9
1
H R + 10 K
1
50 = 0.1R1 + 0 .9 R1 + 9
R1 = 50 9 = 41 KW
RC ¥ 1 mA = 5 2.5 0.3 = 2.2 V
2.2
Hence, RC = = 2.2 KW
1 mA
Figure 7.56
Figure 7.54
Figure 7.57
Solution:
Vo = 0.2 V, Transistor T3 is saturated. T2
is off.
Figure 7.55 VE4 = 0.7 V, VB4 = 0.7 + 0.7 = 1.4V, VB1
= 2.1 V
16. For the TTL circuit shown in Fig. 7.56, find
the current through the collector transistor 5 - 2.1 2.9
T4 when Vo = 0.2 V. Assume VCEsat = 0.2 V, IB1 = = = 0.0725 mA ,
40 K 40 K
b = 100 and VBE = 0.7 V. The a of transistor
T1 in its inverse active mode is 0.01. Assuming T4 saturated, VC4 = 0.7 + 0.2
= 0.9 V
!$
5 - 0.9 4.1
IC4 = = = 0.205 mA
20 K 20 K
17. The circuit shown in Fig. 7.58 supplies
power to an 8 W speaker. Obtain the values
of IC and VCE for the circuit.
Solution:
Writing loop equation through T2 , positive
and negative power supplies and the current
source yield Figure 7.58
15 - VBE - 4 ¥ I E 2 + 15 = 0 18. A transistor with hfe = 100, VBE = 0.6V, VCC
4 I E 2 = 30 - 0.7 = 29.3 = 22.5 V, RC = 5.5 K is used in the circuit of
Fig. 7.59. The Q-point is desired to be at
29.3
IE2 = = 7.32 mA VCEQ = 12.5 V , IC = 1.5mA, and SI £ 2.
4 Find the values of R1, R2 and RE. (IETE )
VCE2 = 30 29.3 = 0.7 V
Figure 7.59
Solution: b (VCC - VBE ) + bICO ( RB + RE )

ICQ =
1.5 mA RB + (1 + b ) RE
IB = = 0.015 mA
100 VCC = RC IC + VCEQ +
VB = RB I B + VBE + RE I E RE
FG I
C IJ
- I CO + RE I C
= ( RB + RE ) I B + VBE + RE IC
Hb K
Ê 1.5 ˆ
FI I 5.5 K ¥ 1.5 mA + RE Á + 1.5˜
= ( RB C
+ R )G - I J +V + RE IC Ë 100 ¯
E CO BE
Hb K = 22.5 12.5 = 10
{RB + (b + 1) RE }I C b ( RB + RE ) I CO = 1.5 mARE = 10 8.25 = 1.75 V,
b(VB - VBE ) 1.75
RE = = 1.16 KW
1.5
Biasing
!%
b ( RB + RE ) IC2 IC1 = DIC = K (VBE 2 - VBE1 ) = KDVBE

S1 = 2 =
RB + (1 + b ) RE DIC KDVBE
Hence, =
100( RB + 116
. ) 100 RB + 116 IC1 K(VCC - VBE1 )
= =
RB + 100 ¥ 116
. RB + 116 DVBE
=
(VCC - VBE1 )
2 RB + 116 ¥ 2 = 100 RB + 116 ,
1
116 As per the problem, 1% =
98RB = 116 and RB = = 1.18 KW 100
98 DVBE DVBE DVBE
= = =
VB = 1.18 K ¥ 0.015 mA + 0.6 + (VCC - VBE1 ) 10 - 0.7 9.3
1.16 K ¥ 1.5 mA 9.3
= 0.018 + 0.6 + 1.74 = 2.358 V ª 2.36 V Fall in the VBE = = 93 mV
100
R1 R2 V R Since VBE changes 2.2 mV/°C, the rise in
RB = , VB = CC 2 ,
R1 + R2 R1 + R2 93 mV
temperature = = 42.3∞C .
VB V 2.36 22.5 2.2 mV / ∞C
= CC and =
RB R1 1.18 K R1
22.5 ¥ 1.18 K
or, R1 = = 11.25 KW
2.36
( R1 + R2 )1.18 K = 11.25 × R2
(11.2 1.18)KR2 = 118K
. R1
10.02R2 = 13.216 K,
R2 = 1.32 KW
19. The current mirror of Fig. 7.60 is designed
to provide IC = 0.5 mA, VCC = 10 V, b =
125. Obtain the value of R. If VBE changes
by 2.2 mV/°C, what would be the permissible
Figure 7.60 Current mirror
temperature range if ICI is to remain within
1% of its nominal design value. 20. Design a CE amplifier shown in Fig. 7.61
Solution: using potential divider biasing to meet the
following specifications.
R=
FG b IJ FG V CC - VBE IJ SI = 5, IC = 1 mA, VCE = 5 V, VCC = 10 V,
H b + 2K H IC K b = 100, VBE = 0.6 V, RE = 1 K
Ê 125 ˆ Ê 10 - 0.7 ˆ Solution:
= Á = 18.3 K
Ë 127 ˜¯ ÁË 0.5 mA ˜¯
VCC = ( RC + RE ) IC + VCE
IC1 = K(VCC - VBE1 ) and 10 - 5
I C2 = K(VCC - VBE 2 ) RC + RE = =5K
1 mA
!&
Figure 7.61
Hence, RC = 5 K 1 K = 4 KW 10R2 = 1.6( R1 + R2 ) = 1.6 ¥ 26.25 + 1.6 R2

VB - VBE = ( RB + RE ) I B + RE IC 8.4R2 = 1.6 × 26.25
IC - (1 + b ) ICO 1.6 ¥ 26.25
= ( RB + RE ) + RE IC R2 = = 5 KW
b 8.4
21. In the symmetrical current mirror of Fig.
{RB + (1 + b ) RE }IC - (1 + b ) ICO (RB + RE )
= 7.60 V CC = 5 V, R = 5 K, b = 200.
b Determine IC1, b1 and b2 for ±1% change
(VB - VBE )b + (1 + b ) ICO ( RB + RE ) in IC1.
IC =
RB + (1 + b ) RE Solution:
DIC (1 + b )( RB + RE ) IC1 =
FG b IJ F V CC - VBE I
SI = = H b + 2K H R K
DICO RB + (1 + b ) RE
(100)( RB + 1) Ê 200 ˆ Ê 5 - 0.7 ˆ
@ =5 = Á
RB + 101 Ë 200 + 2 ˜¯ ÁË 5 K ˜¯
100 RB + 100 = 5 RB + 505

Ê 200 ˆ Ê 4.3 ˆ
= Á = 0.85 mA
95RB = 405 Ë 202 ˜¯ ÁË 5 K ˜¯
405 R1R2 IC 2 b / (1 + b 2 ) b 2 (1 + b 1 )
or, RB = = 4.263 = , a
= 2 = 2 =
95 R1 + R2 IC1 a 1 b 1 / (1 + b 1 ) b 1 (1 + b 2 )
VB @ VBE + RE I E IC 2 - IC1 b (1 + b 1 ) - b 1 (1 + b 2 )
= 2
10 R2 IC1 b 1 (1 + b 2 )
= 0.6 + 1 = 1.6 V =
R1 + R2 =
b 2 - b1
b 1 (1 + b 2 )
10 1.6
= DIC 0.01 b - b1 b 2 - b1
R1 4.263 = = 2 =
IC1 0.85 b 1 (1 + b 2 ) 100(1 + b 2 )
4.263 ¥ 10
or, R1 = = 26.25 KW 0.85
1.6 b 1 (1 + b 2 ) = ( b 2 - b 1 ) = 85b 2 - 85b 1
0.01
Biasing
!'
b 2 ( b 1 - 85) = -85b 1 - b 1 = - 86 b 1 23. What will be the size of EBJ of transistor T3

w.r.t. transistor T1, if 2mA of current is to
-86b1 -86 ¥ 200
b2 = = = - 149.56 be reflected through the collector of T3?
b1 - 85 115
22. Obtain the collector current of each transitor
for a transitor array CA3086 in Fig. 7.62
shown with b dc = b ac = 100 and VBE =
0.715 V.
Figure 7.63
Solution:
10 - 0.7 9.3
IR = =
18.7 K 18.7 K
Figure 7.62 = 0.497 mA ª 0.5 mA
Solution: Hence, to reflect 2 mA of collector current
10 - 0.715 9.285 in T3 = four-number of T1 must be put in
IR = = = 1.658 mA parallel and hence, the area of EBJ must be
5.6 K 5.6 K
equivalent to four-times the area of T1.
Hence, collector current of each transistor 24. Obtain the voltage across transistor T4 in
T2, T3, and T4 = 1.658 mA. Fig. 7.64.
Figure 7.64
!
Solution: Now, if we select IR = 1 mA and VBE1 =

10 - 0.7 0.7 V for Fig. 7.66 also, then
IR = = 0.93 mA
10 K 10 - 0.7
R= = 9.3 KW
VCE4 = 10 + 5.07 = 15.07 V 1 mA
25. Figs. 7.65 and 7.66 are used to generate IR
IO RE = 10 ¥ 10 -6 RE = VT ln
constant currents IO = 10 mA. What values IO
of resistors will be used in these circuits 1 ¥ 10 -3
assuming VBE2 = 0.7 V at a current of 1 mA. = 0.025 ln
10 ¥ 10 -6
Neglect the effect of finite b.
= 0.025 ¥ ln 100 = 0.115
0.115
or, RE = = 11.5 KW
10-5
26. The BJTs T1 and T2 are identical in Fig.
7.67 and current amplifications for T1 and
T3 are b and b* respectively. Obtain the
I
ratio of C 2 .
IR
Figure 7.65 Solution:
I
IR = IC1 + I B3 = IC1 + *E3 ,
b +1
2 IC1
I E3 = I B1 + I B2, IE3 = 2 I B1 = ,
b
2 IC1
IR = IC1 + ,
b (b * + 1)
2 + b (b * + 1) IC1
IR = ,
b (b * + 1)
Figure 7.66
IC1 I b (b * + 1)
= C =
Solution : IR IR 2 + b (b * + 1)
IO
For Fig. 7.65, VBE1 = VBE 2 + VT ln
IR
Ê 10 ¥ 10 -6 ˆ
= 0.7 + 0.025 ln Á
Ë 1 ¥ 10 -3 ˜¯
= 0.7 + 0.025 ln 0.01
= 0.7 - 0.115 = 0.585 V
10 - 0.585
R= = 94.15 KW
1 mA
Figure 7.67
Biasing
!
27. Show that the ratio of collector current IC IC 1

=
to the source current IR in a current mirror IR n +1
1+
circuit where a current source biases a b ( b * + 1)
number of BJTs is given by
(in previous problem n = 1).
Questions for Practice 5. The voltage divider bias is used to make

the Q-point
1. Why is the bias stabilization required in tran- (a) independent of b
sistor amplifiers? What are the various bias (b) independent of VBE
stabilization methods? Draw the circuits and (c) dependent of b
discuss their relative advantages and disad-
6. Most popular bias arrangement is
vantages.
(a) fixed base bias
2. Draw fixed bias and a self-bias circuit for (b) collector to base bias
CE configuration. Discuss the operation of (c) voltage divider bias
each circuit and hence, explain which circuit
7. Improper biasing leads to
gives better stability.
(a) distortion in output
(b) distortion in input
(c) heavy loading
Multiple Choice Questions
8. For an amplifier junctions of BJT should
1. The maximum output swing can be ob- be biased as
tained when the Q-point is (a) base-emitter and base-collector both
(a) near saturation point reverse biased
(b) near cut-off point (b) base-emitter forward and base-collec-
(c) in the middle of the load line tor reverse biased
(c) base-emitter and base-collector both
2. What value of stability factor should be forward biased
selected?
(a) infinity (b) zero 9. The stability factor lies in between
(c) finite (a) zero and unity
(b) unity and (1 + b)
3. For good stability the Q-point should (c) (1 + b) and infinity
(a) vary (b) fixed
(c) none of these 10. The best Q-point in an amplifier for faith-
ful reproduction of the signal is selected
4. The positive peak of the signal will be (a) near cut-off
clipped off if the Q-point shifts towards (b) near saturation
(a) cut-off (b) saturation (c) in the middle of the active region
(c) active regions
!
11. With increasing value of the stability fac- 15. The stability factor S = b + 1 is in the case
tor, the Q-point of
(a) becomes poor (a) fixed base bias
(b) becomes better (b) collector to base bias
(c) is not affected (c) fixed base bias with emitter resistance
12. The thermal stability of fixed base bias cir- 16. The stability factor of collector to base bias
cuit is is better
(a) poor (b) good (a) w.r.t. the fixed base bias
(c) best (b) collector to base bias with emitter re-
13. In the saturation region of the BJT sistance
(c) self bias
(a) VCE = VCC (b) VCE @ 0
17. Inclusion of an emitter resistance in any
(c) VCE = 5V type of biasing circuit
14. The bypass capacitor across the emitter (a) improves stability factor
resistance (b) worsens stability factor
(a) increases the emitter current (c) does not change stability factor
(b) increases the output signal
(c) improves the stability factor

1. (c) 2. (c) 3. (b) 4. (b), (a) 5. (a) 6. (c)
7. (a) 8. (b) 9. (b) 10. (c) 11. (a) 12. (a)
13. (b) 14. (b) 15. (a) 16. (a) 17. (a)
8
BJT Amplifiers
8.1 Introduction
The word amplifier means a circuit that boosts the amplitude of the input signal retaining its other
parameters, i.e. frequency and phase. The amplifiers are classified in many ways. The following inherent
characteristics can be used for classifying them:
∑ Frequency range of operation (audio, radio, video)
∑ Duration of conduction angle
∑ Input signal magnitude
∑ Types of output signal
∑ BJT configurations
∑ Interstage coupling, etc.
8.1.1 Frequency Range of Operation

The range of frequency of operation of any amplifier specifies a particular frequency range within
which it can work. The following frequency ranges can be used to describe the name of a particular
amplifier:
∑ audio range (20 Hz to 20 kHz)
∑ radio range (few kHz to hundreds of kHz)
∑ video range (few MHz).
!"
8.1.2 Duration of Conduction

Another way of classifying the amplifier is by the conduction angle over which it works. The amplifier
biasing determines the duration of conduction angle of an amplifier w.r.t. full cycle of the input signal.
The duration of conduction of amplifier depends upon the fixation of the bias point and the extent of use
of the output characteristics of the transistor used in the amplifier. Hence, it is classified according to
the period of conduction as
∑ Class- A amplifier
∑ Class-B amplifier
∑ Class-AB amplifier
∑ Class-C amplifier
∑ Class-D amplifier
Class-A Amplifier
In Class-A amplifier, the amplified output is present for the complete cycle of the input signal. In other
words, the amplified output signal shape is the faithful reproduction of the input signal as depicted in
Fig. 8.1(a).
Since the amplified output signal shape is exactly the same as the input signal, the distortion is
minimum at the cost of power conversion efficiency. The maximum theoretical power conversion
efficiency of class-A amplifier could be as high as 25%. It is achieved when the amplifier is biased in the
middle of the output characteristics of the BJT along the load line to produce the maximum swing in
both positive and negative half-cycles of the output voltage and current.
Class-B Amplifier
The output of the Class-B amplifier should be present for only one half-cycle of the input signal as
demonstrated in Fig. 8.1(a). Practically the amplifier conducts for slightly less than half-cycle determined
by the crossover distortion. The theoretical power conversion efficiency is more than that of class-A
configuration and is equal to the maximum of 50%. Since the output is only for one half-cycle of the
input signal, the distortion is more w.r.t. Class-A.
Figure 8.1(a) Output waveform of amplifiers

BJT Amplifiers
!#
Class-AB Amplifier
The crossover distortion present in perfect Class-B is responsible for more distortion in the amplified
output. If this crossover distortion is cancelled by application of external forward bias equal to the
inherent potential barrier present across the base-emitter junction, the amplifier is called Class-AB as
depicted in Fig. 8.1(a). Hence, in Class-AB operation, the amplifier conducts for perfectly one half-
cycle. The theoretical power conversion efficiency is the same as that in the case of Class-B amplifier
but distortion is less.
Class-C Amplifier
The amplified output of Class-C amplifier is for a very small fraction of the input cycle as demonstrated
in Fig. 8.1(a). Not only distortion but power conversion efficiency is also maximum in this case. The
Class-C amplifiers are used for amplification of carrier frequency wherein distortion does not have
much significance.
Class-D Amplifier
Class-D amplifier is designed to operate with digital or pulse input that are ON for a very short interval
and OFF for long interval. The major advantage of class-D operation of the amplifier is very less
dissipation as it is ON for a very short interval of time, draining the current from the power supply and
hence its efficiency is high. Fig. 8.1(b) is the block diagram of class-D amplifier. This figure amplifies
the class-D type of signal and then converts it back to the sinusoidal type signal using a low-pass filter.
Since the BJT used in the class-D amplifier is basically ON or OFF, they provide current for a very short
duration when they are turned ON. This allows the class-D amplifier to dissipate very little power during
ON period. Thus, the power conversion efficiency is very high as most of the power applied to the
amplifier is transferred to the load. The power MESFET devices are very popular as driver devices for
the class-D amplifier.
Figure 8.1(b) Block diagram of class-D amplifier
A brief comparison of different classes of amplifiers is given in Table 8.1.
Table 8.1 Comparison of class-A, B, AB, and C amplifiers
Class Conversion efficiency Conduction angle Distortion

Class-A 25 % 0 to 2p minimum
Class-B 50 % 0 to < p medium
Class-AB 78.5 % 0 to p minimum
Class-C > 90 % 0 to < p/2 maximum
!$
Yet, another method to define the type of amplifier is based on the signal handling capability of the
amplifier depending upon input and output signals magnitudes.
8.1.4 Input Signal Magnitude

The maximum magnitude of the input signal defines the signal handling capability of the amplifier. If the
input signal is small, the amplifier is called small signal amplifier. On the other hand, if the input signal is
large, the amplifier selected for the proper operation is called large signal amplifier. The examples of
large signal amplifiers are power amplifiers.
8.1.5 Types of Output Signal

The voltage amplifier can provide large amount of voltage swing but not the current swing simultaneously.
Similarly, a current amplifier provides sufficient amount of current swing but not the voltage swing at
the same time. The power amplifier, however, provides sufficient amount of both voltage and current
swings simultaneously.
8.1.6 BJT Configurations

The types of amplifiers based on the BJT amplifier configurations are:
∑ Common base amplifier (CB)
∑ Common Emitter amplifier (CE)
∑ Common Collector amplifier (CC).
These classifications are based on using one of the three-terminals as common to both input and
output sides. Another method of classifying the amplifier is based on the method of interstage couplings.
8.1.7 Interstage Coupling

The input and output ports of any amplifier have to be connected to the source, load or to the next stage
of the similar type of amplifier(s) without loading the source or loading the output of the amplifier.
Hence, the output of one amplifier is not connected directly to the input of another amplifier through
wires, but through some interface without disturbing the output condition of the first amplifier and the
input conditions of the second amplifier. This interface is called interstage coupling. The general interstage
coupling methods are:
∑ RC coupling
∑ Transformer coupling
∑ Impedance coupling
∑ DC coupling, i.e. no reactive coupling used.
8.2 Qualitative Comparison of BJT Configurations

The qualitative advantages of one configuration of BJT amplifier over the others are taken up for giving
an idea to the reader for their use in a particular situation. Later on quantitative analysis will be taken up.
The symbolic representation of a transistor (BJT) has three leads. The emitter lead is identified by an
arrow that points to the direction of the conventional current flow under forward bias condition. The
BJT Amplifiers
!%
conventional current flows in the direction of the movement of the positive charge carriers (holes).
Middle lead is the base and the third lead (at the other end) is the collector.
8.3 Current Amplification Factor

A very crude definition of the current amplification factor is as the ratio of output current to the input
current. Figure 8.2 shows Common Base (CB), Common Emitter (CE) and Common Collector (CC)
configurations.
Case I: CB Configuration
The output current in common base configuration is IC and the input current is the emitter current IE as
illustrated in Fig. 8.2.
Figure 8.2 Three configurations of ICEO
Hence, the current amplification factor is defined as

IC
a= (8.3.1)
IE
Typically more than 98% charge carriers from emitter reach the collector and hence, the current
amplification ratio is approximated as
98
a= = 0.98 (8.3.2)
100
Numerically IC is less than IE and hence, a is always less but very near to unity i.e. 0.98, 0.99 or
0.999.
Case II: CE Configuration

In Common Emitter configuration, the output current is IC but the input current is base current IB as
depicted in Fig. 8.2. Hence, the current amplification factor is given by
IC 98
b= = = 49 (8.3.3)
IB 2
Here, b is associated with the phase shift of 180°. The denominator is much smaller than the numerator
so b is much larger than a.
!&
Case III: CC Configuration

The output current in the Common Collector configuration is the emitter current IE and the input current
is the base current IB as demonstrated in Fig. 8.2. Hence, the current amplification factor in CC
configuration is
IE I + IB I
b* = = C = 1+ C = 1 + b (8.3.4)
IB IB IB
From Eqn. 8.3.2, 8.3.3, and 8.3.4 it is evident that current amplification factor is minimum in CB
configuration (a), medium in CE configuration (b), and the maximum in CC configuration (b + 1).
8.4 Physical Explanation for ICBO and ICEO

The first two subscript letters C and B in ICBO stand for current flow between collector-to-base terminals
when the third terminal (emitter), indicated by the third subscript letter O, is left open.
Figure 8.3(a) Circuit for ICO (b) Equivalent circuit for ICO
In Figs. 8.3(a) and (b) the collector-base junction is reverse biased, keeping the emitter open, which
effectively widens the depletion width across base-collector junction that allows only minority carriers
to drift across the collector junction. This leads to the reverse saturation current or cut-off current ICBO
that is usually denoted as ICO and is negligibly small. This is called collector to base current when emitter
is left open (ICBO = ICO).
Figure 8.3(c) shows the circuits for physical explanation of the ICEO. The leakage or cut-off current
in common emitter configuration of a transistor when the base is left open can be denoted as ICEO. This
is read as current between the collector and emitter leads when the base lead is left open. From circuit
of Fig. 8.3(c),
Figure 8.3 (c) Physical explanation of ICEO

BJT Amplifiers
!'
I CT = bIBT, IC = ICT + ICO, and IBT = ICO when base is open, i.e. ICT = bICO (8.3.5)
I C = bICO + ICO = (1 + b)ICO (8.3.6)
In circuit of Fig. 8.3(c) ICO is the input (base) current and it is amplified b times to become ICT.
Hence, total collector current IC is
I C = ICO + ICT (8.3.7)
8.5 BJT Ratings

With different constructional geometry several thousand types of BJTs are made including both Si and
Ge of p-n-p and n-p-n structures. An example of rating is shown in Fig. 8.4. In order to help the
customers or users in selecting a proper BJT for a particular application, manufacturers publish data
sheets, manuals and application notes, etc. Among many other quantities, the manufacturer usually
specifies the permissible values of VCE, IC, device dissipation, and maximum allowable junction
temperature. For example, the transistor is listed to have a maximum continuous IC of 10 A and maximum
VCE of 60V. Also the maximum continous device dissipation is 30 W. These three-values define the
permissible region of operation of a particular transistor. A reasonable approximation for the dissipation
at the collector is the product of the collector voltage and current, i.e.
PJ = VCE ¥ IC = PC (8.5.1)
where, PJ = PC is the permissible power dissipation
I C = Quiescent collector current and
VCE = Quiescent collector-emitter voltage
Figure 8.4 Maximum collector dissipation hyperbola
The safe permissible range of operation of BJT can be shown on the maximum collector dissipation
hyperbola is CE configuration as depicted in Fig. 8.4. It has five distinct boundaries. The two boundaries
are described by the transistor characteristics, one being the cut-off region and the other being the
saturation region. The other three are provided by the maximum value specified by the manufacturers
for the collector current, collector-emitter voltage and total power. Manufacturers specify different
!
breakdown voltages as BVCEO and BVCBO. The first two subscripts denote the two terminals between
which the voltage is to exist and the last letter O denotes open, i.e. the measurement is made with the
third terminal left open.
The maximum power curve is obtained by choosing the value of IC lower than IC(max) and calculating
the value of PJ to give specified maximum permissible power.
8.6 Input Resistance

The input resistance in any configuration of BJT amplifier is defined as the ratio of input voltage to input
current keeping the output current zero (the output terminals are left open circuited) as indicated in Fig.
8.5(a) and (b). The dc resistance in case of CB configuration is expressed as
VEB VEB
Ri (CB) = = (8.6.1)
ICO + I BT IC = 0
IE IE = 0
In Fig. 8.5(a) since IC = 0, ICT = ICO

IE = IEO = ICT + IBT = ICO + IBT (8.6.2)
VEB
Hence, Ri (CB) = (8.6.3)
ICO + I BT
Figure 8.5(a) CB configuration (b) CE configuration
This is the resistance of a forward biased diode that can be very low and of the order of a few ohms.
Typical value is 20 W to 0.1 KW. The low input resistance in CB configuration is due to the ratio of very
small forward bias voltage between the base-emitter junction to the large emitter current IE.

The input resistance of BJT in CE configuration is defined from Fig. 8.5(b) as
VBE
Ri (CE) = (8.6.4)
IB IC = 0
BJT Amplifiers
!
IB + ICO = IBT, IC = ICT + ICO = 0 (8.6.5)

IB = IBT ICO (8.6.6)
VBE
Thus, Ri(CE ) = (8.6.7)
I BT - ICO
It is evident from comparing Eqns. 8.6.1 and 8.6.7 that the magnitude of numerators, i.e. | VBE | =
|VEB| are exactly equal in both cases whereas the denominator of Eqn. 8.6.7 is much smaller than that of
Eqn. 8.6.1 and hence Ri(CE) > Ri(CB). The input resistance in the case of CE configuration is higher than
that obtained in CB configuration. It is due to the ratio of small forward bias voltage between base-
emitter junction to the base current IB that is negligibly small w.r.t. either IC or IE.

The input resistance in CC configuration from Fig. 8.6 is expressed as
VBC
Ri(CC) = (8.6.8)
IB IE = 0
Figure 8.6 CC configuration
IE = IET = 0 means IBT = 0 (8.6.9)

IB + ICO = IBT (8.6.10)
|IB| = |ICO| (8.6.11)
VBC
Ri(CC) = (8.6.12)
I CO
It is clear from Eqns 8.6.3, 8.6.7, and 8.6.12 that the input resistance in CC configuration is the
highest as it is the ratio of very large reverse bias voltage between base-collector to the base current IB
that is insignificantly small w.r.t. IE or IC.
!
8.7 Output Resistance

The output resistance of any configuration of the BJT amplifier is defined as the ratio of output voltage
to the output current keeping the input current zero (input terminals left open).
The output resistance from Fig. 8.5(a) is expressed as
VCB
Ro(CB) = (8.7.1)
IC IE = 0
ICT + ICO = IC (8.7.2)

IE = IET = 0, ICT = 0 (8.7.3)
IET = ICT + IBT = 0, IBT = 0, and IC = ICO (8.7.4)
VCB
Hence, Ro(CB) = (8.7.5)
ICO
Since ICO is the leakage current and is of the order of microamperes, Ro(CB) is a much larger quantity
(500 KW).

The output resistance of BJT amplifier in CE configuration can be expressed using Fig. 8.5(b) as
VCE
Ro(CE) = (8.7.6)
IC IB = 0
IB + ICO = IBT and IC = ICT + ICO (8.7.7)

IB = 0, ICO = IBT (8.7.8)
I C = bIBT + ICO = (1 + b) ICO (8.7.9)
VCE V + VBE VCB
Ro(CE) = = CB @ (8.7.10)
(1 + b ) I CO (1 + b ) I CO (1 + b ) I CO
It is clear from comparing Eqns. 8.7.5. and 8.7.10 that Ro(CE) << Ro(CB).

The output resistance in CC configuration of BJT amplifier is written from Fig. 8.6 as
VCE
Ro(CC) = (8.7.11)
IE IB = 0
BJT Amplifiers
! !
I C = ICT + ICO, and IB + ICO = IBT, (8.7.12)

IB = 0, IBT = ICO, IC = bIB + (1 + b) ICO (8.7.13)
IET = IE = IC + IB = bIB + (1 + b) ICO + IB = (1 + b)IB + (1 + b)ICO
= (1 + b)IBT + (1 + b)ICO = (1 + b)ICO + (1 + b)ICO = 2(1 + b)ICO
VCE V + VBE VCB
Hence, Ro(CC) = = CB @ (8.7.14)
2(1 + b ) ICO 2(1 + b ) ICO 2(1 + b ) ICO
Comparing Eqns. 8.7.10 and 8.7.14 reveals that the value of the output resistance obtained from
Eqn. 8.7.14 is less than that obtained from Eqn. 8.7.10. Table 8.2 summarizes input resistance and
output resistance of all the three configurations of the BJTs. It is clear from Table 8.2 that the input
resistance is the maximum in CC configuration and the minimum in CB configuration. On the contrary,
the output resistance is maximum in CB configuration whereas it is the minimum in CC configuration.
Table 8.2 Comparison of CB, CE, and CC amplifier configurations

CB CE CC
VEB VBE VBC
Ri = min = med = max
IBT + ICO IBT - ICO ICO
VCB VCB VCB + VBE
Ro = max = med = min
ICO (1 + b ) ICO 2(1 + b ) ICO
8.8 Voltage Gain

The voltage gain of any amplifier is defined as the ratio of the output voltage to the input voltage. When
the load resistance RL is small in comparison to the output resistance of the transistor, IC is approximately
equal to IE. Assuming the transistor to be properly biased and neglecting the shunting effect of the
biasing resistors, the analysis of different amplifier configurations shown in Fig. 8.7 is now taken up.
Achieving amplification is surprising as the current amplification factor a of BJT amplifier in CB
configuration is less than unity. The output resistance of a BJT in CB configuration is very high (500 KW
to 1 MW) and load resistance is much smaller (1 KW to 5 KW) than the output resistance. Thus, the
output side of the CB amplifier configuration acts as a constant current source and hence, the total
collector current passes through the load resistance RL.
Figure 8.7 CB, CE, and CC amplifier configurations

! "
In other words, the amplification in the transistors is basically due to the capability of transferring this
signal current from low resistance input side to high resistance output side of the amplifier. Hence, the
name transistor was coined by contracting the two terms transfer and resistor as
The voltage gain is expressed as

v L vcb aie RL aRL
Av = = = = (8.8.1)
vs veb ie Ri Ri

The input voltage is the small forward bias across the base-emitter junction and the output voltage is
large due to large collector current flowing through the load resistance. Hence, the voltage gain in CE
configuration is high.
v L v ce bib RL bRL
Av = = = = (8.8.2)
v s v be ib Ri Ri

The voltage gain in CC configuration is defined as
v L vec (1 + b )ib RL (1 + b ) RL
Av = = = = (8.8.3)
v s vbc ib Ri Ri
Here vbc is the large input voltage across the reverse biased base-collector junction and vce is slightly
different from vcb. Thus, the voltage gain is less than unity.
8.9 Power Gain

The instantaneous input power is expressed as
P i = ie2 Ri (8.9.1)
The instantaneous output power developed across the load can be written as
Po = ic2 RL = a 2 ie2 RL (8.9.2)
2 2 2
a i e RL a RL
Hence, power gain = A p = 2
= (8.9.3)
( CB) ie Ri Ri

The instantaneous input power in CE configuration can be expressed as
BJT Amplifiers
! #
P i = ib2 Ri (8.9.4)
The output power developed across the load RL is
Po = ic2 RL = b 2ib2 RL (8.9.5)
2 2 2
b i b RL b RL
Ap = 2
= (8.9.6)
(CE ) i b Ri Ri

The instantaneous power in CC configuration can be expressed as
P i = ib2 Ri (8.9.7)
The output power developed across the load RL is
Po = ie2 RL = (1 + b ) 2 ib2 RL (8.9.8)
(1 + b ) 2 ib2 RL 2
(1 + b ) RL
Ap = = (8.9.9)
(CC ) ib2 Ri Ri
Now the input resistance Ri, the output resistance Ro, current amplification factor b, voltage gain Av,
power gain Ap for different transistor configurations are summarized in Table 8.3.
Table 8.3 Comparison of Ri, Ro, Ai, Av and Ap of CB, CE, and CC
CB CE CC
Ri Min. (20W) Med. (1KW) Max. (1MW)
Ro Max. (1MW) Med. (10KW) Min. (100W)
Ai Min. (a = 0.98) Med. (b = 100) Max. (1 + b)
Av Min. (aRL/Ri) Med. (bRL/Ri) Min.{(1 + b) RL/Ri}
Ap Min. (a2RL/Ri) Max. (b2RL/Ri) Min.{(1 + b)2 RL/Ri}
8.10 Why is CE Widely Used ?

Table 8.3 reveals that the CE configuration is the best for general-purpose amplification of current,
voltage and power. The general topology of voltage amplifier is shown in Fig. 8.8(a). Figure 8.8(b)
shows the input and output sections of Fig. 8.8(a). The main utility of BJT lies in the amplification of
weak signals. In Fig. 8.8(a), vs is the signal voltage having its internal resistance rs. In a good amplifier
total generated signal vs should reach the input terminals of the amplifier as depicted in Fig. 8.8(a).
Figure 8.8(a) Voltage amplifier

! $
Figure 8.8(b) Equivalent circuit
vs Ri
From Fig. 8.8(b), vi = (8.10.1)
Ri + rs
In Eqn. 8.10.1, vi = vs only if Ri >> rs. It means that a good amplifier must have a very large input
resistance. Recall that a good voltage source works properly with its load resistance much greater than
the source resistance. Hence, input resistance of the amplifier works as the load.
Output side of the amplifier is equivalent to the voltage source vo = Avvi in series with its internal
resistance r o. The actual output voltage developed across the load is
Av vi RL
vo = (8.10.2)
RL + ro
It is clear from Eqn. 8.10.2 that the output voltage vo = Avvi only when ro << RL and the total output
voltage appears across the load resistance RL. Hence, a good amplifier should have large input resistance/
impedance and low output resistance/ impedance. For an ideal amplifier the input resistance should be as
high as possible and output resistance as low as possible. The high input resistance will not load the ac
source connected to the input port of the amplifier. The low output resistance matches the low load
resistance such as loud speaker and at the same time prevents it from getting damaged by excessive load
current drawn by the low load resistance connected across its output port. The CC configuration works
as a transformer that transforms very high input resistance to very low output resistance and vice-
versa. It can be named as an electronic transformer.
The practical aspect of loading phenomena can be explained by connecting a water or room heater or
any other heater for that matter to 230 V mains. As soon as the heater is put ON, glowing of bulb
becomes dim. The reason is, the heater drains a very large amount of current. Thus, 230 V mains is
loaded and its voltage goes down enormously only if RL << rs. It means that for a good amplifier, input
resistance should be as large as possible. A good voltage source works properly with its load resistance
much greater than the source resistance. Here, input resistance of the amplifier works as the load for the
input voltage source. Output side of the amplifier is equivalent to the voltage source vo = Avvi in series
with its internal resistance ro.
Similarly, if the load current drained through the output terminals of any amplifier is large (low load
resistance say a short circuit or 1 W), the amplifier will not be able to deliver the rated voltage and
power. Hence, for a good amplifier, CE amplifier section must be preceded and succeeded by a CC
stage for increasing the effective input resistance and decreasing the effective output resistance. Having
analyzed the three configurations of BJTs qualitatively, now the quantitative analysis will be taken up in
the subsequent articles. In order to know the advantages of one configuration of the BJT amplifier over
the others, precisely, the three configurations are analyzed separately in detail.
BJT Amplifiers
! %
8.11 Small Signal Model of BJT

When one of the three terminals of the BJT is made common to the other two terminals, the BJT can be
assumed as a two-port (4-terminal) network as depicted in Fig. 8.9. Out of the four variables V1, I1, V2,
and I2 in Fig. 8.9, any two can be assumed as independent variables, on which the other two variables
depend. Thus, selection of independent variables leads to various types of circuit parameters. Important
among them are:
∑ Impedance parameter (Z-parameters)
∑ Admittance parameters (Y-parameters)
∑ Hybrid parameters (h-parameters)
These four variables can generate six possible combinations taking any two of them together. However,
here we will discuss four combinations that we encounter more frequently.
Figure 8.9 BJT as two-port network
8.11.1 Z-parameters Model

Let us assume that I1 and I2 are independent variables, then V1 and V2 depend partially on I1 and partially
on I2. It is expressed as
V1 = f1(I1, I2) (8.11.1)
V2 = f2(I1, I2) (8.11.2)
Hence, any change in the value of V1 and V2 can be expressed by partial differential equation as
dV1 =
FG d V IJ DI
1
1 +
FG d V IJ DI
1
2 =
FG v IJ i + FG v IJ i
1
1
1
2 (8.11.3)
HdI K1 I2 = K
Hd I K
2 I1 = K
Hi K Hi K
1 2
dV2 =G
F d V IJ DI
2
1 +G
F d V IJ DI
2
2
Fv I Fv I
2
= G Ji +G Ji 1
2
2 (8.11.4)
HdI K1 I2 = K
HdI K 2 I1 = K
Hi K Hi K
1 2
LMv OP LMZ
1 11 Z O Li O
12 1
v1 = Z11i1 + Z12i2 PP MM PP
or, =M P = M (8.11.5)
v2 = Z12i1 + Z22 i2
MNv PQ MNZ
2 21 Z PQ MNi PQ
22 2
The equivalent circuit of Eqn. 8.11.5 is drawn as in Fig. 8.10.

! &
Figure 8.10 Two-generator Z-parameter model of BJT
Here Z11, Z12, Z21, and Z22 have dimension of impedance and hence are called Z-parameters.
Equation 8.11.5 is modified by adding and subtracting Z12i1 to develop a more practical circuit as
v 1 = Z11i1 - Z12i1 + Z12i2 + Z12i1 = ( Z11 - Z12 )i1 + Z12 (i1 + i2 ) (8.11.6)
Similarly, Eqn. 8.11.5 is modified by adding and subtracting Z12i1 and Z12i2 as
v 2 = Z21i1 - Z12 i1 + Z22 i2 - Z12 i2 + Z12 (i1 + i2 )
= ( Z21 - Z12 ) i1 + ( Z22 - Z12 )i2 + Z12 (i1 + i2 ) (8.11.7)
The equivalent circuit of Eqns. 8.11.6 and 8.11.7 is drawn as in Figs. 8.11 and 8.12 using voltage
source model. Figure 8.12 is the current source equivalent circuit of Eqns. 8.11.6 and 8.11.7.
Figure 8.11 One generator Z-parameter model of BJT
Figure 8.12 Current source Z-parameter model of BJT
8.11.2 Y-parameters Model

Assuming V1 and V2 as independent variables, I1 and I2 become dependent variables on V1 and V2. It is
expressed as
BJT Amplifiers
! '
I1 = f1(V1, V2) (8.11.8)

I2 = f2(V1, V2) (8.11.9)
Hence, dI1 =
FG d I IJ DV
1
1
FG d I IJ DV
+ 1 Fi I Fi I
= G Jv +G Jv
2
1
1
1
2 (8.11.10)
H dV K1 V2 = K
HdV K V = K H v K H v K
2
1
1 2
dI2 =G
F d I IJ DV
2
1 +G
F d I IJ DV = FG i IJ v + FG i IJ v
2
2
2
1
2
2 (8.11.11)
HdV K 1 V2 = K
HdV K 2 Hv K Hv K V1 = K 1 2
i1 = Y11v1 + Y12 v2 L i O LY
1 11 Y O Lv O
12 1
or, =M P = M (8.11.12)
i2 = Y12 v1 + Y22 v2 Ni Q NY
2 21 Y PQ MNv PQ
22 2
The equivalent circuit of Eqn. 8.11.12 is drawn as in Fig. 8.13.
Figure 8.13 Y-parameter model
8.11.3 h-parameter Model

Assuming I1 and V2 as independent variables, V1 and I2 become dependent vaviables on I1 and V2. They
can be expressed as
V1 = f1(I1, V2) (8.11.13)
I2 = f2(I1, V2) (8.11.14)
Hence, dV1 =
FG d V IJ DI
1 FG d V IJ DV
+ 1
FG v IJ i + FG v IJ v
= 1
1
1
2 (8.11.15)
1 2
HdI K 1 V2 = K
HdV K 2 I1 = K
H i K Hv K 1 2
dI2 =G
F dI IJ DI
2
+G
F dI IJ DV 2
Fi I F i I
= G Ji + G Jv 2
1
2
2 (8.11.16)
1 2
H dI K1 V2 = K
H dV K 2 I1 = K
H i K Hv K 1 2
v1 = hi i1 + hr v2 Lv O L h
1 11 h O Li O Lh
12 1 i h O Li O
r i
or, = M P =M = (8.11.17)
i2 = h f i1 + ho v2 N i Q Nh
2 21 h PQ MNv PQ MNh
22 2 f h PQ MNv PQ
o 2
!!
v1
Input resistance when output shorted = hi = h11 =
i1 V2 = 0
i2
Forward current ratio when output shorted = h f = h21 =
i1 V2 = 0
v1
Reverse voltage ratio = hr = h12 =
v2 I1 = 0
i2
Output admittance = ho = h22 =
v2 I1 = 0
Here, hi is the input resistance equal to the ratio of change in the input voltage to change in the input
current. Thus, dimensionally it is resistance. Similarly, ho is the output conductance and is equal to the
ratio of change in the output current to change in the output voltage. Its dimension is S (Siemens or
conductance). The hr is the ratio of change in the input voltage for the corresponding change in the
output voltage and it is called reverse voltage ratio (dimensionless). Similarly, hf is the ratio of change in
the output current for the corresponding change in the input current and defined as forward current
ratio (dimensionless). Thus, we see that four hybrid parameters hi, hf, hr, and ho have different dimensions
and hence, their name was derived as hybrid (mixed parameters).
Figure 8.14 Hybrid model of BJT
The hybrid equivalent circuit of BJT from Eqn. 8.11.17 is drawn as Fig. 8.14. The typical values of
hybrid parameters of any BJT in CE configuration are
hi = h11 = 1 KW, hr = h12 = 104, hf = h21 = 100, ho = h22 = 106 S.
We encounter certain difficulties if we try to measure Z-parameters of a BJT in the common base
configuration. In order to measure Z11, for an example, we may arrange the circuits as in Fig. 8.15.
v1
From the definition Z11 = (8.11.18)
i1 i2 = 0
Assuming that the BJT is properly biased, i2 = ie = 0 (ac collector current). The choke L1 in the input
loop offers very large impedance to ac emitter current ie = i1 and does not allow it to pass through the
BJT Amplifiers
!!
supply voltage VEE. Here, a question may arise about why a very large resistance equivalent to the
impedence offered by inductor L1 is not put in place of the inductor L1. If such a large value of passive
resistance is placed in place of the inductor L1, the dc voltage drop across it would be enormous which
practically prohibits the size of the regulated transistor power supply. If the ac impedance offered by the
choke L1 is much larger than the transistor input impedance, then no ac current will pass through the
inductor L1 and hence,
i R1 << ie (8.11.19)
Now we may fix up ie as
vi - v1
ie = (8.11.20)
rs
Figure 8.15 Circuit for hie and hfe
The ac voltage v1 may be easily measured with an ac voltmeter. The direct emitter current IE is
readily established at VEE/R1 by varying R1. The blocking capacitor C1 keeps the direct emitter current
out of the signal source vi and offers negligible impedance at the signal frequency. The problem arises
in trying to set the alternating collector current ic = i2 equal to zero.
We know that the output resistance of a common base transistor configuration is very high as the
base-collector junction remains reverse biased. The current ic appears to emanate from a high impedance
source which may approach up to 1 MW or higher. The value of collector choke L2 must be such that
its reactance is at least 10 times larger than the output resitance say, 100 MW or higher. In order to
obtain a low frequency equivalent circuit of the BJT, its Z-parameters should be measured at frequencies
even less than 30 Hz. For simplicity in calculation, let us assume that impedance offered by the inductor
L1 be 100 MW. The frequency of approximately 16Hz may result into the 100 MW impedance. This
means XL2 must offer at least 100 MW at frequency of 16 Hz. Hence, the required value of inductance
comes out to be
100 ¥ 106 = 2 p f L2 = 2 p ¥ 16 L2 (8.11.21)
100 ¥ 106 100 ¥ 10 6

or, L2 = = @ 106 H (8.11.22)
2 p ¥ 16 100.5
Practically such a large value is hard to achieve, especially if the inter-winding and inter-layer capacitance
is to be low to avoid undesirable resonance. We cannot use a 100 MW resistor instead of the inductor L2
!!
because the collector voltage supply requirement would then become excessively high due to large
voltage drop across this 100 MW resistance on account of the bias collector current. We may, however,
conclude that since i2 emanates from a high impedance source, setting ic = i2 = 0 becomes very difficult.
On the contrary setting v2 = vc = 0 across a high resistance source is easier.
The above statements direct towards measuring y-parameters based on the short circuit measurements.
In other words to set v2 = 0 is not problematic across output of a common base BJT. A very small value
of capacitor C1 offers short circuit across the output terminals of the common collector transistor. The
value of capacitor comes out to be
1 1
100 ¥ 106 = XC1 = =
wC1 2pfC1
1 1 1
C1 = = = @ 1010 F = 100 pF.
100 ¥ 10 6 ¥ 2pf 108 ¥ 2p ¥ 16 108 ¥ 100.5
Conclusion is that instead of Z-parameters, we can measure Y-parameters of any transistor. But
while measuring Y-parameters one may encounter a different problem if one tries to measure y22. The
y22 is defined as
i2
y22 = (8.11.23)
v2 v1 = 0
Equation 8.11.23 suggests that we must set v1 = 0, while applying v2 and measuring i2 as shown in
Fig. 8.16. Since XL2 and the output resistance of the transistor are quite large, v2 will essentially be equal
to vi. The choke L2 prevents the VCC supply from shorting vi. Now to set v1 equal to zero, the reactance
of C1 should be at least one tenth or preferably one hundredth of the input resistance presented by the
transistor when looking into its input terminals. The incremental emitter resistance may be less than
even fraction of an ohm for large values of IE.
Since the base resistance is of the order of (1 a)rb when looking into its input terminals, the net
input impedance that is essentially re + (1 a)rb, may be near an ohm.
Figure 8.16 Circuit for h22 and h12
Reactance XC1 must be at least as small as 0.1 W at low frequencies say at 16 Hz. Therefore, the
minimum required value of C1 should be
1 1
0.10 = = (8.11.24)
2pfC1 100.5 C1
BJT Amplifiers
!!!
1
C1 @ = 0.1 F = 100000 ¥ 106 F = 100,000 mF (8.11.25)
100 ¥ 0.1
Equation 8.11.25 yields a very awkward value of capacitance while for accuracy it should really be
ten-times this value, i.e. 1000,000 mF. Furthermore, it may be desirable to make measurements at 10 Hz
rather than 16 Hz that would demand much larger value of capacitor than calculated. Apparently neither
Z- nor Y-parameters exclusively can be measured quite conveniently. However, a combination of the
two works well and is known as hybrid parameters. Since we can not set i2 = 0 but can force v2 = 0
very easily, we shall let v2 be an independent variable. Likewise, it is easy to set i1 = 0, but not v1 = 0 and
hence i1 is assumed as another independent variable. Thus, I1 and V2 are assumed to be independent
variables for the analysis and measurement of h-parameters. The other two-variables I2 and V1 are
expressed as in Eqn. 8.11.17.
The four dynamic hybrid parameters of a transistor (BJT) at low frequencies are the input resistance
hi = h11, the forward current ratio hf = h21, the output conductance ho = h22, and the reverse voltage-
transmission ratio hr = h12. Since these parameters are known as small signal parameters, it is measured
at and around the small vicinity of the Q-point of the transistor. The existing method of measurement
uses two different circuits for all the four parameters to be measured. As common emitter configuration
is the most widely used amplifier configuration, the analysis and measurements made herein are for the
same configuration.
8.12 CE Amplifier
Figure 8.17(a) is the circuit of a common emitter amplifier (CE amplifier). Its ac circuit is drawn as in
Fig. 8.17(b). The h-parameter model of the amplifier is shown in Fig. 8.17(c) wherein the biasing
resistor RB has been assumed to be high enough w.r.t. the other circuit components.
Figure 8.17(a) CE amplifier (b) ac circuit of CE
The controlled current source hfeib in Fig. 8.17c feeds the two resistances 1/hoe and RL in parallel.
What part of current hfeib is flowing as iL?
i L = ic = - h fe ib
FG 1/ h IJ = - h i
oe fe b
(8.12.1)
H R + 1/ h K 1 + h R
L oe oe L
v be = hieib + hrevce (8.12.2)

- h fe ib RL
vce = vL = iLRL = (8.12.3)
1 + hoe RL
!!"
Figure 8.17(c) Equivalent circuit of CE amplifier
F h h R Ii fe re L
R| h + eh h - h h jR U|
ie ie oe fe re L
vbe = hie -
GH 1 + h R JK b = S| 1 + h R V| i b
oe L oe L
T W
=S
R h + Dh R UV i
ie e L
b (8.12.4)
T 1+ h R W oe L
Hence, input resistance of CE amplifier is expressed as
Ri(CE) =
vbe
= ie
RS
h + Dhe RL UV (8.12.5)
ib 1 + hoe RL
T W
vce
The output resistance is defined as Ro(CE) = (8.12.6)
ic is = 0
For is = 0, the circuit of Fig. 8.17(c) reduces to Fig. 8.17(d).

From Fig. 8.17(d), (rs RB + hie )ib + hrevce = 0 (8.12.7)
ic = hfeib + hoevce (8.12.8)
Substituting ib from Eqn. 8.12.7 in Eqn. 8.12.8 results in
ic = h fe
F-h v I +h
re ce
GH r + h JK oe vce (8.12.9)
s ie
Figure 8.17(d) Equivalent circuit of CE amplifier for is = 0

BJT Amplifiers
!!#
F
ic = hoe -
h fe hre Iv = F r h s oe + hie hoe - h fe hre I v = F r h + Dh I v s oe e (8.12.10)
GH rs + hie JK GH
ce
rs + hie JK GH r + h JK
ce
s ie
ce
vce rs + hie
Hence, Ro (CE ) = = (8.12.11)
ic rs hoe + Dhe
The signal losses in the external circuitry are also considered to obtain the overall voltage and current
gains including the source and load resistances as in Fig. 8.18.
vs i RB
is = , b = (8.12.12)
rs + RB Ri is RB + Ri
ib =
RS v s
UV RS R UV B
(8.12.13)
Tr + R
s B R W TR + R W
i B i
iL ib - h fe RB
Hence, A is = ¥ = ¥
ib is 1 + hoe RL RB + Ri
- h fe RB
@ (8.12.14)
RB + Ri
Figure 8.18 Current source converted to voltage source
From Fig. 8.18, v s = ( rs + RB Ri )is (8.12.15)
v o = vL = iLRL =
F -h Ii R fe
GH 1 + h R JK oe L
b L
=G
F - h IJ R RS v UV RS R UV
fe
L
s B
(8.12.16)
H 1 + h R K Tr + R R W T R + R W
oe L s B i B i
Avs =
v
=G
F - h R IJ RS 1 UV RS R UV
L fe L B
(8.12.17)
v H 1 + h R K Tr + R R W T R + R W
s oe L s B i B i
Hence, the power gain Ap = Avs ¥ Ais (8.12.18)

6
Practical values of hoe = 10 S and hence hoe @ 0. Then voltage current and power gains are simplified as
Avs =
vL
=
FG
- h fe RL IJ RS 1 UV RS R UV = h R B fe L
(8.12.19)
vs H
1 + hoe RL K Tr + R s B R W TR + R W r + R | | R
i B i s B i
!!$
iL h fe RB - h fe RB
Ais = = = (8.12.20)
is ( RB + Ri ) (1 + hoe RL ) RB + Ri
h 2fe RL RB
Aps =
(1 + hoe RL )2 (rs + RB Ri ) ( Ri + RB )
h2fe RL RB
= (8.12.21)
(rs + RB Ri ) ( RB + Ri )
8.13 CB Amplifier
Fig. 8.19(a) is the simplest circuit of common base (CB) amplifier. Its ac and equivalent circuits are
drawn in Figs. 8.19(b) and (c) respectively. It is evident from Fig. 8.19(c) that the current source hfe ib
finds two parallel paths for its closed loop. One path is through the load resistance RL and the other
through the conductance hoe . What proportion of hfeib flows as ic = iL?
d i FGH h + 1R/ h+ 1/ h IJK = 1 + ch h +i R hh

i L = h fe ib
ie L
oe
oe ie
fe b
L oe
F h
=G
IF i I = F
fe e 1 IF h I i fe
H 1 + ch + R hh K H 1 + h K H 1 + ch + R hh JK GH 1 + h JK
ie
J G L oe
J G fe ie L oe fe
e
Figure 8.19(a) CB amplifier Figure 8.19(b) ac circuit of CB
Figure 8.19(c) Equivalent circuit of CB amplifier

BJT Amplifiers
!!%
Ai =
iL i
= c =
1 F IF h I @ h fe fe
=a (8.13.1)
ie ie 1 + hie + RL hoeGH c h JK GH 1 + h JK 1 + h fe fe
Also, vec = vcb veb , thus, vce = veb vcb

v eb = hieib + hrevce = hieib + hre (veb vcb)
(1 hre)veb @ veb = hieib hrevcb (8.13.2)
and, v eb = vL = iLRL = icRL (8.13.3)
Now combining Eqn. 8.13.2 and 8.13.3 yields
veb = hieib vcbhre = hieib hreRLic
h fe hre RL ie hie ie h fe hre RL ie
= hie ib - = -
d1 + h i l1 + (h
fe ie + RL )hoe q 1 + h fe d im b
1 + h fe 1 + hie + RL hoe g r
LM h ie
h h R fe re L
OP
= -
MN1 + h d1 + h im1 + bh + R g h
fe fe ie L oe r PQ i
e (8.13.4)
veb v
Hence, input resistance = Ri = = eb
i1 ie
È h h fe hre RL ˘ h + hie (hie + RL ) hoe - h fe hre RL

= Í ie - ˙ = ie
Í1 + h fe
Î ( )
1 + h fe {1 + (hie + RL ) hoe } ˙˚ 1 + h fe 1 + (hie + RL ) hoe ( ){ }
=
b g d
hie 1 + hie hoe + hie hoe - h fe hre RL i =
hie (1 + hie hoe ) + Dhe RL
d1 + h fe i m1 + bh ie g r
+ R1 hoe (1 + h fe ) {1 + (hie + Rl ) hoe }
hie + Dhe RL hie + Dhe RL hie h 1
= @ = @ ie = (8.13.5)
d1 + h i l1 + (h
fe ie + R1 )hoe q (1 + h fe ) 1 + h fe h fe gm
The input resistance of the amplifier is very low, of the order of few ohms, typically 100 W.
A simplified circuit of Fig. 8.19(c) is drawn as in Fig. 8.19(d).
Figure 8.19(d) Simplified circuit of CB amplifier
Now, the effective input resistance, including the biasing resistance = RB Ri

!!&
vs
From Fig. 8.19(d), is =
rs + RB Ri
ie =
RB
is =
RB FG IJ F v s I (8.13.6)
RB + Ri RB + Ri H K GH r + R
s B R JK i
Since, RB >> Ri = 1/gm as gm is of the order of 10 milli mho, Eqn. 8.13.6 reduces to
ie = is (8.13.7)
Hence, overall current gain = Ai =

FG i IJ FG i IJ = F h I a1f = F h I = a
L e fe fe
(8.13.8)
H i K H i K GH 1 + h JK GH 1 + h JK
e s fe fe
Its output resistance Ro can be defined as

vcb
Ro = (8.13.9)
ic vs = 0
The circuit of Fig. 8.19(c) reduces to Fig. 8.19(e) for is = 0.
Figure 8.19(e) Circuit for output resistance of CB amplifier
1 1
Thus, vcb =
hoe
( )
1 + h fe ib + hieib + hrevce =
hoe
( )
1 + h fe ib + hieib hre (vcb + vbe )
1
vcb(1 + hre) =
hoe
( )
1 + h fe ib + hieib hrevbe
Ï 1 + h fe ¸
vcb = Ìhie + ˝ ib hre vbe
Ó hoe ˛Ô
vcb FG
= hie +
1 + h fe IJ F v I h =FG h
be
1 + h fe IJ h h (8.13.10)
ib H hoe K GH i JK H
b
re ie +
hoe K ie re
For is = 0, ib = ic. Hence, Eqn. 8.13.10 now reduces to

BJT Amplifiers
!!'
v cb 1 + h fe
= hie + - hie hre (8.13.11)
- ic hoe
v cb 1 + h fe 1 + h fe
Hence, its output resistance Ro = = hie (1 hre ) + @ hie + (8.13.12)
- ic hoe hoe
For typical value of h-paramter as hie = 1 KW, hre = 0, hoe = 106 S, hfe = 100, the output resistance
is = 1 K + 100 ¥ 106 = 100 MW (very high).
Figure 8.19(f) Simplified input circuit of CB amplifier
The circuit of Fig. 8.19(d) is simplified to Fig. 8.19(f) to obtain the over all voltage gain.
vs
is = (8.13.13)
rs + RB Ri
ie =
FG R IJ i
B
s =
Ê R
Á
B
ˆ
˜
vs
BHR +RK
i Ë RB + Ri ¯ rs + RB Ri
vs vs
= = (8.13.14)
rs + RB Ri rs + Ri
F i Ih e
v o = vL = iLRL = icRL = hfeibRL = GH 1 + h JK fe RL (8.13.15)
fe
h fe RL vs h fe RLvs
vL = =
d1 + h i br + R g
fe s i (1 + h fe )( rs + hie )
h fe RL v s h fe RL vs
= =
d1 + h iFGH r + 1 +h h IJK ie
(1 + h fe ) rs + hie
fe s
fe
vL h fe RL 100 ¥ 1K
Avs = = = = 50 (8.13.16)
vs (1 + h fe ) rs + hie 100 ¥ 10 + 1K
8.14 CC Amplifier
The common collector circuit is also called emitter follower. The circuit of CC amplifier, its ac and
equivalent circuits are depicted in Figs. 8.20(a), (b) and (c) respectively.
!"
Figure 8.20(a) CC amplifier Figure 8.20(b) ac circuit of CC amplifier
Figure 8.20(c) Equivalent circuit of CC amplifier
vec = vbe + vbc, vce = vbe vcb

or, vce = vcb + vbe (8.14.1)
From Fig. 8.20(c), vbc = hieib + hrevce + (1 + h fe ) ib

FG 1 RL
IJ
Hh oe K
FG 1
vbc = hieib + hre(vcb + vbe) + (1 + h fe ) ib RL
IJ
Hh oe K
vbc (1 + h ) = h i + h v + (1 + h ) i c1/ h R h
re ie b re be fe b oe L
vbc Fv I be
= h + h G J + (1 + h ) G
ie re
F 1 R IJ fe L
i
b Hi K b Hh K oe
ie re
F 1 R IJ
= h (1 + h ) + (1 + h ) G fe L (8.14.2)
Hh K oe
vbc
Its input resistance = Ri (CC ) =
ib
Ri = hie (1 + hre ) + (1 + h fe )
FG 1 RL
IJ
Hh oe K
= hie + (1 + h fe )
FG 1 R J
I L (8.14.3)
Hh
oe K
BJT Amplifiers
!"
If 1/hoe >> RL then Ri = hie + (1 + h fe ) RL = 1 K + 100 ¥ 1 K = 100 K (8.14.4)

1 + h fe
Also if1/hoe << RL , then Ri = hie + (very large) = 1 K + 100 ¥ 106 = 100 MW (8.14.5)
hoe
1
(1 + h fe )ib
hoe (1 + h fe )ib
From Fig. 8.20(c), iL = = = (1 + h fe ) ib (8.14.6)
1 1 + hoe RL
RL +
hoe
iL
Hence, current gain Ai = = (1 + h fe ) = 100 (8.14.7)
ib
vs
From Fig. 8.20(d), is = (8.14.8)
rs + RB Ri
ib =
F R I i = FG R IJ F v
B B s
I (8.14.9)
GH R + R JK H R + R K GH r + R
B i
s
B i s B R JK i
The overall current gain is now expressed as
Figure 8.20(d) Simplified circuit for CC amplifier
Ais =
FG i IJ = F i I F i I = d1 + h
L L b
i FGH R R+ R IJK B
(8.14.10)
H i K GH i JK GH i JK
s b s
fe
B i
Ê 5K ˆ Ê 5K ˆ
Ais = 100 Á ˜ = 100 Á @5
Ë 5 K + 102 K ¯ Ë 107 K ˜¯
i FGH 1 + Rh R IJK @ (1 + h
vo = v L = i L RL = 1 + h fe ib d L
oe L
fe ) ib RL
= (1 + h ) R G
F R IF v I B s
H R + R JK GH r + R || R JK
fe L
B i s B i
Avs =
v
L F R IF 1 I
= (1 + h ) R G B
(8.14.11)
vs H R + R JK GH r + R || R JK
fe L
B i s B i
Ê 5K ˆÊ 1 ˆ Ê 5K ˆ Ê 1 ˆ
= (1 + 100) 1 K Á @ 100 K Á @1
Ë 5 K + 102 K ˜ Á
¯Ë sr + 5 K ˜
¯ Ë 107 K ˜¯ ËÁ 5 K ¯˜
!"
Its output resistance Ro is expressed as
vec
Ro = (8.14.12)
ie is = 0
For is = 0, the circuit of Fig. 8.20(c) reduces to Fig. 8.20(e). Now from Fig. 8.20(e),
(rs RB + hie ) ib + hre vce + vec = 0 (8.14.13)
vec hre vec = (rs RB + hie ) ib (8.14.14)
Figure 8.20(e) Equivalent circuit of CC amplifier
(1 - hre )v ec = ( rs || RB + hie ) ib
Ê ie ˆ
v ec = ( rs || RB + hie ) Á ˜
Ë 1 + h fe ¯
v ec rs || RB + hie hie 1K
Hence, Ro = = @ = = 10 W(very low) (8.14.15)
ie 1 + h fe 1 + h fe 100
8.15 BJT Phase Splitter

Having analysed basic configurations (CB, CE, CC) of BJT amplifiers in detail, it becomes essential to
analyse other types of circuits. Fig. 8.21(a) is the BJT amplifier with an emitter resistance RE. Its small
signal equivalent circuit is drawn as shown in Fig. 8.21(b) assuming the reverse voltage ratio hrv2
negligible. Since, the voltage at collector is 180° out of phase w.r.t the voltage at the emitter, it is called
phase splitter circuit.
v b = hie ib + (1 + h fe ) ib RE = {hie + (1 + h fe ) RE }ib
vb
Hence, input resistance R¢i = = hie + (1 + h fe ) RE (8.15.1)
ib
From Fig. 8.21(c), the input resistance = Ri = RB || Ri¢ (8.15.2)
BJT Amplifiers
!"!
Figure 8.21(a) Phase splitter
Figure 8.21(b) Input cicuit
Figure 8.21(c) Equivalent circuit
RB {hie + (1 + h fe ) RE } RB {hie + (1 + h fe ) RE }
RB || Ri¢ = , rs + RB || Ri¢ = rs +
RB + hie + (1 + h fe ) RE RB + hie + (1 + h fe ) RE
( rs + RB ){hie + (1 + h fe ) RE} + rs RB {rs + hie + (1 + h fe ) RE }RB
= =
RB + hie + (1 + h fe ) RE RB + hie + (1 + h fe ) RE
{rs + hie + (1 + h fe ) RE}RB
v s = is(rs + RB||R¢i) = is (8.15.3)
RB + hie + (1 + h fe ) RE
RB RB
ib = is = is (8.15.4)
RB + Ri¢ d
RB + hie + 1 + h fe RE i
is =
(
RB + hie + 1 + h fe RE) ib (8.15.5)
RB
Now, combining Eqns. 8.15.3 and 8.15.5 yields
!""
vs =
LM{r + h + (1 + h )R }R OPL R
s ie fe E B B + hie + (1 + h fe ) RE OPi
MN R + h + (1 + h ) R PQMN
B ie fe E RB Qb
=
or + h + d1 + h i R tR i
s ie fe E B
b
RB
d
= rs + hie + 1 + h fe RE ib
o i t (8.15.6)
- h fe ib
hoe - h feib
iL = = (8.15.7)
1 1 + ( RE + RL ) hoe
+ RE + RL
hoe
- h fe ib RL
v o1 = i L RL = = -h fe ib RL (8.15.8)
1 + ( RE + RL ) hoe
vo2 = ie RE = (1 + h fe ) ib RE (8.15.9)
v o1 - h fe ib RL - h fe RL
Av1 = = =
vs
{
rs + hie + 1 + h fe RE ib e j }
rs + hie + 1 + h RE
fe { e j }
- 100 ¥ 1 K
= =1 (8.15.10)
10 + 1 K + 100 ¥ 1 K
Av2 =
vo 2
=
1 + h ib RE
fe e =
j h fe RE
vs rs + hie + 1 + h fe RE d i
{
rs + hie + 1 + h fe RE ib e j }
100 ¥ 1 K
= =1 (8.15.11)
10 + 1 K + 100 ¥ 1 K
For RL = RE, Eqns. 8.15.10 and 8.15.11 are equal in magnitude but 180° apart in phase and hence it is
called phase splitter.
Its output resistance is expressed as
v o1 v
Ro = = L (8.15.12)
io ic vs = 0
The small signal equivalent circuit of Fig. 8.21(b) is now drawn for obtaining the output resistance as
Fig. 8.21(c).
Now writing the loop equation as
1 1
vc = ic - h fe ib + {(rs RB + hie ) RE }ic (8.15.13)
hoe hoe
BJT Amplifiers
!"#
Now we have to find out the portion of io = ic which flow as ib in Fig. 8.21(d).
- ic RE
ib = (8.15.14)
RE + rs + hie
Figure 8.21(d) Circuit for Ro of phase splitter
Hence, combining Eqn. 8.15.13 and 8.15.14 yields
1 Ê h fe RE ˆ
vc =
hoe ÁË1 + R + r + h ˜¯ ic + {(rs | | RB + hie ) | | RE }ic (8.15.15)
E s ie
=
|RS 1 FG1 + h R IJ + (r + h ) R |UV ife E
s ie E c
|T h H R + r + h K
oe E s |W ie
=S
R| 1 F1 + h R I + (r + h )R U|V i fe E s ie E
T| h GH R + r + h JK r + h + R W|
oe E s ie s ie E
c
Ro =
v
c
=S
|R 1 FG1 + h R IJ + br + h g R fe E s ie E |UV (8.15.16)
c i |T h H R + r + h K r + h + R
oe E s ie s ie E |W
1 F R IJ FG h + r + h IJ
E fe
Ro = +G s ie
h
oe H r + h + R KH h
s ie K E oe
Ê 1K ˆ
= 106 + Á
Ë 10 + 1 K + 1 K ˜¯
100 ¥ 106 + 10 + 1 K ( ) (8.15.17)
As, rs + h ie << hfe /hoe, Eqn. 8.15.17 reduces to
Ro =
1
+
FG
RE IJ FG h IJ fe
hoe H KH h K
rs + hie + RE oe
1 F h R IJ = 1 FG h R IJ
fe E fe E
= G 1+ (8.15.19)
h H oe r +h + R K s h Hr +h + R K
ie E oe s ie E
!"$
Ê 100 ¥ 1 K ˆ
= 106 Á = 50 MW
Ë 10 + 1 K + 1 K ˜¯
8.16 Darlington Configuration

We have seen that input resistance of emitter follower and BJT phase splitter is high. Still higher input
resistance can be achieved using Darlington pair. This is a very popular interconnection of two Bipolar
Junction Transistors as a single unit, illustrated in Fig. 8.22(a). It is commercially available in the market
by the name of Darlington pair. Its main feature is that the two-BJT works as single transistor with its
current amplification ratio as the product of the current amplification ratios of the two-independent
BJTs. In other words, if b1 and b2 are current amplification ratios of the two BJTs (T1 and T2), then the
overall current amplification ratio in the form of Darlington connection is
b = b1 ¥ b2 (8.16.1)
Figure 8.22(a) Darlington pair
From Fig. 8.22(a) it is clear that

ic2 = b2ib2
ie1 = (1 + b1)ib1 @ b1ib1 = ib2
ic = ic1 + ic2 = b1ib1 + b2ib2 = b1ib1 + b1b2ib1 = b1(1 + b2)ib1 = b1b2ib1 (8.16.2)
ic
Hence, overall current amplification ratio is = = b 1b 2 =100 ¥ 100 = 10 4 (8.16.3)
ib1
VT VT VT VT (1 + h fe1 )
hie1 = = = = = hie 2 (1 + h fe1 )
I B1 I E1 /(1 + h fe1 ) I B2 /(1 + h fe1 ) I B2
VT V VT hie1
hie2 = = T = =
I B2 I E1 I B1 (1 + h fe1 ) 1 + h fe1
Following are the two equivalent circuits in terms of input currents of both transistors. A simple
circuit of Darlington amplifier is shown Fig. 8.22(b). The emitter current of transistor T1 is equal to the
base current of the transistor T2. The circuit of the Darlington configuration is shown in Fig. 8.22(c).
From the ac circuit of Darlington pair amplifier shown in Fig. 8.22(d), its small signal equivalent
circuit looks like the one drawn in Fig. 8.22(e).
BJT Amplifiers
!"%
From Fig. 8.22(e), ib2 = ie1 = (1 + h fe1 )ib1 (8.16.4)
Figure 8.22(b) Input resistance of Darlington pair
Figure 8.22(c) Darlington pair amplifier
Figure 8.22(d) ac circuit of Darlington pair amplifier
Writing loop equation in the input circuit

vi = hie1ib1 + hie 2ib2 + (1 + h fe 2 ) RE ib2
= hie1ib1 + hie 2ib2 + (1 + h fe 2 )(1 + h fe1 ) RE ib1 (8.16.5)
vi
Hence, its input resistance Ri = (8.16.6)
ib1
Ri = hie1 + (1 + h fe1 )hie 2 + (1 + h fe 2 )(1 + h fe1 ) RE
= 1 K + 100 K + 104 K @ 104 KW (8.16.7)

Now the circuit of Fig. 8.22(e) reduces to Fig. 8.22(f). The effective input resistance including the
bias resistance is
!"&
n
Ris = Ri RB = hie1 + (1 + h fe1 )hie 2 + (1 + h fe1 )(1 + h fe 2 ) RE s RB = 104 KW 10 K @ 10 KW (8.16.8)
The upper limit on the value of effective input resistance is limited to the value of RB. Hence, Darlington
configuration could not help much in enhancing the effective input resistance of the Darlington amplifier.
d i
v e = RE 1 + h fe 2 ib2 = RE (1 + h fe 2 )(1 + h fe1 ) ib1 (8.16.9)
v i = Ri ib1 = hie1 + (1 + h fe1 )hie 2 + (1 + h fe1 )(1 + h fe 2 ) RE ib1

n s (8.16.10)
ve RE (1 + h fe1 )(1 + h fe 2 )
= (8.16.11)
vi hie1 + {hie 2 + RE (1 + h fe 2 )}(1 + h fe1 )
vs Ris vs Ri RB vs Ri RB
vi = = =
rs + Ris rs ( Ri + RB ) + Ri RB rs ( Ri ) + Ri RB
vs RB v R
= = s B = vs (8.16.12)
rs + RB RB
Figure 8.22(e) Equivalent circuit of Darlington pair amplifier
Figure 8.22(f) Simplified equivalent circuit of Darlington pair amplifier
Now, voltage gain can be expressed as

ve v RE (1 + h fe1 )(1 + h fe 2 )
Av = = o =
vi vi hie1 + {hie 2 + RE (1 + h fe 2 )}(1 + h fe1 )
104 K
= =1 (8.16.13)
1 K + 100 K + 104 K
BJT Amplifiers
!"'
As hie2 << (1 + h fe 2 ) RE , Eqn. 8.16.13 reduces to
ve v RE (1 + h fe1 )(1 + h fe 2 )
Av = = o =
vi vi hie1 + {hie 2 + RE (1 + h fe 2 )}(1 + h fe1 )
RE (1 + h fe1 )(1 + h fe 2 )
=
{hie 2 + RE (1 + h fe 2 )}(1 + h fe1 )
RE (1 + h fe1 )(1 + h fe 2 )
= =1 (8.16.14)
RE (1 + h fe 2 )(1 + h fe1 )
The output resistance is defined as
vo
Ro = (8.16.15)
io is = 0 where is =
vs
rs
Thus, for obtaining the output resistance, the circuit of Fig. 8.22(e) now reduces to Fig. 8.22(g).
ve = hie 2 ib 2 + hie1ib1 + (rs RB )ib1
= hie 2 ib2 + {hie1 + (rs RB )}ib1 (8.16.16)
io = - (1 + h fe 2 ) ib2 , ib2 = ie1 = - (1 + h fe1 ) ib1 (8.16.17)
vo = - {hie 2 ib 2 + ( hie1 + rs RB ) ib1}
= - hie 2 ib2 - (hie1 + rs RB )

F i I
b2
GH 1 + h JK
fe1
R| hie1 + rs RB - io U|
S|
= hie 2 +
1 + h fe1 1 + h fe 2
V|
T W
Figure 8.22(g) Equivalent circuit of Darlington amplifier for Ro
vo =
R|F h I + h + r R
ie 2 ie1 s B
U|i (8.16.18)
S|GH 1 + h JK (1 + h )(1 + h )|
V o
T fe 2 fe1 fe 2 W
!#
v h hie1 + rs RB 1 K 1 K + 10
Hence, Ro = o = ie 2 + = + = 10 W (8.16.19)
io 1 + h fe 2 (1 + h fe1 )(1 + h fe 2 ) 100 104
d i d it
v c = v L = - h fe1ib1 + h fe 2ib 2 RL = - h fe1 + h fe 2 (1 + h fe1 RL ib1
o
vL RL{h fe1 + h fe 2 (1 + h fe1 )}
= - (8.16.20)
vi hie1 + hie 2 (1 + h fe1 ) + (1 + h fe1 ) (1 + h fe 2 ) RE
vL RL{h fe1 + h fe 2 (1 + h fe1 )} R

Av1 = =- = - L =1 (8.16.21)
vi (1 + h fe1 )(1 + h fe 2 ) RE RE
The effective input resistance Ris can be increased by introducing a resistance R3 between the input
(base point) and junction of the two-bias resistors R1 and R2. The effective base bias resistor after
introducing R3 in this manner = R3 + R1 | | R2. If the value of R3 is large, the effective base bias resistor
will become high and will not load the effective input resistance, but high value of R3 will drastically
reduce the dc base (bias) current. In order to restore the base bias current we will have to increase the
value of VCC to a very large value which costs too much and practically is impossible. A modification in
the common collector/ Darlington configuration is realized by connecting a very large value of capacitor
C between the junction of R1 and R2 and emitter point as in Fig. 8.23(a). This is known as Bootstrapped
amplifier.
8.17 Bootstrap Amplifier

The word bootstrap suggests that the strap is very big. Hence, an amplifier with bootstrap characteristics
has very high input resistance.
If we drag one end of the bootstrap, the same amount drags the other end.
The capacitor C• behaves as a short circuit at all frequencies of interest. This way the resistance R3
has been connected between the input and output of the emitter follower circuit in Fig. 8.23(a). Using
Millers theorem, the reflected value of R3 across input is expressed as
R3
Ri(eff) = (8.17.1)
1 - Av
Since, the voltage gain Av of an emitter follower approaches to unity, Ri(eff) becomes very high. For
instance, if Av = 0.995 and R3 = 10 K,
R3 10 K 10 K
Ri(eff) = = = = 2 MW
1 - Av 1 - 0.995 0.005
Thus, the loading effect of base bias resistor on the input resistance Ri is negligible.
The term bootstrap arises from the fact that if one end of the resistor R3 changes in voltage, the other
end changes through the same potential difference, as if R3 pulls itself up by its boots strap. Its ac and
eqivalent circuits have been drawn in Fig. 8.23(b) and (c) respectively.
BJT Amplifiers
!#
Figure 8.23(a) Bootstrap amplifier Figure 8.23(b) ac circuit of bootstrap amplifier
Figure 8.23(c) Equivalent circuit of bootstrap amplifier
vb - ve vb - ve
i i = i b + i3 = + (8.17.2)
hie R3
ve
Av = (8.17.3)
vb
ii = vb (1 - Av )
FG 1 +
1 IJ
v (1 - Av )
= b (8.17.4)
Hhie R3 Khie R3
vb h R
Hence, input resistance Ri = = ie 3 (8.17.5)
ii 1 - Av
It is known that Av of an emitter follower is unity, i.e. Av = 1, Eqn. 8.17.5 realizes very large input
resistance.
As d
i¢e = ie + i3 = 1 + h fe ib + i3 i
or, i¢e = (1 + h fe )
v b - ve vb - ve
+ = (1 + h fe )
1 RS
+
1
(vb - ve )
UV
hie R3 hie R3
T W
!#
or,
F I F
ve
= vb
1 + h fe 1 1 + h fe 1
ve
I
GH JK GH
RE || RB hie
+
R3
-
hie
+
R3 JK
or, G
F 1 + 1 + h + 1 IJ v = v F 1 + h + 1 I
fe fe
H R || R h R K
E B ie
GH h R JK 3
e b
ie 3
F 1 h + d1 + h iR I (1 + h )R + h
ie fe 3 fe 3 ie
GG R || R + h R JJ v = h R v e b
H E B K ie 3 ie 3
hie + (1 + h fe ) R3
ve hie R3
=
vb 1 hie + (1 + h fe ) R3
+
RE || RB hie R3
1
= (8.17.6)
hie R3
1+
( RE || RB ){hie + (1 + h fe ) R3}
ve 1 1
Av = = =
vb 1 + hie R3 hie
1+
( RE || RB )(1 + h fe ) R3 ( RE || RB )(1 + h fe )
( RE || RB )(1 + h fe ) ( RE || RB )(1 + h fe )
= = =1 (8.17.7)
hie + ( RE || RB )(1 + h fe ) ( RE || RB )(1 + h fe )
The denominator of Eqn. 8.17.7 has (1 + something). This something is negligible w.r.t. to 1. Hence,
voltage gain becomes unity, i.e. Av = 1.
vo
Its output resistance is defined as Ro = (8.17.8)
io vs = 0
The equivalent circuit of Fig. 8.23(c) is modified as Fig. 8.23(d) to obtain the output resistance. The
equivalent circuit in Fig. 8.23(d) is redrawn for convenience of the reader.
As, 1/hoe is very large, under this condition 1/hoe in circuit of Fig. 8.23 (d) is treated as open circuit.
vo
ib = - (8.17.9)
hie
BJT Amplifiers
!#!
Figure 8.23(d) Equivalent circuit of bootstrap amplifier
Writing nodal equation at the emitter point yields

vo
= h fe ib + io (8.17.10)
hie R3 RB
Substituting the value of ib from Eqn. 8.17.9 yields Eqn. 8.17.10 as
vo v F
= - o h fe + io
I (8.17.11)
hie R3 RB hie GH JK
F 1 h fe I
vo = io (8.17.12)
GH h
ie
+
R3 RB hie JK
io 1 1 h fe 1 h fe h fe
= = + = + @ = gm (8.17.13)
vo Ro hie R3 RB hie hie hie hie
Ro = 10 W (Very low)
1. The two-port Darlington impedance sistors (hie = 1 KW, hfe = 100, hre = hoe
booster of Fig. 8.24(a) uses identical tran- = 0). Calculate the z-parameters of the net-
work. Use relevant approximations.
Figure 8.24(a) Figure 8.24(b) Equivalent circuit

!#"
Solution: ib1 = i1 ,
From Fig. 8.24(b), v1 = {hie1 + (1 + h fe1 )hie2} i1 + v2
|RSh
ie1 + (1 + h fe1 )hie 2 |UV i v2
v1 = b1 + RE i2 Similarly, i2 = - (1 + h fe 2 )ib2 +
|T + (1 + h fe1 )(1 + h fe 2 ) R |W E
RE
ib1 = i1 , v2
= - (1 + h fe 2 ) (1 + h fe1 )i1 +
RE
v1 =
|RSh + (1 + h )h
ie1 fe1 ie 2 |UV i + R i
1 E 2 v1 vbe
|T + (1 + h )(1 + hfe1 fe2 ) R |W E hie =
i1
=
ib1
= hie1 + (1 + h fe1 )hie2
v2 = 0
= {(2 + h fe1 )hie + (1 + h fe )2 RE} i1 + RE i2
= hie1 (2 + h fe1 ) = 102 K
Similarly, v2 =
(1 + h fe1 )(1 + h fe 2 ) RE i1 + RE i2 v1 vbe
hre = = =1
v2 i1 = 0
vce i1 = 0
2
= (1 + h fe ) RE i1 + RE i2
i2 ic
Lh (2 + h ) + (1 + h
[Z] = M ie fe fe )
2
RE RE OP h fe =
i1
=
ib1
2 v2 = 0 v2 = 0
MN (1 + h ) R fe E RE PQ = - (1 + h fe 2 )(1 + h fe1 ) = 104
È102 K + 10201 K 1 K ˘
= Í i2 ic 1
Î 10201 K 1 K ˙˚ hoe = = = = 10 -3 S
v2 i1 = 0
vce i1 = 0
RE
È10303 K 1 K ˘ È10.303 M 1 K ˘ LM h + (1 + h )h 1 OP
= Í ˙ = Í ˙ ie1 fe1 ie2
Î10201 K 1 K ˚ Î10.201 M 1 K ˚ h = - (1 + h )(1 + h 1
MN fe1 fe2 ) PQ
2. Obtain the h-parameters of the network RE
shown in Fig. 8.24(a). Transistors T1 and T2
are identical. Use relevant approximations. LM(2 + h )h 1 OP
fe1 ie1
Given hie = 1 KW, hfe = 100, hre = hoe = 0. =
MN - (1 + h ) R1 PQ
fe1
2
Solution: E
From Fig. 8.24(b), È 102K 1 ˘

v1 = {hie1 + (1 + h fe1 )hie 2} ib1 + v2 = Í 3 -3 ˙
Î - 10.2 ¥ 10 10 ˚
3. Obtain the transconductance of the transistor shown in Fig. 8.25(a).
Figure 8.25(a) Figure 8.25(b) Equivalent circuit

BJT Amplifiers
!##
Solution: Solution:
vb = hieib vb = hie1ib1 + hie 2 (1 + h fe1 )ib1
ic = hfeib
Transconductance is defined as ic2 = h fe2 ib 2 = h fe 2 ie1 = h fe2 (1 + h fe1 )ib1
ic h fb ib h fe ib h fe h fb 2ic1 h fe 2 (1 + h fe1 )
= = = = = gm gm = =
v be vbe hie ib hie vbe1 hie1 + (1 + h fe1 )hie2
4. A Darlington stage is shown in Fig.
8.26(a). If the transconductance of T1 and h fe 2 (1 + h fe1 ) h fe 2
T2 are gm1 = ic1/vbe1 and gm2 = ic2/vbe1, the = = = gm2
overall transconductance gm = ic2/vbe is ap- (1 + h fe1 )hie 2 hie2
proximately equal to the transconductance
of the T2. 5. A cascode stage shown in Fig. 8.27(a). If
the transconductance of T1 and T2 are gm1
= ic1/vbe1 and gm2 = ic2/vbe2, show that the
overall transconductance gm = ic2/vbe1 is
approximately equal to the transconduct-
ance of the T1.
Figure 8.26(a)
Figure 8.27(a)

!#$
Solution: F6I 4 I
= 4 I1 + 4 I 2 - 10 + I2
ic2 = h fb 2ie 2 and hib2 =
hie 2 H 111
11 K
1 + h fe 2 -16 4
= I1 + I 2
vbe1 = hieib1 11 11
h fb2 ie2 h fb 2ic1 V2 4 V

ic 2 Z22 = = W and Z21 = 2
gm = = = I2 11 I1
vbe1 vbe1 vbe1 I1 = 0 I2 = 0
-16
h fb 2 h fe1ib1 h fb 2 h fe1 = W
= = 11
hie1ib1 hie1
7. What are values of admittance parameters
= gm1h fb 2 @ gm1 ( h fb1 @ 1) of two-port network in Fig. 8.28(b).
6. Obtain impedance parameters of the two- Solution:

port network shown in Fig. 8.28(a). From Fig. 8.28(b),
I1 =
F 1 + 1 IV - V = V - V 2 1 2
H 5 20K 20 4 20 1
V F1 1 V 3V
I2 =- +1
+ IV = - + 1 2
20 H 10 20 K
2
20 20
I1 1 I
Y11 = = S , Y12 = 1
V1 V2 = 0
4 V2 V1 = 0
Fig. 8.28(a)
1 I 3
=- S , Y22 = 2 = S,
20 V2 V1 = 0
20
I2 1
Y21 = = - S
V1 V2 = 0
20
Fig. 8.28(b) 8. An emitter follower with bo = 100 is biased
at IC = 0.25 mA. The voltage source con-
Solution:
nected at it input has its internal resistance
V1 = 6 I1 + 4 I 2 - 10V1 and of 2 KW. Find out the value of RE such that
11V1 = 6 I1 + 4 I 2 it produces the output resistance of 110 W.
Obtain the voltage and input resistance for
V1 6 V this value of output resistance.
Z11 = = W , Z12 = 1
I1 I2 = 0
11 I2 I1 = 0 Solution:
4 IC ( mA) 0.25
= W gm = = = 0.01 S,
11 25 25
100
V2 = 4 I1 + 4 I 2 - 10 V1 b = 100 = gmrp, rp = = 10 KW,
0.01
BJT Amplifiers
!#%
rs + rp 2 K + 10 K b o RL
ro = = = 118.8 W Voltage gain = -
1 + bo 101 rs + Ri
Desired effective output resistance 100 ¥ 5 K
= 110 W = RE | | 118.8 = - = 20.41
24.5 K
118.8 ¥ RE
= = 110 Output resistance at collector point = ro
118.8 + RE
118.8 RE = 118.8 ¥ 110 + 110RE =
1 FG
1+
h fe RE IJ
(118.8 110)RE, = 8.8RE = 13068 hoe H rs + hie + RE K
RE = 1.485 KW 1 Ê 100 ¥ 0.1 K ˆ
= Á 1+ ˜
Input resistance = Ri = hie + (1 + hfe)RE hoe Ë 2 K + 12.5 K + 0.1 K ¯
= 10 K + 101 ¥ 1.485 K = 10 K + 1
149.985 K = (1 + 0.685)
hoe
= 159.85 KW
If hoe = 1 mS, then ro = 10 6 (1 + 0.685)
(1 + b o ) RE
Voltage gain = = 1.685 MW
rs + Ri
Output resistance at emitter point = ro
101 ¥ 1.485 K
= = 0.93 rs + rp 2 K + 12.5 K
2 K + 159.85 K = = = 0.144 KW
1 + bo 101
9. The BJT in Fig. 8.29 has b = 100 and op-
erates at biasing current IC = 0.2 mA. The
value of source resistance is rs = 2 KW, RL
= 5 K, and RE = 0.1 KW. Obtain voltages at
the collector and emitter of the amplifier.
Also obtain input and output resistances at
the two output points.
I C ( mA) 0.2
gm = = = 12.5 KW Figure 8.29
25 25
bo 100 10. Obtain the voltage of the two state ampli-
rp = = = 8 mS,
gm 12.5 fier shown in Fig. 8.30 with bo = 100 and
Input resistance = Ri = hie + (1 + h fe ) RE operates at biasing current IC = 1 mA. The
passive components connected to the am-
= 12.5 + 101 ¥ 0.1 K = 22.5 KW plifier are rs = 0.6 KW, RC = 1.2 KW = RL.
(1 + b o ) RE I C ( mA) 1
Voltage gain = gm = = = 0.04 S,
rs + Ri 25 25
100 ¥ 0.1 K bo 100
= = 0.4 rp = = = 2.5 KW,
2 K + 22.5 K gm 0.04
Input resistance = Ri = hie = rp = 2.5 KW,
!#&
b o RC CE = 56 ¥ 106 = 56 mF
Voltage gain = Av1 = -
rs + rp
100 ¥ 1.2
= - = 38.7
0.6 + 2.5
b o RL
Voltage gain =AV2 = -
rs + Ri
100 ×1.2
= = 32.4
1.2 + 2.5
Over all voltage gain = AV1 ¥ AV2
= 38.7 ¥ 32.4 = 1253.9
Figure 8.31(a)
12. Calculate the value of the coupling capaci-

tor CB for the circuit shown in Fig. 8.31(b)
so that the lower cut-off for the amplifier
becomes fL = 20 HZ. Given rp = 2.5 K,
bo = 200.
Resistance seen by the coupling capacitor
CB = rs + RB {rp + (1 + h fe ) RE } = R
Figure 8.30 rp + (1 + h fe ) RE = 2.5 K + 201 ¥ 0.6 K
11. Determine the value of the bypass capaci-
= 123.1 K, 14.7 K 123.1 K @ 14.7 K
tor CE in Fig. 8.31(a) to get lower cut-off
frequency fL = 100 HZ assuming CB is ef- R = 0.3 K + 14.7 K = 15 K.
fectively short circuit at frequency of inter-
est. Given gm = 0.1 S, rbb¢ = 0.1 K, rp = 1
For cut-off frequency of fL=
0.5 K, RE = 0.3 K, rs = 1 K. 2p ¥ 20CB
b o = gm rp = 0.1 ¥ 0.5 K = 50, 1
= 15 K, CB = = 0.53 mF
The resistance appearing across 2p ¥ 20 ¥ 15 K
rs + rbb ' + rp 1 K + 0.1 + 0.5 K
RE = =
b +1 51
= 0.0314 K = 31.4 W
rs + rbb ' + rp 300 ¥ 31.4
R= RE =
b +1 331.4
= 28.42 W
1 1
wL = , CE =
RCE 2pf L R
1
= = 5.6 ¥ 105 Figure 8.31(b)
2p ¥ 100 ¥ 28.42
BJT Amplifiers
!#'
- h fe RL
Voltage gain = Avs =
(rs + RB Ri )(1 + hoe RL )
- 55 ¥ 2
= = -125
(0 + 0.8)(11
.)
Power gain = Avs ¥ Ais = Aps = 125 ¥
45.96 = 5745
14. What is the peak value of the output signal
vO for the peak value of the input signal =
10 mV in Fig. 8.33 when operating bias
Figure 8.32 current IC is 1 mA ? hfe = 100.
VT 25
13. What is the voltage gain, current gain and hie = = = 2.5 K,
IB IC / 100
power gain of the amplifier shown in Fig.
8.32 with transistor parameters as hie = 30 ¥ 20
RB = = 12 K
0.8 K, hfe= 55, hoe = 50 mS? 50
10 ¥ 100 12 ¥ 2.5 K
RB = = 9.1 K, RB hie = =2K
110 14.5
Ri @ hie = 0.8 KW vs RB hie vs 2K
vb = = = 5 mV,
h fe RB rs + RB hie ( 2 + 2 )K
Current gain Ais = -
( RB + Ri )(1 + hoe RL ) 5 mV
ib = = 2 mA,
- 55 ¥ 9.1 K 2.5 K
=
(9.1 + 0.8) K (1 + 50 ¥ 2 ¥ 10-3 ) R'L = RC RL =
10 ¥ 3 K
= 2.3 K
- 55 ¥ 9.1 13
= = - 45.96 vO = - bib R'L
9.9(11
.)
= - 100 ¥ 2 ¥ 10 -6 ¥ 2.3 ¥ 103 = 460 mV.
Figure 8.33
!$
15. Obtain voltage gain of the BJT amplifier = (38.25 + 1) Kib, = 39.25Kib
shown in Fig. 8.34 assuming hie = 1 K, h fe vb
= 50, her = hoe = 0, RB = 100 K, RE = 1 K Ri = = 39.25 K << 100 K.
ib
= rs, RL = 3 K.
Hence, vS = (rs + hie)ib +vO
3K
vO = ieRL¢ = (1 + 50)ib v s = (1 + 38.25 + 1)Kib
4
38.25 Kib
3K AVS = = 0.95
= 51 ¥ ib = 38.25Kib 40.25 Kib
4
vb = vO +hieib = 38.25Kib + 1Kib
Figure 8.34
16. Determine the voltage gain in the amplifier 2.59 ¥ 2000 K
circuit shown in Fig. 8.35 assuming VBE Ri = 2M hie = = 2.587 K,
2002.59
= 0.7 V, hfe= 100, her = hos = 0.
vR 2.587vs
vbe = s i = = 0.896vs,
20 0.7 rs Ri
+ 0.3 + 2.587
IB = = 9.65 mA, IC = 965 mA
2 MÙ vo v
AV = ¥ be =
25 vbe vs
hie = = 2.59 KW,
0.00965 - 100 ¥ 15Kib
¥ 0.896 =
vO = - bib RC = 100 ¥ 15Kib, vbe = hieib 2.587Kib
- 100 ¥ 15
¥ 0.896 = 519.5
2.587
Figure 8.35
BJT Amplifiers
!$
17. A BJT amplifier has an input resistance of

100 KW, output resistance of 1 KW, hfe=
200, and voltage gain = 1. What configura-
tion of the BJT has been used.
h fe hre
RiCE = hie -
1 + hoe RL
@ hie (small).
RiCC = hie + (1 + hfe)RL (large)
hie Figure 8.36
RiCB = = very small
1 + h fe 19. Assuming that the IBias is ideal and the BJT
has very large current amplification factor
AV(CE) =
FG - h R IJ FG 1 IJ = large,
fe L b, rbb¢ = 0, ro Æ •, determine the small
H1+ h R KH r + R K
oe L s i signal midband voltage gain, input and out-
(1 + h fe ) RL put reistances of the amplifier shown in
AV(CC) = = 1, Fig. 8.37.
rs + hie + (1 + h fe ) RL
The simplified circuit and its equivalent cir-
h fe RL cuit at midband are also drawn in Fig. 8.37.
AV(CB) = = large
hie + (1 + h fe )rs VT 0.026
hib = = = 0.052 K = 52 W
I EQ 0.5 mA
h 2fe RL rs
AP(CE) = = small, Ri = rs + hib = 50 + 52 = 102 W
(rs + hie )2
1
2
Æ•
(1 + h fe ) RL hoe
Ap(CC) = = large,
rs + hie + (1 + h fe ) RL ic ic i /i
hfb = = = c b
ie ic + ib 1 + ic / ib
h fe h fb RL
Ap( CB) = = very small b
hie + (1 + h fe )rs = = a, vo = hfbieRL ,
1+ b
Hence, it is the case of CC configuration.
- vs ¥ hib
18. Calculate the midband gain of the amplifier veb = hibib =
shown in Fig. 8.36 with b = 800. rs + hib
(1 + h fe ) RL vo veb
Av(CC) = Hence, Avs = ¥
rs + hie + (1 + h fe ) RL veb vs
- h fb ie RL - hib
800 ¥ 0.470 = ¥
= hibie rs + hib
rs + hie + 800 ¥ 0.470
376 h fb RL 1 ¥ 1000
= @1 = = = 9.8
rs + hie + 376 rs + hib 102
!$
Figure 8.37
20. The open circuit voltage and internal resis- Gain of the amplifier = Av
tance of the microphone are 15 mV(rms)
and 100 KW respectively. An amplifier in vo 4
= = = 800
Fig. 8.38 with input resistance of 50 KW is vi 50 ¥ 10 -3
used to amplify the microphone output so
as to deliver 2 W power to a resistive load
of 8 W load. Obtain the voltage gain of the
amplifier.
vs ¥ 50 150 mV ¥ 50
vi = = = 50 mV
150 150
vo2 Figure 8.38
= 2 W, vo(rms) = 4 V,
8
Questions for Practice plifier cannot be more than few hundred

ohm? Justify it.
1. Draw the small signal low frequency 4. Show that the voltage gain of the
model of a BJT in CE configuration. Using bootstrapped amplifier is essentially unity.
this configuration, derive expression for
the voltage gain of an emitter follower am-
plifier. Multiple Choice Questions
2. Derive an expression for the voltage gain
in the CE transistor amplifier in terms of h- 1. The relationship between input and output
parameters. voltage of a common emitter amplifier is
3. Why the value of R3 in bootstrapped am- (a) always unity
(b) always positive
BJT Amplifiers
!$!
(c) always negative 10. The typical value of h-parameters of a BJT

(d) less than unity are
2. The voltage gain of a common collector (a) hie = 1 KW, h fe = 100, hre = 10 ¥ 10- 4,
amplifier is
(a) always equal hoe = 10 ¥ 10-6 S
(b) always positive (b) hie = 10 KW, h fe = 100, hre =
(c) always negative
10 ¥10 4, hoe = 10 ¥ 10- 6 S
3. The voltage gain of a common base ampli-
fier is (c) hie = 1 KW, h fe = 100, hre = 10 ¥ 104,
(a) less than unity
hoe = 10 ¥ 10- 6 S
(b) always positive
(c) always negative (d) hie = 100 KW, h fe = 100, hre =
4. The output current in a Class-C amplifier 10 ¥ 10- 4 , hoe = 10 ¥ 10- 6 S
flows for 11. In an amplifier the output varies
(a) full cycle (a) linearly for any amount of input ampli-
(b) more than half cycle tude
(c) less than half cycle (b) linearly for restricted range of input
(d) half cycle amplitude
5. In Class-AB amplifier the output current (c) nonlinearly for any amount of input
flows for amplitude
(a) full cycle 12. The h-parameters of a BJT are called
(b) more than half cycle (a) small signal parameters
(c) less than half cycle (b) large signal parameters
(d) half cycle (c) T-parameters
6. In Class-A amplifier the output current (d) Z-parameter
flows for 13. The h-parameters of a BJT at high fre-
(a) full cycle quency
(b) more than half cycle (a) remains constant
(c) less than half cycle (b) varies with frequency
(d) half cycle (c) none of these
7. Voltage gain of CB amplifier configuration 14. The configuration that offers highest input
has phase shift of resistance is
(a) 180° (b) 90° (a) CE (b) CB
(c) 360° (d) 45° (c) CC
8. The h-parameters of a BJT are 15. The amplifier that offers highest input re-
(a) dependent on RL sistance and the lowest output resistance
(b) dependent on ICQ (a) CE (b) CB
(c) independent of ICQ (c) CC
(d) constant 16. The configuration that offers highest cur-
9. The dimension of all the four h-parameters rent amplification ratio but lowest voltage
of a BJT are amplification is
(a) the same (a) CE (b) CB
(b) different (c) CC
(c) none of these
!$"
17. The configuration that offers highest 25. The buffer stage can employ the configu-
power gain is ration
(a) CE (b) CB (a) CB (b) CE
(c) CC (c) CC
18. The important considerations in cascading 26. The stage which avoids loading the previ-
of different configurations of BJT ampli- ous stage is called buffer amplifier. What
fier is is the other name ?
(a) matching of impedances (a) CB (b) CE
(b) matching of current gain (c) CC
(c) matching of loads 27. The prime importance in designing a cir-
19. The most popular general purpose ampli- cuit is voltage amplification. Which con-
fier configuration is figuration is preferred for such case
(a) CC (b) CB (a) CB (b) CE
(c) CC (c) CC
20. The CE amplifier configuration is pre- 28. The gain-bandwidth of an amplifier is
ferred over others because it offers (a) always constant
(a) highest current gain, voltage, and power (b) always variable
gains (c) none of these
(b) medium current gain, voltage, and power 29. The gain of an amplifier reduces by a fac-
gains tor of 10, the bandwidth
(c) lowest current gain, voltage, and power (a) remains constant
gains (b) increased by the same factor
21. The input resistance of a CC configuration (c) decreased by the same factor
is 100 KW with its load of 1 KW, the hfe of (d) none of the above
the BJT is approximately 30. The upper 3dB frequency of n-identical
(a) 500 (b) 100 cascaded stages is
(c) 50
22. The configuration that behaves as a con- (a) e 21/n - 1 f2j
stant current source is
(a) CB
(c) CC
(b) CE (b) 1 (2 1/ n
)
1 f2
23. The two stage CC amplifier configuration (c) nf2

provides approximately 31. The upper 3dB frequency of a single stage
(a) unity voltage gain amplifier is 1 MHZ, how many identical
(b) 50 voltage gain stages will result in approximately 510 kHz
(c) none of these upper 3 dB frequency.
24. The input voltage connected across the in- (a) 2 (b) 3
put of a CC stage is 5–0°. Its output volt- (c) 4 (d) 10
age would be 32. The upper 3 dB frequency of a single stage
(a) 5–360 o (b) 5–180 o amplifier is 1MHz, what will be the 3 dB
frequency of ten identical cascaded stages
(c) 5–0 o (d) none of these
BJT Amplifiers
!$#
(a) 0.1 MHz (b) 100 kHz (b) very large input impedance
(c) 268 kHz (d) 168 kHz (c) very low input resistance
33. The effective bandwidth of indentically 38. The output impedance of the Darlington
cascaded stages pair amplifier is
(a) decreases (b) increases (a) very large (b) very low
(c) remains constant (c) none of the above
34. The bandwidth of an amplifier is approxi- 39. The current gain of a Darlington pair is
mately approximately
(a) proportional to its upper 3 dB fre- (a) b / (1 + b ) (b) b
quency
(c) b 2
(b) inversely proportional to its upper 3 dB
frequency 40. At half power frequencies, an amplifier
(c) product of its 3 dB frequencies voltage gain is lowered by
35. The rise time tr for a square wave input of (a) 6 dB (b) 3 dB
an amplifier is related to its 3 dB frequency (c) 2 dB (d) 0.5 dB
in case of square wave input as 41. Compared to a CB amplifier, the CE ampli-
(a) tr = 0.35/f2 fier has
(b) tr = 0.90/f2 (a) lower input resistance
(b) lower current amplification
(c) tr = 0.35 / f2 (c) higher output resistance
(d) tr = 1/ f2 (d) higher current amplification
36. The bootstrap amplifier is associated with 42. One of the effects of negative feedback in
(a) high input impedance amplifier is to
(b) low input impedance (a) increase the noise
(c) none of these (b) decrease the bandwidth
37. The Darlington pair is characterized with (c) increase the harmonic distortion
(a) very large output impedance (d) decrease the harmonic distortion

1. (c) 2. (a) 3. (b) 4. (c) 5. (b) 6. (a)
7. (c) 8. (b) 9. (b) 10. (c) 11. (b) 12. (a)
13. (c) 14. (c) 15. (c) 16. (c) 17. (a) 18. (a)
19. (c) 20. (b) 21. (b) 22. (a) 23. (b) 24. (c)
25. (c) 26. (c) 27. (a) 28. (a) 29. (b) 30. (a)
31. (b) 32. (c) 33. (a) 34. (a) 35. (a) 36. (a)
37. (b) 38. (b) 39. (c) 40. (b) 41. (d) 42. (d)
9
FET Amplifiers
9.1 Introduction
We know that the input resistance of the FET (more appropriately of MOSFET) is ideally infinite and the
output resistance rd is also very high. The calculation of its gain becomes very simple by assuming them
to open circuited w.r.t. the external components.
9.1.1 Small Signal Equivalent Circuit of FET

From Eqn. 6.6.20 it is clear that the drain current ID is function of two variables VGS and VDS described
as
ID = f(VDS,VGS) (9.1.1)
In other words, its value depends partially on both the voltages VGS and VDS. Hence, it can be
expressed by partial differential equation, i.e.
∂ ID ∂I D
dID = DVGS + DVDS (9.1.2)
∂ VGS VDS = K
∂VDS VGS = K
For small signal, DID = dID' then total change in the drain current DID can be expressed as
DI D DI D
DID = DVGS + DVDS (9.1.3)
DVGS VDS = K
DVDS VGS = K
The first term in the parenthesis of Eqn. 9.1.3 is the ratio of small change in the drain current DID to
the corresponding small change in the gate to source voltage DVGS. The small change in the drain
FET Amplifiers
367
current DID belongs to the output side of the FET and the corresponding small change in the gate to
source voltage DVGS belongs to its input side. These two variables have mutual relationship between
them with its dimension as conductance. Hence, it is called the mutual conductance. Similarly, the
second term in the parenthesis is the ratio of small change in the drain current DID to the corresponding
small change in the drain to source voltage DVDS. The small change in the drain current DID belongs to
the output side of the FET and the corresponding small change in the drain to source voltage DVDS also
belongs to the output side only. These two variables have a self relationship with its dimension as
conductance. Hence, it is called drain conductance gd. Now, Eqn. 9.1.3 can be expressed as
DID = gmDVGS + gd DVDS (9.1.4)
or, id = gmvgs + gd vds (9.1.5)
Typical values of FET paramters are rd = 50 KW and gm = 2 mS, m = 100.
Equation 9.1.5 reveals that the drain current consists of two components of currents gmvgs and gdvds.
Eqn. 9.1.5 represents the mathematical model of the FET that is now put in the form of the circuit model
as indicated in Fig. 9.1. The left side of Fig. 9.1 is called the current source circuit model of the FET
whereas the right side of Fig. 9.1 is the voltage source circuit model of the FET.
Figure 9.1 Current and voltage source model of the FET
9.2 Common Source (CS) Amplifier

Figure 9.2(a) shows the circuits of a fixed bias and a self-bias common source amplifier. The coupling
capacitors C1 and C2 provide the functions of isolating the amplifiers dc from the signal source as well
as the load. The bypass capacitor CS provides a low impedance path to ac signal so that the gain of the
amplifier does not get reduced due to the negative feedback provided by resistance RS. The common
source CS amplifier is topologically similar to the common emitter amplifier. The common source
amplifier is perhaps the most widely used FET amplifier configuration. The coupling and bypass capacitors
are replaced by short circuit for the small signal analysis of the amplifier. After these replacements, the
FET amplifier circuit is called the ac circuit of the amplifier.
Figure 9.2(a) Common source (CS) amplifier

368
Figure 9.2(b) is the ac circuit wherein the dc voltages have been short-circuited and coupling and
bypass capacitors have also been assumed to be short-circuited. Its small signal equivalent circuit is
drawn as in Fig. 9.2(c). From this figure the output voltage is expressed as
vgs = v i (9.2.1)
vo = gmvgs(rd ||RD) = gmvi (rd ||RD) (9.2.2)
vo
Hence, voltage-gain = AV = = gm(rd ||RD) @ gmRD (rd>> RD) = 2 × 103 × 10 × 103 = 20
vi
gmrd RD mRD mR
=- =- = - D = gmRD (9.2.3)
rd + RD rd + RD rd
The negative sign in Eqn. 9.2.3 indicates 180° phase difference between the output and input voltages.
The voltage gain is very low as the value of gm(measure of gain) of the FET is very low w.r.t. the gm of
the BJT.
Figure 9.2(b) ac circuit of CS amplifier. Figure 9.2(c) Equivalent circuit of CS amplifier.
The input resistance is defined as

vi
Ri = = RG (9.2.4)
ii vo = 0
vo
Its output resistance = Ro= (9.2.5)
io vi = 0
With the condition vi = 0, the circuit of Fig. 9.2(c) reduces to
Figure 9.2(d) Output resistance of CS amplifier. Figure 9.2(e) Reduced circuit for Ro
Since the current source is zero, it is left open.

Hence, Ro = rd||RD @ RD = 10 KW (9.2.6)
FET Amplifiers
369
9.3 FET Phase Splitter

If the bypassed capacitor present across the source resistance rs is removed from Fig. 9.2(a), it yields
the circuit of a phase splitter as depicted in Fig. 9.3(a). Its ac and small signal equivalent circuits are
drawn in Figs. 9.3(b) and (c).
mvgs
id = (9.3.1)
rd + RD + Rs
mRsv gs
vgs = vi Rsid = vi - (9.3.2)
rd + RD + Rs
(rd + RD + Rs + Rs m )v gs {rd + RD + (1 + m ) Rs }vgs
or = = vi
rd + RD + Rs rd + RD + Rs
(rd + RD + Rs )vi
or vgs = (9.3.3)
rd + RD + (1 + m ) Rs
Figure 9.3(a) FET phase splitter Figure 9.3(b) ac circuit of FET phase splitter
Figure 9.3(c) Equivalent circuit of phase splitter Figure 9.3(d) FET phase splitter for Ro
- mvgs RD - mRD (rd + RD + Rs )vi

vo1 = RDid = = ¥
rd + RD + Rs rd + RD + RL rd + RD + (1 + m ) Rs
370
- mRD
= (9.3.4)
rd + RD + (1 + m ) Rs
vo1 - mRD -100 ¥ 10 K
Av1 = = =
vi rd + RD + (1 + m ) Rs 50 K + 10 K + 100 ¥ 10 K
-1000
= = 0.94 (9.3.5)
1060
mvgs Rs
vo2 = Rsid = (9.3.6)
rd + RD + Rs
Now substituting for vgs from Eqn. 9.3.3 in Eqn. 9.3.6 yields
vo2 =
F mRs IF rd + RD + Rs I vi
GH r
d + RD + Rs JK GH r
d
JK
+ RD + (1 + m ) Rs
mRs vi
= (9.3.7)
rd + RD + (1 + m ) Rs
vo 2 mRs 100 ¥ 10 K
Av2 = = =
vi rd + RD + (1 + m ) Rs 50 K + 10 K + 100 ¥ 10 K
1000
= = 0.94 (9.3.8)
1060
If Rs = RD, then |Av2| = |Av1|
Its output resistance is defined as
vo
Ro = (9.3.9)
io vi = 0
The circuit of Fig. 9.3(c) reduces to Fig. 9.3(d) with the condition vi = 0.
vgs = Rsid and so, vol = (rd + Rs)id m vgs
= (rd + Rs + mRs)id = {rd + (1 + m)Rs}id (9.3.10)
vo1 vo1
Ro = = = rd + (m + 1) Rs = 50 K + 100 ¥ 10 K = 1050 KW (9.3.11)
io id
9.4 Common Drain Amplifier

The common drain (CD) amplifier is topologically similar to the common collector amplifier and is more
popularly known as source follower. It functions similar to the emitter follower. The simplest circuit of
a common drain amplifier including biasing voltages is shown in Fig. 9.4(a). Figure 9.4(b) is its ac
circuit and Figs. 9.4(c) and (d) are equivalent circuits of common drain amplifier.
FET Amplifiers
371
Figure 9.4(a) Self biased CD amplifier Figure 9.4(b) ac circuit of CD amplifier
Figure 9.4(c) Equivalent circuit of CD amplifier. Figure 9.4(d) Simplified circuit of CD amplifier.
vgs = vi vo (9.4.1)
vo = gmvgs(rd ||Rs) (9.4.2)
Combining Eqs. 9.4.1 and 9.4.2 yields
vo = gm(rd ||Rs)(vi vo) (9.4.3)
vo {1 + gm(rd||Rs)} = gm(rd ||Rs)vi
gm (rd || Rs ) mRs 100 ¥ 10 K
Hence, voltage-gain = Av = = = = 0.95 (9.4.4)
1 + gm (rd || Rs ) rd + (1 + m ) Rs 50 K + 100 ¥ 10 K
Input resistance = Ri = RG (9.4.5)
vo
Its output resistance is defined as Ro = (9.4.6)
io vi = 0
The simplified equivalent circuit of Fig. 9.4(d) now reduces to Fig. 9.4(e) for deriving the output
resistance.
Hence, current source gmvo in Fig. 9.4(f) can be replaced by a resistance of the value
vo 1
= (9.4.7)
gm v o gm
Figure 9.4 (e), (f), (g) Equivalent, simplified and reduced circuit of CD amplifier for Ro
372
Now the circuit of Fig. 9.4(f) is simplified as Fig. 9.4(g).
Hence, its output resistance = Ro =

FG 1 ||r || R IJ
d s (9.4.8)
Hgm K
1
rd Rs
gm rd Rs 50 K ¥ 10 K
= = = = 476 W (Low) (9.4.9)
1 rd + (1 + m ) Rs 50 K + 100 ¥ 10 K
(rd + Rs ) + rd Rs
gm
9.5 Common Gate Amplifier

The Common Gate (CG) amplifier is topologically analogous to the common base amplifier. The com-
mon gate amplifier shown in Fig. 9.5(a) is commonly used at high frequencies. Fig. 9.5(c) is the
equivalent circuit of the common gate amplifier.
Figure 9.5(a) Common gate amplifier. Figure 9.5(b) ac circuit of CG amplifier.
Figure 9.5(c) Equivalent circuit of CG amplifier for Ri and Ro.
Its input resistance Ri can be obtained as

vsg = mvgs (rd + RL) id = m(vsg) (rd + RL) id (9.5.1)
(1 + m)vsg = (rd + RL)id (9.5.2)
vsg rd + RL 50 K + 10 K
Ri = = = = 600 W (9.5.3)
id 1+ m 100
The right side circuit of Fig. 9.5(c) is simplified to obtain its output resistance.
vo = (rd + rs)io mvgs = (rd + rs)io + mvsg (9.5.4)
vsg = rsio (9.5.5)
FET Amplifiers
373
vo = (rd + rs)io + mrsio = {rd + (1 + m)rs}io (9.5.6)

vo
Hence, Ro = = rd + (1 + m)rs = 50 K + 100 × 10 = 51 KW (9.5.7)
io
From Fig. 9.5(c) vi = (rs + rd + RL)id + mvgs (9.5.8)
vgs = vsg = vi rsid (9.5.9)
Now, combining Eqs. 9.5.8 and 9.5.9 yields
(1 + m)vi = {rd + Rs + rs(1 + m)}id (9.5.10)
(1 + m )vi
id = (9.5.11)
rd + RL + (1 + m )rs
(1 + m ) RL vi
vo = RLid = (9.5.12)
rd + RL + (1 + m )rs
(1 + m ) RL 100 ¥ 10 K 1000
Thus, voltage-gain = Av = = = = 16.4 (9.5.13)
rd + RL + (1 + m )rs 50 K + 10 K + 100 ¥ 10 61
9.6 High Frequency Model

We know that the FET also exhibits inter-electrode capacitances due to presence of p-n junction and
the channel that limits the frequency response of the FET amplifiers at high frequencies. The inter-
electrode capacitances in CS configuration are shown in Fig. 9.6(a). The typical values of these inter-
electrode capacitors in CS are
Cgs = 8 pF, Cgd = 2 pF, Cds = 0.1 pF (9.6.1)
The interelectrode capacitor between gate and the source Cgd functions as the feedback element from
output to the input in Fig. 9.6(a) at high frequency. This capacitor can be replaced by its equivalent
values across its input and output terminals using Millers theorem. The feedback impedance Z connected
in Fig. 9.6(b) can be reflected across the input and output terminals as in Fig. 9.6(c).
Figure 9.6(a) CS configuration at high frequency
Hence, the high frequency equivalent circuit of FET and MOSFET can now be drawn as in Fig. 9.6(b)
in CS configuration. As Cds is very small w.r.t. other interelectrode capacitors Cgd and Cgs, Fig. 9.6(c)
does not include Cds in its equivalent circuit.
374
Figure 9.6(b) and (c) Equivalent circuit of FET at H.F.
9.6.1 Miller Theorem

The Miller theorem states that the impedance present between output and input of any active device can
be broken into two parts: one part across the input terminals and the other part across the output
terminals of the active device as shown in Fig. 9.7(a).
vi - vo
i= , and vo = Avi (9.6.2)
Z
i=
vi - Avi
=
a
1 - A vi f (9.6.3)
Z Z
Z
Zin = vi = (9.6.4)
i 1- A
Figure 9.7(a) Amplifier with feedback impedance and its Miller equivalent
v o / A - vo (1 - A)vo
Similarly, i= = (9.6.5)
Z AZ
v AZ
Zo = o = @ Z (as A >> 1) (9.6.6)
-i A - 1
From Fig. 9.7(c) with above assumptions
1
Z= (9.6.7)
jw Cgd
Hence, feedback impedance reflected across its input terminals is
FET Amplifiers
375
1
Zi = (9.6.8)
jw Cgd (1 - A)
Thus, value of capacitance reflected across input terminal is
CM = (1 A)Cgd = {1 + gm(rd| |RD)}Cgd (9.6.9)
where, gm(rd ||RD) = Av = Mid-band gain of the amplifier
Similarly, the impedance reflected across the output terminals due to the presence of Cgd is
vo AZ 1
Zo = = @Z= (9.6.10)
-i A -1 jwCgd
Thus, total input capacitances of theFET = Ci = Cgs + (1 A)Cgd (9.6.11)

Hence, Cgd splits into two portions and works for two types of time constants as indicated in
Fig. 9.7 (b). Since the total input capacitance is much larger than the output capacitance, the effect of
Cgd on the output side is neglected.
Figure 9.7(b) Simplified equivalent circuit of FET using Miller's Theorem
9.6.2 Unity Gain Frequency of FET

The transist frequency fT is the frequency at which the gain of the common source FET goes down to
unity. It can be explained using Fig. 9.8.
Figure 9.8 Short circuit current gain of FET.
vgs (SCgd) = gmvgs isc

ii
vgs = S (C + C ) (9.6.12)
gs gd
376
ii
or isc = gmvgs vgs(SCgd) = (gm SCgd)
S (Cgs + Cgd )
isc gm - SCgd gm gm w
Hence, = = = = T (9.6.13)
ii S (Cgs + Cgd ) S (Cgs + Cgd ) jw (Cgs + Cgd ) jw
gm isc
At w = wT = , =1 (9.6.14)
dC gd + Cgs i ii
9.7 Frequency Response of CS Amplifier

The entire frequency spectrum is divided into three ranges. These ranges are specified as
∑ Low frequency range
∑ Mid frequency range and
∑ High frequency range
9.7.1 Mid Frequency Range

All coupling capacitors C1, C2 and bypass capacitor Cs in mid frequency range in Fig. 9.9(a) behave as
short circuits and inter-electrode capacitors Cgs, Cgd, and Cds behave as open circuits. Thus, only
resistive components are present as shown in Fig. 9.9(a) in mid frequency range. Fig. 9.9(b) is the
cascaded ac circuit of RC coupled amplifier at mid frequency. Its equivalent circuit at mid frequency is
drawn as in Fig. 9.9(c). The voltage gain of one stage of the FET amplifier at mid frequency is expressed
as
Av(M.F)= gm(rd| |RL| |RG)vgs (9.7.1)
Figure 9.9(a) Cascaded RC coupled FET amplifiers.
Figure 9.9(b) Cascaded RC coupled FET amplifiers at MF

FET Amplifiers
377
Figure 9.9(c) Equivalent circuit of RC coupled FET amplifiers at MF
9.7.2 High Frequency Range

All coupling and bypass capacitors of Fig. 9.10(a) at high frequency behave as short circuits as depicted
in Fig. 9.9(b). The interelectrode capacitors start playing their role at high frequency range. Fig. 9.10(b)
is the circuit valid at high frequencies wherein all inter-electrode capacitors have been taken into
considerations.
Req = rd ||RL||RG @ rd | |RL (9.7.2)
The small signal equivalent circuit of cascaded FET amplifier at high frequency is drawn in Fig. 9.10(b).
The simplified equivalent circuit is shown in Fig. 9.10(c).
- g mv gs (Req X C / j ) - g mv gs Req - g mv gs Req
vo = = = (9.7.3)
Req + X C / j 1 + Req / X C / j 1 + jReq / X C
1
where, Xc = (9.7.4)
w{Cgs + (1 - Av )Cgd + Cs + Cds}
Figure 9.10(a) Cascaded RC coupled FET amplifiers at HF.
Figure 9.10(b) Small signal equivalent circuit at HF.

378
Figure 9.10(c) Simplified small signal model at HF.
Figure 9.10(d) Plot of Av versus frequency
Hence, voltage gain at high frequency from Fig. 9.10(c) is expressed as

vo - gm Req A (M.F. )
Av(H.F.) = = = v (9.7.5)
vi 1 + jw CReq 1 + jw / w 2
1
where, w2 = (9.7.6)
CReq
The plot of Eqn. 9.7.5 is shown in Fig. 9.10(d).
9.7.3 Low Frequency Range

Let us assume that the bypass capacitor Cs in the low frequency range is infinitely large and the coupling
capacitors offer finite reactances. All inter-electrode capacitances at low frequency behave as open
circuits and do not play any role in its analysis. Thus, the small signal equivalent circuit of Fig. 9.9(a) is
drawn as Fig. 9.11(a). The inter-electrode capacitors behave as open circuited at low frequency.
Figure 9.11(a) Small signal equivalent circuit LF. Figure 9.11(b) Av versus w
FET Amplifiers
379
- gm vgs ( Req RG ) - gm vgs ( Req RG ) - gm R

vo = = = vgs (9.7.7)
1 w w
Req + RG + ( Req + RG )(1 - j 1 ) 1 - j 1
jw C2 w w
vgs =
RG vi
=
RG FG IJ F v I i
(9.7.8)
rs + RG + 1 / jw C1 rs + RG H K GH 1 - jw / w JK
11
vo
=
F
- gm R IF R G I F 1 I @ F -g R I F 1 m
I (9.7.9)
vi GH
1 - jw 1 / w JK GH r + R
s G
JK GH 1 - jw / w JK GH 1 - jw w JK GH 1 - jw
11 1/ 11 / w JK
1 1
where, w1 = , R = Req||RG, w11 =
( Req + RG )C2 (rs + RG )C1
The plot of Eqn. 9.7.9 is shown in Fig. 9.11(b).
9.7.4 Low Frequency Range When Xs π 0

Now let us assume that the two-coupling capacitors C1 and C2 are so large that they start behaving as
short circuit and the effect of bypass capacitor Cs will be analyzed here. The equivalent circuit looks like
the one shown in Fig. 9.12(a).
vgs = vg vs, and vs = Zsid (9.7.10)
Figure 9.12(a) Small signal equivalent circuit.
Now substituting vgs in the voltage source of Fig. 9.12(a) results in

(rd + RL + Zs)id = m(vi vs) = mvi mvs = mvi mZsid (9.7.11)
{rd + RL + (1 + m)Zs}id = mvi
RGvi
Since, vg = @ vi as RG >> rs (9.7.12)
RG + rS
- mvi RL - mRL (1 + jw Cs Rs )vi
vo = RLid = = (9.7.13)
rd + RL + (1 + m ) Zs rd + RL + (1 + m ) Rs + jw Cs (rd + RL ) Rs
Av(L.F.) =
vo
=
FG - mRL IJ F 1 + jw / w I
z
(9.7.14)
vi H
rd + RL + (1 + m ) Rs K GH 1 + jw / w JK
p
380
rd + RL + (1 + m ) Rs rd + m Rs 1 + g m Rs 1 + 2 mS ¥ 1 K
where, wp = = = = = 300 Hz (9.7.15)
Cs (rd + RL ) Rs Cs Rs rd Cs Rs 10 ¥ 10 -6 ¥ 1 K
1 1
wz = = = 100 Hz (9.7.16)
Rs Cs 10 ¥ 10-6 ¥ 1 K
Av(L.F.) =
vo - m RL Ê 1 + jw / w z ˆ 1 + jw / w z F I
= Á ˜ = Av(M.F.) GH JK (9.7.17)
vi rd + (1 + m ) Rs Ë 1 + jw / w p ¯ 1 + jw / w p
Av(L.F.) =
- mRL F
1 + jw / w z I = - g R F 1 + jw / w I
m L z
(9.7.18)
GH
rd (1 + gm Rs ) 1 + jw / w p JK 1 + g R GH 1 + jw / w JK
m s p
=
Av( M.F.) F 1 + jw / w I
z
(9.7.19)
1 + gm Rs GH 1 + jw / w JK
p
The plot of Eqn. 9.7.19 is shown in Fig. 9.12(b).
Figure 9.12(b) Plot of voltage gain versus frequency.
9.8 Frequency Response of CD Amplifier

Fig. 9.13 is the circuit of a Common Drain CD amplifier. The frequency response of the common drain
amplifier can also be broken into three-ranges.
Figure 9.13 Cascaded RC coupled CD amplifiers.

FET Amplifiers
381
9.8.1 Mid Frequency Range

All coupling capacitors C1 and C2 and bypass capacitor Cs at mid frequency behave as short circuits and
interelectrode capacitors Cgs, Cgd, and Cds behave as open circuits.
Hence, in mid frequency range only resistive components are present. Its equivalent circuit in mid
frequency range is drawn as in Fig. 9.14. The voltage gain in mid frequency region is expressed as
Av(M.F.).
Figure 9.14 Mid frequency equivalent circuit of CD amplifier.
Thus, voltage gain = Av(M.F.) = gm(rd||RL||RG) (9.8.1)

Since, RG >> RL and rd, Eqn. 9.8.1 reduces to
Av(M.F.) = gm(rd||RL) (9.8.2)
9.8.2 High Frequency Range

The coupling and bypass capacitors behave as short circuits as depicted in Fig. 9.15(a) at high frequencies.
As RG>> Rs and rd, it is left open and hence Fig. 9.15(a) reduces to Fig. 9.15(b).
Figure 9.15(a) High frequency circuit of cascaded CD FET amplifiers.
Figure 9.15(b) Small signal equivalent circuit of CD at H.F.

382
Figure 9.15(c) Simplified equivalent circuit of CD at H.F.
vs
i1 = (vg vs)SCgs = SCgsvgs, and i1 + gm vgs - (9.8.3)
rd || Rs / (1 + jw Crd || Rs )
rd || Rs
or, vs = (i1 + gm vgs ) (9.8.4)
1 + SC( rd || Rs )
Substituting for i1 from Eqn. 9.8.3 in Eqn. 9.8.4 yields
rd || Rs rd || Rs
vs = ( SCgs + gm )v gs = ( SCgs + gm )( vg - vs ) (9.8.5)
1 + SC( rd || Rs ) 1 + SC( rd || Rs )
1 + {S(C + Cgs ) + gm }(rd || Rs )

vs = (SCgs + gm )vg
FG r || R IJ
d s
(9.8.6)
1 + SC(rd || Rs ) H 1 + SC(r || R ) K
d s
vs ( gm + SCgs )(rd || Rs ) gm + SCgs

= = (9.8.7)
vg 1 + S (C + Cgs )(rd || Rs ) + g m (rd || Rs ) S (C + Cgs ) + g m
gm (1 + jw Cgs / gm ) gm (1 + jw / w z ) 1 + jw / w z
Av(H.F.) = = = (9.8.8)
gm {1 + jw ( C + Cgs ) / gm} gm (1 + jw / w p ) 1 + jw / w p
gm 2 mS g 2 mS
where, wp = = = 167 M rad/s, wz= m = = 250 M rad/s (9.8.9)
C + Cgs (2 + 2 + 8) pF Cgs 8 pF
The plot of voltage gain of Eqn. 9.8.8 is drawn in Fig. 9.16(a).
Its input resistance can be obtained from simplified circuit of Fig. 9.16(b) as
Figure 9.16(a) Voltage gain vs w. Figure 9.16(b) Circuit of CD at H.F for Ri.
FET Amplifiers
383
F
vs = 1 +
gm
i1
I F rd || Rs I (9.8.10)
GH SCgs JK GH
1 + SC(rd || Rs )
JK
vg = vs +
i1 F g
= G1 +
I F r || R I i + i
m d s 1
(9.8.11)
SCgs H SC JK GH 1 + SC(r || R ) JK SC
gs d s
1
gs
Zi =
vg 1 r || R
d s
F g I r || R m d s
(9.8.12)
1 + SC(r || R ) H SC JK 1 + SC(r || R )
= + +G
i1 SCgs d s gs d s
1 1 1
= + + (9.8.13)
SCgs SC + 1 SCgs w 2 CCgs
rd || Rs -
gm (rd || Rs ) gm
Equation 9.8.13 represents the input impedance which can be drawn as in Fig. 9.17(a).
Case I
For wCgs << gm and 1/w C << rd||Rs, capacitor C behaves as short circuit and the super capacitor
indicated by three plates behaves as open circuited. Under such conditions, the input impedance becomes
as shown in Fig. 9.17(b).
Figure 9.17(a) Input impedance Zi. Figure 9.17(b) Simplified circuit for Zi.
Cgs Cgd {1 + gm (rd || Rs )} + Cgs

Two capacitors = Cgd + = (9.8.14)
1 + gm (rd || Rs ) 1 + gm (rd || Rs )
Zi vi
Now, from Fig. 9.17(b), vg =
rs + Zi
1 + g m (rd || Rs )
S[Cgd {1 + gm (rd || Rs )} + Cgs ]
vg = vi (9.8.15)
1 + g m (rd || Rs )
rs +
S[Cgd {1 + gm (rd || Rs )} + Cgs ]
384
vg 1 + g m (rd || Rs )
= (9.8.16)
vi S[Cgd {1 + gm (rd || Rs )} + Cgs ]rs + {1 + gm (rd || Rs )}
If rs= 0(internal impedance of a voltage source), then Eqn. 9.8.16 yields

vg
=1 (9.8.17)
vi
Thus, overall voltage gain =

F v IF v I = F v I
s g s
(9.8.18)
GH v JK GH v JK GH v JK
g i i
1 + jw / w z
Av (H.F.) = (9.8.19)
1 + jw / w p
9.8.3 Low Frequency Range

Let us assume that for analysing the common drain amplifier at high frequency the bypass capacitor CS
is infinitely large and the coupling capacitors have finite reactances. Thus, the small signal equivalent
circuit of Fig. 9.16(a) reduces to Fig. 9.18(a). The inter-electrode capacitors behave as open circuited
at low frequency.
vo = gmvgs
F g R R SC I (v
Req RG m eq G 2
vs) (9.8.20)
R + R + 1 / SC
eq
GH ( R + R )SC + 1JK
G 2
=
eq G 2
g
vo
F R v IJ = FG SC R IJ v
=G G s 2 G
s
H R + 1/ SC K H SC R + 1K
G 2 2 G
Figure 9.18(a) Equivalent circuit at L.F. Figure 9.18(b) Plot of M.F. gain.
vs =
FG SC R + 1IJ v
2 G
o (9.8.21)
H SC R K 2 G

FET Amplifiers
385
vo =
F g R R SC I v - F g R R SC I F SC R + 1I v
m eq G 2 m eq G 2 2 G
GH ( R + R )SC + 1JK GH ( R + R )SC + 1JK GH SC R JK
eq G 2
g
eq G 2 2 G
o
v +G
F g R R SC I F SC R + 1I v = F g R R SC I v
m eq G 2 2 G m eq G 2
o
H ( R + R )SC + 1JK GH SC R JK GH ( R + R )SC + 1JK
eq G 2 2 G
o
eq G 2
g
( R + R )SC + 1 + g R ( SC R + 1)
eq G 2
F g R R SC I v
v =G
m eq 2 G m eq G 2
( R + R ) SC + 1
eq G H ( R + R )SC + 1JK
2
o
eq G 2
g
vo gm Req RG SC2
=
vg ( Req + RG )SC2 + 1 + gm Req + gm Req RG SC2
vo gm Req RG SC2
=
vg ( Req + RG + gm Req RG ) SC2 + 1 + gm Req
vo
=
F
gm Req RG I SC2
vg GH JK
1 + gm Req 1 + ( Req + RG + gm Req RG )SC2 / (1 + gm Req )
vo
=G
F gm Req I SC R 2 G
(9.8.22)
vg H 1 + gm Req JK 1 + jw / w 1
1 + gm Req
w1 =
( Req + RG + gm Req RG )C2
Plot of Eqn. 9.8.22 is shown in Fig. 9.18(b).
9.9 Common Gate Amplifier

Fig. 9.19(a) is the circuit of common gate amplifier. Topologically it is similar to common base ampli-
fier. The high frequency equivalent circuit model of the common gate amplifier is shown in Fig. 9.19(b).
Writing node equation at node S in Fig. 9.19(b).
vi - v s
+ gmvgs =
F
1
+ jw Cgs vs
I (9.9.1)
rs GH
RG JK
vi - v s 1 + jwCgs RG
or + gm(vg vs) = vs
rs RG
vi - v s 1 + jw Cgs RG
or + gm(0 vs) = vs
rs RG
386
Figure 9.19(a) Common gate amplifier.
Figure 9.19(b) H.F. model of common gate amplifier.
or
vi FG1
= gm + +
1
+ jw Cgs vs =
1
+ jw Cgs vs =
IJ F
1 + jw Cgs R
vs I FG IJ
rs Hrs RG R K H
R K H K
1 1 1 1 1 1 1 1
where rs || RG || = R, = + + = + =
gm R 10 W 10 MW 10 W 10 W 10 W 5 W
vs R
= (9.9.2)
vi (1 + jw Cgs R)rs
- gm v gs RL¢ - gm ( vg - v s ) RL¢ - gm ( 0 - vs ) RL¢
vo = = = , RL¢ = RD || RL (9.9.3)
1 + jw Cgd RL¢ 1 + jw Cgd RL¢ 1 + jw Cgd RL¢
vo gm RL¢
= (9.9.4)
vs 1 + jw Cgd RL¢
Now, voltage gain = Av(C.G.) =

FG v IJ FG v IJ = FG v IJ
s o o
Hv K Hv K Hv K
i s i
R| R U| F g R ¢ I = R| R m L
U| F g R ¢ I
m L
=S
|T(1 + jw C R)r V|W GH 1 + jw C R ¢ JK S|T(1 + jw / w
gs s gd L gs s
V
)r |W GH 1 + jw / w JK
gd
(9.9.5)
1 1 1 1
where, wgd = = = 50 M rad/s, wgs = = = 25Grad/s (9.9.6)
Cgd RL¢ 4 pF ¥ 5 K Cgs R 8pF ¥ 5W
FET Amplifiers
387
The plot of voltage versus frequency of common gate amplifier is shown as in Fig. 9.20.
Figure 9.20 Plot of gain versus frequency.
9.9.1 GaAs Amplifiers

The GaAs technology offers amplifiers to be designed for bandwidth in the range of hundreds of
megahertz. The major problem of the MESFET amplifier is low output resistance in saturation. We
know that the current sources play important role in the design of integrated-circuit technology. It is
used as an active load as well as for biasing. The simplest method to implement a current source is to
connect the gate of the depletion mode MESFET to its source as shown in Fig. 9.21. For VDS > VGS
Vth, the MESFET operates in the saturation and Eqn. 6.13.4 is modified as
ID = b (Vth)2(1 + l VDS) = bVth2(1 + l VDS) (9.9.7)
Its output resistance, ro, from Eqn. 6.13.6 is
dVDS 1
ro = = (9.9.8)
dI D bVth2 l
Similarly, the JFET technology has
IDSS = bVth2 and l = 1/|VA| , then (9.9.9)
dVDS 1 VA
ro = = 2
= (9.9.10)
dI D bVth l I DSS
Figure 9.21 MESFET current source, equivalent circuit, connected to loads.

388
Since l for MESFET is relatively high (0.1 to 0.3/V), the output resistance of the current source
shown in Fig. 9.21 is low and hence for most applications the current-source realization becomes
inadequate. Fig. 9.21 with positive supply voltage (+VDD) is used to source the current to a load whose
voltage can be as high as +VDD |Vth |. Similarly, with negative supply voltage the current source in
Fig. 9.21 can sink the current from the load whose voltage can be as high as VSS |Vth |.
9.9.2 MOS Current Mirror

We know that the current mirrors play important role in the design of integrated-circuit technology. It is
used as an active load as well as for providing proportional and stable dc current for biasing various
transistors in the circuit. A simple MOS based current mirror (current source) circuit is shown in
Fig. 9.22. The current mirror of this figure has enhancement mode MOSFETs T1 and T2 with equal
threshold voltage Vth, but may be with different W/L ratios. The MOSFET T2 is operated in saturation
with its drain current = Io. The drain current of T1 (reference current) is written as
ID1 = IREF = K1(VGS Vth)2 (9.9.11)
Since the MOSFET T2 is connected in parallel the MOSFET T1, VGS2 = VGS1 = VGS, the drain current
of T2 is
K2 (W / L) 2
ID2 = IO = K2(VGS Vth)2 = I REF = I REF (9.9.12)
K1 (W / L)1
Figure 9.22 MOS current mirror circuit and its characteristic
Here K2 and K1 have been replaced by corresponding W/L ratios.

Equation (9.9.12) indicates that ID2 = IO can be some multiple of the reference current IREF, its value
depending upon the device geometry. Practically this value of drain equal to IO can be obtained only
when the drain voltage is equal to the VGS as indicated in characteristic part of Fig. 9.22. The variation
in the drain voltage will result into corresponding variation in the drain current IO of T2 due to its finite
output resistance ro.
The inaccuracy in current transfer ratio due to the finite b of the BJT is not present in the MOS
mirrors. Hence, the only parameter of interest in the MOS mirrors is the output resistance ro2. Figures
9.23 are the circuits of MOS current mirrors. In order to determine the output resistance of the cascoded
current mirror in Fig. 9.23, its ac and the corresponding equivalent circuits are drawn in Fig. 9.24. It is
known that the incremental resistance of each of the diode connected transistors T1 and T3 is approximately
FET Amplifiers
389
equal to 1/gm which is very small and hence ground in ac circuit is shifted to both gates of transistors T2
and T4. Transistor T2 is replaced by its output resistance ro2 in Fig. 9.24 and T4 by its complete equivalent
circuit.
Output resistance is obtained as
vo = (ro2 + ro4)io ro4gm4vgs4 (9.9.13)
vgs4 = vg4 vs4 = 0 vs4 = ro2io (9.9.14)
vo = (ro2 + ro4) io + ro4gm4vs4 = (ro2 + ro4) io + ro4gm4ro2io= (ro2 + ro4 + ro2r04gm4)io (9.9.15)
vo
Ro = = ro2 + ro4 + ro2r04gm4 = ro2(ro4gm4) (9.9.16)
io
It is clear from Eqn. 9.9.16 that cascoding transistor T2 with transistor T4 increases the output
resistance from ro2 to ro2(ro4gm4), i.e. by a factor ro4gm4. Similar results can be obtained from Wilson
circuit of Fig. 9.23(h). However, the Wilson circuit suffers from the disadvantage that the collector
voltages of T1 and T2 are not equal and hence, their currents will be unequal. This problem can be
circumvented by including diode-connected transistor T3 as in Fig. 9.23(i).
Figure 9.23 MOS current mirrors (f) Basic, (g) Cascode, (h) Wilson, (i) Modified Wilson current
Figure 9.24 ac and equivalent circuits of MOS cascoded current mirror

390
9.9.3 Active Load CMOS Amplifier

The circuit of active loaded CMOS difference amplifier is shown in Fig. 9.25. Transistors T1 and T2
form the differential amplifier and transistors T3 and T4 form the current mirror as active load. The dc
bias voltage at the output is normally set by the subsequent stage.
Figure 9.25 Active load CMOS difference amplifier.
Similar to the BJT difference amplifier, the signal current is

i = gm(vid /2) (9.9.17)
I
where gm = (9.9.18)
VGS - Vth
Output signal voltage = vo = 2i(ro2||ro4) (9.9.19)
VA
where, ro2 = ro4 = ro = (9.9.20)
I/2
vo 2i(ro2 || ro 4 ) i r V
Hence, the voltage gain = AV = = = (ro / 2) = gm o = gm A
vid vid vid / 2 2 2I / 2
VA I V VA
= gm = ¥ A = (9.9.21)
I VGS - Vth I VGS - Vth
In order to obtain higher gain further, a cascode differential stage along with cascode current mirror
may used. However, this will reduce the output voltage swing.
9.9.4 Cascode Current Source

The increase in the output resistance can be achieved using cascode configuration as in Fig. 9.26.
Output resistance of cascode connection from Eqn. 9.9.16 is
FET Amplifiers
391
ro = (gm2ro2)ro1 (9.9.22)
Eqn. 9.9.22 indicates that adding cascode transistor T2 raises the output resistance of the current
source by a factor of gm2ro2. The typical value of gm2ro2 for GaAs MESFET ranges from 10 to 40 which
is the intrinsic gain of transistor T2. In order to allow maximum swing in the output voltage of the
cascode current source, VBias should be the minimum to drive the transistor in saturation.
Figure 9.26 Cascode MESFET current source. Figure 9.27 Composite MESFET.
9.9.5 Other Cascode Configuration

It is known that very low output resistance of the MESFET puts serious limitation on the performance
of MESFET current source and MESFET amplifiers. The simplest method to alleviate this problem is by
using the composite MESFET in place of a single MESFET configuration shown in Fig. 9.27. This
circuit is unique and operates due to early-saturation phenomenon in these devices. As discussed in the
operation of the MESFET, VDS(sat) is lower than vGS Vt h.
In the composite MESFET circuit of Fig. 9.27, T2 is made much wider than T1. Since, the same
current flows through both devices T1 and T2, |vGS2| is much closer to |Vth| than |VGS1| and thus, |vGS2|
>> |vGS1|. Ignoring channel-length modulation (l = 0) and assuming W1 = 10 mm, W2 = 90 mm, ID1 = ID2 =
1 mA, assuming Vth = 1 V, b = 104A/V2, l = 0.1/V, Io = 1015 A, and n = 1.1, Fig. 9.27 results as VGS
= (2/3) V and VGS1 = 0 V. From this figure
or VDS1 = VGS1 VGS2 = 0 (2/3) = 2/3 (positive and less than VGS1 Vth)
Thus, in the absence of early saturation, T1 would be operating in the triode region. It has been found
that with early saturation effect, T1 can achieve saturation if T2 is 5 to 10 times wider.
The equivalent circuit of the composite MESFET transistors is shown in Fig. 9.27. The
transconductance gm is that of the transistor T1 whereas the equivalent output resistance is increased by
the intrinsic gain of T2, gm2ro2 that typically ranges from 10 to 40. This shows substantial increase in the
output resistance and the reason of attraction of the composite MESFET.
A few examples of the composite MESFET are shown in Fig. 9.28. The leftmost circuit in this figure
is that of a current source with increased output resistance.
392
Figure 9.28 Composite MESFET current source, source follower, and gain stage.
The left side circuit in Fig. 9.28 is that of a source follower as T2 that causes the drain voltage T1 to
follow the voltage changes at the current-source terminal, resulting into bootstrapping T1 and increasing
the output resistance of the current source. This circuit is called self-bootstrapping current source. The
gain of the source follower is
vo ro( equ) gm 2 ro2 ro1
= = @1 (9.9.23)
vi ro(equ) + 1 / gm1 gm 2 ro2 ro1 + 1 / gm1
This indicates that the voltage gain of the composite MESFET as source follower is much close to
unity than obtained by single MESFET source follower.
The right most circuit of Fig. 9.28 is a gain stage using composite MESFET (T1 and T2) as driver and
T3 and T4 composite MESFET forming the current source load. The small signal voltage gain is
vo
= gm1Ro (9.9.24)
vi
where, Ro = output resistance = ro(equ)(T1,T2)|| ro(equ)(T3,T4) = gm2ro2ro1|| gm4ro4ro3 (9.9.25)
9.9.6 MESFET Difference Amplifier

Figure 9.2.9 is the difference amplifier using GaAs MESFET technology. Transistors T1 and T2 form
the differential pair. Transistor T3 forms the biasing current source and T4 active (current source) load.
The performance of the circuit is limited by the low output resistance of T3 and T4. The voltage gain is
vo
= gm2(ro2||ro4) (9.9.26)
vi
Using improved current source can increase the voltage gain. Figure 9.29 enhances the gain of the
MESFET differential pair. The drain of T2 has a current source load with a feedback from the output
FET Amplifiers
393
signal to the drain of T1 via the source follower T3. The current sources I and I/2 are assumed to be ideal
providing infinite output resistance and replaced by open circuits in its equivalent circuit.
Figure 9.29 MESFET difference amplifier and enhanced MESFET differential pair with
equivalent circuit.
In order to obtain the voltage gain of Fig. 9.29, the gate of T2 is grounded and the difference input is
applied at the gate of T1. Its equivalent circuit is drawm as Fig. 9.30.
Figure 9.30 Equivalent circuit.
vs vd1 = gm1vgsr01 = gm1(vi vs)r01 (9.9.27)

vo vs = gm2vgs2r02 = gm2(0 vs)r02 = gm2vsr02 (9.9.28)
Also,vd1 = gm3vgs3r03 = gm3(vo vd1)r03 (9.9.29)
Equation 9.9.29 yields
vd1(1 + gm3r03) = gm3r03vo (9.9.30)
From Eqn. 9.9.28, vo = (1 + gm2r02)vs (9.9.31)
394
Substituting Eqns. 9.9.28 and 9.9.29 in Eqn. 9.9.27 yields

vs vd1 = gm1vgs1r01 = gm1(vi vs)r01
vo g r v
- m 3 03 o = gm1r01 vi -
vo FG IJ
1 + gm 2 r02 1 + gm 3r03 H
1 + gm2 r02 K
or,
FG 1 -
gm3r03
+
gm1r01 IJ
vo = gm1r01(vi)
H1 + g r m 2 02 1 + gm3 r03 1 + gm2 r02 K
FG 1 + g m1r01
-
gm3r03 IJ
vo = gm1r01(vi) (9.9.32)
H1 + gm 2 r02 1 + gm3r03 K
For all transistor to be identically operating and of the same geometry yields as
vo 1 + gm1r01 gm3r03 1 + gm r0 gm r0
= gm1r01 / ( - ) = gm r0 / ( - )
vi 1 + gm 2 r02 1 + gm 3r03 1 + gm r0 1 + gm r0
gm r0
=
1 + gm r0 - gm r0
1 + gm r0
= (gmr0)(1 + gmr0) = (gmr0)2 (9.9.33)
Equation 9.9.33 indicates that the positive feedback through T3 enables Fig. 9.29 to provide gain
equal to the square of the gain available from single stage.
9.10 BiCMOS
Two types of silicon technologies are used for designing the integrated circuit amplifiers and other
circuits. These technologies are based on bipolar and CMOS. The BJT uses bipolar technology whereas
the CMOS uses p-MOS and n-MOS technology. The advantage of the BJT technology over the MOS
technology is that it can generate much higher transconductance gm for the same value of the bias
current resulting into much higher gain of the BJT amplifier than the corresponding MOSFET circuit.
Also the BJT amplifier has better higher frequency response than their MOS counterpart.
The infinite input resistance offered by the MOSFET makes it more suitable as extremely high input
resistance amplifier and almost zero input bias current. The MOSFET is excellent as a switch. The
V-I characteristic of the BJT exhibits an offset voltage of few tenths of volt. The V-I characteristic of
the MOSFET passes right through the origin resulting into zero offset voltage. The CMOS is the currently
used semiconductor technology widely used for the digital circuits.
Thus, each of the two technologies, bipolar and CMOS, has the distinct and unique advantage. An IC
technology that combines these two devices types, allowing each of the utilized in the circuit functions
for which it is best suited, is now emerging and is aptly named BiCMOS. This technology is useful in
design of both digital and analog chips that combine both analog and digital circuits.
FET Amplifiers
395
This technology is very useful in ASICs (Application Specific Integrated Circuits) where there are
diverging qualities of low power dissipation, high component packing density, high speed of operation
etc. The BiCMOS circuit exhibits little degradation in density. Because of low output impedance and
increased charging and discharging currents of BJTs, the propagation delay of the BiCMOS gates does
not increase much as in the case of CMOS gates. In terms of cost, power and density, the BiCMOS
technology can be compared with ECL.
Before discussing the BiCMOS amplifer, let us first examine the basic BJT and MOS amplifier stages.
Figure 9.31 is the active loaded basic BJT common-emitter amplifier. This circuit can be considered as
the half section of the difference amplifier as well. The controlled source is assumed to offer infinite
incremental resistance, the total resistance at the collector is the output resistance of the BJT ro and
hence, the voltage gain is
vo I V V
Av = = - gm ro = - C ¥ A = - A
vi VT IC VT
where, VA = early voltage and falls in the range of 200 V to 30 V.
This is the largest value of the gain attainable from a CE amplifier. The typical value of VA = 50 V, and
since VT = 0.025 V at room temperature, the intrinsic gain of the CE stage is approximately 2000. The
disadvantage is the input resistance, approximately, equal to rp of the BJT. The corresponding counter
part of the MOSFET amplifier is in Fig. 9.31. Its voltage gain is
vo
Av = = - 2 m n COX (W / L)I / l I = - 2 m nCOX (W / L) / l I
vi
where, l is the channel-length modulation factor l = 1/VA.
Figure 9.31 BiCMOS structure : BJT, MOS, BiCMOS cascode, BiCMOS double cascode
Here, the gain is inversely proportional to I . Figure 9.32 shows gain versus bias current plot.
396
Figure 9.32 Actively loaded gain of common-source amplifier versus bias current.
9.10.1 BiCMOS Inverter

The BiCMOS is very popular in VLSI (Very Large Scale Integration) technology. It integrates bipolar
and the CMOS circuits on the same chip. The bipolar includes the properties of high switching speed as
well as high driving capability. The CMOS adds to the low power dissipation, high input resistance and
wide range noise margins to it. This results in highly dense, high speed and low power dissipation digital
circuit. The main disadvantage of the BiCMOS is the complex integration process that increases the cost
per unit chip manufacturing.
Figure 9.33 is the BiCMOS inverter circuit. Transistors T1 and T2 form the CMOS inverter and T3
and T4 form the bipolar output stage along with resistors R1 and R2. This figure can be analysed under
different cases
Figure 9.33 BiCMOS inverter.
Case I
With V1 = 0 V, VGS1 = VG1 VS1 = 0 0 = 0Vand the n-channel transistor T1 do not form the channel
retaining it in cut-off. The VGS2 = VG2 VS2 = 0 VDD = VDD and the pMOS transistor T2 forms the
channel. As T1 is cut-off, no voltage drop exists across R1 and hence, transistor T4 is also cut-off.
If no load is connected to Vo, no current flows through T3 or R2 and T2. Since, T2 forms the channel,
no voltage drop occurs across the channel. Resistor R2 will allow the VDD to appear at the output
terminal. This is tshe reason, R2 is called pull-up resistor making VOH = VCC. In practical situation,
FET Amplifiers
397
however, this ideal condition does not exist. The output of the gate is required to source the current to
a load, for instance, to charge a load capacitance during low-to-high transition (tpLH), T3 turns ON
acting as an emitter follower providing a low output resistance and high current driving capability. This
is the way the load capacitance is charged quickly making the delay tpLH very short.
Case II
With VI = VDD (high), VGS1 = VG1 VS1 = VDD 0 = VDD the n-channel transistor T1 forms the channel.
The VGS2 = VG2 VS2 = VDD VDD = 0 V and the pMOS transistor T2 does not form the channel. As T1
is saturated, no voltage drop exists across it. Its drain current serves to remove the excess charge stored
in the base of T3 that turns off very quickly. The voltage drop across R1 drives transistor T4 ON. As the
load capacitance maintains the voltage high, the collector voltage of T4 is also maintained high. Since, T4
operates in the active region providing a large current to quickly discharge the load capacitor resulting
into short delay of tpLH. With the discharged load capacitance (assuming no dc load), the conducting
channel of T1 and R1 pull down the output terminal to zero, i.e. VOL = 0 V.
Now, again, if VI becomes low (VI = 0 V), T2 turns off, the base charge of T4 leaks out through R1
and the gate returns back to high output state. Thus, we see that the BiCMOS inverter has large output
voltage swing of CMOS and high current driving capability and short propagation delay of the BJT. The
gate dissipates almost zero power in both states, hence the BiCMOS has the best features of both
technologies.
With a fan-out of zero, the delay of a BiCMOS gate is typically 1ns which is larger than that of the
CMOS. But for a fan-out of 10(driving other gates), the propagation delay is still 1ns whereas in the
CMOS it becomes at least twice.
The logic function in the BiCMOS inverter circuit is performed by the CMOS inverter T1 and T2.
Figure 9.34 shows the circuit for a two-input NAND gate.
Figure 9.34 Two-input BiCMOS NAND gate.

Its operation is summarized as
∑ For A = 0 = B, VGS4 = VG4 VS4 = 0 0 = 0V, there is no formation of channel in T4 and hence
T4 is cut-off. VGS1 = VG1 VS1 = VGS2 = VG2 VS2 = 0 VDD = VDD, T1 and T3 form channels
and hence VO = A ¥ B = 0 ¥ 0 = VDD.
!'&
∑ For A/B = 0, T2/T4 is OFF, T1/T3 is ON, and hence VO = A ¥ B = 1 ¥ 0 = VDD.

∑ For A = B = 1 (VDD), T2 and T4 are ON, T5 is also ON, and hence VO = A ¥ B = 1 ¥ 1 = 0.
9.10.2 BiFET and BiMOS Circuits

We know that it is possible to fabricate JFETs/ MOSFETs and BJTs on the same chip. Hence, properties
of FETs and BJTs combine to yield better amplifier circuits. All BiFET(BiMOS) Op. Amps. employ
JFETs/ MOSFETs as input stages and the remaining stages use BJTs amplifiers. The first BiFET(BiMOS)
was commercially produced in 1980s. The FET differential stages have specific advantage over BJTs
w.r.t. higher input resistance, lower input bias current and hence decreased input offset currents, and
higher slew rate. The gate to source resistance of FET is much larger than that of the rp of the BJT to
account for the higher input resistance. The input resistance of the FET differential stage is approximately
four-times that of the corresponding BJT differential stage.
The input bias current of a JFET is the reverse bias current IGSS of the reverse biased gate to channel
junction. This current is very small w.r.t. reverse bias saturation current of the BJT. Since, IGSS is very
small, the offset current due to device mismatch is also smaller than those in the BJT circuits. The use
of MOSFET differential amplifier stages further decreases these quantities as the leakage current through
the gate oxide is much smaller than IGSS of the JFETs.
The gm of a FET is much smaller than that of a BJT for the same amount of drain and collector
currents. This affects the differential gain Adm of the FET amplifier. In order to overcome this limitation,
the BiFET( BiMOS) circuit uses three-stages Op. Amps. Ultimately, BiFET(BiMOS) are low noise
amplifiers w.r.t. BJT amplifier.
1. Obtain voltage gain, input and output resis-

tances of the bootstrapped source follower
circuit shown in Fig.9.35(a).
Figure 9.35(b) Equivalent circuit.

Solution:
Its equivalent circuit is drawn as in
Figure 9.35(a) Bootstrapped source Fig. 9.35(b).
follower.
FET Amplifiers
!''
vgs = vg vs = vg vo vi R3
Ri = =
Since R3 >> R2, R3 may be assumed as if ii 1 - o ¥ R2
v
open circuited w.r.t. the output loop cur- vi R1 + R2
rent. R3
=
vo = ( R1 + R2 )id m R2
1- ¥
mvi ( R1 + R2 ) mvo ( R1 + R2 ) 1 + m R1 + R2
= -
rd + R1 + R2 rd + R1 + R2 If R1<< R2 is substitued, then above equa-
tion reduces to
FG1 + m( R + R ) IJ v = FG m( R + R ) IJ v
1 2
o
1 2
i R3
H r + R + R K Hr + R + R K Ri =
d 1 2 d 1 2 m R
1- ¥ 2
1 + m R2
vo m ( R1 + R2 )
Av = = @ (1 + m)R3
vi rd + (1 + m )( R1 + R2 )
For output resistance, the circuit is simpli-
=
FG m IJ 1 fied as in Fig. 9.36(b).
H1 + mK 1 + rd
rd io = vo mvgs
(1 + m )( R1 + R2 )
= vo (mvo)
=
FG m IJ 1 = (1 + m)vo
H1 + mK 1 + rd
vo rd
m ( R1 + R2 ) Ro = = = gm
io 1+ m
=
FG m IJ 1
vi = 0
H1 + mK 1 + 1
gm ( R1 + R2 )
As {1 + gm(R1 + R2)} >> 1, Av now re-
duces to
Av =
FG m IJ RS g ( R + R ) UVm 1 2
H 1 + m K T1 + g ( R + R ) Wm 1 2
F m IJ
@G
H1 + mK Figure 9.36(a) Equivalent ckt for Ro.
Writing KVL equation in the input loop
yields
vi vx = R3i1 = v x -
F R2 I v
GH R2 + R1 JK o
|R F v I F R2 IJ |UV
= v S1 - G o J G
i
|T H vi K H R2 + R1 K |W Figure 9.36(b) Simplified equivalent circuit for Ro.
"
Hence, the circuit of Fig. 9.35(b) is simpli- 3. Prove that if i1 = i2, in the circuit of
fied as Fig. 9.36(a). 2 RL 1
Fig. 9.37(a) R = + .
For DC values vDD = vDS + ID (R1 + R2), m gm
and vGS = ID R1
2. Design a source follower circuit at Q-point
VDS = 14 V, IDQ = 3 mA, VDD = 20 V, gm =
2 mS, rd = 50 K, VGS = 1.5 V.
Solution:
The circuit of bootstrapped source fol-
lower may be considered for this example.
20 V = 14 V + 3 mA (R1 + R2)
R1 + R2 = 2 KW
Also 1.5 = 3 mAR1
R1 = 0.5 K, and R2 = 1.5 KW
Figure 9.37(a)
Now the output resistance
1 1
= Ro = = = 0.5 KW
gm 2 mS
Now from Fig. 9.36(b)
R1 + R2
(
vs = A¢v vg ) 1
R1 + R2 +
gm
(
= Av¢vg ) 2 K 2+ K0.5 K
vs
Av = = 0.8 A¢v
vg
The effective input resistance is expressed Figure 9.37(b) Equivalent circuit.
as Solution:
R3 vgs2 = vi and vgs1 = Ri1
Ri =
1-
F v IF R I
s 2 Writing KVL in the second loop of Fig.
GH v JK GH R + R JK
g 1 2
9.37(b) yields
mvgs1 + (rd + RL)i2 + RLi1 = 0
R3 R
= = 3 = 1.25R3 mRi1 + (rd + RL)i2 + RLi1 = 0
0.5 K 0.8
1 - 0.8 Av¢ ¥
2K
FET Amplifiers
"
(mR + RL)il + (rd + RL)i2 = 0 -2 RL m 2

=
For i1 = i2, (2 RL + rd )m + 2 RL + rd
(mR + RL) + (rd + RL) =0
-2 RL m 2
2 RL rd 2 RL 1 =
R= + = + (2 RL + rd )( m + 1)
m m m gm
m2 RL
2 RL 1 = ¥
4. Prove that if R = + and i1 = 1 + m RL + rd / 2
m gm
5. Prove that the output voltage vo in Fig.
mv2 {rd + (1 + m ) Rs } - m(rd + RD )v1 9.38(a) is expressed as
, the
(m + 2 )rd + (1 + m )2 Rs + RD
voltage gain of the circuit in Fig. 9.37(a) is mv2 {rd + (1 + m ) Rs } - m (rd + RD )v1
( m + 2 )rd + (1 + m ) 2 Rs + RD
m2 RL
given by ¥
1 + m RL + rd / 2 Its equivalent circuit is drawn as in
Fig. 9.38(b). From this figure
Solution:
vgs1 = v1 Rsi
Writing KVL in the first loop
(rd + R + RL)i1 + RLi2 = mvgs2 vgs2 = v2 vo
Similarly, writing KVL in the second loop (2rd + Rs + RD)i = mvgs2 + mvgs1
RLi1 + (rd + RL)i2 + mvgs1 = 0 = mv2 mvo + mv1 mRsi
Substituting i1 = i 2, yields {2rd +(1 + m)Rs + RD}i = mv1 + mv2 mv0
(rd + R + 2RL)i1 = mvi mv1 + mv2 - mvo
i= (a)
v2 v0 =
mvi 2 rd + (1 + m ) Rs + RD
2 RL + rd + R vo = (rd + Rs)i mvgs1
-2 RL mvi
vo = 2i1RL= = (rd + Rs)i mv1 +mRsi
2 RL + rd + R
= {rd + (1 + m)Rs}i mv1 (b)
2 RL 1
Substituting the condition R = +
m gm
in above equation yields
vo - 2 RL m
Av = =
vi 2 RL + rd + R
-2 RL m
=
2 RL 1
2 RL + rd + +
m gm
- 2 RL m 2
=
m Figure 9.38(a)
( 2 RL + rd ) m + 2 RL +
gm
"
mvi
i=
2 rd + (1 + m )( R1 + R2 )
Figure 9.38(b)
Combining Eqns. (a) and (b) yields
mvi + mv2 - mvo
vo =
2 rd + (1 + m ) Rs + RD
{rd + (1 + m)Rs} mv1
R|1 + m cr + a1 + mfh R
d S U| v =
Figure 9.39(a)
S| 2r + a1 + m f R + R V| o
vo = (R1 + rd + R2)i mvgs2
T d S D W = (R1 + rd + R2)i mvi + mR2i
mv1 + mv2
{rd + (1 + m)Rs} mv1
2 rd + (1 + m ) Rs + RD vo = {R1 + (1 + m) R2 + rd} i mvi
vo
RS(2 + m)r + (1 + m) R + R UV =
d
2
s D
m a
vo = R1 + 1 + m R2 + rd f r
T 2r + (1 + m )R + R W
d s D mv i
mv2 {rd + (1 + m ) Rs } - mv1 (rd + RD ) m2r + a1 + m fb R + R gr - mv
d 1 2
i
2 rd + (1 + m ) Rs + RD
Rr + (1 + m )R + R -
mv S
d 2 UV 1
mv2 {rd + (1 + m ) Rs} - mv1 (rd + RD ) i
vo =
(2 + m )rd + {(1 + m )2 Rs + RD} v0 = T 2r - (1 + m )( R + R )W
d 2 1
2 rd + (1 + m )( R2 + R1 )
6. Obtain voltage gain v0/vi in Fig. 9.39(a) - mv i ( rd + mR1 )
with both FETs having identical param- =
eters. Obtain output resistance also. 2 rd + (1 + m )( R2 + R1 )
For R1 = R2 = R,
Solution:
Its equivalent circuit is drawn as in Fig. - mvi ( rd + mR1 )
vo =
9.39(b). 2{rd + (1 + m ) R}
(2rd + R1 + R2) i = mvgs2 + mvgs1,
=
- mvi FGrd + mR
=
IJ
- mvi rd + mR FG IJ
vgs1= R1i and vgs2 = vi R2i 2 H
rd + (1 + m ) R 2 K
rd + mR H K
{2rd + (1 + m)(R1 + R2)}i = mvi vo m
Av = =-
vi 2
FET Amplifiers
"!
v i - vo vo
= gm vgs +
RF rd || RL
vo
vi = gmvgs RF + RF + vo
rd || RL
vgs = vg vs = vg 0 = vg = vi
vo
vi (1 RFgm) = RF + vo
rd || RL
vo (1 - RF gm )rd || RL
=
vi RF + rd || RL
m
If rd||RL = 3.3K, gm = = 6 mS
rd
Figure 9.39(b) then
7. Calculate the voltage gain for the circuit
shown in Fig. 9.40(a) vo (1 - 6 ´ 2)3.3 K 11 ´ 3.3
= =-
vi 5.3 K 5.3
= 6.85
8. Calculate voltage if the input voltage is con-
nected in series with the RG(40 K) as indi-
cated in Fig. 9.41(a)
Solution:
vi - v g vg - vo
=
Figure 9.40(a) RG RF
vi - v g vg - vo
=
RG RF
vo
= gm v gs +
rd || RL
Figure 9.40(b)
Its small signal equivalent circuit is drawn

as Fig. 9.40(b).
Solution:
From Fig. 9.40(b), Figure 9.41(a)
""
vo (1 - gm RF )(rd | | RL ) RF
=
vi ( RG + RF )( RF + rd | | RL )
- (1 - gm RF )( rd | | RL ) RG
From the above equation it is clear that
the voltage can be set to zero by adjusting
the value of RF = 1/gm. Thus, this circuit
suggests the best method of measurement
Figure 9.41(b) of gm using null technique.
9. In Fig. 9.42 if R3 = 1 M, R2 = 4 K, IDSS =
vgs = vg vs = vg 0 = vg 1 mA, VP = 1 V, VDD = 24 V, the quies-
v g - gm v gs RF = v g - gm vg RF cent drain-to-ground voltage is 10 V,
calculate the value of R1.
= RF
FG v IJ + vo
o
Solution:
H r || R K
d L
VDD = RD I DQ + VD
v (1 - R g ) = G
g F m
F R + r || R IJ v F d L
o
24 = 10 + 56KID
H r || R K d L
14 1
vo IDQ = = = 0.25 mA
(1 - gm RF )rd || RL 56 K 4 K
vg = RF + rd || RL
(a) 2
IDQ = I DSS
F1 - V I
GS
R
vi vg = G vg - vo
d i GH V JK
P
RF 2
æ VGS ö
0.25 mA = 1 mA ç 1 -
F R IJ v
v = G1 + G
-
FG R IJ v
G è -1 ÷ø
i g o
H RK F HR K F = 1 + VGS 1 mA
2
=G
F R + R IJ v
F G
g
FR I
- G Jv G
o (b)
1 + VGS = 0.5
H R K F HR K F VGS = 0.5 1 = 0.5 = IDQR1
Substituting vg from Eqn. (a) in Eqn. (b) 0.5
R1 = = 2 KW
yields 0.25
vi = vg
FG R + R IJ
F G
H R K F
æ RF + rd | |RL ö æ RG ö
çè (1 - g R )(r | |R ) ÷ø vo - çè R ÷ø vo
m F d L F
( RG + RF )( RF + rd | |R L ) Figure 9.42
- (1 - gm RF )( rd || RL ) RG
vi = vo 10. Calculate the quiescent values IDQ, VDS,
(1 - gm RF )(rd | | RL ) RF
and VGS in the region VDS ≥ VGS VPO for
FET Amplifiers
"#
VPO = 3 V of Fig. 9.42. The drain current 11. In the JFET circuit shown in Fig. 9.43(a)
of the enhancement type MOSFET is ex- assume that R1||R2 = 1 M and total stray
pressed as IDQ = 0.2 mA(VGS Vpo )2. capacitance at the output is 20 pF. Deter-
mine the under cut-off frequency of the
Solution:
amplifier. Given gm = 2 mS, Cgs = 20 pF,
1
VGS = (VDD - I DQ RD ) Cgd = 2 pF.
2
= 0.5(30 - 10 I DQ ) = 15 - 5 I DQ Solution:
IDQ = 0.2 mA(VGS Vpo) 2 Miller capacitance at input side = CM =

Cgd (1 + gm RL ) = 2(1 + 2 ¥ 2.5) = 12 pF
5IDQ = (VGS - VPO ) 2 = (15 - 5 I DQ - VPO ) 2
Miller capacitance on output side =
= (15 - 5 I DQ - 3) 2 = (12 - 5 I DQ ) 2 FG g R IJ C
m L
gd = Cgd = 2 pF
5IDQ = 144 - 120 I DQ + 2
25 I DQ H1 + g R K
m L
2
25IDQ 125IDQ + 144 = 0 Total input capacitance = Ci = Cgs + CM
2
IDQ 5IDQ + 5.76 = 0 = 20 + 12 = 32 pF
+5 ± 25 - 4 ¥ 5.76 Total output capacitance = Co = Cgd + Cs
IDQ =
2 = 2 + 20 = 22 pF
+5 ± 1.96 +5 ± 1.4 1
= = = 1.8 mA / 3.2 mA fHi = = 4.97 kHz
2 2 2p ¥ 10 6 ¥ 32 ¥ 10 -12
The IDQ cannot be 3.2 mA because it will 1
fHo =
develop a drop of 32 V across the RD = 10 2p ¥ 2.5 ¥ 10 3 ¥ 22 ¥ 10 -12
K which becomes more than the dc supply = 2.894 MHz
voltage even. Hence IDQ = 1.8 mA. The
VDS = VDD 1.8 mA ¥ 10 K = 30 18 = The under cut-off frequency = 4.97 kHz
12 V and VGS = 0.5(30 18) = 6 V.
Figure 9.43(a)
"$
Figure 9.43(b)
12. A JFET with the following parameters is Solution:

used in a single stage common-source am- The equivalent circuit of the common-
plifier with a load resistance of 100 K. Cal- source amplifier at high frequency is drawn
culate the high frequency cut-off (upper in Fig. 9.44. Now, rd||RL = 100 K||100 K
3 dB) of the amplifier. gm = 2 mS, Cgs = = 50 K.
2.5 pF, Cgd = 2 pF, Cds = 1 pF, rd = 100 K.
Figure 9.44
Input side Miller capacitance =CMo = = 6.67 Mrad/s
FG g R IJ C Hence, upper 3 dB cut-off = 4.89 Krad/s
m L
gd = Cgd = 2 pF
H1 + g R K
m L
13. In the MOSFET amplifier shown in Fig.
9.45(a), the FET has m = 50, rd = 10 K,
Co = 1 + 2 = 3 pF Cgd = 1 pF, Cgs = 5 pF, Cds = 2 pF. Draw a
small signal equivalent circuit for the am-
CMi = (1 + gm RL )Cgd = (1 + 2 ¥ 50)2 pF plifier and calculate its mid-band voltage
= 202 pF gain.
Solution:
Ci = Cgs + CM = 2.5 pF + 202 pF = 204.5 pF
mvgs
6
From Fig. 9.45(b), id =
1 1 10 RS + rd + RL
wHi = = -12 6
=
Ci Ri 204.5 ´ 10 ´ 10 204.5 where, RL = RL || RD = 10 K
= 4.89 Krad/s
vgs = vg vs = vi - Rs id
1 1 108 mvgs
wHO = = = = vi - Rs
Co RL 3 ´ 10-12 ´ 50 K 15 RS + rd + RL
FET Amplifiers
"%
1 V, IDS = 0.5 mA. Estimate the value of

VDS and RD.
Figure 9. 45(a) Figure 9.46
Solution:
2
ID = 0.5 mA = k VGS - Vth b g
= (VGS - 1)2 ´ 10-4
2
bV GS g
-1 = 5 = (2.24)2
VGS = 3.24 V
Figure 9.45(b) Equivalent circuit. 10 - 3.24 6.76
RD = = = 13.52 KW
0.5 mA 0.5 mA
where, RL = RL||RD = 10 K
15. The common source amplifier shown in
vgs = vg vs = vi Rsid
Fig. 9.47 a employs enhancement mode n-
mvgs MOSFET having its parameters: Cgd =
= vi - Rs 2 pF, Cgs = 4 pF, and Vth = 1 V, ID = 2 mA,
RS + rd + RL
VGS = 3 V, VDD = 30 V. Determine mid
mvi gain of the amplifier. Also obtain the higher
id =
rd + RL + (1 + m ) RS cut-off frequency of the amplifier.
mvi RL Solution:
vo = RLid = -
rd + RL + (1 + m ) RS
VDD R2 30 ¥ 10
vo mRL VG = = = 2 V and
=- R1 + R2 150
vi rd + RL + (1 + m ) RS
2
50 ´ 10 K ID
FV
= 2K G GS I
- 1J = K2 F 3 - 1I 2
= 4K2
= - 2
H1 K
10 K + 10 K + 51 ´ 1 K HV T K
2
50 ´ 10 K and K2 = = 0.5
= - = - 7.04 4
71 K
14. A nMOS circuit is shown in Fig. 9.46. The
gm =
∂I D V
= 2 K2 GS - 1
F I F 1 I and
specifications of the circuit are VDD = 10 V, ∂VGS VT GH JK GH V JK
T
b = k = m n Cox
F I
W
= 10-4 mA /V 2 , Vth = gmo = 2 K 2 ¥
1
H K
L VT
"&
Figure 9.47(a) Common source amplifier
Figure 9.47(b) Simplified H.F. equivalent circuit.
Hence for VGS = 2 V, 20 ´ 9.3

= 20 K || 9.3 K = = 6.35 K
æ VGS ö 29.3
æ2 ö
gm = gmo ç - 1÷ = 1 mSç - 1÷ = 1 mS vi
è VT ø è1 ø ii =
RG
rs +
v 1 + jwCi RG
Avg = o = gmRL
vg vi (1 + jwCi RG )
=
= - 1 mS ´ (40 K || 40 K) = 20 rs + RG + jwCi RG rs
10 ¥ 140 RG
RB = 10 K||140 K = K = 9.3 K vg = ii
150 1 + jwCi RG
RB 9.3 K RG vi (1 + jwCi RG )
vg = vi = vi = 0.9vi. = ¥
rs + RB 0.5 K + 9.3 K 1 + jwCi RG rs + RG + jwCi RG rs
vo vg RG vi
Avs = ¥ = 20 × 0.95 = 18.98 = ¥
v g vi rs + RG 1 + jwCi RG rs / (rs + RG )
Total input capacitance = Ci RG vi

= ¥
rs + RG 1 + jwCi RG || rs
= Cgs + (1 + gm RL )Cgd
RG vi
= 4 pF + (1 + 1 ´ 20)2 pF = 46 pF = ¥
rs + RG 1 + jw / w gs
RLeq = rd || RL || RG @ RL || RG
1
where wgs = , rs || RG
Ci (rs || RG )
FET Amplifiers
"'
0.5 K ´ 9.3 K
= = 0.47 K
9.8 K
1012 109
wH1 = = = 45.8 Mrad/s
46 ´ 0.47 K 21.83
The total output capacitance = Ci as the
second stage input capacitance and the bi-
asing resistor will come in effect. Now the
effective resistance in parallel with Ci will
be parallel combination of rd, RL and RG of Figure 9.48(a)
the second stage.
1012 10 9
wH2 = = = 3.4 Mrad/s
46 ¥ 6.35K 292
The lower of the two frequency deter-
mines the higher cut-off frequency of the
amplifier and = 3.4 Mrad/s = 0.54 MHz.
16. An n-channel MOSFET having VTH = 2 V
is used in the circuit of Fig. 9.48(a). Figure 9.48(b) Equivalent circuit.
Initially the MOSFET is off and it remains
in steady state. At time t = 0, a step of 10 8 A B
magnitude 4 V is applied to the input so vo = - = + ,
S(S + 10 ) S S + 10 7
7
that the MOSFET turns ON instanta-
neously. Draw the equivalent circuit and 10 8 108
A=- 7 = 10, and B = = 10
calculate the time taken for the output vo to 10 10 7
fall to 5 V. Device constant k = 5 mA / V2, 10 10
rd = 0, Cds = Cgd = 0. vo = - +
S S + 10 7
Solution: 7
vo(t) = - 10(1 - exp -10 t ) = 5
Initially capacitor was charged to 10 V. 7
0.5 = (1 - exp -10 t )
2 2
b
ID = K VGS - VT g = 5a4 - 2f = 20 mA 7
exp -10 t = 1 + 0.5 = 1.5
10 v dv 7 1
Writing KCL, 20 mA = - o -C o exp10 t =
1K 1K dt 1.5
ln 1 - ln(1.5) 0.41
10 -3 t= = - 7 = 0.04 ms
10 = -10-3 (1 + S ´ 10-7 )vo 10 7
10
S
17. In the MOSFET amplifier of Fig. 9.49 a,
= - ( S + 10 7 )10 -7 vo the signal outputs v1 and v2 obey the rela-
"
tionship (a) v1 = v2/2, (b) v1 = v2/2, (c) v1 mRD vi

= 2v2, (d) v1= 2v2. v2 =
(3 + m ) RD + 2 rd
2 m(vi - v2 ) RD
v1 = - RD id = -
3 RD + 2 rd
2 mvi RD 2 mRD
=- +
3 RD + 2 rd 3 RD + 2 rd
mRD vi
¥
(3 + m ) RD + 2 rd
2 mRD vi mRD - 3 RD - mRD - 2 rd
= ¥
3 RD + 2 rd (3 + m ) RD + 2 rd
Figure 9.49 a 2 mRD vi 3 RD + 2 rd
= ¥-
3 RD + 2 rd (3 + m ) RD + 2 rd
- 2 mRD vi
= = 2 v2
(3 + m ) RD + 2 rd
Hence, option (d) is correct.
18. The enhancement mode nMOSFET used
in Fig. 9.50 has a threshold voltage VT =
0.3 V. Its operating point always remains
in the constant current region of its VI-
Figure 9.49(b) characteristic with an input signal of VI =
0.5 coswt . Its drain current is expressed
2
Solution: c
as iD = K2 VGS - VT h mA .
Writing the loop equation yields
m n e oe r W
(3 RD / 2 + rr )id = mvgs = m( vi - v2 ) where, K2 = = 0.3
2tL
2 m ( vi - v2 ) mn = mobility of the electron in the
= m ( vi - RDid / 2 ) , id =
3 RD + 2 rd channel
v2 =
F R I i = F R I 2 m(v - v )
D D i 2 e r e o = permitivity of the oxide layer
H 2 K H 2 K 3R + 2r
d
D d
below the gate
m( vi - v2 ) RD W = width of the channel
=
3 RD + 2 rd t = thickness of the channel
mRD (3 + m ) RD + 2 rd L = length of the channel between the
v2 (1 + ) = v2 drain and source
3 RD + 2 rd 3 RD + 2 rd
mvi RD Determine its power relations and distor-
= tion in the amplifier, if rs = 0.5 K, RL =
3 RD + 2 rd
FET Amplifiers
"
3.9 K, VDD = 20 V and VGG = 6 V. = 2.7375 + 0.9 cos wt + 0.0375 cos 2wt
Solution: = 2.74 + 0.9 cos wt + 0.0375 cos 2wt
% second harmonic distortion
ID = 0.3 3.3 - 0.3 = 0.3 ´ 9 = 2.7 mA
2
0.0375
VP = VDD IDRL = ¥ 100 = 0.42%
0.9
= 20 - 3.9 K ´ 2.7 mA = 20 - 10.5 = 9.5 V Magnitude of fundamental current = id1
Power drawn from dc power supply = = 0.9 mA
PDD = VDDID = 20 ¥ 2.7 = 54 mW Drop across the load due to fundamental
current = 0.9 × 3.9 = 3.51 V
v RL
3.51
Voltage gain = Av1 = =7 =
vi 0.5
Now total dc current = 2.74 mA
Now PDD = VDD × 2.74 mA = 54.8 mW
PL = (iD2 + iD2(rms)) RL
= 3.9 × (2.74)2 + RLiD2(rms)
Figure 9.50 Enhancement nMOS amplifier = 3.9 × 7.5 + RLiD2(rms)
= 29.25mW + RLiD2(rms)
The quiescent power dissipated across the
MOSFET = PD ( i d1 ) 2 ( i d 2 ) 2
+
= VDS × I D = 9.5 × 2.7 = 25.65 mW . iD(rms) = 2 2
The dc power dissipated in the load 2
= I D2 RL = 2.7 2 ´ 10 -6 ´ 3.9 K = 28.4 mW . ( 0.9) 2 (0.0375) 2

+
When input signal is connected ID = 2 2
2 2
c
= 0.3 VGS - VT + vi h 0.405 + 0.0007 0.4057
2 = = = 0.45
= 0.3b3.3 - 0.3 + v g
i 2 2
= 0.3b3 + v g
2 PL = 29.25 mW + 3.9(0.45) 2
i
= 29.25 mW + 0.789 mW = 30 mW
= 0.3(9 + 6 vi + vi2 )
PD = PDD PL = 54.8 30 = 24.8 mW.
= 2.7 + 1.8vi + 0.3vi2
19. The n-channel FET used in amplifier of
= 2.7 + 0.9 cos wt + 0.3( 0.25 cos 2 wt ) Fig. 9.51 has parameters as : IDSS = 10 mA,
2 cos 2 wt VP = 4 V and gmo = 5 mS. If the coupling
= 2.7 + 0.9 cos wt + 0.075 and bypass capacitors are treated to be
2
short circuited, determine the value of the
= 2.7 + 0.9 cos wt + 0.0375(2 cos 2 wt ) Rs and RL at the operating point ID =
= 2.7 + 0.9 cos wt + 0.0375(1 + cos 2wt ) 2.5 mA, and VDS = 10 V.
"
Figure 9.51 n-channel FET amplifier
Given : ID =2.5 mA, VDS = 10 V, VP = ID 2.5

4 V, IDSS = 10 mA = 5´ =5 = 2.5 mS
I DSS 10
Solution:
The drain current of FET is expressed as 1 Mvi
vg = @ vi
2
1 M + 0.5 K
æ V ö
ID = I DSS ç 1 - GS ÷ = 2.5 mA vo = - gm RL vg = - 2.5 ¥ 8Kvg
è Vp ø
= 20vg = 20vi
2
10 ¥ 10 -3 1 -F VGS I = 2.5 mA Hence, the voltage gain Avs =
vo
= 20
H -4 K vi
2
= 10 ¥ 10 -3 1 +
F VGS I vDS = VDS + vds = 10 20vi
H 4 K = 10 - 20Vim coswt
2
F1 + V IGS
= 0.25 and 1 +
VGS
= 0.5 vGS = VGS + vgs = VGS + Vim coswt
H 4K 4 = 2V + Vim coswt
or VGS = 2 V = RSID
VP = VDS + VGS
2
Rs = = 0.8 KW and VDD 10 20Vimcoswt = - 2 V + Vim cos M t + 4
2.5 mA and 21Vim coswt = 8
= VDS + RLID 8
Vim = = 0.38
30 - 10 21
or RL = = 8 KW
2.5 mA 20. Determine the value of VP and ID for VGS =
The transconductance of the FET = gm 0.5 V of an n-channel FET that has IDSS =
10 mA with drain voltage of 5 V and gmo =
=
∂I D V
= 2 I DSS 1 - GS
F I F- 1 I 5 mA/V.
∂VGS VP GH JK GH V JK P
Solution:
gmo =
∂I D
= 2 I DSS
F - 1 I and VP =
2 I DSS 2 ¥ 10
=4V
∂VGS GH V JK P gmo
=
5
gm = gmo 1 -
F VGS I
GH VP JK
FET Amplifiers
"!
F V I 2 VGS = 0.58V, VDD = 25 = VDS + IDRD

GS
I = I G1 - 15
D
H V JK
DSS
P = 10 + 5 ¥ RD, RD =
5 mA
= 3 KW
2
F 0.5 I = 10a1 - 0.125f
= 10 1 -
2
F V IR 2
H 4K v = V = I R = - I G1 - GS
= 10 ¥ 0.766 = 7.7 mA.

o DS
H V JK
D D DSS
P
L
21. Design a suitable n-channel FET amplifier Gain =

∂V F V I R F- 1 I
DS
= -2 I G1 - GS
circuit that produces quiescent point ID = ∂V H V JK GH V JK
GS
DSS
P
L
P
5 mA, VDS = 10 V with IDSS = 10 mA and æ 0.58 ö æ 1 ö
VP = 2 V, VDD = 25 V. = 2 ¥ 3 ¥ 10 ç1 = 38.7
è 2 ÷ø çè 2 ÷ø
2
ID = I DSS 1 -
F VGS I, 22. The common gate amplifier shown in Fig.
GH VP JK 9.52 employs an n-channel FET whose
2 2
drain current is described as ID = W
æ V ö æ V ö 2
5 = 10 ç 1 GS ÷ , 0.5 = ç1 GS ÷
è 2 ø è 2 ø
FGV IJ
16 1 + GS mA with VDD = 30 V and
H 2 K
æ VGS ö VGS VDS = 10 V. Calculate the value of wgd,
0.71 = ç1 + ÷, wgs and wH for Cgs= 5 pF and Cgd = 2 pF.
è 2 ø 2
Figure 9.52 Common gate amplifier

50 ¥ 30 -33 ± 1089 - 4 ¥ 8 ¥ 26
VG = = 6 V, and VGS +IDR VGS =
250 2 ¥8
= VG = 6 V
2 -33 ± 257 -33 ± 16
6 - VGS F V IJ GS
= =
ID = = 16 G1 + 2¥8 2¥8
2 H 2K -49 -17
= , = 3 V, 1 V.
6 VGS
F
= 32 G1 + V +
V I 2
GS 16 16
4 JK
GS
H 6 - VGS 6 + 1
ID = = = 3.5 mA
2
= 32 + 32 VGS + 8VGS 2 2
2
8VGS + 33VGS + 26 = 0 gm =
∂I D V F
= 2 ¥ 16 1 - GS -
1 IF I
∂VGS VP GH VP JK GH JK
""
F
32 1 -
1 1 IF I
= 32
1 1 F IF I
= 8 mS
2
F V I = 12F1 - 4 - 2 I I
GS
2
H 2 2 KH K 2 2 H KH K I = I G1 -
D
H V JK H -4 K
DSS
p
D
VDD = IDRD + VDS + IDRG

2 2
= IDRD + 10 V + 2 × 3.5 = IDRD + 17 = 12b2 - 0.5 I g = 12(4 - 2 I + 0.25 I )
D D D
IDRD = 30 17 = 13 3ID2 25ID + 48 = 0

13 25 ± 625 - 576
RD = = 3.7 K and ID =
3.5 mA 6
3.7 ¥ 20 25 ± 7
RL = 3.7||20 = = 3 KW = = 5.33 mA, 3 mA
23.7 6
1 1012 VGS = VG VS = 4 2 × 5.33
wgd = = = 6.66 V and also
Cgd RL 2 ´3 K
= 4 2 × 3 = 2 V
109
= = 167 Mrad/s VDS = 20 4 × 5.33
2´3
= 20 21.32 (not possible)
0.5 ¥ 2 1
rs||RG = = 0.4 K and rs || RG || VDS = 20 4 × 3 = 8 V
2.5 gm
VDS(8 V) ≥ VGS VP = 2 ( 4) = 2 V
0.4 ¥ 0.125
= = 0.095 KW
0.525
1 1012
wgs = =
æ 1 ö 5 ´ 0.095 K
Cgs ç rs || RG ||
è gm ÷ø
10 9
= = 2.1Grad / s
5 ¥ 0.095
The lower of the two will be the upper cut- Figure 9.53
off frequency = wH = 167 Mrad/s
23. A JFET with VP = 4 V, IDSS = 12 mA is Hence, it is in saturation.
used in the circuit shown in Fig. 9.53. As- 24. An n-channel JFET has IDSS = 1 mA and
suming the device to be operating in satu- VP = 5 V. Obtain the value of its maxi-
ration, (a) determine ID, VDS and VGS and mum transconductance.
(b) check to confirm that the device is in-
Solution.:
deed operating in saturation.
2
Solution:
ID = I DSS
F1 - V I
GS
and
20 ¥ 100
GH V JKp
VG = = 4 V,
500 ∂I D V 1
VGS = VG VS = 4 IDRs gm = = 2 I DSS (1 - GS ) (- )
∂VGS Vp Vp
FET Amplifiers
"#
2I DSS 2 ´ 1 mA IDSS = 16 mA.

gm(max) = gmo(VGS = 0) = =
Vp 5 Solution:
2
= 0.4 mS F V I = 16F1 - V I 2
GS GS
I = 4 = I G1 -
25. The JFET in the circuit of Fig. 9.54 has
IDSS = 10 mA and VP = 5 V. Obtain the
D
H V JK H -4 K
DSS
p
2
value of Rs for a drain current ID = 6.4 mA. F V I and ± 1 = F1 + V I
GS GS
1 = 4 1+
Solution: H 4K 2 H 4 K
1
V = 4F ± - 1I = 2 V, and 6 V
2
ID = 6.4 = I DSS
F1 - V I
GS F
= 10 1 -
VGS I 2
GS
H 2 K
GH V JK p
H 5 K
Since, VGS = 6 V is less than VP = 4 V
VGS
0.8 = 1 - that is meaningless.
5
Thus, VGS = 2 V is valid = VG VS
Hence, VGS = 0.2 × 5 = 1 V
= 0 RsID
VGS = VG VS = 0 Rs × 6.4 = 1 V
2 V - VD
1 Rs = = 0.5 K and RD = DD
Rs = = 0.156 KW 4 mA 4 mA
6.4 mA
10 - 6
= = 1 KW
4 mA
Figure 9.54
26. An n-channel JFET has a pinch-off volt-
age VP = 5 V, VDS = 20 V and gm = 2 mS. Figure 9.55
The maximum ON resistance is achieved
in the JFET for (a) VGS = 7 V and VDS = 28. The JFET in the circuit of Fig. 9.56 is char-
0 V, (b) VGS = 0 V and VDS = 0 V, (c) VGS acterized by the parameters IDSS = 4 mA
= 0 V and VDS = 20 V, (d) VGS = 7 V and and VP = 4 V. Find (a)Vo if VI = 0, and
VDS = 20 V. (b)VI if Vo = 0.
Solution: Solution:
For minimum value of rd(ON) the length VI = 0 = VGS + 2KID 12
should be minimum with VDS = 20 V and VGS = 12 2KID
the area should be maximum requiring VGS 2
= 0 V. Option (c) is correct. F
ID = 4 1 +
2 I D - 12 I b
= 4 1 + 0.5 I D - 3 g 2
27. Design the circuit of Fig. 9.55 to obtain ID =

H 4 K
2
4 mA and VD = 6 V. Given VP = 4 V and b
= 4 0.5 I D - 2 g
"$
2 2 = 0.5(30 - 10KI DQ ) = (15 - 5KI DQ )

b
= 4 ¥ 0.707 I D - 4 g b
= 2.83 I D - 4 g
I D2 - 8 I D + 16 = 0.35ID IDQ = 0.2(VGS - VT )2
ID2 8.351ID + 16 = 0 = 0.2(15 - 5 I DQ - 3) 2 = 0.2 (12 - 5 I DQ ) 2
8.35 ± 69.72 - 64 = (6 - 2.5 I DQ ) 2
ID =
2 2
6.25 I DQ - 30 I DQ + 36 = IDQ
9 ± 5.72 8.35 ± 2 .39 2
= = 6.25 I DQ - 31 I DQ + 36 = 0
2 2
2
10.74 5.96 I DQ - 4.96 I DQ + 5.76 = 0
= , = 5.37 mA , 2.98 mA
2 2 4.96 ± 24.6 - 4 ¥ 5.76
VGS = 12 2KID = 12 2 K × 5.37 mA IDQ =
2
= 12 10.74 = 1.26V and
4.96 ± 24.6 - 23 4.96 ± 1.6
VGS = 12 2 K × 2.98 mA = 6.04 V = =
2 2
Vo = 12 + 2KID = 12 + 10.74 = 1.26 V 4.96 ± 1.265
and = 12 + 2 K × 2.98 mA = 6.04 = = 1.85 mA , 3.1 mA
2
Figure 9.57(a)
The IDQ cannot be 3.1 mA as it will de-
Figure 9.56 velop a drop of 31 V across the RD = 10K
29. Calculate the quiescent values IDQ, VGS and that becomes more than the dc supply
VDS in the region VDS ≥ VGS Vpo for Vpo = voltage. Hence, IDQ = 1.85 mA. Then VDS
+3 V of Fig. 9.57(a). The drain current of = VDD 10 K ¥ 18.5 mA = 30 15.8 =
the enhancement type MOSFET is ex- 11.5 V and VGS = 0.5(30 18.5) = 5.5 V.
pressed as IDQ = 0.2 mA(VGS Vpo )2. 30. A pMOS has kp = 2 mA/V2 and Vth = 1 V.
It is used as an amplifier shown in Fig.
Solution:
9.57(b), (a) with R1 = 3 MW, R2 = 1 MW,
VDD - RD I DQ and VDD = 12 V. Obtain the value of (a)RS
VGS = 0.5VDS =
2 for VGS = 2 V, (b)RD to make VDS = 4
= 0.5(VDD - RD I DQ ) V. Also obtain the new value of R2 to main-
tain ID by changing Vth = 1.5 V assuming
all other parameters of the transistor re-
FET Amplifiers
"%
maining the same as in (a) and (b). 1.5 ¥ 3 M

R2(new ) = = 0.429 M
Solution: 10.5 M
- 12 ¥ 1 31. The circuit in Fig. 9.58 uses an nMOS
(a) VG = = 3 V with kn = 2 mA/V2, Vth = 4 V The circuit
4
has RD = RS = 2.5 K, R1 = 1 MW and R2 =
VG - VGS + I D RS = 0 2 MW. Obtain (i) ID and VDS. (ii) New
IDRS = - VG + VGS = 3 V 2 V = 1 V value of RS, if ID is to be kept constant at
the value calculated in (i) with changing kn
ID = k p (VGS - Vth( p ) )2 = k p (-2 + 1)2
= 4 mA/V2.
= 2*10 -3 = 2 mA 12 ¥ 2
VG = =8V
1V 3
RS = = 0.5 K VGS = VG IDRS = 8 2.5ID
2 mA
VDD = ( RD + RS ) I D + VDS ,
( RD + RS )2 mA = 12 4 = 8 V
RD + RS = 4 K and
VGS = 0.5 V, VG VGS + ID RS = 0
VG + 0.5 + 2 × 0.5 = 0
-12 R2(new)
VG = 1.5 V =
R1 + R2(new)
RD = 4 K 0.5 K = 3.5 K
(b) For Vth = 1.5 V, Figure 9.58
ID = k p (VGS - Vth( p ) )2 and 2 mA For saturation condition, VDS > (VGS - Vth )
and
ID = k p (VGS - Vthn )2 = k p (8 - 2.5 I D - 4 )2
= 2(4 - 2.5 I D )2 = 2(16 - 20 I D + 6.25 I D2 )
F
= 2 ¥ 6.25 I D2 -
20
ID +
16 I
H 6.25 6.25 K
= 12.5( I D2 - 3.20 I D + 2.56 )
Figure 9.57(b) ID
I D2 - 3.20 I D - + 2.56 = 0
12.5
= 2 mA(VGS + 1.5) 2 I D2 - 3.28I D + 2 .56 = 0
VGS + 1.5 = 1
3.28 ± 10.7584 - 10.24
1.5( R1 + R2 ( new ) ) = 12 R2 (new) ID =
2
"&
3.28 ± 0.5184 3.28 ± 0.72 = 8 2.5 × 1.275 = 4.8125 V

= =
2 2 VDS > (4.8125 4) = 0.8125 V (valid)
= 2 mA and 1.275 mA Valid value of ID = 1.275 mA and not
VDD = VDS + I D ( RS + RD ) 2 mA.
VDS = VDD - I D ( RS + RD ) ID = 1.275 mA and VDS = 5.625 V
= 12 - 2 ¥ 5 = 2 V (b) ID = k p (VGS - VTn )2 = 4(VGS - 4 ) 2
VDS = VDD - I D ( RS + RD ) 1.275

VGS 4 = = 0.5636 and
= 12 1.275 ¥ 5 = 5.625 V 4
VDS > (VGS Vth) VGS = 4.5635 V
VGS = (VG - 2.5 I D ) = (8 - 2.5 ¥ 2) = 3 V Now, IDRS = VG VGS = 8 4.536
and VDS > (3 4) = 1 V (not valid) = 3.4365,
For ID = 1.275 mA, VGS = (VG 2.5ID) 3.4365
RS(new) = = 2.6953 KW
1.275
Multiple Choice Questions 6. The most popular FET amplifier configu-

ration is
1. The output resistance of a source follower (a) common source
is (b) common drain
(a) high (b) low (c) common gate
(c) medium
7. The circuit shown in Fig. 9.59 is an ex-
2. The input resistance of a common drain ample of
amplifier is (a) current series feedback
(a) low (b) high (b) current shunt feedback
(c) medium (c) voltage series feedback
3. The voltage gain of a common gate ampli- (d) voltage shunt feedback
fier is 8. The output resistance of Fig. 9.59 due to
(a) low (b) high feedback gets
(c) medium (d) nearly unity (a) increased
4. The input resistance of a common gate (b) decreased
amplifier is (c) non-variant
(a) low (b) high 9. The input resistance in Fig. 9.59 due to
(c) medium feedback is
5. The output resistance of a common gate (a) increased (b) decreased
amplifier is (c) not affected
(a) low (b) high
(c) medium
FET Amplifiers
"'
0.5 K, m = 10, rd = 20K is

(a) 25.5 K (b) 20 K
(c) 5.5 K
15. If a load resistance in Problem 14 is 2K, its
input resistance is
(a) 22 K (b) 2 K
(c) 242 K (d) 20 K
Figure 9.59
16. The voltage gain of the amplifier shown in
Fig. 9.60 is
(a) 10 (b) 5
(c) 25 (d) 25
(e) 10
17. Output resistance of Fig. 9.60 is
(a) 10 K (b) 5 K
(c) • (d) 20 K
18. The output resistance of Fig. 9.61 is
(a) 30 (b) 300
Figure 9.60 (c) 10 (d) •
19. If rd = 20 K, gm = 2 mS, resistance con-
10. The gain bandwidth product of an FET nected in the source to ground is 3 K, the
amplifier w.r.t. a BJT amplifier is voltage gain of this amplifier is approxi-
(a) low (b) high mated as
(c) equal (d) zero (a) 40 (b) 0.9
11. The output resistance of a CS amplifier is (c) 9 (d) 6
(a) rd||RD (b) rd + (1 + m)RS
(c) rd (d) (1 + m)RS
(e) (1 + m)rd
12. The input resistance of a BJT amplifier
w.r.t. its FET counter part is
(a) more (b) less
(c) equal (d) none of these
13. The output resistance of CD amplifiers
given by Figure 9.61
1 20. If Av = 0.9 in Fig. 9.60, the value of gm is
(a) || rd || Rs (b) rd||Rs
gm (a) 3 mA/V (b) 0.33 mA/V
(c) 3 A/V (d) 0.3 mA/V
(c) rd + (1 + m)Rs (d) rd
21. Voltage gain of a common gate amplifier
14. The output resistance of a CG amplifier
with m = 15, rd = 20 K, RL = 2 K, internal
with voltage source internal resistance of
resistance of the voltage source = 2 K is
"
(a) 0.64 (b) 6.4 quency with rd = 20 K, RD = 5 K, gm = 5

(c) 0.89 (d) 0.9 mS, Cgs = 8 pF, Cgd = 4 pF, Cds = 2 pF is
22. Total input capacitance across the input (a) 76 pF (b) 44 pF
terminals of a CS amplifier at high fre- (c) 26 pF (d) 22 pF

1. (b) 2. (a) 3. (b) 4. (b) 5. (a) 6. (a)
7. (c) 8. (c) 9. (c) 10. (a) 11. (b) 12. (b)
13. (a) 14. (a) 15. (b) 16. (a) 17. (a) 18. (b)
19. (d) 20. (b) 21. (a) 22. (b)
10
Frequency Response of BJT

Amplifiers
10.1 Introduction
The frequency response of any amplifier is defined as change in its output voltage (voltage gain) w.r.t.
varying frequency of the input signal applied to it. In other words, it is the plot of the output voltage
(voltage gain) versus frequency. We know that the frequency of the signal has a pronounced effect on
the response of any network including amplifier having reactive components. Generally all amplifiers fall
in one of the following three categories:
∑ RC coupled
∑ Transformehr coupled
∑ Direct coupled
10.1.1 RC Coupled
We know that the coupling capacitors C1, C2 and the emitter bypass capacitor CE of RC coupled
amplifier shown in Fig. 10.1 at extremely low frequency cannot be assumed short circuited. The reactance
of capacitance increases with decreasing frequency as XC = 1/w C. Hence, at extremely low frequency
its reactance becomes very high and ultimately at zero frequency its reactance theoretically becomes
infinite (1/ wC = 1/0 ¥ C = •). Thus, coupling and bypass capacitors behave as open circuit at extremely
low frequencies. Similarly, the frequency dependent components of the small signal equivalent circuit of
"
the active device and the stray capacitances limit the high frequency response of the amplifier as depicted
in Fig. 10.2. These limitations are present in cascaded stages also.
Figure 10.1 RC coupled amplifier Figure 10.2 Frequency response

Advantages of RC Coupled Amplifier
∑ Cheap (low cost of 4and +)
∑ Light in weight
∑ Better frequency response in audio frequency range
Disadvantages
∑ Comparatively less gain because of loading effect of succeeding stage
∑ Poor impedance matching (output impedance for RC coupled amplifiers is several hundreds of
ohms, but for loudspeaker is only few ohms (4 W typical)
∑ Poor reception with passage of time
10.1.2 Transformer Coupled

Figure 10.3 is the circuit of transformer coupled amplifier. Another good example of transformer coupled
amplifier is the tuned or narrow band amplifier shown in Fig. 10.4.
Figure 10.3 Transformer coupled amplifier

The amplifier that amplifies only one particular frequency or a very narrow band of frequencies is
called tuned potential amplifier. Tuned amplifiers are very widely used in radio and television receiver
Frequency Response of BJT Amplifiers
423
circuits. What we do in the name of tuning is that the carrier frequency wo is varied keeping the
bandwidth wH wL as demonstrated in Fig. 10.4 constant.
Figure 10.4 Response of tuned circuit
wo = carrier frequency of the broadcasting station

wH wL = required bandwidth to receive the signal without significant distortion
In tuning the radio receiver, the dial is set at the carrier frequency of the transmitting station, typically
at 455 kHz for AM, and a signal of the same frequency is supplied to its input. The threaded screw-type
ferrite material of the Intermediate Frequency (IF) transformer is varied slowly and its output voltage is
measured. When the indication of the meter becomes the maximum the IFT is tuned at the frequency
455 kHz as indicated wo in Fig. 10.4. Here, wH and wL are 3 dB frequencies of the tuned circuit having
the maximum value of the signal voltage at wo.
Hence, this transformer coupled amplifier works as a band-pass filter. In other words, it develops
sufficient amount of voltage across its secondary winding for the frequency range of wH wL, to
wH + wL only. The frequencies other than these do not develop sufficient amount of voltage and its
output will be much below the 3 db level. Thus, its effect will not be seen at the output. Hence, it is said
that the frequencies other than 455 kHz have been rejected.
The Class-C amplifier is a narrow band amplifier. Here, it is important to note that the Class-C
amplifier introduces considerable distortion if it is used for amplification of signals having large number
of frequencies. Hence, it becomes essential to use Class-C amplifier for constant amplitude single
frequency signal called the carrier wo. In broadcasting, the intelligence (modulating signal) and the
carrier voltages are amplified separately. The Class-AB amplifier amplifies the signal voltage and the
Class-C amplifier amplifies the carrier voltage.
Advantage of Transformer Coupled Amplifiers
∑ Higher voltage gain can be achieved using step-up transformer
∑ No signal power loss in coupling network (winding resistance very small)
∑ Excellent impedance transformation to obtain maximum power across load
Disadvantages
∑ Bulky in size
∑ Costlier w.r.t. RC coupled amplifier
424
∑ Poor frequency response over audio frequency

∑ Induces hum due to power wiring
Transformer coupled amplifiers have special use in tuned and power amplifiers. The IF stages of
radio receivers are transformer coupled with small capacitors connected across its windings to get
tuned at one particular frequency resulting into maximum voltage gain. The power amplifiers handle
large amount of dc current and hence the load should (loud speaker or servo motor, etc.) be isolated
from the dc circuit. Also the transformer matches the impedance (resistance) of very low value of
speaker to very high value of output impedance (resistance) of amplifiers and produces maximum
power transfer. Thus, transformer coupled amplifiers are specially used for these types of amplifications.
The output of the first stage of the transformer-coupled amplifier shown in Fig. 10.3 appears across
primary winding of the coupling transformer. The output of the coupling transformer is connected to
the input of the second stage. Since the name of the coupling goes after the type of coupling used, it is
called transformer-coupled amplifier. The frequency response of the transformer- coupled amplifier is
very poor in the sense that its output is not constant at all in any frequency range. As the frequency goes
on decreasing, the reactance (XL = wL) of the primary winding of coupling transformer starts decreasing
resulting into decreasing gain. At high frequency, junction capacitors start acting as bypass capacitors
and gain starts decreasing with peaking at some frequency due to resonance. Thus, the transformer-
coupled amplifier amplifies the signals differently at different frequencies, resulting into distortion.
Frequency response of the transformer coupled amplifier shown in Fig. 10.7 does not remain constant
for very low range of frequency.
10.1.3 Direct Coupled

Figs.10.5 and 10.6 are the circuits of direct coupled (dc) amplifier. The frequency response of dc
amplifier is shown in Fig. 10.8. There are no reactive components in the coupling of two stages of the
dc amplifier and hence at high frequency its gain does not fall.
Figure 10.5 Direct coupled amplifier
The two stages of direct coupled (dc) amplifier are either connected directly or through battery or
Zener diode as shown in as in Figs.10.5 and 10.6 respectively. The frequency response of transformer
coupled looks like the one shown in Fig. 10.7. Since there is no reactive component that couples two-
stages of dc amplifier, source and load, its frequency response is flat at low frequency. At high frequency,
425
gain of the dc amplifier falls down due to junction capacitors working as bypass capacitor at high
frequency. The dc amplifier finds its special use wherever very low frequency signals or time average
of the signals are to be amplified. A suitable Zener diode is introduced in Fig. 10.6 to drop the required
voltage difference to maintain the potential at the original value.
Figure 10.6 DC coupled amplifier
Figure 10.7 Transformer coupled amplifier response Figure 10.8 DC amplifier response
The positive end of the battery is connected to the collector point of the first stage of the amplifier
whereas the negative terminal of the battery is connected to the input point of the second stage of the
amplifier to maintain the difference of dc potential as per the bias conditions in dc amplifier of Fig. 10.5.
Battery V1 drops down the potential to zero at the base to avoid damaging of the source. But very often
the battery gets discharged.
Advantages of DC Coupled Amplifier
∑ Voltage gain is flat (constant) over wide range of frequency
∑ No reactive component present
∑ Voltage gain does not fall at all at lower frequencies (no reactive circuit)
∑ Responds to extremely low frequency signals
Disadvantage of DC Coupled Amplifier
∑ Drift phenomenon shifts the bias point and hence is unstable
∑ Battery maintenance is problematic
426
The frequencies wL (w1) and wH (w2) are commonly known as corner, cut-off, break, or half-power
frequencies. The multiplier 0.707 is chosen because the power at these frequencies becomes half of the
midband power. The power at mid frequency is
2
Po(mid)
v2
= L =
d
Av ( mid ) vi i (10.1.1)
Ro Ro
Similarly, the power at 3 dB frequency is expressed as
{v L / 2 }2 { Amid vi / 2 }2 1
Po(3 db) = = = Po( mid ) (10.1.2)
Ro Ro 2
10.2 RC Coupled Amplifier Analysis

Figure 10.1 is a general purpose circuit of the RC coupled amplifier alongwith its frequency response
shown in Fig. 10.2. A more detailed circuit of a RC coupled amplifier including junction capacitors and
stray capacitors is drawn in Fig. 10.9. The ac circuit of this RC coupled amplifier is redrawn as Fig.
10.10 including the junction and stray capacitances at high frequency. The frequency response of the RC
coupled amplifier shown in this figure can be broken into three regions for simplicity in analysis as
∑ Low frequency region, i.e. below wL
∑ Mid frequency region, i.e. between wL to wH and
∑ High frequency region, i.e. above wH
10.3 Factors Affecting Frequency Response

The reactance of a capacitor depends on the frequency. Thus, main factor affecting the frequency
response of a RC coupled amplifier is the presence of capacitors. The coupling and bypass capacitors
offer considerable amount of reactances at low frequency that causes loss of signal across it. The
output voltage and the gain of amplifier decrease at low frequencies. This indicates that capacitors
inherently present inside the device (BJT or FET), called junction capacitors might effectively decrease
the gain at high frequencies.
Figure 10.9 RC coupled amplifier with junction capacitances

427
Figure 10.10 RC circuit of RC coupled amplifier

If the coupling capacitors decrease the gain of the amplifier, why are they used? The ac signal source
is connected to the input of the amplifier through a capacitor that is very cheap and effective. This
coupling capacitor blocks the dc current to pass the ac signal and prevents the signal source from
getting damaged by the dc current. Also the bias condition at the amplifier input does not get disturbed.
It is assumed that it provides a short circuit for the ac signals and open circuit for dc. This assumption
is not valid for very low frequency ranges.
10.3.1 Effect of Coupling Capacitors

At mid and high frequencies, the impedance offered by each of the coupling and bypass capacitors is
negligibly low so that the ac signal drop across it can be neglected. Hence, it really works as short circuit
in the mid frequency range. As the frequency starts decreasing, the impedance of the capacitor starts
increasing and consequently the signal drop across it starts becoming significant. A point is reached
where the signal dropped across the input coupling capacitor C1 becomes appreciable. Thus, the signal
reaching the actual input point of the amplifier is much less. Since the signal reaching the actual input
point of the amplifier is reduced, the output voltage is also proportionately reduced. Similarly, the
appreciable amount of signal lost across the output coupling capacitor C2 reduces the actual voltage
reaching the load resistor RL. Thus, the output voltage available across the load resistance RL is much
reduced at low frequencies.
10.3.2 Effect of Bypass Capacitor

In order to analyse the effect of the bypass capacitor on the frequency response, both input and output
coupling capacitors C1 and C2 are assumed to be short-circuited. Similar to the bypass road, the bypass
capacitor CE provides additional easy and parallel path for the ac signal besides already existing path
through emitter resistance RE as shown in Fig. 10.9. Both ac and dc currents flow through the emitter
bias resistance RE in absence of the bypass capacitor that is essential for bias stability. The ac current
passing through RE changes the bias condition. In positive half-cycle, the reverse bias becomes minimum
being at its peak and maximum being at its negative peak as indicated in Fig. 10.11.
Figure 10.11 Variation in bias without CE

428
The simplest combination of R and C components yields circuits shown in Figs.10.12 and 10.13 that
simulate the frequency response shown in Fig. 10.15. One of the the two-circuits provides output as the
input at low frequency while the other provides output as the input at high frequency only. Thus, they
are called low-pass and high-pass circuit.
10.4 Low-pass High-cut RC Circuit

Figure 10.12 is a low-pass RC circuit, using two components. This circuit works as low-pass filter. In
other words, it passes low frequencies without any attenuation and does not allow at all the high
frequency signals to pass through it. The reactance of a capacitor at low frequencies is
1 1 1
XC = = = =• (10.4.1)
wC 2pfC 2p (0)C
Figure 10.12 Low-pass circuit Figure 10.13 Low-pass circuit at f =0

The output voltage is equal to the input voltage in the range of frequency wherein the capacitor works
as open circuited in Fig. 10.13. The circuit of Fig. 10.12 reduces to Fig. 10.13 as if capacitor is not
present. Thus, low frequency signals will be passed without any attenuation and at these frequencies
vi = vo. Similarly, at high frequencies
1 1 1
XC == = =0 (10.4.2)
wC 2p fC 2p ( • ) C
Figure 10.12 now reduces to Fig. 10.14, replacing the capacitor by a short circuit. The output
voltage becomes zero (vo = 0) at high frequencies as indicated in Fig. 10.14. The output voltage vo for
Fig. 10.12 is written as
vi vi v – - tan - (w / w H )
vo = = = i (10.4.3)
1 + jw CR 1+ j
w
1 + (w /w H )
2
wH
1
where, wH = (10.4.4)
CR
Figure 10.14 Low pass circuit at f = • Figure 10.15 Low-pass high-cut RC response
429
The plot of Eqn. 10.4.3 is shown in Fig. 10.15. This represents low-pass high-cut frequency region.
10.5 High-pass Low-cut RC Circuit

Figure 10.16 is another two-component RC circuit that simulates the behaviour of the RC coupled
amplifier in the low frequency region. It is called high-pass low-cut circuit. The reactance of the
capacitor at low frequencies is
1 1 1
XC = = = =• (10.5.1)
wC 2p fC 2p (0)C
Figure 10.16 High-pass RC circuit Figure 10.17 High-pass RC circuit at f = 0
The circuit of Fig. 10.16 reduce now to Fig. 10.17 wherein capacitor looks to be open circuited at
low frequencies. Hence, at low frequencies vo = 0. Similarly, the reactance of the capacitor at high
frequency is
1 1 1
XC = = = =0 (10.5.2)
wC 2p fC 2p (•)C
A short circuit appears across the capacitor C connected in series with the input signal shown in Fig.
10.18. From Fig. 10.16, the output voltage is expressed as
vi vi vi – tan - (w L /w )
vo = = = (10.5.3)
1 wL 1 + (w L / w )2
1+ 1- j
jw CR w
1
where, wL = (10.5.4)
CR
Figure 10.18 High-pass circuit at f = • Figure 10.19 High-pass low-cut RC response
In other words, vo = vi only at high frequencies where the capacitor behaves as short circuit as
shown in Fig. 10.18. This describes that the high frequency signals are passed without any attenuation.
Eqn. 10.5.3 can be plotted as illustrated in Fig. 10.19. This plot looks like the high frequency region plot
of Fig. 10.17. In other words it is called high-pass low-cut circuit.
430
By intuition, it looks that if the two RC circuits shown in Figs. 10.12 and 10.16 could have been
connected in cascade as shown in Fig. 10.20, it would have produced the response as shown in Fig.
10.2. If the two-RC circuits do not load each other, the overall output voltage of the circuit shown in
Fig. 10.20 could be expressed as
vo = vi 1 1 (10.5.5)
FG1 - j w IJ FG1 + j w IJ
L
H wKH w K H
Figure 10.20 Cascaded low-pass and high-pass RC circuits
The first RC block passes low frequency components of signals and attenuates (stops) high frequency
components of signals. On the contrary, the second block of RC circuit only passes high frequency
components of signals and attenuates (stops) low frequency components of signals. Thus, the composite
block of RC circuit shown in Fig. 10.20 passes only mid frequency signals. Hence, its plot of vo w.r.t.
frequency looks exactly like the one drawn in Fig. 10.2.
p Model of BJT
10.6 Hybrid-p
It is essential to develop the small signal equivalent circuit of BJT for its use as an amplifier at high
frequency. Hence, development of hybrid-p model is taken up first before analyzing its frequency
response.
Condition 1 (VCB¢¢ = 0)
Out of three layers (emitter, base and collector), the resistivity of the base layer is very high w.r.t. other
two layers (emitter and collector). The resistivities of emitter and collector layers are identical, if not
exactly equal. In order to compare the three layers, the extra resistance of the base layer that makes it
very high w.r.t. the other two-layers is separated from the active portion of the base layer calling it the
base spreading resistance rbb¢. This is illustrated by Fig. 10.21 where in the B¢ denotes the active portion
of the base layer.
Figure 10.21 BJT representation

431
Since the conductivities sb<< sc < se, the base layer is thought of as having a resistance rbb¢ extra to
the resistances of the collector and emitter layers. The current transfer ratio a is defined as
DI C
a= (10.6.1)
DI E
VCB ¢ = K
Here, VCB¢ = K (a constant). This constant K can have a value equal to zero (0) also. Hence, the
simplest small signal model of the BJT is derived under the condition VCB¢ = 0.
Out of the total emitter current ie, only aie reaches the collector terminal. Thus, collector current
ic = aie is controlled by the short circuit current transfer ratio a and expressed as
ic = aie (10.6.2)
If we consider the emitter terminal as the input side and collector terminal as the output side, then the
simplest circuit model of the BJT has a current source aie controlled by the input (emitter) current ie.
Since the base-emitter junction is always forward biased, it works as a diode, i.e.
qVB ¢ E qVB ¢ E
h KT h KT
IE = I o (exp - 1) @ I o exp (10.6.3)
where, h = ideality factor
qVB¢E
DI E
=
q FG IJ
Io exp hKT =
q I I FG IJ
I E = E = E (for h = 1)
DVB¢E hKT H K hKT hVT VT H K
DVEB ¢ v KT V 26 ¥ 10-3 26
= eb ¢ = re = = T = = W (10.6.4)
DI E ie qI E IE IE I E (mA)
KT
where, VT = = thermal voltage = 26 mV at room temperature.
q
On input side, the emitter-base junction (diode) resistance re is dependent on the biasing current IE as
illustrated by Eqn. 10.6.4. Hence, the simplest ac model of the BJT is drawn as in Fig. 10.22.
Figure 10.22 Equivalent circuit with VCB¢ = 0
Figure 10.23 Depiction of depletion width under biased condition

432
Condition 2 (VCB¢¢ π 0)
We know that increasing VCB¢ (reverse bias) increases the depletion width across the collector-base
junction. Since the sb << se, almost whole depletion width extends in the base layer as indicated in
Fig. 10.23. The vertical dotted line near CBJ indicates depletion width for less reverse bias where as
solid line indicates the depletion width for higher value of reverse bias voltage. Thus, effective base
width of the BJT is decreased. This effect is also called base width modulation and also Early effect in
the honour of the scientist J. M. Early. Early effect leads to:
∑ Less chance of recombination and hence a increases with increasing |VCB¢|.
∑ Increase of concentration gradient increases both IC and IE. The decrease in effective base
width increases the diffusion of carrier gradient (concentration). This, in turn, increases both
collector and emitter currents. The less effective base width also lessens the recombination
probability of the carriers in the base layer that increases the collector current.
∑ Due to extremely large |VCB¢|, complete depletion of base layer takes place that causes the
voltage breakdown of transistor. This phenomenon is known as punch through or reach
through. Punch through differs from avalanche breakdown which takes place at a fixed voltage
between collector and base, and is not dependent on circuit configuration.
The increase in collector and emitter currents should be counter balanced such that the small signal
model derived for VCB¢ = 0 should also remain valid under the condition VCB¢ π 0. The increase in the
collector current is provided by a path in parallel to the current source aie by putting a voltage controlled
VCB¢ conductance. The value of this conductance is gcc = DIC/DVCB¢. The effect of VCB¢ on emitter
current is nullified by adding a voltage controlled VCB¢ current source in opposite to the direction of and
parallel to re as indicated in Fig.10.24.
ie = gevb¢e gcevcb¢ = (gevb¢e + gcevcb¢) (10.6.5)
Figure 10.24 Small signal equivalent circuit of BJT with VCB¢ π 0
Arranging the previous circuit in common emitter configuration and substituting Eqn. 10.6.5 in place
of ie in of Fig. 10.24 changes to Fig. 10.25. In Fig. 10.25, the value of ie is substituted in terms of the
voltages vb¢e and vcb¢ and the base spreading resistor rbb¢ is also included. Figs. 10.26 through 10.31 are
simplifications of Fig. 10.25 to result the circuit in the form of p-model.
The two current generators in parallel to gcc have been shown separately in Fig. 10.26.
The source gce vcb¢ between B¢ and E node has been replaced by putting the same source between B¢C
and CE nodes keeping the nodal equations the same before and after replacement as in Fig. 10.27.
Similarly, the source agevb¢e between node CB¢ has been replaced by putting the same source between
nodes EB¢ and CE.
433
Hence, hybrid-p equivalent circuit of BJT at low frequency is drawn as Fig. 10.30.
Figure 10.25
Figure 10.26
Figure 10.27
434
1 1 rcc
rb¢c = = = (10.6.6)
gb 'c g cc - (1 - a ) gce 1 - (1 - a ) gce rcc
Figure 10.28
Figure 10.29
Figure 10.30 Hybrid-p equivalent circuit of BJT at L.F.

435
p Model of BJT at High Frequency

10.6.1 Hybrid-p
We know that the high frequency transistors have thin base width that leads to higher base spreading
resistor rbb¢. The rb¢e is the forward biased base-emitter resistance @ 0.025hfe/IEQ at 300°C. Both junctions
have inbuilt depletion capacitances. The base-collector capacitance Cb¢c theoretically varies inversely
12 1/ 3
either as VCB (step graded) or VCB (linearly graded) depending on whether it is an alloy or a grown
junction transistor. The range of this capacitor is from 30pF in case of low frequency transistors to 1 pF
in high frequency transistors.
10.6.2 Transition/depletion Layer Capacitance CT

The formation of p-n junction exhibits inbuilt barrier potential that acts as reverse bias. In a reverse
biased p-n junction, the transition region from n-type to the p-type material may be thought of as charge
free region that acts like insulator or dielectric, while p-type and n-type materials having low resistance
on either side act as plates. This forms two parallel oppositely charged plates with dielectric in between
them. The bound donor atoms on n-side of the layer are positive, while bound acceptor atoms on p-side
of the layer are negative. The capacitance between these layers of bound charge is high because of the
fact that both Si and Ge have high dielectric constants ( e Si = 12, e Ge = 16). This capacitance is called
space charge capacitance or transition capacitance denoted as CT. The typical value of transition
capacitance is of the order 10pF to 1000pF. The parallel plate capacitor is expressed as
eA
CT = farad (10.6.7)
d
where, A = junction area
e = permitivity of semiconductor
d = depletion width
We know that the depletion width of p-n junction increases with increasing reverse bias, this
capacitance is voltage dependent and is expressed as
K
CT = (10.6.8)
(VD + VR )n
where, n = 1/2 or 1/3,
VD = depletion voltage
VR = reverse bias
K = constant
As expected, increasing the junction voltage, Vjun, widens the distance between the two plates (depletion
width) and reduces the capacitance.
In most low frequency transistors, another capacitance, i.e. the forward biased emitter-base junction
capacitance, called, the diffusion capacitance CD dominates the depletion or transition capacitance CTE.
Therefore, it becomes essential to differentiate between the transition and diffusion capacitances. The
emitter-base and collector-base transition capacitances are indicated as CTE and CTC and the diffusion
436
capacitance as CD = Cb¢e. Fig. 10.31 shows variation of transition capacitance of TIV308 Si varactor
diode against applied reverse bias VR.
Figure 10.31 Transition capacitance variation
10.6.3 Diffusion Capacitance CD

With forward bias the depletion width decreases on account of migration of holes to n-side and electrons
to p-side. Consequently, near the depletion region, accumulation of holes on n-side and accumulation of
electrons on p-side takes place. Thus, n-side has excess of holes as minority carriers and p-side has
excess of electrons as minority carriers after diffusion. This can also be approximated as a parallel plate
capacitor charged with diffused carriers. An electric field does exist between the two stored charges
that is maximum at the centre of the junction. If we increase the voltage by DV, the corresponding
change in the charge could be DQ and its ratio is defined as the capacitance CD
DQ
CD =
= diffusion capacitance (10.6.9)
DV
where, Q = charge hold by minority carriers and V is the applied forward bias.
The second effect is that with increasing forward bias, the slope of the impurity concentration versus
distance function increases. It also narrows the depletion width and increases the capacitance.
qV qV
hKT hKT
The diode current I = Io (exp - 1) @ Io exp (10.6.10)
qV
DI
=
q FG IJ
Io exp hKT =
q
I =
I FG IJ (10.6.11)
DV hKT H K hKT hVT H K
DQ D ( It ) DI I t
CD = = = t = t = farad (10.6.12)
DV DV DV hVT hrd
The diffusion capacitance is thus, proportional to the current flow through it. Here t = lifetime of the
carrier. If h =1 the t = rdCD = time constant indicating recombination of excess minority carriers. The
typical value of diffusion capacitance falls in the range of 0.1 mF to 1 mF. Thus, diffusion capacitance is
many times the transition capacitance. Thus, a p-n junction normally has two-types of capacitors
∑ Transition/space charge/barrier capacitance and
∑ Diffusion capacitance.
437
Similar to the reverse biased collector-base junction capacitors, the forward biased emitter-base
junction exhibits the inbuilt transition capacitance CT alongwith a diffusion capacitance Cb¢e. The diffusion
capacitance Cb¢e is dependent on the number of the charges trapped in the base region and hence, it
increases almost linearly with the quiescent emitter current IEQ. The CT is usually smaller than the Cb¢e.
Thus, the hybrid-p model of the BJT looks like the one shown in Fig. 10.32.
Figure 10.32
The useful model of BJT at high frequency, shown in Fig. 10.33, is called hybrid-p model. In this
figure point B¢ represents the active base portion of the junction whereas point B represents the external
base point of the base terminal. Hence, rbb¢ is the ohmic resistance between B¢ and B. The value of rbb¢
ranges from 5 W to 50 W. The value of rbb¢ is proportional to the base-width of the BJT. Therefore, the
base-width of the high frequency BJTs is small and hence, rbb¢ is less for high frequency BJTs.
VT 25 mV
rp = rb¢e = resistance of the base-emitter junction = =
I BQ I EQ / b
Cb¢c = Cm = Transition capacitance of reverse biased collector junction
Cb¢e = Cp = Diffusion capacitance of forward biased emitter junction
rb¢c = rm = feedback resistance parallel with Cb¢c
rce = reverse biased resistance of collector junction
Figure 10.33 Hybrid-p model of BJT

438
Typical values of hybrid-p model parameters are

Cb¢c = CTC = CTE = 0.5 pF, Cb¢e = Cp = 100 pF,
rp = 1 K, gm = 50 mS, rb¢c @ (100 MW) > XCb¢c
rce(100 K) >> hfe ¥ gp, rbb¢ = 50 W.
10.6.4 Output Conductance (gce)

It can be obtained at low frequency by considering input terminals of Fig. 10.34 open circuited, i.e.
ib = 0 as
Figure 10.34 Hybrid-p model of BJT at L.F.
ic = gce vce + gmvp +

vce v
= ce + gm
vce rpF I+ v ce
rp + rm rce r/p + rm
GH JK r/ + r
p m
=
vce Fv r v
+ gm ce p + ce
I
rce
GHrm rm
JK
= gce vce + gmrpgmvce + gmvce = {gce + (gmrp + 1)gm}vce
= {gce + (hfe + 1)gm}vce
ic
= hoe = gce + (hfe + 1)gm
vce
gce = hoe (hfe + 1)gm @ 10 mS (typical)
10.6.5 Feedback Conductance (gm)

This represents the Early feedback voltage source (fT/3) in the hybrid-p model. The feedback voltage
with open circuited input in Fig. 10.34 is
vce rp v r
vp vb ' e = open
= @ ce p
r/p + rm rm
The reverse voltage ratio is written as hre =

vp Fv r
= ce p
I1 =
rp
vce
GHrm
JK v
ce rm
439
rp 1K
rm = = = 100 MW
hre 0.1 ¥ 10-4
A typical n-p-n transistor has fT between 100 MHz to 1 GHz with a common value of 400 MHz. The
hybrid-p model is useful up to approximately fT/3. The hybrid-p model parameters can be expressed in
terms of hybrid model as in Fig. 10.35.
The BJT has an input resistance specified by the manufacturer as hie. It is expressed in terms of two
resistances, i.e
hie = rbb¢ + rb¢e = rbb¢ + rp = 1 KW (10.6.13)
Figure 10.35 Simplified hybrid-p model of BJT
The low frequency hybrid-p model of BJT is shown in Fig. 10.36.
Figure 10.36 Low-frequency hybrid-p model of BJT
The rbb¢ is called the base spreading resistance and is usually of the order of 5 W to 50 W. The input
resistance of the transistor is of the order of 250 W to 8 KW. Hence, one can safely assume that
hie = rbb¢ + rb¢e @ rp (10.6.14)
25 mV 25 mV 25 mV ¥ h fe
rb¢e = rp = = = (10.6.15)
I BQ I EQ / h fe I EQ (mA)
gm =
DI C
=
F ∂I I F ∂I I = h
C B
¥ gp (10.6.16)
DVBE GH ∂I JK GH ∂V JK
B BE
fe

h fe I EQ
gm = = 40IEQ (10.6.17)
0.025h fe
440
10.6.6 b)
Short Circuit Current Amplification Ratio (b
At high frequency the reactance of Cm is much smaller than the resistance rm and hence, it is assumed to
be open, i.e. rm >> XCm and Fig. 10.34 reduces to Fig. 10.37.
Figure 10.37
At node B¢ in Fig. 10.37 ib = (gp + SCp) vp + (vp 0) SCm

ib = {gp + S(Cp + Cm)}vp (10.6.18)
At collector node gmvp + isc = (vp 0)SCm
isc = (gm SCm) vp (10.6.19)
Substituting vp from equation of ib in equation of isc results in
rp
isc = ic = -( gm - SCm ) ib
1 + S(Cp + Cm )rp
-isc i ( gm - SCm )rp gm (1 - SCm / gm )rp
= c =b= =
ib ib 1 + S(Cp + Cm )rp 1 + S(Cp + Cm )rp
g (1 - jw / w z )rp b (1 - jw / w z )
= m = o (10.6.20)
1 + jw / w b 1 + jw / w b
gm 1
where, wz = , wb = , b = gmrp (10.6.21)
Cm rp (Cp + Cm ) o
1
At frequencies where this model is valid gm >> , Eqn. 10.6.20 reduces to
SCm
ic gm rp bo bo
=b= - =- =- (10.6.22)
ib 1 + S(Cp + Cm )rp 1 + S(Cp + Cm )rp 1+ j
w
wb
1
where wb = and b0 = low frequency value of b (10.6.23)
(Cp + Cm )rp
441
The positive sign of b indicates that for short circuit, the collector current is forced to sink to the
ground.
Equation 10.6.25 reveals that the short circuit current ratio b varies with frequency and at f = 0 it is
bo as indicated in Fig. 10.38. The b cut-off frequency fb is the frequency where the dc value of bo
becomes 0.707b. The transition frequency fT is the frequency at which the short circuit current transfer
ratio b in CE configuration becomes unity, called unity gain bandwidth wT.
bo bo bo
b(wT) = 1 = - = = (10.6.24)
1 + jw T / w b 1 + (w T / w b ) 2
1 + ( fT / fb )2
fT
= b 2o 1 @ bo and fT = = fb bo (10.6.25)
fb
bo rp gm gm
fT = bo fb = = = (10.6.26)
2p (Cp + Cm )rp 2p (Cp + Cm )rp 2p (Cp + Cm )
The fT is called gain-bandwidth product.
The current amplification factor in CB configuration at high frequency is described as
ao
a= (10.6.27)
f
1+ j
fa
where ao fi low frequency dc amplification factor of common base transistor
fa fi common base cut-off frequency
At f = fa, the magnitude of a will fall by 3 dB = 0.707ao
Similarly, the current amplification factor in common emitter configuration of the transistor is expressed
as
ao a o / (1 + jf / fa ) ao
b= = =
1-ao 1 - a o / (1 + jf / fa ) (1 - a o )(1 + jf / (1 - a o ) fa )
bo bo
= = (10.6.28)
1 + jf / (1 - a o ) fa 1 + jf / fb
where FG
fb = (1 ao)fa = 1 - bo IJ
fa =
fa
(10.6.29)
H 1 + bo K 1+ b o
or fa = (1 + bo)fb (10.6.30)
fT = fbbo = (1 ao)fabo =
FG b IJ f
o
= a o fa (10.6.31)
H1 + b K o
a
The fT is also called the gain-bandwidth product and fT is very close to fa but less than fa.
Thus, fb < fT < fa.
442
Figure 10.38 Plot of a and b versus frequency
A typical n-p-n transistor has fT between 100 MHz to few GHz with a common value of 400 MHz.
The hybrid-p model is useful up to approximately fT/3.
10.6.7 Common Emitter Amplifier

The total parasitic capacitances present across the input and output terminals can be found out using the
Miller Theorem. The feedback impedance Z connected in Fig. 10.39 can be reflected across the input
and output terminals as in Fig. 10.40.
The simplified hybrid-p equivalent circuit model of common emitter amplifier depicted in Fig. 10.33
is drawn in Fig. 10.39 with the assumption rce = very large @ •, rm >> 1/jw Cm.
Figure 10.39 CE amplifier hybrid-p model at H.F.
The feedback capacitor Cm is reflected at the input and output terminals using Millers theorem.
Feedback impedance reflected across the input terminals due to 1/jw Cm is
1
Zi = (10.6.32)
jw Cm (1 - A)
Thus, value of capacitances reflected across input and output terminals are
CM = (1 A)Cm = (1 + gmRLeq)Cm (RLeq = effective load resistance) (10.6.33)
Co = Cb¢c = Cm (10.6.34)
where A = gmRLeq = mid-band gain of the amplifier
443
This small value of capacitance (5 pF) in parallel with a low resistance typically RL = 2 K has a
negligible time constant (5 ¥ 1212 ¥ 2 ¥ 103 = 10 ¥ 109 = 10ns) w.r.t. input time constant and can be
ignored unless working into a capacitive load.
Since rm and rce are very large values of resistance, they are assumed to be open circuited.
where Ci = (1 + gmRL)Cm + Cp + Csi (10.6.35)
The equivalent circuit shown in Fig. 10.39 has two parts as in Fig. 10.40.
∑ input section, and
∑ output section
Both input and output sections of Fig. 10.40 can be broken into three parts
∑ Mid frequency circuit
∑ Low frequency circuit and
∑ High frequency circuit.
Figure 10.40 Simplified hybrid-p model of RC coupled amplifier
10.6.8 Mid Frequency Response of CE

Fig. 10.40 is simplified as Fig. 10.41 neglecting both coupling capacitors C1 and C2 and all high frequency
capacitors Cp and Cm.
RC
iL = - gm vp (10.6.36)
RC + RL
vs rp
vp = ibrp = (10.6.37)
rs RB + rbb' + rp
vp rp
= (10.6.38)
vs rs RB + rbb¢ + rp
Figure 10.41 Mid frequency equivalent circuit of RC coupled amplifier

444
vo = vL = iLRL = - gm vp
FG R R IJ C L
(10.6.39)
HR +R K C L
Avs =
vo F v I Fv Io
= G J G J = -g G
F R R IJ F
p C L rp I (10.6.40)
vs Hv K Hv K p H R + R K GH r
s
m
C L s RB + rbb¢ + rp JK
10.6.9 Low Frequency Response of CE
For low frequency analysis, the equivalent circuit of Fig. 10.40 is redrawn as Fig. 10.42 neglecting high
frequency capacitors CM and Cm = Co. Now the input and the output equivalent circuit at low frequency
looks the same in its configuration. Here, the bypass capacitor has been assumed to be short circuited
even at L.F.
The analysis for both input and output sections will exactly be identical to each other. From the input
section in Fig. 10.42
Figure 10.42 L.F. hybrid-p model of RC coupled amplifier
b
iL = - g m vp g 1
RC
b
= - g m vp gFGH R R+ R IJK
C
1
1
RC + RL + C 1- j
L
jwC2 wC2 RC + RLb g
b gFGH R R+ R IJK 1w
= - g m vp C
L1
(10.6.41)
1- j
C L
w
vL = i R = b- g v gG
F RR I 1 C L
L L
H R + R JK 1 - j w
m p
C L L1
w
vL
= -g G
F RR I 1 C L
(10.6.42)
vp H R + R JK 1 - j w
m
C L L1
w
445
1
where wL1 =
C2 ( RC + RL )
vs rp vs rp
vp = =
1 Ê 1 ˆ
rp + rbb¢ + rs + (rp + rbb¢ + rs ) Á1 +
jw C1 Ë jw C1 (rp + rbb¢ + rs ) ˜¯
vp rp
= (10.6.43)
+ r )F1 - j
vs w I L2
(rp + rbb¢ s
H wK
1
where wL2 = (10.6.44)
C1 (rs + rbb¢ + rp )
Hence, overall voltage-gain
= Avs =
F v I FG v IJ = FG v IJ
L p L
GH v JK H v K H v K
p s s
F R R I FG 1 IJ ¥
= - gm GH R + R JK GG 1 - j w JJ r r rr F j w I
C L
L1
p
L2
(10.6.45)
C L
H w K ( + + )H1 - w K p bb ¢ s
F R R I FG rp IJ 1
= - gm GH R + R JK H r + r + r K F w I F 1w I
C L
L1 L2
C L p
H1 - j w K H1 - j w K
bb' s
Av( mid)
= (10.6.46)
F 1- j
w L1 IFw
1 - j L2 I
H w KH w K
where Av(mid) = - gm
FG R R IJ FG r
C L p IJ (10.6.47)
HR + R K Hr +r
C L s bb' +r Kp
If C1 = C2 = 10 mF, RC = RL = 1 K, rs = 10 W, rbb¢ = 50 W, rp = 1 K, then
1 1 100
wL1 = = = = 50 rad/s
b
C2 RC + RL g
10 ¥ 10-6 (1 K + 1 K) 2
1 1
wL2 = = -6
= 100 rad/s
C1 (rs + rbb¢ + rp ) 10 ¥ 10 (0.010 K + 0.050 K + 1 K)
The plot of Eqn. 10.6.46 looks like the one shown in Fig. 10.43. Hence, its effective lower cut-off
frequency = 100 r/s.
446
Figure 10.43 Plot of Avs versus frequency
10.6.10 High Frequency Response of CE

For high frequency response, the circuit of Fig. 10.39 reduces to Fig. 10.44. At high frequency the
reactance offered by the coupling capacitor C1 is so low that it is assumed to be short-circuited. On the
contrary, the high frequency model capacitor Ci becomes effective at high frequency. Its reactance
starts decreasing with increasing frequency and ultimately becomes short circuit at f = •. Hence, the
input voltage vi becomes zero and so does the output voltage. Here once again the input and output
sections look like the same as drawn in Fig. 10.40.
Figure 10.44 Hybrid-p model of RC coupled amplifier
From input section of Fig. 10.44 vp is obtained as

rp ib rp ib
vp = = (10.6.48)
1 + jwCi rp 1 + jw / w H 1
where wH1 = 1/Cirp (10.6.49)
Figure. 10.44 reduces to Fig. 10.45 and from this circuit
vs vs (1 + jw Ci rp )
ib = =
rp rs RB + rbb¢ + rp + jw Ci rp ( rs RB + rbb¢ )
rs RB + rbb¢ +
1 + jw Ci rp
447
Figure 10.45 Simplified hybrid-p model of RC coupled amplifier
rp ib Ê rp ˆ ÏÔ vs (1 + jw Ci rp ) ¸Ô
vp = = Á Ì ˝
1 + jw Ci rp Ë 1 + j Ci rp ˜¯
w ÔÓ rs RB + rbb ¢ + rp + jw Ci rp (rs RB + rbb ¢ ) Ô˛
vp rp
=
vs rs RB + rbb¢ + rp + jw Ci rp (rs RB + rbb¢ )
Ê rp ˆ 1
= Á
Ë rs RB + rbb¢ + rp ˜¯ w Ci rp ( rs RB + rbb¢ )
1+ j
rs RB + rbb¢ + rp
Ê rp ˆÊ 1 ˆ
= Á (10.6.50)
Ë rs RB + rbb¢ + rp ¯˜ ËÁ 1 + jw Ci {(rs RB + rbb¢ ) rp }¯˜
- g mvp RL
vo = (Here RL = RL||RC)
1 + jw Cm RL
vo - g m RL
=
vp 1 + jw Cm RL
Av(H.F.) =
vo v
= o
F I FG v IJ p
vs vp GH JK H v K s
Ê - g m RL ˆ Ê rp ˆ 1
= Á ˜Á ˜
Ë 1 + jw Cm RL ¯ Ë rs RB + rbb ¢ + rp ¯ 1 + jw Ci {( rs RB + rbb ¢ ) rp }
Ê 1 ˆÊ - g m RL rp ˆÊ 1 ˆ
= Á ˜Á ˜ Á
Ë 1 + jw Cm RL ¯ Ë rs RB + rbb¢ + rp ¯ Ë 1 + jw Ci {( rs RB + rbb¢ ) rp }˜¯
=
1 F gm RL rp I 1 =
Av( mid )
(10.6.51)
1+ j
w GH r
s RB + rbb ¢ + rp JK 1 + j w FG1 + j w IJ FG1 + j w IJ
w H3 w H2 H w KH w K H2 H3
448
gm RL rp 1 1
where Av(mid) = , wH2 = , wH3 = (10.6.52)
rs RB + rbb¢ + rp Ci {(rs RB + rbb¢ + rp ) rp } Cm RL
If RL = 1 K = RC, RB = 10 K, rs = 10 W, rbb¢ = 50 W, rp = 1 K, Cm = 0.5 pF,
Cp = 100 pF, gm = 50 mS, then
Ci = Cp + (1 + gmRL)Cm = 100 + (1 + 50 ¥ 0.5)0.5
= 100 + 26 ¥ 0.5 = 100 + 13 = 113 pF
(rs| |RB + rbb¢ + rp)| |rp = (rs + rbb¢ + rp)| |rp = rp| |rp = 0.5 K
1 1012 10 9
wH3 = = 3
= = 4 Grad/s
Cm RL 0.5 ¥ 0.5 ¥ 10 0.25
1 1 10 9
and wH2 = = =
Ci {(rs + rbb ¢ + rp ) rp } Ci (rp rp ) 113 ¥ 0.5
9
10
=
= 17.7 Mrad/s
56.5
The plot of Eqn. 10.6.52 is depicted as in Fig. 10.46 with wH3 = 4 Grad/s >> wH2 = 17.7 Mrad/s.
Since the gain goes down by 3 dB at frequency fL1 itself, the lower 3 dB cut-off frequency from
Fig. 10.46 is fL = fL2. Similarly the higher cut-off frequency from Fig. 10.46 is fH = fH2. Though the
gain of the RC coupled amplifier is not constant at all frequencies even in the range fL to fH, yet it is
assumed to be constant as the variation is limited to 3 dB and hence it is called mid band gain which
remains constant over the bandwidth fH2 fL2. The concept of 3 dB comes from the half power point.
At these frequencies the power becomes half. Now, let us analyze for the current gain,
iL =
(- gmvp ) RC RL1
=
- g m vp RL
=
- gm vp RL
, wH3=
1
= 4 Grad/s
1 + jw Cm RC RL1 1 + jw Cm RL w Cm RL
1+ j
w H3
Figure 10.46 Plot of Avs versus frequency

449
iL - gm RL
= (10.6.53)
vp w
1+ j
w H3
vp rp rp
From Eqn. 10.6.48 = = (10.6.54)
ib 1 + jw Ci rp w
1+ j
w H1
Combining Eqns. 10.6.53 and 10.6.54 yield
i - gm RL
Ai = L = (10.6.55)
ib FG
1+ j
w IJ FG
1+ j
w IJ
H w H1 KH w H3 K
1 1 1
wH1 = = =
Ci rp {Cp + (1 + gm RL )Cm } rp {100 pF + (1 + 50 mS ¥ 0.5 K) 0.5 pF}1 K
10 9
= = 8.85 Mrad/s
113
1 1
wH3 = = = 4 Grad/s
Cm RL 0.5 ¥ 10 ¥ 0.5 ¥ 10 3
-12
Thus, the current gain goes down by 3 dB at much lower frequency w.r.t the voltage gain at
2 Mrad/s only.
Example
If mid frequency power is 10W, obtain power at half power points.
Power Gain = AP = 10log10 (Po / Pi), and if Po / Pi = 10, then AP = 10 dB
Hence power at 3 dB down i.e. at (10 3) dB = 7 dB can be expressed as
10log10 (Po / Pi) = 7 dB and Po / Pi = Anti log(0.7) = 5
Thus, the power gain becomes half, i.e. 5 from 10, at the boundary of mid-band gain and lower
cut-off and higher cut-off frequencies.
10.7 Effect of Bypass Capacitor in CE

A simple circuit of RC coupled amplifier to show the effect of bypass capacitor is shown in Fig. 10.47
Figure 10.47 RC coupled amplifier with bypass capacitor Figure 10.48 L.F. response
450
RE v
From Fig. 10.47 vb = rbb ib + vp + (gm vp + ib) and ib = p (10.7.1)
1 + SCE RE rp
Hence vb = rbb¢
vp
+ vp +
RE FG
v
gm vp + p
IJ
rp 1 + SCE RE Hrp K
=
|RS r + 1 + R FG g + 1 IJ |UV v
bb ¢ E
m
1 + SC R H r K |W
p
|T r
p E E p
R| r + r + R F 1 + g r I U|Vv
=S bb ¢ p E m p
|T r 1 + SC R GH r JK |W
p E E p
p
rbb ¢ + rp + RE (1 + gm rp ) + SCE RE (rbb ¢ + rp )

= vp (10.7.2)
rp (1 + SCE RE )
vp rp (1 + SCE RE )
or =
vb rbb ¢ + rp + RE (1 + gm rp ) + SCE RE (rbb ¢ + rp )
rp (1 + jw / w 11 )
= (10.7.3)
{rbb ¢ + rp + RE (1 + gm rp )}(1 + jw / w 12 )
rbb¢ + rp + RE (1 + gm rp )
where w11 = 1/RECE and w12 =
CE RE (rbb¢ + rp )
=
1
1+ E
RS
R (1 + gm rp ) UV (10.7.4)
CE RE (rbb ¢ + rp )
T W
Thus w11 < w12 and vo = gmvpRL
vo v v - gm rp RL (1 + jw / w 11 )
or, = o ¥ p = (10.7.5)
vb vp vb {rbb ¢ + rp + RE (1 + gm rp )} (1 + jw / w 12 )
vo - gm rp RL v - gm RL rp
= and o = (10.7.6)
vb w =0
rbb ¢ + rp + RE (1 + gm rp ) vb w =•
rbb ¢ + rp
If gm = 50 mS, rp = 1 K, RL = 0.5 K, rbb¢ = 0.050 K, RE = 1 K, then
w11 = 1/RECE = 1/1 K ¥ 100 ¥ 106 = 10 rad/s
and w12 =
1
1+ E
RS
R (1 + gm rp )
= 1+
UV
1 K(1 + 50)
10 rad/s = 520 rad/s
CE RE (rbb ¢ + rp )
T 1K W
Hence the plot of Eqn. 10.7.5 looks like Fig. 10.48.
"#
1. Calculate the value of C1 such that the

lower 3dB frequency of the circuit shown
in Fig. 10.49(a) becomes 5rad/s.
Soution:
VT VT
hie = = ,
I BQ I EQ h fe
5 0.7 = 1 K ¥ IB + 1 K ¥ IE Figure 10.49(d) Gain versus frequency plot
I
= 1 K ¥ E + 1 K ¥ IE @ 1 K ¥ IE
b +1 25 mV
hib = = 5.8 W, hie = hfehib
IEQ = 4.3 mA 4.3 mA
= 50 ¥ 5.8 = 0.290 K
Its ac circuit is drawn as in Fig. 10.49(b).
as Fig. 10.49(c) with component con-
nected at emitter side reflected to the base
side.
,./
ic = hfeib
vs
ib =
1 1K ¥ (50 K + 0.290 K)
Figure 10.49(a) 10 + +
SC1 1K + 50 K + 0.290 K
Ê 1K ˆ
ÁË 50 K + 0.290 K + 1 K ˜¯
As 0.290 K << 50 K, it is neglected here in

calculation. Hence, the above equation re-
duces to
vs Ê 1K ˆ
ib =
Figure 10.49(b) ac circuit 1 1K ¥ (50 K) ËÁ 50 K + 1K ¯˜
+
SC1 1K + 50 K
vs Ê 1K ˆ
=
1 1K ¥ (50 K) ÁË 51K ˜¯
+
SC1 51K
vs Ê 1K ˆ
@ Á 51K ˜¯
1
Figure 10.49(c) Equivalent circuit + 1K Ë
SC1
"#
vs ¥ 1K Solution:
vL = 50 Kib = 50 K Its ac circuit is drawn as in Fig. 10.50(b).
Ê 1 ˆ 1
ÁË1K + SC ˜¯ 51K Its small signal equivalent circuit is drawn
1 as Fig. 10.50(c) with component con-
vs ¥ 1K nected at emitter side is reflected to the
Svs
= = base side.
1 ( S + w1)
1K +
SC1
vL S
=
vs (S + w 1 )
where w1 = 3dB frequency of the ampli-
fier. Its voltage gain plot looks like the one
shown in Fig. 10.49(d).
1
w1 = wL =
1KC1
Figure 10.50(a)
Since, the 3dB frequency
1
= 5 rad/s =
1 KC1
1
C1 = = 200 mF
1K ¥ 5
2 Calculate value of C1 and C2 in Fig. 10.50(a)
for double pole of its voltage gain AV = vo / vi
at w = 5rad/s. Also calculate the value of C1 Figure 10.50(b) ac circuit
= C2 for its 3 dB frequency to fall at 5rad/s.
Since hie << 50 K, it is neglected for calcu- The loop equations are written as
lations and hence, the circuit of
Fig. 10.50(c) reduces to Fig. 10.50(d).
È10
/ W + 1 K + 10 K/S -1 K ˘ È i1 ˘
The circuit of Fig. 10.50(d) is further sim-
plified as Fig. 10.50(e).
Í
Î -1 K 1/ K + 500 K + 5 M/S˙˚ ÍÎi2 ˙˚
Èv ˘
= Í s˙
Î0˚
"#!
Figure 10.50(d) Simplified equivalent circuit
Figure 10.50(e)
Further simplified equivalent circuit
Ê 1 ˆÊ 50 ˆ S2
D = Á1 K + 500 K + 1 M =
Ë SC1 ˜¯ ÁË SC2 ˜¯ ( S + w L1 )( S + w L 2 )
500 K 50 K 50 1 1
= 500 M + + + 2 1 M. where wL1 = , wL2 =
SC1 SC2 S C1C2 1 KC1 10 KC2
Since double pole exist at w = 5rad/s
Ê 1 ˆÊ 50 ˆ
@ Á1 K + ˜ Á 500 K + 1
Ë SC1 ¯ Ë SC2 ˜¯ = 5,
1KC1
1K Ê 1 ˆ 500 K Ê 50 ˆ
= ÁË S + 1KC ˜¯ S ÁË S + 500 KC ˜¯ 1
S 1 2 C1 = = 0.2 mF = 200 mF and also
1K ¥ 5
1 1
1K + vs C2 = = 0.02 mF = 20 mF
SC1 10 K ¥ 5
1K 0 1K ¥ vs Its voltage gain versus frequency plot is
i2 = =
D D shown in Fig. 10.50(f).
1Kvs (b) As w1 = w2, the 3dB frequency will be
vo = 500 Ki2 = 500 K determined by the value of capacitance for
D
which C is more i.e. C = 200 mF.
500 K ¥ 1K ¥ vs ¥ S 2
=
Ê 1 ˆÊ 1 ˆ
ÁË S + ˜ Á S+ 1K ¥ 500 K
1KC1 ¯ Ë 10KC2 ˜¯
vo S2
AV = =
vs Ê 1 ˆÊ 1 ˆ
ÁË S + 1KC ˜¯ ÁË S + 10 KC ˜¯
1 2 Figure 10.50(f) Gain versus frequency plot
"#"
3. Obtain the lower 3dB frequency and its volt-

age gain A = vL/vs plot for Fig. 10.51(a).
Its ac and small signal equivalent circuit are
drawn as in Fig. 10.51(b) and Fig. 10.51(c)
with component connected at emitter side
reflected to the base side.
Solution:
The loop equations are written as
È10 W + 1 K + 10 K/ S -1 K ˘ Figure 10.51(a)

Í -1 K 1 K + 500 K + 5M/S˙˚
Î
LMi OP = LMv OP
1 s
Ni Q N 0 Q
2
1K 500 K
D∫ ( S + 10) ( S + 10)
S S
1 K ¥ 500 K
= 2
(S + 10)2
S Figure 10.51(b) ac circuit
10 K
1K + vs
S
1 K 0 1K
i2 = = (vs )
D D
"##
1K
vo = 500 Ki2 = (500 K (vs )
D
500 K ¥ 10 Kvs S 2 vs
= =
500 K ¥ 1 K( S + 10) 2 ( S + 10 ) 2
S2
Figure 10.51(e) Av versus frequency plot
v S2
Av = o =
vs ( S + 10) 2 4. Derive and plot the |Ai|. Find out the 3dB
frequency from the plot for Fig. 10.52(a).
Its plot looks like the one shown in
Fig. 10.51(e).
as in Fig. 10.52(b).
Figure 10.52(a)
Figure 10.52(b) ac circuit
20 K ¥ 2 M 2M 1 K( S + 2 K)
Z2 = = and Z1 = =
20 KS + 2 M S + 100 S + 100
2M Z1| |200 K =
1K +
S + 100 200 K ¥ 1 K( S + 2 K)
1 KS + 100 K + 2 M 1 KS + 2 M =
= @ 200 KS + 200 K ¥ 100 + 1/ KS + 2/ M
S + 100 S + 100
"#$
200 K ¥ 1 K( S + 2 K) 200 K ¥ 1 K( S + 2 K) 1 K( S + 2 K)
= =
200 KS + 20 M 200 K( S + 100) ( S + 100)
20 Kis 200 K( S + 100)i1

i1 = =
100 K ( S + 2 K)1 K 200 K( S + 100) + ( S + 2 K)1 K
20 K + +
S S + 100 Since 200 KS >> 1 KS, and 20 M >> 2 M,
now ib reduces as
20 KS (S + 100)is ib = i1
=
20 KS ( S + 100) + 100 K( S + 100)
(100 ¥ 1 K)ib 50 Sib
+ 1 K(S + 2 K)S iL = =
1M S + 25
2K+
20 S
20 KS ( S + 100)is
= 2
20KS + 2 M S + 100
/ KS 50 Si1
=
S + 25
+ 10 M + 1/ KS 2 + 2 MS
20 KS ( S + 100)is Ai =
FG i IJ FG i IJ
iL
=
L 1
=
20 KS 2 + 4 MS + 10 M
i sH i KH i K
1 s
As 100KS << 4MS, and 1KS2 << 20KS2, i1

F -50 S IJ F S ( S + 100 ) I
=G
now reduces to H S + 25 K GH S + 200 S + 500 JK
2
20KS ( S + 100) is -50 S 2 ( S + 100 )

i1 = @
20 K( S 2 + 200 S + 500) ( S + 2 . 5 ) ( S + 25 ) ( S + 197 . 5 )
Its plot is shown in Fig.10.52(d).
S ( S + 100 ) i s
=
S 2 + 200 S + 500
i1 S ( S + 100 )
=
is S 2 + 200 S + 500
200Ki1
ib =
( S + 2 K)1 K
200 K + Figure 10.52(d) Gain versus frequency plot
S + 100
"#%
5. Obtain the vo/is plot and determine the

value of the capacitor C1 in Fig. 10.53(a)
for w3dB = 10 rad/s.
Solution:
Figure. 10.53(b) is the ac circuit of Fig.
10.53(a). The small signal equivalent circuit
of Fig. 10.53(b) is drawn as Fig. 10.53(c)
Figure 10.53(a) by reflecting emitter side to the base side.
Figure 10.53(d) Simplest equivalent circuit
vo = 100ib ¥ 1 K vo = 100 Kib

500 K | | 11 K = 10.8 K @ 11 K FG -100KS IJ
= 100 K
ib =
50 Kis H S + 1 / 61KSC K 1
1 vo
50 K + + 11 K -100KS
SC1 =
is S + 1 / 61KSC1
50 K ¥ Sis
= vo
Ê 1 ˆ -100 KS
61K Á S + =
Ë 61KC1 ˜¯ is S + 1 / 61KSC1
Sis 1
= Since 3 dB frequency = 10 rad/s =
1 61KC1
S+
61KC1
"#&
1 10 -6 vo = 100Kib
C1 = = = 1.4 mF
610 K 0 . 61 Ê 100 K ¥ 3.5 ˆ FG S IJ
= Á
Its plot is shown in Fig. 10.53(e). Ë 103.5 ¥ 4.5 K ˜¯ H S + 1/ 4.5KC K
1
0.75Svs 0 . 75 Sv s
= =
1 S+w1
S+
4.5KC1
1
where w1 =
4.5KC1
Figure 10.53(e) vo/vi versus frequency plot
6. Find vo / vs and select proper value of ca-

pacitor C1 for the 3 dB frequency of the
amplifier shown in Fig. 10.54(a) to occur
at 10 rad/s.
Solution:
Figure 10.54(b) is the ac circuit of Fig.
10.54(a). The small signal equivalent circuit
of Fig. 10.54(b) is drawn as Fig. 10.54(c).
Here, hie = 580 W << 100 K. Hence, it is Figure 10.54(a)
neglected for calculations.
vs Ê 3.5 K ˆ
ib = ÁË 103.5 K ˜¯
1
1K + + 3.5 K
SC1
3.5 Svs
=
Ê 1 ˆ
103.5 Á S + 4.5 K
Ë 4.5KC1 ˜¯
3.5Svs Figure 10.54(b) ac circuit
=
FG
465.75 S +
1 IJ
H 4.5KC1 K

"#'
Figure 10.54(d) vo / vs versus frequency plot

Figure 10.55(a)
1 10 -4
C1 = =
4.5 K ¥ 10 4.5
= 0.222 ¥ 104 = 22.2 mF

Its plot is shown in Fig. 10.54(d).
7. Plot the variation in the current gain for the
circuit shown in Fig. 10.55(a).

Solution: LMi OP
s
The ac circuit of Fig. 10.55(c) is drawn as
= M0P
Fig. 10.55(b). The small signal equivalent
circuit of Fig. 10.55(d). MN 0 PQ
v1 11
. -0.1 0
ib = = 1 mSv1
1K D = -0.1 0.2 + 0.01S -0.110 -3
hfeib = 100 ¥ 103vi 100 -0.1 11
.
= {1.1(0.22 + 0.011S 0.01)
LM 11. - 0.1 0 OP v1 LM OP
-3 + 0.1 (0.11 + 10)}103
MM-0.1 0.2 + 0.01S -0.1 10 v2
PP MM PP = 0.0121(S+100)103
N100 -0.1 11
. Q v3 N Q
"$
- ( S + 20 )10 -3 i s
=
D
v3 - ( S + 20)is
iL = =
1K 0.0121( S + 100)1K
- 0.083( S + 20)i s
=
Figure 10.55(e) Current gain versus frequency ( S + 100)
plot - 0.083( S + 20)
Ai =
S + 100
1.1 0.1 is Its plot is given in Fig. 10.55(e).
0.1 0.2 + 0.01 S 0 103 8. Obtain the 3 dB frequencies of a single
100 0.1 0 stage RC coupled amplifier shown in Fig.
v3 = 10.56(a) with rs = 0.6 K, rbb = 0.1 K, rp =
D
0.9 K, Cp = 20 pF, Cm = 2 pF, and gm
= 50 mS.
( 0 . 01/ - 20 - S )10 -3 i s
=
D
Figure 10.56(a)
"$
Figure 10.56(c) Simplified hybrid-p model
Figure 10.56(d) Simplified circuit
Solution: FG r IJ
0.94vs p
Coupling capacitors will behave as short H 1 + jw C r K
i p
circuited at high frequencies and hence vp =
rp
Fig. 10.56(b) simplifies to Fig. 10.56(c) at RB¢ + rbb¢ +
1 + jw Ci rp
high frequencies. Applying Thevenins
theorem to left of dotted line yields 0.94vs rp
=
v s RB v s 8. 9 ( RB¢ + rbb¢ ) (1 + jw Ci rp ) + rp
voc = = = 0.94vs , 0.94vsrp
rs + R B 9.5 =
RB¢ + rbb¢ + rp + ( RB¢ + rbb¢ ) jw Ci rp
80 K ¥ 10 K
RB = 80 K| |10 K = = 8.9 K 0.94vs rp
90 K =
( RB¢ + rbb¢ + rp )
rs R B 0.6 ¥ 8.9 K
RB¢ = = = 0.56 K Ê ( RB¢ + rbb¢ ) w Ci rp ˆ
rs + R B 9.5 ÁË1 + j R ¢ + r + r ˜¯
B bb ¢ p
RB | | rs + rce = 0.56 K + 0.1 K = 0.66 K
"$
0.94 vs rp = 0.0296 ¥ 10 9 = 29.6 Mr/s

=
FG
( RB¢ + rbb¢ + rp ) 1 + j
w IJ vo =
g m vp RL
=
g m vp RL
H w H1 K 1 + jwC o R L
1+ j
w
RB¢ + rbb¢ + rp w H2
wH1 =
Ci ( RB¢ + rbb¢ ) rp 1 1
wH2 = = =
0 . 56 + 0 .1 + 0 . 9 Co RL Cm RL
= -12
88 . 7 ¥ 10 ( 0 . 56 + 0 .1 ) 0 . 9 ¥ 10 3 1
-12
1. 56 2 ¥ 10 ¥ 0.66 K
=
88 . 7 ¥ 10 -12
¥ 0 . 66 ¥ 0 . 9 ¥ 10 3
= 0.75 ¥ 10 9 = 750Mr/s
1. 56 The higher 3dB frequency = 29.6 Mr/s
= -9
52 . 7 ¥ 10
For lower 3 dB frequency calculation, Fig. 10.56(b) simplifies to Fig. 10 56(e).
Figure 10.56(e) Equivalent circuit for low frequency analysis
Figure 10.56(e) is further simplified to Fig. 10.56(f) taking parallel combination of RB and rbb' + rp
Figure 10.56(f) Simplified equivalent circuit for low frequency analysis
vp =
vs FG rp RB IJ R 'B =
8.9 ¥ 1 K
= 0.89 K
1 HR + rbb¢ + rp K 9.9
rs + + RB¢ B
jw C1 1
where wL1 =
C1( rs + RB¢ )
=
vs F rp RB I
FG
( rs + RB¢ ) 1 - j
w L1 IJ GH R B + rbb¢ + rp JK
H w K
"$!
1 10-4 10 -6
= -6 gm = = = 0.4 ¥ 106 S
10 ¥ 10 (0.6 + 0.89) K 0.25 K 2.5
1000 gce = hoe (1 + hfe)gm
= = 67 rad/s
10 ¥ 1. 49 = 4 ¥ 106 (1 + 100) 0.4 ¥ 106
g mvp RC RL = 4 ¥ 106 40 ¥ 106
vo =
1
RC + RL + = 36 ¥ 106 S
jw C2
h fe ¥ gp gm
g mvp RC RL Cp + Cm = =
= 2p f T 2p f T
Ï 1 ¸
( RC + RL ) Ì1 - j ˝ 0.4
Ó w C2 (RC + RL ) ˛ =
2 p ¥ 50 ¥ 10 6
g mvp RC RL
= 0.4
Ï w ¸
( RC + RL ) Ì1 - j L 2 ˝ = 8
= 0.127 ¥ 108 = 1270 pF
Ó w ˛ p ¥ 10
1 Cp = 1270 pF Cm
where wL2 =
C2 (RC + RL ) = 1270 pF 2 pF = 1268 pF.
1 10. If mid-band current gain and frequency of
= -6 a BJT amplifier in question 9 are 10 and
10 ¥ 10 ¥3K
10 MHz, obtain b-cut-off, gain bandwidth
1 product, gm, rp, rbb', and Cp.
= = 33.33 rad/s
30 ¥ 10 -3 Solution:
Hence, lower 3 dB frequency = 67 rad/s h fe
9. A BJT biased at IC = 10 mA, VCE = 8 V, |A2 (f)| = ,
produces the hybrid parameter as; h ie = 1+ ( f / fb )2
0.5 KW, h re = 10 4 , h fe = 100 and h oe = 2
4 ¥ 10 6 S having f T = 50 MHz with C m
10 =
100 F 10 I
1+ G
= 2 pF. Obtain the other hybrid-p pa-
rameters.
1 + ( 10 / f ) b
H f JK
2
b
Solution: 2
IC 10 ¥ 10 -3 =
F 100 I = 100, FG 10 IJ = 100 1 = 99
2
gm = = = 0.4 S H 10 K Hf K b
VT 25 ¥ 10 -3
10
h fe = 99 = 9.95
100 fb
rp = = = 0.25 K
gm 0.4 10
or fb = = 1.005 MHz
rbb¢ = hie rp = 0.5 0.25 = 0.25 K 9 . 95
rp 0.25 K Gain-band-width product = fT = hfe fb =
rm = = = 2.5 MW 100 ¥ 1.005 MHz = 100.5 MHz
h re 10-4
"$"
IC 10 ¥ 10 -3 0.4
=
gm = = = 0.4 S 2 p ¥ 100 . 5 ¥ 10 6
VT 25 ¥ 10 -3
0.4
h fe 100 =
rp = = = 0.25 KW 2 p ¥ 1. 005 ¥ 10 8
gm 0.4
= 0.0633 ¥ 108
rbb¢ = hie rp = 0.5 0.25 = 0.25 KW
= 633 ¥ 10 12 = 633 pF. Cp = 633 pF
rp 0.25 K Cm = 633 pF 2 pF = 631 pF.
rm = = = 2.5 MW,
h re 10-4 11. If the transistor used in Fig. 10.57(a) has
gce = hoe (1 + hfe) gm rbb¢ = 0.25 K, rp = 1.5 K, rce = 150 K, gm =
= 4 ¥ 106 (1 + 100) 0.4 ¥ 106 30 mS, Cp = 5000 pF, Cm = 40 pF, calcu-
late its higher and lower cut-off frequen-
= 36 ¥ 106 S cies and the bandwidth of the first stage.
h fe ¥ g p gm The second transistor is a high frequency
Cp + Cm = =
2 pf T 2 pf T
transistor.
Figure 10.57(a)

"$#
Figure 10.57(c) Hybrid-’ circuit of RC coupled amplifier
Soution: + 1.5 @ 0.01 + 0.25 + 1.5 = 1.76 KW

Since, the second transistor is a high fre- rp vs rp vs
quency transistor, its behaviour will be as- vp = =
rs RB1 + rbb¢ + rp rs + rbb¢ + rp
sumed in the mid-band range.
vp rp
hfe = rpgm = 1.5 K ¥ 30 mS = 45, =
vs rs + rbb¢ + rp
Ri2 = (1 + hfe)0.1 K
= (1 + 45) 0.1 K = (46) 0.1 K = 4.6 KW Av(mid) =
FG v IJ FG v IJ
vo
=
o p
RB1 =
55 ¥ 4 . 5
= 4.2 KW
v Hv KHv K
s p s
59 . 5 F r IJ p
60 ¥ 12 = g (R | | R ) G
m L C
RB2 =
72
= 10 KW Hr +r +r K s bb ¢ p
Since rce= 150 K, hence it is left open in = 30 ¥ 1.5 G

F 1. 5 IJ
parallel with 2.4 KW H 0 . 01 + 0 . 25 + 1. 5 K
hie = rbb¢ + rp = 0.25 + 1.5 = 1.75 KW 1. 5 I
= 45 F
hie + Ri2 = 1.75 K + 4.6 K = 6.35 KW H 1. 76 K = 38.4
Effective load to first stage = (hie + Ri2) | | vs rp /(1 + jw Ci rp )
vp =
10 K | | 2.4 K = 6.35 K | | 10 K | | 2.4 K rs rbb¢ + rp /(1 + jw Ci rp )
+
6.35 ¥ 10 ¥ 2.4 K rp v s
= =
6.35 ¥ 10 + 10 ¥ 2.4 + 2.4 ¥ 6.35 ( rs + rbb¢ ) (1 + jw Ci rp ) + rp
6.35 ¥ 10 ¥ 2.4 K 152 . 4 rp vs

= = = 1.5 KW =
63.50 + 24 + 15.24 102 . 75 ( rs + rbb¢ + rp ) + jw Ci rp ( rs + rbb¢ )
Ci = Cp + (1 + gmRL) Cm rp vs
=
= 5000 + (1 + 30 mS ¥ 1.K) 40 ( rs + rbb¢ + rp ) 1 + j
FG w IJ
= 5000 + (1 + 45) 40 = 6840 pF
H w H1 K
rs + rbb¢ + rp
vo = gmvp (RL | | RC) where wH1 =
( rs + rbb¢ ) Ci rp
vo
= gm (RL | | RC) 0.01 + 0.25 + 1.5
vp =
(0.01 + 0.25) 1.5 K ¥ 6840 ¥10 -12
rs | | RB1 + rbb¢ + rp = 0.01 | | 4.1 + 0.25
"$$
1. 76 1. 76 1 1000
= -9
= -9
= -3
= = 13.3r/s
2668 ¥ 10 2668 ¥ 10 75 ¥ 10 75
= 6.6 ¥ 10 = 0.66 ¥ 106 = 0.66 Mrad/s
5
Hence, bandwidth of the amplifier = 0.66
Mr/s 13.3 r/s = 0.66 Mrad/s.
1 1
wH2 = = 12
12. A common-emitter amplifier with an ex-
Co RL -
40 ¥ 10 ¥ 1.5 K ternal capacitor CC connected across the
1 base and the collector of the transistor is
= = 16.7 Mrad/s shown in Fig. 10.58(a). Given gm = 5 mS,
60 ¥ 10 -9
rp = 20 K, Cp = 1.5 pF, Cm = 0.5 pF. Calcu-
Hence upper 3 dB = 0.66 Mrad/s. late mid-band voltage gain vo / vi and de-
Lower 3 dB is controlled by the coupling termine the upper cut-off frequency of the
capacitor 25 mF and is expressed as amplifier.
1 1
wL = = -6
C2 RL 25 ¥ 10 ¥ 1.5 K
Figure 10.58(a)
Figure 10.58(c) Simplified equivalent circuit

"$%
Solution: 30 K ¥ 10 4
Ci = Cp + (1 + gmRL) Cm = 1.5 + 1300.5 where wHi = = 0.115 Mrad/s
2604
= 1302 pF FG v IJ FG v IJ = 0.666 - g ¥ 10 K
o p m
- g mvp ¥ 10 K H v K H v K Ê1 + j w ˆ 1 + j w
vo = p i
1 + jw ¥ 25.5 pF ¥ 10 K ÁË w Hi ˜¯ w Ho
- g mvp ¥ 10 K - gm vp ¥ 10 K
= = - 0.666 ¥ 5 ¥1 0 -3 ¥10 K
1 + jw ¥ 25.5 ¥ 10 -8 w =
1+ j Ê w ˆÊ w ˆ
w Ho Á1 + j 0.115 ¥ 106 ˜ Á1 + j 39.2 ¥ 10 6 ˜
Ë ¯Ë ¯
10 8
where wHo = = 39.2 Mrad/s vo
25 . 5 - 0 . 666 ¥ 50
=
vp =
vi vi F1+ j w I F1 + j w I
10 K + rbb¢ +
GH 0 .115 ¥ 10 JK GH 39 . 2 ¥ 10 JK
6 6
rp - 33 . 33
1 + jw ¥ 1302 ¥ 10 -12 ¥ 20 K =
F1+ j w I F1+ j w I
Ê rp ˆ GH 0 .115 ¥ 10 JK GH 39 . 2 ¥ 10 JK
6 6
Á -12 ˜
Ë 1 + jw ¥ 1302 ¥ 10 ¥ 20 K ¯
vo
Mid-band voltage gain = = 33.33
vi vi
=
20 K Upper cut-off frequency = 0.115 ¥ 106 rad/s
10 K +
1 + jw ¥ 2604 ¥ 10-8
13. An n-p-n transistor has a beta cut-off fre-
Ê 20 K ˆ quency fb = 1 MHz and common-emitter
Á -8 ˜ short circuit low-frequency current gain
Ë 1 + jw ¥ 2604 ¥ 10 ¯ bo = 200. Its unity-gain frequency fT and
vi the alpha cut-off frequency fa are
= (a) 200 MHz, 2011 MHz, (b) 200 MHz,
10 K + 20 K + jw ¥ 2604 ¥ 10 -4
199 MHz, (c) 1991 MHz, 200 MHz,
1 + jw ¥ 2604 ¥ 10 -8 (d) 201 MHz, 200 MHz.
Ê 20 K ˆ fT = bfb = 200 ¥ 1 MHz = 200 MHZ, fa =
Á -8 ˜ (1 + b ) fb = 201 ¥ 1 MHz = 201 MHz
Ë 1 + jw ¥ 2604 ¥ 10 ¯
Solution:
vp 20 K 14. The transistor in the circuit of Fig. 10.59(a)
=
vi 10 K + 20 K + jw ¥ 2604 ¥ 10 -4 is so biased that the collector current IC = 1
mA. Evaluate the small signal voltage gain at
20 K 0 . 666 10 KHz and Ri for (a) CE is bypassed by 25
= =
Ê w ˆ w mF and (b) CE is not connected across RE.
(10 K + 20 K) Á1 + j 1+ j
Ë ˜
w Hi ¯ w Hi
"$&
vi
From Fig. 10.59(b) ib =
1.4 K + 0.1 K + 2.5 K
vi
=
4K
2.5 Kvi
Vp = rpib = = 0.625vi
4K
vo = (gmvp)2 K = (40 mS ¥ 0.625vi)
2 K = 50vi
Hence, voltage gain with bypassed
vo
Figure 10.59(a) RE = = 50.
vi
(b) With CE removed,
vi
ib =
1.4 K + 0.1 K + 2.5 K + 101 ¥ 0.1 K
vi
=
14.1 K
vi
vp = rpib = 2.5 K = 0.17vi
Figure 10.59(b) Equivalent circuit 14.1 K
Solution: vo = (gmvp)2 K = (40 mS ¥ 0.177vi)2 K
1 mA h fe = 14.2vi
gm = = 40 mS = ,
25 mV rp Hence, voltage gain with bypassed
h fe 100 vo
rp = = = 2.5 K RE = = 14.2.
gm 40 mS vi
1 1 15. Obtain the simplified high frequency
XC = =
2 pfC 2p ¥ 10 KHz ¥ 25 ¥ 10 -6 equivalent circuit of Fig. 10.60(a) and de-
100 2 rive expression for the voltage gain and 3dB
= = = 0.65 W frequency neglecting the base spreading re-
50 p p
sistance. Obtain total input capacitor also.
Figure 10.60(a) Figure 10.60(b)

"$'
vi = vb¢e - gm RL
=
Ci = Cp + (1 K)Cm, w
1+ j
RL wH
vo = gm vb¢e 1
1 + jw ( C m + C L ) R L wH = 3dB frequency =
( Cm + CL ) RL
vo -gm RL
=K= Total input capacitance = Ci
v b'e 1 + jw ( C m + C L ) R L
F
= Cp + 1 +
gm RL IC
GH 1 + jw ( C m + C L ) R L JK m
Multiple Choice Questions 6. The typical value of reverse bias collector

junction resistance rce in a high frequency
1. The base width of a high frequency tran- hybrid-p model of the BJT in CE configu-
sistor w.r.t. to a low frequency transistor ration is
is (a) 1 KW (b) 10 KW
(a) bigger (b) smaller (c) 100 KW (d) 100 MW
(c) equal. 7. The typical value of forward bias emitter
2. The base-spreading resistor rbb¢ is junction resistance rb¢e = rp in a high fre-
(a) proportional to the base width quency hybrid-p model of the BJT in CE
(b) inversely proportional to the base configuration is
width (a) 1 KW (b) 10 KW
(c) constant. (c) 100 KW (d) 100 MW
3. The forward biased emitter-base junction 8. The diffusion capacitance CD = Cp in a
resistance is high frequency hybrid-p model of a BJT in
(a) proportional to the dc bias current CE configuration accounts for
through it (a) emitter junction barrier capacitance
(b) inversely proportional to the dc bias (b) collector junction barrier capacitance
current through it (c) excess minority charges trapped in the
(c) constant. base
4. The depletion capacitance with increasing (d) excess charges trapped in collector
reverse bias region.
(a) increases (b) decreases 9. The depletion capacitance Cb¢c = CTC = Cm
(c) remains constant. in a high frequency hybrid-p model of a
5. The typical value of collector-to base feed- BJT in CE configuration accounts for
back resistance rb¢c = rm in a high fre- (a) emitter junction barrier capacitance
quency hybrid-p model of the BJT in CE (b) collector junction barrier capacitance
configuration is (c) excess minority charges trapped in the
(a) 1 KW (b) 10 KW base
(c) 100 KW (d) 100 MW (d) excess charges trapped in collector
region.
"%
10. The depletion capacitance Cb¢e = CTE in a 17. The fb is the frequency at which the short
high frequency hybrid-p model of a BJT in circuit current gain of the transistor in CE
CE configuration accounts for is
(a) emitter junction barrier capacitance (a) half of the mid-band gain
(b) collector junction barrier capacitance (b) one tenth of mid-band gain
(c) excess minority charges trapped in the (c) unity
base (d) 1 / 2 the mid-band gain.
(d) excess charges trapped in collector 18. As the collector current IC increases, the
region. value of fT
11. The typical value of Cb¢e = Cp in a high fre- (a) increases
quency hybrid-p model of the BJT in CE (b) decreases
configuration is (c) remains constant
(a) 1 pF (b) 10 pF (d) decreases to a minimum and then in-
(c) 100 pF (d) 1000 pF creases.
12. The typical value of Cb¢c = Cm in a high fre- 19. The total input capacitance at high fre-
quency hybrid-p model of the BJT in CE quency hybrid-p model of the transistor in
configuration is CE configuration is
(a) 1 pF (b) 10 pF (a) dependent on the Miller capacitance
(c) 100 pF (d) 1000 pF (b) independent of the Miller capacitance
13. The typical value of gm in a high frequency (c) dependent on source resistance.
hybrid-p model of the BJT in CE configu- 20. The Miller capacitance at high frequency
ration is hybrid-p model of transistor in CE con-
(a) 1 mS (b) 10 mS figuration is approximated as
(c) 100 mS (d) 1000 mS (a) (1 + gmRL) Cm + Cp
14. The typical value of the bias spreading re- (b) (1 + gmRL) Cp + Cm
sistance rbb¢ in a high frequency hybrid-p (c) (1 + gmRL)/(Cp + Cm)
model of the BJT in CE configuration is (d) (1 + gmRL)/Cp
(a) 1 W (b) 50 W 21. The mid-band short circuit current gain bo
(c) 500 W (d) 1M W is
15. The transconductance gm of a high fre- (a) proportional to the transconductance
quency hybrid p model of a BJT in CE con- of the transistor
figuration is (b) inversely proportional to the
(a) proportional to the dc current through it transconductance of the transistor
(b) inversely proportional to the dc cur- (c) not related to the transconductance of
rent through it the transistor.
(c) constant. 22. The transition cut-off frequency fT is re-
16. The fT is the frequency at which the mag- lated to fb as
nitude of short circuit current gain of the (a) fT = bo / fb (b) fT = bo fb
transistor in CE configuration is (c) fT = bo / fb (d) fb = bo fT
(a) half of the mid-band gain 23. The a cut-off frequency fa of the transis-
(b) one tenth of mid-band gain tor is related to b cut-off frequency as
(c) unity (a) (1 a) fb (b) fb / (1 a)
(d) 100 (c) (1 + b)fb (d) fb / (1 b)
"%
24. If the values of Cm = 2 pF, Cp = 100 pF, gm 25. If the b cut-off frequency fb = 100 KHz
= 100 mS, RL = 1 K, the value of Miller and b = 100, then the a cut-off frequency
capacitance CM is fa of the transistor is
(a) 302 pF (b) 202 pF (a) 10.1 MHz (b) 1 KHz
(c) 2.02 pF (d) 0.49 pF. (c) 103 Hz.

1. (b) 2. (a) 3. (b) 4. (b) 5. (d) 6. (c)
7. (a) 8. (c) 9. (b) 10. (a) 11. (c) 12. (a)
13. (c) 14. (b) 15. (a) 16. (c) 17. (d) 18. (d)
19. (a) 20. (a) 21. (a) 22. (b) 23. (b) 24. (b)
25. (a)
11
Multistage Amplifiers
11.1 Introduction
Most of the time it is not possible to get the desired amplification by a single stage amplifier. Hence, a
number of stages of amplifiers are connected in cascade to get the desired amplification. A number of
stages are coupled in cascade through different types of coupling networks. The main functions of the
coupling network are as follows:
∑ To allow the ac output signal of previous stage to reach the input of next stage without attenu-
ation
∑ To isolate the dc bias conditions of connected stages
The important coupling methods are:
∑ RC coupling
∑ Transformer coupling
∑ Direct coupling
∑ Impedance coupling
The name of the amplifier is given depending on the type of coupling used in it. The coupling means
connecting the source to the input of the amplifier, the load to the output of the amplifier and output of
one stage of the amplifier to the input of the other stage of the amplifier. The RC coupled amplifier uses
coupling through resistance and capacitance, the transformer-coupled amplifier uses coupling through
a transformer, and direct-coupled amplifiers use dc voltages and resistances for coupling. A block
diagram approach of multistage amplifier configuration is shown in Fig. 11.1.
"%!
Figure 11.1 Cascaded multistage amplifier
The input and output voltages at different points as shown in Fig. 11.1 are related as
vo1 = A1vi1 , (11.1.1)
vo2 = A2 vi 2 , (11.1.2)
As vo1 = vi2 (11.1.3)
vo2 = A2 vi 2 = A2 A1vi1 (11.1.4)
Thus, overall voltage gain of n-number of cascaded stages of the amplifier can be expressed as:
Avn =
FG v IJ FG v IJ *...................* FG v
o1 o2 o (n - 1) IF v I
on
JK GH v JK (11.1.5)
H v KH v K
i1 i2 Hvi ( n - 1) in
Since, vin = vo( n -1) , vi ( n - 1) = vo( n - 2) vi3 = vo2 , vi2 = vo1 (11.1.6)
von
Avn = (11.1.7)
vi1
11.2 Decibel
It has been demonstrated experimentally that human ear responds to sound intensity on a logarithmic
scale rather than linear scale. In other words, if the power content of a particular sound is increased by
a factor of 2, the ear does not perceive it as being twice as loud but as being louder by a factor of
log102 = 0.3. Alexander Graham Bell introduced a new unit for measurement of power gain for such
peculiar behaviour of human ear. The new unit has some specific advantage and is being used in sound
and communication where human ear is not involved. The new unit introduced was given the name bel
(a mutation of inventors name). It is defined as
Power gain in bel = log (power gain ratio)
Mathematically, it is defined as logarithm to the base 10 of the ratio of two power levels, i.e.
Bel = log10
FG P IJ
2
(11.2.1)
HPK
1
Example
If the numerical power gain in ratio of any system is 2 ¥ 106, then power gain in bels is
= log10 (2 ¥ 106) = log10106 + log10 2 = 6 log10 10 + log10 2 = 6 + 0.3 = 6.3 bels (11.2.2)
"%"
It is clear from Eqn. 11.2.2 that bel is a very large unit for most of the practical situations as a power
gain ratio of the order of even 106 amounts to only 6 bels . It would be convenient to use a smaller unit
called decibel (abbreviated dB) that is one tenth of a bel, i.e.
1bel = 10 dB , and 1 dB = 0.1 bel (11.2.3)
Thus, the power gain in bels should be multiplied by 10 to get power in decibels. In other words, the
power gain in decibels is expressed as
Power gain in dB = 10 log ( power gain in ratio) (11.2.4)
For example, a power gain in ratio of 200 leads to 10 log (200) = 10* 2.301 = 23.0l dB and a power
gain 106 in ratio results into 60 dB.
Now the power gain from dB can be obtained as a ratio of power gain by taking antilog of the dB as
RS
Power gain in ratio = anti log Power gain in
FG dBIJ UV (11.2.5)
T H 10 K W
For instance, a power gain of 41.71 dB, divide it by 10 and then take antilog (10 raised to its power
by the value of dB divided by 10) of it.
Power gain in ratio = anti log (4.771) = 104.771 = 59020 = 5.9020 ¥ 104 (11.2.6)
For the ratio of power gain less than 1, the corresponding values of decibels will be negative. For an
example, a power gain of 0.5 is = 10 log10 (0.5)dB = 10(0.301) = 3.01dB. Conversely, if the decibel
value of power gain is negative, the ratio will be less than 1. Table11.1 gives some selected values of
power gains and corresponding decibels, and Table 11.2 gives values of 21/ n - 1 .
Table 11.1 Power gain Table 11.2
Power gain ratio Power gain in dB n 21/n - 1

1 0 1 1.00
10 10 2 0.643
10n 10n 3 0.510
2 3 4 0.431
20 13 5 0.387
3 4.77 6 0.350
5 6.99 7 0.322
7 8.45 8 0.300
11.2.1 Decibel for Voltage and Current Ratios

The decibel as per definition was accepted as the unit of power. It is used equally well for current and
voltage ratios, with the precaution of impedance levels at the point of measurement. The power in terms
of voltages and currents are defined as
v2
P= = i2R (11.2.7)
R
"%#
Here, both v and i are rms values.

2
Hence,
v22 / R2
dB = 10 log
v
= 10 log 2 + 10 log 1
R FG IJ FG IJ = 20logFG v IJ + 10logFG R IJ (11.2.8)
2 1
2
v1 / R1 v1 R2 H K H K Hv K
1 HR K 2
Similarly, dB in terms of current ratios are expressed as
dB = 10 log10
F i I + 10log F R I = 20log F i I + 10log F R I
2
2 2 2 2
GH i JK
2
1
GH R JK10 GH i JK1
GH R JK 10
1
10
1
(11.2.9)
The dB is universally accepted unit of even voltage gains. The frequency response of any amplifier
from very low frequency to extremely high frequency is plotted on the logarithmic graph only. Had no
logarithmic scale of graph been proposed, it would have been impossible to get visual ideas of the
variation of gains (voltage or current) together from very low frequency to very high frequency.
In the case of voltage amplifier it is assumed that the input impedance is matched. Hence, assuming
R2 = R1 , Eqns. 11.2.8 and 11.2.9 now reduce to
2
dB = 10 log10
FG v IJ + 10log (1) = 20log FG v IJ + 0 = 20log FG v IJ
2
10 10
2
10
2
(11.2.10)
Hv K
1 Hv K Hv K 1 1
= 10 log10
F i I + 10log (1) = 20log F i I + 0 = 20log F i I
2
2 2 2
(11.2.11)
GH i JK
2
1
10 GH i JK GH i JK 10
1
10
1
11.2.2 Effect of Cascading on Bandwidth

The product of the individual stages gives the overall gain of the cascaded stages. Thus, the mid-band
gain of the n-identical amplifier stages is expressed as
An = (A)n (11.2.12)
The overall gain of the n-identical cascaded stages of the amplifiers in the low frequency range is
written as
( Ao ) n ( Ao ) n
( A) n = n
= n/ 2
(11.2.13)
FG1- j w IJ L R|1 + F f I L
2
U|
H wK S| GH f JK V|
T W
If f Ln indicates the overall lower 3dB frequency of n-identical cascaded amplifier, then at this frequency
n
FG A IJ L
=
1
=
1
(11.2.14)
n/ 2
HA K o 21/ 2 R| F f I U| L
2
S|1 + GH f JK V|
n/ 2
T W
Ln
R| F f L IJ 2
U| 1/2 F f IJ = 2 L
2
1/n
S|1 + GH f K V| =2 , and 1 + G
Hf K
T Ln W Ln
"%$
fL
= 21/n - 1
f Ln
fL
f Ln = (11.2.15)
1/ n
2 -1
Similarly, the gain of the n-identical cascaded stages of amplifier can be expressed in the high frequency
range as
( Ao ) n ( Ao ) n
( AH )n = n = n/2 (11.2.16)
RS1 + jF w I UV R|1 + F f IJ U|V
2
T| GH w JK W| H
S| GH f
T H K W|
If the overall 3 dB frequency of the n-identical cascaded amplifiers is indicated as f Ln , then
n
FG A IJ
H
=
1
=
1
(11.2.17)
n/ 2
HA Ko 21/ 2 R| F f I U| Hn
2
S|1 + GH f JK V|
T W
H
f Hn
= 21/n - 1
fH
f Hn = FH 21/n - 1 f H IK (11.2.18)
Hence, the bandwidth of n-identical cascaded amplifier is written as

FH IK fL FH IK
f Hn - f Ln = 21/ n - 1 f H -
@ 21/n - 1 f H (11.2.19)
1/ n
2 -1
For example, the overall bandwidth of a 1, 2, and 3 stages of identical RC-coupled amplifiers a with
lower and higher cut-off frequencies of 10 Hz and 1 MHz respectively are
Bandwidth of one-stage amplifier = 1 MHz 10 Hz @ 1 MHz.
Lower and higher cut-off frequencies for two-identically cascaded stages are
fL 10 10
f L2 = = = = 15.55 Hz
21/n - 1 21/ 2 - 1 0.643
f H2 = FH 21/n - 1 f H =IK FG
H
IJ
21/ 2 - 1 f H = 0.643 ×1 MHz = 0.643 MHz = 643 kHz
K
Bandwidth for two two-stages = 643 kHz 0.016 kHz @ 643 kHz .
Lower and higher cut-off frequencies for three identically cascaded stages are
fL 10 10
fL3 = = = = 19.6 Hz
1/ 3 1/ 3 051
.
2 -1 2 -1
"%%
fHn = F I
21/ 3 - 1 f H = 0.51 ¥ 1 MHz = 0.51 MHz = 510 kHz
H K
Bandwidth for three-stages = 510 Hz 19.6 z @ 510 kHz
Thus, we find that as the number of cascading of identical stages of the amplifiers goes on increasing,
the effective bandwidth goes on decreasing from 1 MHz to 643 kHz to 510 kHz for single stage, two
stages, and three stages as depicted in Figure. 11.2.
Figure. 11.2 Bandwidth for a number of stages
The above analysis is valid when the dominant pole in the pole-zero representation of the voltage
transfer function of an amplifier exists. When there is no dominant pole or the pole-zero representation
of multiple amplifiers is different from one another, the higher cut-off frequency can not be exactly
found theoretically. It can be obtained from approximate analysis of the two-pole-zero representation of
transfer function described as
(1 + S / w z1 )(1 + S / w z 2 )
H(s) = (11.2.20)
(1 + S /w p1)(1 + S /w p2 )
or H ( jw )
2
=
(1 + w /w )(1 + w / w )
2 2
z1
2 2
z2
(11.2.21)
(1 + w /w )(1 + w / w )
2 2
p1
2 2
p2
The higher cut-off frequency of such an amplifier is dervied from the 3 dB frequency wH as
1
=
(
2
1 + wH )(
w z21 1 + w H2 w z22 ) (11.2.22)
2 (
2
1 + wH w 2p1 1 + w H2
)(
w 2p 2 )
w H2 w H2 w H2 w H2 Ê w2 w2
H H w H2 w H2 ˆ
or, + + ¥ = 1 + 2 Á + + ¥ 2 ˜ (11.2.23)
w 2p1 w 2p 2 w 2p1 w 2p 2 2 2 2
Ë w z1 w z 2 w z1 w z 2 ¯
2
wH w H2 Ê w H2 w H2 ˆ
or, + - 2 Áw2 + w2 ˜ = 1
w 2p1 w 2p 2 Ë z1 z2 ¯
"%&
1
Hence, wH = (11.2.24)
1 1 Ê 1 1 ˆ
2
+ 2 - 2Á 2 + 2 ˜
w p1 w p 2 Ë w z1 w z 2 ¯
Thus, for n-number of pole transfer function, the higher 3 dB frequency wH will be represented as
1
wH = (11.2.25)
Ê 1 1 ˆ Ê 1 1 ˆ
Á 2 + 2 + ◊ ◊ ◊◊ ◊˜ - 2 Á 2 + 2 + ◊ ◊ ◊◊ ◊˜
Ë w p1 w p 2 ¯ Ë w z1 w z 2 ¯
11.3 CE-CE Cascaded Stages

So far we have analyzed different configurations of BJT amplifiers (CB, CE, and CC) in detail as stand
alone unit. Now let us analyze different combinations of cascaded stages.
Let us obtain output voltage of two- CE stages coupled together as in Fig. 11.3(a).
Assuming that the second stage does not load the first stage, i.e. each stage is isolated, output voltage
of only first stage = vo1 = - h fe1ib1RL1 = - 100 ¥ 2 Kib1
Ê vs ˆ Ê 15 K ˆ vs v
ib1= Á ˜ Á ˜ @ @ s
Ë rs + 15 K ||1K ¯ Ë 16 K ¯ rs + 1 K 1K
Ê v ˆ v
vo1 = -100 ¥ 2 K Á s ˜ = 200vs and o1 = - 200
Ë1K¯ vs
Since the second stage is identical to the first stage, the voltage gain of the second stage is
vo 2
= - 200
vo1
Figure 11.3(a) CE-CE stage

"%'
Figure 11.3(b) ac circuit of CE-CE
Figure 11.3(c) Equivalent circuit of CE-CE
Overall voltage gain of the two identical cascaded stages = ( - 200)( - 200) = 40 ¥ 103 .
If the two stages are not considered as isolated ones, then
vo2 = − ic 2 Rc2 = - h fe 2ib 2 Rc2 = - 100 ¥ 2Kib 2 = - 200Kib 2
RC1|| RB 2
ib2 = − h fe1ib1
RC1|| RB 2 + hie 2
2 ¥ 15 K
where, Rc1|| RB 2 = = 1.765 KW
17
Ê 1.765 K ¥ 1K ˆ
vo1 = -100ib1 Á = - 100ib1 ¥ 0.64 K = − 64 × 103 ib1
Ë 1.765 K + 1K ˜¯
vs v Ê v ˆ
ib1 = , ib2 = o1 and vo1 = - 64 ¥ 103 Á s ˜ = - 64vs
1K 1K Ë 1K¯
Êv ˆ
vo2 = - ic 2 Rc 2 = - h feib 2 Rc 2 = 100 ¥ 2 Kib2 = - 200 K Á o1 ˜ = - 200vo1
Ë 1K ¯
vo2 = 200 ¥ 64vs = 12800vs = 12.8 ¥ 103 vs
vo 2
= 12.8 ¥ 103
vs
This indicates that due to loading effect of the second stage, the overall gain 12.8 ¥ 103 of the
two identical cascaded stages is less than the one of the isolated two stages amplifier 40 ¥ 103.
"&
11.4 CE-CC Cascade Stage

Figure 11.4(a) is the cascade of CE and CC amplifiers. Let us obtain the voltage gain of the cascaded
stages shown in Fig. 11.4(a).
Figure 11.4(a) CE-CC
Figure 11.4(b) ac circuit of CE-CC stage
Figure 11.4(c) Equivalent circuit of CE-CC stage
Assuming both stages are isolated i.e. the first stage is not loaded by the second stage.
vo1 = - h fe1ib1RC1 = 100 ¥ 2Kib1 = 200Kib1
Ê vs ˆ Ê 15 K ˆ v
ibl = Á ˜ Á ˜ @ s
Ë rs + 1 K||15 K ¯ Ë 16 K ¯ 1K
Ê v ˆ
v01= - 200 K Á s ˜ = 200vs
Ë1 K¯
"&
Figure 11.4(d) Simplified equivalent circuit of CE-CC stage
vo1
Hence, only first stage voltage gain without second stage loading = = 200
vs
Ri2 = hie2 + (1 + hfe2)RE2 = 1 K + 100 ¥ 2 K ∫ 200 K
Ri2||15 K = 200 K||15 K @ 15 K
vo2 = (1 + hfe2)RE2ib2 ∫ 200Kib2
vo1 - 200vs
ib2 = =
200 K 200 K
Ê - 200vs ˆ
vo2 = 200 K Á = 200vs
Ë 200 K ˜¯
vo 2
= 200
vs
This indicates that the second stage does not provide any voltage gain. The overall voltage gain of
both stages is just the voltage gain of the first stage.
Now, let us consider the loading effect of the second stage i.e. the effective load for the first stage
RC1|| RB 2 || Ri 2 = 15 K||2 K||200 K @ 15 K ||2 K = 1.76 K
Ê v ˆ
. Kib1 = -176Kib1 = -176 K Á s ˜ = −176vs
vo1 = - 100 ¥ 176
Ë 1 K¯
Thus, voltage gain of first stage with second stage also connected is
vo1
= 176
vs
vo1 176vs
ib2 = = = - 88 ¥ 10 - 5 v s
200 K 200 K
vo2 = 200 K(- 88 ¥ 10- 5 vs ) = 176 vs

vo 2
= 176
vs
"&
This reveals that overall gain of CE-CC stage is simply the gain of the first stage.
11.5 Cascode Amplifier

The cascode amplifier is actually a cascaded combination of common emitter followed by common
base configuration as drawn in Fig. 11.5(a). The ac circuit of the cascode amplifier shown in
Fig. 11.5(a) is drawn as Fig. 11.5(b). Now the small signal equivalent circuit of cascode amplifier
illustrated in Fig. 11.5(b) is drawn as Fig. 11.5(c).
hie 2
hib2 = , vo = - h fb 2ie 2 RL (11.5.1)
1 + h fe 2
ie2 = ic1 = hfe1ib1, ib1 =

FG v IJ FG R IJ
s
(11.5.2)
H R||h + r K H R + h K
ie s ie1
Figure 11.5(a) Cascode amplifier Figure 11.5(b) ac circuit of cascode amplifier
Figure 11.5(c) Equivalent circuit of cascode amplifier
Combining Eqns. 11.5.1 to 11.5.2 yields vo as

vo = − RL h fb 2ie 2 = − h fb 2h fe1RLib1
"&!
=
FG v IJ FG R IJ (- h h R )
s
fb 2 fe1 L (11.5.3)
H R||h + r K H R + h/ K
ie s ie1
vo = −G
F v IJ FG R IJ h h R = − v (h
s s
fb 2 h fe1 RL ) (11.5.4)
H h + r KH RK
ie1 s
fb 2 fe1
h + r/
L
ie1 s
vs
vo = − ( h fb 2 h fe1 RL ) = − g m1h fb 2 R L v s (11.5.5)
hie
If hib2 ∫ 1, then voltage gain is expressed as
vo
Av = = − g m1 RL (11.5.6)
vs
Eqn 11.5.6 indicates that the gain of the cascode amplifier is the same as the gain of the CE stage. The
most important advantage of the cascode connection becomes apparent at high frequencies, where the
capacitance present between base and collector reduces the gain by feedbacking the output voltage
through the capacitor. The cascode connection reduces this effect very significantly and results in
wider-bandwidth high gain amplifier than that provided by the CE stage alone.
11.6 Differential Amplifier

The output voltage of differential amplifier is proportional to the difference of the two-inputs to justify
the name of differential amplifier. Its basic requirement is that its gain should be very high for the
differential mode signals and very low for the common mode signals. The two-inputs for the circuit of
vd v
Fig. 11.6(a) have both common and difference mode signals as v1 = vc - and v2 = vc + d where vc
2 2
is the common mode signal and vd is the differential mode signal. The common mode and differential
mode signals can be represented as depicted on right side of Fig.16.4(a).
For common mode signal, the total emitter current is the sum of the two-emitter currents ie1 and ie2
supplied by transistors T1 and T2. Since both transistors are identical and the circuit of Fig. 11.6 (a)
through the dotted lines is symmetrical in all respects, it can be cut into two halves. The one half circuit
will represent the effect of both halves by considering the emitter resistance as shown in
Figs. 11.6(a), (b) and (c).
11.6.1 AC Analysis
Ideally, the differential amplifier amplifies the two out of phase signals vd and at the same time rejects the
in phase signals vc such as stray pickups, drift, etc. The small signal equivalent circuit for Fig. 11.6(a)
is drawn as Fig. 11.6(b). For analysis in the differential mode, the equivalent circuit of Fig. 11.6(b) can
be cut through the middle of the circuit as indicated by dotted lines with the shorting the emitter resistor
to the ground to give the same effect of voltage drop across the emitter resistance RE as shown in
Fig. 11.6(c).
"&"
IC1 IC2 +VCC

RC RC
v2
T1 T2 Vd /2
vc Vd
rs
rs RE Vd /2
IE1 IE2
v1
v1 v2
0 wt
VEE
Figure 11.6(a) Differential amplifier with common mode and difference mode signals
From left side of Fig. 11.6(c), ib =

FG v /2 IJ
d
(11.6.1)
Hr +h K
s ie
vo1 = − h feib RC = − h fe RC
FG v /2 IJ
d
(11.6.2)
Hr +h K
S ie
Hence, the differential gain

vo1 - h fe RC - h fe RC g R
Ad = = = =- m C (11.6.3)
vd 2(rs + hie ) 2hie 2
Figure 11.6(b) Equivalent circuit of differential amplifier

"&#
Figure 11.6(c) Half-sections in differential mode and common mode
The right side of Fig. 11.6(c) is the simplified equivalent circuit of difference amplifier for the
common mode signals. Here, the emitter resistance has been increased by twice to have the same effect
due to both transistors in the common mode case.
ve
d
From right side of Fig. 11.6(c), 1 + h fe ib = i 2 RE
(11.6.4)
vc - ve vc ve vc 2(1 + h fe ) RE ib
Also ib = = = (11.6.5)
hie + rS hie + rS hie + rS hie + rS hie + rS
{hie + rS + 2(1 + h fe ) RE }ib vc
or =
hie + rS hie + rS
vc
or ib = (11.6.6)
rS + hie + 2(1 + h fe ) RE
vo1 = hfeibRC (11.6.7)

vc
or vo1 = - h fe RC (11.6.8)
rs + hie + 2(1 + h fe ) RE
vo1 - h fe RC
Hence, the common mode gain = Ac= =
vc rs + hie + 2(1 + h fe ) RE
Ad 1 ( h fe + 1) RE h fe RE (h fe RC )2 RE A 2R
CMRR = = + @ = = d E
Ac 2 rs + hie rs + hie 2( rs + hie ) RC RC
RE =
FG R IJ FG CMRRIJ = FG R IJ FG CMRR IJ = CMRR
C C
(11.6.9)
H 2 KH A K H 2 KH R g / 2K g
d c m m
"&$
11.6.2 Input Resistance

The input resistance is very important parameter of the differential amplifier. It determines the input
current for a given input signal. Hence, its resistance in both common and differential modes must be
obtained. The differential mode input resistance is defined as the ratio of small differential mode signal to
the small signal current when a pure differential mode signal is applied to it. From the differential mode
circuit of Fig. 11.6(c), the loop equation can be written as
vd
= ( rS + hie )ib (11.6.10)
2
Thus, its input resistance in differential mode is
vd
Rid = = 2( rs + hie ) (11.6.11)
ib
The loop equation in Fig. 11.6(c) to find out the common mode input resistance is written as
vc = (rs + hie ) ib + 2 RE (1 + h fe ) ib (11.6.12)
v
Hence common mode input resistance = Ric = c (11.6.13)
ib
Ric = rs + hie + 2 RE (1 + h fe ) (11.6.14)
Example
1. Obtain the common mode and differential mode gains for the parameters hie = 1K, h fe = 100 , rs
= 0.02 K , RC = RE = 1K .
- h fe RC -100 ¥ 1 K -100 K
Ac = = @ = 0.5
rs + hie + 2(1 + h fe ) RE 0.02 K + 1 K + 2 ¥ 100 ¥ 1 K 200 K
- h fe RC -100 ¥ 1 K -100 K
Ad = = @ = 49
2(rs + hie ) 2(0.02 K + 1 K) 2.04 K
The value of differential mode gain ( 49) w.r.t. insignificant value of common mode voltage
gain (0.5). Above example reveals that the differential amplifier amplifies only the differential
signals and rejects the common mode signals.
11.6.3 Common Mode Rejection Ratio (CMRR)

We conclude from the above example that the differential amplifier should amplify only the difference
mode signals and reject the common mode signals. But practically some parts of common mode signals
also get through the amplifier. Hence, a figure of merit has been defined that determines the ratio by
which factor the common mode signals are rejected w.r.t. to the difference mode signals This ratio is
called common mode rejection ratio. It is expressed as
"&%
Ad
CMRR = (11.6.15)
AC
Combining Eqns. 16.6.3, 16.6.9, and 16.7.1 yields the CMRR as
CMRR =
rs + hie + + h fe RE
=
1
1+
FG
2(1 + h fe ) RE IJ (11.6.16)
rS + hie 2 H rs + hie K
Equation 11.6.16 reveals that the value of CMRR increases for the increasing value of RE . But the
value of RE cannot be increased to a very large value due to limitation on the requirement of very large
value of dc supply voltage. If RE is selected to be 1 MW for the emitter dc current of 5 mA, the amount
of voltage drop across RE = 1 M ¥ 5 mA = 5 KV. The regulated dc supply of such a value that will allow
a drop of 5 KV across the emitter resistance is hard to achieve. The CMRR for above example comes
out to
CMRR =
1Ê
Á 1+
2 ¥ 100 ¥ 1 K ˆ
=
1
1+
200FG
=
IJ
1 + 196.078
= 98.54
2Ë 0.02K + 1K ˜¯ 2 102
. H 2 K
This suggests that the value of RE should be such that it offers very low resistance for dc current and
at the same time very large resistance for ac signal. The dual role of RE for ac and dc signals can be
realized with the help of a constant current source. Hence in Fig. 11.7 the differential amplifier with
constant current source is realized using another transistor T3.
Figure 11.7 Differential amplifier with long tail
2. Obtain iL in terms of common and differential mode signals for the circuit in Fig. 11.8(a).
Its small signal equivalent circuit is drawn as Fig. 11.8(b). Writing KVL equations in two input
loops yields
"&&
Figure 11.8(a) Differential amplifier
Figure 11.8(b) Equivalent circuit for differential mode input
Figure 11.8(c) Input equivalent circuit for common mode input
(rs + hie )ie1 ( r + h )i

= v1 - ve and s ie e 2 = v2 - ve (11.6.17)
1 + h fe 1 + h fe
"&'
rs + hie
(ie 2 - ie1 ) = v2 - v1 (11.6.18)
1 + h fe
Its output circuit can be separated from Fig. 11.8(b) using generator-splitting theorem and hence
Fig. 11.8(c) is simplified as Fig. 11.8(d). From Fig. 11.8(d),
vd v
v2 = vc + and v1 = vc - d (11.6.19)
2 2
Now, v2 - v1 = vd ,
v2 - v1 vd
ie 2 - ie1 = = (11.6.20)
(hie + rs )/(1 + h fe ) (hie + rs ) / (1 + h fe )
Figure 11.8(d) Output equivalent circuit in common mode configuration
From output circuit for differential mode signal as depicted in Fig. 11.8(d)
i L = - h fe1ib1
FG R IJ + h i F R I = FG R IJ h
C C C
fe (ib 2 - ib1 )
H 2R + R K
C
GH 2 R + R JK H 2R + R K
L
fe 2 b 2
C L C L
RC
= (ie 2 - ie1 ) (11.6.21)
2 RC + RL
Substituting (ie 2 - ie1 ) from Eqn. 11.6.20 in Eqn. 11.6.21 yields
iL =
FG R IJ v - v = FG R IJ F
C 2 1 C vd I = F R IF v h I
C d fe
(11.6.22)
H 2R + R K h + r H 2R + R K GH (h
C L ie s C L ie + rs ) / h fe JK GH 2R + R JK GH (h + r ) JK
C L ie s
1 + h fe
=
FG 1 IJ FG h fe RC IJ 2v d =
- Ad 2vd
(11.6.23)
H 2R + R K H 2(h
C L ie +r Ks 2 RC + RL
- h fe RC
where Ad == Differential voltage-gain (11.6.24)
2(hie + rs )
For common mode signals, the two currents through the emitter resistance add up. Hence, for
common mode signal (ib2 + ib1) from Eqn. 11.6.17 yields
"'
(rs + hie )ie1 (rs + hie )ie 2

+ = ( rs + hie )(ib 2 + ib1 ) = v2 - ve + v1 - ve = v2 + v1 - 2ve (11.6.25)
1 + h fe 1 + h fe
ie1 + ie 2 = (1 + h fe )(ib 2 + ib1 ) (for equal amplification factor)
ve = (ie1 + ie 2 ) RE = (1 + h fe )(ib 2 + ib1 ) RE (11.6.26)
ve
ib1 + ib 2 = (11.6.27)
(1 + h fe ) RE
Substituting for (ib1 + ib 2 ) from Eqn. 11.6.27 in Eqn. 11.6.25 results in
br + h g (1 + hv ) R
s ie
e
fe E
= v2 + v1 - 2ve (11.6.28)
br + h g (1 + hv ) R
s ie
e
fe E
+ 2ve = v2 + v1 (11.6.29)
R| r + h + 2(1 + h
s ie fe ) RE U|v
S| (1 + h ) R V| e = v2 + v1 = 2vc (11.6.30)
T fe E W
2vc (1 + h fe ) RE
ve = (11.6.31)
rs + hie + 2(1 + h fe ) RE
Hence, substituting ve from Eqn. 11.6.31 in Eqn. 11.6.27 results in
ve 2vc (1 + h fe ) RE {rs + hie + 2(1 + h fe ) RE }
(ib 2 + ib1 ) = =
(1 + h fe ) RE (1 + h fe ) RE
2vc
(ib 2 + ib1 ) = (11.6.32)
rs + hie + 2(1 + h fe ) RE
The output circuit for differential mode is drawn as in Fig. 11.8(d) and from it,
i L = h feib
FG R IJ + h i FG R IJ = FG h (i + i ) R IJ
C
fe b
C fe b1 b2 C
(11.6.33)
H 2R + R K H 2 R + R K H 2R + R K
C L C L C L
Now substituting for (ib 2 + ib1 ) from Eqn. 11.6.32 in Eqn. 11.6.33 yields
iL =
FG R IJ h bi + i g = FG R IJ R|S
C
fe b1 b2
C 2vc U|
V| (11.6.34)
H 2R + R K C H 2R + R K |T r + h
L C L s ie + 2(1 + h fe ) RE W
iL =
- 2v F -h R
c
I = - 2vc Ac fe C
(11.6.35)
2 R + R H r + h + (1 + h ) R JK
G
C L 2R + R
s ie fe E C L
"'
11.7 Balancing Differential Amplifier

Obtain iL and values of R1 and R2 that will balance the amplifier and maximize the CMRR in Fig. 11.9(a).
Its small signal equivalent circuits are drawn in Figs. 11.9(b) and (c).
Figure 11.9(a) Balancing differential amplifier
Using superposition theorem ie2 is obtained as
ie2 = h fe2ib 2 = ic2 =

v2
-
v1 FG R IJ E
(11.7.1)
RE R1¢ RE R2¢ H R + R¢ K
R2¢ + R1¢ + E 2
RE + R1¢ RE + R2¢
hie1 + rs h +r
where R1¢ = R1 + , R2¢ = R2 + ie 2 s (11.7.2)
h fe1 h fe 2
Figure 11.9(b) Equivalent circuit of balancing differential amplifier
Figure 11.9(c) Simplified equivalent circuit of balancing differential amplifier

"'
v2 ( RE + R1¢) v1RE (v2 - v1 ) RE + v2 R1¢

ie2 = - =
R1¢(RE¢ + R2¢ ) + RE R2¢ R2¢ (R1¢ + R2¢ ) + RE R1¢ R1¢( RE + R2¢ ) + RE R2¢
vd v
v2 - v1 = vc + vc + d = vd (11.7.3)
2 2
(v2 - v1 ) RE + R1¢v1 v R + R1¢(vc + vd 2)
ie2 = = d E (11.7.4)
RE ( R1¢ + R2¢ ) + R1¢R2¢ RE ( R1¢ + R2¢ ) + R1¢R2¢
Substituting the value of v1 and v2 from Eqns. 11.7.3 in 11.7.4 results in
vd
R1¢v c + ( 2 RE + R1¢ )
ie2 = 2 (11.7.5)
RE ( R1¢ + R2¢ ) + R1¢ R2¢
2 RE + R1¢ 1 R
CMRR = = + E (11.7.6)
2 R1¢ 2 R1¢
Thus, under balanced condition, the two-input loops yields equal voltages and currents. If VBE1= VBE 2 ,
the condition to ensure the two-emitter currents equal is obtained by setting I EQ1= I EQ2 . This results in
Ê rs ˆ Ê r ˆ
Á + R1 ˜ I EQ1 + VBE1 = Á s + R2 ˜ I EQ 2 + VBE 2 (11.7.7)
Ë h fe1 ¯ Ë h fe 2 ¯
Ê 1 1 ˆ
R2 R1 = Á - ˜ rs (11.7.8)
Ë h fe1 h fe 2 ¯
If it is assumed that R2 + R1 = Rx, then, Eqn. 11.7.8 yields
Rx Ê 1 1 ˆ Ê rs ˆ
R2 = + Á - (11.7.9)
2 Ë h fe1 h fe 2 ˜¯ ÁË 2 ˜¯
Subtracting the value of R2 in Eqn. 11.7.9 yields
Rx Ê 1 1 ˆ Ê rs ˆ
R1 = Rx - R2 = Á - ˜Á ˜ (11.7.10)
2 Ë h fe1 h fe 2 ¯ Ë 2 ¯
11.8 Long Tail Differential Amplifier

Let us obtain quiescent condition throughout circuits of op-amp. having long tail of Fig. 11.10(a) and
vo /is, Ri and Ro.
"'!
Figure 11.10(a)
Writing dc loop equation in input circuit of transistor T5 yields IE5 as

3 - 0.7 2.3 I
IES = = = 2.3 mA ª I C5 , I E1 = I E 2 = E 5 = 1.15 mA
1K 1K 2
I E1 1.15
I B1 = I B2 = = mA = 0.0115 mA = 115 mA
h fe 100
VC1 = VC2 = 6 - 115

. = 4.85 V = VB3 , VB2 = 1 - 0115
. = 0.885 V
VE5 = - 3 + 2.3 = 0.7 V, VE1 = VE2 = VB1 - 0.7 = 0.885 - 0.7 = 0.185 V
VCE5 = 0185
. - ( - 0.7) = 0.885 V, VB4 = VB3 - 0.7 = 4.85 - 0.7 = 4.15 V
VE4 = VB4 0.7 = 4.15 0.7 = 3.45 V
3.45V 345 mA
IE4 = = 0.345 A = 345 mA @ IC4, IE3 = IB4 = = 3.45 mA
10 100
3.45 mA 25 mV 25 mV
IB3 = = 34.75 mA, hib2 = = = 21.78 W = hib1
100 I E 2 (mA) 1.15 mA
25 mV 25 mV
hib3 = = = 7.25 W
I (mA) 3.45 mA
E3
25 mV 25 mV 25 mV
hie4 = = = = 7.25 W and
IE 4 / h 345 mA /100 3.45 mA
fe
hie 4 25 mV 25 mV
hib4 = h = = = 0.0725 W
fe I E 4 (mA) 345 mA
"'"
Since CB stage provides very large output resistance the realized ac resistance in place of RE be-
comes infinite. In other words for ac signals, the transistor provides an open circuit. Hence, its equiva-
lent circuit is drawn as shown in Figs. 11.10(b) and (c).
Figure 11.10(b) Input side equivalent circuit
Figure 11.10(c) Output side equivalent circuit
Ri = 10 K||14.34 K = 5.89 K
Ê 10 K ˆ
ib2 = Á is = 0.41(is)
Ë 10 K + 14.34 K ˜¯
VT 25 mV 25 mV Ê 25 mV ˆ
hie3 = = = = Á ˜ h fe = hfe hie4
I E 3Q / h fe I E 3Q / h fe I B 4Q / h fe Ë I E 4Q / h fe ¯
Figure 11.10(d) is the simplified circuit of Fig. 11.10(c).
Ê 1 K/104 ˆ Ê 1K ˆ h 3feib 2
ie4 = h3feib 2 Á 4
3
˜ = h feib 2 ÁË 1 K + 100 K + 1.45 K ˜¯ = 102.45
Ë 1 K/10 + 10 + 2 ¥ 0.0725 ¯
= 9.76 ¥ 103 ¥ 106ib2 = 9.76 ¥ 103ib2
vo = 10ie4 = 9.76 × 103 ib 2 × 10 = 9.76 ¥ 104ib2
vo
=
FG v IJ FG i IJ = 9.76 ¥ 10 ¥ 0.41 = 40.02 ¥ 10
o b2 4 3
= 40.02 V/mA
is Hi K H i K
b2 s
"'#
Figure 11.10(d) Output side equivalent circuit for Ro
In order to obtain the output resistance Fig. 11.10(c) reduces to Fig. 11.10(d). From Fig. 11.10(d).
Ro = (2hib 4 + 0.1 W) ||10 W = (2 ¥ 0.0275 + 0.1 W) ||10 W = (0.145 + 0.1) ||10 W = 0.239 W
11.9 Emitter Coupled Differential Amplifier
iL
Find the quiescent conditions throughout the circuit in Fig. 11.11(a) and the ratio .
iS
Figure 11.11(a)
The dc conditions are calculated as

9 V ¥1K
VB1 = = 2.25 V = VB2, VE1 = VE2 = VB1 0.7 = 2.25 0.7 = 1.55 V
4K
1.55 V 3.1 mA
IE1 + IE2 = = 3.1 mA, IE1 = IE2 = = 1.55 mA
500 W 2
VC2 = 9 2.6*1.55 = 9 4.03 = 4.97 V, VCE2 = VC2 VE2 = 4.97 1.55 = 3.42 V
VB4 = VB3 0.7 = 4.97 0.7 = 4.27 V, VE4 = VB4 0.7 = 4.27 0.7 = 3.57 V
3.57 V I 71 mA
IE4 = = 0.071 A = 71 mA ª IL, IE3 = IB4 = E 4 = = 0.71 mA
50 W h fe 100
VC4 = 9 3.57 = 5.43 V, VCE4 = VC4 VE4 = 5.43 3.57 = 1.86 V
"'$
25 mV
hib1 = hib2 = = 16.13 W, hie1 = hie2 = 1.6 KW
1.55 mA
25 mV
hib3 = = 35.2 W, 1 K||3 K = 0.75 KW
0.71 mA
hie3 = hfe3 ¥ hib3 = 100 ¥ 35.2 W = 3.52 KW

Its equivalent circuit is drawn as in Fig. 11.11(b) reflecting RE to base. From Fig. 11.11(b), the differ-
ential mode collector current (ic2) is expressed as
- is RB - 750is − 750is −750i s
ic2 = hfe ib2 = = = = = 15.9is
2{hib 2 + RB / h fe } 2(161
. + 750 /100) 2 × 23.6 47.2
Figure 11.11(b) Input side equivalent circuit
Figure 11.11(c) Output side equivalent circuit
VT VT V
hie = = = (1 + h fe ) T
I BQ I EQ / (1 + h fe ) I EQ
VT V VT V
hib = , hie = T = = (1/ + h fe ) T ,
I EQ I BQ I EQ / (1 + h fe ) I EQ
hie1 = 100 ¥ hib1 = 100 ¥ 16.1 = 1.6 KW
VT 25 mV ×100
hie4 = (1 + h fe ) @ = 35.2 W
I EQ 4 71 mA
hie4 (reflected at the base of T3) = 100 ¥ 35.2 = 3.52 KW

"'%
VT 25 mV ×100 2500
hie3 = (1 + h fe ) @ = = 32.5 W
I EQ 71 mA 71
iL -ic 2 ¥ 2.6 K i × 2.6 K

From Fig. 11.11c, 4
= = c2 = 0.005ic2
10 2.6 K + 7 K + 500 K 509.6 K
iL = 0.0051 ¥ 104ic2 = 51.0ic2 = 51.0(15.9is) = 810.9is
iL
= 810.9
lS
11.10 CS-CB Amplifier

Obtain voltage gain vo /vi for the cascaded circuit of common source and common base amplifiers
shown in Fig. 11.12(a). Its ac and equivalent circuits are in Figs. 11.12(b) and (c).
From Fig. 11.12(c), vo = hfb2ie2RC (11.10.1)
rd
ie2 = gmvi (11.10.2)
rd + hib
hie
hib = (11.10.3)
1 + h fe
Figure 11.12(a) CS-CB amplifier Figure 11.12(b) ac circuit of CS-CB stage
Figure 11.12(c) Equivalent circuit of CS-CB stage

"'&
Since hib2 << rd, Eqn. 11.10.2 reduces to

RG
ie2 = gm1vi = g m1 vi = gm1vi (11.10.4)
RG + Rs
vo = −h fb 2ie 2 RC = -gm1h fb 2 RC vi (11.10.5)
vo
Hence, voltage gain = = gm1RC (as hfb2 @ 1) (11.10.6)
vi
11.11 CS-CE Amplifier

Estimate the voltage gain vo /vi for the common source common emitter amplifier circuit shown in
Fig. 11.13(a).
Figure 11.13(a) CS-CE stage
- gm1vi rd ~ hie2
ib2 = , Ri2 = hie2||RB ª (11.11.1)
rd + Ri 2
h fe 2 g m1vi rd RC
vo = ic2RC = hfe2ib2RC = (11.11.2)
rd + hi 2
vo g m1h fe 2 rd RC
Hence, voltage gain = Av = = (11.11.3)
vi h/ie 2 + rd
Figure 11.13(b) ac circuit of CS -CE stage

"''
Figure 11.13(c) Equivalent circuit of CS-CE stage
vo g m1h fe 2 rd RC
Av = = = gm1hfe2 RC (11.11.4)
vi rd
11.12 CC-CB (Emitter Coupled) Amplifier

Obtain voltage gain vo /vi in the circuit of Fig. 11.14(a).
Figure 11.14(a) Emitter coupled amplifier Figure 11.14(b) ac circuit
In Fig. 11.14(c), Ri1 = hie1 + (1 + h fe1 )( RE hib 2 ) @ hie1 + (1 + h fe1 ) hib 2 = hie1 + hie 2 (11.12.1)
vo = − RC ic2 = RC h fb 2ie 2 (11.12.2)
− RE
ie2 = ( h fe1ib1 ) (11.12.3)
RE + hib 2
vi
ib1 = (11.12.4)
rs + hie1 + hie 2
vo = RC h fb 2ie 2 = h fb 2 RC
FG R IJ (h
E
fe1 )ib1 (11.12.5)
HR +h K
E ib 2
#
Figure 11.14(c) Equivalent circuit of emitter coupled amplifier
vo = h fb 2 RC
FG R IJ (h ) FG v IJ = h R h FG v IJ
E
fe1
i
fb 2 C fe1
i
(11.12.6)
H R K H r/ + h + h K
E s ie1 H 2h K
ie 2 ie1
vo
= h fb 2 R h G
F 1 IJ = FG h IJ FG R IJ = FG g R IJ (as h
fe1 C m1 C
@ 1) (11.12.7)
vi
C fe1
H 2h K H h K H 2 K H 2 K
ie1 ie1
fb2
11.13 FET-BJT Darlington

Obtain voltage gain and the output resistance for the circuit shown in Fig. 11.15(a).
Its equivalent circuit is drawn as in Fig. 11.15(b). From Fig. 11.15(b),

vgs = v s − hie ib − (1 + h fe )ib RE (11.13.1)
{rd + hie + (1 + h fe ) RE }ib = mvgs = µ {v s − hie ib − (1 + h fe )ib RE } (11.13.2)
{rd + (1 + µ )hie + (1 + µ )(1 + h fe ) RE }ib = mvs (11.13.3)
µvs
ib = (11.13.4)
rd + (1 + µ ){hie + (1 + h fe ) RE }
µvs (1 + h fe ) RE
vo = (1 + h fe )ib RE = (11.13.5)
rd + (1 + µ ){hie + (1 + h fe ) RE }
#
vo µ (1 + h fe ) RE
Hence, voltage gain Av = = (11.13.6)
vs rd + (1 + µ ){hie + (1 + h fe ) RE }
Figure 11.15(c)
For obtaining the output resistance, the circuit of Fig. 11.15(b) is redrawn as Fig. 11.15(c).
vgs = 0 − {hie + (1 + h fe ) RE }ib = {hie + (1 + h fe ) RE }( −io ) = {hie + (1 + h fe ) RE }io (11.13.7)
vo = hie io + µ{hie + (1 + h fe ) RE }io + rd io = {(1 + µ ) hie + µ (1 + h fe ) RE + rd }io (11.13.8)
vo
Ro = = (1 + µ )hie + µ (1 + h fe ) RE + rd (11.13.9)
io
11.14 FET-FET Cascode Amplifier

Analyze the voltage gain and output resistance of the FET cascode amplifier shown in Fig. 11.16(a).
Figure 11.16(a) Figure 11.16(b) ac circuit

#
vgs1 = vg1 vs1 = vs Rsid (11.14.1)

vgs2 = 0 vs2 = (rd + Rs )id + m vgs1 = ( r + R )i + m ( v - R i )
d s d s s d
= m vs - {rd + (1 + m ) Rs }id (11.14.2)
From Fig. 11.16(c), ( 2rd + RD + Rs )id = m vgs1 + m vgs 2 = m vs - m Rs id + m[ mvs - {rd + (1 + m ) Rs }id ]
or [2rd + RD + Rs ) + m (rd + (1 + m ) Rs + Rs ]id = m vs + m 2vs = m vs (1 + m )
m (1 + m )vs m (1 + m )vs
Hence, id = =
(2 + m )rd + RD + {1 + m + m (1 + m )}Rs (2 + m )rd + RD + {1 + m + m + m 2 }Rs
m (1 + m )vs
= (11.14.3)
(2 + m )rd + RD + (1 + m )2 Rs
Figure 11.16(c) Equivalent circuit Figure 11.16(d) Equivalent circuit for Ro
For output resistance, the circuit of Fig. 11.16(c) is further modified as Figs. 11.16(d), (e), and (f).
Figure 11.16(e)
#!
Figure 11.16(f) Figure 11.16(g)
− µ (1 + µ ) RD v s - m 2 RDvs
vo = RDid = 2
@ (11.14.4)
( 2 + µ )rd + RD + (1 + µ ) Rs mrd + RD + m 2 Rs
- m 2 RDvs - mRD vs − RDv s
= 2
= = (11.14.5)
mrd + m Rs rd + mRs 1
+ Rs
gm
vo - RD
For Rs = 0, Av = = = − g m RD (11.14.6)
vs 1/ gm
vgs1 = 0 Rsid (11.14.7)
vgs2 = 0 {rd + (1 + m)Rs}id (11.14.8)
2
Ro = {2rd + µrd + µ (1 + µ ) Rs + (1 + µ ) Rs }id = {( 2 + µ ) rd + (1 + µ ) Rs }id (11.14.9)
For input resistance, Fig. 11.16(g) is considered
vgs2 = vg2 vs2 = 0 vs2 = ( rd + RD )id + µv gs2 = ( rd + RD )id + µv s 2
= ( rd + RD )id + µ {rd + (1 + µ ) Rs }id = {( 2 + µ ) + (1 + µ ) 2 Rs }id
` = (2 + µ ) rd + (1 + µ ) 2 Rs (11.14.10)
vs2(1 + m) = (rd + RD)id = (2 + m)rd + m(1 + m)2Rs (11.14.11)
v r + RD r + RD r 1
Ri2 = s2 = d @ d = d @ = very low (11.14.12)
id 1+ µ µ µ g m2
The input resistance of the second stage becomes the load resistance for the first stage. In cascode
amplifier, the Miller capacitance CM = (1 + gmRL)Cgd = (1 + gmRi2)Cgd is very low. Thus, effective input
capacitance is Cgs + CM. Hence, bandwidth reduction in cascode amplifier is not much.
11.15. CS Differential Amplifier

Find the expression of voltage gain for the circuit in Fig. 11.17(a).
#"
Figure 11.17(a)
The small signal equivalent circuit of Fig. 11.17(b) is drawn as Fig. 11.17(c). As rd > R1, hib3 <<
R2, (1/hoe3) >> hib3, (1/hoe3) >> R3, and R >> R3 these assumptions are incorporated in Fig. 11.17(c)
which results in Fig. 11.17(d). Fig. 11.17(b) is the ac circuit of Fig. 11.17(a).
ie3 = (1 + hfe2)ib2 (11.15.1)
g m v gs R1
ib2 = (11.15.2)
R1 + hie 2 + (1 + h fe 2 )hib 3
Figure 11.17(b)

##
g mvgs R1 h fb 3 (1 + h fe 2 )ib 2 R3
vo = h fb 3ie 3 R3 = h fb 3 (1 + h fe 2 )ib 2 R3 = (11.15.3)
R1 + hie 2 + (1 + h fe 2 )hib 3
vo v (1 + h fe2 )h fb 3 R3 g m R1
Av = = o = (11.15.4)
v gs vi R1 + hie 2 + (1 + h fe2 )hib 3
11.16 FET-BJT Coupled Amplifier

Obtain voltages vo1 and vo2 for the circuit of Fig. 11.18a.
From Fig. 11.18(b), vgs = vi Rsis (11.16.1)
is = (1 + hfe)ib (11.16.2)
{hie + rd + (1 + h fe ) Rs }ib = mvgs = m (vi - Rs is ) = m{vi - Rs (1 + h fe )ib } (11.16.3)
As hie << rd, Eqn. 11.16.3 reduces to
{hie + rd + (1 + µ ) (1 + h fe ) Rs }ib = mvi (11.16.4)
µvi gm rd vi g m vi
ib = = = (11.16.5)
rd + (1 + µ )(1 + h fe ) Rs R gr
r S1 +
d
m d
(1 + h fe
U
)R Vs
1+ g m (1 + h fe ) Rs
T r d W
Figure 11.18(a)
#$
g m (1 + h fe ) Rs vi
vo1 = (1 + h fe )ib Rs = (11.16.6)
1 + g m (1 + h fe ) Rs
g mh fe Rs vi g m h fe RC vi g mh fe ( Rs + RC )vi
vo2 = vo1 + h fe ib RC = + = (11.16.7)
1 + g m (1 + h fe ) Rs 1 + g m (1 + h fe ) Rs 1 + g m (1 + h fe ) Rs
Example
If the upper and lower 3 dB frequencies of one of the three identical cascaded RC coupled amplifiers are
is 3.9 MHz and 64 Hz, obtain the overall 3 db frequencies.
fHn = FH IK
21/n − 1 f H = FH IK
21/ 3 − 1 f H = 0.51 ¥ 3.9 MHz = 1.99 MHz
fL fL 64 Hz
fLn = = = = 125.5 Hz
21/ n − 1 21/ 3 − 1 0.51
Bandwidth of one stage of the amplifier = 3.9 MHz 64 Hz @ 3.9 MHz. Thus, the overall bandwidth
of three identical cascaded amplifier stages = 1.99 MHz 125.5 Hz @ 1.99 MHz.
This example indicates that due to cascading effect, the upper 3 dB frequency is reduced and lower
3 dB frequency is increased considerably. Thus, the bandwidth of the identical cascaded stages is
reduced considerably, i.e. by the factor 21/n − 1 .
#%
1. Show that cascode amplifier shown in Fig. Miller capacitor present across the input
11.19 works as a wideband amplifier pro- side is given as
ducing larger voltage gain than CE con- CM = (1 + gmRL)Cm = (1 + gmhib)Cm
figuration.
h fe 1
Solution: = (l + hib )Cm = (l + hib )Cm
hie hib
V1 Vbe
h11 = = = hiel = (1+1)Cm = 2Cm
i1 V =0
ib1 This way the cascode connection reduces
2
The load to T1 = hib2 which is very small the internal feedback factor h12 enormously
from few ohms to fraction of ohms. Typi- and provides very low Miller capacitance.
cally we can assume it to be 10 W. Hence, Hence tunability and stability of the cascode
above equation is satisfied. connection becomes excellent. As the out-
put resistance of the cascode connection is
ic 2 ic 2 ie2 i i 1/hob2, it can be connected to very large
h2l = = ¥ = c 2 ¥ c1 load resistance. Thus, it results into large
ib 2 v2 = 0
ie2 ib 2 ie2 ib1
gain over a wide range of frequency.
= a2hfe1 2. The lower cut-off frequency of 1st stage
of the amplifier is 100 Hz and that of the
v1 v1 vx
hl2 = = ¥ = hre1 ¥ hrb2 2nd stage is 200 Hz. Similarly the upper
v2 i1 = 0
v x v2 cut-off frequency of the 1st stage is
140 kHz and that of 2nd stage is 100 kHz.
ic 2 ic 2 Find out the overall higher and lower cut-
h22 = = = hoe2
v2 i1 = 0
(1/ hob 2 )ic 2 off frequencies if the two stages are cas-
caded.
Solution:
If overall lower and upper cut-off frequen-
cies are denoted as fL and fH respectively.
Similarly, the lower and upper cut-off fre-
quencies of individual stages are denoted
fL1, fL2 and fH1 , fH2. Then these frequen-
Figure 11.19 cies are approximately related as
Since, h11 = hiel, h2l = a2hfel @ hfel, h22 = 1 1

hoe2, hl2 = hrel ¥ hrb2, the feedback from Ê f ˆ
2
Ê f ˆ
2
the output to the input is negligible, reduc- 1+ Á H ˜ 1+ Á H ˜

Ë fH1 ¯ Ë fH 2 ¯
ing the reverse internal feedback.
Following the CB configuration reduces the 2 2
high frequency parameter of the feedback 1 ÏÔ Ê f H ˆ ¸Ï ÔÔ Ê f H ˆ ¸Ô = 2
= , Ì1 + ˝Ì1 + ˝
effect of Cm in CE configuration. The 2 Ô ÁË f H 1 ˜¯ ÔÔ ÁË f H 2 ˜¯ Ô
Ó ˛Ó ˛
#&
2 2 2 2 2 2 2 2
Ê f ˆ Ê f ˆ Ê f ˆ Ê f ˆ Êf ˆ Êf ˆ Êf ˆ Êf ˆ
or, Á H ˜ + Á H ˜ + Á H ˜ + Á H ˜ = 1 1 + Á L1 ˜ + Á L 2 ˜ + Á L1 ˜ Á L 2 ˜ = 2,
Ë f H1 ¯ Ë fH 2 ¯ Ë f H1 ¯ Ë fH 2 ¯ Ë fL ¯ Ë fL ¯ Ë fL ¯ Ë fL ¯
or, fH4 + f H2 (f H1
2 2
+ f H1 2
) f H1 2
f H2 = 0, f L4 - fL2 (f L21 + f L22) f L21 f L22 = 0
(1402 + 1002 ) 1402 ¥ 1002 = 0, f L4 - f L2 (l00 2 +2002) 4 ¥ l08 = 0,
or, fH4 +2.96 ¥ l04 f H2 8
1.96 ¥ l0 = 0, f L4 - 5 ¥ l04 fL2 4 ¥ l08 = 0,
f H2 =
5 ¥ 104 ± 25 ¥ 108 + 16 ¥ 108
2.96 ¥ 10 4 ± 8.7616 ¥ 108 + 7.84 ¥10 8 f L2 =
2
2
2.96 ¥ 10 4 ± 16.60 ¥ 108 5 ¥ 104 ± 25 ¥ 108 + 16 ¥ 108
= =
2 2
2.96 ¥ 10 4 ± 4.0745 ¥ 10 4 5 ¥ 104 ± 6.4 ¥ 10 4 11.4 ¥ 10 4

= = =
2 2 2
4
= 5.7 ¥ l0
1.114406 ¥ 10 4
= = 5.573 kHz fL = 238 Hz
2
3. Fig. 11.20(a) is the circuit of two-stage
1 1 1
= , common emitter amplifier with transistor
Ê f ˆ
2
Ê f ˆ
2 2 components gm = 50 mS , rp = 1 K, Cp =
1 + Á L1 ˜ 1 + Á L1 ˜ 31 pF, Cm = 4 pF. The passive compo-
Ë fL ¯ Ë fL ¯
nents connected to this amplifier are R1|
ÏÔ Ê f ˆ 2 ¸Ï 2 |R2 = 1 KW, RC = 2 KW, rs = 0.6 KW, and
L1 ÔÔ Ê f L 2 ˆ ¸Ô = 2
Ì1 + Á ˝Ì1 + ˝ RL = 0.5 KW. Calculate the midband gain
Ë f L ˜¯ ÔÔ ÁË f L ˜¯ Ô and the bandwidth of the amplifier.
ÓÔ ˛Ó ˛
Solution:
Figure 11.20(a)
#'

For Midband gain the load resistance to 1st 0.4 K
stage = 1| |1| |2 = 0.4 K vp2 = gm vp1 = gmvp1
1 + 0.4KSC2
Load resistance to 2nd stage = 0.5| |2 =
0.4 K 0.4 K 0.4 K
= gm ¥
1 + 0.4KSC2 1 + 0.4KSC2
vs ¥ 0.5 K 5v
vp1 = = s, 0.5vs /1.1
0.6 K + 0.5 K 11
Ê w 0.3 KC1 ˆ
Vp2 = gmvp1 ¥ 0.4 K, vo = 0.4 K ¥ gm vp2 1.1Á + j ˜
Ë 1.1 ¯
= 0.4 K ¥ gm2 0.4 Kvp1
= gm 0.4 K 0.5vs /1.1
5v 0.8 ¥
vo = 0.4 K ¥ g 2m 0.4 K s = ¥ 50 ¥ 1 + j 0.4w KC2 Ê w 0.3KC1 ˆ
11 1.1Á + j ˜
11 Ë 1.1 ¯
50vs = 181.8vs
1 109
v w H1 = =
Hence, mid-band gain = o = 182 0.4KC2 0.4 ¥ 115
vs
= 21.74 Mrad/s, fH2 = 3.46 MHz
High-frequency response
4. The BJT difference amplifier shown in
C1 = Cp + (l + gmRL)Cm = 31 + (l + 50 ¥
Fig. 11.21 has component value RC = 50 K,
0.4)4 = 115pF = C2
RE = 10 K , and rs = 10 K. The transistor
0.5 K parameters are rk = 50 K, bo = 2000, ro =
vs
1 + 0.5KSC1 400K . Determine differential and common
vp l = mode gains and CMRR for the amplifier.
0.5 K
rs
1 + 0.5KSC1
0.5Kvs
=
0.6 K + 0.5 K + 0.5 K ¥ 0.6 KSC1
0.5vs 0.5vs /1.1
= =
1.1 + jw0.3 KC1 Ê w 0.3KC1 ˆ
1.1Á + j ˜
Ë 1.1 ¯
0.5vs /1.1 1.1
= where, wH2 =
Ê w ˆ 0.3KC1
1.1Á + j ˜
Ë wH2 ¯
1.1 ¥ 109
= = 32 Mrad/s, fH2 = 5.09 MHz Figure 11.21
0.3 ¥ 115
#
Solution: Using simplified equations of Adm and Acm

50 ¥ 400 K yields CMRR as
Effective load = RL = RC| |ro =
450 Adm g m RL
CMRR = = = 2gmRE
= 44.44 K, Acm RL / 2RE
vo1 v h fe RL Thus, for high CMRR, the value of RE
Adm = = o2 = should be very large. So current source
vdm vdm rs + rbb + rp
with high internal resistance should be
h fe RL used in place of RE.
= = gmRL (RL = RC| |ro)
rp 5. A relatively loaded and resistively biased
differential amplifier circuit is shown in
h fe RL 2000 ¥ 44.44 Fig. 11.22. Neglecting the base currents
= = = 1481
rs + rbb + rp 10 + 50 and assuming matched transistors with VA
= • and b = 100. Use VT = 26 mV, VBE(ON)
vo1 v h fe RL = 0.7 V and VCE(SAT) = 0.2 V. Determine
A cm = = o2 =
vdm vdm rs + rbb + rp + 2h fe RE (a) the values of RC and RE to meet the
specifications as, Deferential mode gain
h fe RL h fe RL RL (double ended) = 500, common mode re-
= = =
rp + 2h fe RE 2h fe RE 2 RE jection ratio is = 500, differential mode in-
put resistance = 2 MW, and (b) determine
h fe RL the minimum values of VCC and VEE such
=
rs + rbb + rp + 2h fe RE that the transistors remain in the forward
active region under zero signal condition.
2000 ¥ 44.44 2000 ¥ 44.44 Assume that the dc common mode input is
= =
10 + 50 + 4000 ¥ 10 40060 zero.
= 2.22 Solution:
(a) Ril, = Ri2 = 2hie = 2 MW, hie = 1 MW,
Adm
CMRR =
Acm h fe
gm = = 100 mS
hie
h fe RL rs + rbb + rp + 2h fe RE
= ¥
rs + rbb + rp h fe RL h fe RC
Adm = gmRC = 500 = , Acm = ,
hie 2 RE
rs + rbb + rp + 2h fe RE
= Adm
rs + rbb + rp Hence, CMRR = = 2gmRE = 500
Acm
2h fe RE 500
= 1+ Hence, RE = = 2.5 MW
rs + rbb + rp 2 ¥ 100m S
40000 100 I
= 1+ = 667.67 = 20 log 667.67 R = 500, RC = 5 MW, gm = C ,
60 1 MÙ C VBE
= 56.5 dB IC = 100 mS ¥ 0.7
#
For zero dc input, 2REIE = VEE VBE,

VEE = 0.7 + 2 ¥ 2.626 mA ¥ 2.5 MW
= 13.83V IC = bIB = 100 ¥ 26 ¥ l0 9A
= 2.6 mA
VCC = RCIC + VCE + 2IERE VEE
= 5 ¥ 2.6 + 0.2 + 2 ¥ 26 ¥ l0 6 ¥ l00 ¥
2.5 ¥ l0 6 13.83 = 5 ¥ 2.6 + 0.2 +
2 ¥ 2.626 ¥ 2.5 13.83 = 13 + 0.2 +
13.13 13.83 = 12.5 V
6. In the amplifier circuit shown in Fig.
Figure 11.22
11.23, determine the value of R such that
T2 is biased at VCE2 = 7.5 V neglecting its
VT 26 mV 26 mV base currents. Also, determine the small
(b) hie = = , IB =
IB IB 1 MW signal input impedance of T1 and T2, if
= 26 ¥ l09A, IE = (l + hfe)IB both of them have b = 100 . Use V T =
= 101 ¥ 26 nA = 2.626 mA 26 mV.
Figure 11.23
Solution: = 1.11 mA, IC2 = IRC = 1.11 mA,

(b + 2) VCC VCE 2 12 7.5
IRC = ICl + 2IB = (b + 2)IB = , IC2 = ,R=
b R 1.11 mA
VBE 4.5
IB2 = IB1 = = = 4.1 KW
rp 1.11 mA
(b + 2) IC1RC Input resistance of T1 = RB + hie1
VCC = RCIRC + VBE1 = +
b VT (b + 1)VT
VBE2, Ril = RB + = RB + = RB +
I B1 I E1
b V VBE1 100 12 0.7 101 ¥ 0.026
IC1 = ¥ CC = ¥ = 1 K + 2.366 K = 3.366 KW
b +2 RB 102 10 K 1.11
#
VT h fe
Ri2 = lClhle2 = 1.11 mA = 1.11 mA
I E2
0.026 ¥ 100
= 2.6 W
1.11 mA
7. The circuit in Fig. 11.24(a) is biased such
that VCE2 = 0 when vs = 0 . Neglecting the
base currents of both transistors and for-
ward bias across VBE for both transistors
to be 0.7 V , obtain the value of RE. Draw
the mid-frequency equivalent circuit as-
suming hie = 3 K, hfe = 200, hre= hoe = 0. Figure 11.24(a)
Solution:
=2.61 mA (neglecting base current)
61.5KIC2 VEC2 + 3KIC2 + 6 = 0, 4.5KIC2
6 0.7
= 12 V, IC2 = 12/4.5 K = 2.67 mA Vi = 0, VBE1 + REIE1 = 6, RE =
2.61 mA
VRE2 = 6 2.67 ¥ 1.5 = 4 V, VRC1 = 4 + 0.7 5.3
= 4.7 V = = 2.03 KW
2.61 mA
4.7
ICI = = 2.61 mA, ICI = IE1 = 1RCI
1.8 K
8. Both BJTs in Fig. 11.25 are identical with

hfe = 100 and hie = 25 W at IC = 1 mA. The
circuit has a common mode rejection ratio
of 100. What is the (a) differential gain
vo
and common mode gain of the
vi1 vi 2
circuit. (b) output voltage for vi1 = l0l0mV
and vi2 = 990mV ?
Solution:
1
IC1 = IC2 = 1 mA, IB = = 0.01 mA,
100
IC3 = 2 mA, IB3 = 0.02 mA, IE3 = 2.02 mA
Figure 11.25
#!
4.3 9. Obtain the mid frequency gain of the am-

VRE = 5 0.7 = 4.3 V, RE = = 2.13 K, plifier circuit in Fig. 11.26 with high value
2.02
of beta of the BJT.
Practical value of RE = 2.2 K
RC RC
ADM = =
Ê rs ˆ 2hie
2 Á hie +
Ë 1 + h fe ˜¯
1 K
= = 20
0.05 K
ADM 20
CMRR = 100 = = , ACM = 0.2
ACM ACM
The exact value of common mode gain is Figure 11.26
given as
RC Solution:
RC
ACM = =
Ê rs ˆ hie + 2 RE VT
0.7 + 1KIEI = 5.7, IEI = 5 mA, rp =
Á hie + 2RE + 1 + ˜ IB
Ë h fe ¯
(1 + h fe )VT (1 + h fe )25
1 K = =
= = 0.226 I E1 5
4.4 K + 0.025 K
5
(b) vo = ACMvc ADMvd = ADMvd ACMvC rp = (1 + hfe)
(ACM and ADM are negative) h fe RC
Av =
vd = vi1 vi2 = 1010 990 = 20 mV, hie + (1 + h fe ) RE
V1 + V2 1010 + 990
VC = = h fe RC RC
2 2 = =
5(1 + h fe ) + (1 + h fe ) RE 5 + RE
= 1000 mV = 1 V
vo = 20 ¥ 20 mV 0.2 ¥ l = 400 mV RC 1.2
0.2 @ = = 1.2
RE 1
= 0.400 0.2 = 0.2 V
12
Feedback in Amplifiers
12.1 Introduction
The effects of feedback were first observed when devices were used beyond frequencies for which
they were designed and fabricated. A part of the output signal was observed to be present across the
input terminals of the device through its inter-lead capacitance. Hence, intentionally or unintentionally
the importance of feedback came into being. In RC coupled amplifier a small value of resistance in the
emitter lead and between collector to base working as negative feedback stabilizes the quiescent point
but reduces the gain.
The word feedback gives an impression that at least some portion of the output voltage is fed back to
its input again in any electronic amplifier/ circuit. If the feedback voltage is in phase with its original
input, the resultant input is equal to the sum of the original input plus the feedback input. Since the
feedback voltage adds to its original input voltage, it is called positive feedback.
On the contrary, if the feedback voltage is out of phase to the original input voltage, it subtracts from
the original input voltage and the resultant input is less than the original input. Since the feedback voltage
subtracts the original voltage, it is called negative feedback. It is customary to explain the principle of
feedback with the help of block diagram as shown in Fig. 12.1. A fraction bvvvo of the output vo is fed
back to the input in phase opposition of the original input signal vi.
vo
The voltage gain without feedback = Avv = (12.1.1)
vi
and the feedback voltage vf = bvvvo (12.1.2)
where bvv = gain or attenuation of the b-network.
515
Figure 12.1 Feedback system block diagram
The effective input vi of amplifier is obtained by writing the loop equation as

v s vi v f = 0 (12.1.3)
vs = vi + vf
vo (1 + Avv b vv )v o
vs = vi + bvvvo = + bvvvo = (12.1.4)
Avv Avv
vo Avv
Voltage-gain with feedback = Avf = = (12.1.5)
vs 1 + Avv b vv
Equation 12.1. 5 indicates that the voltage gain is reduced with negative feedback by a factor (1 +
Avvbvv).
Advantages of negative feedback

∑ Increases bandwidth
∑ Reduces noise
∑ Stabilizes gain
∑ Reduces harmonic distortion
∑ Decreases phase and frequency distortion
∑ Increases or decreases input/output resistance as per feedback configuration
Disadvantage of negative feedback

∑ Reduces the gain
12.1.1 Sensitivity to Gain Variation

We know that the gain of any type of amplifier may change due to change in active or passive components
that control the gain such as power supply variations, active parameter variation of BJT, etc. It is but
natural that one would like to achieve zero sensitivity because once the amplifier is designed for a
specific gain it should not change due to change in the components, whether active or passive. This is
the ideal condition. The practical amplifiers are sensitive to the gain variation. We would like to examine
how this sensitivity can be decreased with negative feedback. We also know that
516
Avv
Avf = (12.1.6)
1 + Avv b vv
The sensitivity of Avf (Aif) w.r.t. the variation in Avv is defined as the ratio of the fractional change in
Avf to the fractional change in Avv , i.e.
dAvf / Avf
S= (12.1.7)
dAv / Av
Writing partial differential of Eqn. 12.1.6 yields
dAvf (1 + Avv b vv ) - Avv b vv 1
= 2
= (12.1.8)
dAvv (1 + Avv b vv ) (1 + Avv b vv ) 2
dAvv
dAvf = (12.1.9)
(1 + Avv b vv ) 2
dAvf
=
dAvv (1 + Avv b vv )
=
dAvv FG 1 IJ (12.1.10)
Avf 2
(1 + Avv b vv ) Avv H K
Avv 1 + Avv b vv
dAvf / Avf
1
Thus S= = (12.1.11)
dAv / Av 1 + Avv b vv
Eqn. 12.1.11 indicates that the % change in Avf is reduced by a factor of (1 + Avvbvv) in Avv .
Example
An amplifier having negative feedback produces gain of 40 dB with 5% change due to its internal gain
variation. Calculate the open loop forward gain of the amplifier.
Solution
20log
FG v IJ = 40 = 20log 10
o 2
and
vo
= 100 = Avf =
Av
Hv K
s vs 1 + Av b
1
S= = 0.05,
1 + Av b
1 + Avb = 20,
Av
= 100
1 + Av b
Av = (1 + Avb) 100 = 20*100 = 2*103.
For the sacrifice in the gain from 2*103 to 100, considerable amount of stability has been
achieved.
12.1.2 Bandwidth Modification

We know that the gain of the amplifier at both low and high frequencies falls as indicated in Fig. 12.2.
517
Figure 12.2 Frequency response of RC coupled amplifier
The ratio of its output to input voltage, i.e. voltage gain at high and low frequencies can be expressed
as
Ao Ao
Av (w H ) = and Av (w L ) = (12.1.12)
w w
1+ j 1- j L
wH w
where, wH and wL are upper and lower 3 dB cut-off frequencies.
The change in upper and lower cut-off frequencies can be accounted as
w
Ao / (1 + j )
wH Ao Ao 1
Avf (w H ) = = = ¥
w w 1 + Ao b 1 + j w
1 + Ao b / (1 + j ) 1 + Ao b + j
wH wH w H (1 + Ao b )
Ao 1
= ¥ (12.1.13)
1 + Ao b 1 + j w
w *H
where w *H = (1 + Aob)wH ) = Upper 3 dB cut-off with feedback (12.1.14)
Equation 12.1.14 illustrates that the upper 3 dB cut-off of an amplifier has been increased with
negative feedback by a factor (1 + Aob) i.e. from wH to (1 + Aob)wH .
Similarly, the effect of negative feedback on lower 3 dB cut-off is estimated as
wL
Ao / (1 - j )
w Ao Ao 1
Avf (w L ) = = = ¥
wL w L 1 + Ao b wL
1 + Ao b / (1 - j ) 1 + Ao b - j 1- j
w w w (1 + Ao b )
Ao 1
= ¥ (12.1.15)
1 + Ao b w *L
1- j
w
* wL
where wL = = lower 3 dB frequency with feedback (12.1.16)
1 + Ao b
The effect of negative feedback on the bandwidth of the amplifier is shown by its plot of gain versus
frequency as in Fig. 12.3.
518
Figure 12.3 Effect of negative feedback on frequency response
wL
Bandwidth with feedback = w *H w *L = (1 + Aob)wH @ (1 + Aob)wH (12.1.17)
1 + Ao b
Equation 12.1.17 demonstrates that there is tremendous increase in the bandwidth with negative
feedback.
12.1.3 Noise Reduction

The effect of negative feedback on noise can be analyzed by assuming cascaded blocks of amplifiers
and introducing noise at different points as depicted in Fig. 12.4. From this figure.
Figure 12.4 Effect of negative feedback on noise
ve = vi bvo + vn1 (12.1.18)

vo = [{vi bvo + vn1) A1 + vn2}A2 + vn3]A3 (12.1.19)
or, vo (1 + A1A2A3b ) = (vi + vn1) A1A2A3 + vn2A2A3 + vn3A3 (12.1.20)
(vi + vn1 ) A1 A2 A3 (vn2 ) A2 A3 (v n3 ) A3

vo = + + (12.1.21)
1 + A1 A2 A3b 1 + A1 A2 A3b 1 + A1 A2 A3b
As, A1A2A3b >>1, Eqn. 12.1.21 reduces to
( vi + v n 1 ) v n 2 v
vo = + + n3 (12.1.22)
b A1b A1 A2 b
519
Equation 12.1.22 illustrates that latter the noise introduced more it is reduced. The reduction in the
noise can be shown graphically as in Fig. 12.5.
Figure 12.5 Noise reduction with negative feedback
12.2 Classification of Feedback

The feedback in most simple way is classified as:
∑ Positive feedback
∑ Negative feedback
The other type of feedback classification may be:
∑ Voltage feedback
∑ Current feedback
Feedback can also be classified as:
∑ Series feedback
∑ Shunt feedback
The combination of all the above classifications results in basically four types of feedback as described
below:
∑ Voltage series feedback
∑ Current series feedback
∑ Voltage shunt feedback
∑ Current shunt feedback
All the four types of feedback blocks are arranged in Figs. 12.6, 12.7, 12.8, and 12.9.
Figure 12.6 Voltage series feedback

520
Figure 12.7 Current series feedback
Figure 12.8 Voltage shunt feedback
Figure 12.9 Current shunt feedback
12.2.1 Voltage Series Feedback

The output voltage is directly related to the input voltage in voltage series feedback amplifier and hence,
it is called voltage amplifier. The unit of gain of the voltage amplifier is dimensionless. Its feedback
network also has output and input as voltages and hence, its feedback factor b is also a dimensionless
quantity. Now, the voltage gain of voltage amplifier and its b-factor of Fig. 12.6 is described as
521
vo vf
Avv = and bvv = (12.2.1)
vi vo
Input resistance including the feedback of the circuit shown in Fig. 12.6 is described as
v
Rif = (12.2.2)
ii v0 = 0
From Fig. 12.6
vs = vi + vf, (12.2.3)
and vi = R ii i (12.2.4)
Combining Eqns. 12.2.1, 12.2.2, 12.2.3, and 12.2.4 yields
vs = vi + bvo = vi + Avv bvv vi = (1 + Avvbvv)vi = (1 + Avv bvv)Riii (12.2.5)
vs
Rif = = (1 + Avv bvv)Ri (12.2.6)
ii
Equation 12.2.6 reveals that the input resistance of voltage series feedback amplifier is increased by
a factor (1 + Avvbvv)
The circuit of Fig. 12.6 is reduced to Fig. 12.10 to obtain its output resistance. Its output resistance
is defined as
vo
Rof = (12.2.7)
io
v s =0
vo = Ro io + Avvvi (12.2.8)
For vs = 0, vf + vi = 0 (12.2.9)
vi = vf = bvvvo (12.2.10)
vo = Roio Avv bvvvo (12.2.11)
(1 + Avv bvv)vo = Roio (12.2.12)
vo Ro
Rof = = (12.2.13)
io 1 + Avv b vv
Figure 12.10 Voltage series feedback for output resistance

522
Equation 12.2.13 states that the output resistance of an amplifier with voltage series feedback is
decreased by a factor of (1 + Avvbvv).
12.2.2 Current Series Feedback

The current series feedback amplifier relates its output current with its input voltage and the ratio of the
output current to the input voltage has the dimension of transconductance as shown in Fig. 12.7. Hence
the basic amplifier in this configuration is transconductance amplifier. Its feedback network, on the
contrary, relates to output voltage w.r.t. input current. Thus, its gain and b factor are described as
io vf
Aiv = , bvi = (12.2.14)
vi io
Input resistance including the feedback of the circuit shown in Fig. 12.7 is described as
vs
Rif = (12.2.15)
ii
vo =0
From Fig. 12.7
vs = vi + vf
vs = vi + bviio
vs = vi + Aivbvivi = (1 + Aiv bvi)vi (12.2.16)
vi = R ii i (12.2.17)
vs = vi + bvivo = (1 + Aivbvi)vi = (1 + Aiv bvi)Riii (12.2.18)
vs
Rif = = (1 + Aiv bvi)Ri (12.2.19)
ii
Equation 12.2.19 reveals that the input resistance of voltage series feedback amplifier is increased by
a factor (1 + Aiv bvi).
In order to obtain the output resistance, Fig. 12.7 is simplified as Fig. 12.11 with the condition
vs = 0.
Figure 12.11 Current series feedback for output resistance

523
For vs = 0, vi = vf = bviio (12.2.20)

vo v
io = Aivvi + , io = Aivbviio + o (12.2.21)
Ro Ro
vo
(1 + Aivbvi)io = (12.2.22)
Ro
vo
Hence, the output resistance including feedback = Rof = = (1 + Aiv bvi)Ro (12.2.23)
io
Equation 12.2.23 describes that the output resistance of current series feedback amplifier is increased
by a factor of (1 + Aivbvi).
12.2.3 Voltage Shunt Feedback

The voltage shunt feedback amplifier relates its output voltage with its input current and hence, the ratio
of its output to input quantity has the dimension of transresistance. Its feedback network, however,
relates its output current w.r.t. its input voltage from Fig. 12.8 as
vo if
Avi = , biv = (12.2.24)
ii vo
is = ii + if (12.2.25)
is = ii + bivvo = ii + bivAviii = (1 + bivAvi)ii (12.2.26)
vi
Substituting the value of ii = in Eqn. 12.2.26 results in
Ri
vi
is = (1 + bivAvi) (12.2.27)
Ri
Its input resistance including feedback = Rif
v Ri
Rif = i = (12.2.28)
is 1 + Avi b iv
Equation 12.2.28 reveals that the input resistance of voltage shunt feedback amplifier is decreased by
a factor (1 + bivAvi).
In order to obtain the output resistance, Fig. 12.8 is simplified as Fig. 12.12 with condition is = 0. It
is defined as
vo
Rof = (12.2.29)
io
is =0
524
Figure 12.12 Voltage shunt feedback
For is = 0, ii = if (12.2.30)

ii = bivvo (12.2.31)
Writing loop equation in Fig. 12.12 yields
Roio + Aviii = v o (12.2.32)
vo = Roio Aiv bvivo (12.2.33)
(1 + Aivbvi)vo = Roio
Hence, output resistance including feedback = Rof
vo Ro
Rof = = (12.2.34)
io 1 + Avi b iv
Equation 12.2.34 states that the output resistance with voltage shunt negative feedback is decreased
by a factor of (1 + Avibvi).
12.2.4 Current Shunt Feedback

The current shunt feedback amplifier has direct relationship between its output and input currents.
Hence, the ratio of its output to input quantities is dimensionless as is defined from Fig. 12.9 as
i if
Aii = o , bii = (12.2.35)
ii io
is = ii + if (12.2.36)
is = ii + biiio = ii + Aiibiiii = (1 + Aiibii)ii (12.2.37)
Also vi = R ii i (12.2.38)
525
Now substituting the value of i from Eqn. 12.2.38 in 12.2.37 gives

vi
is = (1 + Aiibiv) (12.2.39)
Ri
Ri
Its input resistance with feedback = Rif = (12.2.40)
1 + Aii b ii
Equation 12.2.40 tells that the input resistance of an amplifier with current shunt feedback is de-
creased by a factor of (1 + Aiibii).
Figure 12.9 is rearranged as Fig. 12.13 with the condition is = 0 to obtain the output resistance.
For is = 0, ii = if = biiio (12.2.41)
Writing node equation at the output node results in
vo
io = + Aiiii (12.2.42)
Ro
Figure 12.13 Current shunt feedback
vo
io = Aiibiiio
Ro
vo
(1 + Aiibii)io = (12.2.43)
Ro
vo
Rof = = (1 + Aiibii)Ro (12.2.44)
Ro
From Eqn. 12.2.44 it is clear that the output resistance with current shunt feedback increases by a
factor of (1 + Aiibii). Practical circuit of BJT amplifiers utilizing different types of feedbacks shall now
be discussed.
526
The input resistance and output resistances of different feedback topology is summarized as below.
Feedback topology Rif ROf
Voltage series Ri(1 + Ab) RO /(1 + Ab)
Voltage shunt Ri /(1 + Ab) RO /(1 + Ab)
Current series Ri(1 + Ab) RO (1 + Ab)
Current shunt Ri /(1 + Ab) RO (1 + Ab)
12.3 Practical Circuit of Voltage Series Feedback

The emitter follower amplifier is called voltage series feedback amplifier. It is also known as voltage-
feedback voltage-error type and is shown in Fig. 12.14(a) with its equivalent circuit as Fig. 12.14b.
Figure 12.14(a) Practical circuit of voltage series feedback
From Fig. 12.14(a), vi = ve + vo = ve + vf (12.3.1)

From Fig. 12.14(b), hieib + REie = hieib + RE(1 + hfe ) ib (12.3.2)
vo = ve = vf = REie = RE(1 + hfe) ib (12.3.3)
Figure 12.14(b) Equivalent circuit Figure 12.14(c) Equivalent circuit with RE = 0
Without feedback vs = vi = hie ib (12.3.4)

vo vo RE (1 + h fe )ib
Avv = voltage-gain without feedback = = =
v s vi hie ib
527
RE (1 + h fe ) RE h fe
= @ = gmRE (12.3.5)
hie hie
vf vo
bvv = = =1 (12.3.6)
vo vo
Avvbvv = T = (gmRE)(1) = gmRE (open loop gain) (12.3.7)
Its input resistance Ri without feedback can be obtained from the circuit of Fig. 12.14(c) as
Ri = hie (12.3.8)
Now its input resistance with feedback is
Rif = Ri(1 + T) = hie (1 + gmRE) = hie + hfe RE (12.3.9)
Its output resistance without feedback is expressed as
vo
Ro = (12.3.10)
io
ib = 0, vi = 0
Hence, for obtaining the output resistance the circuit of Fig. 12.14(b), it is simplified as Fig. 12.14d.
No feedback means active current (1 + hfe)ib flowing through RE does not exist, i.e. they are open
circuited. In other words ib = 0. Thus, output resistance without feedback, i.e. Ro = RE. Now its output
resistance with feedback comes out to be
Ro RE 1
Rof = = = (12.3.11)
1+ T (1 + h fe ) RE gm
1+
hie
Figure 12.14(d) Equivalent circuit for output resistance
Example
Obtain all pertinent quantities for the circuit of voltage feedback voltage error with following of the
circuit parameters; hie = 1 K, hoe = 5 mS, hfe = 100, RE = 1 K.
Avv = 100, bvv = 1, T = 100,
Ri = 1 K, Rif = 1 K + 100 mS ¥ 1 K @ 100 kW
1K 1K
Ro = RE = 1 K, Rof = = @ 10 W
1 + T 1 + 100
528
12.3.1 Voltage Shunt Feedback

A simple practical circuit of voltage shunt feedback amplifier is drawn as in Fig. 12.15(a). We see that
at the base terminal in Fig. 12.15(a) both feedback current if and the original input current is combines
and hence, its feedback quantity is in the form of current. Its equivalent circuit is drawn as in
Fig. 12.15(b).
v
Avi = c (12.3.12)
ib
For no feedback RF is open circuited. Hence, is = ib.
vo = vc = hfeibRc (12.3.13)
vc - h fe ib RC
Avi = = = hfe RC (12.3.14)
is ib
Figure 12.15(a) Practical circuit of voltage shunt feedback
Figure 12.15(b) Equivalent circuit of practical voltage shunt feedback
if
biv = and (12.3.15)
vc
h fe ib RC
if = (12.3.16)
hie + RC + RF
biv =
FG h fe ib RC IJ F - 1 I = -1
(12.3.17)
Hh ie + RC + RF K GH h i R JK h
fe b C ie + RC + RF
h fe RC
Avibiv = (12.3.18)
hie + RC + RF
529
For no feedback RF = •. Hence, right side circuit in Fig. 12.15(b) is meant for obtaining the input
resistance without feedback. The input resistance without feedback is
Ri = hie (12.3.19)
Then its input resistance with feedback is expressed as
Ri hie
RiF = = (12.3.20)
1+ T h fe RC
1+
hie + RC + RF
Its output resistance can be expressed as
1
Ro = (12.3.21)
hoe
In order to satisfy the condition of is = 0, the circuit of Fig. 12.15(b) is modified as Fig. 12.15(c).
1
Ro = RC @ RC (12.3.22)
hoe
Hence, its output resistance with feedback is
Ro RC
Rof = = (12.3.23)
1+ T 1 + h fe RC / (hie + RC + RF )
Figure 12.15(c) Simplified circuit for Ro
Example
Obtain all pertinent quantities for the circuit of voltage feedback current error with following of the
circuit parameters; hie =1 K, hoe = o, hfe = 100, RC = 1 K, RF =20 K.
Avi = hfeRC = 100 ¥ 1 K = 100 K,
-1 1 1
biv = = = = 0.045 S
hie + RC + RF (1 + 20 + 1) K 22 K
100 K
T= = 4.55,
22 K
1K 1K
Ri = 1 K, Rif = = = 0.220 KW
1+ T 1 + 4.55
1K 1K
Ro = RE = 1 K, Rof = = = 0.220 KW
1+ T 1 + 4.55
530
12.3.2 Current Series Feedback

A practical circuit diagram of current-feedback voltage-error with its block diagram representation is
shown in Fig. 12.16(a). Its equivalent circuit is drawn as in Fig. 12.16(b).
Figure 12.16(a) Practical circuit of current series feedback
Figure 12.16(b) Equivalent circuit of current series feedback with RE = 0
From Fig. 12.16(b) it is clear that the same output current (ic @ ie) flows in the feedback resistance.
Hence, it is treated as transconductance amplifier. Thus, output is in the form of current and the
feedback is in the form of voltage. Thus, it is given the name of current series feedback.
ic = hfeib (12.3.24)
vs = vi + ve (12.3.25)
Effective input without feedback vs = vi = hie ib (ve = 0) (12.3.26)
iC h fe ib h fe ib
Hence, gain without feedback = Aiv = = = = gm (12.3.27)
vi vi hie ib
vf ve (1 + h fe )ib RE
Feedback factor = bvi = = =
ic ic h fe ib
(1 + h fe ) RE h fe RE
= @ = RE (12.3.28)
h fe h fe
Aiv * bvi = gmRE (12.3.29)
Figure 12.16(b) without feedback reduces to a figure on the right side of it with the condition RE = 0.
Ri = hie (12.3.30)
531
Now its input resistance with feedback is

Rif = Ri(1 + T) = hie(1 + gmRE) = hie + hfeRE (12.3.31)
Its output resistance is expressed as
vo
Ro = (12.3.32)
io
vi =0
In order to obtain the output resistance circuit of Fig. 12.16(c) is simplified with vs = 0.
Figure 12.16(c) Equivalent circuit for output resistance
Without feedback means that the voltage drop across RE due to (hfe + 1)ib is = 0, i.e. RE = 0.
1
Hence, the output resistance is = Ro @ (12.3.33)
hoe
1
Hence, its output resistance with feedback is = Rof = Ro(1 + T) = (1 + gmRE)
hoe
1
Rof = (1 + gmRE) (12.3.34)
hoe
Example
Obtain all pertinent quantities for the circuit of current feedback voltage error with following of the
circuit parameters; hie = 1 K, hoe = 5 mS, hfe = 100, RE = 1 K = RC.
Solution
100
Aiv = = 100 mS, bvi ∫ RE = 1 K, T = 100 mS ¥ 1 K = 100,
1K
Ri = 1 K, Rif = 1 K(1 + T) = 1 K(1 + 100) = 101 KW.
1
Ro @ = 0.2 M, Rof = 0.2 M(1 + T) = 0.2 M(1 + 100) = 20.2 MW.
hoe
12.3.3 Current Shunt Feedback

The circuit of common base amplifier works as the current shunt feedback circuit as shown in Fig.
12.17(a). Its equivalent circuit is in Fig. 12.17(b). It is evident from Fig. 12.17(c) that the output current
532
ic appears as the feedback current ie. Hence, it is called current feedback current error. Its other name
is the current amplifier as its output resistance is equivalent to the output resistance of a current amplifier.
Figure 12.17(a) Practical circuit of current shunt feedback
Figure 12.17(b) Equivalent circuit Figure 12.17(c) Circuit for output resistance
For no feedback if = 0, i.e.

is = ie (12.3.35)
Writing nodal equation at emitter point yields
iin = (hfe + 1)ib (12.3.36)
iout = hfeib (12.3.37)
iout Aii h fe
= = (12.3.38)
iin 1 + Aii b ii 1 + h fe
Equation 12.3.38 gives the overall gain, i.e. including feedback where Aii = hfe, and bii = 1 and hence,
T = Aiibii = hfe
Its input resistance without feedback is
Ri = hie (for no feedback if = 0 ) (12.3.39)
Hence, its input resistance with feedback is
Ri hie
Rif = = = hfb (12.3.40)
1+ T 1 + h fe
533
Its output resistance is defined as
Figure 12.17(d) Equivalent circuit for output resistance
vo
Ro = (12.3.41)
io
is = 0
Hence, in order to obtain the output resistance, the circuit of Fig. 12.17(b) is simplified as Fig.
12.17(c). The current source in Fig. 12.17(c) is changed to the voltage source as illustrated in Fig.
12.17d. Now writing the loop equation in this figure.
ib h fe ib h fe ib
vo = vc = + + hie ib = + hie ib (12.3.42)
hoe hoe hoe
vO v v
Ro = = C = C (12.3.43)
iO iO h fe ib
Hence, from Eqn. 12.3.42 Ro is
1 h
Ro = + ie (12.3.44)
hoe h fe
Thus, the output resistance with feedback is
Rof = Ro(1 + T) =
F1 hie I (1 + h fe ) = hie +
1 + h fe
(12.3.45)
GH h
oe
+ JK
1 + h fe hoe
Example
Calculate the current gain, input resistance and output resistance with and without feedback for
hfe = 100, hoe = 5 mS, hie = 1 K.
Solution
Aii = hfe = 100, bii = 1, T = 100,
1K 1K
Ri = hie = 1 K, Rif = = ∫ 0.01 KW.
1+T 1 +100
1 hie 1K
Ro = + = 0.2 M + = 200 K + 0.01 K,
hoe 1 + h fe 100
Rof = 0.2 M ¥ 100 = 20 MW.
#!"
1. Obtain input and output resistances with further simplified as Fig. 12.18(d) with as-
and without feedback for the circuit of Fig. suming 200 W resistor w.r.t. 20 W resistor
12.18(a). Its small signal equivalent circuit in parallel as open circuited. Also 11 K re-
is shown in Fig. 12.18(c). Fig. 12.18(c) is sistor in parallel with 0.5 K has been as-
sumed as if open circuited.
Solution:
Figure 12.18(a)

In order to obtain the open loop gain T, we Fig. 12.18d reduces to Fig. 12.18(e).
put v ¢L as the equivalent voltage when it is
disconnected. With vi = 0, the circuit of vL
T =
v ¢L vi =0

#!#
v ¢L 20 20v¢L
ie = ¥ vL = 0.5 Kie = 0.5 K ¥
200 550 + 20 200 ¥ 570
20v ¢L vL 500 ¥ 20 5
= T= = =
200 ¥ 570 v ¢L 200 ¥ 570 57
= 0.088
Figure 12.18(e) Equivalent circuit for T
Hence, the voltage gain can be expressed With v ¢L = 0, the circuit of Fig. 12.18(e) is
as simplified as Fig. 12.18(f).
vL vi 500
Av = for v L¢ = 0 ie = ¥
vi 1K 570
Figure 12.18(f)
vi 500 0.44
vL = 0.5 Kie = 0.5 K ¥ = = 0.403
1 K 570 1 + 0.088
2. Find out Aif, Rif, and Rof with and without
500 ¥ 500 feedback in the circuit of Fig. 12.19(a).
= vi
1000 ¥ 570
VL 25
Av = = = 0.44
vi 57
Ri = 500| |70 = 61.4 W, and Ro = 0.5 KW.
Rif = 61.4(1 + 0.088) W = 66.8 W
500
Rof = = 459.6 W, = Avf
1 + 0.088
Figure 12.19(a)
#!$
Figure 12.19(c)
Figure 12.19 (d) Equivalent circuit for T
Solution: vL = 0.5 Kie = 0.5 K ¥ 100ib

The circuit of Fig. 12.19(c) is modified as
v¢L
Fig. 12.19(d) for is = 0. = 5 ¥ 104 ¥
11 K
vL
From Fig. 12.19(d), T = vL 0.5 ¥ 100
v ¢L = = 4.55
vs = 0 v ¢L 11
v¢L 10 K
ib = ¥
10 K 11 K
Figure 12.19(e) Equivalent circuit for Av

#!%
iL Ri
From Fig. 12.19(e) T = Ri = 10 K | |1 K = 909 W and Aif =
i ¢L 1- T
v ¢L = 0
With v ¢L = 0, Fig. 12.19(c) reduces to 909

= = 163.8 W
Fig. 12.19(e). 1 + 4.55
10 K - ie1 K Ro 500
ib = is , iL = = 0.5ie Ro = 500 W and Rof = =
11 K 2K 1 - T 1 + 4.55
= 0.5 ¥ 100ib = 50ib = 90.1 W
3. Find out the input resistance, output resis-
iL - 50 ¥ 10 K
Aii = = = 45.45 and Aif tance, voltage gain with and without feed-
is 11 K back for Fig. 12.20(a).
Ai 455. Its ac circuit is drawn as in Fig. 12.20(b).
= =- = 8.2 The equivalent circuit is drawn in
1- T 1 + 4.55
Fig. 12.20(c). From Fig. 12.20(c),
Figure 12.20(a)

#!&
Figure 12.20(d) Equivalent circuit for T with vi = 0
Figure 12.20(e)
Solution: For obtaining the T, vi = 0. Hence,
vL @ 30ic2 = 30h fe2ib 2 Fig. 12.20(c) reduces to Fig. 12.20(d).
vL @ 30 ¥ 50(ic3 / 8)
= 30 ¥ 50(ic1/2) = 30 ¥ 25ic1
= 30 ¥ 50( v ¢L /30 ¥ 8) = 6.25 v ¢L
10
From Fig. 12.20(d) ie1 = - ic3 vL
10 + 10 + 20 T= = 6.25
v ¢L
- ic3
= v
4 Ri = i
is
vL = 30 ¥ 50(ic1/2) = 30 ¥ 50(ic3 /8) ic3 = 0
For obtaining the input resistance, the
v ¢L
From Fig. 12.20(c) ie3 = circuit of Fig. 12.20(c) reduces to
30 Fig. 12.20(e).
#!'
Ri = 1 K| |1 K = 0.5 K, Ro = 30 W -vi 1 1
= - 30 ¥ 50 ¥ ¥ ¥
Rif = 0.5 K(1 T) = 0.5 K(1 + 6.25) 1K 2 2
= 3.625 K vL 1 1 1
Av = = 30 ¥ 50 ¥ ¥ ¥ = 0.375
30 30 vi 1K 2 2
Rof = = = 4.14 W
1 - T 7.25 4. Obtain the loop gain, Rif, Rof, Aif and Avf
vL for Fig. 12.21(a).
Av = Its ac circuit is drawn as demonstrated in
vi Fig. 12.21(b). The small signal equivalent
v ¢L = 0
circuit of Fig. 12.21(b) is drawn as Fig.
With the condition v L¢ = 0, i.e. no
feedback 12.21(c).
vi 1K v -i vL
ie1 = ¥ = i , ib2 = c1 T=
1K 2 K 2K 2 v ¢L
vi = 0
-ic1 With vi = 0 Fig. 12.21(c) reduces to
vL = 30ic2 = - 30 ¥ 50
2 Fig. 12.21(d). Fig. 12.21(d) is further sim-
plified as Fig. 12.21(e).
Figure 12.21(a) Voltage feedback voltage error
Figure 12.21(b)
#"
v¢L 1K - 0.5 K ¥ 50 0.476ic1

ib1 = - ¥ = ¥
50 K 1 K + 0.5 K + 0.476 K 1.5 1.976
v¢ 1K v¢ - 0.5 K ¥ 50 0.476 ¥ h fe1ib1
= - L ¥ =- L = ¥ =
50 K 1.976 K 98.9 1.5 1.976
0.5 K ¥ 1 K ¥ - ic 2 - 0.5Kic2 - 0.5 K ¥ 50 0.476 ¥ 50 - vL¢ 1
vL = = ¥ ¥ ¥
1.5 K 15. 1.5 1.976 50 K 1.976
- 0.478Kic1 - 0.476ic1 vL - 0.5 K ¥ 50 0.476 ¥ 50

= = T= = ¥
1K + 0.5 K + 0.476 K .
1976 v ¢L 1.5 1.976
- 0.5Kic2 0.5 K ¥ 50ic 2

1 1
vL = = ¥ ¥
50 K 1.976
15. 1.5
Figure 12.21(d) Equivalent circuit for T

The input resistance without feedback can Ro 333
be obtained by simplifying Fig. 12.21(c) to Ro = 333 W, Rof = =
1 - T 1 + 153
.
Fig. 12.21(e).
= 131.6 W
Ri = 476 W| |1.5 K = 362.5 W,
Rif = 362.5(1 T) W vL
Av =
vi ¢ = 0
= 362.5(1 + 1.53) W = 917 W vL
Figure 12.21(e) Equivalent circuit for Av with v ¢L = 0

#"
vi 476 0.5 K
From Fig. 12.21e ib1 = ¥ = ¥ ( 2500ib1) (0.178)
1K 1976 1.5
0.242vi vL 0.5 K
= Av = = ¥ (50 ¥ 50) ¥
1K vi 1.5
vL = (0.5 K| |1 K)ic2 = (0.5 K| |1 K)hfeib2 Ê 0.242 ˆ
= (0.5 K| |1 K)50ib2 0.178 Á = 35.73
Ë 1 K ˜¯
Ê 0.323 K ˆ Av 3573
.
= (0.5 K| |1 K)50(ic1) Á Avf = = = 11.8
Ë 0.323 K + 1.5 K ˜¯ 1- T 3.03
0.5 K Ê 0.323ˆ 5. Find Avf, Aif, T, Rif, and Rof for the circuit
= ¥ (- 50ib1 ¥ 50) Á shown in Fig. 12.22 (a) assuming all tran-
1.5 Ë 1.823 ˜¯
sistors identical and hre = hoe = 0.
Figure 12.22(a)
The circuit of Fig. 12.22(a) is modified as of transistor T3, the loop equation is written
Fig. 12.22(b). Its small signal equivalent as
circuit is drawn in Fig. 12.22(c). In order Solution:
to find out the input impedance at the base vb3 = hie3ib3 + hie4ib4 + R L (1 + h fe 4 )ib4 (a)

#"
ib4 = ie3 = (1 + hfe3)ib3 (b)

RS
vb3 = ib hie3 + hie4 (1 + h fe3 ) + UV (c)
Substituting Eqn. (b) in Eqn. (a) results 3
T R (1 + h )(1 + h
L fe 3 fe 4 ) W
as
Figure 12.22(d) Equivalent circuit for Av with v L¢ = 0

vbe4 vbe3 hie3ib3 - h fe 2 RC ib 2 (1 + h fe ) 2 RL
hie4 = = =
ib4 1 + h fe 3 ib3 1 + h fe 3 ib3 vL = (e)
d i d i 2hie3 + (1 + h fe3 )2 RL + RC
hie3
= (d)
d1 + h i vL
fe 3 T=
v ¢L
Assumptions are hei1 = hie2, hfe4 = hfe3 vi = 0
= hfe2 Now voltage without feedback can be ob-
Substituting Eqn. (d) in Eqn. (c) yields tained using circuit Fig. 12.22(e). This cir-
vb3 = ib3{hie3 + hie3 + RL(1 + hfe3)2} cuit results from Fig. 12.22(d) after sub-
stituting vi = 0 in it.
Hence, the input resistance seen at the base
of T3 is v ′L
ib2 =
Ri = 2hie3 + (1 + hfe3) RL 2 rs + 2hie + RF
Now the equivalent circuit of Fig. 12.22(c) vL
T=
reduces to Fig. 12.22(d). From Fig. v ¢L
12.22(d)
- h fe 2 (1 + h fe 3 ) 2 RL RC
− h fe2 RCib2 =
ib3 = {2hie3 + (1 + h fe 3 ) 2 RL + RC } ( rs + 2hie1 + RF )
2
d i
2hie3 + 1 + h fe 3 R L + RC (f)
#"!
Figure 12.22(e) Equivalent circuit for T with vi = 0

2 − h fe 2 RC
As hie3 and RC << (1 + hfe3) RL, Eqns. (e)
=
and (f) reduce to rs + 2hie1 + RF
vL = hfe2ib2RC The input impedance of this circuit from
Fig. 12.22(e) results as
vL − h fe2 RC Ri = rs + 2hie1 + RF
T= =
v ¢L rs + 2hie1 + RF The output impedance is expressed as
Now, voltage without feedback can be vo
obtained with the help of circuit of Ro =
io v
Fig. 12.22 (d). From Fig. 12.22 (d). i = 0 = vL
¢
− vs In order to obtain the output impedance all
ib2 = resistances and sources are reflected at the
rs + 2hie1 + RF
emitter of T4 and hence it looks like the one
vL 1 shown in Fig. 12.22(f).
Av=
vs
d
= − h fe 2 RC i
rs + 2hie1 + RF
Figure 12.22(f)
It is well known that if the impedance is hie3 (seen at emitter of T4)

transferred from the emitter lead to the hie 3 hie 4
base of any BJT, it is multiplied by the fac- = =
tor (1 + hfe) and sources are divided by the d1 + h id1 + h i
fe 3 fe4
1 + h fe4
same factor. On the same line if these are = hib4
transferred from the base side to the emit-
Similarly hie4 (seen at its emitter)
ter side, the impedances are divided and
sources multiplied by the factor (1 + hfe). hie 4
= = hib4
Thus, reflecting every thing at the emitter 1 + h fe4
of T4 the circuit of Fig. 12.22(f) results.
#""
Ro
F
= R | | G 2h
L ie 4 +
RC
I
J b
Rif = rs + 2hie1 + RF g FGH1 + r + 2hh R + R IJK
fe C
GH d1 + h fe i JK
2 s ie1 F
= rs + 2hie1 + RF + hfeRC
Now the voltage gain with feedback
RO
Av T T Similarly Rof =
= Avs = = = =1 1- T
1− T 1 T T
6. Determine the nature of feedback present
Thus, the input resistance with feedback in the two-stage feedback amplifier of Fig.
12.23(a). Calculate the Av, Avf, Ri, Rif, Ro,
Rif = Ri(1 T) and R of assuming hfe = 50 and hje = 1.1K.
Figure 12.23(a)
22 ¥ 220 K Ri = hie + (1 + hfe)RE = 1.1 K + 51 ¥ 0.1 K

RB = = 20 K,
242 4.7 ¥ 10.1
= 6.2 K, RL2 = = 3.2 K
0.1 ¥ 10.1 K 14.8
RE| |RF = = 0.099 K = 0.1 K,
10.2
22 ¥ 20 ¥ 1.1 K
RL1 =
0.1 1 22 ¥ 20 + 20 ¥ 1.1 + 22 ¥ 1.1
bvv = @ ,
10.1 100
#"#
484 K is drawn in Fig. 12.24(a). The overall volt-

= = 0.995 K @ 1 K age feedback is given through RG from the
486.2
last stage with |b | = R1/RG. Calculate the
overall gain and input resistance without
ic1 ic1 feedback and with feedback. Given
gm1 = =
vb {hie + (1 + h fe ) RE }ib gm = 6 ¥ l03 S, rd = 10 K , RD = 50 K, RG
= 1 MW, R1 = 40 W .
h fe m = gmrd = 6 ¥103 ¥ 10 K = 60,
50
= h + (1 + h ) R = = 8.065 mS 10 ¥ 50 ¥ 1000 K
ie fe E 6.2 K RL1 =
10 ¥ 50 + 50 ¥ 1000 ¥ 10
Av1 = gm1RL1 = 8.065 ¥ 1 = 8 and
500000 K
= = 8.3 K @ RL2
Av2 = gm2RL2 =
-50
¥ 3.2 K = 145.8 60000.5
11
. 50 K||1 M @ 50 K
Overall voltage gain = Av = Av1 ¥ Av2 - mRL1
Av1 =
= 8 ¥ 145.8 = 1166.34, rd + (1 + m ) R1 + RL1
T = Avv bvv = 11.6634, - 60 ¥ 50 K

=
10 + 51 ¥ 40 + 50 K
Rif = Ri(1 + T) = 6.2 ¥ 11.66 = 72.3 K,
Ro 3.2 K - 60 ¥ 50 K
Rof = = = 0.253 K = = 48.36,
1+ T 12.66 10 + 2.040 K + 50 K
Av 1166.34 40
Avf = = = 92.13 A3v1 = (48.36)3 = 1.13 ¥ 105, bvv = ,
1+ T 12.66 106
40
7. A three-stage common source feedback T = Avvbvv = 1.13 ¥ 105 = 4.523,
amplifier consisting of three identical FETs 106
1 + T = 5.523
+ VDD
RD RD RD
RG1 RG1 RG1
C•
T1 C• T1 C• T1 C•
rs
RG2 RG2 RG2
vs RS RS C• RS C•
Figure 12.24(a)
#"$
Figure 12.24(b)
1mA, IC3 = 4mA. Obtain the open loop

Av . ¥ 105
- 113
Avf = = = 0.205 ¥ 105 gain Aiv, feedback factor bvi, the close loop
1+ T 5.523
iE3 v
= 2.05 ¥ 104 gain Aivf = , voltage gain o , the input
vi vi
Ro 8.3
Ro = 8.3 K, Rof = = = 1.5 K resistance Rin = Rif, and the output resis-
1+ T 5.523 tance Rof. What is the nature of feedback?
8. The collector dc currents for BJTs shown
in Fig. 12.25(a) are IC1 = 0.5 mA, IC2 =
Figure 12.25(a)
Solution: bVT 100 ¥ 26

hie3 = =
bVT 100 ¥ 26 I C3 4
hie1 = = = 4.33 KW
I C1 0.6
= 0.65 K, 9 K| |2.6 K = 2 K,
bVT 100 ¥ 26 RE1| |(RF + RE2) = 100| |(740) = 88 W
hie2 = = = 2.6 KW
I C2 1
#"%
Rie3 = hie3 + (1 + hfe)RE

(h fe + 1)9ib1 909ib1
= 0.65 K + 101 ¥ 88 = 0.65 K + 8.89 K ib2 = - = = 78.36ib1,
11.6 11.6
9.54 ¥ 5 K
= 9.54 K, Ri3| |5 K = = 3.3 K vc1 - 202 Kib1
14.54 = = 15.3
vi 13.22 Kib1
vc1 = vb2 = (1 + hfe)ib1 (RC1| |hie2)
vc2 = vb3 = hfeib2(5 K| |Ri3)
= 101 ¥ 2Kib1 = 202Kib1
= 100 ¥ 3.3 K ¥ 78.36ib1,
vi = {hie1 + (1 + hfe)R¢E}ib1
vc2 100 ¥ 3.3 ¥ 78.36
= (4.33 + 8.89)Kib1 = 13.22Kib1 Hence, = = 129.3
vc1 - 101 ¥ 2
Figure 12.25(b)
iE3 ¥ 100 ¥ 100 vc 3

vf = , = AivfRc3 = 84 ¥ 0.6 = 50.4,
840 vi
vf 10000 Ri = hie1 + (1 + h fe)RE
bvi = = = 11.9 W
i E3 840 = (4.33 + 8.89)K = 13.22 K
vc1 vc 2 ie 3 Rif = (1 + T)Ri = 248.163 ¥ 13.22 K
Aiv = overall gain = ¥ ¥
vi vc1 vb 3 = 3280.7 K = 3.3 MW
The output resistance is obtained by break-
vc1 vc 2 ie3 i
= ¥ ¥ = e3 ing the point at the emitter of T3 and re-
vi vc1 vc2 vi flecting the resistance at the emitter termi-
= (15.3)(129.3)(10.5m) = 20.77 S nal of T3 as
T = A iv ¥ bvi = 20.77 = 247.163, RC 2 + hie 3
RO = + RE3| |(RF + RE1)
1 + T = 248.163 1 + h fe
Aiv 20.77 = 56.5 + 88 = 144.5 W

A ivf = = = 84 mS
1 + Aiv b vi 248.163 ROf = (1 + T)Ro
ic 3 = 248.163 ¥ 144.5 = 35.86 KW
= , ic3 = Aivf vi, vc3 = RC3ic3
vi The nature of the feedback is current se-
= AivfRc3vi ries type.
#"&
9. Determine the nature of feedback applied ues of hfe = 50 and hie = 0.2 K, rs
in the circuit of Fig. 12.26(a) for given val- = 0.05 K = R3, R1 = 0.7 K = R2, RF = 52 K.
Figure 12.26(a)
50 ¥ 200 52.04 i
RF + = 52 K + 0.04 K = hfeib3 = hfeib3, 3 = 60
250 52.09 ib 3
= 52.04 K, rs| |(RF + rs) = 50 W
R2 0.7
52.04 ib3 = hfeib2 = hfeib2
i3 = h feib3 R2 + hie 2 0.9
52.04 + 0.050
ib 3
= 60 ¥ 0.78ib2 = 46ib2, = 46
ib 2
Figure 12.26(b)
R1 0.7 vc3
ib2 = hfeib1 = hfeib1 = 300ib3, = 300
R1 + hie 2 0.9 ib3
ib 2 vc 3 v i i i
= 60 ¥ 0.78ib1 = 46ib1, = 46 Avi = = c 3 b3 b 2 ◊ b1
ib1 is ib3 ib 2 ib1 is
is ¥ 50 is ib1 1 1 634800
ib1 = = , = = 300 ¥ 46 ¥ 46 ¥ =
250 5 is 5 5 5
i3 i i i i = 1.27 ¥ 105 W
Hence, = 3 ◊ b3 ◊ b 2 ◊ b1
is ib3 ib2 ib1 iS 1 1
biv = - =
1 RF 52 K
= 60 ¥ 46 ¥ 46 ¥
5
1.27 ¥ 105
= 25392 = 2.5392 ¥ 10 4 Avi biv = T = = 2.44
52 K
vo = vc3 = hfeib3R3 = 60 ¥ 50ib3
T + 1 = 3.44
#"'
Avi 1.27 ¥ 105 Ro 50

Avif = = Rof = = = 14.53 W
1 + Avi b iv 3.44 1+ T 3.44
= 3.7 ¥ 104 10. Determine the nature of feedback in Fig.
12.27(a). Calculate the values of effective
Ri = rs| |hie = 0.04K, Ro = Rc3 = 0.05 K,
v
Ri 40 input and output resistances and o for
Rif = = = 11.63 W, is
1+ T 3.44 given values of hie = 100 and hie = 1K.
Figure 12.27(a)
Figure 12.27(b)
15.5 ¥ 3 i ¥ 2.5 = 4700 K ¥ 75 ¥ 0.714 = 251685

= 2.5 K, ib1 = s = 0.714is,
18.5 3.5 = 2.51685 ¥ 105 W
ib1 h feib1 ¥ 3 0.1
= 0.714, ib2 = - = 75ib1, biv = = 6 ¥ 103 S,
is 4 16.5
ib 2 T = Avibiv = 2.51685 ¥ 105 ¥ 6 ¥ 103
= 75
ib1 = 2.51685 ¥ 102 ¥ 6 = 15.12
ic2 = hfeib2 = 100ib2, 1¥ 3
Ri = = 0.75 K, Ro = 4.7 K,
vc2 = 4.7Khfeib2 = 470 Kib2, 4
vc 2 i 0.75 K
= 470 K, c 2 = 100, Rif = = 46.5 W,
ib 2 ib 2 16.12
vc2 v i i 4.7 K
= c 2 b2 b1 Rof = = 292 W
is ib2 ib1 is 16.12
##
11. Obtain the values of Av, b, Avf, Ri, Rif, Ro, shown in Fig. 12.28(a) assuming h fe =
Rof in the feedback differential amplifier 100.
Figure 12.28(a)
Figure 12.28(b)
Figure 12.28(c)
##
IC1 = IC2 = 0.5 mA, = 21 K ¥ 9.52 10 K = 189.92 K

VT (1 + h fe ) 25(101) RO 181 W
hie1 = = Rof = = = 19 W
IE 0.5 1+ T 9.52
25(101) 12. The non-inverting op-amp in Fig.12.29(a)
= 1.050 K = hie2, hie3 = = 0.505 K implements a voltage feedback current er-
5
ror type of circuit, (a) Determine the value
Ri = rs + hie1 + hie2 + 1 K| |9 K
of feedback factor biv assuming ideal Op.
= 10 + 5.05 + 5.05 + 0.9 = 21 K R
Amp. (b) How much is the value of 2 , if
(20 + 0.505) K R1
RO = | |10 K| |2 K
101 the open loop and close loop gains are 104
= (198 + 5)| |1.67 K = (0.203K)| |1.67 K and 10 respectively? (c) How much is the
value of feedback in decibel? (d) Obtain
1 the values of vi, vf, and vo for vs = 1V ? (e)
= 181 W, bvv = = 0.1
10 How much change in the close loop gain
Ri3 = hie3 + (1 + hfe)RE occurs, if the open loop gain decreases by
= 0.505 + 101 ¥ 2 K| |10 K 20%?
= 0.505 + 101 ¥ 1.67 K
= 0.505 + 168.67 K = 169.2 K
vo = hfeib2 20 K| |Ri3
= hfeib2 20 K| |169.2 K
= 17.886 ¥ 100Kib2
vi
ib2 = ib1 =
(10 + 5.05 + 5.05 + 1| | 9) K Figure 12.29(a)
vi v
= = - i
(10 + 5.05 + 5.05 + 0.9) K 21 K
vo - 17.886 ¥ 100Kib 2
= Avv =
vi - 21Kib 2
17.886 ¥ 100
= = 85.2
21
T = Avv bvv = 85.2 ¥ 0.1 = 8.52,
Figure 12.29(b)
T + 1 = 9.52
Avv 85.2 R1 104
Avf = = = 8.95, bvv = , 10 = ,
1 + Avv b vv 9.52 R1 + R2 1 + 104 b vv
Rif = Ri(1 + T) rs 999

1 + 104bvv = 1000, bvv = = 0.0999
104
##
Hence, 0.0999(R1 + R2) = R1, 13. Obtain low frequency gain and upper 3 dB
0.0999R2 = 0.9001R1, frequency, if the open loop higher 3 dB fre-
R2 0.9001 quency is l00Hz in Problem 12. Given R1 =
= = 9.01 10 K and R2 = 9 K.
R1 0.0999
Amount of feedback in decibel = 20 log 1
b= = 0.1,
(1 + Avibiv) = 20 log(1 + 103) = 60 dB 10
vo = Avif vs = 10 ¥ 1 = 10 V, 104 104
Af = =
vf = biv ¥ vo = 0.0999 ¥ 10 = 0.999 V 1 + 10 b 1 + 104 ¥ 0.1
4
vi = vs vf = 1 0.999 = 0.001 V
104
20% decrease in 104 yields = 0.8 ¥ 10 4 = = 9.99
1001
open loop gain. Hence, corresponding
change in the close loop gain fHf = (1 + Ab)fH
0.8 ¥ 104 = 1001 ¥ 100 Hz = 100.1 kHz
=
1 + 0.8 ¥ 104 ¥ 0.0999 14. Obtain voltage gain, input resistance, and
output resistance of the non-inverting am-
0.8 ¥ 104 plifier shown in Fig. 12.29(b) using feed-
= = 9.99745
1 + 799.2 back method. Given open loop gain = 104,
10 9.9975 = 0.0025, change in close loop Rid = 100 K , ro = 1 K .
gain = 0.025%
Figure 12.29(c)
2 K ¥ 1000 K -104 ¥ 1 K ¥ 1.996Kis

RL| |RF = = 1.996 K, =
1002 K 1 K + 1.996 K
100 K ¥ 1000 K
rs| |Rid| |RF = | |rs vo - 104 ¥ 1.996 K
1100 K Avi = = = 6662 KW,
is 2.996
= 90.9 K ¥ 1 K = 0.99 K = 1 K
- is 1
- Av ( RL || RF ) biv = =- = 106 S
v = (rs| |Rid| |RF)is, vo = RF i s RF
ro + RL | |RL
T = Avibiv = 6.662, T + 1 = 7.662
- Av ( RL || RF )(rs | | Rid | | RF )is vo v 6662
= = o = = 6662,
ro + RL | |RF vs rsis 1
##!
6662 1.2 K 1200

Avif = = 869.5 RE = = = 50 W
7.662 24 24
0.99 K
Ri = 1 K, Rif = = 130 W,
7.662
2 K ¥ 1000 K
Ro = ro| |RL| |RF = | |ro
1002 K
1.996 K ¥ 1 K
= = 666 W,
2.996
666 W
Rof = = 86.92 W Figure 12.31
7.662
15. Show that if Ab is large then the close loop 16. The series-series type feedback circuit in
voltage gain is given approximately as Avf Fig.12.31 realizes a voltage controlled cur-
v R + RE rent source. Biasing circuit has not been
= o = F . What would be the
vs RE shown. Show that if the loop gain Ab is
value of RE, if RF is set to be 1.2 K to pro- large, then
duce close loop gain of 25 in Fig.12.30. IO 1
=
vs RE
Solution:
IO 1
vE = REIo = Vs, =
vs RE
17. Each stage of a three stage amplifier with-
out feedback has identical pole frequencies
and its open loop transfer function is ex-
pressed as
Ao3
A3(s) = 3
FG1 + s IJ
H w K H
Determine its maximum value of feedback

Figure 12.30 factor bmax for which the amplifier re-
vo Av A 1 mains stable. Also determine the corre-
Avf = = = v = sponding frequency.
vs 1 + Av b Av b b
Ao3
RE + RF R + 1.2 K 1 + Ab = 1 + 3
b
=
RE
= 25 = E
RE
, FG
1+
s IJ
25RE = RE + 1.2 K,
HwH K
##"
Ao3 19. The voltage gain without negative feed-

=1+ 3
b. back is 40 dB. What is the new voltage
FG1 + j w IJ gain if 3% negative feedback is intro-
H w K H duced?
The phase change may change Ab to nega-
Solution:
tive. This can happen only when the total
w FG IJ 3
40 dB = 20log102 = 20log
FG v IJ
o
change in the phase angle of 1 + j Hv K
wH H K i
becomes 180°. The required phasechange vo Av

w Av = = 100 and Avf =
in one stage i.e. 1 + j should be 60°. vi 1- T
wH
Avv 100
w = = = 25
tan C = tan60° = 3 . Here, wC is the 1 + Avv b vv 1 + 100 × 0.03
wH
frequency at which the phase angle 20. In Problem 19 if lower and higher cut off
changes the sign. The value of Ab at frequencies are 100 Hz and 100 kHz, what
Ao3 are two cut-off frequencies after feed-
this frequency = b back? From previous example, b = 0.03,
(1 + j 3 ) 3
bAo3 bAo3 bAo3 Avf = 25.
= –180° = - = - .
( 1 + 3) 3 (2) 3 8 Solution:
b max Ao3 8 fL 100
1 + Ab = 0, = 1, bmax = 3 fLF = = = 25 Hz,
8 Ao 1 - T 1 + 100 ¥ 0.03
Where, bmax is the critical value when the fHF = fH (1 T) = 100 kHz ¥ 4 = 400 kHz.
amplifier starts oscillating and the fre- 21. A negative feedback amplifier with 60 dB
quency of oscillation is wc = 3 wH. voltage gain has lower and upper cut-off
A two-stage amplifier can not produce frequencies 100 Hz and 200 kHz respec-
maximum change in phase shift of 180° tively. For the amplifier bandwidth of
and hence is stable. A three stage amplifier 2 MHz, specify the feedback needed and
can produce phase angle more than 180° new cut off frequencies.
and can become unstable for large value of
Solution:
b.
18. A three-stage feedback amplifier has dc vo
60 dB = 20log103 = 20log = 20logAv,
gain of 104. All the open loop poles are at f vi
= 2 MHz. Determine the maximum value Av = 103
of feedback factor b for which the ampli-
fier becomes unstable and the correspond- Band-width = f HF f LF @ (1 + A v b v )
ing frequency of unstability. 200 kHz = (1 + 1000bv)200 kHz
From above problem A3o = 104, = 2 MHz
8 8
bmax = = , fc = 3 fH = 2 3 MHz
Ao3 104
###
2000 kH/200 kHz - 1 10 1000

bv = @ = 0.01 Avf = = 10 = 20log101,
1000 1000 1 + 1000 × β
22. Design a feedback amplifier having overall 99
gain of 40 dB and sensitivity figure of 4% b= = 0.099
w.r.t. its internal amplifier gain Av. 1000
Solution: 100
fLF = = 1 Hz, fHF = 100 KH(100)
100
40 dB = 20log102 = 20log
FG v IJ ,
o
= 10 MHz
Hv K
i
Avf = 100 Bandwidth = 10 MHz 1 Hz @ 10 MHz

Avv 25. An amplifier without feedback has a gain
Avf = = 100 of 100 and with negative feedback its gain
1 + Avv b vv
falls to 10. Design the feedback network.
Avv 100
0.04 = = Solution:
1 + Avv b vv Avv
A 100
100 A = 100, Af = 10 = =
Avv = = 2500 1 + Ab 1 + 100b
0.04 9
1 + Avvbvv = 25 b= = 0.09
100
24 26. An amplifier has a voltage gain of 100 and
bvv = = 0.096
2500 its voltage gain is increased to 200 by in-
23. The open circuit voltage gain 60 dB of an creasing the bias conditions. Calculate the
amplifier changes by 5%. How much negative feedback factor that must be ap-
change in voltage gain will result with 2% plied to bring the voltage gain to the origi-
negative feedback? nal value 100.
Ai Solution:
(% change in Aif = % change in
1 + Ai β 200
Avf = = 100,
1 + 200 × β
5 5
= = = 0.238%)
1 + 100 × 0.02 21 1
b= = 0.005
24. An amplifier without feedback has a volt- 200
age gain of 60 dB. The lower and upper 27. A negative feedback voltage amplifier re-
cut-off frequencies of this amplifier is 100 quires 1 V input to produce an output volt-
Hz and 100 kHz respectively. Inclusion of age while it requires only 0.1 V input volt-
negative feedback reduces the gain to 20 age to produce the same output voltage
dB. Determine the bandwidth and the new without feedback. Calculate the feedback
gain. factor.
Solution: Solution:
Given Av = 1000, fL = 100 Hz, v2 v Av v
fH = 100 kHz, Avf = 10 = 2 = , and Av = 2 ,
v1 10 1 - T 01.
##$
01
. Av Av 4
v2 = 0.1Av, = , b= = 0.04
1.0 1-T 100
1 T = 1 + Avbv = 10, 30. A feedback amplifier with 5% negative
feedback is designed to have overall gain
9
b= of 20 dB. Calculate the open loop gain of
Av the amplifier. If the above amplifier is ar-
BW without feedback = (15 0.025) kHz ranged for current feedback voltage error
= 15 kHz and its input and output resistances are
100 KW and 100 W respectively. Calculate
BW with feedback = 15 kHz ¥ 10 the new input and output resistances after
feedback is introduced.
= 150 kHz.
Solution:
28. The overall gain of a negative feedback
amplifier is 60 dB and the attenuation pro- Av Av
Avf = 103 = =
vided by network is 80 dB. Calculate the 1 + Av b 1 + 0.05 Av
voltage gain of the amplifier without feed-
back. 50Av Av = 103
Solution: 103
A Av = = 28.83
1 v 49
Avf = 1000, bv = , Avf =
10000 1+ A β
Rif = Ri(1 + 28.83 ¥ 0.05)
v
= 1000,
= 100 KW ¥ 1.442 = 144.2 KW
A A 9A
l= v v = v Ro 100
1000 10000 10000 Rof = = = 69.35 W
1 + Ab 1.442
10000
Av = @ 1000 31. A music program of frequency range from
9 25 Hz to 15 kHz is to be amplified 30 times
29. An amplifier has bandwidth of 2000 kHz at by an amplifier whose input and output
a voltage gain of 100. (a) What will be the voltage are out of phase. The amplifier
new bandwidth and gain if 5% negative while delivering output produces 5% har-
feedback is introduced? (b) What should monic distortion also.
be the amount of feedback if the band-
(a) What type of feedback will reduce the
width is to be restricted to 10MHz?
harmonic distortion?
Solution: (b) What is % distortion if 2% of the out-
BW = 2 MHz, Av = 100, b = 0.05, put voltage is fedback?
(c) What is the output voltage?
BWf = 2 MHz(1 + 5) = 12 MHz
(d) What is the bandwidth with and with-
10 MHz = 2 MHz(1 + Ab) out feedback?
(e) What is the gain of the amplifier with
= 2 MHz(1 + 100b) and without feedback?
##%
Solution: 5
(a) Negative feedback = = 2%
2.5
AV (c) vo = 30vi
bv = 0.02, Avf = 30 = , and
1 + AV β V (d) BW without feedback = (15 0.025) kHz
@ 15 kHz
Av = 30 + 0.6Av
BW with feedback @ 15 kHz (1 + 1.5)
0.4Av = 30, = 37.5 kHz.
30 (e) Gain of amplifier without feedback
Av = = 75, = 76
0.4
Gain of amplifier with feedback
D 5
D = D2f = = 76
1 + Av × β 1 + 75 × 0.02 = = 30.4
2.5
Questions for Practice 11. Enumerate the advantages and disadvan-

tages of negative feedback.
1. Distinguish between positive and negative 12. What happens to the stability of the gain of
feedback and voltage and current feed- an amplifier with negative feedback?
back. 13. What is the effect of negative feedback on
2. Explain the effect of negative feedback on bandwidth of an amplifier?
(a) gain and stability, (b) distortion of an
amplifier.
3. What is negative feedback? Does it neces- Multiple Choice Questions
sarily reduce the voltage gain?
4. What types of feedback are used in ampli- 1. Negative feedback in an amplifier
fiers and oscillators? (a) increases the voltage gain
5. What type of feedback is the emitter fol- (b) decreases the voltage gain
lower an example of? How much negative (c) can change it to an oscillator
feedback is used? 2. Negative feedback in amplifier
6. How current feedback voltage error is pro- (a) reduces the noise
duced in a BJT amplifier? (b) decreases bandwidth
7. What is loop gain? (c) increases lower cut-off frequency
8. What is the effect of negative feedback on (d) increases the noise
input resistance of an amplifier? 3. Current gain with negative feedback in an
9. Which type of negative feedback always amplifier
decreases the output resistance of an am- (a) increases
plifier? (b) decreases
10. Why voltage gain with negative feedback (c) remains the same
is less than that without feedback? 4. Gain bandwidth product of an amplifier
after inclusion of negative feed back
##&
(a) decreases (a) decreased

(b) increases (b) increased
(c) remains the same (c) unchanged
5. Negative feedback increases the input re- 13. A public address system (amplifier) uses
sistance/impedance of an amplifier in case (a) unbypassed emitter resistor
of (b) uses bypassed emitter resistor
(a) current feedback voltage error (c) does not use emitter resistance
(b) current feedback current error 14. The bypassed emitter resistance of a CE
(c) voltage feedback current error amplifier is an example of
6. Output resistance/impedance of an ampli- (a) voltage feedback voltage error
fier is reduced in case of (b) voltage feedback current error
(a) voltage feedback voltage error (c) current feedback voltage error
(b) current feedback, current error 15. Unbypassed emitter resistor in cc amplifier
(c) voltage feedback current error is an example of
7. Emitter follower is widely used because (a) voltage feedback voltage error
(a) its gain is unity (b) voltage feedback current error
(b) its gain is high (c) current feedback voltage error
(c) its output impedance is low and input 16. Negative feedback is utilized in
impedance is high (a) amplifier
8. Negative feedback (b) oscillator
(a) decreases higher and lower cut-off (c) rectifier
frequencies 17. Transmission gain of negative feedback
(b) decreases lower cut-off and increases amplifier is
higher cut-off frequencies (a) Ab (b) 1/Ab
(c) increases lower and higher cut-off (c) A/(1 + Ab) (d) A(1 + A)
frequencies 18. The voltage gain of an amplifier is 100. A
9. Internal disturbances in amplifier with negative feedback of 4% will reduce the
negative feedback is gain to
(a) decreased (a) 20 (b) 25
(b) increased (c) 4 (d) 99.9
(c) the same 19. Common drain amplifier is an example of
10. Input resistance of an emitter follower (a) voltage series feedback
w.r.t. its output resistance is (b) voltage shunt feedback
(a) less (c) current series feedback
(b) more (d) current shunt feedback
(c) equal 20. The common source amplifier with Rs
11. Collector to base bias is an example of connected between the source and ground
(a) voltage feedback current error is
(b) voltage feedback voltage error (a) voltage series feedback
(c) current feedback current error (b) voltage shunt feedback
12. Bias stabilization of an amplifier with (c) current series feedback
unbypassed emitter resistor is (d) current shunt feedback
##'

1. (b) 2. (a) 3. (b) 4. (c) 5. (a) 6. (a)
7. (c) 8. (b) 9. (a) 10. (b) 11. (a) 12. (b)
13. (b) 14. (c) 15. (a) 16. (a) 17. (a) 18. (a)
19. (a) 20. (c)
13
Oscillators
13.1 Introduction
The requirement of signal frequency for experimental purposes sometimes ranges from Extremely Low
Frequency (ELF) in the range of 1 Hz to 300 Hz, to Extra High Frequency (EHF) ranging upto 300 GHz.
We know that ELF cannot be generated by LC oscillators as the requirement of component values
makes it so bulky that practically it becomes impossible to manufacture it without undesirable effects of
resonance. Hence, for generation of ELF and VLF frequencies RC oscillators are used. The classifications
of oscillators based on frequency ranges are
∑ Audio frequency oscillators upto 20 kHz
∑ Radio frequency oscillators 20 kHz to 30 MHz
∑ Very high frequency oscillators 30 MHz to 300 MHz
∑ Ultra high frequency oscillators 300 MHz to 3 GHz
∑ Microwave oscillators 3G Hz to thousands of GHz
The other classification of oscillators is based on connections such as
∑ Phase-shift oscillators
∑ Wein bridge oscillator
∑ LC oscillators (Hartley/ Colpitts, Tuned Collector, etc.)
∑ Crystal oscillators and
∑ Negative resistance oscillators
The fundamental building blocks required for an oscillator are
∑ Frequency determining network
∑ Amplifier to boost the oscillation and
∑ Feedback network
Oscillators
#$
LC or RC circuit is a easily and cheaply available frequency-determining network. As its frequency

depends on the value of these components, it is called frequency-determining network. The transistor
amplifier is required to boost the weak oscillations produced by LC or RC network. The feedback
network is required to feed a portion of the output voltage of the amplifier to the frequency determining
circuit in proper phase. The output voltage from block diagram shown in Fig. 13.1 is
b g
vo = vi ± bvo –q 2 A–q 1 (13.1.1)
The negative () sign in Eqn. 13.1.1 is taken for amplifier where as positive (+) sign is assumed for
the oscillator.
l q
vo 1 − Aβ ( ∠θ 2 + ∠θ 1 ) = Avi ∠θ 1 (13.1.2)
Ï A–q1 ¸
or, vo = Ì1 ˝ (vi ) (13.1.3)
Ó - Ab ( – q1 + – q )
2 ˛
Figure 13.1 Block diagram approach to oscillator
If the denominator of Eqn. 13.1.3 is made equal to zero, i.e.

Ab = 1 and
q1 + q2 = 0 (13.1.4)
Equation 13.1.3 indicates that the output will become infinite and the feedback is said to be positive.
This is the concept of oscillation. An oscillator does not require any input voltage. This condition of
oscillation is known as Barkhausen criteria.
The feedback signal and the input signal should be in phase as per the Barkhausen criteria of oscillation.
We know that one stage of CE amplifier provides 180° phase-shift and hence, additional 180° phase
should be provided by any phase shifting network to result in the addition of the feedback voltage from
the phase shift network to the original input of the CE amplifier in phase. Hence, the CE amplifier in
combination with the phase shifting network would start oscillating.
The 180° phase-shift can be provided in two simple manners, namely,
∑ Phase-leading network
∑ Phase-lagging network.
The RC type phase-lead and lag networks are drawn in Figs. 13.2(a) and (b). From Fig. 13.2(a), the
relationship between output and input voltages is written as
#$
R(vi ) vi vi
vo = = =
R + 1 / jw C 1 2 -1
1- j 1 + (1 / w CR ) {– - tan (1 / w CR)}
w CR
Figure 13.2(a) Phase-lead network Figure 13.2(b) Phase-lag network
vo v – tan -1 (1/w CR ) – tan- 1 ( f L / f ))

= i = (13.1.5)
vi 2 2
1 + 1 / w CR) 1 + ( fL / f )
1 f
where tan q1 = = L (13.1.6)
w RC f
Similarly, from Fig. 13.2(b) the relationship between output and input voltages is
vo =
FG 1/ jw C IJ v = FG v IJ =
i
i vi
H R + 1/ jw C K H 1 + jw CR K 1 + (w CR)2 {– tan -1 (w CR)}
vi – - tan -1 (w CR )
=
1 + (w CR ) 2
-1
vo – - tan -1 (w CR ) – - tan ( f / f H )
= = (13.1.7)
vi f 1 + ( f / fH )
2
1+ j
fH
where, tan q2 = w CR = f/fH (13.1.8)
It is clear from Eqns. 13.1.6 and 13.1.8 that the maximum values of tan q1 and tan q2 will occur at
q = p/2. Hence, one section of either types of RC network will provide only 90° phase shift. Thus, we
see that one section of either RC phase-lag or phase-lead network can provide maximum of 90° phase
shift. Considering the loss component, maximum phase shift of 90° cannot be achieved by one section
of simple RC network shown in Figs. 13.2(a) and (b). Hence, in order to get additional 180° phase shift
at least three sections of RC network are required.
Oscillators
#$!
13.2 RC Oscillators
The RC oscillators contain only R and C components in the feedback loop. The most common type of
RC oscillators are
∑ Phase-shift
∑ Weinbridge
13.2.1 Phase-shift Oscillators

The building block of phase-shift oscillator consists of
∑ an inverting amplifier
∑ three-stage RC phase-shift network
The block diagram representation of a phase-lead RC oscillator is shown in Fig. 13.3.
Figure 13.3 Block diagram of RC phase-shift oscillator

As, Ri = •, if = 0 and so i5 = i6 (13.2.1)
vf
i5 = i6 = (13.2.2)
Z2
Z2i6 + z1i5 = Z2i4
vf
(Z2 + Z1)i5 = (Z2 + Z1)i6 = ( Z1 + Z2 ) = Z2i4 (13.2.3)
Z2
FG
i4 = 1 +
IJ
Z1 v f
=
vf
(1 + a ) (13.2.4)
H K
Z2 Z 2 Z2
Z1
where a= (13.2.5)
Z2
vf vf vf
i3 = i4 + i5 = (1 + a ) + = (2 + a ) (13.2.6)
Z2 Z2 Z2
#$"
Z2i2 = Z2i4 + Z1i3 = (1 + a)vf + (2 + a) avf = (1 + 3a + a2) vf

vf
i2 = (1 + 3a + a 2 ) (13.2.7)
Z2
Z2i4 + Z1i1 = vo= Z2i2 + Z1(i2 + i3) = (Z1 + Z2) i2 + Z1i3 (13.2.8)
vf vf
( Z1 + Z2 ) (1 + 3a + a 2 ) + Z1 ( 2 + a ) = vo
Z2 Z2
{(1 + 3a + a2)(1 + a) + a(2 + a)} vf = vo
vf 1
= 3 2
(13.2.9)
vo a + 5a + 6a + 1
The frequency of oscillation from Eqn. 13.2.9 can be obtained differently by considering two different
types of RC phase-shift networks shown in Figs. 13.2(a) and (b).
Case I: Phase Lead RC Oscillator

The phase lead RC network shown in Fig. 13.2(a) has
Z1 = 1/jw C, Z2 = R (13.2.10)
Z1 1
a= = jx = j (13.2.11)
Z2 w CR
where, x = 1/w CR and S = jw
Substituting the value of a from Eqn. 13.2.11 in Eqn. 13.2.9 yields as
vf 1 1
b= = = (13.2.12)
vo jx − 5x − jx 6 + 1 1 − 5x + j ( x 3 − 6 x)
3 2 2
( x 3 - 6 x)
– - tan -1
1 - 5x 2 – -q
= = (13.2.13)
2 2 2 M
d 1 - 5x i d + x3 - 6x i
Here in Eqn. 13.2.13 q can be set equal to 180° only when
x(x2 6) = 0 (13.2.14)
1
x2 = =6 (13.2.15)
ω 2o C 2 R 2
1
ω 2o = (13.2.16)
6R 2C 2
vf 1 1
w = wo, b = = = − (13.2.17)
vo 1− 5× 6 29
Oscillators
#$#
Equation 13.2.17 indicates that for oscillation to occur, |Ab | ≥ 1

1
Since, |Ab | ≥ 1, hence A ≥1
29
|A| ≥ 29 (13.2.18)
Case II: Phase Lag RC Oscillator

The phase lag RC network is shown in Fig. 13.2(b),
Z1 = R, and Z2 = 1/jw C (13.2.19)
Z1
a= = jw CR = SCR = jx (13.2.20)
Z2
Substituting the value of a from Eqn. 13.2.20 in Eqn. 13.2.9 yields
vf 1 1
b= = = (13.2.21)
vo − jx − 5x + j 6 x + 1 1 − 5x − jx ( x 2 − 6)
3 2 2
Ê x( x2 6) ˆ
–+ (tan 1 Á ˜
1 Ë 1 5 x2 ¯
= = (13.2.22)
2 2 3 2 1 Ê x( x2 6) ˆ (1 5 x2 ) 2 + ( x3 6 x) 2
(1 5 x ) + ( x 6 x) – tan ÁË 1 5 x 2 ˜¯
Herein Eqn. 13.2.22 q = 180° only when

x(x2 6) = 0 (13.2.23)
2
x = w2oC2R2 =6 (13.2.24)
6
w2o = (13.2.25)
R C2
2
vf 1 1
For w = wo, b = = = − (13.2.26)
vo 1− 5× 6 29
Equation 13.2.27 indicates that for oscillation to occur, |Ab | ≥ 1 (13.2.27)
|A| ≥ 29 (13.2.28)
The above equations are valid for devices whose input impedance seems to be very high, ideally
infinite, such as vacuum tube, FET and operational amplifiers. Since the input resistance of the BJT is
very low, the above equations are not valid for BJT RC phase-shift oscillators. Hence, the BJT oscillators
are dealt separately.
#$$
13.2.2 RC Phase Lead BJT Oscillator

An RC phase lead type BJT oscillator that falls in the frequency range of audio oscillator is shown in
Fig. 13.4(a). Fig. 13.4(b) is simplified as Figs. 13.4(c) and 13.4(d). From Fig. 13.13.4(d),
FG
v1 = R +
1 IJ *
ib (13.2.29)
H SC K
Figure 13.4(a) RC phase-lead BJT oscillator
Figure 13.4(b) ac circuit of phase-lead BJT oscillator
Figure 13.4(c) Equivalent circuit of phase-lead oscillator

Oscillators
#$%
i1 =
v1 *
+ ib = 1 +
1 FG
ib* + ib* = 2 +
1
ib*
IJ FG IJ (13.2.30)
R SCR H SCR K H K
v2 = v1 +
1 FG
i1 = R +
1 *
ib +
FG
IJ
2 1
+ 2 2 ib* = ( R +
3 IJ
1
+ 2 2 ) ib* (13.2.31)
SC HSC H
K
SC S C R K
SC S C R
i =i +i =i +
v F 1 IJ i + FG1 + 3 + 1 IJ i
= G2 + 2 * *
3 1
R H SCR K H SCR S C R K
2 1 b 2 2 2 b
Ê
= Á3 +
4 1 ˆ F 3S C R + 4SCR + 1I i *
2 2 2
*
+ ˜¯ i = G JK b b (13.2.32)
Ë SCR S C R H SCR 2 2 2 2 2 2
v =v +
i F 3 + 1 IJ i + FG 3 + 4 + 1 IJ i
= GR + 3 * *
SC H SC S C R K H SC S C R S C R K
3 2 2 2 b 2 2 3 3 2 b
F 6 + 5 + 1 IJ i = FG S C R + 6S C R + 5SCR + 1IJ i
= GR + *
3 3 3 2 2 2
*
(13.2.33)
H SC S C R S C R K H 2 2
S C R K 3 3 2 b 3 3 2 b
i =
v
=G
F S C R + 6S C R + 5SCR + 1I i
3
3 3 3 2 2 2
*
(13.2.34)
4
R HC S C R R
JK 3 3 2
C
b
Applying nodal equation at node v3 yields

Ê 3S 2C 2 R 2 + 4 SCR + 1ˆ *
hfeib = i3 + i4 = Á i +
S 3C 3 R 3 + 6 S 2 C 2 R 2 + 5SCR + 1 *
ib
F I
Ë S 2C 2 R 2
˜
¯
b
S 3C 3 R 2 RC GH JK
Ê R 1 5 ˆ * Ê 4 6 1 ˆ
= Á3 + + 2 2 2+ 2 2 ˜ ib + Á + + 3 3 2 ˜ ib* (13.2.35)
Ë RC S C R S C RR C ¯ Ë SCR SCRC S C R RC ¯
Ê R 1 5 ˆ * Ê 4 6 1 ˆ
= Á3 + - 2 2 2- 2 2 ˜ ib j Á + - 3 3 2 ˜ ib* (13.2.36)
Ë RC w C R w C RRC ¯ Ë w CR wCRC w C R RC ¯
#$&
ib
T= =1 (13.2.37)
ib*
From Eqn. 13.2.36, the imaginary part is equated to zero for the condition of oscillation to occur, i.e.
4 6 1
+ - =0 (13.2.38)
w oCR w oCRC w o3C 3 R 2 RC
2Ê R ˆ
4(w oC)2RRC + 6(w oCR)2 = (w oCR ) Á 6 + 4 C ˜ = 1 (13.2.39)
Ë R ¯
1
wo = (13.2.40)
R
RC 6 + 4 C
R
For w = wo, Eqn. 13.2.36 reduces to
RS
hfe = 3 +
R FG R
− C2R2 6 + 4 C
1 IJ R
− C2 R2 6 + 4 C
FG 5 IJ UV
T RC H 2 2
R C R K H
2
R C RRC K W
R R R
= 3+ − 6 − 4 C − 30 − 20 (13.2.41)
RC R RC
R R
hfe (min) = 23 + 29 +4 C (13.2.42)
RC R
R
If = n, then Eqn. 13.2.42 reduces as
RC
4
hfe (min) = 23 + 29 n + (13.2.43)
n
2
then, 29n (hfe 23)n + 4 = 0 (13.2.44)
(h fe − 23) ± (h fe − 23) 2 − 4∗29∗4

or, n= (13.2.45)
2∗29
Equation 13.2.45 is real if (hfe 23)2 ≥ 4*29*4, or otherwise it will become imaginary that is not
possible for the current amplification factor.
Hence, hfe > 4∗ 29 + 23 = 23 + 4∗5.38 = 23 + 21.52 = 44.52 (13.2.46)
Thus, minimum value of hfe (min) for oscillation to occur will be 44.52.
13.3 Weinbridge Oscillator

Another type of popular RC oscillator is the Weinbridge. In Weinbridge oscillator the total phase shift of
360° is provided by two stages of CE amplifier and input voltage to the amplifier is made equal to zero
Oscillators
#$'
at one particular frequency, i.e. at the frequency of oscillation by balancing the bridge as shown in
Fig. 13.5. Resistor R and capacitor C form the frequency adjustment network, while resistors RF and R1
form the feedback path for gain adjustment.
Figure 13.5 Operational amplifier Weinbridge oscillator
Assumptions
∑ Neither the b-network loads the amplifier nor the amplifier loads the b-network,
∑ The b-network does not introduce any phase-shift.
R
1 + SCR SCR
v2 = (v *L ) = (v *L ) (13.3.1)
1 R (1 + SCR ) 2
+ SCR
R+ +
SC 1 + SCR
R1
v1 = v() = (v *L ) (13.3.2)
R1 + RF
vL
v2 v1 = v(+) v() = (13.3.3)
A
SCR R1 v
2
v *L v *L = L (13.3.4)
b1 + SCRg + SCR R1 + R F A
vL
=T=
FSCR R1
A
I
*
vL GH 2
-
(1 + SCR ) + SCR R1 + RF JK
F I
= GH b1 + S / wS / wg + S / w
2
o
-
R1
JK
R1 + RF
A (13.3.5)
o o
1
where, wo = (13.3.6)
RC
For the condition of oscillations T = 1– 0∞ (13.3.7)
#%
S /w o R1 1
2
- = (13.3.8)
(1 + S /wo ) + S / wo R1 + RF A
S /w o 1 R1 R (1 + A) + RF
2 = + = 1 (13.3.9)
(1 + S /wo ) + S /w o A R1 + RF ( R1 + R F ) A
jw / w o R (1 + A) + RF
2 2
= 1 (13.3.10)
1 - w / w o + j3w / w o ( R1 + R F ) A
{R1 (1 + A) + RF }(1 - w 2 /w o2 ) + j (w + w o ){3R1 (1 + A) + 3RF - A(R1 + R F )} = 0

For zero phase-shift, the imaginary part of Eqn. 13.3.10 is equated to zero, i.e.
3{(1+A)R1 + RF} = (R1 + RF) A (13.3.11)
(A 3)RF = (2A + 3) R1 (13.3.12)
RF 2A + 3 2A
= @ =2 (13.3.13)
R1 A-3 A
Equating real part to zero yields
1
wo = (13.3.14)
CR
These derivations are perfectly valid for vacuum tube, FET, and operational amplifiers, but not for
BJT oscillator as its input resistance is very low w.r.t. tubes, FETs and Op. Amps. Hence, separate
derivations are required for BJT oscillators. A BJT Weinbridge oscillator is shown in Fig. 13.6(a). Its ac
circuit and b-network are drawn as in Fig. 13.6(b) and (c).
Figure 13.6(a) BJT Weinbridge oscillator

Oscillators
#%
Figure 13.6(b) ac circuit of BJT Weinbridge oscillator
Figure 13.6(c) b-network and its response
Since the input resistance of the BJT amplifier becomes parallel to the parallel combination of R and C,
this resistance R2 is assumed as
R2 @ Ri | |RB| |R3 (13.3.15)
vi SC1R2
b= = 2
vo S C1C2 R1R2 + S ( C1R1 + C2 R2 ) + SC1R2 + 1
1
= (13.3.16)
1+
R1 C2 F
+ jw C2 R1 - 2
1 I
+
R2 C1 GH w C1R2
JK
Equating imaginary part to zero yields frequency of oscillation as
1
w2o = (13.3.17)
C1C2 R1 R2
Substituting the value of wo from Eqn. 13.3.17 in Eqn. 13.3.16 yields
1
b (wo) = (13.3.18)
R1 C2
1+ +
R2 C1
If C1 = C2, b (wo) becomes
#%
1
b (wo) = (13.3.19)
R1
2+
R2
Since for oscillations to occur Ab ≥ 0, then
R1
Av ≥ 2 + (13.3.20)
R2
The plot of b looks like the response of series resonant circuit and its maximum value is equal to
b(wo) as shown in Fig. 13.6(c). When the bridge is balanced
1 + SC1 R1 R2
( RE ) = ( R3 ) (13.3.21)
SC1 SC2 R2 + 1
R3 S 2 C1C2 R1 R2 + S (C1 R1 + C2 R2 ) + 1
=
RE SC1 R2
R3 R C 1
= SC2R1 + 1 + 2 + (13.3.22)
RE R2 C1 SC1 R2
Equating the imaginary part gives frequency of oscillation as
1
w2o = (13.3.23)
C1C2 R1 R2
and the real part of Eqn. 13.3.20 to provide sustained oscillation is
R3 R1 C2
= + (13.3.24)
RE R2 C1
If C1 = C2 = C, and R1 = R2 = R, then (13.3.25)
R3
=2
RE
1
wo = (13.3.26)
RC
The two-variable coupled ganged capacitors or resistors can vary the frequency of oscillation. A
negative feedback is also provided through R3 and RE in order to avoid distortion and to improve the
linearity of the phases characteristic.
13.4 Radio Frequency Oscillators

The audio oscillators such as RC phase-shift and Weinbridge are not suitable for generation of high
frequency because of the limitation in fabrication of low values of R. On the other hand such low values
of inductors are easily fabricated and hence, for radio frequency oscillators, only LC circuit in different
forms such as tuned collector, tuned base, Hartley, Colpitts, or Clapp, etc. are used. Figure 13.7(a) is
the most general form of LC oscillator configuration used for radio frequency oscillation.
Oscillators
#%!
Figures 13.7(b) and (c) are its ac circuit and small signal equivalent circuits. It is evident from Fig.
13.7(c) that Z3 and hie are in parallel. The junction of Z3 and Z2 are grounded (common). Now, Z1
becomes in series with the parallel combination of Z3 and hie.
The effective load is now parallel combination of Z2 and Z1 in series with the parallel combination of
Z3 and hie. This statement is mathematically expressed as
FG Z + h Z IJ Z
1
ie 3
2
ZL =
H h +Z K
ie 3
=
{hie ( Z1 + Z3 ) + Z1Z3}Z2
(13.4.1)
hie Z3 hie ( Z1 + Z2 + Z3 ) + ( Z1 + Z2 ) Z3
Z1 + Z2 +
hie + Z3
Figure 13.7(a) Hartley/ Colpitt’s oscillator circuit Figure 13.7(b) ac circuit
Figure 13.7(c) Equivalent circuit of Hartley/ Colpitt’s oscillator
The voltage gain is expressed as

h fe h fe {hie ( Z1 + Z3 ) + Z1Z3}Z2
Av = gmZL = - ZL = (13.4.2)
hie hie {hie ( Z1 + Z2 + Z3 ) + ( Z1 + Z2 ) Z3}
#%"
FG
vo = Z1 +
hie Z3 IJ FG
h ( Z + Z3 ) + Z1Z3
i = ie 1 i
IJ (13.4.3)
H hie + Z3 K H hie + Z3 K
hie Z3
vf = i (13.4.4)
hie + Z3
vf hie Z3
bv = = (13.4.5)
vo hie ( Z1 + Z3 ) + Z1Z3
For the condition of oscillation
Avbv = 1 (13.4.6)
h fe Z2 Z3
Avbv = − =1 (13.4.7)
hie ( Z1 + Z2 + Z3 ) + ( Z1 + Z2 ) Z3
(1 + hfe)Z2Z3 + hie(Z1 + Z2 + Z3) + Z1Z3 = 0 (13.4.8)
The Hartley, the Colpitts, or the clapp oscillator, circuits can be realized using different combinations
of passive components Z1, Z2 and Z3.
13.4.1 Hartley Oscillator

The Hartley oscillator requires two inductors and one capacitor. Colpitts oscillator, on the other hand,
requires two capacitors and one inductor. A useful way to remember this is Hartley starts with the
letter H, the same as Henry inductor and thus needs two inductors. Similarly, Colpitt starts with
the letter C, the same as capacitor, so the Colpitt oscillator would require more capacitors (two)
than inductors (one).
1 -j
Z1 = = , Z2 = jw (L2 + M), Z3 = jw (L3 + M) (13.4.9)
jw C1 w C1
Figure 13.8 Hartley oscillator circuit

Oscillators
#%#
Substituting the values of Z1, Z2, and Z3 from Eqn. 13.4.9 in Eqn. 13.4.7 yields
1 jw ( L3 + M )
(1 + h fe ) jw ( L2 + M ) jw ( L3 + M ) + { jw ( L2 + M ) + jw ( L3 + M ) - j }hie + =0 (13.4.10)
w C1 jw C1
1 L +M
−(1 + h fe )ω 2 ( L2 + M )( L3 + M ) + jω {( L2 + L3 + 2 M ) − }hie + 3 2
=0
ω C1 C1
L3 + M 1
− (1 + h fe )ω 2 ( L2 + M )( L3 + M ) + jω {( L2 + L3 + 2 M ) − 2 }hie = 0 (13.4.11)
C1 ω C1
Hence, equating the imaginary part of Eqn. 13.4.11 to zero yields
1
w2o = (13.4.12)
( L2 + L3 + 2 M ) C1
1
fo = 2p ( L2 + L3 + 2 M ) C1 (13.4.13)
The real part of Eqn. 13.4.11 is equated to zero to maintain the condition of oscillation.
L3 + M
Thus, − (1 + h fe )ω 2 ( L2 + M ) ( L3 + M ) = 0 (13.4.14)
C1
L3 + M{1 (1 + hfe)w2 (L2 + M)C1} = 0 (13.4.15)
1
(1 + hfe)(L2 + M) = 2 (13.4.16)
ω o C1
2
Substituting the value of woC1 from Eqn. 13.4.12 in Eqn. 13.4.16 yields as
(1 + hfe)(L2 + M) = (L2 + L3 + 2M) (13.4.17)
L2 + L3 + 2 M L3 + M
hfe = −1 = (13.4.18)
L2 + M L2 + M
The Hartley oscillators are used in all radio receiver circuits as local oscillator.
13.4.2 Working Principle

A transient current is produced in the tank circuit as soon as the power supply is switched ON and
because of this transient the damped oscillation starts in the tank itself. This oscillation in the tank circuit
induces a voltage in the L2 due to feedback through coupling between L2 and L3. The two windings of
the autotransformer are arranged in such a manner that there is 180° phase-shift between the voltages
induced in them. Another 180° phase-shift is introduced by the BJT in CE configuration. Hence, a total
of 360° phase-shift exists around the loop and the feedback becomes positive, which is the requirement
of an oscillator.
13.4.3 Colpitt’s Oscillator

The circuit of Colpitts oscillator of Fig. 13.9 can be derived from the generalized circuit of Fig. 13.7(a).
The external passive frequency determining components for Colpitts oscillator are selected as
#%$
1 1 1 1
Z2 = = -j , Z3 = = -j , Z1 = jwL1 (13.4.19)
j w C2 w C2 jw C3 w C3
Figure 13.9 Colpitt’s oscillator circuit
Substituting the values of passive components from Eqn. 13.4.19 in Eqn. 13.4.8 yields
−
1 + h fe |RS
+ jω L1 −
1 1 FG
+
1 IJ |UVh
ie +
L1
=0 (13.4.20)
2
ω C2 C3 |T 2
H
ω C2 C3 K |W C3
Equating imaginary part of Eqn. 13.4.20 to zero yields
1 1 C + C3
w2L1 = + = 2 (13.4.21)
C2 C3 C2 C3
C2 + C3
w2o = (13.4.22)
C2 C3 L1
Equation 13.4.22 gives the frequency of oscillation. Now equating the real part of Eqn. 13.4.20 to zero
results in
−1 L1
(1 + h fe ) +
ω o2 C2 C3 C3 = 0 (13.4.23)
(1 + hfe) = w2o L1C2 (13.4.24)

Substituting the value of w2o L1 from Eqn. 13.4.22 in Eqn. 13.4.24 gives
Oscillators
#%%
C2
1 + hfe = 1 + (13.4.25)
C3
C2
or, hfe = (13.4.26)
C3
The practical circuit of Colpitts oscillator looks like the one shown in Fig. 13.9.
13.4.4 Working Principle
The transient current is produced in the tank circuit and the damped oscillation starts in it as soon as the
power supply is switched ON. A part of the damped oscillation across C3 is directly connected across
the base-emitter junction. The amplified version of the oscillation appearing across the base-emitter
junction appears in the collector side, which supplies the loss in the tank circuit because of which the
damped oscillation started. The RF choke provides isolation to the ac signal either coming from the
power supply side to the collector side or signal going from the collector side to the power side.
13.4.5 Clapp Oscillator
The Clapp oscillator is the refinement of Colpitts oscillator. In Colpitts oscillator an additional capacitor
C1 has been added in series with the inductor L1 as indicated in Fig. 13.10 that results in Clapp Oscillator.
1
Z1 = jw L1 +
jw C1
Hence, for condition of oscillation (1 + hfe) Z2Z3 + hie(Z1 + Z2 + Z3) + Z1Z3 = 0
Substituting components in place of Z1, Z2 and Z3 the condition of oscillation results as
1 + h fe F 1 1 1 Ê I 1 ˆ 1
+ h fe jw L1 +
GH + + + Á jw L1 +
JK =0 (13.4.27)
2
w C2C3 j w C1 j w C2 j w C3 Ë jw C1 ˜¯ jw C3
Equating imaginary part of Eqn. 13.4.27 to zero yields
1 1 1
jw L1 + + + =0
jw C1 jw C2 jw C3
w2o =
FG 1 + 1 + 1 IJ 1 =
FG
1 C1C2 + C2C3 + C3C1) IJ
HC C C K L
1 2 3 1 L1 H C1C2C3 K
1 1 1 1
wo = ( + + ) (13.4.28)
L1 C1 C2 C3
#%&
Figure 13.10 Clapp oscillator
The Capacitors C2 and C3 are shunted by inter-electrode (transition capacitance) and stray capacitances
and hence, the frequency of oscillation of the Colpitts oscillator changes. On the other hand, these
capacitances have no effect on C 1 in the case of Clapp oscillator and hence, its frequency of oscillation
strictly depends on C1. The value of C1 is much smaller than C 2 and C3 and hence, wo depends on just
C1 and approximate value of the frequency of oscillation of the Clapp oscillator is
1
wo = (13.4.29)
L1C1
Substituting this value of wo in the real part of Eqn. 13.4.27 yields
1 + h fe L1 1
+ ≥1
2
ω C2 C3 C3 ω 2 C1C3
1 + h fe
+
1
£ L1w2o =
FG
C1C2 + C2 C3 + C3C1 ) IJ
C2 C1 H
C1C2 C3 K
1 + h fe
£
FG C C
1 2 + C2 C3 + C3C1 )
−
1IJ C C + C2 C3 + C3C1 − C2 C3
= 1 2
C C + C3C1
= 1 2
C + C3
= 2
C2 H C1C2 C3 C1K C1C2 C3 C1C2 C3 C2 C3
C2 + C3 C
or, 1 + hfe £ = 1+ 2
C3 C3
C2
or, hfe £
C3
Oscillators
#%'
13.4.6 Tuned Collector

The tuned collector oscillator contains a tank circuit connected to the collector of the BJT as shown in
Fig. 13.11. Capacitors C1 and C E serve as short circuits across the resistors R2 and RE respectively. A
part of the output voltage is fedback as negative to its original input voltage through one of the windings
of the transformer to its input. Since R2 and RE are short-circuited for alternating voltages, the feedback
voltage appears directly across the base-emitter junction of the BJT.
Figure 13.11 Tuned oscillator
The voltage gain of the circuit shown in Fig. 13.15(a) is expressed as

h fe
Av = gmZL = ZL (13.4.30)
hie
1 R + jw L p
where ZL = ( R + jw L p ) || = (13.4.31)
jw C 1 - w 2 L pC + jw CR
Since the voltage feedback in this case is through the mutual coupling, the feedback factor
- jw M
bv = (13.4.32)
R + jw Lp
For oscillations to occur, Av bv = 1 (13.4.33)
h fe R + jw L - jw M
p
¥ ¥ =1 (13.4.34)
hie 1 - w 2 LpC + jw CR R + jw M
or hfe(1 w2LpC) + jw CRhie = jw Mhfe (13.4.35)
Real part equal to zero, give the frequency of oscillation, i.e.
1
wo = (13.4.36)
Lp C
#&
Equating the imaginary part of Eqn. 13.4.35 yields the mutual inductance as
M = CR
Fh I ie
(13.4.37)
GH h JK
fe
13.5 Crystal Oscillators

The crystal controlled oscillators overcome the major drawback of the BJT oscillators. The main
disadvantage of BJT oscillator is that its frequency of oscillation shifts during continuous operation for
a long duration. This shift in the frequency of operation is due to many parameters affecting it. The
important parameters that are responsible for the shift in the frequency of BJT oscillator are as follows:
∑ The active parameters of BJT which participate in the frequency determination shift due to
temperature and power supply variations.
∑ The external passive frequency determining components R, L, and C change with the change in
the temperature. Hence, oscillation frequency changes.
These factors are well taken over by the crystal controlled oscillators. Crystal controlled oscillators use
some type of piezoelectric crystals.
13.5.1 Piezoelectric Crystal

The natural shape of the Piezoelectric crystal is hexagonal. (The wafer surface cut perpendicular to any
of the axis is called that axis cut). Figure 13.12 shows x-axis and y-axis cuts as they are perpendicular
to these axes respectively.
The Piezoelectric crystals exhibit a property that if a mechanical stress is applied across one face, the
electric potential is developed across opposite face. The inverse is also true. This phenomenon is called
Piezoelectric effect. Thus, when an alternating electric potential is applied across one face as shown in
Fig. 13.13, it produces mechanical vibrations.
Figure 13.12 x-axis and y-axis cuts
These mechanical vibrations become maximum when the frequency of applied alternating potential
matches with the natural frequency of oscillation of the crystal. Hence, the crystal vibrates with the
maximum amplitude of vibration at resonant frequency. Its electrical equivalent circuit looks like the one
shown in Fig. 13.13.
Oscillators
#&
When the crystal does not vibrate, it is like a capacitor with the crystal itself as the dielectric as
shown in Fig. 13.13. Hence, in its equivalent circuit of Fig. 13.13, the capacitor C1 represents the non-
vibrating capacitance of the crystal.
The vibrating crystal is represented by a series r, L, C circuit as demonstrated in Fig. 13.13.
∑ L Æ mass of the vibrating crystal
∑ C Æ elasticity of the vibrating crystal
∑ r Æ mechanical friction and
∑ C1 Æ capacitance between faces of the crystal due to crystal holder
Figure 13.13 Piezoelectric crystal circuit, equivalent circuit
The impedance of the equivalent circuit shown in Fig. 13.13 comes out to be
1 1 S 2 LC + SCr + 1
Zs = r + jw L + = r + SL + =
jw C SC SC
FG 1 IJ S 2
LC + SCr + 1
Z = Zs
1
=
H SC K
1 SC
=
S 2 LC + SCr + 1
(13.5.1)
SC1 1 S 2 LC + SCr + 1 S {( S 2 LC + 1) C1 + ( SC1r/ + 1) C}
+
SC1 SC
Equation 13.5.1 has one-pole at the origin and two-poles elsewhere. The zero exists between the pole
at origin and other poles. Its reactance plot looks like the one shown in Fig. 13.14(a).
The impedance plot of the crystal is shown in Fig. 13.14(b). Here, zeros determine the series resonant
frequency whereas, the poles determine the parallel resonant frequency.
w2LC + jw C + 1 = 0 (13.5.2)
w2z = 1 (13.5.3)
LC
At wz the value of impedance is = Z(wz) = r (13.5.4)
The parallel resonance occurs at the pole frequency.
w2pLCC1 + C + C 1 = 0 (13.5.5)
C + C1
w2p = (13.5.6)
LCC1
The crystals are available in the frequency range of 15 kHz to 32 MHz. The values of r, L, C, and C 1
are such that the pole and zero frequencies are in the close proximity. It is evident from Fig. 13.14a that
#&
the phase-shift changes suddenly from 90° to + 90° in between frequency wz and wp as the capacitive
reactance becomes inductive reactance just crossing the x-axis.
dφ
Hence, = measure of frequency stability (13.5.7)
dω
dφ
As increases, the stability also increases. If Q of the crystal is very high (infinite Q can be
dω
realized with ideal inductor having zero resistance), the change in phase-shift will be abrupt, i.e.
dφ
= ∞ . Hence, the crystal oscillator has excellent frequency stability provided that Q is very high and
dω
the values of L and C do not change. R represents the crystal loss (very small). Hence, the quality factor
of the crystal may be as high as 20,000. The quality factor as high as 106 has already been reported in
the literature.
Typical dimensions of the x-cut crystal are: Thickness = 6 cm, Width = 3.3 cm (along y-axis), and
Length = 2.7 cm.
Figure 13.14(a) Pole-zero plot of piezo crystal Figure 13.14(b) Z versus frequency plot
The corresponding frequency of resonance using the thickness mode of vibration is 466 kHz. Its
electrical equivalent circuit elements are
C1 = 6 pF, L = 3.1 H, C = 0.04 pF, r = 404 KW
C
Its Q is as high as 2,400. Since, the ratio = 0.006666, the electrostatic coupling between vibrating
C1
crystal and the external circuit is negligibly small. If we neglect the value of r in the equivalent circuit of
the crystal depicted in Fig. 13.13, then Eqn. 13.5.1 reduces to
1
S2
S 2 LC + 1 S 2 + ω 2z
+
Zc = = LC = (13.5.8)
2
S ( S LC + 1) C1 + C F
SC G S
1
2
+
1
+
1 IJ SC1 ( S 2 + ω 2p )
H LC LC1 K
Oscillators
#&!
where wz =
1
and wp =
FG
1 1 1
+
IJ (13.5.9)
LC H
L C1 C K
Typical circuits of crystal controlled oscillators are shown in Figs. 13.15(a) and (b). Figures 13.15(c)
and (d) are equivalent and simplified equivalent circuits of crystal controlled oscillator.
Figure 13.15(a) Crystal oscillator Figure 13.15(b) Crystal controlled Hartley oscillator
Figure 13.15(c) Equivalent circuit Figure 13.15(d) Simplified equivalent circuit
From Figs. 13.15(d)

FG
− gm vπ' rπ IJ
vp =
H
SC1 1 + SC2 rπ K
1 S 2 + ω 2z rπ
+ 2 2
+
SC1 ( S + ω p ) SC1 1 + SC2 rπ
vπ - gmrp
= = T = 1– 0∞ (13.5.10)
'
vπ (S 2 + w 2z )C1 (1 + SC2 rp )
1 + SC2rp + SC1rp +
(S 2 + w 2p )C1
For oscillation T = 1– 0∞ = 1 + j(0) (13.5.11)

#&"
Hence, separating the real and imaginary parts from Eqn. 13.5.11 as
1 + gmrp =
(w 2 - w z2 ) C 1 w 2 - w z2
= 2 (13.5.12)
(w 2 - w 2p ) C 1
w - w 2p
(w 2 - w z2 )C1C2 ( w 2 - w 2z )C2
C1 + C2 = = (13.5.13)
(w 2 w 2p ) C 1
w 2 w 2p
Equating the imaginary part of Eqn. 13.5.10 to zero results in the natural frequency of oscillation wo, i.e.
(C1 + C2)(w2o w2p) = ( w2o w2z)C2 (13.5.14)
w2o {(C1 + C2) + C2}= w2p (C1 + C2) + w2zC2 (13.5.15)
(C1 + C2 )w 2p + w z2C 2 (K + 1)w 2p + w z2
w2o = = (13.5.16)
C1 + 2C2 K+2
C1
where, k= (13.5.17)
C2
Thus, the frequency of oscillation must be between wp and wz and the difference between them is of
only few cycles (at most, a few kHz).
C1 + C2 C
1 + hfe = = 1+ 1 (13.5.18)
C2 C2
C1
hfe = =K (13.5.19)
C2
Example
For the values of crystal constant Cm = 6 pF, L = 3.1 H, Cs = 0.04 pF, and r = 4.4 K, obtain the pole and
zero frequencies.
1 1 106
wz = = = = 2.84 MHz
LC 31
. ¥ 0.04 pF 0124
.
wp =
FG
1 1 1
+
IJ = 1012 FG
1
+
1 IJ
= 2.84 MHz
H
L C1 C K H
. 0.04 6
31 K
The difference in wp wz = (2.85 2.84) MHz = 0.01 MHz = 10 kHz.
13.6 Unijunction Transistor (UJT)

The word unijunction stands for one junction device. Hence, UJT is one junction transistor. The unijunction
transistor (UJT) has many uses in the electronic industry. It is used in multivibrators, sawtooth waveform
Oscillators
#&#
generators, and timing and time delay applications. UJTs are frequently used to trigger larger current
carrying devices such as the Silicon Controlled Rectifier (SCR). The construction, circuit symbol and
equivalent circuit of UJT are shown in Fig. 13.16.
Figure 13.16 Representation of unijunction (construction, circuit symbol, equivalent circuit)
The heart of the device is a highly doped n-type Silicon bar to which are attached two-leads, Base-1
(B1) and Base-2 (B2). These terminals make ohmic contacts to the n-type bar. A p-material is diffused
in the bar and a connection is taken out from the p-material, called emitter (E). The p-n junction diode
is symbolized in the conventional manner by an arrow showing the direction of conventional current in
forward biased case. The n-type Silicon bar is represented by two-bulk resistances RB1 and RB2.
RBB = RB1 I E =0 + RB 2 (13.6.1)

The interbase resistance (RBB ranging from 4 K to 10 K) is the resistance between the two-base leads
B1 and B2 and is equal to RBB = RB1 + RB2. The RB1 is larger than RB2 with the emitter open and is
variable. Since voltage divide proportionally along resistance, the voltage drop across RB1 (vary from
4K to 50 W) is higher than that across RB2 with the emitter open. The fraction of total resistance
represented by RB1 out of RBB is known as intrinsic stand off ratio by the Greek letter, h, i.e.
R B1 R
h= = B1 (13.6.2)
RB1 + RB 2 R BB IE = 0
RB1VBB
VB1 = = hVBB IE = 0
(13.6.3)
RB1 + RB 2
The value of h ranges from 0.4 to 0.8 depending upon construction and emitter bias. The low output
impedance of the UJT is ideal for driving the SCR that has relatively low input impedance from gate to
cathode.
13.6.1 UJT Characteristic Curve

Let us suppose that the emitter of the UJT is biased such that some emitter current flows. Recall that the
conductivity of the material is proportional to the number of holes and electrons available to carry
current. When emitter to Base-1 junction is forward biased, the emitter material (p-type) injects holes
into the n-type bar. These injected holes are repelled by positive potential connected to Base-2 towards
#&$
Base-1 and holes are accumulated in Base-1 region. Thus, the conductivity modulation of Base-1 takes
place and so RBB becomes a variable resistance and with more forward bias more holes are injected and
hence RB1 is reduced until the lowest value is reached, called the saturation resistance RB1(sat). If only the
emitter to Base-1 junction is forward biased with Base-2 open, the characteristic curve is as shown in
Fig. 13.17.
Figure 13.17 Characteristic curve of UJT
The emitter current IE increases rapidly once forward bias voltage exceeds the inherent potential
barrier voltage (0.7 V) of the p-n junction. Figure 13.18 is the circuit for generating the more frequently
used static emitter characteristic curve. Now, a voltage VBB is also applied between the Base-1 and
Base-2 creating a current IB2. We set a fixed value of VEE and note down the magnitude of the voltage
across RB1 for certain value of VBB. This fraction of voltage is represented by hVBB. This voltage
appears across diode D1 as reverse voltage and the resulting diode current is called leaking current IEO
as indicated on the output characteristic of Fig. 13.18. As the voltage VEE is increased the diode remains
reverse biased because of its own barrier potential (0.7 V) and also because of the positive reverse bias
created by the voltage across RB1 (= hVBB). Because of the reverse bias condition of the diode, the
emitter current is low and the UJT is said to be in the off condition (or cut-off). Before any appreciable
emitter current can flow, VEE must exceed the voltage across RB1 (= hVBB) plus the barrier potential of
the diode, VD1 . This is the critical or peak voltage, VP of the UJTor the voltage at which emitter current
begins to flow (conduction starts).
Vp = VD1 + VB1 = VD1 + hVBB (13.6.4)
Figure 13.18 Characteristic curve of UJT

Oscillators
#&%
For small value of VD1 as compared to hVBB (VD1 = 0.7V), VP = hVBB. For VEE = 0, IE = IEO (just
like reverse saturation current of the transistor). As VEE increases IEO decreases and ultimately becomes
zero. Once the peak voltage has been reached emitter current begins to flow and drastic phenomena
occur that are unique to the UJT(compared to the BJT). Carriers are injected in the bar between emitter
and Base-1, causing its resistance to drop drastically. As emitter current continues to increase, the
resistance RB1 decreases causing the voltage across RB1 to decrease. Normally when current increases,
voltage increases (Ohms law). In this case the opposite occurs and the region is referred to as the
negative resistance position of the characteristic curve shown in Fig. 13.19.
Figure 13.19 Negative resistance in UJT
It is evident from Fig. 13.19 that to the left of VP, the emitter current IE is never greater than IEO that
nearly equals the reverse biased leakage current ICO of the BJT. Thus, this region is called cut-off
region.
Once the conduction starts at VE = Vp, the emitter volatage VE drops with increasing IE. This
corresponds to decrease in RB1 with increasing IE. Thus, the device depicts a negative resistance region
that is stable enough to be used in many applications such as oscillator trigger circuit, sawtooth generator,
timing circuits, etc. Ultimately a valley point is reached and further increase in IE places the device into
saturation region and R B1 = RB1 (sat) as indicated in Fig. 13.19.
This unstable condition occurs automatically without any adjustment of supply voltage VEE. When
R B1 reaches its lowest value, called the saturation resistance R B1 (sat), the emitter voltage VE reaches its
lowest value and the point VV referred to as the valley point of the curve is reached.
Raising the supply voltage VEE produces emitter current in excess of the valley current and causes a
voltage drop across the bulk resistance of the emitter and Base-1. As current increases voltage increases
producing a positive saturation resistance as indicated in Fig. 13.20. For fixed values of h and VD1 , the
magnitude of VP will vary as VBB as VP› = hVBB› + VD1
#&&
Figure 13.20 Saturation resistance in UJT
13.6.2 UJT Applications

The most common use of UJT is in triggering of SCRs and multivibrators. The UJT may be used as any
of the basic multivibrators by selecting the load line properly. Its best use is as stable (free-running)
multivibrator. The selection of R1 and R2 must be done such that the dc load line cuts the characteristic
of the UJT once in its negative resistance region (point A in Fig. 13.21). In other words it must cut the
UJT characteristic to the right of peak point VP and left of the valley point VV. Point A becomes the
operating point because there is no other place of intersection of the load line and the characteristic.
Figure 13.21 Load line of UJT
The ability of the capacitor to store energy and to oppose any change in voltage across it produces
oscillations in it. Hence, a capacitor is added to the emitter and ground of the UJT in Fig. 13.21 to make
the circuit more unstable. Figure 13.22(a) shows the basic UJT oscillator where R1 and R2 are added in
order to develop a signal between the base-1 and emitter for the UJT to operate as a relaxation oscillator.
The load line must cut the UJT curve to the left of the valley and cross it only once. When power is
applied, the capacitor C starts charging through resistance R with a time constant RC.
Oscillators
#&'
Figure 13.22(a) A stable circuit of UJT Figure 13.22(b) VR2 with IE = 0
At IR = IP and VE = VP, the equality IR = IP is valid as the charging current of the capacitor at this
instant of time, is zero, i.e. the capacitor at this moment of time changes from charging to discharging
state. Then
VE = VBB IRR (13.6.5)
IRR = VBB VE = IpR = VBB Vp at peak point (13.6.6)
VBB − VP
In order to ensure firing of the UJT, R < (13.6.7)
IP
At the valley point IE = IV and VE = VV so that (13.6.8)
VBB IRR = VE (13.6.9)
or VBB IVR = VV (13.6.10)
VBB − VV
R= (13.6.11)
IV
In order to ensure turning off of the UJT,
VBB − VV
R> (13.6.12)
IV
Thus, the range of R is limited by
VBB − VV V − VP
< R < BB (13.6.13)
IV IP
The voltage drop VR1 across R1 when IE = 0 from Fig. 13.22b is
VBB R1
VR1 = (13.6.14)
R1 + RB1 + R B 2 + R2 I E =0
The moment VBB is applied, vE (= vC) charges towards VBB from VV through R as shown in Figs.
13.22(b) and (c) with the time constant t1 = RC. The charging equation is given by
#'
vC = VV + (VBB VV)(1 et/RC) (13.6.15)

The voltage VR1 is obtained in Eqn. 13.6.14 during charging time.
At the moment vC = vE = Vp, the UJT enters into conduction state and the capacitor will start
discharging through RB1 + R1 at a rate determined by the time constant (RB1 + R1)C as indicated in Fig.
13.22(d). The discharge equation for the voltage vE = vC is expressed as
− t /( R B1 + R1 ) C
vC = V p e (13.6.16)
Equation 13.6.16 is somewhat complicated by the fact that RB1 will decrease with increasing values
of IE and VBB and R1 will affect the discharge rate and the final value. The equivalent network of
discharge is shown in Fig. 13.22(d). The voltage drop VR1 across R1 during discharging will be
(V p − VD1 ) R1
VR1 = (13.6.17)
RB1 + R2
Figure 13.22(c) Charging and discharging path Figure 13.22(d) Equivalent network
Now the charging time t1 can be determined from Eqn. 13.6.15 as

vc(charging) = VV + VBB VV (VBB VV)et/RC = VBB (VBB VV)et/RC (13.6.18)
− t1 / RC
At, t = t1, vC = Vp and Vp = VBB − (VBB − VV )e (13.6.19)
− t1 / RC
(VBB − VV ) e = VBB Vp
t1 / RC
(VBB − V p )e = (VBB VV)
t1 V − VV
= ln BB
RC VBB − V p
VBB − VV
t1 = RC ln (13.6.20)
VBB − V p
Oscillators
#'
vc(discharging) = VP e −t /( R B1 + R1 )C (13.6.21)
Assuming t1 as t = 0 for discharging equation, at t = t2 gives vc= VV (13.6.22)
− t /( R B1 + R1 ) C
VV = VP e (13.6.23)
Vp
e + t / ( RB1 + R1 )C =
VV
t2 = ( R B1 + R1 )C ln
FG V IJ
P
(13.6.24)
HV K
V
The complete period of one cycle = t1 + t2 = T
VBB − VV VP
T = RC ln + ( R B1 + R1 ) ln (13.6.25)
VBB − VP VV
As VV << VBB, Eqn. 14.6.25 reduces to
T = RC ln{
1
} + ( R B1 + R1 )C ln
Vp FG IJ (13.6.26)
V VV H K
1− P
VBB
If VD1 is ignored in Eqn. 14.6.4 Vp = hVBB + VD1 ≥ hVBB, then Eqn. 14.6.26 reduces to
T = RC ln
FG 1 IJ + ( R B1
FG V IJ
+ R1 )C ln P
(13.6.26)
H1− ηK HV K
V
This is the time period of a relaxation oscillator with the oscillation frequency
1
fosc = (13.6.27)
T
Typical values of R1 and R2 are 100 W to 200 W, but usually R1 is less than R2.
Discussions
This rise in VE (Fig. 13.21) is along the cut-off region of the UJT until Point-B (the peak) is reached.
Without capacitor C the voltage would drop immediately to Point A and remain there. With the capacitor
in the circuit, the voltage can not drop immediately. As the capacitor discharges, the discharging current
(emitter current) moves to the right as shown by the dashed curve. As the capacitor discharges, the
voltage drops (emitter voltage and capacitor voltage are the same) and intercepts the UJT curve at Point-
C (on down to the valley). In order to reach a stable operating point the voltage must rise up to the value
represented by Point-A, but because the capacitor voltage can not change rapidly enough, the operation
is shifted to Point-D (cut-off) and the process repeats itself. The loop from point-B back to D usually
takes place in much shorter time than the rise along the cut off region to Point-B. This is due to the short
time constant (RC). Recall that R is reduced to a low value when there is emitter current. The discharge
of capacitor takes place between time t1 and t2. The short conduction causes a sharp spike produced
across RB1 shown as VB1 . A rough estimate of frequency has been derived which is valid for most UJT
oscillators.
#'
1. In the relaxation oscillator of Fig.13.22(a), 12 × (2.5 + 01.)

if VBB = 12 V, R = 50 K, R1 = R2 = 0.1 K, C = + 0.7
01. + 5 + 01
.
= 0.1 mF, RBB = 5 K, h = 0.5, VV = 1 V,
IV = 10 mA, Ip = 10 mA, and RB1 = 0.1 K 12 × 2.6
= =6V
5.2
during discharge time, determine (i) RB1
VBB − VV V − VP
and RB2 in charging phase, (ii) Vp, the < R < BB ,
IV IP
minimum voltage to turn ON the UJT, (iii)
the permissible range of R, (iv) frequency 12 - 1 12 - 6
or <R< ,
of oscillation, if RB1 = 0.1 K during dis- 10 mA 10 m A
charge, and (v) Sketch vC and VR2 for one 1.1 K < R < 600 K
complete cycle. The value of R = 50 K (selected) falls
in this range. Hence, the circuit will
work.
VBB − VV
(iii) t1 = RC ln
VBB − V p
Ê 12 - 1 ˆ
= (50 K ¥ 0.1 m F)ln Á
Ë 12 - 6 ˜¯
Ê 11ˆ
= 5 ms ln Á ˜
Ë 6¯
= 5 ms 1n(0.166) = 5 ms ¥ 0.61
= 3.03 ms
t2 = ( RB1 + R1 )C ln
FV I
P
GH V JK
V
Figure 13.23
Ê 6ˆ
= (0.1 + 0.1) K ¥ 0.1 mF ln Á ˜
Ë 1¯
Solution:
= 0.02 ms(6) = 0.02 ms ¥ 1.79
RB1 R = 0.036 ms
(i) h = 0.5 = = B1 ,
RB1 + RB 2 5K Hence, time period
RB1 = 2.5 K, RB2 = 5 2.5 = 2.5 K = T = t1 + t2 = 3.03 + 0.036
VBB ( RB1 + R1 ) = 3.066 ms.
(ii) vc = Vp = + VD1
R1 + RB2 + RB2 + R2 Thus, the time period is predominated
by the charging time.
Oscillators
#'!
(iv) The frequency of oscillation FV -V IR (6 − 0.7)01

.
P D1
VR1(discharging) = GH R + R JK 1 =
1 1000 B1 1 0.2
= fosc = = = 326 Hz
T 3.066 5.3 × 01
.
VBB R1 = = 2.65 V
VR1(charging) = 0.2
R1 + RB 2 + RB 2 + R2 2. Obtain the loop gain of circuit shown in
12 × 01
. Fig.13.24. Also obtain frequency for zero
= = 0.23 V loop-phase and RF/R1 for oscillation.
5.2
Figure 13.24
Solution: X CVO R
V+ = I2R =
VO = (R + XC)I1 XCI2, R + 3RX C + X C2
2
(R + 2XC)I2 XC I1 = 0, VO R / SC
=
(R + 2 XC ) R 2 + 3R / SC + 1 / S 2 C 2
I1 = I2
XC VO R
= 2
Hence, R SC + 3R + 1 / SC
VO R
(R + 2 X C ) =
VO = ( R + X C ) I 2 - X C I2 3R + jw CR 2 - j1/w C
XC
V+ R
R 2 + 3RX C + 2 X C2 − X C2 or b = =
or VO = I2 VO 3R + jw CR 2 - j / w C
XC
RF
R 2 + 3RX C + X C2 Gain = Av = 1 +
= I2 R1
XC
or I2 = 2
X CVO
Loop gain = Avb = 1 +
FG RF IJ
R + 3RX C + X C2 H R1 K
#'"
F I The magnitude for oscillation

GH 3R + jw cRR - j / w C JK
2
FG1 + R IJ R = 3R
F
For oscillation to exist Avb = 1 H RK 1
FG
or 1 +
RF IJ
R = 3R + jw CR 2 - j / w C or
RF
=2
H R1 K R1
Hence, for zero phase frequency, jw0CR2 3. Obtain the loop gain of circuit shown in
j/w0C = 0 Fig.13.25. Also obtain frequency for zero
loop-phase RF and R1 for oscillation.
or w20 = 1/C2R2
Figure 13.25
Solution: RVO X C
V+ = I2XC =
( 2 R + X C ) I 2 − RI I = 0 R 2 + 3RX C + X C2
(2 R + X C ) VO R / SC
I1 = I 2 and =
R R + 3R / SC + 1 / S 2 C 2
2
VO = ( R + X C ) I 1 − RI 2 VO R
= 2
(2 R + X C ) R SC + 3R + 1 / SC
= ( R + X C ) I 2 − RI 2
R VO R
=
(2 R 2 + 3RX C + X C2 ) − R 2 3R + jw CR2 - j1 / w C
= I2
R V+ R
or b = =
R 2 + 3RX C + X C2 VO 3R + jw CR 2 - j / w C
= I2
R RF
Gain = Av = 1 +
RVO R1
I2 = 2
R + 3RX C + X C2 Loop gain = Avb
Oscillators
#'#
The magnitude for oscillation

FG
= 1 + RF IJ FG R
2
IJ
H R K H 3 R + jw CR - j / w C K
1 FG1 + R IJ R = 3R
F
For oscillation to exist Avb = 1 H RK 1
FG RF IJ RF
or 1 + R = 3R + jw CR 2 - j / w C or =2
H R1 K R1
Hence, for zero phase frequency, 4. Find the loop gain for the circuit in
Fig. 13.26. Find the values of C and RF for
jw 0 CR 2 - j / w 0 C = 0
R = 10 K at frequency of oscillation =
or w20= 1/C2R2 10 kHz.
Figure 13.26
Solution: VO VO 2VO
I5 = I3 + I4 = + +
VO RF SCRRF SCRRF
I1 =
RF VO V 3VO V
+ 22 2
= O + + 2 2O 2
VO VO S C R RF RF SCRRF S C R RF
V1 = 0 − =
SCRF SCR F 2VO V
VX = V2 − I 5 = 2 2O
VO SC SCR F S C RRF
I2 =
SCRRF VO 3V V
2 2O 3 3O2
V VO SCR F S C RRF S C R RF
I3 = I1 + I2 = O +
RF SCRRF
3VO 4V V
I = 2 2O 3 3O 2
V2 = V1 − 3 SCR F S C RRF S C R RF
SC
2VO V
VX
=
1
3+
4
+
FG 1 IJ
=
SCR F
2 2O
S C RRF
VO SCRF H
SCR S 2 C 2 R 2 K
VO − SCRF
2VO V or =
I4 = + 2 2O 2 VX 3 + 4 + 1
SCRRF S C R RF 2 2 2
SCR S C R
#'$
− S 2 C 2 RRF w 2C 2 RRF 4 4 3R 2
= = or RF = = ×
1 j ω 2o C 2 RRF R 1
3SCR + 4 + 4 + j3w CR -
SCR w CR = 12R = 120 K, and
2 2
w C RFF 1 1
= C= =
CR Ê 2 1 ˆ 2πf o R 3 2p ¥ 10 K ¥ 10 K ¥ 3
4+ j Á 3w ˜
w Ë C 2 R2 ¯
10 8
= = 0.92 nF
1 2p ¥ 3
wo = , magnitude for oscillation
CR 3 5. Find the loop gain for the circuit in
ω 2o C 2 RRF Fig. 13.27. Obtain the value of RF for R =
≥1 10 K and the frequency of oscillation to
4
begin.
Figure 13.27
Solution: ( SCR + 1)VO

V2 = V1 − I 3 =
VO SC SCRF
I1 = (2SCR + 1)VO
RF
( SCR + 1)VO S 2 C 2 RRF
V1 = 0 −
SCRF ( S 2 C 2 R 2 + 3SCR + 1)VO
=
( SCR + 1)VO S 2 C 2 RRF
=
SCRF ( S 2 C 2 R 2 + 3SCR + 1)VO
I4 =
( SCR + 1)VO S 2 C 2 R 2 RF
I2 = , I3 = I1 + I2
SCRRF (2SCR + 1)VO
I5 = I3 + I4 =
VO ( SCR + 1)VO (2SCR + 1)VO SCRRF
= + =
RF SCRRF SCRRF ( S 2 C 2 R 2 + 3SCR + 1)VO
+
S 2 C 2 R 2 RF
Oscillators
#'%
( 3S 2 C 2 R 2 + 4 SCR + 1)VO RF
= =
S 2 C 2 R 2 RF Ê 5 6 1 ˆ
R Á1 - 2 2 2 - j + j 3 3 3˜
Ë w C R w CR w C R ¯
I5 - (S 2C 2 R 2 + 3SCR + 1)VO
VX = V2 − = 1 0.408
SC S 2 C 2 RRF For oscillation wo = =
CR 6 CR
( 3S 2 C 2 R 2 + 4 SCR + 1)VO
Hence, magnitude for oscillation
S 3C 3 R 2 RF
RF

=−
3 3 3 2 2
( S C R + 6S C R + 5SCR + 1)VO2
FR 1 - 5 I ≥ 1
S 3C 3 R 2 RF GH w C R JK
2
0
2 2
VX
=
( S 3C 3 R 3 + 6S 2 C 2 R 2 + 5SCR + 1) F 5 I
or R = RG 1 -
VO S 3C 3 R 2 RF
F
H w CR JK 2
0
2
= R(1 5 ¥ 6) = 29 R = 290 K
VO S 3C 3 R3 RF
or = 6. Obtain the loop gain for the circuit shown
VX R( S 3C 3 R3 + 6S 2C 2 R 2 + 5SCR + 1)
in Fig.13.28. Find the values of RF and C
RF for oscillation to begin at 10KHz.
=
Ê 6 5 1 ˆ
R Á1 + + +
Ë SCR S 2C 2 R 2 S 3C 3 R3 ˜¯
Figure 13.28
Solution: 1 SCR
I3 = I1 + I2 = VO + VO
VO RF RF
I1 =
RF 1 + SCR
= VO
RVO R SCR RF
V1 = 0 − = VO , I2 = VO
RF RF RF
#'&
R (3 + 4 SCR + S 2 C 2 R 2 ) SCR
V2 = V1 RI3 = VO + VO
RF RF
(1 + SCR) R ( 2 + SCR) R 1 + 6SCR + 5S 2 C 2 R 2 + S 3C 3 R 3
VO = VO = VO
RF RF RF
( 2 + SCR) SCR Vx = V3 RI7

I4 = VO
RF
- R 3 + 4 SCR + S 2 C 2 R2
d iV
= o
1 + SCR RF
I5 = I3 + I4 = VO
RF
(1 + 6SCR + 5S 2 C 2 R 2 + S 3C 3 R 3 ) R
(2 + SCR) SCR = VO
= VO RF
RF
(4 + 10SCR + 6S 2 C 2 R 2 + S 3C 3 R 3 ) R
1 + SCR + 2SCR + S C R 2 2 2 = VO
= VO RF
RF
VO RF
or
=
1 + 3SCR + S 2 C 2 R 2
VO V X = (4 + 10SCR + 6S 2 C 2 R 2 + S 3C 3 R 3 ) R
RF
RF
(2 + SCR) R =
V3 = V2 RI5 = VO (4 - 6w 02C 2 R 2 ) R + jw 0 CR (10 - w 02C 2 R 2 ) R
RF
(1 + 3SCR + S 2 C 2 R 2 ) R For oscillation to occur wo = 10

VO CR
RF
Hence, magnitude for oscillation
- 2 R - SCR2 - R - 3SCR2 - S 2 C 2 R 3 - RF
= VO ≥1
RF
d4 - 6w 20 C 2 R2 R i
- R 3 + 4 SCR + S 2 C 2 R2
d iV or RF = (4R 6w20C2R3)
= o
RF
= (4 6 ¥ 10)R = 54R = 540 K
2 2 2
(3 + 4 SCR + S C R ) SCR
I6 = VO 10 1.007
RF C= = = 10.07 ¥ 109
2πf o R 10 K ¥ 10 K
1 + 3SCR + S 2 C 2 R 2 = 10.07 nF
I7 = I5 + I6 = VO
RF 7. Obtain the frequency of oscillation of the
LC oscillator shown in Fig. 13.29. The
BJT has very large b. Also obtain the gain
Oscillators
#''
for such an oscillation.
Figure 13.29 1
= fo =
The simplified circuit of the Fig. 13.29 2π ( L2 + L3 + 2 M )C
looks like that of the Colpitts oscillator.
1 106
The frequency of oscillation of Colpitts os- = =
2p 2000 ¥ 200 ¥ 10 -18 2p ¥ 0.633
C1 + C2
cillator is given as = wo = = 251 KHZ
C1C2 L1
The required amplification = hfe = C1 The corresponding feedback factor to

C2 L3 + M
maintain oscillation =
8. The Hartley oscillator of Fig. 13.8 Con- L2 + M
tains L2 = 500 mH, L3 = 1000 mH, M =
1000 + 250 1250
250 mH, C = 200 mH, RL = 10 KW, and gm = = = 1.67
= 10 mS. Calculate its frequency of oscil- 500 + 250 750
lation and magnitude of oscillation. Av = gmRL = 100
Solution: Hence, Avb = 100 ¥ 1.67 = 167 which is
much greater than unity and hence it will
Frequency of oscillation
maintain oscillation.
Questions For Practices be stabilized? What are the merits of such

oscillator?
1. Explain the working of a Weinbridge oscil- 2. Draw the structure and biasing arrange-
lator. Derive an expression for the fre- ment of a UJT and explain its characteris-
quency of oscillations. How the magnitude tics. Derive the condition of forward
breakdown.
$
3. Explain the Weinbridge oscillator circuit. 9. Plot VB1 and VB2 of Fig.13.36
Why is negative feedback employed in it, Solution:
in addition to positive feedback?
4. The RC-circuit of a Weinbridge oscillator
consists of R1 = R2 = 220 K and C1 = C2 =
250 pF. Determine the frequency of oscil-
lations.
5. In relaxation oscillator of Fig. 13.22a, if
VBB = 12 V, R = 20 K, C = 1 mF, RB1 = RB2
= 0.1 K, Ip = 100 mA, IV = 10 mA, VV = 1 V,
determine (a) Vp, (b) Rmax and Rmin, (c) T
and fosc, (d) VR2.
6. In Fig. 13.22a VBB = 40V, h = 0.6, Ip =
10mA, Iv = 5mA, VV = IV, determine the Figure 13.36
range of R. 10. Calculate the frequency of oscillation of a
7. In a UJT circuit in Fig. 13.34 with VBB = BJT phase-shift oscillator for R = 6 K, C =
20 V, h = 0.6, RB1 = 2 K(IE = 0), VD 1000 pF, and RC = 18 K. Determine the
= 0.7V, determine RBB, RB2, VRB1, and Vp. minimum value of hfe required for such
8. For the relaxation oscillator shown in oscillation.
Fig. 13.35 with RBB = 10 K, h = 0.6, Ip = 11. Calculate the frequency of Weinbridge os-
50 mA, Iv = 5mA, Vv = 1.2 V, VRB1(disch arging) cillator circuit for R = 10 K and C =
= 0.2K, R = 68 K, C = 0.1mF, R2 = 2.2 K, 2400 pF. Also determine the value of RE
determine (a) RB1 and RB2(IE = 0), (b) Vp, and R3 for its oscillation.
(c)range of R, (d) frequency of oscillation 12. For the BJT Colpitts oscillator shown in
if RB1 = 0.2 K, (e) VR2. Fig. 13.9 with circuit values as L = 100 mF,
L RFC = 0.5 mH, C 1 = 0.005 mF, C 2 =
0.01 mF, CC = 10 mF, determine frequency
of oscillation and minimum value of hfe for
such oscillation.
13. For the BJT Hartley oscillator shown in Fig.
13.8 with circuit values as L1 = 750 mH,
LRFC = 0.5 mH, L2 = 75 mH, M = 150 mH,
C = 150 pF, determine frequency of oscil-
Figure 13.34 lation and minimum value of hfe required.
Multiple Choice Questions

1. The phase difference between input and
output voltages of an oscillator is
(a) 180° (b) 360°
(c) 90° (d) 270°
Figure 13.35
Oscillators
$
2. Barkhausen criteria says

(a) Ab = 1 (b)
FG
(CR) 2 6 + 4
RC IJ
(b) Ab = 1/29 H R K
(c) Ab = 29
1
3. An electronic oscillator contains (c)
(a) amplifier without feedback 2p RC
(b) amplifier with positive feedback 11. The condition of sustained oscillation in
(c) amplifier with negative feedback BJT phaseshift oscillator is given by
(d) ac to dc converter 4 RC 29 R
4. For sustained oscillations loop gain is (a) h fe = 23 + +
R RC
(a) 0°
(b) 180° 4 RC 23R
(b) 29 + +
(c) 90° R RC
5. The maximum phase-shift produced by an
4 RC 29 R
ideal section of the RC circuit is (c) 23 + +
(a) 45° (b) 90° R RC
(c) 30° (d) 60° 12. The frequency of oscillation of FET phase-
6. The number of RC sections required in lead oscillator in radian square is
phase-shift oscillator is at least (a) 1 / 2π 6 RC
(a) 1 (b) 2 (b) 1 / 2πRC
(c) 3 (d) 4 (c) 6 / 2πRC
7. The phase-shift introduced by RC network (d) 2π / 6 RC
sections is 13. The frequency of oscillation of FET phase-
(a) more than introduced by the amplifier lag oscillator in radian square is
(b) less than introduced by the amplifier (a) 1 / 2π 6 RC
(c) equal to introduced by the amplifier (b) 1 / 2πRC
8. The phase-shift oscillator can use either (c) 6 / 2πRC
(a) phase-lead or phase-lag RC sections (d) 2π / 6RC
(b) the combination of phase-lead and 14. The-phase-shift oscillator generally con-
phase-lag RC sections tains
(c) only phase-lead RC sections (a) two-stages of RC circuit
(d) only phase-lag RC sections (b) one stage of LC circuit
9. The phase-shift oscillator can produce (c) three-stages of RC circuit
(a) rectangular wave shapes (d) four-stages of RC circuit
(b) sine waves 15. The oscillation in an LC circuit is pro-
(c) irregular wave shapes duced due to
(d) DC voltages (a) transfer of energy between L and C
10. The frequency of oscillation in radian of (b) transfer resistance between L and C
BJT phase-shift oscillator is (c) none of the above
16. Oscillations must employ
1 (a) negative feedback
(a)
FG
(CR ) 2 6 + 4
RC IJ (b) positive feedback
H R K (c) neither negative nor positive feedback
$
17. The most suitable oscillator circuit for (a) 1/3 (b) 3
2 kHz frequency is (c) 1/29 (d) 1/29
(a) Hartley oscillator 26. The frequency of oscillation of the Hartley
(b) Weinbridge oscillator oscillator is expressed as
(c) Colpitts oscillator
(a) 1 / ( L1 + L2 + 2 M ) / C
(d) Tuned collector oscillator
18. Undamped oscillation requires (b) ( L1 + L2 + 2 M )C
(a) tuned circuit, amplifier, and feedback
circuit (c) ( L1 + L2 + 2 M ) / C
(b) rectifier, amplifier, and feedback cir- 27. The current amplification in Hartley
cuit oscillator comes out to be
(c) phase-shift circuit, amplifier, and (a) b L + Mg / b L +M g
1 2
feedback circuit
19. Electronic oscillator is better than me- (b) ( L1 + L2 + 2 M )
chanical one because (c) ( L1 + 2 M )( L2 + 2 M )
(a) it has better frequency stability 28. The frequency of oscillation of Colpitts
(b) it has higher efficiency oscillator wo is given as
(c) it can produce 20 Hz to 200 MHz
(a) (C1 + C2 ) / C1C2 L
20. The most suitable oscillator circuit for
1 MHz frequency is (b) (C1C2 ) / (C1 + C2 ) L
(a) Hartley oscillator
(b) Weinbridge oscillator (c) (C1 + C2 ) L / C1C2
(c) phase-shift oscillator 29. The current amplification factor in radian
21. The Hartley oscillator has square of Colpitts oscillator is
(a) tapped coils (a) C1/C2 (b) C1C2
(b) untapped coils (c) C1 + C2 (d) C1 C2
(c) no coils 30. Crystal oscillator is preferred because
22. The Weinbridge oscillator uses (a) it works at very high frequency
(a) negative and positive feedback both (b) it produces highly stable oscillations
(b) negative feedback only (c) it provides high output swing
(c) positive feedback only 31. An oscillator circuit
(d) none of the above (a) operates in Class A condition
23. The Weinbridge oscillator is generally used (b) cannot operate in Class A
for (c) can operate in Class A with high dc
(a) wide range of sine wave generation supply voltage
(b) narrow range of sine wave generation 32. Crystal oscillator is preferred because
(c) square wave generation (a) frequency of oscillation is between its
24. The frequency of oscillation of a poles and zero
Weinbridge oscillator is (b) frequency of oscillation falls at the
(a) 1/2pRC (b) 2pRC poles
(c) 1/RC (d) R/C (c) frequency of oscillation falls at the
25. The feedback factor b at frequency of os- zeros
cillation of Weinbridge oscillator is
Oscillators
$!
33. The stability of frequency of oscillation is (a) phase shift type

high if (b) Weinbridge type
dφ (c) Colpitts type
(a) =∞ 42. The frequency of oscillation will be stable
dt
in
dφ (a) Hartley (b) Colpitts
(b) =0
dω (c) crystal (d) Weinbridge
dφ (e) phase-shift
(c) =∞ 43. The unipolar device is
dω
(a) p-n diode
34. Oscillation occurs with
(b) BJT
(a) positive feedback having unity loop
(c) UJT
gain
44. UJTs are generally used in
(b) negative feedback having unity gain
(a) audio amplifier
(c) positive feedback having more than
(b) oscillator
unity loop gain
(c) firing circuit of SCR
35. The minimum number of RC sections re-
45. While designing a UJT relaxation oscilla-
quired in phase-shift oscillator is tor the value of the external resistance
(a) two connected between base-one (B1) and the
(b) three ground is generally preferred to be the
(c) four order of
36. The phase-shift oscillator requires an ex- (a) 100 W (b) 1 KW
ternal phase shift of (c) 10K W (d) 1 MW
(a) 90° (b) 180° 46. The V-I characteristic of a UJT between
(c) 360° (d) 270° the base terminals is similar to that of
37. The Weinbridge oscillator requires the ex- (a) an ordinary resistance
ternal phase shift of (b) a bipolar transistor
(a) 0° (c) a silicon unilateral switch
(b) 90° (d) a thyristor
(c) 180° 47. An RC oscillator is used to generate signals
38. The parallel resonant frequency (fp) and in the
the series resonant frequency (fs) in a (a) AF range
crystal are related as (b) RF range
(a) fp > fs
(c) VHF range
(b) fp = fs
(d) microwave range
(c) fp < fs
48. To generate a 1MHz signal, the most suit-
39. The coils of Hartley oscillator are
able circuit is
(a) coupled (b) decoupled
(a) Weinbridge oscillator
40. The capacitors in Colpitts oscillator are
(b) Colpitts oscillator
(a) coupled together
(c) phase-shift oscillator
(b) not coupled together
(d) none of these
41. The type of oscillators used in the simple
radio receivers is
$"

1. (b) 2. (c) 3. (b) 4. (a) 5. (d) 6. (a)
7. (c) 8. (a) 9. (b) 10. (a) 11. (a) 12. (a)
13. (c) 14. (c) 15. (a) 16. (b) 17. (b) 18. (a)
19. (a) 20. (a) 21. (a) 22. (a) 23. (b) 24. (a)
25. (a) 26. (a) 27. (a) 28. (a) 29. (a) 30. (b)
31. (a) 32. (a) 33. (a) 34. (a) 35. (b) 36. (b)
37. (a) 38. (a) 39. (a) 40. (a) 41. (c) 42. (c)
43. (c) 44. (b) 45. (a) 46. (a) 47. (a) 48. (c)
14
Power Amplifiers
14.1 Introduction
The purpose of voltage amplifier is only to provide voltage boost (gain) and not boost the current
simultaneously. The voltage or current amplifiers are designed to produce small output voltage or current
swing to avoid distortions. The linear incremental model of the transistor is based on this assumption in
order to describe it completely. The power output is not a criterion in designing either current or voltage
amplifier. In order to have sufficient amount of output power, both voltage and current swings should
be quite large. The output stage of almost all electronic systems such as radio, TV, tape recorder, PA
systems, etc. have a power stage. The output stage, thus, must deliver a specified amount of power to
the load such as a loudspeaker (in radio, TV, tape recorder, PA systems, etc.), servomotors (in control
systems), and antenna (in RF transmitter), etc. It is well known that speech signal is converted to
electrical signal by the microphone. The converted signal is very weak (of the order of few mV). Such
weak voltage cannot drive the loud speaker directly. This weak signal is first passed through a number
of amplifier stages to raise its magnitude to sufficiently high value (few volts). This voltage is now used
to drive the power amplifier. The power amplifier is capable of delivering the power required by the loud
speaker to produce equivalent sound signal.
Another important example of use of the power amplifier is in the broadcasting station to feed the
required amount of power to the radiator (antenna). A 1 KW transmitter means 1 KW power is supplied
to the antenna by the power amplifier. Power amplifiers in other applications are also used to provide
sufficient amount of power to different types of loads. For compromising between the size and economy,
the transistor in the output stage must be selected to handle the output power plus some safety factor.
$$
The maximum power can be delivered only when both voltage and current swings must cover most part
of the output characteristic of the transistor. The power dissipation is the major problem and power gain
is of interest as it is required to handle enough power in the last stage so that the preceding stage need
not be a power amplifier, but a low power current amplifier. Normally BJTs are used in power stages
for the purpose.
Our main aim is to obtain maximum power output from a given device or to obtain its maximum
conversion efficiency, i.e. conversion of dc power supply energy into the useful signal energy. We
know that the device dissipation will clearly be minimized for maximum current flow with minimum
voltage drop across the device or minimum current flow with maximum voltage drop across the device.
This criterion can be satisfied along the load at two points as
∑ VCE(max), IC(min) and
∑ VCE(min), IC(max)
Example
From Fig. 14.1 it is clear that along the load line IC(max) = 5 mA, IC(min) = 0.0 mA, VCE(min)
= 0.2 V and VCE(max) = 20 V.
The power amplifier thus, handles large swings of voltage and current and hence, it should
have been called the large signal amplifier. The name power amplifier is derived from the power
supply that is converted in the form of ac power.
Figure 14.1 Maximum current and voltage swings
14.2 Classification of Power Amplifier

The power amplifiers are classified in many ways. The simplest classification is
∑ Single ended
∑ Double ended
Power Amplifiers
$%
14.2.1 Single-ended Power Amplifiers

Single ended means the output is obtained w.r.t. one end permanently grounded. In such situations
either one or several transistors are connected in parallel to drive the load. The single-ended amplifier
circuits are shown in Figs. 14.2(a) and (b).
Figure 14.2(a) Resistance coupled and transformer coupled single-ended amplifiers
Figure 14.2(b) Transformer coupled multiple transistors in single-ended amplifiers
14.2.2 Double-ended Power Amplifiers

In double-ended amplifier none of the ends (terminal) is permanently grounded. The double ended is
often called push-pull stage. It describes two loops containing two transistors. The currents in the two
loops flow in opposite directions inside the transistor but add in the load as shown in Fig. 14.3.
Figure 14.3 Double ended configuration push-pull stage complementary stage
Almost every power amplifier has double-ended configuration. It is because two transistors share the
total output power and each transistor handles one half of power. One can use the alternative way to put
$&
two transistors in parallel as in Fig. 14.2(b), to handle the same amount of power. However, in this case
the large amount of output current due to both (or a number of transistors) flows in the same direction
through the transformer winding. This introduces a net dc magnetizing flux in the transformer that
limits the signal handling capabilities of the transformer and causes increased distortion. However, in the
double-ended stage as demonstrated in Fig. 14.3, any dc magnetizing flux created in one half of the
primary winding is cancelled by the other half of the primary winding. Thus, if the two halves of the
primary winding are balanced, no net dc magnetizing flux results.
Another reason of using double-ended stage is that the load is usually magnetic transducer such as
loudspeaker, servomotors, etc. We do wish to keep the dc out of the load to avoid magnetic saturation.
This can be achieved only with double-ended scheme. Another very strong reason in favour of double-
ended scheme is that even harmonic distortion from two sides (loops) tends to cancel. Thus, double-
ended scheme has advantages over the single ended scheme. Another classification of the power amplifiers
is set by the percentage of conduction cycle that occurs. The Class A, Class B, Class AB, and Class C
are the classification of power amplifier as per conduction duration. The waveforms for these classes
are demonstrated in Fig. 14.4.
Figure 14.4 Waveforms of Class A, B, AB, and C amplifier
Class A
Each of the transistors whether in single-ended or double-ended scheme conducts for 100% time (for
both half cycles) in Class A operation w.r.t. the input signal as indicated in Fig. 14.4.
Power Amplifiers
$'
Class B
Each of the transistors in Class B operation conducts for 50% time (for only one half-cycle) of the input
cycle. In another words each transistor conducts for only half-cycle of the input signal as demonstrated
in Fig. 14.4.
Class AB
The Class AB operation is nothing but Class B operation with the advantage of eliminating the crossover
distortion of Class B operation. In order to avoid the crossover distortion, Class B amplifier is forward
biased by the amount of VBE. Thus, it conducts for slightly more than 50% but less than 100% of the
time of the input signal. This is illustrated in Fig. 14.4.
Class C
The conduction in Class C occurs for less than 50% time of the input cycle as shown in Fig. 14.4
leading to distortion in this case. Here it is important not to preserve the shape of the signal but to get
large amount of power. Hence, Class C amplifiers are used for carrier signal amplification only where
signal reproduction without any change is not important but the power is the main criteria.
Another way of classification of the power amplifier is by arrangement of (devices) transistors
∑ Push-pull
∑ Complementary symmetry scheme
The doubled-ended scheme amplifier is the same as push-pull configuration. In complementary
symmetry scheme, if one transistor is p-n-p, then the other is n-p-n. It requires two batteries to bias
both p-n-p and n-p-n transistors properly. The most important disadvantage of complementary symmetry
scheme is the requirement of the matching characteristics of p-n-p and n-p-n transistors and two
batteries. However, the difficulties in manufacturing matched transistor pairs are gradually decreasing.
The power amplifier is capable of delivering sufficient amount of both voltage and current swings
simultaneously. The voltage or current amplifier raises either voltage or current. A very basic question
arises in the mind of the reader that do power amplifiers amplify power? The answer is no. Then why
is it called power amplifier ? It should have been called large signal amplifier as it amplifies large signals
passing through multistage amplifiers. As the power amplifier converts the dc power to the ac power, it
is called power amplifier. The output power is only controlled by the input signal but is not proportional
to the input signal. The ac power input is so small w.r.t. the power supplied by the dc power supply that
it is not even considered in calculation of its efficiency.
14.3 How Do Power Amplifier Differ From Voltage Amplifiers?

The simplest circuit of voltage amplifier is shown in Fig. 14.5(a). This circuit is biased for Class A
operation. Its dc load line is also drawn as in Fig. 14.5(a) and swing in the output signal for the
corresponding swing in the input signal is shown in Fig. 14.5(b).
$
Figure 14.5(a) Voltage amplifier and load line for Class A amplifier
Figure 14.5(b) Current and voltage variation in Class A amplifier
The average power supplied to or dissipated by any linear device is expressed as

T
P= z
0
v ( t ) i ( t ) dt (14.3.1)
where vc(t) = total voltage across the device

ic(t) = total current passing through the device
We know that
Ic = Iav + ic(t) = Iav + ic(t) (14.3.2)
Vc = Vav + vc(t) (14.3.3)
T
1
P=
T zl
o
q
Vav + v c ( t )}{ I av + i c ( t ) dt (14.3.4)
Power Amplifiers
$
T T
1 1
=
T zl
o
V av I av q dt +
T zl
o
V av i c ( t ) dt q
T T
1 1
+
T zlo
I av v c ( t ) dt + q
T zl
o
q
v c ( t ) i c ( t ) dt (14.3.5)
T T
Since
1
T z
o
v ( t ) dt =
c
1
T z
o
i ( t ) dt = 0 (average of full period = 0)
c
(14.3.6)
P = Vav Iav +
1
T z
0
v (t ) i (t )dt = power in (dc + ac) terms
c c
(14.3.7)
Thus, the average power supplied or dissipated by the device consists of the sum of the power in the
dc and ac terms.
Average power dissipated in the load
T
PR C =
1
T z
0
2
ic(rms) RC dt (14.3.8)
As ic(t) = ICQ + Icmcoswt (14.3.9)

T T
2
ic(rms) =
1
T z
0
{ I CQ + i c ( t )}
2
dt =
1
T z
0
(I
CQ
+I
cm
2
Coswt ) dt (14.3.10)
=
1
T z
0
2 2 2
( I CQ + 2 I CQ . I cm .cosw t + I cm cos w t )dt (14.3.11)
T
1
ic(rms) =
T z
0
2
( I CQ 2
+ 2 I CQ I cm cos w t + I cm cos2w t )dt (14.3.12)
T
1 I2
=
T z
0
2
( I CQ + 2 I CQ I cm cosw t + cm (1 + cos 2w t )dt
2
(14.3.13)
2 2
or i c2( rms ) 2
= I CQ +
I cm
= 2
I CQ
F I IJ
+G
cm
(14.3.14)
2 H 2K
2
PR C = ic2(rms) RC = I CQ
F I I 2
cm
R = P + PR C ( ac ) (14.3.15)
GH +
2 JK
C R C ( dc )
2
PR C ( ac )
F I IJ
=G
cm
RC (14.3.16)
H 2K
$
From Fig. 14.5(a) it is clear that maximum current and voltage swings will occur when the Q-point
is selected just in the middle of the output characteristic of the transistor along the load line. Hence,
VCC
Icm = = ICQ (14.3.17)
2 ( RC + R E )
VCC
As RC >> RE, Icm = ICQ @ (14.3.18)
2 RC
Po = PR C ( ac )
F I IR
=G
2
cm
=
2
I CQ RC
H 2 JK C
2
2 2
Ï VCC ¸ RC VCC
= Ì ˝ @ (14.3.19)
Ó 2( RC + RE ) ˛ 2 8 RC
Average power supplied by dc power supply
T T
1 1
PCC =
T z
{VCC i C ( t )} dt =
0
T z
VCC { I av + i C ( t )} dt
0
T
1
=
T z
VCC { I CQ + I R1 + R 2 } dt
0
= VCC{ICQ + I R1 + R2 } @ VCCICQ as ICQ >> I R1 + R2 (14.3.20)

The power supplied by the dc source is independent of signal current or voltage evident from
Eqn. 14.3.20. Hence dc power supplied by the dc power supply is
2
VCC VCC
PCC = VCC @ (14.3.21)
2 ( RC + R E ) 2 RC
Average Power Dissipated in the Collector

The power dissipated in the collector of the transistor is represented by PC and is mathematically
expressed as
T T
PC =
1
T z
0
v CE i c dt =
1
T Ú {V
0
CC - ( RC + RE ) ic }ic dt (14.3.22)
T T
=
1
T z
0
V CC . i c dt -
1
T z
0
2
( R C + R E ) . i c dt = PCC PR - PR
C E
(14.3.23)
T
PR C + PR E =
1
T z
0
( R C + R E ){ I
CQ
+ i ( t )} dt
C
2
(14.3.24)
Power Amplifiers
$!
R| ( I + 2 I . i
T
U|
= (RC + RE)
1
T|
S
T z
0
2
CQ
2
CQ C ( t ) + iC ( t ) dt V|
W
F 2
2 I
I cm
= ( RC + R E )G I + J (14.3.25)
GH CQ
2 JK
2
PC = PCC - PRC - PR E = PCC - ( RC + RE ) I CQ
F 2
Icm I (14.3.26)
+ GH 2 JK
Conversion Efficiency
It is defined as the ratio of output power to the input power. The input power is mainly supplied by the
dc supply VCC and an insignificant amount of ac input signal power w.r.t. the dc power supplied, i.e. the
total input power = PCC + Pin, but Pin << PCC. Hence, total input power is dependent upon the power
supplied by the dc power supply and the maximum conversion efficiency is expressed as
Pac ( output ) Pac ( out ) i c2 ( rms ) R C
h= = =
Pinput PCC VCC I CQ
2
2
I cm RC / 2 I CQ RC / 2 I CQ R C
= = =
VCC I CQ VCC I CQ 2 V CC
( VCC / 2 R C ) R C 1
= = = 25% (14.3.27)
2 VCC 4
Thus, the maximum theoretical efficiency is 25%. The practical conversion efficiency will be much less
than 25%.
Figure of Merit
The figure of merit is another useful parameter of power amplifier. This is defined as the ratio of
maximum collector dissipation power to the maximum ac power developed across the load. It is
mathematically expressed as
PC( nax) 2
VCC / 4 RC
F= = 2
=2 (14.3.28)
Pout (max) VCC / 8 RC
Eqnuation 14.3.28 indicates that twice the useful power is dissipated across the transistor.
Power Dissipated in Biasing Resistors
The power dissipated in biasing resistors can be obtained by subtracting the power dissipated across the
device out of the total power supplied by the dc power supply, i.e. power wasted = power supplied by
dc supply power dissipated across the transistor
$"
= PCC PC = VCCICQ VCEQICQ

2
= [VCC {VCC (RC + RE)ICQ}]ICQ = (RC + RE) I CQ (14.3.29)
Equation 14.3.29 gives the amount of power wasted in the collector and emitter resistances. In order
to get maximum ac power developed across the load RC that is proportional to both RC and Icm and
hence both RC and Icm should be large.
Case I
If RC is selected to be very large, the ICQ and hence Icm will be limited to very low value.
Case II
When Icm is selected to be very large, the corresponding value of RC will be very low. These two
contradictory conditions can be taken care of by separating the dc and ac current paths. In order to
achieve maximum value of Icm, the value of ICQ should be in the middle of the output characteristic of
the transistor. The maximum value of RC can be selected without disturbing the dc bias conditions. A
very simple circuit to separate the load resistance from passing the dc current through it is shown in
Fig. 14.6(a). Here the load resistance has been connected to the collector of the BJT through a blocking
capacitor C• that works as the short circuit at signal frequencies and open circuit for dc. But this circuit
is not capable of stopping the ac current passing from the dc current path, i.e. RC. Thus, ac collector
current divides in two paths, namely
∑ One part passing through the collector resistance RC
∑ The other part passing through the load resistance RL
Figure 14.6(a) Separation of ac and dc current
In Fig. 14.6(b) separate paths for ac and dc currents have been provided. The RFC choke used in
place of RC in Fig. 14.6(b) chokes the path of ac to pass through it. Thus, ac completely passes through
the load resistance RL and dc passes through the choke with very small resistance to provide large ICQ.
Attempts were made to avoid the dc loss in resistors. Also in order to maintain good stability of the
circuit RE π 0.
Power Amplifiers
$#
Condition I : Transistor cut-off

The choke provides infinite impedance to ac voltage. It can be replaced by a constant current source as
shown in Fig. 14.6(c). When transistor is cut-off, i.e. ic = 0, iL = ICQ. Hence, maximum voltage across
the capacitor plus maximum voltage across the load is expressed as
VCE = VCC + RLiL = VCC + R L

FG V IJ = 2V
CC
CC (14.3.30)
HR KL
Condition II : Transistor Saturated

The capacitor starts discharging through the saturated transistor as indicated in Fig. 14.6(e). The collector
current will be supplied by both constant current source ICQ and discharging current VCC/RL.
Open circuit voltage across the transistor = VCE = VCC + RLICQ
VCC
= VCC + R L = 2VCC (14.3.31)
RL
Its load line is drawn in Fig. 14.6(d).
Power supplied by dc supply
= PCC = VCCICQ = VCC

FG V IJ = V
CC
2
CC
(14.3.32)
HR K R
L L
Figure 14.6(b) Separation of ac and dc currents Figure 14.6(c) Charging path
Figure 14.6(d) Class A amplifier’s load line with choke Figure 14.6(e) Discharging path
$$
Equation 14.3.32 is independent of signal current.

Power developed across the load
2
I cm
= PL = i c2 ( rms ) R L = RL (14.3.33)
2
2
VCC
PL(max) = (14.3.34)
2 RL
Power dissipated across the transistor
= PC = PCC - PR L (14.3.35)
2 2
VCC I cm
PC = RL (14.3.36)
RL 2
The PC will be minimum when the second term in RHS of Eqn. 14.3.36 becomes the maximum i.e.
2 2
I cm VCC 2
VCC
for R L to become maximum = RL =
2 2 R L2 2 RL
2 2 2
VCC VCC VCC
Hence, PC(min) = = (14.3.37)
RL 2 RL 2 RL
2
VCC
PC(max) = (14.3.38)
2 RL
Hence, the conversion efficiency
PR L PR L 2
( I cm / 2 ) RL
h= = = (14.3.39)
Pin PCC VCC I CQ
2
( I cm / 2 ) RL I cm
= = (14.3.40)
( I cm R L ) I CQ 2 I CQ
Equation 14.3.40 will be maximum for maximum value of collector current. Hence, maximum efficiency
is
1
h=
= 50% for Icm = ICQ (14.3.41)
2
Equations 14.3.27 and 14.3.41 reveal that just replacing the collector resistance by choke has doubled
the efficiency. The variation in power dissipated across transistor, power developed across the load,
power supplied by the dc power supply and efficiency w.r.t. the collector current Icm is plotted as
shown in Fig. 14.6(f).
The assumption made for Fig. 14.6(b) does not hold good as the reactive impedance offered by
blocking (coupling) capacitance (C2) becomes appreciable at signal frequency. On the other hand the
Power Amplifiers
$%
reactive impedance offered by the choke becomes very low and the signal passes through the choke and
at the same time the signal is blocked by the blocking capacitor C2. Hence, the power developed across
the load becomes small. Thus Fig. 14.6(b) is not a practical circuit of power amplifier.
Figure 14.6(f) Plot of PCC, PC, PL, h versus Icm
14.4 Single-ended Transformer Coupled Stage

We know that the load of almost all electronic equipment such as radio, TV, tape recorder, PA systems,
etc. is a loudspeaker. The loudspeaker converts the electrical signal into sound signal. The aim is to get
maximum power transferred to the load (loudspeaker). The maximum power can be transferred only
when the output impedance of the power amplifier matches the load impedance. Since the output
impedance of the amplifier is significantly higher (of the order of few KW) than the very low-load
impedance (of the order of 3 W, 4 W, 8 W, etc.) a transformer with appropriate number of turns is
required to match the low impedance load to high output impedance of the amplifier as a source. A
single-ended transformer coupled power amplifier is shown in Fig. 14.7(a) for the purpose.
The transformer of Fig. 14.7(a) is simplified on its right side to explain impedance matching. The
fundamental equations governing transformer action are
(ic) vc = isvs = iLvL (14.4.1)
n1vs = n 2vp,
Figure 14.7(a) Transformer coupled Class A amplifier and impedance transformation

$&
n2 n2
vs = vL = vp = vc (14.4.2)
n1 n1
n1ip = n2is = n2iL,
n1 n1
or iL = ip = ( - ic ) (14.4.3)
n2 n2
vL
The load impedance is expressed as RL = (14.4.4)
iL
Similarly, reflected load impedance R L* across the primary winding is expressed as
vp vc ( n1 n 2 ) v L
R L* = = =
ip - ic ( n 2 n1 ) i L
2 2
F n I F I =F n I
=G
1 v
L 1
RL = n 2 RL (14.4.5)
H n JK GH JK GH n JK
2
i
L 2
The load impedance reflected across the primary winding could be as high as 625RL if the turn ratio
n1/n2 = 25. If the load impedance is 8 W, the R L* = 625 * 8 = 5 K. The load line for Fig. 14.7(a) is drawn
as shown in Fig. 14.7(b).
Figure 14.7(b) Transformer coupled load line
Maximum Power Output

The maximum swing in the collector current without distortion would be = Icm = ICQ from load line. The
power supplied by the dc power supply is expressed as
PCC = VCC ICQ (14.4.6)
2
VCC VCC
PCC = VCC = (14.4.7)
R L* R L*
2
Power transferred to load = PL(ac) =
FI IR 2
Lm
=
2
I cm FG n IJ
1
RL =
2
I cm *
RL (14.4.8)
GH 2 JK L
2 Hn K
2 2
Power Amplifiers
$'
PL(max)
FI IR
=G
2
CQ *
=
2
VCC
(14.4.9)
H 2 JK L
2 R L*
2 2
VCC I cm *
Collector Dissipation PC = PCC PL = - RL (14.4.10)
R L* 2
2
VCC
PC(max) = for no signal (14.4.11)
R L*
2
Pout(ac) ( I Lm / 2 ) RL n2 I Cm
2
RL / 2
The conversion efficiency h= = = (14.4.12)
PCC 2
VCC / R L* 2
VCC / R*L
=
2
( I cm / 2 ) R L*
=
F I I F R I = 1 = 2P
2
cm
*2
L
(14.4.13)
2
VCC / R L*
GH 2 JK GH V JK 2
2
CC
out(ac)max
Figure of Merit (F)

The figure of merit is defined as the ratio of maximum power dissipated across the transistor to the
maximum output ac power developed across the load, i.e.
2
PC(max) VCC / R L*
F= = 2
=2 (14.4.14)
Pout(max) VCC / 2 R L*
PC(max) = 2Pout(ac) max (14.4.15)

In order to get 1 W ac power across the load, the transistor selection should be such that it can
dissipate 2 W of power.
14.5 Integrated Circuit Class A Amplifier

Emitter follower is the most popular form of the circuit used in integrated circuit manufacturing as Class
A output stage of the amplifier because it has very low output resistance (impedance). Hence, the
emitter follower is analyzed for large signal operation. Fig. 14.8(a) is the circuit of an emitter follower
biased by a constant current source I = ICQ2 for the positive half-cycle of the signal.
The constant biasing current I in the emitter follower is supplied by a constant current source
connecting it to the junction of the emitter and the load resistance RL. Since the ideal current source is
assumed to have infinite internal resistance, the ac emitter current will flow through the load resistance
RL and not through the constant current source circuit.
Vo(min) = IRL (14.5.1)
Vo(min) + VCE2 = V CC
VO(min) = VCC + VCE(sat) (14.5.2)
$
Figure 14.8(a) IC form of Class A amplifier
Figure 14.8(b) Transfer curve of emitter follower Figure 14.8(c) IC form of Class A amplifier
|I| ≥
e
- V
CC
-V
CE 2 (sat) j (14.5.3)
R
L
Different waveforms of Fig. 14.8(a) are shown in Fig. 14.8(d). Considering the case when the
output is open circuited, i.e. RL = •, the collector current of T2 (ic2 = I) flows as the emitter current of
transistor T1 (ie1 @ ic1 = I). Transistor T2 supplies the constant (bias) current I. As the emitter current ie1
= I + iL, the value of I must at least be greater than the largest negative load current or otherwise
transistor T1 cuts off and Class A operation no longer maintains. The transfer curve of emitter follower
of Fig. 14.8(a) is drawn as Fig. 14.8(b). The output voltage from transfer curve is written as
Vo = VI VBE1 (14.5.4)
Power Amplifiers
$
The VBE1 in Eqn. 14.5.4 depends upon the emitter current ie1 and iL. The positive limit of the linear
region is determined by the saturation of T1. Thus,
Vo(max) = VCC VCE1(sat) (14.5.5)
The limit of linear region in the negative half - cycle of Fig. 14.8(c) is determined by either T1 turning
off or by T2 getting saturated, i.e. total I is supplied to the load resistance RL. Hence, it flows in the
opposite direction. So the bias current I is selected such that the output voltage can swing from VCC
to +VCC with the quiescent value being zero as depicted from Fig. 14.8(b). The corresponding waveform
of vCE1 = VCC vo is shown in Fig. 14.8(d). Assuming that I has been selected to allow the maximum
negative load current of VCC/RL, the collector current of T1 has waveform of Fig. 14.8(d). Similarly, the
instantaneous power dissipation across T1 is
PCE1 = vCE1ic1 (14.5.6)
The maximum power dissipated across T1 = VCCI. This indicates that the emitter follower transistor
dissipates the largest amount of power when vo = 0. Since no input signal can be present for very large
period, transistor T1 must be able to withstand a continuous power dissipation of VCCI. The product of
VCC and I is minimum when either of them is minimum. Hence, for a full period PCE1 has two minima
and two maxima as depicted in Fig. 14.8(d). Thus, frequency of PCE1 is twice the frequency of IC1 and
vCE1 as indicated in Fig. 14.8(d).
Figure 14.8(d) Signal waveforms of Class A amplifier
Second Harmonic Distortion

We have seen that the dynamic transfer curve of any active device is not linear. This non linearity arises
as the static characteristics are not equidistant straight lines for constant of input current excitation.
$
Thus, the output waveform looks different in shape from the input excitation due to non linearity in the
transfer curve. This is called non linear or amplitude distortion.
In order to investigate the distortion, instead of relating the device collector current ic linearly with its
base current ib as ic = aib, let us assume the closer relationship as
ic = aib +bi2b (14.5.7)
Where a and b are constants. If the input excitation i.e. ib is sinusoidal then
ib = Ibmcoswt (14.5.8)
2
bI bm
or, ic = aIbmcoswt + bI2bmcos2wt = aIbmcoswt + (1 + cos2wt)
2
= Bo+ B1coswt + B2cos2wt (14.5.9)
where Bo, B1, and B2 are other constants.
Equation 14.5.11 reveals that the output contains the input signal frequency along with its second
harmonics and also a constant term. The parabolic non linear distortion introduces distortion in the
output component whose frequency is twice the frequency of the input excitation signal. Also, as the
sinusoidal signal changes the average value of the output voltage, a constant term appears in the output
which is known as rectification.
Thus, the second harmonics has been introduced in the output waveform of the BJT amplifier due to
non-linearity in its transfer curve. The second harmonic distortion is defined as
B2
D2 = (14.5.10)
B1
Conversion Efficiency (h)
The power conversion efficiency is mathematically expressed as
Pac (out)
h= (14.5.11)
PCC
The power developed across the load resistance RL is expressed as
v o2 ( rms ) v o2 (max)
Pac(out) = = (14.5.12)
RL 2 RL
The power drawn from the negative supply = VCCI as the current passing through transistor T2 is
constant I. The average current of transistor T1 = I. So average power drawn from the positive power
supply = VCCI. Thus, the total dc power supplied by the dc power supply is
PCC = 2VCCI (14.5.13)
Combining Eqns. 14.5.12 and 14.5.13 yields the power conversion efficiency h as
v o2(max) / 2 R L 1 v o (max) v o (max)
h= = ¥ ¥ (14.5.14)
2VCC ⋅ I 4 I . RL VCC
Power Amplifiers
$ !
Since IRL ≥ vo(max) £ VCC (14.5.15)

The maximum efficiency can be obtained at the boundary of the inequality of Eqn. 14.5.15.
Thus vo(max) = VCC = IRL (14.5.16)
1
h= = 25% (14.5.17)
4
14.6 Double-ended Amplifier

The double-ended configuration of the amplifier is also called the push-pull power amplifier as drawn in
Fig. 14.9(a). The value of the bias resistors R1 and R2 determines the class of operation of the amplifier.
Fig. 14.10 depicts the composite load line for a Class A operation of the push-pull amplifier configuration.
The configuration of Fig. 14.9(a) requires center-taped input and output transformers. The Class B
pushpull amplifier is cut just through the middle as shown in Fig. 14.9(b). The output transformer has
a turns-ratio of 2 n1 : n2 from entire primary to secondary as shown in Fig. 14.9(c).
Figure 14.9(a) Class A push-pull stage
Figure 14.9(b) Half-section of Class B push-pull Figure 14.9(c) Output transformer
The total reflected impedance seen across the primary is

2
R L*
F
=G
2 n1 I
(14.6.1)
H n 2 JK R L
$ "
Both transistors in Class A operation of Fig. 14.9(a) drive output all the time. So both transistors are
always connected to the load through two halves of the transformer primary windings. The output
section of Class A push-pull amplifier is redrawn as Fig. 14.9(d). Its incremental model is drawn as
Fig. 14.9(e).
Figure 14.9(d) Output section of Class A push-pull Figure 14.9(e) Output circuit of Class A
The output resistance of each transistor is = 1/hoe. The two transistors seem to be in parallel through
the transformer windings as seen by the load. Hence, its equivalent is drawn as in Fig. 14.9(f).
Fig. 14.9(g) the output circuit reflected on primary side.
Figure 14.9(f) Output circuit seen from load Figure 14.9(g) Output circuit reflected to primary
The output circuit seen by each transistor can be obtained from Fig. 14.9(h) by dividing each current
source by two and multiplying each conductance by two. Fig. 14.9(h) is the circuit seen by each
transistor. Thus, the effective load seen by each transistor is 2 R L* = 2 ( n 1 / n 2 ) 2 R L . The transistor
should be biased at a Q-point just in the middle of the cut-off and saturation as indicated in Fig. 14.9(i).
Figure 14.9(h) Output circuit seen by each transistor Figure 14.9(i) Load line of each transistor
The largest possible peak in the collector current swing for undistorted sine-wave operation is then,
Power Amplifiers
$ #
VCC
Icm = (14.6.2)
2 R L*
The composite load line for Class A push-pull operation has been drawn in Fig. 14.9(i). The collector
current ic1 of T1 will increase from the quiescent value ICQ1 in the positive half - cycle of the input signal
and that ic2 of T2 will decrease from the quiescent value ICQ2 by the same amount as depicted in
Fig. 14.10. The induced voltage in the secondary of the output transformer across RL is proportional to
difference in two collector currents ic1 and ic2, i.e. (ic1 ic2).
Figure 14.10 Composite load of Class A push-pull amplifier
Let ib1 = Ibmcoswt (14.6.3)

and ib2 phase opposition of ib1 due to transformer
ib2 = ibmcos(wt + p) = Ibmcoswt (14.6.4)
ic1 = ICQ1 + ao + a1coswt + a2cos2wt + a3cos3wt + ..... (14.6.5)
ic2 = ICQ2 + ao + a1cos(wt + p) + a2cos2(wt + p) + a3cos3(wt + p) + ..... (14.6.6)
Since both half of the push-pull circuit are assumed to be identical in all respect, i.e.
|ICQ1| = |ICQ2| (14.6.7)
and ic2 = ICQ2 + ao a1coswt + a2cos2wt a3cos3wt + ..... (14.6.8)
Hence ic1 ic2 = 2a1coswt + 2a3cos3wt + 2a5cos5wt + ..... (14.6.9)
$ $
Equation 14.6.9 reveals that even harmonics and dc components are cancelled in push-pull configuration.
Since the distortion in the signal is in the form of harmonics, the magnitude of distortion decreases with
increasing harmonics. The magnitude of second harmonic distortion is much more than the third harmonic.
Thus, eliminating second harmonic minimizes the distortion to a great extent.
Advantages of Push-pull
∑ Even harmonics are not present in the output
∑ Signal output power is high
∑ The ripple coming from the power supply is balanced out
∑ Core saturation avoided as IC of both BJTs opposes each other
Disadvantages
∑ Two matched transistors are needed
∑ Unequal amplification due to unmatched BJTs
∑ Center tap transformer essential (costly affairs)
∑ Transformer is bulky and expensive
Conversion Efficiency
The Currents in the load of the composite characteristic will add and the power output is expressed
as
2
Pout(ac) = i L2 (rms) R L = ( 2 i cm ) 2
R L* =G
F (2 I ) I R = 4 FG I IJ
cm
2
* cm
. R L* (14.6.10)
H 2 JK L
H 2K
Power supplied by the dc supply = PCC = VCC(2ICQ ) =2 V G
FV I=V
CC
2
CC
(14.6.11)
CC
H 2 R JK R
*
L
*
L
Since no dc power is dissipated in the load

PCC = Pout(ac) + 2PC (14.6.12)
2
VCC 2
2PC = *
2 I cm . R L* (14.6.13)
RL
From Eqn. 14.6.13 it is clear that collector dissipation is the maximum for no signal, i.e.
Icm = 0.
2
V CC
PC(max) = *
(14.6.14)
2 RL
Power Amplifiers
$ %
2
Pout(ac) 2 I cm R L*
The conversion efficiency h = = (14.6.15)
PCC 2
VCC / R L*
The output power and hence, the efficiency will be maximum for largest swing in the collector
current. At the same time the collector dissipation will be minimum. The maximum value of collector
current from Eqn. 14.6.14 is substituted in Eqn. 14.6.15 to result in the maximum power output and
efficiency i.e.
2 2
2
VCC VCC
Pac(out)max = 2 I cm R L* = 2 = (14.6.16)
4 R L* 2 R L*
2
VCC / 2 R L* 1
h= 2
= = 50% (14.6.17)
VCC / R L* 2
Figure of Merit (F)
2
Pac out(max) VCC / 2 R L*
F= = 2
=1 (14.6.18)
PC (max) VCC / 2 R L*
PC(max) = Pac(out) max (14.6.19)
Thus, power dissipation and output ac power are of the same amount.
14.7 Class B Push-pull

The exact circuit of Class B push-pull derived from Fig. 14.9(a) is redrawn as Fig. 14.11(a). The load
line for Class B push-pull is drawn in Figs. 14.11(b). The ac representation of Class B push-pull is
shown in Fig. 14.11(c). The change in the signal currents ic1 and ic2 and the bias current from the dc
supply are indicated in Fig. 14.11(d).
The current coming out from the dc supply looks like the full-wave rectifier output where as the
individual collector currents looks like the output of half wave rectifier displaced by 180° w.r.t. the
other. Since only one transistor works at a time and both halves are identical in all respects, the circuit
of Fig. 14.11(c) can be cut from the middle to simplify its analysis. The single transistor output circuit
of Class B amplifier is shown in Fig. 14.11(d).
Figure 14.11(a) Class B push-pull stage

$ &
Figure 14.11(b) Load line of Class B push-pull power amplifier
Figure 14.11(c) Simplified circuit of Class B push-pull Figure 14.11(d) Half of Class B push-pull
The incremental model of Class B push-pull amplifier is drawn as Figs.14.11(e) and 14.11(f) with
reflected load impedance R L* .
Since transistor is biased in Class B, i.e. ICQ = 0. The voltage across its collector-emitter = VCEQ
= VCC (open circuit voltage).
Figure 14.11(e) Output circuit seen by load Figure 14.11(f) Output circuit seen by each BJT
14.7.1 Load Line

When transistor T1 is conducting (saturated), T2 becomes OFF.
Hence VCE1 = 0, ICQ2 = 0 (14.7.1)
2
VCC
Ic(max) = Icm = (14.7.2)
R L*
Power Amplifiers
$ '
The secondary winding voltage vL induces a voltage in the primary winding across transistor
T2 = nv1.
VCE2 = VCC + nvL (14.7.3)
VCC
vL(max) = R l* = VCC (14.7.4)
R L*
Now, the voltage across transistor T2 is
VCE2 = VCC + VCC = 2VCC (14.7.5)
ic2 = 0 (14.7.6)
The load line of Class B push-pull looks like the one shown in Fig. 14.11(b). The wave shapes of
Class B push-pull are shown in Figure 14.12. Hence, each transistor works for one half-cycle, the shape
of ic1 and ic2 looks like the output of the half wave rectifier and the current drained from the dc supply
looks like the output of a full wave rectifier as depicted in Fig. 14.12. There is no forward bias provided
externally across the base-emitter junction in perfect Class B push-pull operation, the equivalent amount
of signal is consumed bringing the transistor from cut-off to conduction region. This leads to a dead
space in transferring the conduction from one transistor to the other. This introduces distortion called
crossover distortion to be discussed in subsequent article.
14.7.2 Power Calculations
Power supplied by dc supply = PCC = VCCICQ = VCCIav (14.7.7)

The dc voltage remains constant = VCC (14.7.8)
The average or dc value of the current waveform is shown in Fig. 14.12 is obtained after integrating
the current drained out from the dc supply that looks like the waveform a full-wave rectifier over the full
period, i.e.
π 2π
1 1
IDC = Iav =
2π z
0
I cm cosω td (ω t ) +
2π z
π
I cm cos ω td (ω t )
p p p
1 1 2I
= Ú I cm cos w td (w t ) + Ú I cm cos w td (w t ) = cm Ú cos wtd (w t ) (14.7.9)
2p 0 2p 0 2p 0
p
I cm I 2 I cm
cos w td (wt ) = cm [ - cos w t ]0 =
p
= Ú (14.7.10)
p 0 p p
PCC = VCC
FG 2 I IJ
cm
(14.7.11)
H p K
2
I cm
Power transferred to the load = Pout(ac) = i c2 (rms) R L* = R L* (14.7.12)
2
$!
Power dissipated in transistors 2 Pc = PCC Pout(ac)

2
2 V CC . I cm I cm
2 Pc = . R L* (14.7.13)
p 2
The maximum dissipation can be obtained by differentiating Eqn. 14.7.13 and equating it to 0, i.e.
Figure 14.12 Output wave form of Class B push-pull amplifier
∆ ( 2 PC ) 2 VCC 2 I cm .RL*
= =0 (14.7.14)
∆ I cm p p
2 VCC
Icm = *
(14.7.15)
p . RL
Substituting this value of Icm from Eqn. 14.7.15 in Eqn. 14.7.13 yields the maximum collector dissipation.
2 2
2 VCC 2 VCC 4 VCC 2 VCC
2 Pc(max) = ¥ - = (14.7.16)
p pR L* 2 p 2 R L* p 2 RL*
Power Amplifiers
$!
Hence, maximum dissipation across each transistor PC(max)

2
0 .1 VCC
Pc(max) @ (14.7.17)
R L*
pac out(max) 2
I cm RL* / 2 pI cm R L*
The conversion efficiency h = = = (14.7.18)
PCC VCC 2 I m / π 4 VCC
2
VCC
Since Icm = (14.7.19)
R L*
( p / 4 )( VCC / R L* ) R L* p
h= = = 0.785 = 78.5% (14.7.20)
VCC 4
Figure of Merit (F)

The figure of merit is defined as the ratio of power dissipated in the transistor to the power developed
across the load and is expressed as
2
PC (max) 0 .1 VCC / R L*
F= = 2
= 0.2 (14.7.21)
Pacout (max) I cm R L* / 2
Pc(max) @ 0.2 Pout(ac)max (14.7.22)
In order to avoid crossover distortion, the circuit of Fig. 14.11(a) is provided a small forward bias
equal to the drop across the base-emitter junction VBE. This configuration is called Class AB and works
as Class B push-pull configuration.
Advantages of Class B over Class A

∑ Delivers more output power
∑ Results in higher efficiency
∑ Dissipates negligible power in no signal condition.
Disadvantages of Class B w.r.t. Class A

∑ Results in more distortion as only one half cycle is present in its output,
∑ It results in another type of distortion known as crossover distortion also.
14.8 Complementary Symmetry Output Stage

The simplest circuit of Class A push-pull complemenary amplifier configuration shown in Fig. 14.13(a).
It consists of matched pairs of complementary transistor n-p-n and p-n-p in such a manner that one of
them conducts at a time. Unless the input voltage vI becomes more than VBE (= 0.6 V) none of the
transistors conducts. When vI > 0.6 V, transistor T1 conducts and operates as an emitter follower. In
such case vo = vI VBE1 and T1 supplies the load current. In this duration the emitter-base junction of
transistor T2 remains reverse biased by vI and does not conduct.
$!
Figure 14.13(a) Class A push-pull stage with crossover distortion
Figure 14.13(b) Transfer characteristic of Class B output stage
When the input voltage becomes more negative than 0.6 V, i.e. VI £ 0.6 V, transistor T2 starts
conducting and T1 becomes off. Then, vo follows vI, i.e.
Vo = vI + VBE1 (14.8.1)
In this case transistor T2 supplies the load current. Thus, once vI ≥ 0.6V, transistor T1 supplies
(pushes) current to the load and T2 sinks (pulls) current from the load. Hence, the circuit of
Fig. 14.13(a) works in the push-pull fashion.
VCC VCE1(sat) = vo = vI + VBE1
vo = vI + VEB2(sat) = vI VBE2(sat) = VCC + VEC2(sat) = VCC VCE2(sat)
vI = VCC VCE2(sat) + VBE2(sat)
The transfer curve of Class B push-pull configuration is drawn as Fig. 14.13(b). The dead space
between 0.6 V to +0.6 V results in the crossover distortion as demonstrated in Fig. 14.13(a).
Power Amplifiers
$!!
h)
14.8.1 Power Conversion Efficiency (h
Let us write the output power developed across the load, Pout(ac), in terms of the peak value of the output
voltage vo = vo(max) that result as
v o2 (rms) v o2 (max)
Pout(ac) = = (14.8.2)
RL 2 RL
The current drawn from each dc power supplies VCC and +VCC looks like the output of a half-wave
rectifier with its peak amplitude IDC that yields as
v
IDC = o (max) (14.8.3)
πR L
Hence, dc power supplied by the two power supplies is
v o (max)
PCC(+) = PCC() = ICVCC = VCC (14.8.4)
pR L
Thus, the total dc power supplied by both dc power supplies is
2 v o (max)
= PCC(+) + PCC() = 2 PCC = 2 ICVCC = VCC (14.8.5)
pR L
Combining Eqns. 14.8.2 and 14.8.5 yields the conversion efficiency as
v o2 (m ax) / 2 R L FG π IJ vo(max)
h= = (14.8.6)
2 v o (m ax)V C C / π R L H 4K V CC
The efficiency could be maximum when VO(max) = VCC VCE(sat) @ VCC.
p
Hence, hmax = = 78.5% (14.8.7)
4
2
Vo (max) 2
Pout(ac) max = = VCC (14.8.8)
2 RL 2 RL
14.8.2 Power Dissipation Across the Transistor

The power dissipated for no signal, i.e. vI = 0. The average power dissipated in presence of signal is
expressed as
PC = PCC Pout(ac) (14.8.9)
2 vo(max)VCC vo2(max)
PC = - (14.8.10)
p RL 2 RL
$!"
Differentiating Eqn. 14.8.10 w.r.t. vo(max) and equating it to zero yields the condition of maximum
dissipation across the transistor.
∆PC 2 VCC 2 vo(max)
= - =0 (14.8.11)
∆vo(max) p RL 2 RL
2 VCC
vo(max) = (14.8.12)
p
Substituting the value of vo(max) from Eqn. 14.8.12 in Eqn. 14.8.10 results in the dissipation across
each of the transistors as
2 2 2 2
4 VCC 4 VCC 4 VCC 2 VCC
PC(max) = = = 2 (14.8.13)
p 2 RL 2 p 2 RL 2 p 2 RL p RL
For maximum power dissipation across each transistor, the power conversion efficiency is calculated
by substituting Eqn. 14.8.12 in Eqn. 14.8.6.
Hence, h=
FG v IJ F p I = FG 2 V IJ F p I = 1 = 50%
o (max) CC
(14.8.14)
H V K H 4 K H pV K H 4 K 2
CC CC
Plot of its efficiency is shown in Fig. 14.14.
Figure 14.14 PC versus vo(max)
From Fig. 14.14 it is clear that the power dissipation starts decreasing for increasing value of vo(max)
2
beyond VCC/p . As Pout(ac) is proportional vo(max) / 2 RL to vo(max), it increases with increasing value of vo.
It is important to note that the frequency of power dissipation across the transistor is four times the
signal frequency.
14.8.3 Reduction of Crossover Distortion

The crossover distortion inherent in perfect Class B push-pull complementary operation can be minimized
using negative feedback technique as demonstrated by Fig. 14.15. The dead space of ± VBE (@ 0.7 V)
reduces to ± 0.7 V/Ao using circuit of Fig. 14.15, where Ao is the dc gain of the Op. amplifier. Nevertheless
the slew-rate limitation at high frequency will limit the turning ON and OFF of output transistors. The
crossover distortion reduction is achieved in a better manner in Class AB operation.
Power Amplifiers
$!#
v0 = (v1 v0) A0 VBE1

v0 V BE1
+ v0 = v1
A0 A0
v0 = v1 (as A0 @ •)
Figure 14.15 Reduction of crossover distortion
14.9 Class AB Push-pull Stage

An externally small amount of non-zero bias current provided as shown in Fig. 14.16(a) can virtually
eliminate the crossover distortion. Here, VBB/2 appears across each base-emitter junction of transistors
T1 and T2, which virtually cancels the inherent drop across the base-emitter junction.
Figure 14.16(a) Class AB push-pull Figure 14.16(b) Ideal transfer curve of Class AB
For vI = 0, vo = 0 (14.9.1)
Assuming matched pair, the small but non-zero bias currents are
V BE
2 VT
ie1 = ie2 = ICQ = I o e (14.9.2)
The value of VBB is selected as per the requirement of the quiescent current ICQ.
14.9.1 Operation
For positive half-cycle input
$!$
VBB
vo = v I +
− VBE1 (14.9.3)
2
This voltage forces the load current i1 to flow through RL as indicated in Fig. 14.16 (a). Hence, increasing
value of vI, ie1 must also increase as
ie1 = ie2 + i1 (14.9.4)
The increase in ie1 is coupled with the corresponding increase in the VBE1. Since VBE1 + VBE2
= VBB, increase in VBE1 must decrease VBE2 as VBB is constant. Thus, with increasing value of ie1, ie2
starts decreasing.
VBE1 + VBE2 = VBB (14.9.5)
V BB
2V
As ie1 = ie2 = ICQ = I o e T (14.9.6)
V BB ie 1 ie 2
= VT ln = VT ln (14.9.7)
2 Io Io
I CQ
Also VBB = 2 VT ln (14.9.8)
Io
ie 1 ie 2 ICQ
VT ln + VT ln = 2 VT ln (14.9.9)
Io Io Io
2
Also ie1ie2 = I CQ (14.9.10)
I CQ
ie1 = + i1 (14.9.11)
ie 2
or, i e21 - i e 1 i e 2 - I CQ
2
=0 (14.9.12)
The above equations indicate that the transistor T1 supplies the load current acting as the emitter
follower for positive half-cycle of the input voltage. In the mean time transistor T2 conducts current that
decreases with increasing value of vo since it works as the reverse bias for its emitter-base junction and
for large value of vo the current through T2 can be ignored.
Transistor T2 also supplies the load current acting as the emitter follower for negative half-cycle of
the input voltage. In the mean time the conduction of current through T1 decreases with increasing
negative value of vo since it works as reverse bias to its emitter-base junction. Transistor T1 virtually
does not conduct in such case for large value of vo. Hence, the transfer curve of Class AB push-pull
configuration reduces to Fig. 14.16(b).
14.9.2 Output Resistance

The output resistance of Class AB stage can be obtained from Fig. 14.17(a). This figure has been
reduced from Fig. 14.16(a) with the assumption that all voltage sources are ideal.
Power Amplifiers
$!%
Ro = re1| |re2 (14.9.13)

Where re1 and re2 are small signal emitter-base resistances of T1 and T2.
V
As ie1 = ie2 = ICQ = I o e VT (14.9.14)

where V = external forward bias applied across each emitter-base junction.
V
Di e 1 FI I
o
= G J .e VT
=
ie 1
(14.9.15)
DV HV K
T VT
Figure 14.17(a) Class B push-pull Figure 14.17(b) Class B push-pull biasing with diode
DV VT
re1 = = (14.9.16)
Di e 1 ie1
DV VT
Similarly re2 = = (14.9.17)
Die2 ie 2
Ro = re1| |re2 =
bV /i g bV /i g =
T e1 T e2 VT
(14.9.18)
bi + i g v b i
e1 e2 T e1 + ie 2 g
bi g bi g
e1 e2
It was discussed previously that as ie1 increases ie2 decreases and vice-versa and the output resistance
remains constant in the region vI @ 0. This indicates absence of the crossover distortion. For large load
current, either ie1 or ie2 will become insignificant and Ro starts decreasing with increasing load current.
14.10 Biasing of Class AB Circuit

The integrated circuit approach of realizing the output stage as Class AB suggests that the two external
bias voltage VBB/2 have to be generated internally rather than connecting the two equivalent batteries.
14.10.1 Biasing Using Diodes

The generation of VBB internally in the integrated circuit approach is done by passing a constant current
IBias through two diodes as illustrated in Fig. 14.18. Normally in integrated circuits diodes are realized in
the form of transistors only with different ratings of power handling capabilities as per the need. Similarly
$!&
here diodes are not required to be of the same power handling capabilities but different than that of
transistors T1 and T2. Hence, the quiescent current ICQ in T1 and T2 will be = nIBias, where n is the ratio
of the emitter junction area of the output devices to the junction area of the biasing diodes. In other
words, the saturation current Io of the output transistors is n times that of the biasing diodes. Area rating
is very simple to implement in the integrated circuit but very difficult to realize in the discrete circuit
design.
The base current of T1 must at least be = ICQ/b @ IL/b when the Class AB stage shown in Fig. 14.18
is supplying (sourcing) current to the load resistance RL. It necessitates that IBias must be greater than
the maximum anticipated base drive for T1. This condition sets a lower limit on the value of the IBias.
Since ICQ = nIBias and also ICQ is much smaller than the peak load current (less than 10%), it is observed
that n cannot be made very large. In other words the area of diodes cannot be made very smaller than
that of the transistors.
Figure 14.18 VBE multiplier without and with precision adjustment
14.10.2 Biasing Using VBE Multiplier

It was discussed in the previous example that generation of VBE using diode as shown in Fig. 14.17(b)
is suitable in the case of integrated circuit. Sometimes even discrete circuit design becomes inevitable.
Hence, a more versatile circuit arrangement as illustrated in Fig. 14.18 is called VBE multiplier type of
biasing is used. This circuit arrangement works well for both integrated and discrete circuits. The VBE
multiplier is realized using transistor T3 with feedback resistance R1 connected between its collector and
the base. Hence, resulting two terminal device is supplied with a constant current source IBias. If
IB3 = 0, then I R1 = I R 2 .
V BE 3
I R1 = I R 2 = I R = (14.10.1)
R2
Hence, VBB = (R1 + R2)IR =

V BE 3 FG R
R2 1 + 1
IJ = V FG1 + R IJ
BE 3
1
(14.10.2)
R2 H R2 K H RK 2
From Eqn. 14.10.2 it is clear that the voltage VBE is multiplied by the factor (1 + R1/R2) and hence,
given the name VBE multiplier. The VBE multiplier is used to control the quiescent current ICQ. In
Power Amplifiers
$!'
integrated circuit design it is easy to control the ratio of two resistances R1 and R2 whereas in the case
of discrete circuit design a potentiometer as depicted in Fig. 14.18 may have to be used to control ICQ
accurately.
The value of VBE1 is determined by the portion of IBias flowing as collector current of T3.
So,
IC3 = IBias IR (14.10.3)
VBE = VT ln
FG I IJ
C3
(14.10.4)
HI Ko3
14.11 Power Transistors

The transistors required to handle currents in the range of ampere and withstand power dissipation of
watts and tens of watts differ very much in their physical structure, packaging, etc. The transistors that
handle such large amount of currents and power dissipation are called power transistors. The power
transistors, thus, dissipate large amount of power across collector-base junction. Nevertheless the
junction temperature Tj must not be allowed to exceed the specified maximum Tj(max), otherwise the
transistor junction may be permanently damaged. The usual range for silicon transistors are 150° to
1500°C.
14.11.1 Thermal Resistance

If a transistor is operating in the open air, the heat dissipated in the transistor junction will conduct away
from the
∑ junction to the transistor case
∑ from transistor case to air.
The dissipated power raises the junction temperature w.r.t. to air can be expressed as
Tj TA = PCqjA (14.11.1)
where qjA = thermal resistance between junction and ambient having the unit of °C/W.
Eqnuation 14.11.1 indicates the amount of increase in the temperature over ambient per watt dissipated
power. Thus, smaller the value of thermal resistance, lesser increase in the temperature over ambient
will take place. Thus, in free air qjA depends on primarily on the type of packaging. The transistor data
sheet specifies the value of qjA. Equation 14.11.1 is similar to Ohms law. In this analogy,
∑ Power dissipated ¤ Current
∑ Temperature difference ¤ Voltage difference
∑ Thermal resistance ¤ Electrical resistance
Thus, the thermal conduction process may be represented by electrical circuit as shown in
Fig. 14.19(a).
$"
14.11.2 Derating Curve

The variation in maximum collector dissipation with the case temperature is an important characteristic
supplied by the transistors manufacturers. A typical curve is shown in Fig. 14.19(b). From this figure
it is clear that the transistor can dissipate safely the rated maximum PC(max) below the temperature TAO.
However, the maximum allowable power dissipation decreases with increasing value of temperature
higher than that of TAO as indicated in Fig. 14.19(b). This phenomena is called derating of power curve.
The slope of the derating curve is written as
T j (max) - T AO T j (max) - T AO
Slope = qjA = = - (14.11.2)
0 - PC (max) PC (max)
The power dissipation at any ambient temperature TA can be obtained from Eqn. 14.11.2 as
T j (max) - T A
PC(max) = (14.11.3)
q jA
For Tj(max) = TA, no power can be dissipated as no heat can be removed from the junction.
Figure 14.19(a) Thermal conduction Figure 14.19(b) Derating curve
14.11.3 Transistor Case With Heat Sink

A typical common physical connection of transistor with heat sink is shown in Fig. 14.20(a). Now the
heat dissipation is not directly from junction to ambient environment but through the heat sink.
qjA = qjC + qCA (14.11.4)
where qjC is the thermal resistance between junction and the case and qCA is the thermal resistance
between case and ambient.
While the circuit designer has no control over qjC he can control qCA. A popular approach to dissipate
heat from case to ambient is through the heat sink. The heat is easily conducted from the case to the
ambient via the heat sink. Hence, thermal resistance qCA is broken into two parts as
qCA = qCS + qSA (14.11.5)
Power Amplifiers
$"
Figure 14.20(a) Transistor with heat sink Figure 14.20(b) Electrical circuit of heat sink
Now, Fig. 14.19(a) is modified including the heat sink as Fig. 14.20(b).
Thus Tj TA = PC (qjC + qCA + qCS + qSA) (14.11.6)
1. Both the transistors, T1 and T2, of a Class ib2 = ii = 0 0 < wt < p

B push-pull amplifier shown in = ii = cos(w 0t + p) p < wt < 2p
Fig. 14.21(a) work in the non-linear range
described by its collector currents as iL = n(ic1 + ic2) 0 < wt < p
ic1 = 10 ib1 + i b2 1 and ic2 = 10 i b 2 + i b2 2 n
= n 10 ( i b 1 - i b 2 ) + ( i b21 - i b2 2 ) s
with i1 = 10 nii + ni2i. Obtain the load
current iL. Plot iL showing the non- = 10 n(ib1 0) + n ( i b21 - 0 )
linearity in it.
= 10 ni i + ni i2 0 < wt < p
Solution:
= 10 n ( 0 - i b 2 ) + n ( 0 - i b2 2 )
From Fig 14.21(a),
= 10 n { 0 - ( - i i )} + n ( 0 - ( - i i ) 2
ib1 = ii = cos w0t 0 < wt < p
=0 p < wt < 2p = 10 ni i - ni i2 p < wt < 2p
Figure 14.21(a) Class B push-pull power amplifier

$"
Figure 14.21(b) Plot of iL
Hence, the load current can be expressed as and T2 operating in a Class A push-pull
2 amplifier shown in Fig. 14.22 have non-linear
iL = n{10 ii + i sgn (ii )}
i
collector currents expressed as
= n{10 cos ω o t + cos 2 ω o tsgn (cos ω o t )}
ic1 = 10 i b 1 + i b21 and ic2 = 10 i b 2 + i b2 2 .
RS 1
b
= n 10 cos ω o t + 1 + cos 2ω o t sgn cos ω o t g b gUVW Solution:
T 2
It is well known that in Class A
2. Obtain iL if IBQ1 = IBQ2 = 1A and ii = coswot
for the condition that both transistors T1 for ii > 0, iB1 =IBQ1 + ib1 = IB + ii
for ii < 0, iB2 =IBQ2 + ib2 = IB ii
Figure 14.22 Class A push-pull power amplifier
Hence, for IBQ1 = IBQ2 = IB = 1A, ii l

= n 20 i i + 4 I B i i q
= cos wot, and iL is expressed as
iL = n(ic1 ic2) = n l 20 cos w ot + 4 * 1 * cos w o t q
RS10( I + i ) + ( I + i ) UV 2 = 24 n cosw o t
B i B i
=n 2
T- 10(I - i ) - ( I - i ) W
B i B i
Power Amplifiers
$"!
Hence, it is evident from the last equation 2

VCC 20
that iL is linear. This shows that Class A PC = VCC ICQ = = 20 ¥ =4W
R*L 100
push-pull amplifier does not result in non-
linearity. h = 2/4 = 1/2 = 50%
3. Estimate the ratings of single ended Class 2
A power amplifier shown in Fig. 14.23(a). VCC 400
PC(max) = = = 4 W,
Neglect the loss in RE and also in the bias R L* 100
resistors R1 and R2.
PC (max) 4
F= = = 2.
PL (max) 2
VCC 20
iC(max) = = = 0.2 A and
R L* 100
VC(max) = 20 V.
The signal swing is shown in Fig. 14.23(b).
4. In Fig. 14.23(a), the maximum power de-
veloped across the load is 2 W for the in-
put signal ii = Iimsinwot. Obtain PL(max) for
Figure 14.23(a) Class A single ended power the signal expressed as
amplifier I im I im
ii = sin w o t + sin 3 w o t .
2 2
Solution:
LM R I U + R I U OP R
2
im
2
PL(max) =
MN ST 2 2 VW ST 2 2 VW PQ
im
L
2
I im
= RL
4
2
Figure 14.23(b) Current swing
=
RS UV R
1 Iim
L =
1 2
PL (max) = = 1 W
Solution: 2 2 T W 2 2
R L* = n2RL = 42 ¥ 6.25 = 100 W, 5. If the efficiency of the transformer in

Fig. 14.24 is 75% only, estimate iC(max),
2
VCC 400 vCE(max), PC(max), PCC, ICQ, n and PL(max) =
PL(max) = = = 2 W, 2 W.
2 R L* 2 ¥ 100
$""
Figure 14.24 Transformer loss representation

Solution: Rt 0 . 25 1
PL (max) = =
RL 0 . 75 3
h ¥ h transformer =
PCC
PL(max) 2
FG
R L* = n2(Rt + RL) = n 2 RL 1 +
Rt IJ
PCC =
h ¥ h(transformer)
=
0.5 ¥ 0.75
H RL K
=
4
= 5.33 W
FG
= n 2 RL 1 +
1IJ
= n 2 RL
F 4 I = 75.2
0 . 75 H 3 K H 3K
PCC 5.33 W 75.2 ¥ 3
ICQ = = = 0.267 A n2 = = 9.024
VCC 20 V 4 ¥ 6.25
VCEQ n@3
20 V
The load resistance = = = 75 W 6. Determine iC(max), PL(max), and h for the
I CQ 0.267 A
following ratings of the transistor shown
in Fig. 14.25(a). Given PC(max) = 2 W,
PC max
F=2= , BVCEO = 80 V, and VCE(sat) = 1 V
PL max
PC(max) = 2 PL(max) = 5.33W = PCC
The transformer can be represented with a
loss component equivalent to a resistance
R L* as shown in Fig. 14.24.
2 2
I Lm I Lm
Ptotal = ( R t + R L ) 0 . 75 = RL
2 2
0.75Rt = RL 0.75RL = 0.25RL
Figure 14.25(a) Class A single ended power
amplifier
Power Amplifiers
$"#
PC (max)
ICQ = ,
VCEQ
PC (max)
VCEQ VCE(sat) = RL
VCEQ
2
V CE Q − V CE ( sat ) V CE Q − PC (m ax) R L = 0
2
Figure 14.25(b) Load line
VCEQ =
VCEsat
± PC max R L +
FG V IJ
CE sat
Solution:
2 H 2 K
2
Substituting PC(max) = 2 W and VCE(sat)
I CQ R L + V CE ( sat ) I CQ − PC (ma x) = 0 = 1 V results in VCEQ = 0.5 ± 4.5 = 5 V.
Hence, maximum attainable symmetrical
2
- VCE ( sat ) ± VCE ( sat ) + 4 RL PC (max) swings would be
ICQ =
2 RL ic(max) = ± 0.4 A, VCE(max) = ±4 V
2
2 I cm
=
VCE ( sat )
±
FG V IJ
CE ( sat )
+
PC (max) PL(max) = i c2( rm s ) R L =
2
RL
2 RL H 2R K L RL
0 .16
VCEQ VCE(sat) = ICQRL and PC(max) = *10 = 0.8 W
2
= VCEQICQ PCC = VCCICQ = 5*0.4 = 2 W
PC (max) PL (max) 0.8
− VCE ( sat ) = ICQRL h= = = 0.4 = 40%
I CQ PCC 2
2 The approximate value can be found out
1 Ê 1ˆ 2
ICQ = - ± Á ˜ + from the load line drawn in Fig. 14.25(b) as
20 Ë 20 ¯ 10
V CEQ − V CE ( sat ) 5-1
ICQ = = = 0.4 A
= 0.05 ± 0.025 + 0.2 RL 10
= 0.05 ± 0.474 = 0.524 A, 0.424 A 7. Obtain the value of RB, VBB, PCC, PL(max),
n and n in Fig. 14.26(a) for PC(max) =
Since ICQ in this case is symmetrical
100 W such that the maximum power can
swing. Hence,
be translated to the load.
Figure 14.26(a) Transformer coupled power amplifier Figure 14.26(b) Load line
$"$
Solution: 8. Obtain the following for the circuit of

PC(max) = 100 W = VCEQICQ = VCCICQ Fig. 14.27(a) with VCC = 15 V, I = 10 mA,
and RL = 1 K for an output voltage of 5 V
100 peak sinusoid (i) power delivered by the
ICQ = =5A
20 power supply, (ii) maximum power dissi-
The maximum voltage swing = 20 + 20 pated in T1 and (iii) efficiency.
= 40 V
20
The ac load resistance = = 4 W.
5
The dc and ac load lines are drawn as
shown in Fig. 14.26(b). The slope of ac
load line is
1 RL
= W , R L* = 2
4 n
RL 10
n= = = 1.5
R L* 4 Figure 14.27(a) Emitter follower output stage
I CQ
PCC = PC(max) = 100 W, IBQ =
b
5
= = 0.5 A, PBB = VBBIBQ
10
V BB - 0 . 7
Also IBQ = = 0.5 A
RB
V BB - 0 . 7 V BB - 0 . 7
RB = =
IB 0.5
Figure 14.27(b) Output power stage
= 2(VBB 0.7)
If a reasonable value of VBB is selected Solution:
equal to be 2V, then PS = PCC(+) + PCC() = 15*/10 + 15*10
RB = 2 * 1.3 = 2.6 W, PBB = 2 * 0.5 = 1 W = 300 mW
2
PL(max) = PC(max) =
FG IJ
I cm
RL Fv L ( p eak ) IJ 2
H 2K PL(max) = G RL
2
H 2 K
F 5. 5 IJ
=G 4 = 60.5 W Ê 5 ˆ
2
H 2K = Á
Ë 2 ˜¯
1K = 12.5 mW
PL max 60 . 5 60 . 5
h= = @ PC(T1) = VCCI = 15*10 = 150 mW
PCC + PBB 100 + 1 100 + 1
= 0.599 = 60%
Power Amplifiers
$"%
PL (max) 12.5 mW 10. Obtain the following for the complemen-

h= = tary symmetry power amplifier shown in
PCC ( + ) + PCC ( - ) 300 mW
Fig. 14.28(a), (i) power developed across
= 0.0417 = 4.2% the load, (ii) maximum power supplied by
the two dc power supplies and (iii) maxi-
9. The output stage of a power amplifier
mum power dissipated by each transistor.
shown in Fig. 14.27(b) with VCC = 15 V
Also get the plot of PL, PCC, and PC versus
and Icm = 1 K is required to deliver an out-
Icm in the range 0 < Icm < 2 A.
put voltage of 5 V peak sinusoid, deter-
The complementary symmetry power am-
mine the following neglecting crossover
plifier shown in Fig. 14.28(a) is cut
distortion; (i) power delivered by the
through the middle by dotted line and re-
power supply, (ii) maximum power dissi-
sults into an equivalent circuit containing
pated in T1, and (iii) efficiency.
one transistor as in Fig. 14.28(b).
Solution:
2 Vm
(i) PS = PCC(+) + PCC() = I cm
p
2 Vm VCC 2 * 5 15
= ¥ = ¥ = 47.75 mW
p RL p 1K
5
(ii) VCEIC = (15 − 5) = 10*5 = 50 mW
1K
2 2
ÊV ˆ Ê 5 ˆ
(iii) PL(max) = Á m ˜ RL = Á 1K
Ë 2¯ Ë 2 ˜¯
= 12.5 mW
PL (max) 12.5 mW
h= = = 0.262
Ps 47.75 mW
Figure 14.28(a) Complementary symmetry
= 26.2% power amplifier.
Figure 14.28(b) Half section

$"&
Solution: VCC
Icm =
(i) Power developed across the load 2 .2 p
2 2
=
FG I IJ
Lm
RL =
FG 2 IJ 4 = 8 mW
H 2K H 2K
(ii) Power drained from both dc supplies
= PS = PCC(+) + PCC()
=
FG 2 V IJ I
m
=
F 2 *10 I 2 = 12.73 W
H p K cm
H p K
Thus, power supplied by each dc supply
12 . 73
= = 6.365 W Figure 14.28(c) Plot of PL, PCC, PC vs Iim
2
(iii) Power dissipated across PR C (1 W) Now substituting this value of Icm in the
equation of PC results in the maximum
2 power dissipated across each transistor as
=
FG I IJ
cm
R C @ 0.1(Icm)2
HpK PC =
F 1 I FG V IJ
CC
2
1 .1
FG V IJ
CC
2
PS = PCC(+) + PCC() = 2 PCC

H 2 .2 K H p K H 2 .2 p K
2
= 2 PC + 2 PRC + PR L Ê 1 ˆ Ê VCC ˆ
= Á = 2.3 W
Ë 2 ¥ 2.2 ¯˜ ÁË p ˜¯
PR L FG V I IJ CC cm
PC = PCC - PR C - = Now substituting this value of Icm in the
2 H p K equation of PC results in the maximum
2 power dissipated across each transistor as
0.1(Icm 2
)
F 1 I FG I IJ R cm
H 2K H 2 K L
PC =
F 1 I FG V IJ
CC
2
- 1 .1
FG V IJ
CC
2
FG V I IJ 0.1(I ) H 2 .2 K H p K H 2 .2 p K
CC cm 2
= cm
H p K Ê 1 ˆ Ê VCC ˆ
= Á
2
= 2.3 W
2 Ë 2 ¥ 2.2 ¯˜ ÁË p ˜¯
F 1 I F I IJ R = FG V I IJ 1.1(I
G J G cm CC cm
cm)
2
11. Calculate VCC and maximum power that
H 2K H 2 K H p K L
can be delivered to a 10 W in Fig. 14.28(d)
Hence, the maximum power dissipated for PC(max) = 4 W, BVCEO = 40 V, iC(max)
across each transistor can be obtained af- = 1 A.
ter differentiating the equation of PC w.r.t. The symmetrical half section of the
Icm and equating it to zero as complementary symmetry type amplifier
∂PC VCC shown in Fig. 14.28(d) reduces to
= - 2 * 1 .1 I cm = 0, Fig. 14.28(e).
∂I cm p
Power Amplifiers
$"'
Figure 14.28(d) Complementary symmetry
Figure 14.28(e) Half section

Solution: amp limitation of 15 V with ICmax = 2 A ,
2VCC = 20 V << BVCEO (= 40 V) PCmax = 1 W. After mounting the transistor
on a heat sink, it sustains PCmax = 3 W.
VCC 10
Iim = = =1A Solution:
RL 10 The circuit has a current booster as the
VCC = 10 ¥ 1 = 10 V op-amp to provide very small current of
2
F I 2 the order of 25 mA. The gain of the op-
PL(max)
F
= G
I cm I
J .RL = G
VCC
JK RL amp is
H 2K H 2RL
Ê 8ˆ
2
VCC Av = Á 1 + ˜ vs = 5 vs.
100 Ë 2¯
= = =5W
2 RL 2 ¥ 10 The maximum output of the op-amp is lim-
12. The power of a phonograph pick up signal ited to ±15 V (given). For no input signal
Vm (t) is amplified by the power amplifier applied, voltage at the junction of both
shown in Fig. 14.29 to feed to an 5 W loud V
emitters is = CC . Thus, the voltage re-
speaker. What is the maximum power de- 2
livered to the 5 W loud speaker for the quired at the base of the n-p-n BJT =
maximum output voltage subject to op- VCC
+ VBE1 = 7.5 + 0.7 = 8.2 V and to the
2
$#
VCC 2Vpeak 2VCC

base of p-n-p BJT = - + VBE1 = 7.5 IDC = , PDC(max) = VCC ¥
2 pRL pRL
+ 0.7 = 6.8 V. 2
2VCC
Thus, peak swing across RL = v peak to peak =
pRL
V V
= CC - VBE1 + CC - VBE1 v i vi - vo v v v
2 2 + =0, i + i = o
In complementary configuration the tran- 2 8 2 8 8
sistor works in the saturation, VO = VCC or, 5vi = vo , vi = vo / 5
VCE(SAT) = VCC. Hence, the output power
developed across the load is vo v v V V V
+ o - i = 2, o + o - o = 2 ,
2 5 8K 8K 5 8K 40K
Pac
FV
=G
peak - peak IJ 1 V2
= CC =
225
or, vo = 10 V
H 2 2 K RL 8 RL 8¥5
= 5.625 W vo2 100
PL (max) = = = 10 W
2 R 10
Figure 14.29
Questions for Practice Multiple Choice Questions

1. Explain the classification of amplifier on 1. The output power in a power amplifier is
the basis of operating point. (a) proportional to the ac input power
2. Draw the circuit of a Class C amplifier us- (b) converted from the dc power supply
ing transistor and explain its operation. (c) due to feedback
3. Explain the meaning of impedance match- 2. A practical power amplifier has cascaded
ing. How is it achieved? stages of
4. Draw the transistor push-pull power am- (a) voltage amplifiers, a driver stage and a
plifier circuit and explain its operation. power stage
(b) current amplifier, a driver stage and a
power stage
(c) power amplifiers, a driver stage and a
power stage
Power Amplifiers
$#
3. The power conversion efficiency of a di- (a) 55% (b) 50%

rectly fed resistive load in Class A ampli- (c) 78.5% (d) 100%
fier is 12. The efficiency of a Class A push pull am-
(a) 55% (b) 78.5% plifier is
(c) 50% (a) less than Class B push-pull
4. In ClassA amplifier, the distortion is (b) more than Class B push-pull
(a) maximum (b) minimum (c) equal to Class B push-pull
(c) medium 13. The efficiency of Class AB and Class B
5. The power conversion efficiency of Class push-pull amplifiers are
AB amplifier is (a) equal (b) not equal
(a) 55% (b) 78.5% (c) none of these
(c) 50% 14. The primary function of the transformer is
6. The power conversion efficiency of Class to
C amplifier is more than (a) step up the voltage
(a) 55% (b) 78.5% (b) step up the current
(c) 50% (c) match the load impedance to the out-
7. The crossover distortion takes place in put impedance of the amplifier
(a) Class A amplifier 15. The complementary symmetry power am-
(b) Class B amplifier plifier uses
(c) Class AB amplifier (a) two p-n-p transistors
8. Introduction of an inductor in place of RC (b) two n-p-n transistors
in Class A power amplifier (c) one p-n-p and the other n-p-n transis-
(a) increases its efficiency tors
(b) decreases its efficiency (d) one BJT and the other UJT
(c) does not effect its efficiency 16. The power amplifiers are called
9. The maximum theoretical efficiency of a (a) small signal amplifiers
Class A single ended transformer coupled (b) large signal amplifiers
amplifier is (c) magnitude amplifiers
(a) 15% (b) 55% 17. Which power amplifier has the maximum
(c) 50% (d) 78.5% distortion?
10. The efficiency of a Class A power ampli- (a) Class A (b) Class B
fier with inductor in place of RC and trans- (c) Class C
former coupled single ended amplifier are 18. The push-pull amplifier is free from
(a) equal (b) not equal (a) noise
(c) none of these (b) second harmonic distortion
11. The maximum theoretical efficiency of a (c) saturation
Class A push-pull amplifier is
1. (b) 2. (a) 3. (a) 4. (b) 5. (b) 6. (b)
7. (b) 8. (a) 9. (c) 10. (a) 11. (b) 12. (a)
13. (a) 14. (c) 15. (c) 16. (b) 17. (c) 18. (b)
15
Operational Amplifier
15.1 Introduction
The name operational amplifier has been derived from the fact that it was originally developed for
performing mathematical operations such as additions, subtractions, multiplication, division, integration,
differentiation, etc. of electrical signals. Though the number and types of stages of commercially available
operational amplifiers vary widely from one configuration to the other, a general configuration is
demonstrated in Fig. 15.1 that has three stages cascaded together. It is usually referred to as operational
amplifier (op-amp).
Figure 15.1 Block diagram of operational amplifier

The input stage has usually two differential stages to provide very high input impedance and high gain
to differential mode signals. In other words, it must have very high value of Common Mode Rejection
Ratio (CMRR). It should be able to reject the common mode signals as well. As a dc (direct coupled)
$#!
amplifier does not have any coupling or by pass capacitor, it works well from very low frequency
(theoretically from zero frequency) to very high frequency. However, it suffers from the major disad-
vantage of drift. The drift is a phenomenon that shifts the operating point and hence, the output also
changes due to changes in ICO, VBE, b with the rise in temperature and other similar effects. It can be
taken care of using balanced differential amplifier as drawn in Fig. 15.2(a). Its detailed analysis will be
taken up separately.
15.1.1 Level Shifter

We have seen that the op-amp is a cascaded version of dc amplifier. As dc amplifiers do not have any
coupling capacitor, the voltage levels from the output of one stage to the input of the following stage
cannot be connected directly or otherwise the bias conditions will be disturbed. Hence, a voltage shifter
is required between the output of one stage to the input of the other stage. It is desirable to have
quiescent output of the final stage of the differential amplifier at 0 V, i.e. for vid = 0 V, v0 = 0 V.
Example
The dc voltage at the collector point of a CE amplifier is much higher than the voltage at the base of the
following stage. Hence, connecting collector point of one stage to the base point of the other stage
requires a voltage shifter. In other situation, the dc output voltage must be adjusted by the voltage shifter
to zero volts for no input signal. The practical example of the simplest type of level shifter is an emitter
follower. The simple circuits of level shifters are shown in Fig. 15.2(b).
Figure 15.2(a) Discrete differential amplifier
Figure 15.2(b) Level shifters

$#"
From Fig. 15.2(b), V1 = VI 0.7 V (15.1.1)

Figure 15.2(b) shows another voltage level shifter circuit using resistors R1 and R2 in the emitter leg.
The main disadvantage of this method is that the signal suffers from attenuation as R2/(R1 + R2). The
attenuation of signal can be avoided using a constant current source Io as demonstrated in Fig. 15.2(b).
V2 = VI VBE R1Io (15.1.2)
Figure 15.2(b) replaces resistor R1 by an Avalanche diode.
Vo = VI VBE VZ (15.1.3)
A number of forward biased diodes may be used in place of single Zener diode. We know that the
dynamic resistance of a Zener or p-n diode is very low w.r.t. R2, the attenuation of even small signal is
well taken care.
In addition to dc level shifting, the signal requirement to the input of the output stage is very large.
Hence, the small signal input of the output stage is amplified through number of stages in order to avoid
saturation in any one stage of the voltage amplifier.
15.1.2 Output Stage

The aim in designing of the output stage lies in supplying sufficient amount of current to the load at its
very low output impedance. The simplest example of such output stage is a complementary emitter
follower shown in Fig. 15.3.
Figure 15.3 Output stage and common mode and difference mode signals
We know that the output stage of an op-amp must provide large swings in both the output current
and output voltage. The ideal peak to peak voltage swing could be set as much as +VCC to VEE. The
transistor T1 conducts in the positive half-cycle of the input signals and supplies current to the load
resistance RL whereas transistor T2 supplies current in the negative half-cycle. Thus, the current flow
through the load resistance RL is for both half-cycles.
15.1.3 Differential Amplifier (DC Analysis)

We have already analyzed differential amplifiers in Chapter 10 in detail. Here, we shall first discuss its dc
analysis. The circuit for dc analysis will remain the same for both common mode and difference mode
cases, as no signal is required for dc analysis. The ac signals (for both common and differential mode
signals) are shorted to ground as shown in Fig. 15.4 for dc analysis. For dc analysis only one half circuit
of Fig. 15.4 will be sufficient.
$##
Hence, writing the input loop equation of Fig. 15.4 as

I CQ
VEE = 2REIE + VBE + rs (15.1.4)
b
Figure 15.4 Differential amplifier for dc analysis
Figure 15.5 Common mode and difference mode differential amplifier circuits
ICQ @ IEQ and IEQ1 = IEQ2 = IEQ (15.1.5)
VEE - VBE V - VBE r

ICQ = @ EE as 2RE >> s
r 2 RE b
2 RE + s
b
Similarly, writing the loop equation in the output loop of Fig. 15.5.
VEE + VCC = VCEQ + RCICQ + 2REIEQ (15.1.6)
VEE - VBE
Since ICQ =
2 RE
2REICQ = VEE VBE (15.1.7)
$#$

VCEQ = VEE + VCC RCICQ 2REIEQ = VEE + VCC RCICQ VEE + VBE
= VCC RCICQ + VBE (15.1.8)
Example
For VEE = VCC = 10V, rs = 20W, RE = 1K, RC = 200W, and b = 100, obtain the quiescent values.
10 - 0.7 10 - 0.7 9.3
From Eqn. 15.1.6 ICQ = =
rs 20 @ 2 K = 4.65 mA
2 ¥ 1K + 2 ¥1K +
b 100
VCEQ = 10 + VBE RCICQ = 10 + 0.7 (2 K + 0.2 K) 4.65 mA
@ 10.7 0.93 = 9.77 V
The ac analysis of the differential amplifier has already been done in Chapter 11. However, the long-
tail differential amplifier shown in Fig. 15.6 incorporating a current source using transistor T3 is taken
up here. The input resistance is very important parameter of the differential amplifier. It determines the
input current for a given input signal. Hence, its resistances in both common and differential modes
have been derived in Chapter 11. It was shown in this article that CMRR increases proportionately to
increasing value of the RE. This increase in the value of RE becomes counter productive w.r.t. the dc
power supply. For an example, if RE is selected to be 1 MW for the emitter dc current of 5 mA, the
amount of voltage drop across RE = 1 M ¥ 5 mA = 5 KV.
Figure 15.6 Differential amplifier with long tail
The regulated dc supply of such a value that will allow a drop of 5 KV across the emitter resistance,
is hard to achieve. Such a situation can be created by providing two separate paths, one for ac and the
other for dc. The selection of RE should be such that for dc current it should offer very low resistance
and at the same time for ac signal it should offer very large resistance. The dual role of RE for ac and dc
can be attained with the help of a constant current source.
$#%
The third transistor T3 working as a current source supplies constant current IE3 to the emitter
currents of T1 and T2. The impedance seen from the collector lead of T3 is approximately 1/hoe3. Thus,
basically T3 offers very large ac resistance to the emitter leads of T1 and T2. The quiescent emitter
current in Fig. 15.6 can be approximated as
IE1 + IE2 = IC3 @ IE3, IE1 = IE2,
VEE VBB VBE3 = REIE3
VEE - VBB - VBE 3

IE3 =
RE
IE3 V - VBB - VBE 3
IE1 = IE2 = = EE
2 2 RE
I CQ1
VCC = RCICQ1 + VCEQ1 VBE1 rs
h fe
VCEQ1 = VCEQ2 = VCC + 0.7 RC

F rs I
ICQ
GH h fe JK
The important difference between the two transistor amplifier circuit of Fig. 15.4 and the three
transistor amplifier shown in Fig. 15.6 lies in the value of RE. This figure has ac value of RE @ 1/hoe that
is very large resistance, of the order of megohms whereas in Fig. 15.5 the value of RE cannot be set
more than few Kohms, typically few hundreds of ohms.
The common mode and difference mode gains of the difference amplifier has been derived and
discussed in Chapter 10. These gains and CMRR are expressed once again as
vo1 - h fe RC - h fe RC g R
Ad = = = =- m C
vd 2(rs + hie ) 2hie 2
v - h fe RC
Ac = o1 =
vc rs + hie + 2(1 + h fe ) RE
Ad 1 h fe + 1 RE
e jh fe RE d
h fe RC 2 RE A 2R i
CMRR = = + @ = = d E
Ac 2 rs + hie rs + hie 2 rs + hie RC bRC g
It is evident from these equations that with increasing value of RC, both differential and common
mode gain increases but CMRR decreases which is an undesirable effect. The other method of increasing
the gain is by cascading a large number of similar stages of amplifiers. The large cascading introduces
counter-productive phase shift that may cause oscillation in amplifier. Increasing value of RC produces
corresponding dc drop across RC. However, this resistance sets a limit on dc supply voltage due to high
drop across RC, and fabrication of large value of RC requires large chip area.
$#&
We can conclude that we have to select a device in place of the collector resistance that should
provide low value of dc resistance and at the same time very high value of ac resistance. Such a device
is a current source or current mirror. The dc resistance of a current source is very low, of the range of
KW through which dc current of the order of mA flows. This introduces a drop of fraction of the dc
supply voltage. On the other hand, its dynamic resistance is very high, resulting into very large voltage
gain.
15.1.4 Active Load

Transistors T3 and T4 form current mirror that is working as the active load to transistor T2 in Fig. 15.7.
I EQ
When v 1 = v2 = 0, IC1 = IC2 =
2
I L = IC4 IC2 = 0
Increasing value of v1 w.r.t. v2 forces corresponding increase in the value of IC1 and decrease in the
value of IC2 such that IC1 + IC2 = IEQ.
For I L = IC4 IC2 and IC1 = IC2 (always),
I L = IC4 IC2 = gmv1 gm v2 = gm(v1 v2)
or I L = gmvd
Figure 15.7 Differential amplifier with active load
Examples
1. The Darlington differential amplifier configuration shown in Fig. 15.8 has been used as a self
contained integrated circuit. Determine the quiescent operating conditions and the maximum
possible voltage output swing available from it. Assume hfe = 100 for all transistors.
$#'
Figure 15.8 Differential amplifier with Darlington connection
Solution
The transistor T5 works as a current-source whereas other transistors works as differential
amplifier.
- 6*2.9
VB5 = = 4.14 V, VE5 = 4.14 V 0.7 V = 4.84 V
13
. + 2.9
6 - 4.84 I 0.9
IE5 = = 0.89 mA @ 0.9 mA, E5 = = 0.45 mA = IE1 = IE2
1.3 K 2 2
I E1 0.45
IE3 = IE4 = IB1 = IB2 = = = 4.5 mA
h fe 100
VC1 = VCC RC(ICQ1 + ICQ3) = 12 10 K(0.45 + 0.0045) mA = 12 4.5 = 7.5 V
Ê 4.5 mA ˆ
VE3 = rsIB3 VBE3 = 0.01 K Á 0.7 = 0.00045 0.7 = 0.7 V
Ë 100 ˜¯
VE1 = 0.7 0.7 = 1.4 V
VCEQ5 = VE1 VE5 = 1.4 + 4.8 = 3.44 V
2. Obtain dc currents and voltages throughout the circuit of simplified circuit of an op-amp shown
in Fig. 15.9.
Solution
All silicon transistors have been used. The solution starts from transistor T3.
10
VB3 = 15 = 10 V, VE3 = VBE3 0.7 = 10 0. 7 = 10.7 V
15
$$
VE 3 - 10.7 - (-15) 4.3 0.5

IC3 = = = = 0.5 mA, IE1 = IE2 = = 0.25 mA
8.6 K 8.6 K 8.6 K 2
Figure 15.9 Simple circuit representing op-amp
VC1 = 15 20 ¥ 0.25 = 10 V, VE6 = 10.7 V

VE 6 - 10.7 - ( - 15) 4.3 2
IE6 = = = = 2 mA, IE4 = IE5 = = 1 mA
2.15 K 2.15 K 2.15 K 2
VC5 = 15 3 ¥ 1 = 12 V = VB7, VE7 = VB4 VBE7 = 12 0.7 = 11.3 V
15 - 11.3 3.7
IE7 = = = 1.42 mA = IC7
2.3 K 2.3 K
VB8 = 15 + 15.7 ¥ 1 = 0.7 V, VE8 = VB8 VBE8 = 0.7 V 0.7 V = 0 V
15
IE8 = = 5 mA
3
15.2 Ideal Characteristics of Operational Amplifier

We know that ideal numbers are infinite and zero. Hence, ideal characteristics of an op-amp are in the
form of either zero or infinite as described below:
∑ infinite input resistance, i.e. Ri = •
∑ zero output resistance i.e. Ro = 0
∑ infinite open circuit voltage gain, i.e. A = •
∑ zero input offset current, i.e. Iio = 0
∑ zero output offset voltage, i.e. vo = 0 for vi = 0
The symbolic representation of op-amp looks like a triangle with its vertex indicating the direction of
flow of signals, i.e. vertex indicates the output voltage. It has two input terminals, namely,
$$
∑ inverting and
∑ non-inverting
These terminals are indicated in Fig. 15.10. The terminal marked with negative sign () is called
inverting terminal as any signal applied to it w.r.t. other terminal grounded produces the amplified output
with 180° phase shift. In other words, the phase shift between input and output voltages are 180° .
Figure 15.10 Symbol of an op-amp
Similarly, the terminal marked with positive sign (+) is called non-inverting terminal as any signal
connected to it with other terminal grounded produces the amplified output without any phase shift. The
three most important characteristics of any amplifier are
∑ input resistance
∑ output resistance and
∑ open circuit voltage gain
The equivalent circuit model of an ideal op-amp is shown in Fig. 15.11. The non-ideal op-amp
equivalent circuit may be drawn as shown in this figure that deviates from the ideal one in the manner
that it has finite input Ri and output Ro resistances and also finite open circuit voltage gain A. We know
that an op-amp is a voltage controlled voltage source hence, implications of these parameters must be
examined before taking into consideration its ideal characteristic.
1. Ri = •. Very large input resistance means the op-amp does not draw any current through its
input terminals. Hence, the signal to its input can be supplied by any of the voltage sources
without the fear of getting the source loaded any time.
Figure 15.11 Ideal and non-ideal model of an op-amp
2. Ro = 0. It means that the op-amp can be connected to any load, even to a short circuit. As it is
clear from its equivalent circuit of Fig. 15.11 its output voltage vo is expressed as
$$
Avi R L
vo = (15.2.1)
Ro + RL
It is clear from Eqn. 15.2.1 that its output voltage is dependent on both output resistance and
the load resistance. If Ro << RL, then Eqn. 15.2.1 reduces to
v o = Avi (15.2.2)
Eqn. 15.2.2 reveals that the output voltage is independent of load resistance RL in the case of an
op-amp This leads to the conclusion that an op-amp can be loaded to any extent.
3. A = •. The output is infinite even for insignificant input and hence, infinite gain. The product of
infinity and zero (insignificant input, i.e. Avi = • ¥ 0) is indeterminate but can be finite. This
leads to the conclusion that vi = 0 means that the voltage between two input terminals is zero.
Having analysed the non-ideal op-amp characteristics, now it will be used as a circuit element in
different types of circuits.
15.3 Frequency Response of Op-amp

We know that the bandwidth of an ideal op-amp is infinite, but in the case of a practical op-amp the
Open loop gain starts rolling-off (decreases) at higher frequencies. What could be the reason for such
decrease in the gain at higher frequencies? Obviously, it would be the capacitive effect across the output
terminals of the op-amp whose reactance starts decreasing with increasing frequency and hence, the
output voltage decreases at very high frequency and the gain gets drastically reduced. The simplest
model of the op-amp at high frequency can be drawn as in Fig. 15.12.
AoL vd (1/ jw C ) AoL vd AoL vd AoL vd
From Fig. 15.12, vo = = = = (15.3.1)
Ro + 1/ jw C 1 + jw CRo 1 + jw / w h 1 + jf / fh
vo AoL
Hence, loop gain of the op-amp = Av = = (15.3.2)
vd 1 + jf / fh
where v d = differential mode input signal
AoL = Open loop dc gain of the op-amp
f h = 3 dB frequency
Figure 15.12 High frequency model of op-amp and its frequency response
$$!
Equation 15.3.2 reveals that

∑ for f < fh, the magnitude of the gain is = 20logAoL dB.
∑ for f = fh, the gain falls by 3 dB from 20logAoL dB.
∑ for f > fh, the gain rolls-off at the rate of 20logAoL dB.
Equation 15.3.2 is plotted as in Fig. 15.12.
A practical op-amp has a number of stages of amplifiers with each of them producing a roll-off
characteristics as shown in Fig. 15.12. The general open loop voltage of the op-amp is one as indicated
in Fig. 15.13.
Figure 15.13 Open loop gain versus frequency plot of op-amp
The frequency response of the op-amp shown in Fig. 15.13 produces the open loop gain of the op-
amp as
AoL
Av = (15.3.3)
(1 + jf / f 1 )(1 + jf / f 2 )(1 + jf / f 3 )
where f1 < f2 < f3.
Equation 15.3.3 has f1 as the dominant pole as this frequency dominates over the other two frequencies
f2 and f3 for fall of the gain.
15.3.1 Compensation Techniques

Special cases do exist where very large bandwidth and low gain are required. In such situations, externally
components are connected across the output of the op-amp to achieve such requirements. Two methods
are used for such compensations:
∑ Dominant pole compensation
∑ Pole-zero compensation
Dominant Pole compensation
If Av is the uncompensated open loop gain of the op-amp then a RC circuit in series with the op-amp as
in Fig. 15.14 can produce a dominant pole. Adding a pole to decrease the gain can generate the dominant
pole compensated transfer function.
$$"
1
v
( AoL ) AoL AoL AoL vd
jw C
Av¢ = o = = = = (15.3.4)
vd 1 1 + j CRo
w w f
Ro + 1+ j 1+ j
jw C wd fd
Figure 15.14 Dominant pole compensation
vo A – - tan f / f d
Hence, open loop gain of the op-amp = A¢v = = oL (15.3.5)
vd 1 + f / fdb2
g
1
where fd = (15.3.6)
2pRo C
AoL
A¢v = (15.3.7)
(1 + jf / f1 )(1 + jf / f2 )(1 + jf / f3 )(1 + jf / fd )
where f d < f1 < f2 < f3 (15.3.8)
1
The compensated gain starts decreasing at the rate of 20 log AoL dB/decade and at fd = as
2pRo C
indicated in Fig. 15.15 it passes through 0 dB at dominant pole frequency f1.
Figure 15.15 Dominant pole compensation

$$#
The main disadvantage of this scheme is that it reduces the open loop bandwidth drastically, but the
noise immunity has been improved as the noise frequency components outside the bandwidth are eliminated.
Pole-zero Compensation
By this scheme the uncompensated open loop gain (transfer) function is altered by introducing both zero
and pole as shown in Fig. 15.16(a) and the corresponding plot is shown in Fig. 15.16(b). The compensation
network is selected such that it produces zero at the first corner frequency f1 of the uncompensated
transfer function Av. This zero cancels out the effect of the pole at f1. The pole of the compensating
voltage network is selected such that the transfer function Av¢ passes through 0 dB at the second corner
frequency f2 of the uncompensated transfer function in Eqn. 15.3.3. In order to avoid the loading effect,
R2 >> R1.
vo A ( R + 1/ jw C1 ) ( AoL )(1 + jw C1R1 )
Av¢ = = oL 1 =
vd R + R1 + 1/ jw C1 {1 + jw C1 ( R + R1 )}
( AoL )(1 + jw / w z ) ( AoL )(1 + jf / f z )

= = (15.3.9)
(1 + jw /w p ) (1 + jf / f p )
Here, f z = fi
Figure 15.16(a) Pole-zero compensation
Figure 15.16(b) Pole-zero compensation

$$$
Now substituting Eqn. 15.3.3 in Eqn. 15.3.9 gives

(1 + jf / f z ) AoL
Av¢ =
(1 + jf / f p ) (1 + jf / f1 )(1 + jf / f 2 )(1 + jf / f 3 )
AoL
= (15.3.10)
(1 + jf / f p )(1 + jf / f 2 )(1 + jf / f 3 )
where f p < f1 < f2 < f3 (15.3.11)
Figure 15.17 Comparison of pole-zero and only pole compensation
Figure 15.17 gives an estimate of improvement in the 3 dB bandwidth of the amplifier when
compensated using networks yielding only one pole and one zero. This improvement in bandwidth is
clearly (f2 f1) The internally compensated operational amplifiers available in the market has very large
bandwidth and very high open loop gain. The frequency response of an important operational amplifier
such as 741 is shown in Fig. 15.18. Its gain-bandwidth product is 1 MHz as indicated in Fig. 15.18.
Figure 15.18 Frequency response of 741

$$%
Slew Rate
The slew rate is defined as the rate of change of the output voltage w.r.t. the change in the input voltage.
The output voltage beyond dominant pole frequency does not change simultaneously, it becomes very
different. The output under such condition is called the slew rate limited output. The Maximum Slew
Rate (MSR) may be defined as the maximum rate of undistorted change of output voltage for the supply
of maximum output amplitude. There are many factors that are responsible for limiting the MSR. One of
these factors is the load capacitance. Its typical value of the slew rate ranges from 1 V/ms to 100 V/ms.
Due to presence of the load capacitance, a time constant comes into the picture for the output response
of the amplifier. The output voltage rises slowly w.r.t. input voltage as shown in Fig. 15.18. It may be
understood as slow rate rising voltage. The typical value of slew rate of 741 is 0.5 V/ms.
The slew rate may be thought of as slow rate of output signal w.r.t. input signal as indicated in
Fig. 15.19. Let the sinusoidal output be represented as
v o = Vm sin w t (15.3.12)
where Vm = maximum allowed amplitude of voltage.
Figure 15.19 Slew rate
The amplitude of derivative of the vo = |Vmw cos w t| (15.3.13)

The maximum rate of change of the output amplitude wVm and the maximum slew rate can
be = wVm.
If the MSR = 1 V/ms = wVm = 2p f Vm
and for Vm = 1 V the maximum frequency for the undistorted output voltage is
MSR 1 V/ ms 106
fmax = = = = 159 kHz (15.3.14)
2pVm 2p ¥ 1 2p
If the amplitude of the output signal is changed to 10V, the maximum frequency for the undistorted
MSR 106
output becomes = fmax = = = 15.9 kHz.
2pVm 2p ¥ 10 V
$$&
15.4 Offset Voltage

The offset voltage can be read as set off voltage. In other words, the output voltage must be zero when
the set is off. We think that the set is off when the input signal is not applied. Hence, for no input signal,
the output signal should also be zero as illustrated in Fig. 15.20 but the output voltage do exist even
without input voltage, i.e. vo is finite for vi = 0.
Figure 15.20 Offset voltage demonstration
voffset
In this figure applying a voltage at its input has compensated the offset voltage appearing
A
across the output. The offset is compensated by application of the external dc voltage across the nulling
terminals of op-amp as shown in Fig. 15.21.
Figure 15.21 Offset compensation and nulling method
15.5 Inverting Op-amp Circuit

The most widely used op-amp circuit is in the form of inverting configuration. The simple inverting
amplifier circuit using op-amp is shown in Fig. 15.22(a). This circuit has a resistance R1 connected
between its inverting terminal and the signal vi ◊ RF is the resistance connected between its output and
inverting terminal to provide the negative feedback.
For ideal op-amp ii = 0, hence,
v i = v(+) v() = 0 (15.5.1)
where, v(+) and v() are voltages at noninverting and inverting terminals.
The non-inverting terminal in Fig. 15.22(a) is grounded and vi = 0, the summing point voltage is v(+) = v()
$$'
Figure 15.22(a) Inverting op-amp circuit
Figure 15.22(b) Non-inverting op-amp circuit
v(+) = v() = 0, i1 = if and i1 if = 0 (15.5.2)

vs - 0 0 - vo
= (15.5.3)
R RF
R
v o = F vs (15.5.4)
R1
15.5.1 Non-inverting Op-amp Circuit

The non-inverting op-amp configuration is also called the voltage follower as its output voltage in totality
follows the input voltage under the condition RF = 0. In such situation the output terminal directly gets
connected to its inverting input terminal as demonstrated in Fig. 15.22(b). The signal is connected to its
non-inverting terminal. From Fig. 15.22(b),
v(+) = v() and i1= if (15.5.5)
va f v o - v( - )
= (15.5.6)
R1 RF
RF
vo v() = v( - ) (15.5.7)
R1
$%
FG
vo = 1 +
RF IJ R
v( -) = 1 + F vs
FG IJ (15.5.8)
H R1 K R1 H K
The close loop gain of the non-inverting op-amp shown in Fig. 15.22(b) is described by Eqn. 15.5.8
that is always greater than unity and is a positive number. In other words, it is not associated with any
phase-shift between the input and output.
Example
For the circuit shown in Fig. 15.23, obtain the output voltage. This circuit can be analyed by superposition
theorem.
Thus vo1 = output due to input signal v1 only, and
vo2 = output due to input signal v2 only.
v o = vo1 + vo2
vo1 = -
FG R IJ vF
1
HR K 1
Similarly vo2
F R IJ v
= G1 + F
2
H RK 1
Total output voltage vo

F R IJ v + FG1 + R IJ v
= G F
1
F
2
HRK H R K 1 1
FR I F
= G J (v - v ) + v 2 1 2
HR K 1
Figure 15.23 Signals at inverting and non-inverting terminals
15.6 Summing Op-amp Circuit

An op-amp circuit in Fig. 15.24 can perform weighted sum of any number of signals. This figure has
three input signals v1, v2, and v3 connected to the inverting terminal of the op-amp through resistances
R1, R2, and R3 respectively.
$%
Figure 15.24 Summing op-amp circuit
The summing point S is virtually grounded because v(+) = 0.

v(+) = v() = 0 (15.6.1)
Currents i1, i2, and i3 are expressed as
v1 v v
i1 = , i2 = 2 , i3 = 3 (15.6.2)
R1 R2 R3
Also i1 + i2 + i3 + if = 0 (as ii = 0) (15.6.3)
v1 v2 v v
+ + 3 = o (15.6.4)
R1 R2 R3 RF
v o = RF
FG v
1
+
v2 v
+ 3
IJ (15.6.5)
HR1 R2 R3 K
Equation 15.6.5 reveals that the output voltage is the weighted sum of the three input voltages with its
corresponding weights of RF /R1, RF/R2 and RF/R3. If RF = R1 = R2 = R3, then,
v o = (v1 + v2 + v3) (15.6.6)
Equation 15.6.6 illustrates that the circuit of Fig. 15.24 works as simple inverting adder.
15.6.1 Subtractor
A circuit that provides the difference of two signals is called subtractor. Fig. 15.25 is the circuit of a
subtractor.
R3
v + = v2 = v
R2 + R3
v1 v v - vo
= -
R1 RF
vO Ê 1 1ˆ v v2 R3 Ê 1 1ˆ v
or = v Á + ˜ 1 = Á + ˜ 1
RF Ë RF R1 ¯ R1 R2 + R3 Ë RF R1 ¯ R1
$%
vo v2 R3 Ê 1 1ˆ v
or = Á + ˜- 1
RF R2 + R3 Ë RF R1 ¯ R1
If R 1 = RF = R2 = R3 = R, then
v2 RR Ê 1 1 ˆ v1R
vo = Á + ˜-
R + R Ë R R¯ R
v
= 2 (2) v1 = v2 v1
2
Thus, the output voltage vo is equal to the difference of
Figure. 15.25 Subtractor
the two input voltages v2 and v1.
15.6.2 Programmable Gain Amplifier

In place of a fixed feedback resistor RF, a potentiometer (variable resistor) may be used to obtain a
variable scale factor (variable gain control) as indicated in Fig. 15.26(a). Though, the change in the scale
factor is large but it cannot be linear and its input resistance is severely affected, i.e. it falls with
increasing gain. In order to avoid such limitations, Fig. 15.26(b) is proposed. Here, the scale factor is
limited to a maximum of RF /R1. In this case, the variable gain shall be linear and input resistance is fixed
at R1. The circuit can be arranged to switch either manually or automatically, through a series of
resistors of different values to set the particular scale factors for obtaining the predetermined values of
scale factors.
Figure. 15.26(a) Large variable gain Figure. 15.26(b) Low variable gain
Fig. 15.27 illustrates the use of a monolithic quad JFET switch for arranging a programmable gain
op-amp circuit. The op-amp is also a high input resistance FET input amplifier. The gain select inputs
operate on TTL level.
15.6.3 Voltage Follower

The word voltage follower means the output voltage exactly follows the input voltage. The output in
case of the voltage follower is directly connected to the inverting input terminal of the op-amp as
illustrated in Fig. 15.28. The input signal is then connected to the non-inverting terminal.
$%!
Figure. 15.27 Programmable gain amplifier Figure 15.28 Voltage follower circuit
Since in Fig. 15.28 v(+) = v() = vs (15.6.7)

The output is directly connected to the inverting input terminal
v o = v(+) = v() = vs (15.6.8)
Voltage gain of the voltage follower is
vo
=1 (15.6.9)
vs
15.7 Op-amp Integrator & Differentiator

Now we discuss the basic circuits of integrators and differentiators alongwith its limitations on fre-
quency range.
15.7.1 Basic Op Amp Integrator

One of the important mathematical operations performed by the Op Amp is integration of the input
signal. The simple arrangement of an integrator is shown in Fig. 15.29(a). The point S is again virtually
grounded and hence
v1 (t )
i(t) = (15.7.1.1)
R1
The capacitor C in the feedback path will be charged to voltage vo with the constant current as
1 1 v1 (t ) 1
vo =
C z
i (t )dt + Vo (0) =
C z R1
dt + Vo (0) =
R1C z v1 ( t ) dt + Vo (0) (15.7.1.2)
$%"
Eqn. (15.7.1.2) indicates that the output voltage is pro-

portional to the integration of the input voltage with the
initial condition Vo (0) and hence the circuit of Fig.
15.29(a) is called an integrator.
Here, Vo (0) = initial condition of voltage stored on the
capacitor.
Now we obtain the output waveform for different types
of inputs.
Figure 15.29(a) Op amp integrator circuit
(a) Step input
Vi = a (t ≥ 0)
1
vo = - adt + Vo (0) = -at (15.7.1.3)
R1C Ú
where, initial condition, Vo (0) = 0, R1C = 1
(b) Square wave input
Vi = a(0 < t < T/2) and Vi = a(T/2 < t < T)
T /2 T /2
1 aT
vo = Ú adt + Vo (0) = Ú adt = at (0 < t < T/2) = at t = T/2 (15.7.1.4)
R1C 0 0
2
T
1 Ê T ˆ aT
vo = Ú - adt = at (T/2 < t < T) = a Á T - ˜ - = 0 at t = T (15.7.1.5)
R1C T / 2 Ë 2¯ 2
Figure 15.29(b) is the frequency response of the integrator for step and square inputs.
Figure 15.29(b) Input and output wave forms of step and square wave input
D.C. Stabilization
The integrator circuit shown in Fig. 15.29(a) produces the output voltage proportional to the time
integral of the input signal provided the input signal frequency is not too low. The impedance offered by
capacitor C at low frequency is very large w.r.t. the input resistance R1 i.e. |ZC| >> R1 in Fig. 15.29(a).
The close loop gain |ZC|/R1 tends towards infinity and dc stabilization is not achieved. The gain in dB is
$%#
positive. At high frequency |ZC| << R1 and close loop gain becomes very low (negative dB). A resistor
RF across the capacitor C in the feedback path is included to provide d.c. stabilization when input signal
frequency is too low so that at such low frequency the open circuit impedance offered by the feedback
path does not destabilize the process of integration. The main function of RF is to limit the low fre-
quency gain of the amplifier and hence minimizing the problem of the drift. The introduction of resistor
RF puts a limitation on the frequency of integration of the signal. From Fig. 15.29(a), output voltage is
expressed as
t
ZF 1 1 1
vo = vi = - vi = vi = - vi dt (15.7.1.7)
R1 jw CR1 SCR1 R1C Ú0
1 d
We know that = Ú dt and S = (15.7.1.8)
S dt
vo 1 1 1 Ê 1 ˆ
= - =- =- = -1 = 0 dB Á for w h = (15.7.1.9)
vi SCR1 jwCR1 wCR1 Ë CR1 ˜¯
Fig. 15.29(d) is the frequency response plot of the basic
and practical integrator.
At w = wh, where |ZC| = R1, it provides unity gain
(0 dB). Hence, this circuit is seldom used. A resistance
(RF) is connected across the capacitor (C) to provide dc
stability (at low frequency) as in Fig. 15.29(c). From Fig.
15.29(c).
RF (1/ SC ) RF
ZF = = (15.7.1.10)
RF + 1/ SC SCRF + 1
Close loop gain of practical integrator Figure 15.29(c) Practical integrator
vo Z RF
= =- F =-
vi R1 ( SCRF + 1) R1
Ê R ˆ 1 1
= Á- F ˜ =-
Ë R1 ¯ SCRF + 1 R
jw CR1 + 1
RF
vi v 1
vo = - ( RF >> R1 ) @ - i = - vi dt (15.7.1.11)
jw CR1 SCR1 CR1 Ú
Eqn. (15.7.1.11) is the equation of a basic (ideal) integrator.
vo Ê R ˆ 1 ÊR ˆ 1
= Á- F ˜ = - Á F dB - 3dB˜ for w min = w a =
vi Ë R1 ¯ 1 + 1 Ë R1 ¯ RF C
$%$
RF
=- at w = 0 (15.7.1.12)
R1
The close loop gain of the practical
Ê R ˆ
integrator is constant Á - F ˜ in the range
Ë R1 ¯
of frequency from 0Hz to wa. The gain starts
decreasing after wa at a rate 20dB/decade.
Hence, the circuit works as integrator in the
1 1
frequency range wa = and wh = .
RF C CR1
The values of R1C and RFC could be selected
assuming a thumb rule wh = 10 wa. In the
range of frequency from 0 to wa rad/sec,
the impedance offered by the capacitor C is
much less and the feedback resistance RF
that provides stable close loop gain. The
Figure 15.29(d) Plot of close gain versus frequency of
frequency range in between wa rad/sec and
integrator
wh rad/sec, the impedance offered by C is
larger than the feedback resistance RF and hence it starts working as integrator.
We see that wa << wh. Normally it is assumed that wh = 10 w a.
For C = 0.1 mF and R1 = 10 KW,
1 1
wh = = = 1Krad/s
R1C 10 K ¥ 0.1 m F
1Krad/s 1
wa = = 100rad/s, hence value of RF = = 100KW
10 100 ¥ 0.1 m F
15.7.2 Basic Op Amp Differentiator

The Fig. 15.29(a) becomes differentiator if the position of 2-passive components is interchanged. The
circuit of differentiator of Fig. 15.29(e) has also its inverting terminal point S virtually grounded.
Thus,
v(+) = v() = 0 (15.7.2.1)
vo
if = (15.7.2.2)
RF
The input current through C1 in Fig. 15.29(e) is proportional to the rate of change of v1. The output
causes an equal current to flow through RF, therefore vo takes on a value proportional to the rate of
change of the input voltage. For an ideal Op. amp, the response is described as
$%%
dv1 - v0
i(t) = C1 = if = (15.7.2.3)
dt RF
dv1
v o = C1RF (15.7.2.4)
dt
Eqn. 15.7.2.4 indicates that the circuit of Fig. 15.29(e) works as differentiator. The circuit shown in
Fig. 15.29(e) is not the practical one. It is susceptible to the high frequency noise, since the ac gain
increases at the rate of 20dB per decade. In addition, the RF and C1 in this figure works as low-pass
filter, which contributes a 90° phase shift to the loop and can cause stability problems, even with the
frequency compensated amplifier for unity gain. Hence, a resistor R1 is connected in series with the
capacitor C1 as in Fig. 15.29(f).
Figure 15.29(e) Op Amp differentiator circuit Figure 15.29( f) Practical differentiator
Practical Differentiator
Similar to the basic integrator, the impedance offered by the capacitor C1 of basic differentiator is also
very high i.e. |ZC | >> RF as in Fig. 15.29(e). The close loop gain becomes very low (approximately
zero). The circuit provides attenuation (negative dB). Hence, this circuit is seldom used. A resistance is
connected in series with the capacitor C1 as in Fig. 15.29(f). At high frequency |ZC| << RF, the close
loop gain becomes very large (approximately infinite). In other words, it provides magnification (positive
dB). This is again known as dc instability. At w = wL, where |ZC| = RF, it provides unity gain (1 = 0 dB).
So wL is called unity gain frequency.
The close loop gain of basic differentiator can be written as
RF d
vo = vi = SRFC1vi = jwRFC1vi = RFC1S(vi) = RFC1 vi (15.7.2.5)
Z1 dt
vo 1
= jwRFC1 = 1|wRFC1| = 1 for w L = (15.7.2.6)
vi RF C1
vo 1
= 0dB for w L = (15.7.2.7)
vi RF C1
The circuit of practical integrator is shown in Fig. 15.29(f).
$%&
1 SC R + 1
Z1 = R1 + = 1 1
SC1 SC1
vo
Close loop gain of practical differentiator =
vi
RF RF SC1RF RF
=- =- +- =- (15.7.2.8)
Z1 SC1R1 + 1 SC1R1 + 1 R1 + 1/ SC1
SC1
- RF R
= = - F for w = • (15.7.2.9)
R1 + 1/ j • C1 R1
vo = - RF /R1 =-
RF /R1 Ê R ˆ 1
= Á- F ˜ for w = w a =
1
1 / 1 / (15.7.2.10)
vi - j w C R
1 1 - jw a w Ë R1 ¯ 1 +1 C1 R1
Ê R ˆ 1
= Á- F ˜ (15.7.2.11)
Ë R ¯ 21
Fig. 15.29(g) is the frequency response

plot of the basic and practical differentiator.
At high frequency the impedance offered
by the capacitor C1 is very low in compari-
son to the value of R1 and hence stable close
R
loop gain is provided by - F . Below
R1
frequency wa to wL, the impedance of C1
much less than R1 and hence C1 becomes
effective and works as differentiator. Figure 15.29(g) Plot of close gain versus frequency of
differentiator
1 1
Hence, wL = << wa =
RF C1 C1R1
1 1
or, 10wL = wa, wL = -7
= 1Krad/s, so wa = 10Krad/s = -7
10 K ¥ 10 10 R1
1
R1 = -7
= 1KW.
10 ¥ 10K
Applications of Differentiators
(a) Ramp input (Vi = at for t > 0)
d d (-at )
vo = RFC1 vi = RF C1 = a (for RF C1 = 1)
dt dt
Figure 15.29 (h) is the frequency response of the differentiator for ramp and triangular inputs.
$%'
(b) Triangular input (Vi = at for 0 < t < T/2 and at for T/2 < t < T))
d d (-at )
vo = RFC1 vi = RFC1 = a (0 < t < T/2)
dt dt
d d (at )
vo = RFC1 vi = RFC1 = a (T/2 < t < T)
dt dt
Figure 15.29(h) Output of practical differentiator for ramp and square wave inputs
15.8 Non-linear Applications of Op-amps

So far we have discussed the use of op-amps for low signal inputs. Now let us describe some applications
of ideal op-amp under large signal operations. It is known that an op-amp has two input terminals. The
differential configuration of op-amp was designed to use the op-amp as a comparator. The non-ideal
and ideal transfer characteristic of the op-amp are shown in Fig. 15.34.
Figure 15.34 Non-ideal and ideal transfer characteristic of op-amp
The linear range of transfer curve in left side of Fig. 15.34 can be assumed to be very small (few milli
volts typically 120 mV). By proper design the linear range to right side of this figure is neglected. Since,
open circuit voltage gain of op-amp is infinite, any difference in the two input voltages saturates the
output of op-amp limited to positive or negative supply voltage. In other words, output voltage under
saturated condition is either +Vsat = +VCC or Vsat = VCC.
$&
15.8.1 Comparator
The basic comparator swings its output to ±VCC for slightest difference in its two input voltages. Its
output voltage polarity when the one input signal exceeds the magnitude of the other called threshold
level. The threshold level is denoted as reference voltage VR. A comparator is basically an op-amp
without any negative feedback.
We know that if the loop gain of any circuit is made exact unity, its close loop gain becomes infinite.
This is the requirement of a comparator for giving abrupt transition in its output level limited to the two
saturation values +VCC and VCC.
When the input voltage Vi is less than VR in Fig. 15.36, the output voltage Vo is negative and is limited
by the negative supply voltage (VCC). When the input voltage Vi becomes more than VR, the output
voltage Vo becomes positive and is limited by the positive supply voltage (+VCC). The comparator is
used to compare two input voltages and its output indicates which input voltage is higher than the other
at any instant. Thus, a comparator is a circuit not used for amplification of the signals, but to indicate
whether the signal magnitude is more or less than a specified reference voltage level. It has many uses
in digital circuitry.
Figure 15.35 Switching positive to negative and negative to positive saturation
Figure 15.36 Comparator with VR

Figure 15.37 shows that the output voltage swings between positive saturation to negative saturation
limited by +VCC and VCC respectively. It can be used as a zero crossing detector also. In short
Vo = +VCC for VI > 0+
Vo = VCC for VI < 0
Figure 15.37 Comparator with VR = 0

$&
15.8.2 Window Detector

The window detector is a circuit that detects input signal VI that falls between two predefined values of
voltages. For practical example, the input signal VI may be from a photosensitive device on a camera.
The cameras operation needs to be modified depending upon whether the incident light is too low or too
high, or in-between these extremes. The function of window detector have been given in Table 15.1.
The reference voltage to comparators in Fig. 15.38 are
R1VB 24
V1 = = = 8 V and
R1 + R2 + R3 3
V2 =
bR + R g V
1 2 B
=
2 ¥ 24
= 16 V
R1 + R2 + R3 3
Table 15.1 Functions of Window detector
VI V1 V2 Vo1 Vo2 Vo
VI < 8 V 8V 16 V VCC +VCC 0
16 V > VI >8 V 8V 16 V +VCC +VCC 1(+VCC)
VI > 16 8V 16 V +VCC VCC 0
The reference voltages V 1 and V 2 are

connected to the inverting input of the
comparator A1 and non-inverting terminal of the
comparator A2 respectively. When VI < V1 (= 8
V), the output of comparator A1 will remain at
negative saturation (Vsat = VCC) and Vo2 =
+VCC. Thus, the output of AND gate becomes 0
(as VCC = low state). Whenever VI > V1, Vo1 =
+VCC and Vo2 = +VCC. Now the output of AND
gate is 1 (= +VCC). When VI > V2 (16V),Vo1=
+VCC, and Vo2 = VCC hence, the output of the
AND gate is again 0. This is explained in Table
15.1. The AND gate will produce an output only
when the Vo1 and Vo2 are 1 (= +VCC)
Another example of comparator is in a low-
level light detector as shown in Fig. 15.39. Here, Figure 15.38 Window Detector
RP represents a photoresistor when resistance is very high for low light level.
R R R
Vo1 = P V1 = P (-1 V) = P V
R R R
where RP is in KW. The output of A2 will be positive for Vo1 less than the reference voltage +1.5 V.
Thus, (Rp/10) < 1.5
or Rp < 15 K, Vo = VCC
(Rp/10) > 1.5
or Rp > 15 K, Vo = VCC
$&
The circuit will have negative output (which can be used to turn ON a warming lamp) when the light
level is low enough to make RP > 15 KW.
Figure 15.39 Low light level detector
15.8.3 Schmitt’s Trigger

A combination of comparator and positive fedback leads to an useful circuit called Schmitts Trigger. A
comparator has only one threshold voltage at which it changes its states from positive saturation to
negative saturation or vice-versa. A comparator can be designed with two threshold voltages rather than
one. These threshold levels of a comparator are denoted by high threshold VTH and low threshold VTL
around a reference voltage VR. Figure 15.40 is the circuit of a comparator with positive feedback
without reference voltage, i.e. VR = 0 V.
If a portion (b Vo = b VCC) of the output voltage is fedback to the non-inverting input terminal of the
op-amp it is called positive feedback. If the close loop gain Avb is greater than unity, i.e. Avb > 1, the
regeneration begins and the output voltage will be saturated at either Vmax = VCC, or Vmin = VCC. As VI
is increased from 0V, nothing happens to the output voltage Vo until VI reaches the value slightly more
than b VCC when the output switches to negative saturation value (VCC) as indicated in Fig. 15.40. On
the other hand, when VI returns back to less than b VCC, the output switches again back to positive
saturation +Vsat = +VCC. Thus, the output becomes bistable. This is plotted in Fig. 15.40.
Let us assume that initially output voltage = Vo = Vmax = VCC. Now if the input increases and become
slightly higher than b VCC = VTH (called higher threshold voltage), the output switches from VCC
to VCC. Now when the input is decreased, it does not switch back at b VCC, but at bVCC = VTL,
called lower threshold voltage. Thus, there exists a hysteresis (lag).
The amount of hysteresis in Fig. 15.41 is = VTH VTL.
Writing nodal equation at VI+ yields
VI ( + ) - Vo VI + - VR
+ =0
R2 R1
or FG
VI+ 1 + 1 IJ = V o
+
VR
H
R2 R1 K R 2 R1
R1VO RV
or VI+ = + 2 R
R1 + R2 R1 + R2
For VI+ positive and large enough to saturate op-amp, VO = VCC at VI+ = VTH.
R1VCC R2VR
VI+ = VI = VTH = +
R1 + R2 R1 + R2
$&!
Figure 15.40 Positive feedback comparator VR = 0 V
Figure 15.41 Schmitt’s Trigger with VR

Here the reference voltage is not fixed but derived from the output voltage through a voltage divider
R1 and R2. The expressions for these two threshold voltages VTH and VTL are derived here.
Suppose Vo = +Vsat = +VCC, the voltage at non-inverting terminal is
R (V - VR ) R (V - VR )
= VR + 1 o = VR + 1 CC = VTH
R1 + R2 R1 + R2
This voltage is called upper threshold voltage VTH. As long as VI < VTH, the output remains constant
at +Vsat = +VCC. When VI is just more than the VTH, the output regeneratively switches to Vsat = VCC
and remains at this level as long as VI > VTH .
For Vo = Vsat = VCC, the voltage at the non-inverting terminal of the Schmitts trigger is
R (- Vsat - VR ) R (V + VR )
= VREF = VR + 1 = VTL = VR - 1 sat
R1 + R2 R1 + R2
$&"
R1 (VCC + VB )
= VR -
R1 + R2
We see that VTL < VTH, and the difference between these two voltages is called the hysteresis width VH.
R (V - VR ) R (V + VR ) 2 R1VCC
VH = VTH VTL = VR + 1 CC VR+ 1 CC =
R1 + R2 R1 + R2 R1 + R2
Since +Vsat = +VCC, R2 = 80 K and R1 = 20 K,
VTH = VR + 0.2 (VCC VR) = 0.8 VR + 0.2 VCC
V TL = VR 0.2 (VCC + VR) = 0.8 VR 0.2 VCC
Hence, VTH VTL = 0.4 VCC = Hysteresis or Backlash of the Schmitts trigger.
Examples
1. Determine the two threshold voltage and the hysteresis voltages of the Schmitts trigger circuit
Figure 15.42
Solution
VTH = 0.8VR + 0.2VCC = 0.8 ¥ 2.5 + 0.2 ¥ 12.5 = 2 + 2.5 = 0.5 V
V TL = 0.8VR + 0.2 ¥ VCC = 0.8 ¥ 2.5 + 0.2 ¥ 12.5 = 22.5 = 4.5 V
VH = VTH VTL = 0.5V (4.5V) = 5 V
2. Change the value of the battery supply VR such that VTL = 0 V. Obtain the new value of VTH and
draw the output waveform for the input shown in Example 1.
Solution
V TL = 0 V = 0.8VR 0.2 VCC
VR = 0.2 ¥ 12.5/0.8 = 12.5/4 = 3.125 V
VTH = 0.8 VR + 0.2 VCC = 0.8 ¥ 3.125 + 0.2 ¥ 12.5 = 2.5 + 2.5 = 5 V
Since the input voltage never crosses the VTH and hence, the circuit will never switch to low state. It
will always remain in the high state.
15.8.4 Peak Detector
The basic function of the peak detector is to capture the peak value of the input signal and retain the peak
value. The principle of peak detector is based on storing the highest value of the signal on a capacitor.
The highest value remains stored until the capacitor is discharged. When VI exceeds VC (voltage across
$&#
the capacitor) in Fig. 15.43, the diode D is forward biased and the circuit behaves like a voltage fol-
lower. Consequently, the output voltage Vo follows the input voltage VI as long as VI > vC and capacitor
gets charged to the peak value of the input signal. As soon as VI drops below vC, the diode becomes
reverse biased and the capacitor holds the charge till the input voltage again attains a value higher than
v C .
Figure 15.43 shows waveshape of positive peak detector.
Figure 15.43 Peak detector circuit
15.8.5 Clipper
If a reference voltage VR is connected in series with the load resistance in the half-wave rectifier, a
clipping circuit shown in Fig. 15.44(a) results. When VI > VR, the output voltage Vo becomes positive
and diode D is forward biased. With the diode in conduction, the circuit behaves as unity gain amplifier
and VI is transmitted to the load VL as shown in Fig. 15.44(b). The diode is reverse biased with VI < VR
and hence, the load is not connected to VI. Thus, top of the signal is only present and rest part of the
signal has been clipped OFF. Zener diodes can be used to clip the waveshapes also as indicated in Fig.
15.44(b). The circuit in positive half-cycle behaves as an inverting amplifier and the output is just the
inverted form of the input wave. The Zener diode breaks down in the negative half-cycle and the voltage
Vo is limited by the breakdown voltage of the Zener diode VZ.
Both, positive and negative peak clipping can be implemented as in Fig. 15.44(c). In positive half-
cycle, the Zener diode VZ2 breaksdown and the output voltage is limited by its break down voltage VZ2.
In the positive half-cycle, Zener diode VZ1 breaks down and the output voltage is limited to its break
down voltage VZ1.
Figure 15.44(a) Clipper

$&$
Figure 15.44(b) Positive peak clipper
Figure 15.44(c) Positive and negative peak clipping
15.8.6 Clamper
Clamping means raising to a level. The clamping is also called dc restorer or inserter. This circuit is used
to add a desired value of dc voltage in addition to some ac voltage. Just like the physical clamp used to
fix up any thing at certain height, the electrical clamping is used to shift the ac level by a fixed dc voltage.
Depending on the dc inserted whether it is positive or negative it is called positive or negative clamping
as indicated in Fig. 15.45.
With VI = 0 V, VA is positive and diode D conducts. The circuit operates as a voltage follower and its
output voltage Vo = VR. On the application of VI = Vmsinwt to the inverting input terminal, the diode
conducts in the negative half-cycle and the capacitor C charges to the peak negative value, i.e. Vm
through the forward biased diode. During positive half-cycle, the diode D does not conduct and the
capacitor circuit remains open. The capacitor retains the voltage stored in the negative half-cycle Vm.
Since this Vm is in series with the ac input signal, the output voltage will be = Vm + VI. The total output
voltage = Vo = VR + Vm + VI. Negative clamping can be implemented by reversing the polarity of the
diode.
$&%
Figure 15.45 Clamper circuit with positive and negative clamper waveshape
15.8.7 Constant Current Source

The voltage at point S remains constant as the Zener voltage VZ does not change due to change in the
supply voltage VCC in circuit of Fig. 15.46 provided VCC > VZ. The inverting input terminal of the op-
amp is at virtual ground.
Figure 15.46 Floating and grounded load current sources
VZ V
i1 = . As no current flows into the op-amp input, i1 = iL = Z . Since VZ and R1 both are constant,
R1 R1
the load current remains constant.
As an example, if VZ = 6 V, and R1 = 0.2 K, i1 = iL = VZ/R1 = 6/0.2 = 30 mA. This current remains
constant through the load provided VCC > 6 V.
As (VI V2) A = V0, and A @ 106, VI = V2 = VE.
VE = REIE = REIC,
VE V
or IC = = I
VE RE
Hence, for fixed value of VI, the collector current IC becomes constant.
$&&
15.8.8 Voltage to Current Converter

One of the common applications of the op-amp is in driving a low resistive load (such as a coil for an
example) with a voltage source of low internal resistance. The voltage to current converter is the
obvious need for such types of applications. Figure 15.47 performs this function effectively.
No voltage drop takes place across the voltage source internal resistance rs as no current flows into
the op-amp terminals and the full voltage appears between the non-inverting terminal and the ground.
Thus, the current IS = vS /rs. Since no current flows into the input terminal of the op-amp, the feedback
current IL must be equal to IS.
Hence, I L = Is = vs/rs (15.8.1)
Figure 15.47 Voltage to current converter
Equation 15.8.1 reveals that the voltage source vS has been converted to current IL into the load
15.8.9 Operational Transconductance Amplifier (OTA)

The transconductance amplifier is also called voltage-to-current converter (V/I) or Voltage Controlled
Current Source (VCCS). It produces output current proportional to the change in the input voltage. The
proportionality factor between the output current and input voltage of the amplifier is called the
transconductance. The MOSFET in Fig. 15.48 functions as a transconductance amplifier. We know
that a conventional operational amplifier can be used as transconductance amplifier. However, mono-
lithic ICs do exist that are designed specifically for such operations.
A voltage source vS drives the amplifier that controls the drain current to flow through a load. The
change in the drain current (load current) is proportional to the change in the input voltage. The
transconductance gm = id/vi can be obtained using small signal equivalent circuit shown.
vgs = vs Rsid
gm v gsrd gm (vs - RS id )rd

id = = (15.8.2)
rr + RS + RL rr + RS + R L
or {rs + RL + (gmrd + 1)Rs} id = gmrdvs
$&'
Figure 15.48 Transconductance amplifier
id gm rd
or =
vs rs + R L + (1 + gmrd ) Rs
gm
= (15.8.3)
rs / rd + R L / rd + (1 / rd + gm ) Rs
Figure 15.49 Operational transconductance amplifier

$'
National semiconductor LM3080 is a popular OTA. The OTA is a single chip amplifier wherein the
transconductance is controlled by an externally connected resistance. The pin diagram and internal
circuitry of the LM3080 is shown in Fig. 15.49. The input section of LM3080 consists of T1 and T2
transistors forming differential pair with active loading provided by transistors T3, T4, T7 and T8. The
quiescent collector currents of T1 and T2 are set up by the current mirror formed by T5 and T6. The
external resistor RR determines the input bias as current IR of the amplifier. The output of the differential
amplifier is applied to the push-pull output stage formed by T7, T8, T9 and T10. Since, transistor T8 and
T10 are in the common emitter configuration, the output resistance of the amplifier is extremely high that
suggests it to be an ideal voltage controlled current source. The transconductance has the unit of
siemens and is defined as
Io I
gm = = L
Vi Vi
A few of the characteristics of LM3080 are shown in Table15.2.
Table 15.2 Characteristics of LM3080
Slew rate 50 V/ms

Open-loop bandwidth 2 MHz
IOUT ±350 mA (guaranteed minimum)
Output resistance 1 MW
Input resistance 26 KW
Transconductance range 10 mS200 mS (linear with IR)
CMRR 110 dB
VIO 0.4 mV
IB 0.4 mA
IIO 0.1 mA
The variable transconductance is controlled by the reference resistor RR using supply voltage VCC in
Fig. 15.49. The reference (bias) current for the current mirror (source) formed by transistors T5 and T6
and is determined as
IR = (|VEE| VBE1)/RR (15.8.4)

Since IC6 = IR , the collector currents IC1 = IC2 = IR /2
IE1 = IC1 = IE2 = IC2 = IEO (expVBE / VT 1) = IEO expVBE / VT (15.8.5)
dI E 1 dI C1 1
gm1 = gm2 = = = I EO expVBE /VT
dVBE 1 dVBE 1 VT
I E1 I I /2 I
= = C1 = R = R (15.8.6)
VT VT VT 2VT
$'
Using Eqn. 11.6.1 the two collector currents IC1 = IC2 are
h fe vi / 2 h fe vi
IC2 = = (vi / 2) = gm , and (15.8.7)
rS + hie hie 2
vi
IC1 = gm (15.8.8)
2
vi
These reference currents set IC8 = IC2 = gm
2
vi v I v
Hence, I L = IC8 IC10 = gm + gm i = gmvi = R i (15.8.9)
2 2 2VT
It is evident from Eqn. 15.8.9 that by varying either IR ( through RR) or (and) vi, we can vary the load
current and hence, the gain. If we assume that RL<< output resistance of the output current source,
then voltage gain is expressed as
VV I R I R
AV = = L L = R L (15.8.10)
vi vi 2VT
Clearly Eqn. 15.8.10 signifies that the voltage gain of the circuit in Fig. 15.49 can be controlled by the
reference current IR.
The LM3080 is basically arranged in two modes of operations : inverting and non-inverting amplifier
configurations as indicated in Fig. 15.50. The output current in both modes of operation is forced
through the load resistor RL to develop the required output voltage. Similar to the conventional operational
amplifier, resistors R1 = R2 are set to reduce the effect of input offset and bias currents. The alternative
method to determine the input bias (reference) current is shown right most in Fig. 15.50. The bias
current from Fig. 15.49 is
VEE + VC - VBE
IR = (15.8.11)
RR
The bias current should be limited in the range
0.1 mA £ IR £ 1 mA (15.8.12)
Using Eqn. 15.8.6
IR 1
gm = = I = 20IR (15.8.13)
2VT 2 ¥ 25 mV R
The output current developed by the non-inverting amplifier configuration is
I L = gmvi and (15.8.14)
v o = vL = ILRL = gmRLvi (15.8.15)
Voltage gain of the non-inverting configuration of the OTA amplifier shown in Fig. 15.50 is
vo
AV = = gmRL (15.8.16)
vi
$'
Figure 15.50 Inverting and non-inverting OTA amplifier configurations
Similarly, the voltage gain of inverting configuration can be derived as

vo
Av = = gmRL (15.8.17)
vi
Example
Determine the component values connected to the OTA amplifier shown in Fig. 15.50 in inverting
configuration to restrict the input bias current to the value IR = 20 mA for VCC = |VEE| = 10 V and
AV = 10. Here, VC = 0 in circuits shown above.
VEE - VBE 10 - 0.7 14.3
RR = = = = 0.715 MW
IR 20 m A 20 mA
gm = 20IR = 20 ¥ 20 mA = 400 mS
Av 10
RL = = = 25 KW
gm 400 mS
It would be reasonable to assume that the output voltage of the LM3080 would vary ±14 V for a load
of 25 KW. This suggests that the OTA must source a load current of ±14/25 K = ±560 mA. On the
contrary, the characteristic of the OTA LM3080 indicates that it would sink or source only ±350 mA
of current. Hence, in all probability it would not produce the designed value of output voltage swing of
±14 V. It would be appropriate to reduce the load current by increasing the load resistance from 25 KW
to 40 KW. This means RR must be increased to decrease IR and gm to maintain the required voltage gain
of 10.
15.8.10 Applications of OTA

The simplest example of OTA application is the amplitude modulator shown in Fig. 15.51. The modulating
signal and carrier voltages are defined as
v m = Vm sin wmt (15.8.18)
vc = Vc sin wct (15.8.19)
$'!
The OTA in Fig. 15.51 is basically in the non-inverting mode. Its transconductance is determined by
RR. The output voltage, with modulating voltage inactive, is given by Eqn. 15.8.16. With the introduction
of the modulating signal vm, the input bias current is the algebraic sum of IR and iR. Thus, the amplifier
bias current and the gain of the OTA varies around the Q-level set by RR.
Figure 15.51 OTA as modulator
The non-signal transconductance from Eqn. 15.8.13 is

gm0 = 20IR (15.8.20)
The time varying transconductance produced by varying modulating signal current iR is
gm = 20IR + 20iR = gm0 + 20iR (15.8.21)
The modulating current is expressed as
vm V
iR = = m sin wmt (15.8.22)
rr rr
20Vm
Hence, gm = gm0 + sin wmt (15.8.23)
rr
FG
v o = gmRLvc = gm 0 +
20Vm IJ
sinw m t RLVC sin wct
H rr K
20Vm
= gm 0 RLVC sin w C t + RLVC sin w m t sin w C t (15.8.24)
rr
20Vm RLVC 1
= gmoRLVC sin wct + {cos (wc wm)t cos (ws + wm)t} (15.8.25)
rr 2
$'"
Equation 15.8.25 is the output of an amplitude modulated signal with carrier frequency wC and side
bands wC wm and wC + wm.
Example
Obtain the expression of output voltage and sketch the frequency domain representation of the output
for components and modulating and carrier voltages given as RR = 100 K, rr = 50 K, R1 = R2 = 1 K, RL
= 40 K, Vin = 2 sin 2p ¥ 500t, and vC = 10 sin 2p ¥ 5000t.
12 - 0.7
IR = = 0.113 mA
100 K
Figure 15.52
gm0 = 20IR = 20 ¥ 0.113mA = 2.26 mS

vm 2
iR = = sin 2p ¥ 500t = 40 sin 2p ¥ 500t mA
rr 50 K
20Vm RLVC 1
v o = gm0RLVC sin wCt + {cos (wC wm)t cos (wC + wm)t}
rr 2
= 2.26 ¥ 40 ¥ 10 sin 2p ¥ 5000t
20 ¥ 2 ¥ 40 K ¥ 10
+ {cos 2p(5000 500)t cos 2p(5000 + 500)t}
50 K ¥ 2
= 904 sin 2p ¥ 5000t + 160 {cos 2p ¥ 4500t cos 2p ¥ 5500t}
15.8.11 Current to Voltage Converters

Figure 15.53 works as a current to voltage converter. The current IS in this circuit is introduced into the
inverting terminal of the op-amp, setting up an equal amount of current through the feedback resister
RF. Since, the voltage present between two input terminals of an op-amp is practically zero, the output
voltage Vo is
Vo = RFIF = RFIS (15.8.26)
It is clear from Eqn. 15.8.26 that the source current IS has been converted into the output voltage Vo.
The current to voltage converter is useful where a current is to be measured without introducing an
undesired resistance (ROF = 0) or where a current source such as photocell has a high shunt resistance.
$'#
Figure 15.53 Current to voltage converter
Example
A photodiode generates 0.2 mA/mW of radiant power for a constant reverse-bias voltage. Design a
circuit to measure radiant power with a voltmeter. If RF = 5 K and radiant power = 100 mW.
Solution
The voltmeter will read Vm = RFIR = 5 ¥ 103 (0.2 mA /mW) ¥ 100 mW) = 100 mV = 0.1 V.
The scale factor of the light meter is 1 mW/mV.
Figure 15.54 Photodiode lightmeter
The photo current could be allowed to flow through a resistance to develop a measurable voltage, but
this voltage would reduce the reverse bias and alter the photodiode characteristic. A circuit can be set up
as in Fig. 15.54. Since VI = 0 V there is no bias voltage change with change in ID.
15.8.12 Sample-hold Circuit

Sometimes it is essential to record the signal voltage at a particular instant of time and keep it constant
for a certain period. For example, when the analog voltage is directly connected to the input of an ADC,
the conversion process can be adversely affected if the analog voltage is changing during the conversion
time. A sample-and-hold circuit to hold the analog voltage constant while ADC conversion is taking
place can improve the stability of the conversion process. A simplified diagram of a sample-and-hold
circuit is drawn in Fig. 15.55.
$'$
Figure 15.55 Sample-and-hold circuit
The sample-and-hold circuit contains a unity-gain buffer amplifier A1 that presents a high impedance
to the analog signal VI and has low output impedance that can rapidly charge the hold capacitor C. The
capacitor will be connected to the output of A1 when digitally controlled switch (MOSFET) is closed.
This is called the sample operation. The switch will be closed long enough for C to charge to the current
value of the analog input. For example, if the switch is closed at the instant t = to, the output of A1 will
quickly charge C up to the voltage VI. When the switch is opened, C will hold this voltage so that the
output of A2 will feed this voltage to the ADC. The unity-gain buffer A2 presents high impedance that
does not allow to discharge the capacitor voltage appreciably during the conversion time of the ADC and
hence, the ADC essentially receives the dc input voltage VI. The duration of time for which the switch
remains closed is called the acquisition time and depends on the value of C and the characteristics of the
S/H circuit.
15.8.13 Logarithmic Amplifiers

It is well known that the voltage across a p-n junction is proportional to the logarithm of the current ID,
passing through the diode. The current through a diode for an applied voltage of VD is expressed as
ID = I O (eqVD / KT - 1) @ I O e qVD / KT , (15.8.27)
where IO = diode leakage current
qVD ID
or = ln (15.8.28)
KT Io
KT I D I
or VD = ln = VT ln D (15.8.29)
q Io IO
where, VT = 25 mV at room temperature.
In Fig. 15.56 a diode is connected between output and the inverting input terminal of the op-amp. Its
output voltage is proportional to the logarithm of the input voltage. Such an amplifier is called logarithmic
amplifier.
The inverting terminal is at virtual ground. Hence, the voltage across the diode is given by = VD = VO.
The voltage across the resister R is VI and the current through R = I1 = VI /R. The diode current ID is
now written as
$'%
ID = I1 = VI/R (15.8.30)
ID V V
VO = VD = VT ln = VT ln I = VT ln I (15.8.31)
IO RI O VR
where VR = RIO
Figure 15.56 Logarithmic amplifier with diode and BJT
It is clear from Eqn. 15.8.31 that the output voltage of the amplifier is proportional to logarithm of the
input voltage rather than proportional to the input voltage itself. For example, if the input voltage were
changed by a factor of 10, there is a linear change in VT volts in the output voltage. Here VT is sensitive
to temperature. This circuit works well for either fixed temperature or for very small change in temperature.
A better logarithmic amplifier is shown in Fig. 15.56 by replacing the diode by a transistor.
Figure. 15.57
A common base transistor has been put in the feedback path. Since the collector is held at virtual
ground and the base is already grounded, the transistors volt-amp characteristic becomes that of a
diode and is expressed as
$'&
Figure 15.58 Difference logarithmic amplifier
VI VO
I1 = IC = IE = + = I EO (eqVo KT - 1) , (15.8.32)
R AR
IC = IE, VCB = 0V, VBE = VO, A = very large @ 106. (15.8.33)
VI
Hence = I EO (eqVo KT - 1) = I EO eqVo KT , and as eqVo KT
>> 1 for positive Vo, (15.8.34)
R
or VR = RI EO e qVo KT
= RIO (IEO = IO) (15.8.35)
KT V V
or VO = ln I = VT ln I (15.8.36)
q IO R IO R
Assumption
The emitter-base junction is forward biased. This implies that for vi to be negative, vo is positive. The
output voltage is proportional to the logarithm of the input voltage. From Eqn. 15.8.36 it is clear that the
output voltage is temperature sensitive. The stable VR = IOR cannot be obtained. This can be avoided by
using difference amplifier circuit arranged in Fig. 15.58. This input voltage is applied to the input
terminal of the log amplifier and a reference voltage is applied to the input terminal the other log amplifier
as shown in this figure.The two transistors used in two log amplifiers are integrated close to each other
in the same wafer of the chip. This can ensure close matching of saturation current and provides good
thermal tracking.
As IEO = IO is dependent on temperature, VR = IED1R = IOR cannot be maintained constant. This
effect is avoided by connecting the output of one log amp to the inverting input of the difference amp
$''
and the output of the other log amp to the non-inverting terminal of the op-amp as shown in Fig. 15.57.
The input to the other log amp is the reference voltage VR. The outputs Vo1 and Vo2 are expressed as
KT V KT VR
vo1 = ln I , and vo2 = ln (15.8.37)
q IO R q Io R
KT V KT V
Hence vO 3 = vo2 vo1 = ln R + ln I
q IO R q IO R
KT V KT V V
= ln I ln R = VT ln I (15.8.38)
q IO R q IO R VR
The reference voltage in this equation can be set to a fixed value irrespective of replacement of the
transistor and temperature changes. However, vo1 is still proportional to the temperature T. This can be
balanced out by adding the fourth op-amp in the voltage follower mode. This voltage follower has the
temperature sensitive resistance RTC with positive temperature coefficient (sensistor) so that the slope
of the equation becomes constant with change in the temperature. The output Vo is expressed as
vo = 1 +
F I
R2 KT V R FG V
ln I = 1 + 2 VT ln I
IJ (15.8.39)
GH JK
RTC q VR RTC H VR K
15.8.14 Antilog Amplifier
A simple antilog amplifier circuit is drawn in Fig. 15.59. The input to the antilog amplifier is fed to the
base of T2 through temperature compensating voltage divider network using resistances R2 and RTC.
The output voltage VO is fed back to the inverting input terminal of the operational amplifier A1 through
resistor R.
VBE 1
VT VO
VO = RI1 = RIC1 = RIO exp and so, VBE1 = VT ln = V1 (15.3.40)
RI O
VR RTC
Similarly VBE2 = VT ln , VB2 = VI (15.3.41)
RI O RTC + R2
VB2 VBE2 V1 = 0
RTC V V V
or VI = VT ln R VT ln O = VT ln R
RTC + R2 RI O RI O VO
RTC V
or 0.4343 ¥ V1 = 0.4343 ¥ VT ln R
RTC + R2 VO
%
Fig. 15.59
or log
VR V
= 0.4343 ¥ I ¥
RTC
= KVI K =
FG
0.4343
¥
RTC IJ
VO VT RTC + R2 H VT RTC + R2 K
VR
or = 10 KVI
VO
or VO = VR 10 - KVI (15.3.42)
Equation 15.3.42 indicates that for increasing the input voltage by unity decreases the output by a
decade. The commercially available functional chip for anti-log amplifier is 755.
15.9 Precision Rectifier

The inherent potential barrier present across the diode does not become significant in rectifiers used for
converting ac to dc for higher ranges of voltage, i.e. in the range of voltage 5 V to 50 V or higher.
However, there are applications where very small voltage of the order of 100 mV has to rectified (in the
case of detection of RF signal). In such cases the voltage drop across the diode of 0.7 V cannot be
ignored as the RF signal is of the order of only 100 mV or so. Hence, it is not possible to employ
conventional rectifiers for such applications and circuits of precision rectifiers have been suggested for
such applications.
15.9.1 Superdiode Half-wave Rectifier

Our aim is to use a practical diode as an ideal diode with the help of an op-amp. The superdiode is a diode
having ideal characteristics. The scheme shown in Fig. 15.60 converts a practical diode to a superdiode
using an op-amp.
%
As VI starts increasing in the positive half-cycle, the output VA of the op-amp becomes increasingly
positive. Hence, diode is forward biased and starts conducting. The simplified circuit is shown to the
right side in Fig. 15.60. The relationship among voltages are written as
(VI VO) A = VA and VO + 0.7 V = VA
or (VI VO) A VA = 0, (VI VO) A VO 0.7 V = 0
or (1 + A)VO = AVI 0.7 V
AVI 0.7 V
Hence, VO = - @ VI (as A very large, typically 106)
1+ A 1+ A
Figure 15.60 Precision rectifier
Thus, the circuit in the positive half-cycle works as a voltage follower and output is exactly the same
as the input. The VA in negative half-cycle become negative, the diode does not conduct hence, no
voltage is developed across the load RL. Notice that the drop across the diode of the order of 0.7V as in
the case of conventional rectifier circuit does not appear here.
The circuit starts operating as soon as the VI increases by negligibly small amount of voltage equal to
diode drop divided by the open circuit gain of the op-amp. A straight-line transfer curve between Vo and
VI passing almost through the origin is obtained as indicated in Fig. 15.61. This arrangement makes the
circuit suitable for rectification of small voltage even in the range of mV.
Figure 15.61 Characteristic of superdiode and output of half-wave rectifier

%
15.9.2 Disadvantages
∑ When VI < 0, VO = 0, entire magnitude of the input voltage VI appears across the two input
terminals of the op-amp. If the magnitude of VI is more than few volts, the op-amp may be
damaged unless overload protection is present inside the op-amp. It is an essential feature for
any op-amp.
∑ When VI >> 0, the diode goes into saturation and bringing it back in the linear region takes some
time. This time delay will slow down the circuit operation and limit the frequency of operation
of the superdiode in half-wave rectifier.
The circuit of an inverting amplifier can be used as a half wave precision rectifier using two diodes
D1 and D2. Fig. 15.62 is the circuit of a half wave precision rectifier. In the positive half-cycle
(VI > 0 V), VA becomes negative that reverse biases diode D1 and forward biases diode D2. The forward
biased diode D2 closes negative feedback loop around the op-amp The virtual ground appears at the
inverting input terminal of the op-amp. The output VO is clamped at one diode drop below zero, i.e. VO
= 0.7 V. In the negative half-cycle (VI < 0), VA becomes positive that forward biases diode D1 and
reverse biases diode D2. The forward biased diode D1 closes negative feedback loop around the op-amp
through the feedback resistance RF. The virtual ground appears at the inverting input terminal of the op-
amp The current through negative feedback resistor RF is equal to the current through input resistor
R1, i.e.
VI V
I1 = = IF = O
R1 RF
VO R
or = F
VI R1
or VO = VI (for RF = R1)
The transfer curve is a straight line passing through the origin that falls in the second quadrant
indicating input voltage equal to the output voltage.
Figure 15.62 Precision half-wave rectifier

%!
15.9.3 Precision Full-wave Rectifier

The full-wave precision rectifier is also called absolute value circuit and its effective circuit are shown
in Fig. 15.63(a). In positive half-cycle input voltage, i.e. VI > 0 V, diode D1 conducts as VA becomes
negative and diode D2 is reverse biased in this figure.
2
VA =
RF R
VI and Vo = F VA =
RF FG IJ V I
R1 R1 R1 H K
Vo = VI (RF = R1)
In the negative half-cycle, i.e. VI < 0, VA becomes positive that reverse biases diode D1 and forward
biases diode D2. Now the effective circuit is drawn in Fig. 15.63(b).
Figure 15.63(a) Full-wave precision rectifier and its equivalent for positive cycle
Figure 15.63(b) Equivalent circuit of full-wave precision rectifier in negative half-cycle
We know that VI V1 = R1I1

Writing node equation at V1 node yields
VI V VA
+ A + =0
R1 R R1 + RF
%"
2VI + 2VA + VA = 0 (RF = R1 = R)

or VA = (2/3)VI
VO = (2/3)VI 1 +
FG 1IJ
= VI
H 2 K
Figure 15.63(c) Wave shape of precision full-wave rectifier
The wave shape of precision full-wave rectifier is drawn in Fig. 15.63(c).
15.10 Square Waveform Generation

We know that the output of the op-amp in the saturation region is limited to ±(VZ + VD) as shown in
Fig. 15.64. The forward drop across the diode is of the order of VD = 0.2 V and the Zener drop VZ is of
few volts, hence VZ > VD (VD = 0). The op-amp is forced into saturation region for square wave
generation as indicated in Fig. 15.64.
VO = ±VZ + VD as VD = 0.2V << VZ,
VO = ±VZ, b = R2 /(R1 + R2)
R2
VR = bVO = V = bVZ is fedback to the non-inverting terminal of the op-amp. It can assume
R1 + R2 O
value of ±bVZ. Whenever the voltage at negative input terminal exceeds the VR, switching takes place
resulting into square wave.
Let us assume an instant when the output voltage VO = +VZ. The capacitance now starts charging
with the voltage VO through R. The voltage at the non-inverting terminal at this moment of time is held
at +bVZ set by R1 and R2. This condition continues as the charge on the capacitor C rises until it just
exceeds the +bVZ (reference voltage). As soon as the voltage at the inverting terminal becomes just
more than the reference voltage (VR = +bVZ), the output is driven to VZ. The voltage at capacitor at this
instant of time is +bVZ. Now the capacitor C starts discharging through R towards VZ till it becomes
slightly more negative than bVZ. The output voltage switches more and more negative until its voltage
just exceeds bVZ. The output switches back to +VZ. This cycle repeats. The frequency is determined
by the time taken to charge the capacitor from bVZ to +bVZ and vice versa.
%#
Figure 15.64 Square wave generator
VC(t) = VF (VF Vi)et/RC (15.10.1)

where Vi = initial value of voltage on the capacitor = bVZ, and
VF = final value of voltage on the capacitor = +VZ.
Hence VC(t) = + VZ {VZ (bVZ)et/RC} = VZ{1 (1 + b)et/RC} (15.10.2)
At t = T/2 = T1, the voltage across the capacitor reaches the value of +bVZ and switching takes place.
Thus VC(T1) = +bVZ = +VZ 1 - (1 + b ) e - T1 / RC
o t
T1/RC
or +b = 1 (1 + b)e
T1/RC
or (1 + b)e =1b (15.10.3)
T1/RC 1+ b
or e = ,
1- b
or T1 = RC ln
FG 1 + b IJ = RC ln 1 + R 2 / ( R1 + R2 ) R + 2 R2
= RC ln 1 = RC ln 1 +
FG
2 R2 IJ
H1- bK 1- R 2 / ( R1 + R2 ) R1 HR1 K
= RC ln(1+ 2) = RC ln 3 (for R2 = R1) (15.10.4)
Equation 15.10.4 reveals that T1 is independent of VO. Since T1= T/2 (15.10.5)
Hence, the time period = 2RC ln 1 +

FG 2 R2 IJ = 2RC ln 3 (for R2 = R1) (15.10.6)
H R1 K
15.10.1 Triangular Wave Generator
Integrating the square wave generated in Fig. 15.64 one can generate the triangular wave shape. Let us
suppose that the voltage at the output of the comparator A1 is VO1 = +Vsat in Fig. 15.65. The output of
the integrator A2 will be a negative going ramp described mathematically as
%$
1
VO =
R1C1
z
VO1 dt (15.10.7)
Figure 15.65 Triangular wave generator
One of the ends of the voltage divider formed by R3 and R2 is connected to VO1 and the other end is
connected to the negative going ramp generated at the output of the integrator A2. At time t = T 1, when
the negative going ramp attains a value Vsat, the effective voltage at the junction a becomes slightly
less than 0V. This forces the comparator A1 to switch from positive saturation +Vsat to negative saturation
Vsat. During the time when the output of A1 is at Vsat, the output of A2 increases in the positive
direction. At the instant t = T2, the voltage at point a becomes just above 0V, thereby switching the
output of A1 from Vsat to + Vsat. The cycle repeats and generates a triangular wave shape. We see that
the frequency of square wave and triangular wave is the same. However, the magnitude of the triangular
wave depends on the RC value of the integrator A2 and the output voltage VO1 of A1. The output level of
A1 can be set to the desired level by using appropriate Zener diode(s).
The effective voltage at point a during the time when output of A1 is at +Vsat can be expressed as
R2
Va = Vramp + Vsat - (- Vramp )
n s (15.10.8)
R2 + R3
At t = T1, the voltage at point a becomes zero.
R2 R2
Hence Vramp + Vramp + Vsat = 0 (15.10.9)
R2 + R3 R2 + R3
- R2 - R3 + R2 R2
or Vramp + Vsat = 0
R2 + R3 R2 + R3
R2
or Vramp = Vsat (15.10.10)
R3
Similarly at t = T2, the output of A1 switches from Vsat to +Vsat. (15.10.11)
R2
Hence Vramp
R2 + R3
o d
-Vsat - + Vramp it = 0 (15.10.12)
%%
R2 R2
or Vramp Vramp - Vsat = 0
R2 + R3 R2 + R3
R3 R2
or Vramp = Vsat
R2 + R3 R2 + R3
R2
or Vramp = Vsat (15.10.13)
R3
2 R2
The peak to peak amplitude of triangular voltage = Vo(pp) = Vramp (Vramp) = Vsat
R3
The output voltage of the comparator switches from Vsat to +Vsat in half time period t = T/2.
Substituting this value of time in the basic equation of integration we get
T /2
VO(pp) =
1
z (Vsat ) dt =
1 T FG IJ
Vsat (15.10.14)
R1C1
0
R1C1 2 H K
Hence, time period T=
FG V IJ (2R C ) = RS(2 R R )V UV(2R C ) = 4R R C
O(pp)
1 1
2 3 sat
1 1
1 2 1
(15.10.15)
HV K
sat T V W sat R 3
15.10.2 Monostable Multivibrator

The word mono means one. Hence, the monostable multivibrator has only one stable state and a quasi-
stable state. The presence of a trigger pulse forces it to go to the quasi-stable state for a predetermined
interval of time T and comes back again to its stable state. The time T is independent of width of the
trigger pulse. Figure 15.66 shows the circuit and waveforms of monostable multivibrator.
Figure 15.66 Monostable multivibrator and its waveforms

%&
Let us assume that the circuit is in the stable state that prevails in the absence of trigger pulse and the
output of the op-amp is in the positive saturation voltage, i.e. Vmax = +VCC. The diode D1 conducts
through R. The point V is clamped to one diode drop (0.7V) above ground. The capacitor is charged to
VD1.
R3 R3
At this moment of time V+ =
R2 + R3
Vmax = b
R2 + R3
g
+ VCC = bVCC (15.10.16)
The stable state is maintained because b VCC is larger than VD1.

Now let us assume that the negative trigger pulse is applied directly at non-inverting terminal of
Fig. 15.66. After passing it through differentiator the negative edge of the pulse is coupled to the cathode
of diode D2 via capacitor C1. If the trigger pulse is of sufficient height to cause V+ to go below V, the
op-amp sees a net negative input voltage and its output voltage will switch to the negative saturation
output voltage Vmin = VCC. This in turn causes V+ to go negative to bVCC that keeps the op-amp in
this state. Now, D1 cuts-off isolating the circuit from further change at the trigger input.
The negatively saturated output voltage of the op-amp cuts-off diode D1 and the capacitor C starts
discharging exponentially to negative saturation output voltage VCC with time constant RC. The
monostable multivibrator is in its quasi-stable state and will prevail till the diclining V goes below the
voltage at V+ = bVmin = bVCC. At this moment, the output of the op-amp switches back to Vmax =
+VCC and the voltage V+ also goes back again to bVmax = + bVCC. The capacitor C now starts charging
towards positive saturation output voltage +VCC until diode D2 turns ON and the circuit returns back to
its stable state.
It is clear from Fig. 15.66 that the output produces a negative going pulse. The discharging of
capacitor C is expressed as
V_(t) = Vmin (Vmin VD1) et/RC = VCC (VCC VD1)et/RC (15.10.17)
At t = T, V_(t) = bVmin = bVCC = VCC (VCC VD1) e -T / RC
or (1 b )VCC = (VCC + VD1) e -T / RC
Hence, T = RC ln
FG 1 + V / V IJ = RC ln FG 1 IJ = RC ln FG
D1 CC 1 IJ
H 1- b K H1 - b K H 1 - R / (R
3 2 + R )K
3
= RC ln G
F R + R IJ = RC ln 2 = 0.693RC (R = R )
2 3
2 3 (15.10.18)
H R K 2
15.11 Analog Multiplier

An analog multiplier is a versatile functional device for applications like multiplication and division of two
signals, squaring of a signal, frequency doubling and shifting, phase angle detection, etc. Fig. 15.67 is a
symbolic representation of an analog multiplier. The output of the analog multiplier in Fig. 15.67 is
expressed as
Vx ¥ Vy
VO = (15.11.1)
VREF
%'
Normally, VREF is internally set to 10 V.

Vx ¥ Vy
Hence VO = (15.11.2)
10
Figure 15.67 Symbol of analog multiplier
As long as Vx and Vy < VREF, the amplifier does not saturate. Eqn. 15.11.2 can be described in
different quadrants as
∑ for Vx and Vy both being positive, the multiplier works as one quadrant multiplier.
∑ for Vx held positive and Vy swing positive and negative, the multiplier works as two quadrant
multiplier.
∑ for Vx and Vy both swinging positive and negative, the multiplier works as four quadrant multi-
plier.
A large number of techniques have been used to multiply two analog signals to conform to
Eqn. 15.11.1. One of the techniques used in log-antilog multiplier is based on well known mathematical
relationship that the sum of log of two numbers is equal to the log of product of those two numbers.
This can be illustrated by Fig. 15.68.
Figure 15.68 Symbol of analog multiplier
Figure 15.68 is set for one quadrant multiplication. The transconductance type multiplier is the four
quadrant multiplier. The AD533 and AD534 are multiplier IC chips available in the market.
15.11.1 Application of Multiplier: Frequency Doubling

Let us represent two sinusoidal signals with exactly same magnitude and frequency, but with a phase
difference between them as
%
v1 = Vx sin wt and v2 = Vy sin (wt + q) = Vy(sin wt cos q + cos wt sin q) (15.11.3)

Here, q is the phase difference between these two sinusoidal signals. When these signals are applied
to the inputs of four quadrant multiplier, its output is
vO = Vx sin wt ¥ Vy sin (wt + q) = Vx Vy(sin2wt cos q + sinw t(cos w t sin q)
VxV y
= (2 sin 2 w t cos q + 2 sin w t cos w t sin q )
2
VxV y
= {1 - cos 2w t ) cos q + sin 2w t sin q }
2
VxV y VxV y VxVy
= cos q - cos 2w t cos q + sin 2w t sin q
2 2 2
VxV y VxV y
= cos q +
(sin 2w t sin q - cos 2 w t cos q ) (15.11.4)
2 2
Equation 15.11.3 indicates that its first term has dc value and the second and the third terms are
double the frequency of the input signal.
15.11.2 Divider
The division process can be assumed as the complement of the multiplication process. Hence, a divider
can be realized by placing the multiplier element in the feedback path of the operational amplifier as
Vx -V Vy ¥ Vz
Ix = = and V =
R R VREF
Vy ¥ Vz Vx Vy ¥ Vz Vy ¥ VO
Hence, VX = V = , Ix = = =
VREF R VREF RVREF
VREF ¥ Vx
Thus VO =
Vy
15.11.3 Square Rooting

The square rooting is also achieved by connecting the multiplier in the feedback path of the operational
amplifier as shown in Fig. 15.69(b).
Vx V V V 2 / VREF
Ix + IF = + =0= x + z hence, Vz = VxVREF
R R R R
%
15.11.4 Power of Any Value

Sometimes the solution of differential equation requires the use of multipliers for generating any power
of any variable. The following circuits demonstrate how square and cube of any variable x can be
realized as in Fig. 15.69(c).
Figure 15.69(a) Analog divider
Figure 15.69(b) Square rooting
In order to avoid imaginary quantity to be generated, the input voltage must be positive.
Figure 15.69(c) Squaring of x
15.11.5 Cube Rooting

The any cube root of any variable can be obtained as illustrated in Fig. 15.70.
%
Figure 15.70 Cube root and fractional cube root
15.12 Filters
The history of classical theory of filters dates back to 1915. Those days electrical communication
networks and systems utilised filters in the form of coupled and tuned circuits until 1922, when Campbell
proposed a general approach to wave filter design. Subsequently, Zobell presented a better version of
wave filter design and his work on m-derived filter based on image parameters was published in 1923.
Since then a rapid development of new electronic component and design techniques led to many more
varieties of filtering methods and quite a few of them are used even today.
We all have used paper filter to separate the liquid from any solid suspension in it. In civil construction
we use wiremesh grid to separate a specified size of the material and reject the other types. The word
filter means a selective device that allows a desired size (range) of matter or energy to pass through it
while stopping all other sizes substantially. Thus, electric filter is a network that transmits a voltage of
desired frequencies with negligible attenuation in its magnitude and attenuates it appreciably for all other
frequencies.
The analogy of an electric filter can be made with the lint filter on an automatic dryer. It allows the air
(moisture) to pass through but traps the lint. Another example of filtering is in the fuel line filter of an
automobile. It traps the dirt particles present in the fuel and allows the gasoline to go to the carburettor.
Thus, by way of comparison, an electric filter will pass signal voltage of some frequencies and attenuate
the others. Here, we will restrict our discussions regarding active filters to the extent of analog filters
using resistors, capacitors, and op-amps. The most important disadvantages of active filters are gain-
bandwidth product and slew rate at high frequencies. There are many ways to define filters. One way of
defining filter is by range of frequencies that it selects or rejects. The common nomenclature of filters
are
∑ Low-Pass (LP)
∑ High-Pass (HP)
∑ Band-Pass (BP)
∑ Band-Reject (band-stop) (BRF)
∑ Notch
%!
Useful varieties of filters may include:

∑ Lumped LC filters
∑ Crystal and ceramic filters
∑ Mechanical filters, microwave filters
∑ Lumped and distributed active RC filters
∑ Switched capacitor filters
∑ Digital filters
The whole group of filters can broadly be divided into two categories:
∑ Passive filters
∑ Active filters
Design and fabrication techniques of passive filters are firmly based on the theory of insertion loss
with lumped parameters. The prime factor in favour of passive RLC network lies in the availability of
exact synthesis procedure to facilitate the design. But the excessive physical size at low frequencies
comes in the way of its incorporation in the large-scale system.
The best passive filter is the composite filter having the following:
∑ One or more sections of constant K-type filter to improve the attenuation well beyond cut-off
frequency
∑ One or more sections of m-derived filter to improve the attenuation characteristic just at the
cut-off frequency
∑ Two terminating half sections of m-derived filter (with m = 0.6 to be connected on either side)
to obtain constant match over the entire pass band
It is amply clear from above points that the best passive filter necessarily demands the use of a large
number of passive resistors, capacitors, and inductors. Hence, it occupies more space and weight and
becomes economically prohibitive. In addition, passive RC filters do not generate transfer functions
with quality factor Q more than half hence, cannot be used in high selectivity filters.
The stringent requirement of compact filtering exists at lower and sub-audio band of frequencies.
This can be achieved by replacing the passive inductors with active ones. Hence, a new approach to
inductorless filter design was advanced with vacuum tubes (as introduced active element) capacitors
and resistors in mid-thirties. These active RC filters could not gain popularity due to their bulky size,
high price and power consumption of vacuum tubes till the advent of BJTs in 1947. Initially attention
was given to novel circuit elements such as Negative-Impedance Converters (NICs) with BJTs and
their uses in the design philosophies strictly based on the use of discrete components. Linvills efforts
on inductorless filters in the year 1954 provided stimuli for the major breakthrough in the design theory
of active filters. In the subsequent year, Sallen and Key published a catalogue of 18-RC active filters,
each of them containing single amplifier. With the introduction of silicon monolithic operational amplifiers
op-amps in the commercial market use of active filters became an attractive proposition due to their
easy availability in monolithic integrated form as off-the-shelf item at low cost. Active filters became
more popular than passive filters because of the production of the cheap modular solid state op-amp.
The active filters are better than the passive filters in terms of price as well as performance. Good
quality active RC filters can be designed and built with resistors, capacitors and op-amp. The primary
%"
application of active RC filters still lies at low frequencies where inductors using magnetic core materials
are not suitable because of their bulky size, heavy weight, high cost, and low quality factor. The recent
trends in the design and synthesis technique of active RC filters are to use more than one active elements
in order to improve the system reliability, accuracy and performance.
Features of active RC filters in microelectronics form can be summarized as:
∑ Reduction in size, weight and power consumption (no passive inductors)
∑ Excellent isolation to prevent loading while cascading different sections of it
∑ Provide required gain
∑ Readily compatible with ICs as inductors are not present
∑ Can be tuned independently with minimal interaction
∑ Can generate Q as high as even few hundreds
Along with the above mentioned unique characteristics it has the following limitations:
∑ Different op-amps exhibit different frequency responses hence, design criteria differs for dif-
ferent op-amps.
∑ Unlike design of passive filters, it requires a dc power supply also.
15.12.1 Design Methods

The advent of Integrated Circuit (IC) technology has revolutionalised the design philosophies of active
RC filters. Synthesis procedures using op-amps can basically be classified as follows:
∑ Direct
∑ Cascaded forms
The desired filter transfer function in direct from of synthesis procedure is realized with active (op-
amp.) as well as passive (RC) elements as a single section of two port network similar to the realization
procedure of a passive filter. The realization method is very simple for lower order transfer functions
but as the order increases, complexity of RC network also increases, and it becomes quite cumbersome
to assess the sensitivity of transfer functions pole parameters w.r.t. variation in network elements.
Apart from these difficulties such types of realization techniques lead to increased value of sensitivity
figures. This leads to introducing techniques like coupled biquad, follow-the-leader-feedback, etc.
The overall transfer function of cascaded form of realization technique is broken into factors of
several sub-transfer functions of first and second order and each of them is realized separately. The
overall network is then obtained by cascading the individual sections together with proper isolations.
This technique suggests modular approach to design complicated filter networks and facilitates the post
design adjustments without any interaction among its different sections. The general second order
transfer function is commonly known as biquadratic equation and can be expressed as
N ( s) N ( s) N ( s)
T(s) = = = 2 (15.12.1)
D( s) S + aS + b
2 S + S (w p / Qp ) + w 2p
The biquadratic function in Eqn. 15.12.1 is characterised by two-system parameters
Pole frequency w p = (b)1/2, and (15.12.2)
%#
Pole quality factor Qp = (b)1/2/a (15.12.3)

The practicability of the design of active RC filter lies in the fact that it has high value of Q and
actually low Qp and wp sensitivities for variation in its active as well as passive parameters. The sensitivity
figure is an estimate of the effect of parameter variation on network function. Higher value of sensitivity
figure results in more variation in the transfer function for the corresponding change in related parameters.
Hence, its performance becomes poor. The sensitivity figures of the design parameter y w.r.t. change in
the element x is defined as
dy / y Ê x ˆ Ê ∂ y ˆ
S xy = = Á ˜ (15.12.4)
dx / x ÁË y ˜¯ Ë ∂ x ¯
The filter response is specified by its voltage transfer functions at different nodes in the circuit. The
typical frequency responses of LP, HP, BP, and BR filters are shown in Figs. 15.71.
Figure15.71 Active filters’ responses
The sharpness of cut-off between the pass and stop bands depends upon the order of the filter. A
higher order filter differentiates between these two-ranges of frequencies better than a lower-order
filter. The order of the filter is specified by the degree of the highest order frequency dependent term
present in the denominator of the voltage transfer function.
Here fo is also called the centre frequency whereas (fH fL) is called the bandwidth. The simple
example of a first order filter circuit is shown in Fig. 15.72.
(1/ SC) vi vi vi
v(+) = = = (15.12.5)
R + 1/ SC SCR + 1 CR( S + 1/ CR)
%$
Figure 15.72 First order LPF
R1vo
v() = (15.12.6)
RF + R1
v() = v(+) (15.12.7)
R1vo vi
v() = = v(+) = (15.12.8)
RF + R1 CR( S + 1/ CR)
vo 1 R + R1 Aw
= ¥ F = o H (15.12.9)
vi CR( S + 1/ CR) R1 S +wH
where wH =
1 R
, Ao = 1 + F
FG
1 IJ (15.12.10)
CR H
R1 CR K
Equation 15.12.9 is the standard form of the filter transfer function describing its low frequency gain
Ao and cut-off frequency wH. Equation 15.12.9 defines the first order filter as S (= jw), it is of the order
of unity. From its frequency response it is clear that the roll-off is 10db/decade and it will not give sharp
cut-off. As the order of the filter increases, the slope of the roll-off also increases and cut-off becomes
sharper to precisely differentiate between the cut-off and pass bands.
15.12.2 Biquad Realization

Various multiple feedback type circuits are available in the literature for realizing biquadratic voltage
transfer functions. Multiple feedback structures with two amplifiers are supposed to be superior to one
amplifier structure on account of sensitivity and lower gain requirements. Sedra et al. and Mitra et al.
have classified and compared a number of one and two or more op-amp based filter structures. The
number of filter structures are indeed large and only a few of them have been considered here for
comparison.
15.12.3 Sallen-Key Filters

The simplest and the oldest single amplifier single feedback structures go to the credit of Sallen and Key
as shown in Fig. 15.73.
%%
Figure 15.73 Sallen-Key structures
vo Yv
From left circuit of Fig. 15.73, = 2 1
K Y2 + Y5
v1 = 1 +
FG Y5 IJ FG v IJ
o
(15.12.11)
H Y2 K H KK
Writing nodal equation at node v1 yields
vo
viY1 = (Y1 + Y2 + Y4)v1 Y4vo Y (15.12.12)
K 2
Substituting the value of v1 from Eqn. 15.12.11 in Eqn. 15.12.12 yields
viY1 = (Y1 + Y2 + Y4) 1 +

FG IJ
Y5 v v
¥ o Y4vo o Y2
H Y2K K K
RS Y
= Y1 + Y2 + Y4 + (Y1 + Y2 + Y4 )
UFv I
- KY - Y V G J 5 o
T Y WH KK 2
4 2
v iY 1 Y 2
Fv I
= l(Y + Y ) Y + (Y + Y + Y ) Y - KY Y q G J o
1 4 2 1
H KK
2 4 5 2 4
v iY 1 Y 2
Fv I
= m(Y + Y )bY + Y g + Y (Y - KY )r G J o
1 4 2 5
H KK 2 5 4
vo KY1Y2
= (15.12.13)
vi (Y1 + Y4 )(Y2 + Y5 ) + Y2 (Y5 - KY4 )
From Eqn. 15.12.13 different types of filter functions can be realized.
Case I
For Y1 = Y2 = G and Y4 = Y5 = SC, Eqn. 15.12.13 yields as
%&
vo KG 2 KG 2
= = 2 2
vi (G + SC)(G + SC) + G (1 - K ) SC S C + 2SCG + G 2 + (1 - K ) SCG
K / C2 R2 Kw 2p
= = (15.12.14)
S 2 + S (3 - K ) / CR + 1 / C 2 R 2 S 2 + S (3 - K )w p + w 2p
1 wp 1
where wp = , Qp = = (15.12.15)
CR (3 - K )w p 3 - K
Equation 15.12.14 indicates second order voltage transfer function of low-pass filter. The circuit of
the low-pass active filter looks like the one shown in Fig. 15.74(a).
Figure 15.74(a) Circuits of low-pass filter
Figure 15.74(b) Circuits of high-pass filter
The sensitivities of wp and Qp can be obtained as

∂w p 1 ∂w p 1
= 2
, and = 2
∂R CR ∂C C R
%'
w
SR p =
F R I F ∂w I =FG - R IJ FG 1 IJ = 1
p
(15.12.16)
GH w JK GH ∂R JK H 1 / CR K H R C K
p
2
w
S C p = 1
∂ Qp ∂ Q p ∂Q p - 1*- 1
=0= , = ,
∂R ∂C ∂ K (3 - K ) 2
2
Q Ê K ˆ ∂ Qp
SK p = Á ˜ =
K FG IJ FG 1 IJ =
K
(15.12.17)
Ë Qp ¯ ∂ K 1 / (3 - K ) H K H 3- KK 3- K
Case II
If Y1 = Y2 = SC, and Y4 = Y5 = G are substituted in Eqn. 15.12.13 it yields
vo KS 2 C 2 KS 2
= 2 2 =
vi S C + ( 3 - K ) SCG + G 2 S 2 + ( 3 - K ) S / CR + 1 / C 2 R 2
KS 2 KS 2
= = (15.12.18)
S + (3 - K )w p S + w 2p
2 wp
S2 + S + w 2p
Qp
Equation 15.12.18 represents the second order voltage transfer function of a high-pass filter. Its
circuit is shown in Fig. 15.74(b).
v Y2
From right circuit of Fig. 15.73, - o = v1,
K Y2 + Y5
or v1 = 1 +
FG IJ
Y5 vo
(15.12.19)
H K
Y2 K
Writing nodal equation at v1 in the right side circuit of Fig. 15.73 yields
viY1 = (Y1 + Y2 + Y3 + Y4)v1 Y4vo +

FG v IJ Y
o
(15.12.20)
H KK 2
= (Y1 + Y2 + Y3 + Y4) 1 +
FG IJ
Y5 vo v
Y4vo + o Y2
FG IJ
H K
Y2 K K H K
viY1Y2 = { (Y1 + Y2 + Y3 + Y4)Y2 (Y1 + Y2 + Y3 + Y4)Y5 KY2Y4 + Y22}
FG v IJ
o
H KK
= {(Y1 + Y3 + Y4)(Y2 + Y5)(Y5 + kY4)Y2}
FG v IJ
o
H KK
%
vo - KY1Y2
= (15.12.21)
vi (Y1 + Y3 + Y4 )(Y2 + Y5 ) + Y2 (Y5 + KY4 )
Case III
If Y1 = Y2 = Y4 = G and Y3 =Y5 = SC are substituted in Eqn. 15.12.21 it yields
vo - KG 2 - KG 2
= = 2 2
vi (2G + SC) (G + SC) + G (SC + KG) S C + 3SCG + 2G 2 + SCG + KG 2
- K / C2 R2 - K / C2 R2
= 2 2 2 = (15.12.22)
S + 4S / CR + (2 + K ) / C R S + 4S / CR + w 2p
2
Equation 15.12.22 is the voltage transfer function of a low-pass filter.

2+ K
where wp =
CR
vo - Kw 2p / (2 + K ) - Kw 2p / (2 + K )
= = (15.12.23)
vi
S 2
F
+ 4S G
wp I +w 2 S2 + S
wp
+ w 2p
H J
2+KK
p Qp
wp 2 + K 2+ K
Qp = = (15.12.24)
4w p 4
Case IV
If Y1 = Y2 = Y4 = SC and Y3 = G = Y5 are substituted in Eqn. 15.12.21 it yields
vo - KS 2 C 2 - KS 2 C 2
= =
vi (2SC + G) ( SC + G) + SC (G + KSC) 2S C + 3SCG + G 2 + SCG + KS 2 C 2
2 2
- KS 2 C 2 - S 2 K / (2 + K )
= =
(2 + K ) S 2 C 2 + 4SCG + G 2 S 2 C 2 + 4 S / (2 + K )CR + 1 / C 2 R 2 (2 + K )
- {K /(2 + K )}S 2
= (15.12.25)
S 2 + 4 S /(2 + K )CR + w 2p
where w p = 1/CR 2 + K (15.12.26)

vo - {K /( 2 + K )}S 2 -{K /(2 + K )}S 2
= =
vi S 2 + 4S 4w p
ew p 2 + K + w 2p
j s2 + S + w 2p
(2 + K ) 2+ K
%
-{K /(2 + K )}S 2

= (15.12.27)
wp
S2 + S + w 2p
Qp
Equation 15.12.27 is the voltage transfer function of a high-pass filter.
wp 2+ K 2+ K
where Qp = = (15.12.28)
4w p 4
Case V
If Y1 = G = Y3 = Y5 and Y2 = Y4 = SC substituted in Eqn. 15.12.21 it yields
vo - KSCG
=
vi (2G + SC)(SC + G) + SC(G + KSC)
- KSCG
=
S C + 3SCG + 2G 2 + SCG + KS 2 C 2
2 2
- KSCG
=
(1 + K ) S C 2 + 4 SCG + 2G 2
2
-{ K /(1 + K ) CR}S
= (15.12.29)
S + 4S / CR(1 + K ) + 2 /(1 + K ) C 2 R 2
2
-{K /(1 + K )CR}S -{K /(1 + K )CR} S

= = (15.12.30)
4 wp
S2 + S + w 2P S2 + S + w 2P
(1 + K )CR Qp
1 2
where wp = (15.12.31)
CR 1 + K
vo -{Kw p 1 + K / 2 (1 + K )} S - Sw p {K /( 2(1 + K )
= =
vi
S2 + S
4 w p 1+ K F + w 2p S2 + S
I w p2 2
+ w 2p
1+ K 2
GH JK 1+ K
- Sw p K / 2(1 + K )
o t
= (15.12.32)
wp
S2 + S + w 2p
Qp
w p 1+ K 1+ K
where Qp = = (15.12.33)
2 2w p 2 2
%
Equation 15.12.32 is the voltage transfer function of a band-pass filter. Though Sallen and Key
schemes are not very good w.r.t. sensitivity figures, they became popular particularly for practical
circuits from the point of view of simplicity, requirement of op-amps. and passive components. These
structures employ either positive or negative feedback to realize the complex poles. Many types of single
amplifier active RC filter structures are available and it is really difficult to decide which one is superior.
Sensitivity figures can be taken as one of the measures to decide the quality of active networks. In this
aspect, amplifier gain contribution dominates the other sensitivity figures caused by temperature changes
because passive component sensitivities can be simplified by selecting precision resistors and capacitors
of equal and opposite temperature co-efficients.
A comprehensive comparison of the performance parameters, such as pole quality factor Qp and pole
frequency wp and its sensitivities alongwith the design equations of SK + and SK for low-pass (LP),
band-pass (BP) and high-pass (HP) can be studied at length as described in Eqns. 15.12.14, 15.12.27
and 15.12.32. It becomes clear from the study of sensitivity figures that low sensitivity structure (all
SK and BP of SK +) generally require high gain amplifiers. This requirement puts a limitation on the use
of low sensitivity network on the gain of the amplifier to be low because it may result in higher sensitivities.
In order to avoid the above shortcomings, Moschytz proposed the gain sensitivity product as a figure of
merit of single amplifier RC filters. The pole sensitivity of a single amplifier active RC filter can be made
zero if an infinite gain amplifier is used. But this pole sensitivity product has a non-zero value even if the
pole sensitivity is zero. Fujii suggested a method to realize the prescribed gain-pole sensitivity to deter-
mine the minimum absolute value of gain-sensitivity product.
15.12.4 State Variable Biquad

A number of schemes fall under the category of state variable multi-loop feedback filters. The pole
producing networks are independent of zeros of the biquad in these realization schemes and even Q and
wo can also be adjusted independently. In general, these complex transmission zeros can be realized by
two methods:
∑ Summation method
∑ Feedforward method
15.12.5 Summation Method

This technique is based on analog computer method of successive integration like KHN to produce LP,
BP and HP transfer functions which may suitably be summed as indicated in Fig. 15.75 to implement
generalized biquadratic functions.
- v1
The node voltage v2 = (15.12.34)
SC2 R2
Writing nodal equation at the inverting input terminal of the A1 op-amp yields
vi v1 v
+ + 3 =0 (15.12.35)
R4 R1 R3
(1 + SC1 R1 )
% !
Figure 15.75 Summation method for all types of filters
v1
v 3 = v2 = (15.12.36)
SC2 R2
vi v (1 + SC1 R1 ) v1
= 1
R4 R1 SC2 R2 R3
S 2 C1C2 R1 R2 R3 + SC2 R2 R3 + R1
= v1
SC2 R1 R2 R3
v1 SC2 R1 R2 R3
= 2
(15.12.37)
vi R4 S C1C2 R1 R2 R3 + SC2 R2 R3 + R1 )
(
1 1
S S
v1 C1 R4 C1 R4
= = (BP) (15.12.38)
vi 1 1 1
S2 + S + S2 + S + w 2p
C1 R1 C1C2 R2 R3 C1 R1
Equation 15.12.38 is voltage transfer function of band-pass filter.
F S
1 I
v2 F v v I F
2 1 1 IG C1 R4 JJ
= G ¥ J = G-
vi H v v K H SC R JK GG - S
1 i 2 2 2
+S
1
+ w 2p JK
H C1 R1
1
C1C2 R2 R4
= (LP) (15.12.39)
1
S2 + S + w 2p
C1 R1
Equation 15.12.39 represents the voltage transfer function of a low-pass filter.
% "
Writing nodal equation at the summing point of A4 yields

vo v v v
+ i + 1 + 3 =0 (15.12.40)
R8 R5 R6 R7
- SC2 R1 R2 R3
v1 = 2
vi (15.12.41)
R4 ( S C1C2 R1 R2 R3 + SC2 R2 R3 + R1 )
v1 - R1 R3vi
v 3 = v2 = = 2
(15.12.42)
SC2 R2 R4 ( S C1C2 R1 R2 R3 + SC2 R2 R3 + R1 )
v3 - R1 R3
or = 2
vi R4 ( S C1C2 R1 R2 R3 + SC2 R2 R3 + R1 )
Now, substituting Eqns. 15.12.41 and 15.12.42 in Eqn. 15.12.40 yields
vo v SC2 R1 R2 R3vi
= i 2
R8 R5 R4 ( S C1C2 R1 R2 R3 + SC2 R2 R3 + R1 ) R6
R1 R3vi
2
R4 ( S C1C2 R1 R2 R3 + SC2 R2 R3 + R1 ) R7
vo R R R S 2 C1C2 R1 R2 R3 + SC2 R2 R3 R7 ( R4 R6 - R1 R5 ) + R1 R6 ( R4 R7 - R3 R5 )
= 4 6 7
R8vi R4 ( S 2 C1C2 R1 R2 R3 + SC2 R2 R3 + R1 ) R5 R6 R7
S2 + S
FG 1 IJ FG1 - R R IJ + FG 1 IJ FG1 - R R IJ
1 5 3 5
vo FR I
= -G J 8 HC R K H R R K HC C R R K H R R K
1 1 4 6 1 2 2 3 4 7
(15.12.43)
vi HR K 5 2
S + SG
F 1 IJ + FG 1 IJ
HC R K HC C R R K
1 1 1 2 2 3
2 F 1 IJ FG1 - R R IJ + w FG1 - R R IJ
1 5 2 3 5
vo
=-
R8 FG IJ S + SG
HC R K H R R K H R R K
1 1 4 6
p
4 7
(15.12.44)
vi R5 H K 2
S + SG
F 1 IJ + w 2
p
HC R K 1 1
1
1 C1C2 R2 R3 C1 R1
where wp = , Qp = = (15.12.45)
C1C2 R2 R3 1 / C1 R1 C2 R2 R3
S2 + S
wp FG1 - R R IJ + w FG1 - R R IJ
1 5 2
p
3 5
vo R
= 8
FG IJ Qp H RRK H RRK
4 6 4 7
(15.12.46)
vi R5 H K S2 + S
wp
+ w 2p
Qp
% #
Equation 15.12.46 can be used to generate different types of filter function under different condi-
tions.
Case I
With R1R5 = R4R6, R3R5 = R4R7, and R8 = R5, Eqn. 15.12.46 reduces to
vo S2
= (HP) (15.12.47)
vi wp
S2 + S + w 2p
Qp
Equation 15.12.47 is the voltage transfer function of a high-pass filter.
Case II
With R1R5 = 2R4R6, R8 = R5, and R7= • (open), Eqn. 15.12.46 reduces to
wp wp
S2 + S b1 - 2g + w 2
p S2 - S + w 2p
vo Qp Qp
=- = (all-pass) (15.12.48)
vi 2
wp wp
S +S + w 2p 2
S +S + w 2p
Qp Qp
Equation 15.12.48 is the voltage transfer function of all-pass filter.
Case III
when R1R5 = R4R6, R8 = R5, and R7 = • (open) are set in Eqn. 15.12.46, it reduces to
vo S 2 + w 2p
= (Notch) (15.12.49)
vi wp
S2 + S + w 2p
Qp
Equation 15.12.49 represents the voltage transfer function of a notch-filter.
Moustakas et al. offered an alternative to KHN circuit by realizing an RLC prototype BP filter function
through active means. The output of this prototype is then integrated and differentiated to generate LP
and HP second order voltage transfer functions. Apart from novelty, this modular approach has three
sections, each of them performing specific transfer functions without sacrificing its performance with
additional advantage of reduced element counts. Similarly, local positive feedback has been applied to
optional blocks to achieve high-Q and reduced element counts. This freedom is simply not available in
KHN circuit.
The other circuit to obtain the LP, HP and BP filter using Kerwin-Huelsman-Newcomb (KHN) biquad
is shown in Fig. 15.76.
% $
Figure 15.76
Writing node equation at non-inverting terminal of A1 yields

v + - vi v - v+
= BP (15.12.50)
R3 R4
or
FG 1 + 1 IJ v = FG R + R IJ v 3 4
=
vi v
+ BP
HR R K H R R K
3 4
+
3 4
+
R3 R4
or, v+(R3 + R4) = vBP R3 + viR4 (15.12.51)
Multiplying both sides by (R5 + R6) Eqn. 15.12.51 becomes
v+(R3 + R4)(R5 +R6) = vBPR3(R5 + R6) + viR4(R5 + R6) (15.12.52)
Similarly, writing node equation at inverting terminal of A1 yields
v- - v LP v - v-
= HP (15.12.53)
R5 R6
FG 1 + 1 IJ v = FG R + R IJ v5 6
=
v HP v LP
+
HR R K H R R K
5 6
-
5 6
-
R6 R5
v(R5 + R6) = vLP R4 + vHP R5 (15.12.54)

Multiplying both sides by (R3 + R4) Eqn. 15.12.54 becomes
v(R5 + R6)(R3 + R4) = vLP R4(R3 + R4) + vHP R5(R3 + R4) (15.12.55)
Since, LHS of Eqns. 15.12.52 and 15.12.55 are the same, equating these equations yield
v BP R3 ( R5 + R6 ) + vi R4 ( R5 + R6 ) = v LP R4 ( R3 + R4 ) + v HP R5 ( R3 + R4 )
or vBPR3(R5 + R6) + vLP R4(R3 + R4) + vHP R5(R3 + R4) = viR4(R5 + R6) (15.12.56)
v HP v v
Also vBP = , vLP = BP = 2 HP (15.12.57)
SC1 R1 SC2 R2 S C1C2 R1 R2
% %
Hence, vHP = S2C2C1R2R1vLP and vBP = SC2R2vLP (15.12.58)

Substituting from Eqn. 15.12.58 into Eqn. 15.12.56 yields
or vi R4 ( R5 + R6 ) = - v BP R3 ( R5 + R6 ) + v LP R4 ( R3 + R4 ) + v HP R5 ( R3 + R4 )
= [ S 2 C1C2 R2 R1 R5 ( R3 + R4 ) + SC2 R2 R3 ( R5 + R6 ) + R4 ( R3 + R4 )]v LP
v LP R4 ( R5 + R6 )
or = 2 (15.12.59)
vi S C1C2 R1R2 R5 ( R3 + R4 ) + SC2 R2 R3 ( R5 + R6 ) + R4 ( R3 + R4 )
v BP v v
= LP ¥ BP
vi vi v LP
R4 ( R5 + R6 )( - SC2 R2 )
= 2
(BP) (15.12.60)
S C1C2 R1R2 R5 ( R3 + R4 ) + SC2 R2 R3 ( R5 + R6 ) + R4 ( R3 + R4 )
v HP v v
= LP ¥ HP
vi vi v LP
R4 ( R5 + R6 )(S 2 C1C2 R1R2 )
= (HP) (15.12.61)
S 2 C1C2 R1R2 R5 ( R3 + R4 ) + SC2 R2 R3 ( R5 + R6 ) + R4 ( R3 + R4 )
15.12.6 Feed Forward Method

In this approach, the input voltage is fed forward to various nodes of pole producing networks to
generate the required transmission zeros and hence named feed-forward method. A number of such
types of circuits have been suggested and one of them is drawn in Fig. 15.77.
Figure 15.77 Feed forward topology
Writing nodal equation at inverting input terminal of A3 yields

vo v
+ i + SC2 v2 = 0 (15.12.62)
R2 R6
% &
vo vi
v2 = (15.12.63)
SC2 R2 SC2 R6
Writing nodal equation at inverting input terminal of A1 yields
vi v v
+ 1 (1 + SC1 R1 ) + 2 = 0 (15.12.64)
R4 R1 R3
R1 R1
v1 = vi v2 (15.12.65)
(1 + SC1R1 ) R4 (1 + SC1 R1 ) R3
Also writing nodal equation at the inverting input terminal of A2 yields
vi v v
+ 1 + o =0 (15.12.66)
R5 R7 R8
R8 R
vo = vi 8 v1 (15.12.67)
R5 R7
Combining Eqns. 15.12.63, 15.12.65 and 15.12.67 yields
vo =
FG R IJ v + FG R IJ R v + FG R IJ R v
8
i
8 1
i
8 1
2
H R K H R K (1 + SC R ) R H R K (1 + SC R ) R
5 7 1 1 4 7 1 1 3
F R I F R I R v + FG R IJ R RS v
8
= G J v + G J i
8 1
i
8 1 o

vi UV
H R K H R K (1 + SC R ) R H R K (1 + SC R )R T SC R
5 7 1 1 4 7 1 1 3 2 2 SC2 R6 W
v +G J
o
F R I R FG v IJ
8 1 o
H R K (1 + SC R ) R H SC R K
7 1 1 3 2 2
F R I F R I R v FG R IJ R FG v IJ
8
= G J v +G J i
8 1 i 8 1 i
H R K H R K (1 + SC R )R H R K (1 + SC R )R H SC R K
5 7 1 1 4 7 1 1 3 2 6
2
R7 ( S C1C2 R1 R2 R3 + SC2 R2 R3 ) + R1 R8
vo
(1 + SC1 R1 ) SC2 R2 R3 R7
S 2 C1C2 R1 R3 R4 R6 R7 + SC2 R3 R6 R4 R7 1 -
FG R1 R5 IJ
+ R1 R4 R5
= R8
H R4 R7 K vi
(1 + SC1 R1 ) SC2 R3 R4 R5 R6 R7
C1C2 R1 R2 R3 R7 S 2 + S
RS C2 R2 R3
+
R1 R8 UV
T C1C2 R1 R2 R3 C1C2 R1 R2 R3 R7 Wv o
R2
RS
C1C2 R1 R3 R4 R6 R7 S 2 + S
1 RRFG
1- 1 5 +
R1 R4 R5IJ UV
= R8
|T C1 R1 H
R4 R7 K
C1C2 R1 R3 R4 R6 R7 |W v
i
R4 R5 R6
% '
RS
R2 S 2 + S
1
+
R8 UV S2 + S
1 RR FG
1- 1 5 +
R5 IJ
T C1 R1 C1C2 R2 R3 R7 Wv o = R8
C1 R1 R4 R7H C1C2 R3 R6 R7
vi
K
R2 R5
RSS 2
+S
1
+
R8 FG IJ R|SS + S 1 FG1 - R R IJ + R U|V v
R
vo = 8
UV 2 1 5 5
i
T C1 R1 C1C2 R2 R3 R7 H K |T C R H R R K C C R R R |W
R5 W 1 1 4 7 1 2 3 6 7
1 F
2 RR I R 1 5 5
S +S G 1- J +
vo F R
= G J
I
8
C R H R R K
1 1 C C R RR 4 7
(15.12.68) 1 2 3 6 7
vi HR K S +S 1 + R
5 2 8
C1 R1 C1C2 R2 R3 R7
S2 + S
wp FG1 - R R IJ + R FG R R IJ
1 5 8 2 5
=
FG R IJ
8
Qp H R R K CC R R R HR R K
4 7 1 2 2 3 7 6 8
(15.12.69)
HR K
5 2
S +S
wp
+ w 2p
Qp
S2 + S
wp FG1 - R R IJ + w FG R R IJ
1 5 2
p
2 5
FR I
= G J 8
Qp H R R K HR R K
4 7 6 8
(15.12.70)
HR K 5 S +S2 wp
+ w 2p
Qp
R8
where wp = , Qp= wpCR (15.12.71)
C1C2 R2 R3 R7
Equation 15.12.70 is also capable of generating all types of voltage transfer functions.
The second order state variable schemes are not suitable for realizing high-Q and high frequency
poles due to finite gain-bandwidth product of the op-amp. Introducing a real negative pole p far away
from the existing complex poles can eliminate the effect of finite gain-bandwidth. Addition of a real
negative pole changes the second order system to third order system whose transfer function can be
expressed as
N ( s) N ( s)
T(s) = 2
= 3
( S + aS + b )(S + p) ( S + kS 2 + mS + n)
15.13 Simulated Inductance Approach

The interest in the field of active filters using simulated inductances was evoked with Orchards
observations on the inherent low-sensitivity feature of resistively terminated LC ladder filter. In addition
to low-sensitivity, this approach offers the extra advantage of tunability simply by means of trimmer
capacitors. The simplest way of using inductorless filter is to design a passive RLC filter strictly based
on the conventional methods and then replace each passive inductor by simulated ones. Such scheme is
%!
simple because LC filters are available. Different methods for simulating inductances are being reviewed
briefly along with an example of using active RC filter with simulated inductance.
Any one of the following active elements can achieve simulation of inductance:
∑ Negative Impedance converter (NIC)
∑ Gyrator
∑ DVCCS/ DVCVS
∑ Current conveyor (CC II)
The role of NICs in the design of active filters is more academic and historical in nature than practical.
It was popular during the initial phase of active synthesis development technique. Its lesser use may be
attributed to:
∑ The high sensitivities to active as well as passive parameters of the configuration
∑ Its relative inconvenience for fabrication as a monolithic chip
Active elements such as NICs and controlled sources are not commercially available in the integrated
form like Op. Amp. However, schemes suitable for using some of these elements in the integrated forms
have been reported and one of them is an active gyrator. The active gyrator evoked considerable amount
of interest from the point of view of design and application in the field of inductorless filters. If an ideal
gyrator is capacitively terminated at one of its ports, it realizes an inductance at the other port.
Simulation of inductance values far in excess of conventional coil values can be achieved by gyrator
that simplifies the practical aspects of synthesis particularly at very low frequencies. Even at high
frequencies, a higher quality factor can be attained as the realized inductance does not suffer from skin
effect and core losses. The basic Riordan circuit for the simulation of active inductor in the form of
active gyrator with op-amp is shown in Fig. 15.78.
The circuit of Fig. 15.78 can now be analyzed for its input impedance as
v i = v2 = v4 (15.13.1)
(vi v1) = Z1i1 = Z1i (15.13.2)
(v2 v1) = (vi v1) = Z2i2 = Z2i3 = Z1i (15.13.3)
(v2 v3) = (v4 v3) = Z3i3 = Z4i4 (15.13.4)
v 4 = vi = Z5i5 = Z5i4 (15.13.5)
Figure 15.78 Active gyrator (Riordan circuit)

%!
FG
v i = Z5i4 = Z5 -
Z3IJ FGZ IJ Z
i3 = Z5 - 3 i2 = Z5 - 3
FG IJ FG - Z IJ i
1
(15.13.6)
H Z4 K HZ4 K Z4 H KH Z K 2
vi ZZ Z
Zin = = 1 3 5 (15.13.7)
i Z2 Z 4
1
If Z1 = Z3 = R = Z4 = Z5, and Z2 = are substituted in Eqn. 15.13.7, then
jw C
Zin = jw CR2 (15.13.8)
Figure 15.78 realizes a pure (loss less) inductance and the value of the realized inductance L = CR2.
Differential voltage controlled current source (DVCCS) is another active element that is used to
simulate inductance basically in the form of gyrator. A relatively newer active element, the second
generation current conveyor (CC II) has been introduced in the recent past to realize both floating as
well as grounded inductors.
Example
The use of simulated inductance in active RC filter design can be exhibited by an example of notch filter
shown in Fig. 15.79. This is the conventional method of designing a notch filter with a lossy inductor.
Passive elements C, L and R1 form a series resonant circuit between the non-inverting input terminal of
the op-amp and ground. At resonant frequency, also called centre frequency, the capacitive impedance
is equal and opposite of the inductive impedance and the net resonant impedance reduces to minimum
value of R1. Consequently the input and output voltages in Fig. 15.79 also reduces to the minimum value
(zero). For the resonant frequency to be 50 Hz, the value of inductor required with C = 0.2 mF is 50 H,
such a large value of good quality passive inductor can hardly be thought of; but simulation in excess of
this value of inductance is not at all difficult. An inductor L alongwith R1 in series can be simulated as a
lossy inductor using Fig. 15.80.
Figure 15.79 Notch filter

%!
Figure 15.80 Lossy inductor simulation
vi R2 SC2 R2 vi
v= = (15.13.9)
R2 + 1/ SC2 1 + SC2 R2
vi - v v {1 - SC2 R2 /(1 + SC2 R2 ) vi
ii = = i = (15.13.10)
R1 R1 (1 + SC2 R2 ) R1
vi
Zin = = R1(1 + SC2R2) = R1 + SL,
ii
where L = C2R2R1 (15.13.11)
Equation 15.13.11 simulates a lossy inductor, which can be used in the circuit of Fig. 15.79 to realize
a notch filter function.
The voltage at non-inverting terminal v(+) of Fig. 15.79 is written as
( S 2 LC + SCR1 + 1) vi
v+ = (15.13.12)
S 2 LC + SC( R1 + R5 ) + 1
Writing node equation at the inverting input terminal of the Op. Amp. yields
(G3 + G4) v() G3vi G4v0 = 0 (15.13.13)
Substituting for v(+) {as v(+) = v()} from Eqn. 15.13.12 yields as
( S 2 LC + SCR1 + 1) vi
(G3 + G4) - G3vi = G4vo
S 2 LC + SC ( R1 + R5 ) + 1
( R + R4 ) ( S 2 LC + SCR1 + 1) - {S 2 LC + SC ( R1 + R5 ) + 1} R4
vi = R3vo
S 2 LC + SC( R1 + R5 ) + 1
( S 2 LC + SCR1 + 1) R3 - R4 R5 S 2 LCR3 + SC( R1 R3 - R4 R5 ) + R3

R3 v o = =
2
S LC + SC ( R1 + R5 ) + 1 S 2 LC + SC ( R1 + R5 ) + 1
%!!
ÊR R R ˆ
S 2 + SC Á 1 - 4 5 ˜ +
1 R R R
S 2 + SC 1 1 - 4 5 +
FG1 IJ
vo
=
Ë L R3 L ¯ LC
=
L R3 R1 H
LC K (15.13.14)
vi Ê R
S 2 + SC Á 1
+ R 5ˆ
+
1 R
S 2 + SC 1
+ R5 FG+
1 IJ
Ë LC ˜¯ LC LC H LC K
S 2 + 2 d1w1S + w12 S 2 + Sw1 / Q1 + w12
= = (15.13.15)
S 2 + 2 dw 0 S + w o2 S 2 + Sw o / Q + w o2
1 w R + R5
where, wo = = w1, o = 1 (15.13.16)
LC Q L
Q=
woL
=
L
=
1 F LI (15.13.17)
( R1 + R5 ) ( R1 + R5 ) LC ( R1 + R5 ) GH C JK
For R1R3 = R4R5, Eqn. 15.13.14 reduces to
S 2 + SC
R1 R RFG
1- 4 5 +
1 IJ 1
L H
R3 R1 LC KS2 +
vo LC
= = (15.13.18)
vi 2
S + SC
FG
R1 + R5
+
1 IJ2
S + SC
R1 + R5
+
1 FG IJ
H
LC LC K LC LC H K
Sensitivity of Q1 and w1 are found as
Ê L ˆ Ê ∂ Qˆ
S LQ = Á ˜ Á =
L FG IJ
1
¥
1
=
1 1 ( L / C )1/ 2
¥ ¥
Ë Q ¯ Ë ∂ L ˜¯ H K
Q ( R1 + R5 ) C 1/ 2 2 L1/ 2 Q 2 R1 + R5
Q 1
= = (15.13.19)
2Q 2
1 - R1 - R5
S LQ = = S CQ , S Q = ,S Q = ,
2 R1 R1 + R5 R5 R1 + R5
w 1 w
SL o = = SC o (15.13.20)
2
15.13.1 Frequency Dependent Negative Resistance Approach

The basic idea behind this approach lies in transforming a passive RLC filter into an equivalent two port
network after rationalizing the impedance of each passive element by a frequency dependent impedance
1
which may be of the form S or . After scaling, a new network is obtained by converting an inductance
S
K
to a resistance, a resistance to a capacitance and a capacitance to an impedance of the form 2 . This
S
K
new element which has the impedance form of 2 is known as Frequency Dependent Negative Resist-
S
%!"
ance (FDNR). The effect of such a transformation is to eliminate the inductors and create a new but
topologically equivalent network which includes FDNRs. The impedance transformation gives rise to
S2-impedance term and S2 admittance term. The terminal relationship for S2 impedance is
v
= S 2D
Z(s) = (15.13.21)
i
Similarly, for S2 admittance element it is
i 1
Y(s) == (15.13.22)
v DS 2
In order to distinguish between circuit elements with impedance proportional to S2 and 1/S2, the
terminology FDNR and FDNC are used respectively. An FDNR is symbolically represented by
twocapacitors as shown in Fig. 15.81(a). At real frequencies, it represents a second order capacitor also
called supercapacitor. Its impedance is defined as
B 1
= 2
Z(s) = (15.13.23)
S w D
where, D is frequency invariant and has unit of Farad.
Figure 15.81(a) FDNR filter
It is evident from Eqn. 15.13.23 that Z(s) is real negative quantity and is the function of frequency.
Hence, the term Frequency Dependent Negative Resistance (FDNR) seems to have achieved the universal
adoption.
The basic Riordan circuit of Fig. 15.78 can be used for attaining FDNR if Z2 and Z4 are chosen as
capacitors and Z1, Z3 and Z5 as resistances. With these substitutions, Fig. 15.78 attains an input impedance
as
Zin(jw) = w2C2R3 (15.13.24)
A slightly different version of FDNR can be obtained by choosing Z1 and Z3 or Z1 and Z5 or Z3 and
Z5 as capacitors and rest of the impedances as resistors. Under such conditions
Yin(jw) = w2C2R (15.13.25)
Since Eqn. 15.13.25 has the dimension of a conductance it is called Frequency Dependent Negative
Conductance.
%!#
The use of op-amp in the extended frequency range (beyond 3 dB frequency) is the present trend to
improve the high frequency performance of active filters. The gain of the actual amplifier is not infinite
and is frequency dependent except at very low frequency (below 10 Hz). Finite input and output
impedances further characterize a practial op-amp. Neglecting the frequency dependent amplifier gain in
the design of active filters can lead to serious accuracy, sensitivity and stability problems which usually
restrict the filter performance to low-Q and low frequency operations.
The frequency dependent dominant pole roll-off characteristic of an op-amp. can mathematically be
represented as
Aow o B
A(s) = = (15.13.26)
S +wo S +wo
where A o = open loop dc gain of op-amp
w o = 3 dB frequency of op-amp and
B = Aowo= the gain-bandwidth product of op-amp
If the frequency range of interest is considerably higher than the 3 dB frequency, then
B
A(s) = (15.13.27)
S
Frequency dependent model of the actaul op-amp. was explicity implemented in the analysis resulting
in active R filters suitable for medium Q and high frequency applications. Rao and Srinivasan eliminated
one capacitor in the active realization of second order band pass filter. In addition to lower sensitivities,
such a scheme is more suitable for integration because of reduced number of capacitance. Singh reported
a second order low-pass filter using only one op-amp, one resistance and one capacitance. Shifting the
position of R in between the output and inverting terminal of the op-amp can modify Singhs circuit as
indicated in Fig. 15.81(a). This circuit realizes both LP and notch filter functions. Writing equation at
node v1 as
(vi v1)SC =
bv - v g
1 0
R
or, SCRvi = (1 + SCR)v1 v0 (15.13.28)
Also, (vi v1)

FG A w IJ 0 0
= (vi v1)
FG B IJ = v 0
HS +w K 0 HS +w K
0
or,
F BI
(v v ) G J = v0 (15.13.29)
i
H SK
1
B
Now, SCRvi = (1 + SCR)v1 v0 = (1 + SCR)v1 (vi v1)
S
FG BI
Jv
= 1 + SCR + vi
B
H SK 1
S
or,
FG SCR + B IJ v = FG1 + SCR + B IJ v
H SK Hi
SK 1
%!$
v1 S 2 CR + B S 2 + B / CR
or, = 2 = 2
vi S CR + S + B S + S / CR + B / CR
S 2 + w 20
= (Notch Filter) (15.13.30)
S 2 + Sw 0 / Q + w 20
B w0 B
where, w0 = and Q = = w0CR = CR = BCR
CR 1/CR CR
i = (vi v1)SC = vi -
RS S 2 CR + B
vi SC
UV
T S 2 CR + S + B W
=
RS S CR + S + B - S CR - B v UVSC
2 2
2 i
T S CR + S + B W
=S
R S v UV SC = S C v i
2
2 2 i
T S CR + S + B W S CR + S + B
vi 1 B
Hence, = R+
Zi = + 2 (15.13.31)
i SC S C
The equivalent circuit in Fig.15.81(a) represents Eqn. 15.13.31. The output voltage from the equiva-
lent circuit of Fig. 15.81(a) yields as
B / S 2C B
Now, v0 = vi = 2 vi
1 B S CR + S + B
R+ + 2
SC S C
B / CR w 20
= vi = vi
S 2 + S / CR + B / CR S 2 + S w 0 / Q + w 20
b g
v0 w 2O
or, = 2 (LP Filter) (15.13.32)
vi S + S w o / Q + w O2
b g
The circuit of Fig. 15.81(a) is now modified as Fig. 15.81(b) and from this circuit
Figure 15.81(b)
%!%
(v1 v0)SC =
bv - v g
i 1
R
or, vi v1 = SCR(v1 v0)
or, vi = (1 + SCR)v1 SCRv0
(v1 v0)
FG B IJ = (v v ) FG B IJ = v
HS +w K 0
HSK
1 0 0
or,
F S I F S + B IJ v
v = G1 + J v = G
H BK H B K
1 0 0
0
F B IJ SC = v FG S IJ SC = v S C
i = (v = v ) SC = v G 1 -
1 1 1 1
2
H S + BK H S + BK S+B
v1 1 B
or, = Zi = + 2
i SC S C
vi 1 B
Hence, Zi = = R+ + 2 (15.13.33)
i SC S C
B / S 2C B B / CR
Now, v0 = vi = 2 vi = 2 vi
1 B S CR + S + B S + S / CR + B / CR
R+ + 2
SC S C
w 20
= vi
S + S w 0 / Q + w 20
2
b g
v0 w 20
or, = 2 (LP Filter) (15.13.34)
vi S + S w 0 / Q + w 20
b g
where, w0 = (B/RC)1/2, Q = (BRC)1/2 (15.13.35)
Sensitivity figures for Q and w0 for deviation in different parameters, both active and passive are
derived as
1 1
S RQ = = S CQ = S BQ , and S Rw o = = S Cw o = S Bw o (15.13.36)
2 2
15.13.2 Switched Capacitor Filter

The main advantage of the active RC filters is that they do not use passive inductors. The main difficulty
in making active RC filters in monolithic IC form lies in:
∑ the need for large value of capacitors
∑ the requirement of accurate RC time constant
The integrated resistors have poor temperature and linearity characteristics. The large value of resistors
takes excessive amount of chip area. This is the main reason why active RC filters could not be produced
%!&
in fully integrated form in MOS technology. It is impossible to manufacture suitable value passive
components of active RC filter with the same accuracy as those which are simulated using the op-amp.
The MOS technology can produce the product of RC of sufficient magnitude and accuracy. The
switched capacitor offers an attractive alternative of the active RC filters. It is easy to implement MOS
switches, MOS capacitors and MOS op-amp. It is difficult to fabricate resistance of the range of 103 W
to 106 W and capacitors in the range of 1nF to 1mF with accuracy @ 1% or better which is generally
required for audio frequency and instrumentation applications.
All analog circuits can be implemented using MOS switches, capacitors and op-amps. This suggests
that the integration of both digital and analog functions is possible on the same chip. In VLSI technology
two very important components are MOS transistors and MOS capacitors, especially in the range of pF.
The conventional circuits performance depends upon the time constant RC of the circuit. The active
RC filters are continuous-time filters, i.e. the input and output signals remain present all the time. The
active filters often employ hybrid technology consisting of monolithic op-amp. and thin-film resistors
and capacitors. The switched capacitor filters are analog sampled data systems, containing only
∑ Capacitors
∑ Op-amp
∑ MOS switches
If the switching frequency is much higher than the signal frequency, the sampled data filter provides
an alternative and attractive equivalent arrangement for the active RC filter.
Advantages
∑ Complete filter is available in the monolithic form
∑ Since it uses MOS technology, high component density is possible
∑ Since component ratios are controlled more precisely than individual component values, its
accuracy is more
∑ Resistance is realized using capacitors, power consumption is reduced
∑ No physical resistance is present, high tolerance, temperature drift and large physical size is
reduced
Trials with switched capacitor filter led to op-amp fabrication.
15.13.4 Realization of Resistor Using Capacitor

Switched capacitors have been used to overcome the above difficulties. The term switched capacitor is
used because of the switching operation of a capacitor between two nodes. The switching of capacitors
at sufficiently high rate is equivalent to a resistor between two nodes. It can be demonstrated by circuit
of Figs. 15.82(a d)
In Fig. 15.82(b), when switch S1 is closed (ON) and switch S2 open (OFF), the input voltage charges
the capacitor C with the expression
Q = Cvi (15.13.37)
%!'
Figure 15.82(a) Figure 15.82(b) Figure 15.82(c) Figure 15.82(d)
Now the conditions of S1 and S2 are changed, i.e. S1 becomes OFF and S2 becomes ON. Capacitor C
starts discharging. If the switches are ideal, the charging and discharging will be instantaneous. The
current passing through the capacitor C depends on the rate at which the charge is transferred to it. If
the switch is made ON and OFF for Tclock second, the current i passing through it is expressed as
Q Q Cvi
i= = Qf = = = Cvi fclock (15.13.38)
T Tclock Tclock
where Tclock = clock period and fclock is the clock frequency.
It is assumed that fclock >> fsignal. If the switched-capacitor circuit were replaced by a resistance, the
current i would be expressed as
vi T 1
R= = clock = (15.13.39)
i C Cf clock
In Fig. 15.82(d), when S1 is ON and S2 is OFF, the capacitor C is charged to vi. When S1 is OFF and
S2 is ON, the charged capacitor C starts discharging and discharges to the output voltage vo. If vo < vi
(normally), charge transferred is
Q = C (vi vo) (15.13.40)
The rate of transfer of charge is defined as the current flow through the capacitor and is expressed
as
Q C(vi - vo )
i= = (15.13.41)
Tclock Tclock
The equivalent value of floating resistor shown in Fig. 15.82(c) is written as
vi - vo T 1
R= = clock = (15.13.42)
i C Cf clock
The equivalent resistor R that can perform the same function as Fig. 15.82(c) is expressed in
Eqn. 15.13.42. From Eqns. 15.13.39 and 15.13.42, it is clear that R is function of C and fclock and is
inversely proportional to these variables. Since C is fixed, the value of R is inversely proportional to the
value of fclock.
Here, switches used are of MOS types having ON resistance of the order of KW and OFF resistance
of the order of several hundred MW. Hence, the OFF/ON resistance ratio is very high typically of the
order of 105. The VGS is generated by external clock of the period T. The MOS switches are controlled
by two phase (f and f ), non-overlapping clocks as shown on the left side of Fig. 15.83. It is essential
%"
that when S1 is ON, S2 must be OFF and vice-versa. In this figure the capacitor current consists of
short burst at each switch closing. If the switches are opened and closed at faster rate, the burst of
current wave will have the same amplitude but will occur more often. This means the average current is
larger for higher switching rate. Figure 15.83 contains enhancement n-type MOSFET implementation
of Fig. 15.82(a).
Note : In order to obtain a suitable value of R, the fclock >> fsignal.
Other switched capacitor circuits are shown in Figs. 15.8(a c.)
Figure 15.83 Two phase signals and input/output currents
15.13.5 Switch Capacitor Integrator

The transfer function of the RC integrator shown in Fig. 15.85(a) approximated as
1 -1
G(s) = = (15.13.43)
SRC jw /w o
1
where wo = = frequency at which the gain becomes unity (15.13.44)
RC
Figure 15.84(a)
%"
Figure 15.84(b)
Figure 15.84(c)
In transforming the active RC integrator into switched capacitor integrator, the resistor R is to be
replaced by a simulated resistor in the form of a capacitor. Figure 15.85(b) is the representation of
Fig. 15.85(a) except the replacement of input resistor R by a grounded capacitor in between two-MOS
transistors acting as switches S1 and S 2. Non-overlapping two-phase clocks drive these two MOS
switches. Fig. 15.85(b) shows two-phase clocksf and f .
During the clock phase f, C1 is connected across the signal source vi as indicated in Fig. 15.85(c).
Variation in vi is negligibly small. This follows that during f clock, the capacitor C1 charges up to
voltage vi. The charge accumulated across C1 is written as
QC1 = C1vi. (15.13.45)

%"
Figure 15.85(c) Figure 15.85(d)
During f clock, the capacitor C1 gets connected to the virtual grounded input of the op-amp. as
indicated in Fig. 15.85(d). Thus, capacitor C1 is forced to discharge and its previous charge QC1 gets
transferred to C2 during the ON period of f clock.
From these discussions it is clear that during each clock Tclock an amount of charge = QC1= C1vi is
extracted from the input signal source vi and supplied to the integrator capacitor C2. The average
current flowing between the input node and the virtual ground is
dQ DQ C1vi
Iav =
= = (15.13.46)
dt Dt T
Equation 15.13.46 defines an equivalent resistance R that is in effect present between the input and
the virtual ground.
vi T 1
Thus, R= = clock = (15.13.47)
I av C1 C1 f clock
Tclock C
Now, the integrator time constant RC2 = C2 = 2 Tclock (15.13.48)
C1 C1
If the ON and OFF durations of the clock are kept small, one can think that the process is almost
continuous.
Thus, the clock frequency fclock and the ratio of the capacitors C2/C1 determine the time constant that
decides the frequency response of the filter. Both of these parameters can be controlled in IC process.
The capacitor ratio can be achieved large rather than absolute values. The accuracy of capacitor ratio
can be controlled in MOS technology within 0.1%.
Another point worth observing is with reasonable clock frequency (100 kHz) and not too large
capacitor ratio (10) one can obtain reasonably large time constant (104s) suitable for audio applications.
Since the capacitor occupies large area of IC chip, the ratio accuracy quoted above are obtainable with
capacitor value as low as 0.2 pF.
Stray capacitance
MOS switches, their interconnections, and top and down plates of the switched capacitors face the
problem of stray capacitive effect. The parasitic effects are due to
%"!
CS1 = source-to-substrate capacitor of T1

CD1,CD2 = drain-to-substrate capacitor of T1 and T2
CS2 = source-to-substrate capacitor of T2
CTS,CBS = top and bottom plate parasitic of C2
Since the stray capacitance CS1 and CBS are across voltage sources they are not effective. The other
stray capacitors CS2 and CTs are connected between ground and the virtual ground, also are effective.
Thus, only two-stray capacitances (CD1 and CD2) are effective as in Figs. 15.86(a) and 15.86(b).
Figure 15.86(a) Presence of stray capacitance
Figure 15.86(b)
15.14 DVCVS/DVCCS
Another very important linear active element acting simultaneously as Differential Voltage Controlled
Voltage Source (DVCVS) and Differential Voltage Controlled Current Source (DVCCS) is also used to
generate all types of transfer functions. As such DVCVS/DVCCS is basically a differential input linear
active element and its circuit symbol is shown in Fig. 15.87.
%""
Figure 15.87 Symbol of DVCVS/ DVCCS
The output current of the DVCVS/DVCCS is proportional to the difference of the input voltages v1
and v2. To be exact, the output current Io of the DVCVS/DVCCS is expressed as
Io = G(v1 v2) (15.14.1)
Example
Obtain input resistance of the circuit shown in Fig. 15.88(a).
Figure 15.88(a) DVCCS circuit
Solution
io = gm(0 vi) = gmvi (15.14.2)
v o = ioRL = gmviRL (15.14.3)
vi - v o v + gm RL vi (1 + gm RL ) vi
ii = = i =
RF RF RF
vi RF
or, Zi = = (15.14.4)
ii 1 + gm R L
vi 1/ jw C 1
If RF is changed by a capacitor, then Zi = = = (15.14.5)
ii 1 + gm R L jw C (1 + gm R L )
The circuit works as a capacitor multiplier with multiplying factor (1 + gmRL).
Consider the circuits of Figs. 15.88(b) and (c).
%"#
Figure 15.88(b) HP circuit Figure 15.88(c) LP circuit
From Fig. 15.88(b) ii = j(vi vo)w C and io = (0 vo)gm = ii (15.14.6)

or vogm = j(vi vo)w C
or (gm + jw C)vo = jw Cvi
vo jw C 1 1 1
Hence, = = = = (HP) (15.14.7)
vi gm + jw C 1 + gm / jw C 1 - jg m /w C 1 - jw H /w
This transfer function of Eqn. 15.14.7 describes a high pass circuit.
From Fig. 15.88(c) io = (vi vo) gm (15.14.8)
1 ( v - vo ) g m
vo = io = i (15.14.9)
jw C jw C
or
FG
vo 1 +
gm IJvg
= i m
H jw C Kjw C
vo g / jw C 1 1
Hence, = m = = (LP) (15.14.10)
vi 1 + gm / jw C 1 + jw C / gm 1 + jw /w L
This is the transfer function of a low pass circuit.
Second Order Functions

Figure 15.89 is a generalized circuit of biquad realization.
Figure 15.89 Biquad circuit

%"$
io1 = (v1 vo)gm1 and io2 = (vo1 vo)gm2 (15.14.11)
io1 i
Also, = vo1 v2 and o2 = vo v3 (15.14.12)
jw C1 jw C2
io1 g v g v
or vo1 = + v2 = m1 1 - m1 o + v2
jw C1 jw C1 jw C1
or io2 = j (v o - v3 )w C2 = ( vo1 - vo ) gm2
gm1 gm2 v1 gm1 gm2 vo

= - + gm 2 v 2 - g m 2 v o
jw C1 jw C1
or
FG SC2 +
gm1 gm2 IJ g g
+ gm2 vo = SC2 v3 + gm2 v2 + m1 m2 v1
H SC1 K SC1
S 2 C1C2 + SC1 gm2 + gm1 gm2 S 2 C1C2 v3 + SC1 gm2 v2 + gm1 gm2 v1
or vo = (Biquad) (15.14.13)
SC1 SC1
From Eqn. 15.14.13, different biquad equations for LP, BP, HP, and BR can be obtained.
Case I: When v2 = v3 = 0, Eqn. 15.14.13 reduces to
S 2 C1C2 + SC1 gm2 + gm1 gm2 g g

vo = m1 m2 v1
SC1 SC1
vo gm1 gm2
or = 2 (LP) (15.14.14)
vi S C1C2 + SC1 gm2 + gm1 gm2
Case II: When v1 = v3 = 0, Eqn. 15.14.13 reduces to

S 2 C1C2 + SC1 gm2 + gm1 gm2
vo = gm2v2
SC1
vo SC1 gm2
= 2 (BP) (15.14.15)
v2 S C1C2 + SC1 gm2 + gm1 gm2
Case III: When vi = v2 = 0, Eqn. 15.14.13 reduces to

S 2 C1C2 + SC1 gm2 + gm1 gm2
vo = SC2v3
SC1
vo S 2 C1C2
= 2 (HP) (15.14.16)
%"%
Case IV: When v1 = v3 and v2 = 0, Eqn. 15.14.13 reduces to
S 2 C1C2 + SC1 gm2 + gm1 gm2 g g

vo = SC2 v3 + m1 m2 v1
SC1 SC1
S 2 C1C2 v3 + gm1 gm2 v1 S 2 C1C2 + gm1 gm2

= = v1
SC1 SC1
vo S 2 C1C2 + gm1 gm2

= 2 (BR) (15.14.17)
Figure 15.89 describes all types of second order filter functions, each one having the same natural
frequency of oscillation e gm1 gm2 . j
15.15 BiFET and BiMOS Circuits
We know that it is possible to fabricate JFETs/MOSFETs and BJTs on the same chip. Hence, properties
of FETs and BJTs were combined to yield better amplifier circuits. All BiFET(BiMOS) op-amps. employ
JFETs/MOSFETs as input stages and the remaining stages use BJT amplifiers. The first BiFET(BiMOS)
was commercially produced in 1980s. The FET differential stages have specific advantage over BJTs
w.r.t. input resistance, lower input bias current and hence decreased input offset current, and higher
slew rate. The gate to source resistance of FET is much larger than that of the rp of the BJT to account
for the higher input resistance. The input resistance of the FET differential stage is approximately four
times that of the corresponding BJT differential stage.
The input bias current of a JFET is the reverse bias current IGSS of the reverse biased gate to channel
junction. This current is very small w.r.t. reverse bias saturation current of the BJT. Since, IGSS is very
small, the offset current due to device mismatch is also small than those in the BJT circuits. The use of
MOSFET differential amplifier stages further decreases these quantities as the leakage current through
the gate oxide is much smaller than IGSS of the JFET.
The gm of a FET is much smaller than that of a BJT for the same amount of drain and collector
current. This affects the differential gain Adm of the FET amplifier. In order to overcome this limitation,
the BiFET(BiMOS) circuit uses three-stages Op. Amps. Ultimately, BiFET(BiMOS) are low noise
amplifiers w.r.t. BJT amplifiers.
15.16 Analog Computer

The word analog has been derived from analogy that means similarity. The analog computer is electrical
simulation (similarity) of the physical system that predicts its behaviour under different types of excitations.
Thus, the problem boils down to describe a physical system by a set of either algebraic or differential
equations. In essence we have to describe the physical system by a mathematical model (equation) that
specifies relationship between independent and dependent variables. Electronic devices whose
%"&
characteristics must be analog in nature must solve the mathematical equation. The most versatile
analog electronic device is op-amp. The basic function of the analog computer may be:
∑ to solve mathematical equation
∑ to simulate physical system
∑ to control a physical process
The programming procedure of analog computer is to arrange op-amps. to solve a mathematical
equation as indicated in the describing equation and provide means for displaying it. The describing
function indicates the use of integrator, summer, inverter, etc. Thus, in addition to op-amp., the practical
analog computer must include:
∑ an assortment of precision resistors and capacitors used to set time constant of the integrator
∑ an assortment of function generators to provide various types of inputs
∑ potentiometers for adjusting constants
∑ switches for controlling operations
∑ means for indicating the initial conditions
∑ means for displaying output (oscilloscope, recorder etc.)
∑ problem board for connecting components
∑ patch cords for connecting different sections
The faithful simulation of analog computer of a physical system in the hands of skillful operator
provides an insight into the characteristics of the physical system and permits the design engineer to
evaluate the effect of the change in the system parameters before actual system can be built. For an
instance, the weight of an automobile must be correlated with its velocity or acceleration so that a
compromise may be made on its maximum limit of velocity and acceleration and its weight without
overturning it.
Steps involved in using an analog computer are:
∑ set up mathematical equation of the physical system
∑ rearrange the mathematical equation for computer operation
∑ select proper scale factors
15.16.1 Computer Diagram Notations

Two types of notations are in common use for analog computer. In the notations presented, it is
assumed that resistors and capacitors are connected externally to the op-amps. However, one can
assume that the resistors and capacitors are internally connected and need not be shown externally. The
constant of multiplication is indicated inside each block. The two types of notations are illustrated in
Fig. 15.90.
%"'
Figure 15.90 Notations of analog computer blocks

%#
Example
Arrange the computer to solve the simultaneous equations as
2x + 4y = 10 and 2x y = 4
Solution
x = [2y 5]
y = [2x + 4]
These variables are generated and used by each other as in Fig. 15.91.
Figure 15.91 Solution of simultaneous equation
15.16.2 Circuit of One Degree Freedom

Let us consider a physical system of one-degree-of-freedom of Fig. 15.92, in which K is the spring
constant, D is the damping co-efficient, m is the mass of the system. Sometimes spring constant is
written in terms of compliance that is inverse of K.
Assumption : m = constant, K = linear, and D µ velocity.
Figure 15.92 One-degree-of-freedom system

%#
Figure 15.93 Computer diagram
External force = F
Resistive forces are:
dv d2x
∑ inertial force = Fm = m = m 2
dt dt
dx
∑ damping force = FD = D
dt
∑ spring force = FK = Kx
Now applying DAlemberts principle ÂF =0
or F + Fm + FD + FK = 0
d2x dx
or Fm 2
-D - Kx = 0
dt dt
d2x dx
or F=m 2
+D + Kx
dt dt
or mx + Dx + Kx = F
or
x =
RS D x + K x - F UV = {a x + a x - F }
1 2 1
Tm m mW
Example
The physical system of Fig. 15.92 has the mass m = 1 kg, damping (frictional) coefficient D = 2 Ns/m,
and spring constant K = 104 N/m. Plan an analog computer program to obtain record of displacement
and velocity for an applied force F = 200 cos 200t.
Solution
The equation of motion of the physical system is written as
mx + Dx + Kx = F
%#
or (1 kg) x + (2 Ns/m) x + (104 N/m) x = 200 cos 200t

or x + 10 4 x = x + 2dw n x + w 2n x = 200 cos 200t
x + 2
100
The natural frequency of oscillation = wn = 100 r/s and fn = = 16 Hz
2p
2
d = damping factor = = 0.01 (over damped system)
2 ¥ 100
The bandwidth of an XY recorder is very low, i.e. maximum up to 10 Hz. Hence, in order to get a
hard copy of the response of the system, we have to slow down the problem on the analog computer
because the recorder will not follow the rapid variations in the displacement and velocity. Let us slow
down the problem by a factor of 10. The equation of vibration now becomes
100 xt + 10 ¥ 2 xt + 104 xt = 200 cos 200 ¥ t/10
xt + 0.2 xt + 102 xt = 2 cos 20t
10
The natural frequency of oscillation of this equation = wn = 10 r/s and fn = = 1.6 Hz
2p
Hence, 10 Hz recorder will be able record this.
15.16.3 Reasons for Time and Magnitude Scaling

The dependent and independent variables of analog computer are voltage and time (in seconds or milli
seconds). The scaling is essential if the independent variable of the physical problem is other than the
time such as displacement, angle, etc. Also it becomes essential when the independent variable of the
physical system though time, yet in either micro second or in hours. The analog computers independent
variable is always in seconds or milli seconds. Hence, the physical problem has either to be speeded up
or slowed down to suit the physical devices of display or recorder.
15.16.4 Time Scaling

In order to change the time scale of any equation, it is only required to make a substitution for the
independent variable such as
t = at
where t = computer time
t = problem time or real time
a = time scale factor (constant)
This suggests two possibilities:
∑ If a > 1, the computer time t will be more that the real time (physical system time) and the
computer will take more time than the physical system after time scaling. In other words, a >
1, will slow down the problem on computer.
%#!
∑ If a < 1, the computer will take less time to solve the problem after time scaling.
d d d d2 d2 d2
= =a and 2 = 2
= a2 2 ,
dt dt / a dt dt d (t / a ) dt
dn n d
n
Similarly, = a
dt n dt n
Example
If a physical system is described by the equation

x + 2.5 x + 100 x = 50 sin10t, x(0) = 1, = x(0) = 2 .
The recorder available has the bandwidth of 1Hz. Suggest the time scale factor to get the hard copy
of the output.
Solution
10
wn = 10 r/s and fn = = 1.6 Hz. The recorder of 1Hz bandwidth cannot record 1.6 Hz signal. Hence,
2p
it has to be slowed down. Let the time scale factor has a relationship as t = 5t. After time scaling the
equation becomes
xt + 5 ¥ 2.5xt + 100 xt = 50 sin 10 ¥ t/5, x(0) = 1, x (0) = 2/5.
25
or xt + 0.5xt + 4 xt = 2 sin 2t, x(0) = 1, x (0) = 0.4.

2
The natural frequency of oscillation of time scaled equation = wn = 2 r/s and fn = = 0.33 Hz. The
2p
0.5
damping factor after scaling = d2 = = 0.125
2¥2
2.5
Damping factor before scaling = d1 = = 0.125.
2 ¥ 10
This indicates that time scaling does not change the characteristic of the equation other than the time
variable.
15.16.5 Magnitude Scaling

In general let us assume that the dependent variable of the physical system is cm or inch. This dependent
variable has to be related to the dependent variable of the analog computer that is volt. The displacement,
velocity and acceleration of the physical system are related to the computer variable to volt only as
Vx = Kx ¥ x
Vx = K x ¥ x
Vx = K x ¥ x
%#"
where, Kx = volt/cm or inch

K x = volt/(cm or inch/sec)
K x = volt/(cm or inch/sec2)
Normally the maximum output voltage of an op-amp is ±10 V. This range should not be exceeded to
avoid the problem of saturation of the amplifier. Hence, selection of the magnitude scale factor should
be done accordingly.
Vmax
Kx £ (volt/cm or inch)
xmax
If Vmax = 10 V, xmax= 2.5 cm, then
10
Kx £
= 4 V/cm
2.5
This is the maximum limit of the magnitude scaling. It is always advisable to fix this limit less than 4.
15.16.6 Estimation of Maximum Values

Let us consider the equation
x + a1 x + a2 x = f(t)
Assuming that fm is the magnitude of f (t) and that is known from the knowledge of a physical
problem. As a first approximation, let us neglect the damping effect i.e. a1 = 0 and f (t) = fm. Assuming
zero initial conditions, it can be shown that the displacement x(t) is

x + a2 x = fm
2
or (D + a2)x = fm
Roots of complementary function= ± j a 2 = ± jwn

Hence, complementary function = A cos(wnt + B)
-1
P.I. =
1
fm =
1 F
fm = 1 +
D2 I fm F
= 1
D2 If m fm
a 2 + D2 FG D2
IJ GH a2 JK a2 GH a2 JK a 2
@
a2
a2 1 +
H a2 K
fm
Thus, total solution x(t) = A cos (wnt + B) +
a2
fm
or 0 = A cos B + and
a2
dx
Also = Awn sin (wt + B) = Awn sin B = 0, Hence, B must be equal to zero.
dt
f
Then A= m
a2
%##
fm fm fm
Now x(t) = cos wnt + = (1 coswnt)
a2 a2 a2
fm f
xmax = (1 + 1) = 2 m
a2 a2
fm f
x m = wn sin wnt = wn m
a2 a2
fm f
xm = w n2
cos w n t = w 2n m = w n x m
a2 a2
Example
A vibratory system is described by the equation
x + 2.5x + 100 x = 0, x(0) = 1 and x(0) = 2
(a) Rewrite the equation to slow down the problem by a factor of 5, (b) select the proper magnitude-
scale factor for the computer solution of the problem, (c) sketch the computer diagrams.
Solution
(a) In order to slow down the problem by a factor of 5, let us assume t = 5t and hence the original
equation is written as
xt + 5 ¥ 2.5xt + 100 xt = 0, xt (0) = 1, xt ( 0) = 2/5.
25
or xt + 0.5xt + 4 xt = 0, xt (0) = 1, xt (0) = 0.4.
10 5
The original undamped natural frequency of the system wn1 = 100 = 10 r/s, fn1 = = =
2p p
2.5 2.5
1.59 Hz = 1.6 Hz and d1 = = = 0.125
2 ¥ wn 2 ¥ 10
2 1
The slowed down undamped natural frequency of the system = wn1 = 4 = 2r /s, f = = =
2p p
0.5
0.33 Hz, and d1 = = 0.125
2¥2
This shows that characteristics of the equation remains the same even after time-scaling the problem.
The change in the initial condition due to time scaling is demonstrated as x(0) = 1 and x (0) = 2/5
= 0.4. This indicates that there is no change in the initial condition for the displacement but change in the
velocity takes place.
It is now essential to determine the magnitude of x(t) and its derivatives, let us assume that xm =
x(0) = 1.
Neglecting damping, the magnitude of the velocity and acceleration can be approximated as
xm = wn2xm = 4 ¥ 1 = 4
x m = wnxm = 2 ¥ 1 = 2 and
%#$
(b) The magnitude-scale factor can be selected as

10
Kx £ = 10 V/cm or inch
1
10
Kx £ = 5 V/(cm/s)
2
10
K x £ = 2.5 V/(cm/s2)
4
In order to avoid the saturation limit let the corresponding voltage limit = 8 V, then
8
Kx £= 8 V/cm or inch
1
8
K x £ = 4 V/(cm/s)
2
8
K x £ = 2 V/(cm/s2)
4
Now the problem is magnitude-scale by multiplying the whole equation by 2 as
2 xt + 2 ¥ 0.5xt + 2 ¥ 4 xt = 0
The above equation is rearranged as per the magnitude-scales inside the bracket of each term as
( 2) xt + (4) ¥ 0.25xt + (8) xt = 0
( 2) xt = [( 4) ¥ 0.25xt + (8) xt ]
The lower order terms are generated by integrating (2) x and not x . This is depicted in
Fig. 15.94. Since the output of the integrator corresponding the displacement is 8 V, its capaci-
tor will be charged to the value 8 ¥ x(0) = 8 V. The output voltage of the integrator correspond-
ing to velocity is labelled - 4 x and x (0) = 0.4; hence, its capacitor will be charged to 4 ¥ 0.4
= 1.6 V.
Figure 15.94 Solution of time and magnitude scaled problem

%#%
15.16.7 Function Generation

1. Using transfer function simulation with factorable denominator
S +1 S +1 A B
G(s) = 2
= = +
S - 5S + 6 ( S - 2)( S - 3) S-2 S-3
or S + 1 = A(S 3) + B(S 2)
or A + B = 1 and 3A 2B = 1
2 A + 2B = 2
-3 A - 2B = 1
hence, B = 1 A = 1(3) = 4
-A =3
S +1 S +1 -3 4 Y
Now G(s) = 2
= = + =
S - 5S + 6 ( S - 2)( S - 3) S -2 S -3 X
4 -3
Y= X + X = Y1 + Y2
S-3 S -2
4
or Y1 = X
S-3
or (S 3) Y1 = 4X
1
or Y1 =
S
(4 X + 3Y1 ) = z (4 X + 3Y1 ) dt
-3
Similarly, Y2 = X
S -2
or (S 2)Y2 = 3X
1
or Y2 =
S z z
( - 3 X + 2Y2 ) = - (3 X - 2Y2 )dt = (2Y2 - 3 X )dt
Figure 15.95
%#&
2. G(s) =
3S + 4
=
3S + 4
=
W FG IJ FG Y IJ
2
S + 3S + 2 ( S + 1)( S + 2) X H K HWK
W 3S + 4 Y 1
Thus, = and =
X ( S + 2) W ( S + 1)
or SW + 2W = 2SX + 4X
1
or W = (4 X - 2W ) + 2 X =
S
SY + Y = W
z (4 X - 2W )dt + 2 X
1
or Y=
S
(W - Y ) = z (W - Y )dt
Figure 15.96
3. Non-factorable denominator
Y S+2
= 2
X S + 3S + 3
or S2Y + 3SY + 3Y = SX + 2X
2 X + SX - 3Y - 3SY X - 3Y 2 X - 3Y
or Y= 2
= +
S S S2
= z (3Y - X )dt + zz ( - 3Y + 2 X ) dt
Figure 15.97
%#'
t
4. y= z
0
aydt + y(0) , or, y + ay = 0
Figure 15.98
or (D + a)y = 0, or, y = C1eat, initial condition : at t = 0, y = y(0)

y(0) = C1,
or y = y(0)eat
5. Design an analog computer set-up to generate the function
y(t) = 5(1 exp05t cos 2t)
The maximum computer range is ±10 V.
y(t) = 5 5 exp05t cos 2t
or 5 exp0.5tcos 2t = 5 y
dy
= + 5(0.5)exp -0.5t cos 2 t - 5 exp -0.5t(2) ( - sin 2 t)
dt
= + 0.5 (5)exp -0.5t cos 2 t + 5(2)exp -0.5t sin 2 t
= - 0.5( y - 5) + 5(2) exp -0.5t sin 2 t

d2y Ê dy ˆ
2
= - 0.5 Á ˜ + 5(2) ( - 0.5) exp-0.5t sin 2t + 5(2) exp-0.5t (2) cos 2t
dt Ë dt ¯
= - 0.5
FG dy IJ - (0.5) 5(2)exp -0.5t
sin 2t + (22 )(5 exp -0.5t cos 2t )
H dt K
dy
5(2) exp -0.5t sin 2t = + 0.5 ( y - 5)
dt
760
d2y Ê dy ˆ Ï dy ¸
Hence, = - 0.5 Á ˜ + ( - 0.5) Ì + 0.5 ( y - 5) ˝ + 22 (5 - y )
dt 2 Ë dt ¯ Ó dt ˛
dy dy
=- - 0.25 y + 125
. + 20 - 4 y = - - 4.25y + 2125
.
dt dt
d2y dy
or 2
+ + 4.25 y - 2125
. =0
dt dt
or
y + y + 4.25y - 2125
. =0
dy
y(0) = 5 5 = 0, = (0.5)(5) = 2.5
dt t=0
y(max) = 5 + |5| = 10
dy
= 5(0.5cos2t + 2sin2t} ext0.5t = 5 0.52 + 2 2 = 5 ¥ 4.25
dt max
= 5 ¥ 2.06 = 10.3

y = - ( y + 4.25 y - 2125
. )y
z y dt = y =
y
10.3
10.3 = - z RST y
10.3
y
(10.3) + 4.25 (10) - 2125
10
. dt
UV
W
y
Now the computer diagram can be constructed starting with as the input of the integrator.
10.3
Figure 15. 99
1. The output of an op-amp integrator can Solution:

swing from +15 V to 15 V. The step in-
1 vi
put shown in Fig. 15.100(a) is vi = 0 for
t < 0 and switched at t = 0 to 5 V. The
vo = -
RC z vi dt + C = -
RC
t+C
output voltage vo = +15 V for t < 0. Plot At t £ 0, vi = 0 and vo= +15 V, vo = 15

the waveform.
761
vi vi
=- *0 + C C = 15V, vo = - t + 15 ,
RC RC
vi Now the waveform is plotted as in Fig.

0= - t + 15 and 15.100(b).
RC
2. For the instrumentation amplifier shown
15
t= RC = 15 1 K ¥ 10 -6 = 3 ms in Fig. 15.101, using two ideal op-amps
vi 5 verify the following equation
The time at which the vo = 15 (GKP Univ. 1994).
=-
FG v IJ t + 15
i FG
vo = 1 +
R2 2 R2
+
IJ
( v2 v1 )
H RC K H R1 R3 K
30 30
t= RC = 1 K ¥ 10 -6 = 6 ms
vi 5
Figure 15.101 Two op-amp instrumentation amplifier
Solution: At node v() of A2

Writing node equations at node v() of A1 FG 1 + 1 + 1 IJ = v v3 v1
o
v2 + +
v1
FG 1 + 1 + 1 IJ = v 2
+
v3 HR R R K R
1 2 3 2 R1 R3
HR R R K R
1 2 3 3 R1
762
Subtracting this equation from previous FG R2 2 R2 IJ

one yields vo = 1 + + (v2 - v1 )
H R1 R3 K
FG 1 + 1 +
1 IJ
(v1 - v2 ) +
1
( v1 - v2 )
3. Show that the cross coupled differential
HR R R3 K R3 voltage follower instrumentation amplifier
1 2
shown in Fig. 15.102 produces output
v voltage vo = (1 + a + b) (v2 v1).
=- o
R2
FG 1 + 1 +
2 IJ
( v1 - v2 ) =
- v0
HR R
1 2 R3 K R2
Figure 15.102 Three op-amp instrumentation amplifier

Solution: FG R1IJ R
= 1+ b v2 - b 1 v1
From Fig. 15.102 H R K R
* KR2 vo2 Kvo2 KR2 FG
KR2 IJ FG Kv IJ
vo2 = = vo = vo1 + 1 + o2
KR2 + R2 K +1 R2 H
R2 K H1+ KK
vo1 = v1 + aR1i, vo2 = v2 bR1i,
= - Kvo1 + Kv o2 = K (v o2 - vo1 )
v - v2
where, i = 1
R
R|FG1 + b R IJ v - bFG R IJ v
1 1 U|
= KS
H R K 2
H R K 1
vo1 = v1 + a
R1
R
( v1 - v2 ) || - FGH1 + a RR IJK v + aFGH RR IJK v V||
1
1
1
2
T W
FG
= 1+ a
R1 IJ R
v1 - a 1 v2 R|FG1 + (a + b) R IJ v 1 U|
H R K R
= KS
H R K 2
R1 F R I V
vo2 = v2 - b ( v1 - v2 ) || - G 1 + ( a + b) J v | 1
R T H R K |W
1
763
vo = (1 + a + b)(v2 v1) for This illustrates that using only few kilo
ohm resistances in the form of T-network
R = R1 provides very large feedback resistance
4. Obtain the voltage vo for the circuit of resulting into very large gain.
Fig. 15.103. (AMI 1992). 5. Obtain the voltage gain vo/vi for
Solution: Fig. 15.104(a).
Writing node equations as Solution:
vi v
=- a
FG 1 + 1 +
1IJ
v1
R1 R2 HR R +R i 1 RF K
R2 vo v
va = - vi = + i
R1 RF R
FG 1 +
1
+
1 IJ
v
va = o +
0 v2 =
R1
v1
HR 2 R3 R4 K
R3 R2 R1 + Ri
R1 Ri
FG R + R IJ v
vo = 1 + 3 3
a
or v2 v1 =
R1 + Ri
v1 - v1 = -
R1 + Ri
v1
H R RK 2 4
vo Ri
F R + R IJ R v
= - G1 + 3 3 2
i A
= v2 v1 = -
R1 + Ri
v1
H R RKR 2 4 1
R2 R3
R2 + R3 +
vo RF R4
=- =
vi R1 R1
If R1 = R2 = R3 = 1 K, R4 = 10 W,
then RF = 2 K + 1 M/10 = 2 K + 100 K
= 102 K, voltage-gain
v 102 K
= Av= o = - = 102
vi 1K
Figure 15.104(a)
Combining above equations yield

vo Ri + R1
- ¥
A Ri
( R + R1 ) ( R + RF ) + RRF v v
¥ i - o = i
RRF ( Ri + R1 ) RF R
vi ( R + R1 ) ( R + RF ) + RRF + ARRi
= i vo
Figure 15.103 R ARRF Ri
764
Hence, ( Ri + R1 ) ( R + RF ) + RRF
ARF Ri ¥
vo RRF ( Ri + R1 )
=-
vi ( Ri + R1 ) ( R + RF ) + RRF + ARRi ( R + R1 ) ( R + RF ) + RRF
+ i vi
6. Obtain the voltage gain vo/vi for Fig. RRF ( Ri + R1 )
15.104(b). vo vi
Solution: = +
RF Ri + R1
Ê1 1 1 ˆ ( Ri + R1 ) ( R + RF ) + RRF + ARRi )
v1 Á + + ˜ - vo
Ë R R1 + Ri RF ¯ ARRF Ri
v vi ( R + R1 ) ( R + RF )
= o + =- i vi
RF Ri + R1 RRF ( Ri + R1 )
FG R IJ v
v2 = vi + ( v1 - vi ) 1 Hence, o
HR +R K vi
1 i
F R IJ + v FG R IJ ARi ( R + RF )
1 i =-
=v G 1 i ( Ri + R1 )( R + RF ) + RRF + ARRi
HR +R K HR +R K
1 i 1 i
7. Obtain the voltage gain vo/vio for
Ri Ri
v2 v1 = - v1 + vi Fig. 15.105.
R1 + Ri R1 + Ri
Solution:
Ri
= ( vi - v1 )
R1 + Ri
vo Ri
= (v2 v1) = (vi v1) ,
A Ri + R1
Ri + R1 voFG IJ = (vi v1)
Ri H K
A
F v I F R + R IJ + v
v = - G oJ G i 1
1
H AK H R K i
i
FG v IJ R + R
o i 1
H AK R i Figure 15.105
v3 - vio v3 v3 - vo
+ + =0
Ri + R1 R RF
v3
FG 1 +
1
+
1 IJ
HR +R
i 1 R RF K
vio v
= + o
Ri + R1 RF
RRF + ( Ri + R1 ) ( R + RF )
v3
( Ri + R1 ) RRF
Figure 15.104(b)
765
vio v vi v 1 1 FG IJ
= + o + o = + v1
Ri + R1 RF R1 RF R1 RF H K
v3 - vio
v1 = v3 vio and v2 = R1
Ri + R1 = -
FG 1 + 1 IJ v ' o
vo v - vio
= v2 v1 = 3 Ri v3 + vio
HR R K A
1 F
A Ri + R1 vi v F 1 + 1 IJ v
o o
R + R1 vo =- -G
v3 = - i ¥ + vio R1 R HR F R K A 1 F
Ri A
(1 + A) R1 + RF
FG v vo Ri + R1 IJ =- vo
AR1 RF
io - ¥
H A Ri K Avf
v
= o =-
ARF
RRF + ( R + RF ) ( Ri + R1 ) vi (1 + A) R1 + RF
b g
Ri + R1 RRF vi v1 = R1i1
vo vio vo ARF vi
= + vi + = R1i1 = vi -
RF Ri + R1 A A{(1 + A) R1 + RF }
vo A ( R + RF ) Ri
= (1 + A) R1 + RF - RF
vio ARRi + RRF + ( R + RF ) ( Ri + R1 ) R1i1 = vi
(1 + A) R1 + RF
8. Prove that the voltage gain and input resis-
(1 + A) R1
tance with feedback in Fig. 15.106 is given = vi
ARF (1 + A) R1 + RF
by the expressions Avf = - v (1 + A) R1 + RF
R1 (1 + A) + RF Rif = i = R1
RS R UV ||R , where R is the i1 (1 + A) R1
F
and Rif = R1 + i i RF
T 1+ AW
internal input resistance of the op-amp
= R1 +
(1 + A)
Solution: This input resistance comes in parallel to
the op-amps internal input resistance Ri.
v - v1 v - vo
i1 = i = if = 1 Hence, effective input resistance is equal to
R1 RF
vi v FG
1 1 IJ Rif =
RSR + R UV||R F
+ o = + v1 1 i
R1 RF H
R1 RF K T (1 + A) W
and vo = Av1 9. Show that if Ri = •, Ro = 0 and A1 and A2< 0
in Fig. 15.107, then vo = A2{A1(vf v1) + v2}
where vf = vo
FG R IJ . If A A R 1 1 2 1
>> 1,
HR +R K R +R 1 F 1 F
F R IJ FG v - v IJ .
then v = G 1 +
o
F
1
2
H R KH AK i 1
Figure 15.106
766
vo - A2 A1
FG R v IJ = A (A v
1 o
2 1 1 v2)
HR +R K
1 F
{(1 - A2 A1 ) R1 + R/ F } vo
= A2(v2 A1v1)
R1 + RF
vo =
R1 + RF FG
v
¥ v1 - 2
IJ
R1 H
A1 K
Figure 15.107
Solution:
FG
= 1+
RF IJ FG v - v IJ
1
2
The output of first op-amp is expressed as H R1 KH A K 1
(v1 vf ) A1 = vo1 10. For the dc level shifter circuit shown in

The output of the second op-amp is Fig. 15.108(a), determine the level shift be-
tween input and output voltages.
vo = A2(v2 vo1) = A2{v2 A1(v1 vf)}
= A2{A1(vf v1) + v2} Solution:
R1 Vi = VBE 1 + VR1 + VR2 + Vo ,

Also, vf = vo
R1 + RF
VE1E2
VBE2 = VR2 = R2
vo = A2
|RS A FG R
1
1
vo
I U|
-v J +v V
1 2
R1 + R2
|T H R + R
1 F K |W

767
Vo = Vi VBE1 VE1E2
= Vi VBE1 1 +
FG R1
VBE2
IJ
H R2 K
VBE1 = VBE2 = VBE
FG
Vo = Vi VBE 1 + 1 +
R1 IJ
H R2 K
FG
= Vi VBE 2 + R1 IJ
H R2 K
11. Obtain the level shift Vo in Fig. 15.108(b).
Solution:
I1 = IE1 + IC2 = IC1 + IB1 + IC2 Figure 15.109(a)
= IC1 + IB1 + bIB2
= IC1 + IB1 + bIC1
= IB1 + (1 + b)IC1 @ 1 + b I C
b g
1
VCC = I1R1 + VBE1 + Vi = R1(1 + b)IC1
+ VBE1 + Vi
Figure 15.109(b)
VCC - Vi - VBE 1
IC1 =
(1 + b ) R1
Vo = R2IE2 = R2(1 + b)IB2
= R2(1 + b)IC1
(VCC - Vi - VBE 1 ) (1 + b ) R2
=
(1 + b ) R1
(VCC - Vi - VBE 1 ) R2
Vo =
R1
12. Draw the output wave shapes of the volt-
age follower using op-amp with 1 V/ms Figure 15.109(c)
slew rate with the square wave input
shown in Fig. 15.109(a).
Solution: signal that does not produce appreciable
It is seen from the wave shapes of vo that distortion. A 10 kHz signal produces
remarkable distortion occurs for slew rate appreciable distortion as shown in
at high frequency. Fig. 15.109(b) is100 Hz Fig. 1.5109(c). A 1 MHz signal becomes
sawtooth wave as in Fig. 15.109(c).
768
13. A square wave input of 8 V peak to peak 2.4

magnitude and frequency 2 MHz is applied SR = = 1.8 V/ms
4ms
to a voltage follower which produces the
The 741 cannot be used.
triangular output as shown in Fig. 15.110.
16. The characteristic of the diode is given by
What is its slew rate?
the relationship as ID = IS(eqV/hKT 1),
Solution: where V is the forward voltage and h is the
4V ideality factor = 1 (Ge) and 2 (Si). Express
SR = = 16 V/ms Vo as a function of Vi. What is the value of
(0.5/2) m s
input voltage to result in output voltage Vo
KT
= 0, if R = 100 KW , IS = 1 mA and
q
= 26 mV.
Figure 15.110
14. The 741 op-amp is used as an inverting
amplifier with its gain = 50. What would
be the maximum input signal magnitude
applied to it if its voltage gain is flat upto
100 kHz?
Solution:
Slew rate of the 741 = 0.5 V/ms, Figrue 15.111
2pfVi(pp) ID
SR = 2pf Vm = , eqV / KT = + 1, V = KT ln I D + 1 FG IJ
106 IS q IS H K
SR (V / ms) ¥ 106 0.5 ¥ 10
Vi(pp) =
6.28 ¥ 100 ¥ 10 3
=
6.28 = 0.026 ln
FG I D IJ
+1
HI S K
= 0.796 V
È ÊI ˆ ˘
The maximum input signal to get VD = 0.026 Íln Á D ˜ + ln 1˙
ÎÍ Ë I S ¯ ˚˙
0.796
undistorted output should be =
50 È ÊI ˆ ˘
= 0.026 Íln Á D ˜ + 0 ˙
= 15.9 mV.
Î Ë IS ¯ ˚
15. A peak to peak input signal of 500 mV has
to produce a peak to peak undistorted out-
VO = VD = 0.026 ln
FG I IJ , I = V = I
D i
put voltage of 3 V with a rise time of 4 ms. HI K R
D i
S
Can 741 be used for such application?
Solution: (a) VO = VD
F V IJ = 0
= 0.026 ln G i
Rise time = 3 V (90% 10%)

H RI K S
= 3 V (0.90 0.10) = 2.4 V

769
FG V IJ = ln 1, dVo dVo i
= ln i (b) i = -C2 , =- ,
H RI K dt dt C2
S
Vi = RIs = 105 ¥ 10 6 = 0.1 V idt Q C Vf
dVO = - =- =- 1
17. In the circuit of Fig. 15.112 the output
C2 C2 C2
voltage Vo is initially zero. The switch is idt Vdt
(c) i = V/R, dVo = - = -
connected first to A to charge the capaci- C2 RC2
tor C1 to the voltage V. It is then connected
V
to point B. This process repeats f times =- in one second
per second. Calculate (a) transfer of RC2
charge per second from A to B, (b) Derive
V C Vf
the average rate of change of the output Equating dVo yields as - =- 1 ,
voltage Vo, (c) If the switch and capacitor RC2 C2
are removed and a resistor is connected 1
between point A and B, what will be the R=
C1 f
value of resistor to get the same average
rate of change the output voltage, (d) If The integration of the steady input voltage
the repetition rate of the switching action gives ramp (rate of change) voltage.
is 104 times per second, C1 = 100 pF, C2 = C Vf
(d) dVo = - 1
10 pF and V = 10 mV, what is the average C2
rate of change of the output voltage?
100
Solution: = - 10 ¥ 10 -3 ¥ 10 4 = 1000 V
10
(a) When the switch changes from B to A
18. Show that the circuit in Fig. 15.113 simu-
f times per second, the charge trans-
lates an inductance across its input termi-
ferred to the capacitor C1 = Qf = C1Vf.
nals.
The capacitor charges exponentially,
but the time constant of charging is
zero and hence capacitor charges in-
stantaneously.
V = VSS(1 e t / RC ) = VSS(1 e t / 0 )
Q
= VSS =
C1
Figure 15.113
Solution:
vi - vo
ii = + SC( vi - v+ ) , v+ = vo
R2
Figure 15.112
770
SCR1vi (1 + jw CR1 ) R2
(as unity gain), v+ = =
1 + SCR1 1 + jw CR2
ii =
FG 1 + SCIJ v - FG 1 + SCIJ v
i =
(1 + jw CR1) R2 (1 - jw CR2 )
HR K HR K
2 2
+
(1 + jw CR2 )(1 - jw CR2
1 + SCR2 1 + SCR2
= vi - v+ (1 + w 2C 2 R1 R2 + jw C ( R1 - R2 ) R2
R2 R2 =
1 + w 2 C 2 R22
=
1 + SCR2
vi -
FG
1 + SCR2 SCR1 IJ
vi = R + jwL
R2 H
R2 1 + SCR1 K (1 + w 2 C 2 R1 R2 ) R2
2 2
1 + S C R1 R2 + SC ( R1 + R2 ) where, R = ,
2 2
1 + w 2 C 2 R22
= - SCR1 - S C R1 R2 vi
R2 (1 + SCR1 ) C( R1 - R2 ) R2
and L =
1 + SCR2 1 + w 2C2 R22
= vi
R2 (1 + SCR1 ) 19. Draw the waveform of vo (t) as function
of vi. Specifying the output voltage vo (t),
vi (1 + SCR1 ) R2
Hence, Zi = = determine the voltage levels and time con-
ii 1 + SCR2 stants involved.
Figure 15.114
Solution: VF - VC
et/RC = ,
When input is changing from 12 V to VF - Vi
+12 V, the capacitor gets charged to the VF - Vi 12 - ( - 12)
maximum voltage exponentially with the t = RC ln = RC ln
VF - VC 12 - 0
time constant = 12 K ¥ 0.1 ¥ 106 = 1.2 ms.
In order to find out the time taken by the = RC In 2
capacitor to reach the final value = 12 V, = 12 × 103 × 0.1 × 10 6 × 0.693
we have to see the following expression = 0.832 ms
VC = VF (VF Vi)et/RC, As the capacitor gets charged from 12 V
771
to slightly above 0 V, the output amplifier Solution:

gets saturated.
When the capacitor is charged to +12 V, F
vo1 = vi 1 +
R I
= 2vi
the capacitor starts discharging through H R K
saturated transistor with a time constant = 1 v 2v ( s)
100 × 0.1 × 106 = 0.01 ms
20. Show that circuit of Fig. 15.115 simulates
vo2 = -
CR z vo1dt = - o1 = - i
SCR SCR
2vi ( s)
vi ( s ) or, vo2 = iiR = -
an inductor i.e. is inductive. SCR
ii ( s )
v (s)
or, i = SCR2/2 = jwCR2/2 = jwL
ii ( s )
Figure 15.115
2
where L = CR /2 10 ¥ 2 150 10 ¥ 2 ¥ 10
vo = - × =-
21. How much is the output voltage in the cir- 15 35 35
cuit of Fig. 15.116. = 6.5 V
Solution:
Writing node equation at the inverting in-
put terminal of the op-amp results as
vi - v- v - vo Ê 1 1 ˆ
= - , Á + v-
5K 10 K Ë 5 K 10 K ˜¯
vi v
= + o
5 K 10 K
10vi 5vo 10
or, v = + = v+ @ vo
15 15 100
F 1 5 I 15 - 50
F I Figure 15.116
- vo = vo
H 10 15 K H
150 K 22. Obtain the value of resistor R for the con-
=
F -35I v =
10 ¥ 2 dition that both inputs V and V+ should be
H 150 K o
15
772
amplified by the same amount in Solution:

Fig. 15.117. V V - V2 Vo - V2
R
V1 = Vo = o , in +
2R 2 R R
= IL , V1 = V2
Vin Vo Vo Vo
- - + = IL
R 2R 2R R
Vin dV 1
or, IL =
R
= C 2 , V2 =
2
dt RC zVin dt
Figure 15.117 Vo = 2V2 =

RC zVindt
If the input voltage is square wave, the
Ê 22 ˆ R
For V = 0, VO = Á 1 + ˜ V- output voltage is a triangular wave of mag-
Ë 10 ¯ R + 15 nitude ±VP and frequency f.
3.2 R 24. Find out the value of two resistors used in
= V+ a non-inverting op-amp to result in the
R + 15
voltage gain of 21 dB.
22
For V+ = 0 , VO = - V- = 2.2 V Solution:
10
21dB = 1021 / 20 = 101.05 = 11.22
VO 3.2 R V
= = O = 2.2 , R2
V+ R + 15 V- = 1+ , R2 = 10.22 R1
R1
3.2R 2.2R = 33
If R1 is selected to be 10 KW, R2
or, R = 33 KW = 102.2 KW
23. Derive a relationship between the input and 25. Obtain the transfer function between input
output voltages for the circuit shown in and output voltages of Fig. 15.119. What
Fig. 15.118. Also obtain the output wave- will be the value of the capacitor required
form for a symmetrical square wave input to yield a phaseshift of 270° at a frequency
voltage of amplitude Vp and frequency f. of 1 kHz with R = 10 K?
Figure 15.118
Figure. 15.119
773
Solution: vo 1 - SCR 1 - jw CR
or, = =
vi / SC vi vi 1 + SCR 1 + jwCR
v2 = = ,
1 1 + SCR
R+
SC 1 + (w CR ) 2
= =1
vi - v1 v - vo 1 + (w CR ) 2
= 1 ,
R R
Phase shift = tan1 wCR tan1 wCR
2v1 = vi + vo
v i + vo vi = 2 tan1 w CR = 270°
= ,
2 1 + SCR or, tan1 w CR = 135°, tan135 = 1
2vi = w CR
vo + vi = ,
1 + SCR 1 0.159
C= =
2 vi 2p ¥ 1000 ¥ 10K 10 7
vo = - vi
1 + SCR = 0.159 ¥ 10 7
( 2 - 1 - SCR)vi (1 - SCR)vi C = 0.159 × 107 = 0.0159 mF
vo = =
1 + SCR 1 + SCR The plots of magnitude and phase shift
are shown in Fig. 15.120.
Figure 15.120 Phase and magnitude plot of given circuit

26. Obtain the transfer function between input Solution:
and output voltages of Fig. 15.121. vi R v SCR v - v1
v2 = = i , i
1 1 + SCR R
R+
SC
v - vo
= 1 , 2v1 = vi + vo
R
v i + vo v SCR
= i ,
2 1 + SCR
2vi SCR
vo + vi = ,
1 + SCR
Figure 15.121
774
2vi SCR
vo = - vi ( -1) 2 + (w CR) 2
1 + SCR = - =1
( 2SCR - 1 - SCR)vi 1 + (w CR) 2
=
1 + SCR Phase shift = 180° tan1 w CR tan1 wCR
( SCR - 1)vi = 180° 2 tan1 w CR
=
1 + SCR The plots of its magnitude and phase-shift
vo -1 + jw CR are shown in Fig. 15.122.
SCR - 1
or, = =
vi 1 + SCR 1 + jw CR
Figure 15.122 Phase and magnitude plot of given circuit
27. What value of the resistance RB will pro- for RA = RC = RD = 1 KW. What will be the
vide balance of the bridge yielding Vo = 0 value of output voltage, if now RB is set to
0.5 K?
Figure 15.123
Solution: VB12 12VB
V2 = =
5VRD 12 + 10 22
VB = = 2.5 V
RC + RD V A Vo Ê 1 1 ˆ
+ = V1 Á +
5VRB 5VRB 10 12 Ë 10 K 12 K ˜¯
VA = =
RA + RB 1 K + RB
775
12V A 10Vo 12VB tion of the current io coming out from the
V1 = + = , 10Vo operational amplifier flow as the load cur-
22 22 22
rent iL?
= 12(VB VA) , Vo = 1.2 (VB VA),
Solution:
For the condition Vo = 0
-10 ¥ 12
= 12
F 5R IJ , R
. G 2.5 - B
A + RB = 2RB,
For Vin = 0, Vo =
120
= 1 V,
H R +R K A B 1
RA = RB = 1 KW T= = 10 ms
100
F 5 ¥ 0.5 I Vin = 12 = 0,
VO = 1.2 2.5 - = 1.2( 2.5 - 1.67)
H 1.5 K -10 ¥ 01
. cos 2p ¥ 100t
= 0.996 V Vo =
1
28. Sketch the waveform of the output voltage = 1(cos 2p ¥ 100t)V
for the circuit of Fig. 15.124. What por-
Figure 15.124
vo v Hence, io = 1mA cos 2p × 100t, now iL

iL = = io + if = io + o , = io (max) if = 1 mA 0.1 mA = 0.9 mA
RL RF
Hence, total iL(max) = 0.9 mA + 0.9 mA
Vo V V V V = 1.8 mA.
io = - o = o - o @ o
RL RF 1 K 10 K RL 29. Determine the output voltage vo for the cir-
V RF i f cuit shown in Fig. 15.125.
io = o =
RL RL
RF Vi
= ¥
RL R1
10 K 12
= ¥ = 1 mA (max),
1 K 120 K
12
ii = = 0.1 mA = if ,
120 K
iL = io if = 1 mA 0.1 mA = 0.9 mA Figure 15.125
776
Solution: or, Vo = (2 1.99)1.99 = 0.02 V

V -V 30. Show that the system shown in Fig.
4V ¥ 100 V - V1
V2 = = 2 V, I = 1 0 15.126 is a double integrator. In other
200 100 99 words, prove that the transfer gain is given
V1F 1
+
1
=
I 4 V
+ o vo -1
H100 99 K
100 99 by
vi
= 2 2 2 , assume an ideal op-
C R S
4 ¥ 99 Vo ¥ 100
or, V1 = + =2V amp.
199 199
Figure 15.126
Solution: R/2
Y12B = -
I2 1 R R
I2 + I3 = 0, Y21A = , I2 = Y21A Vi, + +
Vi S 2 C 2 2 SC 2SC
I3 R/2 R/2
= Y12B, =- =-
1 R 1 + SCR
Vo +
S 2 C 2 SC S 2C 2
I3 = Y12BVo, ViY21A + VoY12B = 0
RS 2 C 2
=-
VO Y 2(1 + SCR)
or, = - 21A . In T-network, Z1
Vi Y12 B VO Y
and Z2 are series elements and Z3 is Hence, = - 21 A
shunt element. Vi Y12 B
2( SCR + 1) 1
Z =- =- 2 2 2
Y12 = Y21 = - 3 2 2
2 R( SCR + 1) RS C R S C
DZ
Z3 31. Obtain the voltage transfer function be-
=- tween output and input voltages of
Z1 Z2 + Z2 Z3 + Z3 Z1 Fig. 15.127. When switch is open, the op-
Now, amp does not draw any current and hence
1 / 2 SC I2 = 0.
Y21A = -
R R Solution:
R2 + +
2 SC 2 SC
1 / 2 SC 1
=- =-
2 2R 2 R( SCR + 1)
R +
2SC
777
Solution:
Figure 15.127
Figure 15.128
Vi - V1 V - VO Vi R2
= 1 , V1 =
R1 R2 R1 + R2 When the control signal is high, it reduces
the channel width and provides very large
VO R1 resistance to provide open circuit, thus V1
+
R1 + R2 = V2 = Vi.
Vi R1 VO R1 VO R1
V1 = Vi = + Hence, = = 1.
R1 + R2 R1 + R2 Vi R1
Vi ( R1 + R2 - R2 ) V R 33. Find the condition of input voltage for
= O 1 making the LED ON in Fig. 15.129.
R1 + R2 R1 + R2
Solution:
VO R
or, = 1 = 1. 10 ¥ 10
Vi R1 V1 = = 5 V.
20
When the switch is closed, the non-invert-
Hence, LED will glow if Vi > 5 V.
ing input terminal is pulled to ground and
hence its gain
R2
= - .
R1
32. Obtain voltage gain under the control of
voltage applied at the gate of the JFET
in Fig. 15.128. When control signal = 0,
the JFET offers minimum drain resistance
and hence non-inverting input terminal Figure 15. 129
is pulled to approximately ground. Thus, 34. What will be the value of input voltage Vi
VO R such that the LED in Fig.15.130 starts
=- 2.
Vi R1 glowing.
LED will glow if Vi > 5 V.
778
Figure 15.130
Figure 15.132
35. An op-amp with a slew rate of 1.5 V/ms
has been used as an inverting amplifier with 1 0.5
gain of 10. What is the maximum input sig-
nal if the frequency of input signal is
Vo = -
RC
t = 120 s.
z
( - 0.5)dt = 12 =
5
dt ,z
1 kHz?
38. The switch was closed initially for 0.5
MSR MSR minutes and then opened. What will be the
wmax = , Vm =
Vm w max input voltage if the output in Fig. 15.133 is
initially 0 and 5.4 V after the switch is
1.5 0.159 ¥ 1.5 opened.
= =
10 -6
¥ 2p ¥ 1 K 10 -3 1 V
= 0.2385 × 103.
Vo = -
RC z
Vi dt = - i t = 5.4
RC
Vi
=- 30
36. Calculate the voltages V1 and VO in Fig. 500 ¥ 10 3 ¥ 30 ¥ 10 -6
15.131.
Vi
=- 30 = 2Vi
2 ¥ 10 Ê 50 ˆ 5¥3
V1 = = 1 V , VO = Á 1 + ˜ 2 V
20 Ë 20 ¯ 5.4
or, Vi = = 2.7 V
=7V 2
Figure 15.133
39. A differential amplifier converted to differ-
ence amplifier has feedback and input re-
Figure 15.131 sistor of equal values as in Fig. 15.134.
What will be the output, if inputs to invert-
37. When will the output get saturated in ing and non-inverting terminals are 1.5sin
Fig. 15.132? w t and 1.5 cos w t.
779
Solution: VO = 8.94 × 0.1 = 0.894 V = Vm

Vo = V2 V1 = 1.5cos w t 1.5sin wt @ 0.9 V
= 1.5(cos wt sin wt)
1 1
= 1.5 ¥ 2( cos w t - sin w t )
2 2
p p
= 1.5 ¥ 2(cos cos w t - sin sin w t )
4 4
Ê pˆ
= 2.12 cos Á w t + ˜
Ë 4¯
Figure 15.135
41. What is the relationship between resistors

R and R1 and R2 in Fig. 15.136.
Solution:
R = R1||R2.
Figure 15.134
40. The integrator shown in Fig. 15.135 pro-

duces an output voltage = Vo = Vm sin
(100t + f) in response to an input voltage Figure 15.136
of Vi = 0.1 sin(100t). What is the maxi-
mum value of the output voltage?
R / ( SCR2 + 1)
AvCL = - 2
5K
50 K 10
=- =-
5K ( SCR2 + 1) ( SCR2 + 1)
10
=-
( j100 ¥ 0.1 ¥ 10 -6 ¥ 50 ¥ 10 3 + 1) Figure 15.137
10
=- 42. The offset voltage to the circuit of Fig.
( j 0.5 + 1)
15.137 is 1 mV. How much output voltage
10 10
=- =- = 8.94 will be displayed?
e 0.52 + 1
j d 0.25 + 1 i
780
Solution:
1000
± ¥ 1 mV = ±1 V.
1
43. What would be the frequency of oscilla-
1
tion in Fig. 15.138, if C = mF and R =
2p
1 K ? What would be the minimum gain of
the amplifier to sustain oscillations?
1 1
f= =
2pRC 1
2p ¥ 10 3 ¥ ¥ 10 -6
2p
= 103 Hz Figure 15.138
R 2R 44. Calculate the ratio of ON duration to OFF
The minimum gain = 1 + 2 = 1 + 1
R1 R1 duration of the output waveform of circuit
= 3 (R2 = 2R1) in Fig. 15.139.
Figure 15.139
1+ b 1+ b
T1 = RC ln , ln = ln 3 = 1.1
1- b 1- b
For T2 at 15 V, diode is forward biased.
1+ b R = 2 K||2 K = 1 K
T2 = RC ln ,
1- b 1+ b
Hence, T2 = RC ln = 1 ms × 1.1
10 K 1 1- b
b= = , RC = 1 K × 1 mF
10 K + 10 K 2 = 1.1 ms,
= 1 ms , For T1 at +15 V , diode is off, R = 2 K, RC
= 2 K × 1 mF = 2 ms
781
T1 = RC ln
1+ b
= 2 ms × 1.1 = 2.2 ms, =-
RF FGV R
VC - d + 1 + F
IJ FG IJ
1- b R1 H 2 R1 K H K
Hence,
T1
=
2.2 ms
=2
FG R3 V
VC + d
IJ
T2 1.1 ms H R2 + R3 2 K
45. Obtain CMRR for the circuit shown in L R + F R + R I F R I OPV
= M- F 1 F 3
Fig. 15.140. MN R GH R JK GH R + R JK PQ
1 1 2 3
C
R3V2
V+ =
R3 + R2
= V
+M
L R + F R + R I F R I OP V
F 1 F 3 d
V1 RF V R
MN R GH R JK GH R + R JK PQ 2
1 1 2 3
= + O 1 ( R + RF ) R3 - RF ( R2 + R3 )
R1 + RF R1 + RF = 1 VC
R1 ( R2 + R3 )
For V1 = 0 , Vo2 = 1 +
FG RFIJ
V+ ( R1 + RF ) R3 + RF ( R2 + R3 ) Vd
H R1 K +
R1 ( R2 + R3 ) 2
= 1+
FG RF IJR3
V2 Vo VO
H K
R1 R2 + R3 ADM = =
Vd VC = 0
Vd
R
For V2 = 0 , Vo1 = - F V1 ( R1 + RF ) R3 + RF ( R2 + R3 )
R1 =
2 R1 ( R2 + R3 )
Vo = Vo1 + Vo2
VO VO
R R
= - F V1 + 1 + F
FG R3
V2
IJ ACM =
VC
=
VC
R1 H
R1 R2 + R3 K Vd = 0
Vd V ( R1 + RF ) R3 - RF ( R2 + R3 )
=
V2 = VC + and V1 = VC - d R1 ( R2 + R3 )
2 2
A
Hence, CMRR = DM
ACM
( R1 + RF ) R3 + RF ( R2 + R3 )
=
2{( R1 + RF ) R3 - RF ( R2 + R3 )}
(91)100 + 90(101)
=
2{( 91 ¥ 100 - 90(101)}
( 9100 + 9090) 18190
= = = 909.5
2(9100 - 9090) 10 ¥ 2
46`. Obtain the output voltage of the amplifier
Figure 15.140
shown in Fig. 15.141
1
Vo = Vo1 + Vo2 vo1 = -
RC z
v s dt = - vs dt z
z
vo1 = 2 vs dt - 2v2 - 2v3
782
Figure 15.141
47. The output voltage of Schmitt trigger R
VUT = - ( - VSAT )
drawn in Fig. 15.142 is limited to 10 V and dR
5 V connecting suitably chosen Zener di- 1
odes across the output. What are the upper = - ( -5 ) = 0.5 V
10
trip and lower trip voltages of the circuit?
R 1
VLT = - VSAT = -10 = 1 V
dR 10
48. Obtain the output voltage for input voltage
vi = sinwt applied to the circuit in Fig.
15.143.
Solution:
For vi > 0 V, diode is reverse biased, no
loop closes. vo = vi
For vi < 0 V, diode is forward biased, loop
Figure 15.142 closes. vo = vi
Figure 15.143
49. Obtain the output voltage of Fig. 15.144.
What is the name of this circuit?
Solution:
For Vi > 0, D1 is forward biased and D2 is
reverse biased, Vo = 0.
For Vi < 0, D1 is reverse biased and D2 is
R
forward biased, Vo = - 2 Vi . The circuit
R1
is a half wave rectifier and conducts for
negative half cycle only. Figure 15.144
783
IO
50. What is the ratio of current in
Ii
Fig. 15.145.
RL
IO = I i
RL + R
Figure 15.146
52. What is the value of the output voltage in

Fig. 15.147.
Figure 15.145
V1 V1 - V01 V1 - V2
51. Obtain the value of RA such that VO = + + =0
2 2 1
V2
- 2V1 in Fig. 15.146. V01 V2
3 2V1 = + = 0.5 V01 + V2
2 1
10 KV2 V110 V0 5
V+ = = V = + V1 = 0.25V01 + 0.5 ¥ 2 V = 1 V
10 K + RA 15 15
or, V01 = 0
2V V
= 1 + 0
3 3 F 1 + 1 + 1IV
At node 2,
or,
30V2
= 2V1 + VO ,
H 1 2 2K 2
10 + RA
30V2 V0 V1 V1
VO = - 2V1 = + +
10 + RA 2 1 2
V 30V2 or, 2V2 = 0.5V0 + 1
Vo = 2 - 2V1 = - 2V1
3 10 + RA 4 -1
1 30 or, VO = =6V
or, = , RA = 90 10 = 80 KW 0.5
3 10 + RA
Figure 15.147
784
d 2 vin that D represents a frequency

53. Show that ii = D in Fig. 15.148 dependent negative resistance.
dt 2
assuming all op-amps are ideal. Also show
Figure 15.148 Riordan circuit

The circuit of Fig. 15.148 can now be S 2 C1C2 R2 R4
analyzed for its input impedance as ii = vin
R3
vi = v 2 = v4
d 2 vin
(vi v1) = Z1i1 = Z1ii = D ,
dt 2
(v2 v1) = Z2i2 = Z2i3 = (vi v1) CC R R
D= 1 2 2 4.
Z1 R3
= Z1ii, i3 = - ii 2
Z2 ii S C1C2 R2 R4
=
(v2 v3) = Z3i3 = (v4 v3) = Z4i4 , vin R3
Z -w 2 C1C2 R2 R4
i4 = - 3 i3 =
Z4 R3
v4 = vi = Z5i5 = Z5i4 = negative conductance.
Z3 Z1 54. Find out the output voltage vo for the cir-
= Z5 ¥ ii , cuit in Fig. 15.149.
Z4 Z2
Z2 Z4 V2 3 1
ii = vin V+ = , V = V1 + Vo
Z1Z3 Z5 2 4 4
1 = 0.75V1 + 0.25Vo
If Z1 = ,
SC1 0.5 0.75
Z2 = R = Z4 = Z3, and Z5 Vo = V2 - V1
0.25 0.25
1
= are substituted in above, then = 2V2 3V1
SC2
785
Figure 15.149
55. Obtain the output voltage of an op-amp FG 2R IJ
summer shown in Fig. 15.150. Vo = 1 + ( -2 + 2 + sinwt ) = 3 sinwt
H R K
2R
Av = 1 + =3
R
Figrue 15.150
56. Circuit of summing integrator
(15.12a)
57. Circuit of summing differentiator
(15.12aa)
16
Regulated Power Supplies
16.1 Introduction
Almost all electronic equipment (communication, instrumentation, control and data processor) and its
sub-systems require stabilized dc power supplies of different voltage levels. To cite an example, all PCs
require ± 5 V, ±12 V dc supplies. Similarly, analog circuits using operational amplifiers, instrumentation
amplifier, analog to digital converter, digital to analog converters, etc. require ±12 V or ±15 V. The
industrial control loops work on 24 V dc. The RADAR units require 10 KV 15 KV dc power supplies.
The power ratings of these dc supplies may vary from a few watts to a few kilowatts. Hence, we must
know the requirements of dc power supplies. A dc power supply must meet the following requirements:
∑ Good line regulation
∑ Good load regulation
∑ Higher conversion efficiency
∑ Higher power density for reduction in size and weight
∑ Less harmonics in input and output waveform for reduction in filter size
∑ Higher reliability
The regulated (stabilized) dc power supply family can be categorized as in Fig. 16.1.
The common terminology used for these dc power supplies are:
Regulated Output
The output dc voltage of the supply must remain constant within a specified limit, usually 1% or better.
%&%
Figure 16.1 DC power supply family
Isolation
The output terminals of dc supplies must electrically be isolated from the input power source which is
generally ac supply, i.e. mains. This isolation permits different ground voltage levels in different sections
of any electronic equipment or system/sub-systems.
Multiple outputs
We know that different sections of any electronic equipment may require different voltage levels of
positive as well as negative polarities. The positive and negative voltage levels must also be isolated from
each other, as well as from the ac mains.
Supervisory circuits
Different levels of dc voltages may be required in different sections of electronic equipment/systems at
different time in a desired sequence that must be controlled with the help of logical supervisory circuit.
Load regulation
An ideal dc power supply must be able to supply a constant voltage between its output terminals, no
matter what current is drawn from it. However, the output voltage of practical power supply does not
remain constant, rather it changes with variation in the load current IL. Generally, the output voltage
drops with increasing load current. The power-supply specifications include a full load current IFL
rating, which is the maximum current that can be drawn from it within the tolerance limit of its output
voltage. The terminal voltage at full-load current IFL is called the full-load voltage VFL. Similarly, the no-
load voltage VNL is the terminal voltage when zero current is drawn from the supply. In other words, it
is called the open circuit voltage. One of the measures of power-supply performance is in terms of how
well it is able to maintain a constant voltage between its no-load to full-load conditions. It is referred to
as load regulation and is expressed as
VNL - VFL
% Load regulation = ¥ 100 (16.1.1)
VFL
Line regulation
The line regulation is another measure of the ability of a power supply to maintain a constant output
voltage with the corresponding change in the mains voltage. In this case, it is a measure of the sensitiveness
%&&
in the change of the output voltage for the corresponding changes in input or line voltage. This specification
is usually expressed in percent as
DVo Vo
% Line regulation = 100% per volt. (16.1.2)
DVi
The above definition is based on the assumption that the load current remains constant.
Voltage regulator
A voltage regulator is a device or combination of devices, designed and combined to maintain the output
voltage of a power supply constant to the extent possible. It can be considered as a closed-loop system
because it monitors output voltage and generates appropriate feedback that automatically increases or
decreases the output voltage as per the necessity to compensate for any tendency in change of the
output voltage. Thus, the purpose of a regulator is to eliminate any variation in output voltage that might
otherwise occur because of changes in load, line (input) voltage or changes in temperature. Thus, the
output voltage of a dc power supply might depend on:
∑ Load current variation
∑ Input voltage variation
∑ Temperature changes
In other words, the output voltage is expressed as the function of three variables: input voltage, Load
current and ambient temperature, i.e. Vi, IL, T and is mathematically expressed as
Vo = f (Vi, IL, T) (16.1.3)
The output dc voltage is partially dependent on the change in the load current IL, partially dependent
on the change in the input voltage Vi, and the temperature change. The total change DVo in the output
voltage Vo can be expressed mathematically as the sum of the partial contributions of all parameters.
Thus, DVo can be written as
∂Vo ∂V ∂V
DVo = DVi + o DI L + o DT (16.1.4)
∂Vi ∂I L ∂T
DVo = SViDVi + SRoDIL + STDT (16.1.5)
Each of the derivatives in Eqn. 16.1.5 is a measure of regulation or stabilization of the voltage regulator
with reference to a particular variable. Thus, the input regulation or stabilization factor SV is expressed
as
∂Vo
Svi = (16.1.6)
∂Vi I L and T = K
The load regulation is the ratio of change in the output voltage to the change in the load current. Its
dimension is of resistance hence, it is termed as output resistance Ro or internal resistance of the voltage
regulator. It is expressed as
∂ Vo
Ro = (16.1.7)
∂ IL Vi and T = K
With increasing load current output voltage decreases as indicated in Fig. 16.2, therefore the negative
sign is there.
%&'
It also indicates that Ro must be taken positive when Vo decreases for increasing Io = IL or vice
versa.
The temperature coefficient ST of the voltage regulator is expressed as
∂ Vo
ST = (16.1.8)
∂T Vi and I L = K
Figure 16.2 Output dc voltage versus load current variation
A dc power supply is normally rated in terms of output dc voltage, output dc current or the output
voltage and current product. The output voltage in some power supply units can be varied within a
certain voltage range with the condition that the units can be loaded upto a certain maximum permissible
current limit.
16.2 Classification of Voltage Regulators

The power supplies used in electronic equipment are more or less charged with the task of controlling
or regulating electrical power. The word control is used here because whether we rectify, invert,
regulate, or change the voltage or current levels, some control technique is involved. Such control of
power delivered to a load can be achieved only by absorbing surplus power in any control device. In
order to be energy conscious, the very concept of surplus or throwaway power deserves close scrutiny.
The voltage regulator employs different approaches to control the power and can be classified as
∑ Linear (dissipative) voltage regulator
∑ Switch-mode (non-dissipative) voltage regulator
16.2.1 Linear (Dissipative) Voltage Regulator

The control elements in linear voltage regulator circuit are generally active devices, i.e. power transistor
which is always operated in the active conduction mode. The active device senses the output of the
circuit continuously and adjusts its conduction to maintain output voltage at a desired value. Here the
power dissipation is function of input voltage and load fluctuations. The linear voltage regulator can be
of feedback or non-feedback type. The following voltage regulators are important in this category.
Non-feedback types
∑ Zener diode regulator and
∑ Emitter follower regulator
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Zener diode and emitter follower regulators are the simplest regulators. These are normally employed
only for the following:
∑ Coarse regulation with low cost
∑ Low output current requirements
∑ Where efficiency is not an important consideration
Feedback types
∑ Series regulator
∑ Shunt regulator
The control element in series type regulator is in series between input and output circuits and can
work with much lower voltage than the output voltage but the total load current passes through it.
Hence, it is suitable for low current and high voltage regulation needs. In shunt type regulator, the
control element is parallel to the load so it passes only a fraction of the total load current but works at full
load voltage. Hence, it is suitable for high current and low voltage applications.
Advantages
The Zener diode regulator circuits have been discussed in Chapters 2 and 3. Zener regulators are
preferred because they are simple, light in weight, reliable, and they regulate over a range of current.
Disadvantages
∑ Poor efficiency due to loss in series resistance and diode itself
∑ Stabilized voltage is equal to breakdown voltage and cannot be varied
∑ Breakdown voltage is dependent on temperature
16.2.2 Stabistor
Stabistor is the name given to the regulation achieved by a diode in forward biased region. It is well
known that the diode current beyond cut-in voltage rises very sharply for fractional change of voltage
across its base-emitter voltage. The typical change in voltage of 0.2 V brings a change in few tens of
mA. The single diode regulator in forward bias case is shown in Fig. 16.3(a). A number of diodes as
shown in Fig. 16.3(b) may be connected in series to increase the regulated voltage.
Figure 16.3(a) Stabistor type regulator Figure 16.3(b) String of diodes as stabistor
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16.2.3 Emitter Follower Regulator

The Zener diode regulator has inherent limitation of current. In other words, the current rating of the
diode must be higher than the load current. This condition cannot be met by one Zener diode. Hence,
other type of regulator is required. The emitter-follower circuit shown in the Fig. 16.4 is a simple non-
feedback type of transistor voltage regulator. The transistor that is connected in series with the unregulated
input and regulated, output voltages is hence called the series type of voltage regulator.
Here, the control element is the n-p-n transistor, often called the PASS transistor because it conducts
or passes total load current of the regulator. It is usually a power transistor and mounted on a heat sink
in a heavy-duty power supply that delivers substantial current. The Zener diode provides the reference
voltage, and the base to emitter voltage of the transistor is the control voltage.
Figure 16.4 Emitter-follower voltage regulator

The Zener diode is reverse biased and that reverse current is furnished to it through resistor R.
Although Vi is unregulated, it must remain sufficiently large and R must be sufficiently small to keep the
Zener in its breakdown region. Though the unregulated input voltage Vi varies VR remains essentially
constant.
VZ = VR = VBE + Vo (16.2.1)
VBE = VR Vo (16.2.2)
As VR = VZ is constant, any change in Vo must cause a corresponding change in VBE in order to
maintain the equality valid. When Vo decreases, VBE increases that causes the n-p-n transistor to conduct
more heavily and produce more load current.
Notice that the transistor is used essentially in an emitter-follower form. The load is connected to the
emitter and the emitter follows the base that is connected to a constant voltage VR. Hence, it is known
as emitter-follower regulator. For successful regulator operation, the pass transistor must remain in its
active region, Vi must not drop to a level so small that the Zener is no longer in its breakdown region and
the Zener voltage VR should be highly independent of both current and temperature.
Vi = VCE + Vo (16.2.3)
16.3 Series Voltage Regulator

Of all linear regulators, the most commonly used, s the series regulator. The shunt regulator is generally
used for a constant load whereas the series regulator is normally used for a variable load. Since most of
the applications require variable load, the series type regulator is taken up here in details.
A stabilized voltage supply essentially consists of the following blocks:
∑ Transformer
∑ Rectifier
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∑ Filter
∑ Regulator
∑ Load
The above discussed blocks are connected in series as shown in Fig. 16.5.
Figure 16.5 Voltage regulator block diagram

As we have already discussed rectifiers and filters in Chapter 4, we start our discussions on regulators.
A series regulator is divided into five blocks as arranged in Fig. 16.6(a). The voltage regulation is taken
up here for load current IL variation. Comparing a sample of the output voltage w.r.t. a fixed reference
voltage performs regulation against the load current variation. The difference of the two is amplified and
is used to control the series control element T1. A simple circuit of a series regulator is shown in Fig.
16.6(b). Different blocks of Fig. 16.6(a) are taken up one by one in detail.
Fig.ure 16.6(a) Block diagram of series regulator
Figure 16.6(b) Series regulator

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16.3.1 Sampler
It is a simple resistive voltage divider across the regulated output Vo as indicated in Fig. 16.7. The
sample voltage VS derived from the sampler is
Ê R2 + R p 2 ˆ Ê R2 + R p 2 ˆ
VS = Á V = Á V (16.3.1)
Ë R1 + R2 + R p1 + Rp 2 ˜¯ o Ë R1 + R2 + R p ˜¯ o
The resistances R1, R2, and Rp1 + Rp2 = Rp should be made of the same material and are kept at the
same temperature.
16.3.2 Reference Element

Zener diodes are used as constant voltage reference element because its breakdown voltage remains
relatively constant over a wide range of reverse current. The effect of temperature, reverse current and
diode resistance on the breakdown voltage are the parameters that are taken into consideration for the
selection of the Zener diodes as the reference element.
Figure 16.7 Sampler, Zener reference and equivalent circuit
The complete equivalent circuit of the Zener diode in the Zener region includes a small dynamic
resistance rz in series with a battery voltage equal to the Zener breakdown potential VZ as indicated in
Fig. 16.7. However, for all practical applications it is assumed that the external resistances are much
larger than the dynamic resistance of the Zener diode and hence rz = 0. Thus, the Zener diode is equated
by a constant voltage VZ only. From Fig. 16.7.
I3R3 + rz (I3 + I2) + VZ = Vo (16.3.2)
As I3 >> I2 Eqn. 16.3.2 reduces to
I3R3 + rzI3 + VZ = Vo (16.3.3)
(R3 + rz) DI3 = DVo (16.3.4)
As, DVZ = 0, rz DI3 = DVR (16.3.5)
Hence, combining Eqns. 16.3.4 and 16.3.5 yields
b R + r g DrV
3 z
z
R
= DVo
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DVR rz r
= = z (16.3.6)
DVo R3 + r/z R3
It is clear from Eqn. 16.3.6 that the change in the reference voltage can be made very small w.r.t. the
change in the output regulated voltage by selecting the Zener diode having very low dynamic resistance.
16.3.3 Comparator
The comparator compares a sample of the output voltage w.r.t. the constant reference voltage VZ and
produces output proportional to the difference of the two signals. The CE amplifier or emitter coupled
differential amplifier is normally used as a comparator. The choice depends upon the degree of regulation
and temperature stability required. The simple comparator with its equivalent circuit is drawn in
Fig. 16.8. From this figure
VBE2 + Vz = V s (16.3.7)
Since IB2 = f(VBE2) = f(Vs Vz) (16.3.8)
Figure 16.8 Comparator and its equivalent circuit
Suppose output voltage Vo decreases with increase in the load current IL. The VBE2 will also decrease
accordingly and hence the base current will also decrease as shown in Fig. 16.9.
Figure 16.9 Variation of IB2 with forward bias VBE2

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Since IC is proportional to IB, the decrease in IB2 will force IC2 to decrease proportionately.
16.3.4 Amplifier
The amplifier raises the level of the difference signal to such a value that is sufficient to drive the series
control element. The single transistor T2 in most of the cases as shown in Fig. 16.8 performs the
function of comparison and amplification.
Figure 16.10 IC2 with VCE2
16.3.5 Series Control Element

The series control element interprets the amplified difference signal and makes appropriate adjustment
to maintain the output voltage constant. The circuit of a series control element shown in Fig. 16.6 (b) is
redrawn as Fig. 16.11.
Figure 16.11 Series element working
If the output (load) voltage Vo decreases due to increase in the load current IL, then the forward bias
between base-emitter of T2 = VBE2 = Vs Vz also decreases. Since the base current of T2 = IB2 = f(VBE2)
= f (Vs Vz) it decreases consequently from IB2 to I*B2 as indicated in Fig. 16.9 and IC2 will also
proportionally decrease. The base current of T1 = IB1 = I4 IC2 = I4 bIB2. As I4 remains constant
because input voltage for the time being assumed to be constant, decreasing IC2 forces IB1 to increase.
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The collector current of T1, thus, increases proportionately from IC1 to I*C1 as shown in Fig. 16.10. It is
evident from this figure that the quiescent point shifts from Q1 to Q2 resulting in decrease of VCE1 to
V*CE1. Thus, the part of the voltage released by VCE1 (DVCE = VCE1 V*CE1) is gained by the output
voltage Vo . Hence, any attempt to decrease in the output voltage is compensated by the equal amount of
voltage released by VCE1. The process of regulation is shown by block diagram in Fig. 16.12.
Figure 16.12 Regulation process of output voltage
As Vi is constant, Vi = VCE1 + Vo, With decreasing value of Vo, VCE1 has to increase. Following
characteristics are essential for the selection of the series control element
∑ VCE(min) ≥ Vi(max) Vo(max)
∑ IC(max) ≥ Io(max)
∑ PC(max) ≥ Vo(max)*IC(max)
16.3.6 Pre-regulator
The pre-regulator is included as one of the blocks in the voltage regulator to take care of the input
voltage variations. It provides the constant current to the junction of the base of T1 and the collector of
T3. A simple pre-regulator circuit is shown in Fig. 16.13.
Figure 16.13 Pre-regulator
As Vz is connected across R3 and VBE3, the collector current of Vz is independent of the change in
VBE3 caused by the input voltage variation. In other words, transistor T3 is working as a constant
current source.
Hence, IC3 = IE3 IB3 = IB1 + IC2 (16.3.9)
Vz = VEB3 + R4IE3 (16.3.10)
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VZ - VBE 3
or R4 = (16.3.11)
IE3
As Vz is constant, forward bias to the base of Vo is also constant. Hence, IB3, IC3, and IE3 will be
constant even if the input (mains) voltage varies. The value of R5 may be obtained as
Vi (min) - Vz - I z rz
VCE = and I5 = IZ + IB3 (16.3.12)
I z + I B3
A simple circuit of series voltage regulator with pre-regulator is shown in Fig. 16.14.
The prominent disadvantages of linear type dc voltage regulators are
∑ less efficient
∑ large in size due to large transformer
∑ heat sink for series transistor to dissipate heat due large power loss
Figure 16.14 Series voltage regulator with pre-regulator
16.4 Shunt Regulator

The shunt regulator is another form of the feedback regulator as described by blocks in Fig. 16.15(a).
In sharp contrast to the series regulator, the control device in this case is in the shunt path. Although the
shunt regulator is not as efficient as the series regulator, it has advantages of
∑ greater economy
∑ simplicity
This type of regulator is usually recommended for relatively constant load. Each of the blocks in the
shunt regulator performs the same function as its counterpart in the series regulator. The control element
in parallel to the load maintains a constant load voltage by shunting more or less current from the load.
The simplest shunt voltage regulator circuit is shown in Fig. 16.15(b).
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Figure 16.15(a) Block diagram of shunt regulator
Figure 16.15(b) Shunt voltage regulator using BJT and operational amplifier
It is convenient to think that the control element in shunt regulator works as a variable resistor. When
the load voltage decreases, the resistance of the control element is made to increase thus, diverting less
current from the load hence, the load voltage rises. Conversely, when the load voltage increases, the
resistance of the control element decreases, and more current is shunted away from load. The source
resistance on the unregulated side forms a voltage divider with the parallel combination of the control
element and RL. Thus, when the resistance of the control element increases, the resistance of the parallel
combination increases and by voltage divider action the load voltage also increases.
Applying KVL results in VBE = VL Vz = Vo Vz = Vo Vz
As Vz = constant, VBE µ VL, and IB µ VBE, IC = b IB, IC µ IB, decreasing VL forces IC to decrease and
IL increases. As IC decreases, the drop across VCE = VL increases to the original value. On the other
hand VL = Vz + VBE, as Vz = constant, decreasing VL decreases VBE and hence IB and IC decrease.
Decreasing IC increases the drop across VCE to reach the original value hence VL remains constant.
Resistances R1, R p and R2 form a voltage divider as depicted in Fig. 16.15 (b) that feeds a voltage
proportional to VL back to the non-inverting input terminal of the op-amp This voltage is greater than the
reference voltage VR applied to inverting input. The output of the amplifier is a positive voltage proportional
to bVL VR. If VL decreases, the amplifier output decreases and transistor T conducts less heavily and
hence VCE = VL becomes more. One important advantage of shunt regulator circuit is that it has inherent
current limiting capability. It is clear that the load current cannot exceed Vi /R4 which is equal to the
current flow through R4 under short-circuited condition of output. Since the load current must flow
through R4, the power dissipation in the resistor may be quite high, especially under short circuit
conditions. This condition makes it necessary to include some circuit arrangements that can take care of
it automatically. These types of circuit arrangements are called current limiting circuits.
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16.5 Current Limiting Techniques

We know that all general purpose dc power supplies should have short-circuit or overload protection
facility. One form of protection circuitry is called current limiting whereby specially designed circuitry
limits the current that can be drawn from the supply to a certain specific maximum, even if the output
terminals are short-circuited. In other words, the protection circuit provides a shunting path to it.
It is well known that the voltage regulator circuits offer very low output resistance. Therefore, it is
necessary to introduce protective measures for the over load current in the circuit. This is particularly
important in the emitter-follower regulator and the series regulator circuits wherein the load current can
vary over a wide range. In the series regulator circuit, overloading can result in a permanent damage to
the series-pass transistor T1, if it is not properly protected. For example, when the output terminals are
shorted, full input voltage Vi appears across transistor T1 and the resulting current out of it = Vi /Ro
passes through it. In such a case, the power dissipated in T1 can become several times the transistor
ratings. Hence, it is essential that the protective means are introduced to it to become effective almost
instantaneously.
A series fuse is sometimes used in an attempt to protect the series-pass transistor from excessive
power dissipation under output short circuit or overload conditions. This cannot provide the required
protection under all conditions of overload, largely because the thermal time constant of the fuse is
much larger than that of power transistor and also one has to replace the blown fuse. In order to avoid
these difficulties electronic protection techniques (also known as electronic fuses) have been preferred
to ensure reliable and safe operation of the regulator. There are many approaches to solve this problem.
Two of the important techniques are:
∑ Constant current limiting circuit
∑ Foldback current limiting circuit
An effective current limiting circuit must respond fast enough to protect the series-pass transistor by
limiting the current to a safe value as well as to protect the load from any further damage and permit the
regulator to return to normal operation as soon as the overload condition is removed.
16.5.1 Constant Current Limiting

Fig. 16.16(a) shows a popular current limiting circuit incorporated into regulator using operational
amplifier. As the load current increases, the voltage drop across the resistor Rsc increases. Since Rsc is
in parallel to the base emitter junction of the transistor T2, if the load current becomes excessive enough
to produce a drop of more than 0.7 V (cut-in voltage for the silicon transistor) across Rsc, then T2 starts
conducting substantial collector current. As a consequence the current that would otherwise enter into
the base of T1 is diverted through T2. The pass transistor this way is prevented from supplying additional
load current. The maximum (short-circuit) current that can be drawn from the dc supply is equal to the
current that is essential to develop a voltage drop of 0.7 V across Rsc, i.e.
0.7
IL(max) = (16.5.1)
Rsc
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Figure 16.16(a) Series voltage regulator with current limiting circuit
Figure 16.16(b) Load-voltage-current characteristic
The output voltage of a current-limited regulator decreases, if the load resistance is made smaller than
that which would draw maximum current at the regulator output voltage. Figure 16.16(b) shows a
typical load-voltage-load-current characteristic for a current-limited regulator. The characteristic shows
that load current may increase slightly beyond IL(max) as the output approaches a short circuit condition
(Vo = 0). Note that T2 in Fig. 16.16(a) supplies a small amount of additional current to the load once
current limiting takes place.
Example
What would be the condition of output voltage for a 30 V regulated dc power supply with Rsc = 3.5 W
in Fig. 16.16(a) for (a) RL = 1 KW, (b) 100 W, (c) 10 W, (d) 1 W.
Solution
We should first calculate the maximum current that the power supply can deliver under short circuit
condition, i.e.
0.7
IL(max) = = 0.2 A. Under any load condition the output current of the power supply cannot be
3.5
more than this value.
30
(a) The load current for 1 KW is = IL = = 0.03 A
1K
Since, VBE2 < IL(max) (= 0.2A), the output voltage remains constant.
&
(b) For RL = 100W, the load current will become,

30
IL(0.1 K) = = 0.3A. Since, IL(0.1 K) = 0.3A > IL(max) (= 0.2A), current limiting will take place
100
and the output voltage will drop, i.e.
Vo = IL(max) RL = 0.2 ¥ 100 = 20 V
Similarly the output voltage for 10 W and 1 W load can be obtained as
(c) Vo(10 W) = 0.2 ¥ 10 = 2 V
(d) Vo(1 W) = 0.2 ¥ 1 = 0.2 V
16.5.2 Foldback Current Limiting

Another form of over current protection called foldback limiting is used to reduce both the output
current and voltage if the load resistance is made smaller than that which would draw a specified
maximum load current IL(max). Figure 16.17 shows a method to add foldback limiting to the basic
current limited regulator.
Figure 16.17 Series voltage regulator with foldback limiting circuit
We have already seen that the output voltage of current-limited regulator decreases as the load
resistance is made smaller. In foldback limiting, this decrease in output voltage is sensed and is used to
further decrease the amount of current that flows to the load. Thus, as load resistance decreases beyond
a certain minimum, both load (output) voltage and output current approach towards zero. The foldback
characteristic is shown in Fig. 16.18. The principal purpose of foldback is to protect a load from over
current, as well as protecting the regulator itself.
Notice the similarity of this circuit to the current-limited regulator circuit shown in Fig. 16.16(a) the
only difference is that the base of T2 is now connected to the junction of R4 R5 voltage divider. Writing
KVL around the loop, we find that
VBE2 = VRsc VR4 (16.5.2)
Notice that VR4 will increase or decrease as the load voltage increases or decreases. When the load
current increases to its maximum permissible limit, VRsc becomes large enough to make VBE approximately
0.7 V, i.e. VRsc become large enough to exceed the drop across VR4 by about 0.7 V = VRsc VR4.
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Figure 16.18 Load-voltage-current foldback characteristic
At this point, current limiting occurs exactly similar to the current-limiting regulator in Fig. 16.16. If
the load resistance is now made smaller, the load voltage will drop. As the load voltage drops, VR4 also
drops. Consequently, a smaller value of VRsc is required to maintain VBE = 0.7 V. Since VBE remains
essentially constant at 0.7 V, a smaller load current must flow to produce further drop across R4.
Further decrease in load resistance produces further drops in load voltage and a further reduction in load
current. This way cumulative action takes place and both voltage and current become ultimately zero.
This is called foldback limiting. If the load resistance is restored to its normal operating value, the circuit
resumes normal regulator action.
Example
What should be the value of Rsc in Fig. 16.17 in order to limit the value of maximum current to 1 A ? The
circuit of this figure maintains a constant voltage of 5 V with R4 = 1 KW and R5 = 9 KW.
Solution
R4
VR4 = Vo = 0.5 V, VBE = 0.7 V = VRSC 0.5 V.
R4 + R5
or VRSC = 0.7 + 0.5 = 1.2 V,
VR
SC 1.2
Hence, Rsc = = = 1.2 W
I L(max) 1
The above shortcomings could be resolved to a large extent by integrating these components in the
form of an IC chip. The chip with fixed and variable dc voltage outputs is commercially available. These
chips have been given the name Linear IC Voltage Regulators.
16.6 Linear Voltage Regulators : First Generation

An excellent dc voltage regulator can be built using an op-amp, Zener diode, two resistors or one
potentiometer and one or more transistors. In 1868, Fairchilds semiconductor division integrated all of
these components (plus others) into single IC and called it the A722 monolithic voltage regulator.
Because of its flexibility it is used even today. It does, however, require a number of support components,
has minimal internal protection circuitry and requires the user to add boost transistors for more current
capability and resistor for limiting short-circuit current. The race was on to make a three-terminal fixed-
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voltage regulator. National Semiconductor won with the LM309, in a close finish with Fairchilds 7800
series. The LM309, and 7805 have three terminals. To use one, all you have to do is connect an
unregulated supply between its input and common terminals. Then connect a load between the output
and common and the design is complete. (Connect a decoupling capacitor across both input terminals
and output terminals to improve performance). These devices have internal protection circuitry that will
be discussed separately.
16.6.1 Second Generation

The success of the ±5 V regulators changed the philosophy of many system designers. There was no
need to have a central regulator supplying current to each circuit board in the system and suffering the
large I2R loss. Now each printed circuit board could have its own on board local regulator. The local
regulator also protected its ICs against line voltage transients.
The ±5 V regulator is very successful and an array of three-terminal regulators of 6, 8, 9, 12, 15, 18,
and 24 V and their negative counterparts are available. One can even think that devices act as a dc
transformer. Now, if we need a 15 V regulator to furnish 1A, we simply need one IC.
16.6.2 Third Generation

Linear IC regulators became popular but created serious problems for Original Equipment Manufacturers
(OEMs) to stock it. How do you stock all these sizes, and how do you make enough to suit the growing
number of voltage requirements? The LM117 was the first successful superior-performance adjustable
positive ICvoltage regulator. The LM117 adjustable negative regulator followed it.
Classification
Linear IC voltage regulators are classified by the following four characteristics:
∑ Polarity : negative, positive, or dual tracking
∑ Terminal count: three-terminal or multiterminal
Fixed or adjustable output voltage: standard fixed voltages are ±5 V, ±6 V, ±9 V, ±12 V, ±15 V,
±18 V and ±24 V
Output current
Typical output current capabilities are 0.1 A, 0.2 A, 0.25 A, 0.5 A, 3 A, 5 A, 10 A, 18 A and 21 A.
Common characteristics
The instantaneous voltage at the input of an IC regulator must always exceed the dc output voltage by
a value that is typically equal to 0.5 V to 3 V. This requirement is called minimum instantaneous input-
output voltage or simply headroom.
Self-protection circuits
The internal circuitry of these devices senses the load current. If the load current exceeds a specified
value, the output current is automatically limited until the over load is removed. They also measure both
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their input-output difference voltage and load current to be sure that no disallowed combination occurs.
If it does, the regulator shuts down. This feature is called safe area protection. Finally, these regulators
even measure their own temperature to see if the heat sinks in them properly. If the internal die temperature
exceeds 150°C to 175°C, then it should be shut down. Once the fault is removed the regulator goes back
to work.
External protection
Despite the well-designed internal protection circuitry, misuse, sabotage or certain failures of external
circuits can still damage regulators. The measures one can take to safeguard against these eventualities
are given in the data sheets of a particular regulator.
Ripple reduction
Manufacturers of linear IC regulators specify their performance by a parameter called ripple rejection. It
is the ratio of the peak-to-peak input ripple voltage to the peak-to peak output ripple voltage. It is
typically 60 dB or more. That is a reduction in ripple voltage of at least 1000:1. For example, if 5 V of
ripple are at the regulators input, less than 5 mV appear across the load.
Adjustable IC Regulator 723
This type of voltage regulators provide precise regulation of the output voltage for both line and load
variations. Generally it provides continuously adjustable output voltage within a specified range, current
limiting, and remote shut down. Its pinout is shown in Fig. 16.19.
Figure 16.19 Pinout of 723 adjustable regulator
The 723 is a general-purpose IC voltage regulator. It is an example of a popular and very versatile
adjustable (variable) regulator. It can be connected to produce
∑ positive or negative outputs from 2 V to 37 V
∑ can provide either current limiting, or fold back limiting
∑ with an external pass transistor it can handle load currents up to 10 A
∑ can be used as switching regulator
Table 16.1 shows electrical characteristics of the 723. Note the terminal labeled VREF at the output of
the voltage reference amplifier. This is an internally generated voltage of approximately 7 V that is
available at an external pin.
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Table 16.1 Electrical characteristic of the 723

Parameter Min Typical Max
Input voltage 9.5 V ----- 40 V
Output voltage 2V ----- 37 V
Input output voltage difference 3V ----- 38 V
Short circuit current limit (Rsc = 10 W, Vout = 0 V) ---- 6.5 mA ----
Standby current drain( IL = 0, Vin = 30 V) ---- 2.3 mA 4 mA
Long term stability ---- 0.1 %100 Hr ----
Ripple rejection (50 Hz to 10 kHz, CREF = 0 pF), ---- 75 dB ----
(50Hz to 10 kHz, CREF = 5 pF) ---- 86 dB ----
Average temp. (55°C £ TA £ +125°C) ---- 0.002 %/°C 0.0015%/°C
Coeff. of output voltage( 0°C £ TA £ 70°C) 0.003 %/°C 0.0014%/°C
Output noise voltage (BW = 100 Hz to 10 kHz, CREF --- 20 mVrms ----
= 0pF), (BW = 100 Hz to 10 kHz, CREF = 5pF) 2.5 mVrms
Current from VZ --- ---- 2.5 mA
Current from VREF ---- ---- 15 mA
Internal power dissipation ---- ---- 800 mW
Reference voltage 6.8 V 7.15 V 7.5 V
Line regulation (Vi = 12 V to 15 V, ( 0° C £ TA £ 70°C), ---- 0.01%VO 0.1%VO
(Vi = 12 V to 40 V 0°C £ TA £ 70°C) ---- 0.1%VO 0.2%VO
Load regulation (IL = 1 mA to 50 mA) ---- 0.03%VO 0.15%VO
(55°C £ TA £ +125°C) 0.6%VO ----
In order to set a desired regulated output voltage, the user connects this 7 V output or an externally
divided-down portion of it to one of the line inputs of the error amplifier. The error amplifier is a
comparator that compares the externally connected reference to a voltage proportional to Vo. Depending
on whether the reference is connected to the non-inverting or the inverting input, the regulated output is
either positive or negative. For normal positive voltage regulation, the unregulated input is connected
between terminals labelled V(+) and VC, and V() is connected to ground. Note the transistor labeled
current limiter in Fig. 16.20(a).
By making external resistor connections to the CL(current-limiter) and CS (current senser) terminals,
either the current-limiting circuit or the foldback circuit can be implemented. The current limiter performs
the function of T2 in each of those figures. Of course, the terminals can be left open if no limiting is
desired. Fig. 16.20(b) shows the 723 regulator connected to maintain its output at any voltage between
+2 V and +7 V.
The voltage at NI terminal can be obtained from the simplified functional diagram of Fig. 16.20(b).
&$
Figure 16.20(a) Block diagram of 723 a djustable regulator
The internal circuitry of the 723 linear variable regulator contains two sections not connected to each
other. The first section contains a Zener diode, a constant current source and a reference amplifier. The
constant current source forces the Zener diode to operate at a fixed voltage. The reference amplifier
provides a fixed output voltage of approximately 7 V. The second section of the IC contains an error
amplifier, a series pass transistor T1 and a current limiting transistor T2. The error amplifier compares
the sample of the output voltage at INV input terminal w.r.t. the reference voltage VREF connected at the
NI terminal. The error signal controls the conduction of the series pass transistor T1. Its various terminals
are taken out on its 14-pin DIP package or 10-pin metal can package.
Figure 16.20(b) Simplified functional block of the 723
The difference between VNI and the output voltage Vo that is directly connected to the INV terminal is
amplified by the error amplifier. The output of the error amplifier drives the series pass transistor T1 so
as to minimize the difference between the VNI and VINV inputs of the error amplifier. Since, T1 works as
an emitter follower,
VI NV @ Vo (16.6.1)
From Fig. 16.20 (b), (VNI VINV)Aerro amp = Vo (16.6.2)
Vo
Now VNI = + Vo @ Vo (16.6.3)
Aerror amp
VREF R2
VNI = Vo = (16.6.4)
R1 + R2
&%
7.15R2
From data sheet, VREF = 7.15 V, then Vo = (16.6.5)
R1 + R2
It is clear from Eqn. 16.6.5 that the regulated output voltage cannot be more than 7.15 V. For larger
voltage than 7.15 V, a different circuit of Fig. 16.20(c) is arranged.
We see from the specifications in Table 16.1 that VREF may be between 6.8 V and 7.5 V. Therefore,
the actual value produced by a given device should be measured before selecting values for R1 and R2,
if a very accurate output voltage is required. Notice that the full (undivided) output voltage Vo is fed
back to the Inverting input INV through R3. For maximum thermal stability R3 should be set equal to
R1||R2.
The NI terminal in Fig. 16.20(b) is connected to VREF through R3, i.e.
VNI = VREF, (VREF. VINV)Aerror amp = Vo
Figure 16.20(c) Low voltage (100 mV to +7 V and > 5 V) regulator using 723
or VREF = VINV +
Vo
@ VINV =
FG R2 IJ V
o (16.6.6)
Aerror amp H R1 + R2 K
or
FG
Vo = 1 +
R1IJ
VREF (16.6.7)
H R2 K
It is clear from Eqn. 16.6.7 that the regulated output voltage will always be higher than 7.15 V. The
circuit shown in Fig. 16.20(c) is connected to provide current limiting, where,
0.7
IL(max) = (16.6.8)
Rsc
The 100 pF capacitor shown in the Fig. 16.20(c) is used to ensure circuit stability. When the circuit
is connected to provide foldback limiting, a voltage divider is connected across VOUT in Fig. 16.20(c).
The CL terminal on the 723 regulator is then connected to the middle of the divider, instead of VOUT.
&&
16.6.3 Current Boosting 723 Regulator

The maximum current capability of the 723 regulator is 140mA. In certain applications this value of
current is not sufficient. Hence, a current boosting transistor is used as depicted in Fig. 16.21 for the
purpose. The current in this figure from the output VO of the regulator drives the base of the transistor.
The unregulated dc voltage Vi supplies collector current. The emitter current IE = bIB = bIo. Thus the
load current IL = IE = bIo. This indicates that the output current of the voltage regulator 723 is not IO, but
b times IO that is achieved by connecting an external transistor as in Fig. 16.21.
Figure 16.21 Current boosted low voltage regulator
16.6.4 Positive Voltage Series IC Regulator 78XX

Unlike linear voltage regulator 723, 78XX series is popular type of fixed positive voltage regulator. The
78XX series as well as LM series are three terminal positive voltage regulators with number of voltage
options as indicated in Table 16.2. These ICs are designed as fixed voltage regulators and with adequate
heat sinking can deliver output currents in excess of 1A. Although these devices do not require external
components, such components can be used to obtain adjustable voltages and currents to the same
extent. These ICs also have internal thermal overload protection and internal short-circuit current limiting.
The proper operation of Fig. 16.22 requires a common ground between input and output voltages VI
and VO called dropout voltage. Furthermore, the capacitor CI is required if the regulator is located at an
appreciable distance from a power supply filter. Even though CO is not needed, it may be used to
improve stability and the transient response of the regulator. These regulators can also be used as
current sources.
Figure16.23 shows a typical connection diagram of the 7805 as a 0.5A current source. The current
supplied to the load is given by the equation
VR
+ IQ
IL = (16.6.9)
R
where, IQ = quiescent current in amperes {typical value for 7805C may be = 0.5A from electrical
characteristic presented in Table 16.3.
&'
Table 16.2 Voltage Options
Device Output Max. Input Min. Input

Type Voltage Voltage (V) Voltage
(V) (V)
7805 5 35 7.3
7806 6 35 8.3
7808 8 35 10.5
7810 10 35 12.5
7812 12 35 14.6
7815 15 35 17.7
7818 18 35 21 XX in 78XX indicates output voltage value.
7824 24 40 27.1
Figure 16.22(a) 78XX series regulator application, package, current source

(Courtesy: Motorola Semiconductor)
Table 16.3 Electrical characteristics of the 7805 voltage regulator
Characteristics Condition Min. Typical Max.

Output voltage Tj = 25°C 4.8 V 5V 5.2 V
Line regulation Tj = 25°C, 7V £ Vin £ 1 V ---- 3 mV 100 mV
Tj = 25°C, 8V £ Vin £ 12V ---- 2 mV
50 mV
Load regulation Tj = 25°C, 5 mA £ Iout £ 1.5 A ---- 15 mV 100 mV
Tj = 25°C, 250 mA £ Iout £ 750 mA ---- 5 mV
50 mV
Output voltage 7 V £ Vin £ 20 V, 5mA £ Iout £ 1A 4.75V ----- 5.25 V
P £ 15 W
Quiescent current Tj = 25°C ----- 4.2 mA 8 mA
Quiescent current with line ----- ----- 1.3 mA
(Contd.)
&
Characteristics Condition Min. Typical Max.

Change with load ----- ----- 0.5 mA
Output noise voltage TA = 25°C, 10 Hz £ 1 £ 100 kHz ----- ----- 40 mV
Ripple rejection f = 120 Hz, 8V £ Vin £ 18 V 62 dB 78 dB
Dropout voltage Iout = 1A, Tj = 25°C ----- 2V -----
Output resistance f = 1 kHz ----- 17W -----
Short circuit current Tj = 25°C, Vin = 35 V ----- 750 mA -----
Peak output current Tj = 25°C ----- 2.2 A -----
Average temperature Iout = 5 mA, 0°C £ Tj £ 120°C ----- 1.1 mV/°C -----
Coefficient of output voltage
16.6.5 Current Boosting 7805 Regulator

We know that the current capability of three terminal voltage regulators can be increased by connecting
a series pass transistor in parallel with the regulator as depicted in Fig. 16.23 From this figure
Iin = IGND + IL = IL = Io without T1 ON (16.6.10)
So long as the load current is low, voltage drop across R1 = VR1 < 0.7 V which is not sufficient to turn
ON the transistor. With increasing value of load current VR1 increases continuously. As soon as VR1 ≥
0.7 V, the transistor becomes ON.
Figure 16.23 Boosted current capacity of 7805
Example
IL = Io = 100 mA = Iin. (T1 = OFF)

Hence, VR1 = 0.1 A ¥ 7 W = 0.7 V. This value of voltage across the VBE of Si transistor will be able to
turn it ON. Once the transistor becomes ON, the load current is IL = Io + IC
VEBb ON g VBE ON
For regulator, IB = Iin IR = Io = Io + (16.6.11)
R1 R1
&
bVBE (ON) bVEB(ON)

IL = Io + bIB = (1 +b)Io + = (1 + b)Io (16.6.12)
R1 R1
Since, Io(max) of 7805 = 1A, VEB(ON) = 1V, and b = 20, then
IL = 1(21) - 20
F 1 I = 21 2.857 = 18.183 A.
H 7K
Thus, Fig. 16.23 can boost a current from 1A to 18.183A using transistor T1.
16.6.6 Negative Voltage Series IC Regulator

The 79xx series of voltage regulators are complements to the 78xx series devices, i.e. this series pro-
vides negative voltage. These negative regulators are available in the same voltage options as that of the
78xx series, as shown in Table 16.4. Figure 16.24 shows the package types in which the 79xx series
voltage regulators are available.
Table 16.4 Voltage Options
Device Output Max. Min. Input
type voltage Input voltage
voltage
7902 2 V 35 V 4.3 V
7905 5 V 35 V 7.3 V
7905.2 5.2 V 35 V 7.5 V
7906 6 V 35 V 8.4 V
7908 8 V 35 V 10.5 V
7909 9 V 35 V 11.5 V
7912 12 V 35 V 14.6 V
Fig. 16.24 79XX series regulator package
7915 15 V 35 V 17.7 V
(Courtesy: Motorola Semiconductors)
7918 18 V 35 V 20.8 V
7924 24 V 40 V 27.1 V
16.6.7 Three Terminal Adjustable Voltage IC Regulator

Many manufacturers using fixed voltage regulators like the 78xx and 79xx series in their line of products
had to stock and hold an inventory of each voltage regulator in order to have shelf accessibility to a
specific device. This approach increased the inventory and proved to be very costly especially when
production stops due to the unavailability of a particular voltage regulator. Adjustable voltage regulators
are better alternatives to the huge inventory and increasing production costs as they are a single device
satisfying voltage requirements from 1.2 V upto 37 V. In addition, these types of regulators have
performance monitoring and reliability advantage over the fixed types.
Three terminal regulators have following characteristics:
∑ Vo provides fixed voltages specified by the manufacturers
&
∑ |VIN| ≥ |VOUT| + 2 V
∑ Io(max) : load current can vary maximum upto rated current
∑ Thermal shutdown : IC regulators have built-in temperature sensor that turns OFF the IC when
it becomes too hot (nearly 125°C to 150°C). The output current drops and unless cooled
significantly, does not provide more current.
In view of the above points, adjustable voltage regulators have become more popular because of
versatility, performance and reliability. The LM317series is the most commonly used general-purpose
adjustable voltage regulator.
16.6.8 Three Terminal Adjustable Positive Voltage Regulator

In this section we learn about the LM317 series adjustable three terminal positive voltage regulators. The
different grades of regulators, in this series are available with output voltage of 1.2 V to 37 V. and output
current from 0.1 A to 18.12 A as shown in Table-16.5. The symbolic representation of the LM317
series regulators is shown in Fig. 16.25.
Table 16.5 Voltage options
Device Available Output Vin(max) Ripple Package

VO (V) current (V) rejection
(A) (dB)
LM317 1.2 to 37 1.5 40 80 TO-39
LM317H 1.2 to 37 0.5 40 80 TO-39
LM317HV 1.2 to 37 1.5 60 80 TO-3
LM317HVH 1.2 to 37 0.5 40 80 TO-39
LM317L 1.2 to 37 0.1 40 80 TO-92
LM317M 1.2 to 37 0.5 40 80 TO-202
(a) (b)
Figure 16.25 LM317 package, typical circuit diagram (Courtesy: National Semiconductor Corp.)
Three terminals of adjustable voltage regulators are Vin, Vout, and ADJUSTMENT (ADJ). Figure
16.25 shows a typical connection diagram for the LM317 regulator. From this diagram it is obvious that
LM317 requires only two external resistors to set the output voltage. When configured as shown in this
&!
figure the LM317 develops a nominal 1.25 V referred to as the reference voltage VREF, between the
output and adjustment terminals. This reference voltage is impressed across resistor R1 and since the
voltage is constant, the current I1 is also constant for a given value of R1. Because resistor R1 sets
current I1 it is called the current set or program resistor. In addition to the current I1 the current IADJ
from the adjustment terminal also flows through the output set resistor R2.
The LM317 is designed such that IADJ is 100 mA. Thus, referring to Fig. 16.25, the output voltage Vo
is
Vo = R1I1 + R2(IADJ + I1) (16.6.13)
V
where I1 = ref (16.6.14)
R1
R1 = current I1 setting resistor, R2 = output Vo setting resistor

IADJ = adjustment pin current
Substituting the value of I1 in Eqn. 16.6.14 yields
FG
Vo = Vref 1 +
R2 IJ + I ADJ R2 (16.6.15)
H R1 K
where Vref = 1.25 V = reference voltage between output and adjustment terminals.
However, the current IADJ is very small (100 mA) and constant. Therefore, the voltage drop across
R2 due to IADJ is also very small and can be neglected. In short
Vo = 125
. 1+
FG R2 IJ (16.6.16)
H R1 K
Equation 16.6.16 indicates that the output voltage Vo is a function of R2 for a given value of R1 and
can be varied by adjusting the value of R2. The current set resistor R1 is usually 240 W and to achieve
good load regulation it should be tied directly to the output of the regulator rather than near the load.
Normally, no capacitors are needed unless the LM317 is situated far from the power supply filter
capacitors, in which case an input bypass capacitor C1 is needed as in Fig. 16.26. A 0.1 mF disc or 1 mF
tantalum capacitor is suitable for the input bypassing for almost all applications.
Figure 16.26 LM317 with capacitor and protective diodes (Courtesy: NS Crp.)
&"
An optional output capacitor C3 can be added to improve the transient response. The output capacitor
in the range of 1 mF to 100 mF of aluminum or tantalum electrolyte are commonly used to provide
impedance and rejection of transients. In addition, the adjustment terminal can be bypassed with C2 to
obtain very high ripple rejection ratio that are difficult to achieve with standard three terminal regulators.
A typical value bypass capacitor of C2 = 10 mF have been reported to attain 80 dB ripple rejection at any
output level. When external capacitors are used with the LM317, sometimes it becomes essential to add
protection diodes to prevent the capacitors from discharging through low current points into the regulator.
However, there is no need to use diodes for output capacitors of 25 mF or less. Thus, protection diodes
are included for use with output voltage more than 25 V and higher values of output capacitance.
16.6.9 Three Terminals Adjustable Negative Voltage Regulators

The LM337 series of adjustable negative voltage regulators is a complement to the LM317 series devices.
These negative regulators are available in the same voltage and current options as the LM317 devices.
Table 16.6 shows the different grades of regulators in the series.
Table 16.6 Voltage options of LM337
Devices Available Output Vin(max)(V) Ripple Package

Vo(V) current (A) rejection (C dB)
LM337 1.2 to 37 1.5 40 77 TO39
LM337H 1.2 to 37 0.5 40 77 TO39
LM337HV 1.2 to 47 1.5 50 77 TO3
LM337HVH 1.2 to 47 0.5 50 77 TO39
LM337LZ 1.2 to 37 0.1 40 65 TO92
LM337M 1.2 to 37 0.5 40 77 TO202
The LM117, 217, and 317 are positive voltage regulators whereas LM137, 237, and 337 are negative
voltage regulators.
* Diagram LM337 standard packages (Courtesy: National Seniconductor Corporation)
16.7 Dual IC Power Supply

Operational amplifiers invariably require dual power supplies for its proper working. The dual power
supply can be realized using two regulators:
∑ Positive regulator
∑ Negative regulator
The LM340 15 is a +15 V regulator whereas, LM320 15 is 15 V regulator with its current capabilities
to the maximum of 18.21 A each. These regulators are arranged as in Fig. 16.27 to yield the dual supply
voltage of ±15 V.
Diodes D1 and D2 are used to protect the regulators against input terminals short-circuiting. Diodes
D3 and D4 are used to protect the regulators by not allowing both of them to turn ON simultaneously. If
there is a load between the two outputs, the faster will try to reverse the polarity of the other and cause
it to be latched up unless it is properly clamped. The clamping function is provided by these D3 and D4
diodes. Once the regulators start operating properly, both diodes are reverse biased and no longer these
diodes have any effect on the circuit.
&#
Figure 16.27 Dual regulated power supply
16.8 Switched Mode Power Supply

The Switch Mode Regulators (SMPS) are used in modern digital equipment such as telephone ex-
change, PCs, robotics, etc. to overcome the shortcomings of linear voltage regulators. These systems
require
∑ very compact
∑ light weight
∑ highly energy efficient supplies
Figure 16.28 shows a very simple arrangement of a switch mode power supply (SMPS). In this
system the 50Hz input (mains) voltage is rectified and filtered. Then this filtered dc voltage is chopped
at a very high frequency by a switch. The chopped voltage is applied to the primary of a transformer and
then stepped down to the required level through the secondary winding of transformer. The output of
the transformer is again rectified and filtered to get the required dc voltage.
The output voltage is sensed by a control circuit that supplies a correction signal to the driver circuit
to vary the ON/OFF time of the switch and compensate for any change at the output. The power-
switching device in switch mode power supply is always operated in a switched mode. In other words,
it is operated either in the cut-off or in the saturation region and hence, it is more efficient than the linear
supply. The transformer size more or less determines the overall size of the unit and is drastically
reduced due to energy conversion at high frequency. If the input of the SMPS is dc source like a
battery, solar cell, etc., then the input rectifier is not at all needed and the power supply becomes a dc to
dc switching power supply (dc to dc converter). Comparison between the linear power supplies to that
of the switched mode can be seen in Table 16.7.
&$
Figure 16.28 Switch mode power supply blocks
Table 16.7
Linear Power Supply Switched Mode Power Supply
Good regulation Good regulation
Less noise Less noise
Less ripple More ripple
Less efficient Highly efficient
Big size Smaller size
Low cost High cost
No I/O isolation possible I/O isolation possible
16.8.1 Basic Principle of dc to dc Conversion

A simplified circuit shown in Fig. 16.29 (a) illustrates the working principle of dc to dc converter. The
ON/OFF action of the switch supplies a train of pulses to the load resistor. The supply terminal is
connected to the load during the tON period when the switch is ON. In the duration tOFF, when the
switch is OFF (open), the supply voltage is disconnected from the load. As the switch makes and
breaks, the input dc voltage Vi is chopped at the rate of the switch changing from ON to OFF and vice
versa.
Figure 16.29(a) dc to dc converter

&%
Thus, the chopped voltage is available across the load terminals. The average voltage is
Vi tON Vt
Vo(DC) = = i ON = Vi d (16.8.1)
tON + tOFF T
tON
Where, T = switching period = tON + tOFF and d = duty cycle =
T
In order to increase the dc value a filter circuit is added in Fig. 16.29(a) to result in Fig. 16.29(b).
Figure 16.29(b) dc to dc converter with capacitor filter
A slightly different circuit of a switching regulator and its waveform is shown in Fig. 16.29(c). The
circuit of Fig. 16.29(c) has improved version of filtering circuit as compared to that of the Fig. 16.29(b).
It has an inductor and a free wheeling diode apart from the elements of Fig. 16.29(a). This switch can
be controlled by external electronic circuitry.
Figure 16.29(c) Block diagram and waveform of switching regulator
The average load voltage can be varied in two different ways:

∑ Frequency modulation or variable frequency technique
∑ Pulse Width Modulation (PWM) or constant frequency technique
Variable frequency control
In this method, the switching period is varied by keeping either
∑ ON time tON, constant or
∑ OFF time tOFF constant
PWM control
The switching frequency (f = 1/T) in pulse width modulated type of switching regulator is kept constant
by varying the ON time, tON of the pulse width. In the variable frequency control arrangement, frequency
has to be varied over a wide range to provide the full output voltage range that results in discontinuity
&&
and sluggishness at low frequency. The probability of interference with the signalling and telephone
lines is more. The PWM control gives low ripple and requires smaller size of the filter and has fast
response. The controller design is also simpler for PWM control. The PWM technique is thus, preferred
scheme for DC-DC converters. The strength of the base drive control signal is such that the switching
transition is either fully ON or fully OFF. The intermediate state of conduction does not arise. A crude
PWM controlled circuit of the switch mode regulator is shown in Fig. 16.30.
Figure 16.30 PWM controlled SMPS
Suitably turning the switch ON and OFF results in the desired output voltage. The intermittent
switching of the input power source would have given a similar shape output voltage but for the
smoothening action of the inductor and the free wheeling diode. When the switch is closed, the current
Io flows in the inductor L feeding it to the load resistor RL that is equal to the load current under ideal
condition. This current builds up the magnetic field and stores energy. Briefly the inductor stores energy
when the switch is ON and releases this energy through the free wheeling diode and the load resistance
RL when it is OFF. The current in the inductor tries to continue flowing. The voltage across the inductor
always opposes the input action. In other words, when the switch is ON, the P terminal of the inductor
will be positive and the Q terminal negative. In this duration, the free wheeling diode is reverse biased.
When the switch is OFF, the direction of the induced voltage reverses, i.e. the terminal P becomes
negative and Q positive. Thus, diode is forward biased and provides the path for the stored energy to
release through the load. The output voltage will be the average of the voltage waveform created by the
switch. In order to qualify as a switching regulator, the action of the switch can be random but must
depend upon the output voltage as in the case of the static voltage regulator.
Figure 16.30 incorporates circuitry (not shown) that allows to measuring the output voltage Vo,
comparing against a fixed reference and then create a control signal for the switch. The base of BJT in
an actual situation is connected to the control signal that implements the switching function.
The base drive may have any of the three forms
∑ pulse of constant frequency with variable pulse width in accordance with the output voltage
(variable duty width cycle)
∑ variable pulse of constant width
∑ a combination of the above two methods, though, unpredictable is controlled by the output
voltage
The magnitude of the base control signal is such that the switching transitor is either saturated or cut-
off. The intermediate state conduction does not exist. For given values of the filter elements, i.e. the
inductor L and capacitor C, the higher the value of the switching frequency better would be the filtering
action. This implies that high frequency operation results in smaller values of L and C. This is a highly
desirable condition.
&'
The practical operating frequency ranges in excess of 20 kHz. The upper limit being set by the quality
of the filtering capacitor, the capacitance of the free wheeling diode and the high frequency capability of
the switching transistor. The effort is to design a switching power supply of highest efficiency constructed
with the required load regulation and ripple voltage specification. Here efficiency means the ratio between
output power and the input power. The typical value of 80% to 85% is common. The wasted power
dissipated as heat in switching regulator shall now be discussed. It must be emphasized that since there
are several ways of implementing a regulator design the example taken up here is only the representative
of the particular type.
Working Principle
The Pulse Width Modulator (PWM) circuit controls the ON and OFF time of the electronic switch T1.
The power is supplied from the input voltage to the load through L when the switch is ON in Fig. 16.30.
The potential Vp is approximately Vi (neglecting VCE(sat) of the transistor). Diode D is reverse biased and
C is charging. When T1 turns OFF, the inductor L will force Vp to become negative to keep the current
flowing in it. The diode D will start conducting and the load current will flow through D and L. The
voltage Vp is smoothened through L and C giving a dc output Vo. The current flowing through L is equal
to the nominal DC load current plus some DIL that is due to the charging voltage across it. The waveform
of the SMPS shown in Fig. 16.30 is drawn as in Fig. 16.31.
Figure 16.31 SMPS waveform

Empirically DIL(pp) is set at approximately 40% of Io. The voltage across the inductor is expressed as
DI L dI L
VL = L = L = (Vi Vo) (16.8.2)
Dt dt
T
DIL @ VL (16.8.3)
L
(V - Vo )tON
DIL+ = i and (16.8.4)
L
Vt
DIL = o OFF (16.8.5)
L
Vt
Neglecting the drop across VCE(sat) and i ON . Also assuming DIL+ = DIL yields
T
(Vi Vo)tON = VotOFF
&
Vi tON Vt
Vo = = i ON (16.8.6)
tON + tOFF T
where, T = time period = tON + tOFF. (16.8.7)
The energy output of the circuit in one complete period (T = tON + tOFF) is equal to = ILVoT.
The energy input during the ON interval (tON) = ILVitON (16.8.8)
Since there is no other source of energy and losses are neglected,
ILVoT = ILVitON (16.8.9)
tON Vo
= (16.8.10)
T Vi
tON
The fraction of the time the switch is closed, , is known as the duty cycle. Therefore, under
T
equilibrium condition, the ratio of output voltage to the input voltage is equal to the duty cycle.
tONVi
Vo = (16.8.11)
T
Thus, Vo can be varied or maintained constant with varying Vi or the duty cycle. The variation in the
duty cycle corresponds to the PWM.
As the transistor T1 conducts during tON only
I o (DC)tON
Ii(DC) = (16.8.12)
tON + tOFF
Vi (DC) Io (DC)tON
Pin = Vi(DC)Ii(DC) = (16.8.13)
tON + tOFF
Pout = Io(DC)Vo(DC) (16.8.14)
The efficiency h of the circuit of Fig. 16.30 is expressed as
P Io (DC)Vo (DC)
out(dc)
hmax = = (16.8.15)
P Vi tON I o ( DC ) (VCE ( sat )t ON + VDt OFF )I o(DC)
in(dc) +
T T
Assuming hypothetically for simplification, VCE(sat) @ 1 V = VD (16.8.16)
Vo (DC)
hmax = (16.8.17)
Vi t ON
+1
T
Vo (DC)
hmax = (16.8.18)
Vo + 1
&
In actual practice h will be less than this due to the losses occurring in the series (pass) transistor T1,
freewheeling diode D and filter circuit elements L and C. The theoretical and practical considerations
lead to the value of L given by
2.5Vo (DC)Vi (DC) - Vo (DC)
L= (16.8.19)
Vi (DC) I o( DC ) f
where L is in mH and f is the switching frequency in Hz.
Vo ( DC ) {Vi (DC) - Vo (DC) }T 2
Similarly, the value of C is given by C = (16.8.20)
8DVo(DC)Vi(DC) L
where, DVo(DC) = peak to peak ripple voltage of Fig. 16.31.
16.9 Step-up Switching Regulator

It is possible to use switching circuits to build step-up regulators, i.e. the output voltage is larger then the
input supply voltage. A simple circuit of step up regulator is shown in Fig. 16.32. The output current
consists of an average value IL(DC) and a triangular ripple content as shown in Fig. 16.32.
The peak to peak ripple content is about 40% of IL(DC) which is a heuristic figure. The transistor T1
is used as switch to alternately apply Vi(DC) across the inductor L. During the time tON, transistor T1 is
ON, the energy is drawn from the Vi(DC) and stored in the inductor L. The diode D is reverse biased
when T1 is ON and Io(DC) is supplied from the previous cycle. When T1 opens during tOFF, VC1 will rise
positively to the value required for forward biasing the diode D hence, D is turned ON. The output
current Io(DC) is now supplied through L and D to the load resistor RL and any charge lost from C during
tON is replenished.
Figure 16.32 Switch mode power supply

&
From Faradays law or electromagnetic induction

di
V= L , (16.9.1)
dt
di DI L
In the duration tON, V = Vin and = (16.9.2)
dt tON
Vin tON (V - Vin )t OFF
DIL+ @ , and DIL = o (16.9.3)
L L
It can be assumed that DIL+ = DIL (16.9.4)
VintON = (Vo Vi)tOFF (16.9.5)
FG
Vo = 1 +
tON IJ t +t FG
Vi = ON OFF Vi =
T
Vi
IJ FG IJ (16.9.6)
H tOFF K tOFF H tOFF K H K
In order to determine the input current Iin(DC), i.e. IL(DC), let us assume 100% efficiency.
Hence, Pin = Iin(DC) Vin(DC) = Input power (16.9.7)
Po = Io(DC)Vo(DC) = I oVo 1 +
FG tON IJ (16.9.8)
H T K
For 100% efficiency Po = Pin (16.9.9)
FG
Iin = I o 1 +
tON IJ = I FG IJVo
(16.9.10)
H T K H Ko
Vin
However, the efficiency is never 100% and there will be losses due to the saturation voltage of the
switching transistor T1 and the diode voltage drop VD. The power loss due to these drops is equal to
VCE(sat)Iin = Iin for VCE(sat) @ 1V in t = tON (16.9.11)
VDIo @ Io for VD = 1V in t = tOFF (16.9.12)
Total loss = VCE(sat)Iin + VDIo @ Iin + Io = I o

FG Vo
+1
IJ (16.9.13)
H Vi K
Po = VoIo and Pin = Po + losses = Po + I o
FG Vo
+1
IJ (16.9.14)
H Vi K
Output power Po Vo I o Vo
hmax = = = = (16.9.15)
Input power Ê
Po I o Á
+ 1 +
Vo ˆ FG
V
Vo I o + I o 1 + o
IJ FG V
Vo + 1 + o
IJ
Ë Vin ˜¯ H
V
in K H V
i K
Other losses such as the loss in inductor, loss in capacitor, and the switching losses that can occur
in the transistor and the diode will also come in the picture. In order to determine the value of C
following points must be kept in the mind.
& !
∑ C supplies Io during tON, i.e. when transistor T1 is ON and D is reversed biased.

∑ The voltage change on C during this time will be DVC = DVo which represents the output
voltage of ripple content. As a design rule this output ripple is taken as 40% of Vo(peak to peak).
I o t ON
DVo = (16.9.16)
Co
I O t ON
C= (16.9.17)
DVo
Vin
From Eqn. 16.9.6 tOFF = T (16.9.18)
Vo
tON = T tOFF = 1 -
FG Vin IJ
V - Vin
T = o T (16.9.19)
H Vo K Vo
ÊV
C = IoT Á o
- Vin Vo ˆ
= IO
FG V - V IJ
o in
(16.9.20)
Ë DVo ˜¯ H DV f V K
o o
where C is in Farad, f in Hz and DVo = peak to peak output ripple. The value of inductor is determined
as
DIL = load current measured from peak to peak which is 40% of IL (as a design decision)
DIL = 0.4IL = 0.4IL (neglecting losses) = 0.4 I o

FG V IJ o
(16.9.21)
HV K in
Vin tON
L= (16.9.22)
DI L+
Since Vin is applied across L during tON only.
Vin t ON Vo - Vin
L= and as tON = T (16.9.23)
FV I
0.4 I G J
o
o Vo
HV K in
2.4Vin2 (Vo - Vin )

L= (16.9.24)
Vo2 Io f
Though complicated, the switching regulator is a highly efficient device capable of transforming dc
input power to practically any desired voltage levels. For a given power handling capability, the weight
of a switching regulator is much smaller than its static counterpart and now, with the use of special
purpose integrated circuits meant for switches, output is lesser than that of a good static regulator and
a fair amount of ripple is usually present. In applications where ripple content must be low, it is common
to pre-regulate switching type circuit and then use a static regulator in the final stage. This kind of a
hybrid combination gives the best result to efficiency versus good regulation situation.
& "
From the relationships that have been derived earlier, it is evident that high operating frequency is
desirable as it leads to smaller values of the inductor, reducing weight and overall cost of the switching
regulator. But high frequency operations create problems which affect the quality of the passive and
active components. These components are more costly than the mass-produced parts meant for other
applications that are cheap and can be obtained off the shelf anywhere. The inductor, capacitor and the
diode are the parts which have to be special while the other components are ordinary. A description of
the desirable properties of the switching regulator components follows.
16.9.1 Passive Switching Components

Filter capacitors whose values range from 1mF onwards are of the electrolytic type and the cheapest.
The most easily available variety in this category is the aluminium electrolytic capacitor. Apart from this
advantage, this kind of capacitor has a wide range of voltage and capacitance values. However, this
variety of the capacitor suffers from certain defects as far as its use in a switching regulator is concerned.
Every capacitor can be represented by a circuit combination of a capacitor, an inductor and a resistor.
The inductor comes from the fact that most capacitors are made by wrapping (which behave like turns)
aluminum foil-insulator combinations. Because of the presence of inductance the capacitor will have a
self-resonant frequency so, upto this frequency, the capacitor will essentially offer capacitive reactance.
But, above this frequency, the reactance will be inductive so that it stops behaving like a capacitor.
Ideally it should be possible to charge and discharge a capacitor without any power loss; a resistor
represents the loss that is incurred in real capacitors. It is difficult to quantify this as it depends upon
temperature, operating voltage and age but since this is an important parameter some tests and thumb
rules are used to make an estimate. This impedance offered by the capacitor will strongly depend upon
the value of equivalent resistance near and above the self-resonant frequency. These parameters should
also be taken into consideration at high temperatures. A lesser important factor is the ripple current
carrying rating of an electrolytic capacitor. The ripple currents generate internal heat in the capacitor
that affects the heat sensitive components.
From the above discussion one can see that for applications where the switching frequency is below
10 kHz and for situations where temperature changes are not too high, ordinary Al capacitor can serve
the purpose reasonably well. Improvements in the performance can be made by various circuit techniques,
i.e. several lower valued capacitors can be parallely shunted by a smaller low inductive capacitor such as
ceramic or tantalum type. For operations above 10 kHz specially constructed four leaded stacked type
of electrolytic capacitors can be used. The expensive tantalum electrolytic capacitor is worth considering
when long life and superior performance is expected because it is economical and the large capacitance
values and large working voltage are not available elsewhere. These capacitors outperform A1 ones in
every aspect.
For very high switching frequencies in the region of 50 kHz and higher, electrolytic capacitance is
not considered at all. In such case ceramic and other non-electrolytic varieties are frequently used.
16.9.2 Inductor
The desirable qualities of an inductor are:
∑ Magnetically unsaturable
∑ No dc resistance
& #
∑ No stray parasitic capacitance

∑ No core losses
∑ Large inductance to volume ratio
However, in actual practice, an inductor will have all the imperfections contrary to the points mentioned
above. Compromising and optimizing the values of the parameters to best serve a given situation fabricate
a real inductor. Common core materials are of ferrite made in cup shapes and occasionally toroidal and
molybdenum permalloy in toroidal structures. Suitable air gaps are always provided to avoid abrupt or
premature saturation of the core material. At high switching frequencies the required number of turns is
small and this helps to keep the resistance and stray capacitance of the inductor low. A badly designed
inductor can cause very large peaks of current to flow through the switching transistor or the free
wheeling diode causing these to be destroyed.
16.9.3 Switching Transistor

The operation of transistor switches are, theoretically, so quick that it makes and breaks instantaneously.
Also the voltage drop across it is ideally zero. However, in practice hardly any transistor switch meets
these conditions. The base drive is usually kept so high that it saturates. When the switch, leads to a
situation where the base region of the transistor is flooded with extra carriers, at this point even if the
base drive is removed, these excess charges in the base keep the collector current flowing. It takes a
while (of the order of tens to hundred microseconds) before the base charges, and therefore the collector
current, are removed. This manifests itself in a slower turn-off time whereas the excess base drive is
required to achieve a fast turn off time. So the base signal waveform is carefully designed in order to
help leak the excess base charges during OFF-time. The base signal is actually made negative (and not
zero as we have shown). Apart from the base drive considerations, the Safe Operating Area (SOA) must
not exceed the maximum current and voltage values at any point and also remain within its maximum
thermal dissipation limitation. For critical operation it must be remembered that at elevated temperatures
the SOA shrinks and that faster switching times (on-time) help to somewhat enlarge it. Manufacturers
classify switching transistors separately and provide the extra details pertaining to the rise, storage and
fall times of these units which help a designer to take a decision on the matter of switching frequency
and the nominal duty cycles.
16.9.4 Free Wheeling Diode

For low frequency operations (near dc to about a few kHz), diodes are chosen on the basis of their
current carrying capacity and the reverse blocking voltage rating. The cost is hardly considered since
they are so cheap. However, at high frequencies the same charge storage effects plague diode (as in the
switching transistor). Excess charges are stored during the forward conduction period, much like a
capacitor, which are removed during off-time and the process takes a few to a few hundreds of ms.
This phenomenon causes reverse currents to flow through the diode and thus, increases the ripple
content and extra heat dissipation.
Two processes make fast recovery diodes, each having its own advantages and faults and find
application in areas that best suit their strong points. One way is to add gold as an extra dopant while
& $
fabricating the diodes. Gold acts as charge trapping centre within the semiconductor and thereby reduces
the lifetime of the carriers and help in reducing the storage time. This process however increases the
forward drop of the diode and the reverse leakage current. The Schottky barrier diodes also known as
hot carrier diodes do not involve minority carriers, as do all bipolar devices. Rectification between a
metal and semiconductor interface has an inherently low capacitance and a low forward voltage drop.
This enables the device to work well beyond 100 kHz. Unfortunately, the reverse blocking voltage is
also low and is usually under 30 V.
Between the two types of diodes described above, the areas of application are fairly clear cut. For
low voltage supplies working at a high frequency, Schottky diodes will be most suitable because of their
low forward and backward voltage ratings (gold diodes have high forward voltage drops). When supply
voltages are in the region of 10 V or higher (working at high switching frequencies), the higher forward
drop of gold doped diodes become less significant but their higher reverse blocking voltage becomes
useful and so, in this situation, a gold doped diode will be more suitable.
1. Show that the circuit of Fig. 16.33 produces a regulated dc voltage of +12 V.
Figure 16.33 +12 V regulated power supply

Solution:
capacitor = 2 ¥ 16.2 = 21.85 V
2V
The full wave dc voltage = VDC = m = The minimum voltage required across the
p input terminals of the LM7812 = 14.6 V.
2 2Vrms 2 2 ¥ 18
Hence, with 21.85 Vinput voltage, LM7812
= = 16.2 V will produce 12 V regulated output.
p p
After filtering, the voltage across the 2. For the circuit shown in Fig. 16.34, calcu-
late the unregulated and regulated dc volt-
ages.
Figure 16.34 +5V regulated power supply

& %
Solution: I dc
The maximum voltage appearing across Hence, Vr (peak) = 3 ¥
4 3 fC
the secondary of the transformer is +15 V.
Hence, the full wave rectified voltage = 500 ¥ 10 3
= = 10 V
2 ¥ 15 4 ¥ 50 ¥ 250 ¥ 10 6
VDC = = 9.55 V
p
VDC = Vin Vr (peak) = 20 10 = 10 V
This voltage when filtered by the capaci-
tor, is Here 10 V is the minimum voltage that
will appear across the input terminals
2 ¥ 15
= 2¥ = 13.5 V. of the 7805 regulator to provide 5 V fixed
p voltage.
The 13.5 V is much more than the mini-
4. What would be the maximum value of the
mum voltage required at the input termi-
load current without deviating from pro-
nals of the 7805 regulator to produce 5 V
viding 5 V fixed voltage by Fig. 16.34 with
regulated voltage.
C2 = 250 mF
3. Calculate the minimum value of the voltage
when the circuit of Fig.16.34 is to supply a Solution:
In order to produce the fixed voltage, the
load current of 500 mA with the maximum
input voltage VI ≥ 7.3 V.
voltage appearing across its secondary =
20 V with C2 = 250 mF. Vr(peak) = Vm Vi(min) = (15 7.3) = 7.7 V
Solution: Vr(peak) 7.7
Vrms = = = 4.45 V
Vr(peak) = 3Vrms 3 1732
.
I dc IDC = 4 3 fCVrms
Vrms = ,
4 3 fC = 4 3 ¥ 4.4 ¥ 50 ¥ 250 ¥ 10-6 = 0.381 A
5. Calculate the regulated output voltage for
the circuit shown in Fig. 16.35.
Figure 16.35 Adjustable voltage regulator
VREF VREF ( R1 + R2 )
Vo = R1I1 + R2(I1 + IADJ) and I1 = , Selecting R1 = 250 W, Vo =
R1 R1
As IADJ = 100 mA, IADJ R2 @ 0 + IADJ R2 @ VREF 1 +
FG R2 IJ = 1.25 ÊÁ1 + R ˆ˜
2
H R1 K Ë 250 ¯
& &
R2 10 6. Assuming 2 V is dropped across the 7805

= - 1 = 8 1 = 7, and obtain the value of IL, Vo, VL, the mini-
250 125
.
mum input voltage for R = RL = 10 W,
R2 = 250 ¥ 7 = 1.75 KW 10 W in Fig.16.36.
Figure 16.36 +5V regulated power supply
VR Vo = VL + VR = 5.042 + 5 = 10.042 V
IL = + I GND , from data sheet IGND =
R The minimum input voltage required = Vi
4.2mA and VR = 5 V = Vdrop(7805) + Vo = 2 + 10.042 = 12.042 V
5 DVo vo
IL = + 0.0042 = 0.5042 A 7. Obtain Ro and SV = = for the shunt
10 DVi vi
regulator circuit shown in Fig.16.37(a).
VL = 10 ¥ 0.5042 = 5.042 V,
Figure 16.37(a) Shunt regulator and its equivalent circuit
Solution: r +h
a resistance = z ie
vo vo h fe h fe
ib = , h fei b =
rz + hie rz + hie Now the circuit of Fig.16.37(a) reduces to
The current source h fei b is represented by Fig.16.37(b).
Figure 16.37(b) Simplified equivalent circuit

& '
From Fig. 16.37(b), vo h fe vo v

+ + o = io
Ê 1 1 h fe 1ˆ vi rz + hie rz + hie Rs
ÁË R + r + h + r + h + R ˜¯ vo = R
L z ie z ie s s
Rs (rz + hie )
Ro =
vo DVo 1 rz + hie + Rs (1 + h fe )
= = = SV
vi DVi Rs (1 + h fe ) Rs
1+ + Rs
RL rz + hie = = SRo
The circuit of Fig. 16.37(a) is further sim- 1 + Rs (1 + h fe )/(rz + hie )
plified to obtain the output resistance as 8. Obtain SV and Ro for the emitter follower
Fig. 16.37(b). regulator shown in Fig. 16.38(a).
v
Ro = o
io vi = 0
Figure 16.38(a) Emitter-follower
Figure 16.38(b) Equivalent circuit of voltage regulator
Figure 16.38(c) Equivalent circuit of emitter-follower voltage regulator

&!
Solution: From Fig. 16.38(c), output resistance Ro

From equivalent circuit of Fig. 16.38(b), can be obtained as
Vc R1i1 hieib = ve ve (rz + hie )ib r + hie
Ro = = = z
Here R1 is the load for firing of the Zener ie (1 + h fe )ib 1 + h fe
v =0
diode.
9. Calculate the load voltage, load current and
ve
ie = (1 + hfe)ib = the base current of the series pass transis-
RE tor shown in Fig. 16.39. Also obtain the
F I Zener current.
vc hie ve
vc - R1 - GH = ve JK Vo = Vz VBE = 6 0.7 = 5.3 V
R1 + rz 1 + h fe RL
20 - 6 14 5.3
rz vc ÏÔ h 1 ¸Ô I= = = 0.14A, IL = IE =
= Ì ie ¥ + 1˝ ve @ ve, 100 100 1K
R1 + rz ÓÔ1 + h fe RL ˛Ô = 5.3 mA
R1 + rz R
vc = ve @ 1 ve
rz rz
vi - vc vc vc v
= + ic = + e
Rs R1 + rz R1 + rz RL
vi v vc v
= c + + e
Rs Rs R1 + rz RL
=
FG 1 + 1 IJ v + v c
e Figure 16.39 Emitter-follower voltage regulator
HR R K R
1 s L
5.3 mA
IB = = 106 mA,
F 1 1 IF R I v
= G + J G Jv + 1
e
e 50
H R R KH r K R
1 s z L Iz = 140 mA 106 mA = 139.89 mA
10. For the circuit shown in Fig. 16.40, obtain
R R|F
1 R I r R U| s z s the output voltage and the Zener current.
= SG 1+ J + Vv e
r R T|H
z s R K R R W| 1 1 L
R2
R1 VB = Vo = VBE + VZ
R1 + R2
DVo v v rz = 0.7 + 6.3 = 7 V
SV = = o = e =
DVi vi vi R rR
1+ s + z s
R1 R1 RL FG
Vo = 1 +
R1 IJ
(VBE + Vz )
R1 H R2 K
rz
=
R r FG IJ FG
= 1+
20 IJ
7 = 7 ¥ 1.5 = 10.5 V
1+ s 1+ z
R1 RL H K H 20 + 20 K
10.5 - 6.3 4.2
Iz = = = 4.2 mA
1K 1K
&!
Figure 16.40 Series regulator circuit
Multiple Choice Questions 6. The voltage regulator circuit offers

(a) very high output resistance
1. The regulation of an ideal power supply (b) very low output resistance,
should be (c) low input resistance
(a) 100% (b) 50% (d) high input resistance
(c) 0% (d) 75% 7. The shunt type regulator is suitable for
2. The output voltage of regulator power (a) low current high voltage
supply (b) low current low voltage
(a) increases (b) decreases (c) high current low voltage
(c) remains constant (d) high current high voltage
3. The non-feedback type of voltage regula- 8. In stabistor, the diodes are connected in
tor is (a) forward bias
(a) Zener diode regulator (b) reverse bias
(b) series regulator (c) no bias
(c) shunt regulator 9. The pass transistor is used as the control
4. The regulator which falls into the feedback element in
type is a (a) Zener regulator
(a) emitter follower type (b) emitter-follower regulator
(b) series/shunt type (c) shunt regulator
(c) Zener type 10. The most commonly used regulator cir-
5. The series type regulator is suitable for cuitry is
(a) low current high voltage (a) Zener regulator
(b) low current low voltage (b) shunt regulator
(c) high current low voltage (c) series regulator
(d) high current high voltage (d) emitter-follower regulator
&!
11. The instantaneous voltage at the input of (c) high impedance

an IC regulator must always (d) rejection of transients
(a) exceed the dc output voltage 16. The dual power supply can be realized by
(b) lower than the dc output voltage using
(c) equal to the dc output voltage (a) two positive regulators
(d) none (b) two negative regulators
12. To avoid the increase in the load current (c) one positive and one negative regula-
IC regulators utilize tor
(a) external protection circuits (d) none
(b) self-protection circuits 17. In IC722 voltage regulator, current capa-
(c) current boosters bility can be increased by using
13. The ICregulator that can be used as (a) current limiter
switching regulator is (b) heat sink
(a) IC722 (b) IC7805 (c) current booster
(c) LM317 (d) none (d) none
14. 78xx series regulator are three terminal 18. The ratio of peak to peak input ripple volt-
fixed age to the peak to peak ripple output volt-
(a) positive voltage regulator age is called
(b) negative voltage regulator (a) ripple factor
(c) dual tracking (b) ripple rejection
(d) none (c) ripple voltage
15. In LM317, the adjustment terminal is by- (d) gain
passed with a capacitor to obtain
(a) very high ripple rejection ratio
(b) low ripple rejection ratio

1. (c) 2. (c) 3. (a) 4. (b) 5. (d) 6. (b)
7. (c) 8. (a) 9. (b) 10. (c) 11. (a) 12. (b)
13. (a) 14. (a) 15. (a) 16. (a) 17. (c) 18. (b)
17
Integrated Circuit Timers
17.1 Introduction
Among the integrated circuit family of timers: 555, 556, and 558, the IC555 is the most popular, cheap,
and versatile timer. The Signetics Corporation introduced the bipolar version of the 555 of integrated
circuit timer in the year 1972. Many other companies too have introduced their CMOS version. The 555
is capable of generating stable time delays of the order of microseconds to hours. It uses the supply
voltage in the range of +5V to +18V. It is compatible to both TTL and CMOS circuits.
Figure 17.1(a) Block diagram of 555-timer

&!"
The circuit of the 555 timer consists of two comparators, an SR Flip-Flop and a transistor T14.
Transistor T14 operates as switch as shown in Fig. 17.1(a). One power supply is required for its
operation. Three equal valued resistors R1 = R2 = R3 = 5 K are connected between VCC and the ground
to form a potential divider. These three equal valued resistors provide reference (threshold) voltages at
the input of two comparators, its name, triple 555 has probably been derived from this.
The NE555 is a general purpose timer of temperature ranging from 0°C to 70°C whereas SE555 can
be safely operated in the range from 55°C to 125°C without any drift. The IC555 timer comes in 8-pin
and 14-pin DIL packages as well as in circular TO 99 metal can with 8-leads as shown in Fig. 17.1(b).
The 555-timer comes in dual-package as 556 and a quad-pack of identification No. 558.
Figure 17.1(b) DIL and TO – 99 packages of the 555
Some important applications of the 555 timer are in making frequency divider, pulse generation, linear
sawtooth generation, square wave generation, pulse detector, temperature controller, LED flasher, auto
wiper control, touch-plate controller, photo timers and auto head light controllers, etc.
Working Principle
The Triggered and Reset terminals are active low. In other words, they are activated by low voltages.
The working principle of the 555 timer can be explained using two switches (comparators C1 and C2)
controlling the charging and discharging of externally connected capacitor C through externally connected
resistor R by the supply voltage +VCC. On flipping the first switch (C2) ON, the output Q of the SR FF
becomes high i.e. Q = 1 and Q = 0. This does not switch the transistor T14 into saturation and the
short circuit across the capacitor is not presented. The capacitor C now starts charging through R
towards +VCC. When the voltage at the charged capacitor reaches more than the higher threshold
voltage VTH (2VCC/3 > VTH), second switch (C1) becomes ON that resets the SR FF to produce Q = 0
and Q = 1. The Q = 1 (+VCC) saturates transistor T14 that provides short circuit across the capacitor
and gets discharged through the transistor T14. Thus, two switches (C2 and C1) can be used to control
charging and discharging of a capacitor to produce delay and oscillations.
A comprehensive explanation about comparators (high-gain differential amplifier) is given in Table
17.1. The truth table of SR FF is given in Table 17.2. It clearly indicates that output is high only when
S is high provided R is low. Similarly, the output is low when S is low and R is high simultaneously. No
state change takes place when Sn = Rn = 0. Moreover if Sn = Rn = 1, the state of circuit is undefined,
indeterminate, or ambiguous.
&!#
Table 17.1 Comprehensive description of comparators
Switched ON Non-inverting Inverting terminal Result

terminal
Comparator-2 +VCC/3 = VTL trigger input > + VCC/3 ve output at Comparator C2
(C2) as threshold trigger input < + VCC/3 +ve output at Comparator C2
Comparator-1 VTH > +2VCC/3 +2VCC/3 = VTH +ve output at Comparator C1
(C1) VTH < +2VCC/3 as threshold voltage ve output at Comparator C1
Table 17.2 Truth table of SR-FF

Inputs Outputs Voltages at pins
Sn Rn Qn + 1 Q n+1
0 0 Qn Q n+1 Qn (previous condition)

0 1 0 1 0 ‹ (quiescent condition)
1 0 1 0 1
1 1 x x x (indeterminate)
Nowadays most of 555 timers have pre-set and clear facilities for the internal flip-flop used and
accordingly such timers have a little bit different functional block diagrams. Block diagrams for dual
timer IC556 and 558 are shown in Figs. 17.2(a) and (b). The detailed circuit diagram of IC555 is drawn
in Fig. 17.2(c).
Figure 17.2(a) Functional block diagram of 556

&!$
Figure 17.2(b) Functional block diagram of 558
Figure 17.2(c) Detailed circuit diagram of the LM555 Timer

&!%
17.2 Monostable Multivibrator Using 555

Figure 17.3 is the functional block diagram of a 555 based monostable multivibrator containing a series
connections of one externally connected capacitor (C) and one resistor (R). As the name implies, the
monostable multivibrator has only one stable state and a quasi stable state. In the stable state, the SR FF
remains in the reset condition i.e. S = 0, R = 1, and Q = 0, Q = 1. As Q = 1(VCC), the transistor T14 is
driven to saturation that shorts the capacitor (C) bringing the voltage across the capacitor to nearly zero
volt i.e. vC = 0 V. As vC = 0 V = voltage at pin-6, the comaparator C1 produces its output = VCC (low
state). Hence, reset input R = 0. As the Trigger terminal is left open, it assumes a high voltage (+VCC)
> VTL = VCC/3, the comparator C2 also switches to output VCC (low state). This confirms previously
assumed state i.e. it remains in the previous state of reset logic and output at pin-3 is = 0 V. In order to
trigger the monostable multivibrator, a negative pulse more than VTL = +VCC should appear at the
Trigger input terminal, then the comparator C2 switches to high state (+VCC) to provide the condition
S = 1, R = 0, and Q = 1, Q = 0. Transistor T14 does not operate allowing capacitor C charging
exponentially towards +VCC through resistor R as shown in Fig. 17.4. This is the quasistable state of the
monostable multivibrator. The quasistable state prevails as long as the voltage across capacitor C does
not exceed the high threshold voltage VTH of the comparator C1. At this time the output of the compa-
rator C1 becomes high (+VCC) resetting the output of the SR FF to force Q = 0, Q = 1 and the output
at pin-3 again goes to zero volt. The monostable multivibrator has come back to its stable state and can
accept another negative going pulse for its operation.
Figure 17.3 Functional circuit of mono-stable multivibrator using the 555
The output voltage will be equal to VCC VBE(28) VBE(27) 6.2 KI6.2K = VCC 1.7 V as it is clear
from the detailed circuit of 555 shown in Fig. 17.2(c) and shall be of duration T. The duration T is
&!&
independent of the value of +VCC. Here, it is important to note that trigger pulse duration should be much
shorter in comparison to duration T. It may be noted that once triggered, the output remains in the HIGH
state until time T elapses which depends only on R and C. Any additional trigger pulse coming during
this time will not change state of the output. However, if a negative going reset pulse is applied at the
reset terminal (pin-4) of the 555 during the timing cycle, transistor T25 becomes OFF and T14 becomes
ON. This allows the timing capacitor C to be immediately discharged. The output waveform is shown
in Fig. 17.4.
The charging expression is expressed as
vC (t) = VCC (1 e t/RC) (17.2.1)
2VCC
The charging time T lasts as long as VC (t) = .
3
2VCC
So, VC (t) = = VCC (1 eT/RC) (17.2.2)
3
or, T = RC ln 3 = 1.1RC (Seconds) (17.2.3)
Figure 17.4 Timing pulse

&!'
Figure 17.5 Simplified circuit of monostable multivibrator using the 555

It is clear from circuit that the output of the transistor T2 is directly connected to the input of T14.
This arrangement turns ON T14 immediately avoiding any propagation delay through the FF. Now, even
if the reset pulse is released, the output will still remain LOW until a negative going trigger pulse is again
applied at pin-2. The graph of delays for various combinations of R and C is drawn in Fig. 17.6.
Sometimes the monostable multivibrator circuit of Fig. 17.5 mistriggers at the positive going edge, even
with the presence of the control pin bypassed by the capacitor. A modified circuit shown in Fig. 17.7 is
used to prevent this type of undesirable effect.
The RC differentiator produces the positive and negative pulse at the edges of the triggering pulse.
The positive pulse is bypassed to ground by the diode and only negative pulse is available at pin-2.
Figure 17.6 Graph of delays for combinations of R and C.
Figure 17.7 Monostable circuit to avoid positive triggering

&"
17.2.1 Missing Pulse Detector

Whenever the input trigger pulse becomes LOW, the emitter-base diode of the transistor T22 shown in
Fig. 17.8(a) is forward biased. The capacitor C in Fig. 17.8(a) gets clamped to a few tenths of a volt
(@ 0.2 V) which shorts the capacitor C. The 555 timer is forced into idle state with a HIGH output
voltage VO at pin-3. When the trigger voltage magnitude becomes HIGH, the transistor T22 cuts-off and
capacitor C starts charging. If the trigger magnitude again becomes LOW before the timer completes its
timing cycle, the voltage across C, VC (t), is reset to about 0.2V @ 0V. However, if the trigger voltage V1
does not become LOW before the timer completes its timing cycle, the 555 enters into its normal state
and output voltage VO becomes LOW. The circuit is designed so that the time period of the monostable
circuit RAC is slightly higher than the period of the triggering pulse V1 and it suddenly misses a pulse.
Thus as long as trigger pulse keeps on coming as trigger pin-2, the output remains in high state. If a
pulse misses, transistor T22 cuts-off and the 555 times enters into normal monostable state as indicated
in Fig. 17.8(b).
If the triggering pulse is generated from a rotating wheel, the circuit can indicate when its speed
drops below a predetermined value.
Figure 17.8(a) Missing pulse detector
Figure 17.8(b) Missing pulse detector waveforms
17.2.2 Pulse Width Modulation

Figure 17.9 shows the circuit and associated waveform of the pulse width modulation obtained by
monostable multivibrator using the 555 timer. The application of continuous triggering voltage at pin-2
produces a series of pulses at its output pin-3. Duration of the output pulse depends on the magnitude of
modulating input voltage applied at pin-5. The modulating signal applied at pin-5 gets superimposed with
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already existing control voltage equal to 2 VCC/3 at the inverting terminal of the comparator C1. This
compares with the threshold voltage of Fig. 17.9 and pulse width modulation takes place. The modulating
voltage and the corresponding output waveform are drawn to the right side of the circuit in Fig. 17.9.
We know that the pulse width is dependent on the value of R, C, UTP, and VCC and it is expressed as
Ê UTP ˆ
a = W = RC ln Á1 -
Ë VCC ˜¯
Since the modulating signal (voice or computer data) is capacitively coupled to pin-5, it controls the
UTP and thus Vmod adds to the quiescent UTP. Therefore,
2V 1 W
UTP = CC + Vmod , T = , D=
3 f clock T
Figure. 17.9 Pulse width modulation

In PWM the width of the pulse varies but the period remains the same and is given by the frequency
of the input trigger. As the frequency is the same, the leading edge of the pulse occurs after a fixed
interval of time. The modulating signal does not affect the period T of the trigger input but changes the
width of the pulse. The pulse width is the maximum at maximum positive voltage of the modulating
signal and minimum at the maximum negative of modulating voltage.
17.2.3 Linear Ramp Generator

The circuit of monostable based ramp generator is shown in Fig. 17.10. The resistor R used for
providing a time constant (RC) is replaced by a constant current source using transistor T3. The capacitor
will now be charged linearly by the constant current source.
Figure 17.10 Linear ramp generator

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The capacitor voltage is expressed as
1 t
VC(t) = idt , KVL equation results as VCCR1/(R1 + R2) VBE = (1 + b)IBRE
C Ú0
@ b IBRE = ICRE = IRE
where IB, IC are base and collector currents and b amplification of transistor.
R1VCC ( R1 + R2 )VBE 1 CC - ( R1 + R2 )VBE

RV
T
I= , vC(t) = Ú dt
( R1 + R2 ) RE 0 ( R1 + R2 ) CRE
At time t = T, the capacitor voltage L?J becomes 2VCC /3, then
2VCC R V - ( R1 + R2 )VBE
= 1 CC T,
3 ( R1 + R2 )CRE
2( R1 + R2 )CREVCC
T=
3{R1VCC - ( R1 + R2 )VBE }
The capacitor discharges as soon as its voltage reaches 2VCC/3 that is the threshold of the compara-
tor C1 in the monostable multifunctional diagram. The capacitor voltage remains zero till another trigger
is applied. The waveforms are shown at right side of the Fig. 17.10. The typical component values are:
R1 = 47 K, R2 = 100 K, RE = 2.7 K, C = 0.1 mF, VCC = 5 V.
17.3 Astable Multivibrator Using 555

The functional block diagram of a 555 based astable multivibrator is shown in Fig. 17.11(a). It consists
of a 555 timer and two externally connected resistors (RA, RB) and a capacitor C. The wave shapes of
astable multivibrator is shown in Fig. 17.11(b). Let us assume that the charging starts at the second
positive going pulse i.e. at the starting of TC. The capacitor C starts charging exponentially through
RA + RB towards +VCC till the voltage level across the capacitor C exceeds 2VCC/3. At this moment of
time, the output of the comparator C1 becomes high (+VCC). Simultaneously, voltage across the capacitor
equals 2VCC/3 (more than the low threshold voltage VCC/3). The output of the comparator C2 becomes
low (VCC) i.e. S = 0, R = 1. This resets the SR FF to yield Q = 0 and Q = 1. As soon as Q becomes
high i.e. Q = 1(+VCC), transistor T14 is driven into saturation to provide a short circuit at the junction of
RA and RB. Now, the capacitor C starts discharging through resistor RB. The discharging of the capacitor
prevails till the voltage across the capacitor C becomes VCC/3 = VTL when comparator C2 outputs a high
to set the SR FF to yield Q = 1 and Q = 0. This way, the cycle of charging and discharging repeats.
&"!
Figure 17.11(a) Astable multivibrator using the 555
Figure 17.11(b) Wave shapes of astable multivibrator using the 555
VCC t /( R + R ) C
RS UV
From Fig. 17.11(b),vC(t) = VCC (VCC VTL) expt/(RA + RB )C
= VCC VCC -
e A B
T3 W
At t = 0 the charging starts and continues for t = TC where it reaches to 2VCC/3 and
2VCC V
RS UV
Hence, = VCC VCC CC exp{TC/(RA + RB)C}
3 T
3 W
or
2 RS1 UV
= 1 - 1 - e - TC /( RA + RB ) C
3 T3 W
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or RS1 - 1 UVe - TC /( RA + RB ) C
=
2 - TC /( RA + RB ) C 3 - 2 1
e = =
T 3W 3 3 3
TC /(RA + RB)C 1

or e =
2
or TC = (RA + RB)C ln 2= 0.69(RA + RB)
We see from Fig. 17.11(c) that the output will be low for the period TD. The exponential discharge
from 2VCC/3 stops when vC(t) = VCC/3 at time TD. This equation is expressed as
VCC 2VCC - TD / RBC
vC (t) = = e
3 3
or e TD /RBC = 2
Hence, TD = RBC ln 2 = 0.69RBC
Total period = TC + TD = 0.69(RA + RB)+0.69 RB = 0.69 (RA + 2RB)
Figure 17.11(c) Charging discharging waveform of astable multivibrator
The Pin-3 of IC555 is the output pin and it remains high during the charging time TC of the capacitor
C. In other words, so long as Q terminal of the FF is low, discharge transistor T14 cannot conduct and
at the same time inverter A outputs the inverted Q i.e. a high at the output terminal.
The maximum value of output attained during the time TC = VO (high)
= VCC VBE(28) VBE(27) 6.2 KI6.2 K @ VCC 1.7 V. (17.3.1)
The minimum value of output voltage attained during time TD = VO(low) = 0
TON TC T
The ratio = = C is defined as the duty cycle of the output pulse. This is
TON + TOFF TC + TD T
obtained as
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RA + RB
Duty cycle = d = DT = (17.3.2)
RA + 2 RB
This duty cycle DT is always less than 50%. The circuit of Fig. 17.11(a) has duty cycle over 50%.
For getting the lower duty cycle, the circuit of Fig. 17.11(d) is used wherein C is charged only through
RA.
Figure 17.11(d) Shorter duty cycle astable multivibrator using 555-timer
During discharge time, voltage at pin-7 is near ground potential since T14 is not only ON but actually
designed for saturated operation. Figs. 17.11(e) and (f) show the charging and discharging modes of
astable multivibrator.
During charging interval, voltage across the timing capacitor can be expressed as
2VCC VCC
vc(t) = 1 - e -t /RAC
( ) + . (17.3.3)
3 3
2VCC 2VCC V
At, t = TC, = 1 - e - TC / RAC + CC
d i (17.3.4)
3 3 3
1
e - TC / RAC =
2
TC = RAC ln 2 = 0.693 RAC (17.3.5)

RBVCC
Observe that is the Thevenins equivalent voltage. The discharge cycle starts
RA + RB
2VCC
when vc ( t ) = at t = TC.
3
The vc(t) from Fig. 17.11(f) can be written as
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vc ( t ) =
RS 2V CC
-
RBVCCUV FG IJ
exp
-t RV
+ B CC (17.3.6)
T 3 RA + RBW H Ktd RA + RB
where, t d = ( RA RB )C = Discharge time constant
Figure 17.11(e) Charging mode Figure 17.11(f) Discharging mode
Note that vC (t) in Eqn. 17.3.6 is the voltage across the timing capacitor during the discharge interval.
V
After putting vC (t) = CC and solving for TD results into
3
VCC
=
2VCC RSRV
- B CC exp
-tUV FG IJ
RV
+ B CC (17.3.7)
3 3 RA + RB
T td W H K
RA + RB
R| F 2R - R I U| = ( R
= t CSln G A B
R| F 2R - R I U|
RB )C ln A B
TD
|T H R - 2R JK V|W
d
A B
A S| GH R - 2R JK V|
T A BW
(17.3.8)
TC 0.693RAC 0.693 (1 + RA / RB )
= = (17.3.9)
TD Ê 2 R - RB ˆ ÏÔÊ 2 R ˆ ÊR ˆ ¸Ô
( RA RB )C ln Á A ˜ ln ÌÁ A - 1˜ Á A - 2˜ ˝
Ë RA - 2 RB ¯ ÓÔË RB ¯ Ë RB ¯ Ô˛
Figure 17.11(g) Plot of frequency for combinations of RA + 2RB and C

&"%
Figure 17.11(h) Astable multivibrator with 50% duty cycle
For 50% duty cycle, TC = TD, and solving for RA /RBwe get RA = RB = 2.362. This value of RA /RB does
not come straight. One has to obtain it by iteration. A similar result for 50% duty cycle situation is for
frequency of oscillation and this frequency f is obtained by approximating
T = 2TC = 2RAC ln 2 (17.3.10)
1 1 1 1 0.721
f= = = = = (17.3.11)
T 2TC 2 RAC{ln (2)} 2 ¥ 0.693 RAC RAC
We see from Eqn. 17.3.2 that the duty cycle will always be less than 50% for this circuit. In order to
achieve 50% duty cycle we are forced to make RA= 0. Thus, collector of T14, pin-7 is directly connected
to the power supply, (+VCC) that allows to flow an extra current through T14 which may get damaged
with the excessive current.
A circuit shown in Fig. 17.11(h) allows to set the duty cycle to any value. During charging interval,
the diode is forward biased and provide effective short circuit to RB so that
TC = 0.693RAC
During the discharge interval, transistor T14 becomes ON thereby grounding the pin-7 and diode is
reverse biased so that
TD = 0.693RBC
Hence, total period = T = TC + TD = 0.693(RA + RB)C
RB
Now duty cycle D= and
RA + RB
1 1 1.44
frequency f= = =
T 0.693( RA + RB )C ( RA + RB )C
Here both RA and RB have been taken as variable resistors. However, a small value of fixed resistance,
100 W has been added to both RA and RB to limit the peak discharging current of the transistor T14 when
even the variable resistance accidentally becomes zero.
&"&
17.3.1 Schmitt Trigger

The 555 timer in astable multimode can be used in a Scmitt trigger circuit shown in Fig. 17.12. The two
comparators are tied together and externally biased at VCC/2 through two resistors R1 and R2. Since the
comparator C1 will change state at 2VCC/3 and lower comparator C2 at VCC/3, the bias provided is
centered between these two thresholds. Thus any input signal of sufficient magnitude (> VCC/6 = 2VCC/
3 VCC/2) which exceeds the reference levels causes the internal FF to alternately set and reset providing
a square wave output as shown in Fig. 17.12. It can be seen that unlike the conventional multivibrator,
no frequency division takes place here. In this case the frequency of the output is the same as the
frequency of the input voltage.
Figure 17.12 Schmitt trigger
17.3.2 Pulse Position Modulation

The pulse position modulation can be achieved by applying a modulating signal as indicated in Fig. 17.13
at pin-5 of the 555 timer connected in astable mode. The position of the output pulse varies with the
modulating signal, as the threshold voltage and the time delay are varied.
The output pulse indicates that the frequency is varying leading to pulse position modulation. The
typical component values are RA= 3.9 K, RB = 3 K, C = 0.01 mF and VCC = 5 V.
Figure 17.13 Pulse position modulation

In the pulse positon modulation, both width and period of the pulse vary with modulating signal.
Here, the pulse width and period are expressed as
&"'
VCC - UTP
b
W = - R A + RB C ln g VCC - 0.5UTP
, T = W + 0.693RBC, Space = 0.693RBC
The space here is constant and it is the time between trailing edge of one pulse and the leading edge
of the next pulse. Since, the space is constant, position of the leading edge of any pulse depends how
wide the preceding pulse is. For this reason it is called PPM.
17.3.3 FSK Generation

In digital data communication, shifting a carrier frequency between two preset frequencies transmits
binary coded signals. This type of transmission is called FSK (Frequency Shift Keying) technique. The
555 timer in astable mode of Fig. 17.14 can be used to generate the FSK signal.
Figure 17.14 FSK generation
Let us assume that a standard digital data input frequency signal has the frequency of 150 kHz. When
the input is high, transistor T is cut-off and the 555 timer works in normal astable mode of operation.
The frequency of the output waveform is given by
1.44
fo =
( RA + 2 RB )C
In a teletypewriter using MODEM (modulator-demodulator), the frequency between 1070Hz to 1270Hz
is used as one of the standard FSK signals. The components RA , RB and C can be selected so that fO =
1070 Hz. When the input becomes LOW, transistor T becomes ON and connects the resistance
R across RA. The output frequency now is expressed as
144
.
f1 =
( R A || R + 2 RB )C
The resistance R can be adjusted to set the frequency f1 = 1070 Hz to 1270 Hz.
17.4 VCO With 555

A simple VCO scheme is shown in Fig. 17.15. A transistor (FET or BJT) can be used to replace the
switch, S. The 2N2607 FET can directly be used for S as in Fig. 17.15.
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We observe that output of the timer is connected to the gate of the FET through R3 to turn ON the
FET whenever timer output is at its low state. op-amp. acts as an integrator. A negative voltage at the
dV Vi
input Vi is converted into a positive ramp by integrator circuit. The slew rate of V1 is 1 = .
dt ( R1C1 )
This V1 is fed to 555s threshold terminal. Terminal-5 of 555 is control terminal biased at voltage VZ
fixed by the Zener diode VZ . As soon as V1 reaches VZ, the threshold comparator of 555 switches the
timer output to its low state and switch turns ON making C1 to discharge. Discharge of C1 means
integrator output V1 lowers to approximately zero voltage. However, lower the value of resistance of S,
faster is the discharge rate for certain specific value of C1. When V2 drops to VZ /2, the timer is triggered
to its high state output turning OFF S again so that C1 starts charging and V1 rises. This process repeats
itself resulting in an output voltage whose frequency is proportional to the input d.c. voltage.
Figure 17.15 VCO circuit

Triggering of timer is allowed after C1 is completely discharged through R2C2 delay network only if
R2C2 > RONCI where RON is ON resistance of switch S. The output pulse width TP is given by TP =
0.693R2C2 @ 0.7R2C2. This Tp puts an upper limit on the operating frequency of the VCO. It is interesting
V
to note that the time limits the output of the integrator between 0 and z volts between 0 and (V2 /2)
2
volts, therefore the output frequency f has a relationship with Vz. At, t = T, V2 reaches the value V2/2 at
the rate defined as
Vi
DT = (17.4.1)
R1C1
V2 Vi
= (17.4.2)
T R1C1
1 Vi 2Vi
fo = = = for To >> TP (17.4.3)
To V2 R1C1 VZ R1C1
17.5 Phase Lock Loop (PLL)

These days phase lock loops (PLLs) are available as an inexpensive off the shelf item in the form of
monolithic ICs. The technique of PLL is used for controlling electronically the frequency of satellite
communication system, airborne navigation system, FM communication system, computers etc.
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The basic block diagram of PLL consists of:

∑ A Phase Detector/Comparator
∑ A voltage Controlled Oscillator (VCO)
∑ A Low-pass Filter
∑ An Error Amplifier
The VCO is a free running multivibrator that operates at a set frequency fo, called free running
frequency. If an input signal vs of frequency fs is applied to PLL, the phase detector compares fre-
quency fs and the frequency (fo) of the output voltage VO of the VCO. If two signals differ in the
frequency or phase, an error voltage ve proportional to the frequency or phase difference is generated.
The phase detector is basically a multiplier that produces the sum (fs + fo) and difference (fs fo)
components of frequency at its output. The low-pass filter removes the high frequency component
(fs + fo). The difference frequency component of the signal is amplified and then applied as control
voltage vc to VCO. The signal vc shifts the VCO frequency in a direction to reduce the frequency
difference between fs and fo. Once this action starts, we say that the signal is in the capture range. The
VCO continues to change frequency till its output frequency is exactly the same as the input signal
frequency. The circuit is then said to be locked. Once locked, the output frequency fo of VCO is
identical to fs except for a finite phase difference.
This phase difference generates a corrective control voltage vc that shifts the VCO frequency from fo
to fs and there by maintains the lock. The PLL tracks the frequency changes of the input signal. Thus,
a PLL goes through three stages:
∑ Free running
∑ Capture
∑ Locked or tracking
Phase Detector
Suppose we have a mixer with the input voltages having the same frequency of 50 kHz and 50 kHz.
Then the difference frequency is 0 that represents a dc voltage. In other words, a dc voltage comes out
from the mixer when the input frequencies are equal.
A phase detector can also be defined as a mixer that is optimized for use with equal input frequencies.
It is called a phase detector (or phase comparator) because the amount of dc voltage depends on the
phase angle f between the two input signals. As the phase angle changes, the dc voltage also changes
accordingly. Fig. 17.16(a) illustrates the phase angle between two sinusoidal signals. When these signals
drive the phase detector of Fig. 17.5(b), a dc voltage comes out. One type of phase detector produces
the dc output voltage that varies as shown in Fib. 17.5(c). This figure reveals that when the phase angle
f = 0°, the dc voltage is maximum.
As the phase angle increases from 0° to 180°, the dc voltage decreases and ultimately goes down to
a minimum value Vmin. When f is 90°, the dc output is average of the maximum and minimum outputs.
For example, a phase detector has a maximum output of 10 V and a minimum output of 5 V. When the
two inputs are in phase, the dc output is 10 V. When the inputs are 90° out of phase, the dc output is
7.5 V. When the inputs are 180° out of phase, the dc output is 5 V. The key idea is that the dc output
decreases when the phase angle increases.
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Figure 17.16 (a) Phase angle between signals, (b) phase detector, (c) output of phase detector
VCO
Recall the idea how a 555 timer could be operated as a voltage controlled oscillator (VCO) by applying
a dc voltage to the control input. When the dc voltage in Fig. 17.16(d) increases, the frequency of the
output signal decreases. In other words, a dc voltage controls the oscillator frequency. Typically, the
frequency decreases linearly with an increase in dc voltage as indicated in Fig. 17.16e.
Figure 17.16(d) DC input controls VCO output, (e) VCO frequency inversely proportional to dc input
Many other designs are possible for VCOs. For example, one approach uses an LC oscillator with a
varactor (voltage controlled capacitor). By varying the dc voltage applied to the varactor we can change
the capacitance and control the resonant frequency. The important thing to remember about any VCO is
that an input dc voltage controls the output frequency. Thus, increasing dc control voltage causes the
VCO frequency to decrease.
Phase-locked Loop
Figure 17.17 is the block diagram of a phase-locked loop (PLL). An input signal with a frequency of fs
is one of the inputs to a phase detector. The other input comes from the VCO. The phase detector
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produces signals of sum frequency (fs + fo), the difference frequency (fs fo), harmonics of the
frequencies of the 2-input signals etc.
A low-pass filter filters the output of the phase detector containing frequency (fs fo). This removes
the difference frequency (fs fo) from sum frequency (fs + fo) and the harmonics of input signals (nfs,
nfo). Only the difference frequency (fs fo) (DC voltage) comes out of the low-pass filter. This dc
voltage then controls the frequency of the VCO.
This feedback system locks the VCO frequency on to the input frequency. When the system is
working correctly, the VCO frequency equals fx, the same as that of the input signal. Therefore, the
phase detector has two inputs with frequencies; the phase angle between these inputs determines the
amount of dc output. Figs. 17.17(b) to (d) show the phasors for the input signal and the frequency of
the VCO.
If the input frequency changes, the VCO frequency will track it. For instance, if the input frequency
fs increases slightly, its phasor rotates faster and the phase angle increases as shown in Fig. 17.17(c).
This means less dc voltage will come out of the phase detector. The lower dc voltage forces the VCO
frequency to increase until it equals fs.
On the other hand, if the input frequency decreases, its phasor slows down and the phase angle
decreases as shown in Fig.17.17(d). Now dc voltage will come out of the phase detector. This causes
the VCO frequency to decrease until it equals the input frequency. In other words, the PLL automati-
cally corrects the VCO frequency and phase angle.
Figure 17.17(a) Phase locked loop, (b) phasor diagram, (c) increasing frequency increase f and
(d) decrease frequency decreases phase angle f
Lock Range
The lock range of a PLL is the range of input voltage frequencies over which the VCO can remain
locked on to the input voltage frequency.
Here is a numerical example. Suppose the VCO is locked on to an input frequency of 50 kHz. If the
input frequency increases to 51 kHz, the phase detector immediately sends less voltage to the VCO and
increases its frequency to 51 kHz. If the input frequency later decreases to 49 kHz, the phase detector
sends more dc voltage to the VCO and decreases its frequency to 49 kHz. In either case, the feedback
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automatically adjusts the phase angle to produce a dc voltage that locks the VCO frequency on to the
input frequency. The lock range fL is the range of frequencies that the VCO can produce and is given by
fL = fmax fmin
Where fmax and fmin are the maximum and minimum VCO frequencies. For example if the VCO
frequency can vary from 40 kHz to 60 kHz. The lock range equals.
fL = 60 kHz 40 kHz = 20 kHz
Once the PLL is locked on, the input frequency fs can vary from 40 kHz to 60 kHz. The VCO will
track this input frequency and the locked output will be equal to fs.
If the input signal frequency is too low or too high, the phase difference falls out side the range of 0°
to 180°. Therefore the phase detector cannot produce the additional voltage needed for the VCO to
remain locked on. At these limits, therefore, the PLL loses its lock on the input signal. The lock range is
generally specified as a percentage of the VCO frequency. For example, if the VCO frequency is 10 kHz
and lock range is ±20%, the PLL will remain locked on any input signal frequency falling between 8 kHz
and 12 kHz.
Free-Running Mode
Recall the astable 555 timer with no control voltage. It oscillates at a natural frequency determined by
the circuit components. The same is true for the VCO in Fig.17.17 (a). If the input siganl is discon-
nected, the VCO oscillates in a free running mode with its frequency determined by its circuit elements.
Capture range
Let us assume that the input signal frequency is outside the lock range. Under such condition, the VCO
is free running at 10 kHz. Now if we assume that the input frequency changes towards the VCO
frequency, the PLL will be able to lock at some point on to the input frequency. The range of input
frequencies within which the PLL can reestablish the lock is called capture range. The capture range is
specified as a percentage of the free running frequency. If Fo = 10 kHz and capture range is ±5%, the
PLL can lock on to an input siganl frequency between 9.5 kHz to 10.5 kHz. Thus, the PLL can lock on
to the input frequency if it lies within the capture range, a band of frequencies centered on the free-
running frequency. The formula for capture range is
fC = f2 f1
Where f2 and f1 are the highest and lowest frequencies the PLL can lock into. The capture range is
always less than or equal to the lock range and is related to the cutoff frequency of the low-pass filter.
The lower the cutoff frequency, the smaller is the capture range.
Here is an example, suppose the PLL can initially lock into a frequency as high as 52 kHz or as low
as 48 kHz. Then the capture range is 4 kHz, with a center frequency of 50 kHz. If the lock range is
20 kHz and lock has been acquired, then the input frequency can vary gradually from 40 kHz to 60 kHz
without lock.
Locked Output
One use for the locked output fs of a PLL is to synchronize the horizontal and vertical oscillators of TV
receivers to the incoming sync pulses. The PLLs can also automatically turn on each TV channel by
&##
locking on to the channel frequency. Still another use for PLLs is locking on to weak signals from
satellites and other distant sources that improve the signal to noise ratio.
In general, the locked output is a signal with the same frequency as the input signal. Even though the
input signal may drift over a rather large frequency range, the output frequency will remain locked on.
This eliminates the need to tune a resonant circuit for maximum output.
FM Output
Figure 17.18 shows an LC oscillator with a variable tuning capacitor. If the capacitance is varied, the
oscillation frequency changes. Figure 17.18 illustrates the output signal. This is an example of fre-
quency modulation (FM). If the capacitance of Fig.17.18 varies, it generates sinusoidal signal at a rate
of 1 kHz. The modulation frequency is a 1 kHz.
When an FM signal like Fig. 17.18 is the input to a PLL in Fig.17.17(a). the VCO will track the input
frequency as it changes. As a result, a fluctuating voltage comes out of the low-pass filter. This voltage
has the same frequency as that of the modulating signal. In other words, the dc output now represents
a demodulated FM output. This is useful in FM receivers. If the modulating signal is music, the signal
out of the FM output will be the same music.
Figure 17.18 Frequency of modulation with varying capacitor generates varying frequency FM
signal
The 565
The NE565 from Signetics is a 14 pin IC that can be connected to external components to form a PLL.
Figure 17.19 shows a simplified block diagram. Pins 2 and 3 are differential inputs to the phase detector.
If a single ended input is preferred, pin 3 is grounded and the input signal is applied to pin 2. Pins 4 and
5 are usually connected together. In this way the VCO output becomes an input to the phase detector.
In those applications where the locked output is desired, pin 4 is the output pin.
An external timing resistor is connected to pin 8, and an external timing capacitor to pin 9. These two
components determine the free running frequency of the VCO given by
0.3
f=
RC
The external passive components R and C are selected to produce a free-running VCO frequency at
the center of the input frequency range. If we want to lock on to an input frequency between 40 kHz
and 60 kHz, we choose R and C to produce a free-running VCO frequency of 50 kHz.
Pin 7 is the FM output, used only when an FM signal is driving the phase detector. In FM receivers,
a demodulated signal comes out of this pin. This signal then goes to other amplifiers and eventually
comes out from the loudspeaker.
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Notice the filter capacitor CF between Pin 7 and ground. This capacitor and the internal 3.6 KW
resistor form a low pass RC filter to remove the original frequencies, their harmonics, and the sum
frequency. The cutoff frequency of this filter is given by
1
fc =
2pRF CF
Figure 17.19 Block diagram of 565P
The lower the cutoff frequency of this filter, the smaller is the capture range. In some applications,
the filter capacitor is omitted and the capture range equals the lock range. Figure 17.20 is the experimen-
tal circuit of 565 PLL.
If the ac siganl generator of Fig. 17.20 is disconnected, the 565 is in the free-running mode of
operation. The oscilloscope shows the magnitude and frequency of the VCO output (pin 4). Use a
vertical sensitivity of 5 V/cm and a time base of 0.lms/cm. Measure the minimum and maximum free-
running frequencies with an electronic counter. (If not available, use f = 1/T)
where T is the period seen on the oscilloscope). Adjust the potentiometer to get a center frequency of
approximately 5 kHz.
Figure 17.20 Experimental circuit of 565 PLL

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1. Design a VCO having the maximum range the frequency of the trigger signal to be
of 1 kHz. Assume power supply +VCC = 2 kHz.
15 V. Required pulse width should not Solution:
exceed 100ms.
Solution:
Zener diode is FZ6.2 A, whose Vz = 6.2 V,
assuming 0.5 mA as diode current
VCC - VZ 15 - 6.2
RZ = =
diode current 0.5 mA
= 17.6 K
The switch S is a p-channel FET : Figure 17.21 Monostable multivibrator
2N2608. It has Vp @ +3 V < +VCC and
ID @ 3 mA The circuit of Fig.17.21 is for divide by 2.
Vp The tp should be slightly greater than T.
RON = = 0.5 K Let tp = 1.2T i.e. 20% extra to T. Hence tp
2 ID
1.2
Let C1 to be fully discharged before = = 0.6 ms
triggering occurs R2C2 > RONC1 2kHz
Since, Tp = 0.7R2C2 = 100 ms tp

From tp = 1.1RAC, we get RA =
Assuming RONC1 ten times less than TP i.e. 11
.C
RONC1 @ 10 ms 0.6 mS
= = 54.5 KW
10 m s 1.1 ¥ 10-8
C1 = = 0.02 pF
500 W 3. In Fig.17.22 RA = 2.2 K, RB = 3.9 K and
C = 0.1 mF. Find out the pulse width of
2Vi
R1 = @ 16 KW for Vi = 1 V positive and negative pulses. Also calculate
VZ f oC1 the free running frequency.
Tp Solution:
Assuming R2 = 10 K, C2 =
0.7 R2 TC = 0.693(RA + RB)C = 0.693(6.1 K)107
= 0.423 ms.
100 ms
= = 150 pF. TD = 0.693(3.9 K)107 = 0.2703 ms
0.7 ¥ 10 KW
1
As R3 is not a critical component, it can be Hence, fo =
TC + TD
assumed of the value 100 KW
2. For Fig. 17.21, what should be the value 1
of RA, if the value of C = 0.01 mF. Consider = = 1.45 kHz
(0.423 + 0.2703) ms
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4. Determine the frequency of the free

running ramp generator if R is set at 10 K
in Fig. 17.23 Assume that VBE = VD = 0.7
V. C3 is decoupling capacitor.
Solution:
3IC
fo =
VCC ¥ C
where, IC in amp and C in mF
Figure 17.22 Astable multivibrator VCC - VEB 5 - 0.7

IC = =
R 10 K
Figure 17.23 Free running ramp generator
4.3 stages in Fig. 17.24. Clock generator is

= = 0.43 mA normally an astable multivibrator having
10 K
asymmetrical output waveform with equal
3 ¥ 0.43 mA charge and discharge times. This
fo = @ 5.16 kHz
5 ¥ 5 ¥ 10 8 symmetry can be minimized and for this
5. Using NE556, design a clock generator to make R2 >> R1.
produce pulses of 5 kHz spread over three
Figure 17.24 Astable multivibrator

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Solution:
R1 + R2
Under such circumstances, the duty cycle DT = 50% =
R1 + 2 R2
1443
.
The capacitor values for above values of resistances using fo = are shown in
( R1 + 2 R2 )C
Table 17.2.
Table 17.2
Frequency (Hz) Capacitor (mF) R1 (KW) 2R2 (KW)
13130 1.01 2(5 + 50) 2(5 + 0.05)
1301300 0.11 2(5 + 50) 2(5 + 0.05)
130013000 0.01 2(5 + 50) 2(5 + 0.05)
Three standard values of capacitors This is the minimum trigger voltage

(1 mF, 0.1 mF, and 0.01 mF) have been required to produce pulse at the output.
assumed here. The circuit diagram for The capacitor will charge up to UTP =
the corresponding generator designed is
2VCC 2 ¥ 12
drawn in Fig.17.24. = = 8 V . The falling edge of
6. Calculate the values of R and C for 3 3
Monostable operation of the IC555 timer the output starts at 20 ms.
with VCC = 12 V and pulse width of 7. What would be the duration of the pulse
20 ms. Also find out the minimum for Monostable operation of IC555 timer
threshold voltage required that would with R = 1 MW and C = 470 mF?
produce the output pulse. How much will Solution:
be the value of the capacitor? At what The duration of pulse of Monoshot = T =
instant of time the falling edge of the 517
output starts? 1.1RC = 11
. ¥ 1 ¥ 470 = 517s = = 8.62
60
Solution: minutes
From Eqn. 17.2.3, the pulse width of 8. If an IC555 timer is used to generate a
Monoshot = T = 1.1RC = 20 ms ramp voltage with constant collector
20 ms current of 1 mA, VCC = 15 V, and C =
or, RC = = 18.18 ms, 0.1 mF, what would be the slope of the
1.1
ramp voltage generated? How much is the
20 ms peak value of the generated ramp? What is
If R = 33 K, C = = 0.55 mF
33 K the duration of the ramp?
The lower comparator trips at LTP = Solution:
VCC 12 V dQ dV
= = 4 V . Thus, the input at We know that Q = CV, =i=C ,
3 3 dt dt
trigger pin-2 falls from VCC = 12 V to 4 V.
&$
dV 1 1 mA Maximum Pulse width = Tmax = 10 ¥ 103

= Slope of the ramp = =
dt C 0.1 m F FG
12
¥ 0.1 ¥ 106 ln 1 -
IJ
= 1.61 ms
= 10 V/ms H
15 K
Peak value of the ramp generated = V = Minimum Pulse width = Tmin = 10 ¥ 103
UTP =
2VCC
=
2 ¥ 15
= 10 V
FG
¥ 0.1 ¥ 106 ln 1 -
8 IJ
= 0.762 ms
3 3 H 15 K
Period = T =
b g
2 R1 + R2 RE CVCC
Maximum duty cycle = Dmax =
Tmax
m b
3 R1VCC - R1 + R2 VBE g r T
162
.
2 (147) 2.7 ¥ 0.1 ¥ 15 = = 1.46 ms
= 11.
3{47 ¥ 15 - (147) 0.7}103
Tmin
Minimum duty cycle = Dmin =
119.07 T
= ¥ 103 =0.67 ms
1806.3 0.762
= = 0.7 ms
9. The pulse width modulator using IC555 11
.
timer has VCC = 15 V, R = 10 K, and C = 10. Figure 17.13 is the circuit of pulse position
0.1 mF. The clock frequency is 2 kHz. modulator using IC555 timer having VCC =
What is the period of the output pulse, if 12 V, RA = 3.9 K, RB = 3 K, and C =
the peak value of the modulations signal is 0.1 mF. What is the value of quiescent
2 V. How much is the quiescent pulse pulse width and period of the output pulse?
width? What is the maximum and What would be the minimum and
minimum pulse widths and duty cycles? maximum pulse width if the peak value of
Solution: the modulation signal is 2 V? How much is
Period of the output pulse = period of the the space between the two pulses?
1 = 0.5 ms Solution:
pulse = T =
2kHz Quiescent period of the output pulse is
when the modulating signal is not present.
Quiescent pulse width = T = 1.1 ¥ 10 ¥ 0.1
Thus quiescent
¥ 103 = 0.11 ms
Width = W = 0.693(RA + RB)C
2VCC 2 ¥ 15 = 0.6983(6.9) ∏ 0.1 ¥ 103 = 0.47 ms
UTP = + vmod , UTPmax = +2
3 3 T = 0.693(RA + 2RB)C = 0.6983(9.9) ¥ 0.1
2 ¥ 15 ¥ 103 = 6.86 ms
= 12 V, UTPmin = -2 =8V
3 2VCC 2 ¥ 12
UTPmax = + Vmod = +2
3 3
Ê UTP ˆ
Pulse width = T = RC ln Á1 - , 2 ¥ 12
Ë VCC ˜¯ = 10V, UTPmin = -2 = 6 V
3
&$
Maximum pulse width = Tmax 12 - 6

= (6.9)0.1 ¥ 103 ln = 0.86 ms
V - UTPmax 12 - 3
b g
= - R A + RB C ln CC
VCC - 0.5UTPmax Space between two pulses = = 0.693RBC
= 0.6983 ¥ 0.1 ¥ 103 = 0.21 ms
12 - 10
= (6.9)0.1 ¥ 103 ln = 0.86 ms T = W + 0.693RBC, Tmin = Wmin +
12 - 5 0.693RBC + 0.2 lms = 0.49 ms
Maximum pulse width = Tmin Tmax = Wmax + 0.693RBC = 0.86 ms +
VCC - UTPmin 0.21 ms = 1.07 ms.
= (RA + RB)C ln
VCC - 0.5UTPmin
Questions for Practice (c) 1-comparator, 1-SR-FF, 1-discharge

transistor.
1. Why 555 is associated with the integrated 2. In order to avoid the false triggering, the
circuit timer? reset terminal should be connected to
2. List features of the 555 timer. (a) ground
3. In how many modes the 555 timer can (b) +VCC
operate? (c) none of these
4. Where the 555 timer is used as a
3. The maximum voltage connected to pin-8
monostable multivibrator?
is
5. Enumerate useds of the 555 as astable
(a) 5 V
multivibrator.
(b) 18 V
6. What is a PLL?
(c) 10 V
7. What is the function of low-pass filter in
the PLL? 4. The minimum voltage connected to pin-8
8. What is a VCO? is
9. What does the phase detector do in PLL? (a) 0.7 V
10. What is the effect of filter capacitor on the (b) 0.2 V
capture range of the PLL? (c) 5 V
11. How do you define lock range of the PLL? (d) 18 V
5. The threshold voltage for IC555 is
(a) VCC/3
Multiple Choice Questions (b) 2VCC/3
(c) V CC
1. The IC555 timer contains 6. For astable operation of the IC555, the
(a) 2-comparators, one SR-FF, one reset terminal is connected to
discharge transistor (a) ground
(b) 2-comparators, 1-SR-FF, 1- (b) V CC
discharge transistor, 1-buffer (c) threshold voltage
&$
7. The charging time constant in astable (c) 20-transistors, 2-diodes, and 10-
operation of the IC555 is resistors
(a) 0.693(RA + RB)C 15. The 555-timer can be used as
(b) 0.693RBC (a) bistable, monostable, astable
(c) 0.693(RA + 2RB)C (b) bistable, monostable
(c) monostable, astable
8. The discharging time constant in astable
operation of the IC555 is 16. A decreasing phase angle of a phase
detector produces a dc output voltage that
(a) 0.693(RA + 2RB)C (a) increases
(b) 0.693(2RA + RB)C (b) decreases
9. The duty cycle in astable operation of the (c) remains constant
IC555 is 17. An increasing dc control voltage in the
(a) (RA + RB)/(RA + 2RB) VCO produces a frequency that
(b) (RA + RB)/(RA RB) (a) increases
(c) (RA + RB)/2(RA + RB) (b) decreases
(c) remains constant
(d) RB/(RA + 2RB)
18. If the maximum and minimum frequencies
10. The pulse width of the IC555 monostable of a VCO are 450 kHz and 350 kHz, the
multi is given by lock range is
(a) 0.893RC (a) 100 kHz
(b) 1.1RC (b) 800 kHz
(c) RC (c) 450 kHz
(d) 1/RC 19. A PLL can acquire initial lock for a
11. In the astable mode of operation of the maximum input frequency of 415 kHz and
IC555, the capacitor charges between a minimum input freqyency of 385 kHz.
(a) 0 to VCC The capture range equals
(b) 0 to VCC/3 (a) 30 kHz
(c) VCC/3 to 2VCC/3 (b) 83 kHz
(d) 2VCC/3 to VCC
(c) 2.075 kHz
12. The charging time in astable multivibrator
using IC555 is 20. The free running frequency of a 565 PLL
(a) greater than the discharging time with timing resistance of 10KW and timing
(b) less than the discharging time capacitor of 0.01mF is
(c) equal to the discharging time (a) 1 kHz
13. The output of IC556 and IC558 are (b) 3 kHz
compatible to (c) 0.3 kHz
(a) TTL logic 21. The cut-off frequency of a low-pass filter
(b) RTL logic used with 565 PLL with an external
(c) DTL logic capacitor of 0.01 mF is
14. The internal circuitry of IC555 has as (a) 4.42 kHz
many as (b) 15.9 kHz
(a) 23-transistors, 2-diodes, and 16-
(c) 1 kHz
resistors
22. Which of the following remains constant
(b) 20-transistors, 2-diodes, and 16-
in a pulse width modulation
resistors
&$!
(a) pulse width (a) capture range

(b) time period, duty cycle (b) lock range
(d) space (c) free running frequency
23. Which of the following remains constant (d) phase difference
in a pulse position modulation 25. When the PLL becomes locked on to the
(a) pulse width input frequency, the VCO frequency is
(b) time period, duty cycle (a) less than fo
(d) space (b) more than fo
24. The bandwidth of a low-pass filter in a PLL
(c) equals fo
determines
(d) equals fm

1 (b) 2 (b) 3 (c) 4 (c) 5 (b) 6 (b)
7 (a) 8 (b) 9 (a) 10 (b) 11 (c) 12 (a)
13 (a) 14 (a) 15 (c) 16 (a) 17 (b) 18 (a)
19 (a) 20 (b) 21 (a) 22 (b) 23 (d) 24 (a)
25 (c)
18
Special Two-terminal Devices
18.1 Introduction
The electrical conductivity of the semiconductor is influenced by external physical quantities such as
temperature, illumination intensity, magnetic field, etc.
The thermistor is a compound semiconductor. Its resistance is dependent on the temperature. Similarly,
magneto resistor is another semiconductor device. It is made of polycrystalline compound which has
the property of changing resistance under influence of magnetic field.
The word thermistor stands for thermal dependent resistance and is a temperature sensitive device
(resistor). In other words, its terminal resistance changes w.r.t. change in its body temperature. It is not
a junction device. It is constructed from Ge, Si or mixture of oxides of cobalt, nickel, strontium or
manganese. The compound used determines whether the device will result in positive or negative
temperature coefficient. Normally thermistors available are of negative temperature coefficient type.
The physical appearance and its symbol are shown in Fig. 18.1.
Figure 18.1 Physical appearance and symbol of thermistor
18.2 Light Dependent Resistance (LDR)

The LDR is a two-terminal semiconductor device. Both its terminals are connected to a thin sheet of a
photo-conducting material. When this thin layer of photo-conducting material is exposed to light, its
&$#
resistance varies. This is why it is called photo-resistive device. The physical appearance and symbol of
the LDR are depicted in Fig. 18.2.
The most frequently used photo-conductive compounds are:
∑ Cadmium sulfide (CdS)
∑ Cadmium selenide (CdSe)
∑ Lead sulfide
∑ Lead selenide
∑ Lead telluride
∑ Indium antimonide
Figure 18.2 LDR appearance and symbol

The most widely used compound for LDR is cadmium sulphide. LDRs surface is coated with cadmium
sulphide. The coating contains some impurities like antimony, indium nitrate, etc. for improving the
efficiency. The peak spectral response of CdS occurs at 5100 Å and for CdSe at 6150 Å. Spectral
response of different types of material w.r.t. human vision are shown in Fig. 18.3.
Figure 18.3 Relative spectral response of Si, Ge, selenium w.r.t. human eye
&$$
In the absence of illumination, a very low current called the dark current flows through the photo-
resistor. The resistance corresponding to this dark current is called the dark resistance. The dark
resistance becomes as high as few hundred MW. On illuminating, its resistance decreases and large
current starts flowing through it. Its sensitivity is in the range of few milli-ampere per unit lux or mA/lm.
The heat dissipation across the device is of the order of 100mW to 1W. It is available in ranges of few
kW to several MW
When the photo resistor is illuminated as shown in Fig. 18.4 a current called the joint current, flows
through it.
Figure 18.4 Photo-resistor action, geometry, bias circuit
The difference between the joint current Ij and the dark current Id is obviously called the photo current,
i.e.
Ip = Ij Id (18.2.1)
The photo-resistor is operated only when driven by externally applied voltage. It offers the same resistance
in both directions.
Disadvantages
∑ Considerable time lag, typically 100 ms in CdS and10 ms in CdSe
∑ Non-linear w.r.t. illumination flux
∑ Resistance is temperature dependent
When light falls on semiconductor, electron-hole pairs are generated. These electron-hole pairs change
the conductivity of the material. Under the influence of external electric filed, the electron-hole pairs
move in opposite direction leading to current flow. Thus, current carriers are present in the semiconductor
until recombined or collected at the contacts. Let us consider a state where electron-hole pair generation
rate is equal to its recombination rate Reh, i.e.
dn
Reh = = GL (18.2.2)
tp
where, tp = effective recombination time of the excess carriers

GL = electron-hole pair generation rate
Let us assume that LDR is lightly doped n-type semiconductor and hence, electrons dominate the
conductivity. In the absence of optical signal, the conductivity of the semiconductor as derived in
Chapter 1 is rewritten as
&$%
so = q(nomn + pomp) (18.2.3)

where the subscript o indicates the conductivity, electron and hole densities in the absence of light
(dark).
The optical signal generates electron-hole pairs, i.e.dn = dp. The semiconductor conductivity now
changes to
s = q{mn (no + dn) +mp(po+ dp)} (18.2.4)
The excess carrier is defined as dn = dp = GLt p (18.2.5)
We know that presence of optical energy changes conductivity of the semiconductor. The change in the
photo-conductivity is expressed as
Ds = q(mn dn +mpdp) = qdn(mn + mp) = qdp(mn + mp) (18.2.6)
The total current density J is related with the external electric field E as
J = (Jd + JL) = (so+D s)E (18.2.7)
V
or IL = JL ¥ A = qdp(mn + mp)EA = qdp(mn + mp) A (18.2.8)
L
Hence, change in the resistance of the LDR is
L
DR = (18.2.9)
qdp( m n + m p ) A
Equation 18.2.9 indicates that as the excess charge carriers increase due to light intensities, the
resistance of the device decreases. Equation 18.2.8 can also be expressed as
IL = JL ¥ A = qGLtp(mn + mp)AE (18.2.10)
We also know that the mnE and mpE represent the electron and hole velocities respectively. Under the
influence of high electric field, these quantities, mnE and mpE, become saturated. Hence, these become
independent of the electric field. Let us define the transit time of the electron in the device as
L L
tt = = (18.2.11)
vn mn E
Substituting mnE from Eqn. 18.2.11 in Eqn. 18.2.10 yields the light generated current or the photocurrent
as
IL = qGLtpmn 1+ FG mp IJ EA = qG FG t IJ FG1+ m IJ LA
L
p p (18.2.12)
H
mn K t H t KH m K
n
This is the photocurrent generated in a circuit. The primary photocurrent can be defined as
ILp = qGLAL (18.2.13)
Equation 18.2.13 represents the photocurrent if each electron-hole pair contributes one charge carrier.
In other words, the device does not produce any current i.e. the device does not have any gain. Now,
w.r.t. the primary photocurrent, the gain of the photocurrent generated in a circuit is expressed as
I Êtpˆ
Gp = L = Á ˜ 1+
mp FG IJ (18.2.14)
I Ë t ¯
LP m
t H n K
&$&
Equation 18.2.14 is more popularly known as photo-conductive gain. This gain is possible only
because the electron moves around the circuit many times before it recombines with the photo-generated
hole. Each time the electron completes the circuit it contributes to current. The characteristic of a
typical thermistor with negative temperature co-efficient is shown in Fig. 18.5.
Figure 18.5 Resistance temperature characteristic of thermistor
If we assume that tp is large and tt is small then a very large gain can be produced. In Si device where
tp is very large the gain could be excess of 1000. However, a higher gain is produced on the expense of
speed, as the speed is controlled by the transit time tt. While the advantage of the LDR is that it produces
large gain, it suffers from noise current due to the presence of large ambient light signal.
Example
A GaAs n-type LDR shown in Fig. 18.6 is subjected to an external voltage of 5 V. The minority carrier
lifetime tp = 107 electron and hole mobilities are mn = 0.8 m2/V.s, mp = 0.1 m2/V.s. Obtain the transit
time of the electron, and gain of the photo-conductor.
Solution
For constant mobility the transit time of the electron is
L L L2 (20 × 10− 6 ) 2 400 * 10-12
tt = = = = = = 1010S
mn E m nV / L m nV 0◊8 × 5 4.0
Figure 18.6 Specimen of photoconductor

&$'
Hence, Gp =
FG t IJ FG1+ m IJ = F 10
p p
-7 I F1 + 01. I = 10 (1+ 0.125) = 1.125 ¥ 10
3 3
H t K H m K GH 10
t n
-10 JK GH 0.8JK
The electric field created across the length of the GaAs specimen is
5
E= -6
= 2.5 ¥ 105 V/m = 250 KV/m
20 ¥ 10
Now, if we assume approximate velocities of electrons and holes at 250 KV/m as vn @ 1.5 ¥ 106 m/s,
and vp @ 2 ¥ 105 m/s respectively, then
L 20 ¥ 10-6
Transit time of electron = tt = = = 1.333 ¥ 1010 s
vn 1.5 ¥ 105
Now the gain of the photo-conductor = Gp=

10-7 FG1 + m IJ = 0.75 ¥ 10 FG1 + m E IJ
p 4 p
1.333 ¥ 10-10 H mK n H m EK n
Ê vp ˆ Ê 2 ¥ 105 ˆ
4 1 + 4 Á1 + 4
= 0.75 ¥ 10 ÁË vn ˜¯ = 0.75 ¥ 10 Ë 1.5 ¥ 10 6 ˜¯ = 0.75 ¥ 10 (1 + 0.133)
= 0.84 ¥ 104
The error introduced in the gain will be minimum at low field. The constant mobility assumed for
electron and hole must accordingly be changed at high field.
The important areas of its uses may be enumerated as:
∑ Light sensitive alarms
∑ Light activated relays
∑ Measuring light
∑ Fast recording situation, etc.
18.2.2 Photodiodes
We know that the current through a reverse biased p-n junction changes considerably if the device is
exposed to illumination. The variation in the output current is linear with respect to the luminous flux.
This characteristic of p-n junction has been utilized in fabricating semiconductor photodiodes. When
photons of light energy collide with a valence electron and impart sufficient energy to it to break open its
covalent bond, it gets separated from its parent atom. Similarly, holes get separated from its parent atom
in p-type material. Thus, electron-hole pair generation takes place in a p-n junction. Therefore, we can
generalize the statement that when light impinges on a semiconductor, electron-hole pairs are generated.
If some of these generated electron-hole pairs get collected, it leads to photocurrent.
We also know that if light falls on an unbiased p-n junction, i.e. electron-hole pairs get generated in
the depletion width Wo as shown in Fig. 18.7. Let us consider that the excess carriers in the long p-n
diode structure shown in Fig. 18.7 are generated at a rate GL.
&%
Figure 18.7 Illuminated p-n junction
We know that very high electric field exists across the junction as the junction is very thin (@ 106 m)
as shown in Fig. 18.8. This high electric field sweeps these generated electron-hole pairs into n- and p-
regions. Electrons are swept into the n-region while holes are swept into the p-region very rapidly. This
results into excess carrier generation, over and above the equilibrium concentration of the carriers pn
and np as shown in this figure.
Figure 18.8 p-n junction illuminated by the sunlight
The photocurrent resulting from absorption of photons in the depletion width Wo is expressed as
x
z
IL1 = Aq GL dx = AqGLWo
x'
(18.2.15)
where A = area of the junction diode.

Since electrons and holes move under the influence of very high electric field in the depletion region
the response is very fast. These electrons and holes contribute to the current IL1 and hence, it is called
the prompt photocurrent.
In Fig. 18.8, pn and np are the equilibrium concentrations of holes and electrons in p- and n-regions
respectively.
The carriers are generated in neutral n- and p-regions of the diodes in addition to its generation in the
depletion region. It is expected that the holes generated within the distance of LP (diffusion length) from
&%
the edge of the depletion width (x = 0) will be able to enter the depletion width from where they will be
swept to p-region. Similarly, electrons generated within the distance Ln (diffusion length of electron)
from edge of the depletion width (x' = 0) will be able to enter the depletion width from where they will
be swept away into the n-region. Electrons and holes so generated will be collected which results in
current flow. Thus, photocurrent would come from all carriers generated in the region Lp + Wo + Ln.
Assuming that the electron-hole pairs are generated at a constant rate GL and taking the help of the
continuity equation, Eqn. 2.7.9, we define steady state continuity equation for holes in the n-region by
adding the generation rate to Eqn. 2.7.9 as
∂ 2dpn dpn
Dp - + GL = 0 (18.2.16)
∂x 2 tp
where, Dp = diffusion constant of minority carrier (hole),
tp = life time (recombination time) of hole.
The excess carrier density = dpn = p(x) pn (18.2.17)
The voltage V is assumed positive for forward bias and negative for the reverse bias.
The boundary conditions from Fig. 18.8 can be derived as
dp( x fi • ) = GLtp (18.2.18)
R|S F qV I - 1U|V
dp(x = 0) = pn exp (18.2.19)
|T GH k T JK |W
B
We assume that no recombination takes place in the depletion width if W0 < Lp = (Dptp)1/2 and the
n-region is much larger than Lp. The solution of Eqn. 18.2.16 can be broken into two parts:
∑ Complementary function (homogeneous solution)
∑ Particular integral
The homogeneous solution in the form of complementary function results for GL = 0 and is of the
form
d 2dpn¢ dpn¢
- 2 =0 (18.2.20)
dx 2 Lp
The solution of Eqn. 18.2.20 is
dpn¢ = Ao exp -
F x I (18.2.21)
GH Lp JK
The particular integral is of the form
dpn¢¢ GL
= (18.2.22)
L2p DP
or n = GLt p
dp≤ (18.2.23)
&%
Now the total solution is expressed as
dpn = Ao exp -
F x I +G t (18.2.24)
GH J Lp
Lp K
The value of constant Ao is obtained by substituting the boundary condition at x = 0 from Eqn.
18.2.19 in Eqn. 18.4.24 as
|RS FG qV IJ - 1|UV = A + G t
pn exp o L p (18.2.25)
|T H k T K |W
B
or
R| F qV I - 1U|V - G t
A = p SexpG (18.2.26)
o
T| H k T JK W|
n
B
L p
È ÏÔ Ê qV ˆ ¸Ô ˘ Ê x ˆ
Hence, dpn ( x ) = Í pn Ìexp Á - 1˝ - GLt p ˙ exp Á - ˜ + GLt p (18.4.27)
ÎÍ ÓÔ Ë k BT ˜¯ ˛Ô ˚˙ Ë Lp ¯
Eqn. 18.2.27 represents distribution of excess holes in n-region.
It is known that dpn(x = 0) is essentially equal to zero if the diode is operated either under short circuit
condition, i.e. V = 0 or in reverse bias condition. This gives rise to reduction of the Eqn. 18.2.27 as
R|
dpn ( x ) = GLt p 1 - exp -
F x I U| (18.2.28)
S| GH Lp JK V|W
T
Now the hole-current due to carriers absorbed in the n-region is obtained as
IpL = AqD
ddp( x )
= AqD G t
R|0 - F - 1 I expF - 0 I U| (18.2.29)
p p L pS G L J G JV
dx x =0 T| H p K H Lp K W|
or IpL = AqGLLp (18.2.30)
The electron current can be obtained similarly. Hence, total current due to carriers in the depletion
region and neutral n- and p-regions is written as
IL = InL + IpL + IL1 = qAG L ( Ln + Wo + L p ) (18.2.31)
We know that the contribution of the photocurrent from the neutral n- and p-regions have a slower
time response as the carriers are collected under diffusion process with almost no field. In case widths
of neutral n- and p-regions (dp and dn) are smaller than Lp and Ln along with the boundary condition
{dp(dn) = dn(dp) = 0}, we can assume that probably half the carriers generated in the neutral regions
contribute to photocurrent. The current is then written as
RS
d
IL = qG L Wo + n +
dp
A
UV (18.2.32)
T
2 2 W
We should note that the electron-hole pair generation is not uniform. With increasing depth, it decreases.
Hence, the average generation rate should be taken. It is also important to note that the photocurrent
flows in the direction of the reverse bias current of the diode.
&%!
The total current in a diode connected to the external load is shown in Fig. 18.9. The photodiode in
this figure is represented by a current source IL feeding to the diode. The internal characteristic of the
diode is represented by a shunt resistance Rsh and a capacitor CD and the external characteristic by a
series resistance of the diode as Rs. In the photovoltaic mode, as a solar cell, the device is connected to
a high resistive load RL. In the photoconductive mode as detector, the device is connected in series with
a load and an external power supply. Hence, light generated current and the diode current in the absence
of the light give total current. If V is the voltage applied across the diode, the total current is
ÔÏ Ê e(V + Rs I ˆ Ô¸
I = I L + I o Ì1 - exp Á ˜˝ (18.2.33)
ÓÔ Ë hk BT ¯ ˛Ô
where, h = ideality factor.
Figure 18.9 Equivalent circuit of photodiode
Figure 18.10 shows a simple representation of a semiconductor photodiode. The device is made of a
semiconductor p-n junction kept in a sealed plastic or glass casing as shown in this figure. The cover is
so designed that the light rays are allowed to fall only on one surface across the junction. The remaining
sides of the casing are painted to restrict the penetration of light rays. It is a semiconductor device that
generate emf when illuminated by light.
The generated emf is called the photo emf. When this light falls on the surface near the p-n junction,
the atoms of the crystal get ionized and generation of additional electron-hole pairs take place. The
junction field drives some of the generated holes into the p-region whereas the electrons remain in the
n-region because they cannot surmount the existing potential barrier. Thus, holes and electrons are
accumulated in p- and n-regions respectively. This establishes a potential difference, called the photo
potential difference. A current starts flowing when a load is connected to it.
Figure 18.10 Biasing, symbol and characteristic of photodiode

&%"
The photodiode operates in two modes namely,

∑ current mode
∑ voltage mode
The photo-diode in the current mode needs external bias but in the voltage mode it does not require
any external voltage source. The two modes of operation are depicted in Fig. 18.11. In the current mode
the photodiode is reverse biased. In the absence of illumination, the dark current flows through the
diode. The light falling on n-region of the device generates electron-hole pairs. The hole reaches the
p-n-junction and under the influence the junction field, passes to the p-region. Thus, the illumination
gives rise to a minority carrier hence, minority current from n- to p-region starts flowing. This change
in current due to illumination results in a voltage drop across an externally connected load. The voltage
drop is proportional to the illumination intensity falling on the junction of the photodiode.
Figure 18.11 Voltage and current mode operation of photodiode
The reverse saturation current is solely due to the thermally generated minority carriers in the n- and
p-type materials. The application of light to the junction results in transfer of energy from the incident
light in the form of photons to the atomic structure, resulting in an increase in the minority carriers
hence, increase in the reverse bias current. This is clearly depicted in Fig. 18.10. When the reverse
biased photodiode is kept in darkness, the current flowing through the device corresponds to the reverse
biased saturation current that is negligibly small. The dark current is that current which exists without
any illumination. It is evident from Fig. 18.10 that the current only returns to zero with a positive voltage
applied equal to VT. The lens in this figure has been used to focus the light at the junction.
The current flowing through the device is directly proportional to the quantity of light flux. Another
factor that governs the amount of current flowing through the device is the distance of the source of
illumination from the junction. We know that the amount of current flowing in a reverse biased
semiconductor photodiode is due to diffusion of minority charge carriers to the junction. Obviously, if
the distance is increased, the conduction will be less and the amount of current flowing will be decreased
because there will be a chance of recombination for the minority charge carriers. To increase the
amount of current flowing through the device one has to bring the illuminating source nearer depending
on the temperature. The working temperature limit specified by the manufacturer must be strictly
maintained for efficient performance of the device.
A semiconductor photodiode finds its application in areas such as,
∑ computer card punching and typing
∑ light operated switches
∑ sound track of films
∑ systems for detecting light
∑ electronics control circuits, etc
&%#
BPX40, BPX41, BPX42, BPY68, BPY69, OAP12, etc. are some of the commonly used photodiodes.
The energy thus, transmitted as discrete package called photons has a level directly related to the
frequency of light waves falling on it, is determined as
W = hf (joules) µ f (18.2.34)
34
where h = Plancks constant = 6.624 ¥ 10 joules sec.
As h is constant, the energy of the incident light is proportional to its frequency. The frequency is
related to the wavelength as
C
l= (18.2.35)
f
where l = wavelength in metre (m)
C = velocity of light = 3 ¥ 108 m/s, and
f = frequency of incident wave (Hz)
General unit of wavelength is angstrom/micro-meter/nano-meter.
where, 1Å = 1010 m, 1 mm = 106, 1 nm = 109 m.
The wavelength is an important parameter for selecting the material to be used in opto-electronic
devices. The relative response along with visible-light spectrum of Si, Ge, and selenium are shown in
Fig. 18.3. Also, the number of free electrons generated in each material is proportional to the intensity of
the incident light. The intensity is a measure of the amount of illumination flux falling on the surface. The
luminous flux is generally measured in lumen (lm) or watt. These units are related as 1W radiative power
= 680 lumen at 555 nm.
1
In other words, 1 lumen = = 1.47 ¥ 10 3 W (18.2.36)
680
A typical level of illumination of the sun in a summer day on the surface of the earth is
1.3 ¥ 105 lm/m2.
18.3 Phototransistor
A phototransistor is a n-p-n transistor that is generally used in common emitter configuration. The bias
voltage is applied between the emitter-collector leaving the base open. The transistor action of this
device is controlled by light flux. Figure 18.12 shows simple representation of a phototransistor. In
absence of the light signal IB = 0.
Hence, IC = (1+ b ) I CO (18.3.1)
Figure 18.12 Phototransistor layout

&%$
The excess photo-generated carriers in the presence of light signal within the base-collector junction
contribute to the originally flowing reverse saturation current (1+ b ) I CO . Hence, total reverse saturation
current passing through the collector junction seems to be I CO + I L , after circulating through the emitter
junction, collector current is equal to
IC = (1+ b ) I CO + I L (18.3.2)
It is only because of the transistor action that the photo-generated current gets multiplied by (1 + b).
The V-I-characteristics of phototransistor for different luminous flux levels are shown in Fig. 18.13.
The construction of a phototransistor is similar to a conventional n-p-n transistor with a little hole
made on the surface near the collector-base junction. A small lens is fixed on this hole for allowing a
focused light beam to concentrate on the collector base junction. In the modern methods of fabrication,
highly - light-effective materials are used instead of making a hole and fixing a lens on it. From Fig.
18.12 it is clear that the emitter base junction JE is forward biased, whereas the collector base junction
JC is reverse biased. When the transistor is kept in darkness there will be very few minority charge
carriers (thermally generated) that will cause the flow of reverse saturation collector current. This
current for obvious reasons will be negligibly small.
Figure 18.13 VI-characteristic of phototransistor
Additional photo generated minority charge carriers will be available which will add to the reverse
saturation current once the light is being focused at the collector base junction. Thus, as soon as the
light source is applied, the transistor starts conducting and amplified current starts flowing through the
reverse biased junction. Thus, owing to the transistor amplification action the current by the luminous
flux will increase a lot.
Sensitivity of a phototransistor is higher than other photosensitive semiconductor devices. However,
it is less stable than a photodiode. Photo transistors are used as measuring devices and also as actuators
in the photo relay circuits. BPX25, BPX70 , BPX71, BPY76, OCP70, etc. are some of the photo-
transistors available in the market.
18.4 Photovoltaic Cell

A photovoltaic cell is a photodiode without reverse bias voltage applied across it. If a photodiode is
illuminated without any reverse bias voltage being applied, the device starts generating a potential across
&%%
its terminals. This generated voltage is called the photovoltaic emf and this phenomenon of generating
voltage is known as the photovoltaic effect. We have seen in case of a photodiode that the reverse
saturation current becomes constant at large reverse bias voltages. This current is contributed by injection
of only minority charge carriers. Hence, when the current becomes saturated, its value remains constant
even if the reverse voltage is changed. Reducing the reverse voltage only results in lowering of the
potential barrier that does not affect the flow of reverse current. However, if the reverse voltage is
reduced substantially, it allows some majority charge carriers also to cross over the barrier, causing
flow of forward current. The forward current has a tendency to reduce the already flowing reverse
current. Now, as the reverse voltage is further decreased, there will be a tendency for the reverse
current to decrease rapidly. If forward voltage is applied the potential barrier is further lowered and
gradually a position arises when the forward current due to the majority charge carriers become equal to
the reverse current. This results in neutralization of the two opposite current and the net current become
zero. The voltage at which the resultant current in a semiconductor photodiode becomes zero, is called
the photovoltaic emf. Since no current flows through the device, the total voltage (photovoltaic emf)
appears across the terminals of the device. The V-I characteristics of a photovoltaic cell are represented
as shown in Fig. 18.14.
It is clear from the V-I characteristics that the reverse current decreases as the reverse voltage is
decreased. The no load voltage of a photovoltaic cell varies non-linearly with the amount of luminous
flux falling on the surface of the device. This characteristics between the no load voltage and luminous
flux has been shown in Fig. 18.14.
Figure 18.14 V-I plot of photovoltaic cell
In case the terminals of a photovoltaic cell are short-circuited in the presence of the luminous flux,
the photovoltaic emf present across it will cause the flow of a large amount of current that is known as
the short circuit current of the device. The short circuit current varies linearly with the luminous flux as
Seeing the variations of no load voltage Vo and the short circuit current Isc with the luminous flux it
can be concluded that the internal resistance of a photovoltaic cell decreases with increase in luminous
flux.
Photovoltaic cells are mainly used in laboratory and research applications. The BPY10 is a commonly
used photovoltaic cell. One major application of photovoltaic cell is in supplying power to satellites and
extraterrestrial probes.
&%&
18.5 IR Emitter
Infrared-emitting diodes are solid-state gallium arsenide devices that emit a beam of radiant flux when
forward biased. The construction of the device is shown in Fig. 18.15. When the junction is forward
biased, electrons from the n-region will recombine with excess holes of the p-material in a specially
designed recombination region sandwiched between the p- and n-type materials. During this recombination
process, energy is radiated away from the device in the form of photons. The generated photons either
will be reabsorbed in the structure or leave the surface of the device as radiant energy indicated in
Fig. 18.15. The linearly related radiant flux in mW versus dc forward current for a typical device appears
in Fig. 18.16.
Note: There is almost a linear relationship between the two. A few areas of applications for such device
include card and paper-tape readers, shaft encoders, data-transmission systems and intrusion alarms.
Figure 18.15 IR emitting diode Figure 18.16 Flux versus forward DC current
18.6 Solar Cell

In the recent past considerable efforts have been made to extract energy from non-conventional sources.
The sunlight is the most important non-conventional source of energy. On a normal sunny day, the sun
provides energy density of 1.35 KW/m2. This huge amount of energy available free of cost, must be
collected to be used during energy crisis. The device that converts light (solar) energy to electrical
energy is given the name solar cell. Solar cells have generated interest as an alternative source of energy.
The basics of the p-n diode to convert the optical signal to electrical signal have already been discussed.
These arguments hold good here also. Solar cells operate without connecting any external power supply
to it and depend on the sunlight, to generate current and voltage. A situation can be imagined when the
sunlight falls on an unbiased p-n junction, i.e. electron-hole pairs get generated in the depletion width Wo
as shown in Fig. 18.17. These generated electron-hole pairs get collected at the two ends of the depletion
width under the influence of high electric field present across the depletion width. This gives rise to the
open circuit voltage Voc.
Figure 18.17 p-n junction illuminated by the sunlight

&%'
The basic construction of a silicon (p-n junction) solar cell should ensure that the light impinges
perpendicularly on maximum portion of the junction surface area. Also, the formation of the junction
should be near the surface of the semiconductor as well as metallic contacts should be made such that
almost all photons reach the junction surface. A pictorial view of the solar cell is shown in Fig. 18.18.
ITotal = Idiode - Ilight (18.6.1)
Figure 18.18 Sectional and top view of solar cells
The conventional current flow through a diode is expressed as

RS FG qV IJ - 1UV
I = I o exp (18.6.2)
T H KT K W
In presence of the sunlight, extra electron-hole pairs will be generated in the region Ln + Wo + Lp . As
very high field is present across the depletion width, the generated electron-hole pairs start drifting in
opposition to the forward biased current of the diode. It can be expressed mathematically as
RS FG qV IJ - 1UV - I
Itotal = I d + ( - I L ) = I o exp (18.6.3)
T H KT K W L
In Eqn. 18.6.3, the light dependent current IL depends partially on intensity and frequency v of
incident radiation, efficiency of generation h and reflection co-efficient R of the semiconductor surface.
The two limiting conditions of solar cells are:
∑ Open circuit voltage
∑ Short circuit current
18.6.1 Open Circuit Voltage

In an open circuit the current flow through the diode must be zero. Hence, equating Eqn. 18.6.3 to zero
with V = VOC and I = 0 yields as
R|S F qV I - 1U|V - I
I = 0 = I o exp OC
(18.6.4)
T| GH K T JK W|
B
L
or exp
FG V IJ = 1+ I
OC L
(18.6.5)
HV K I
T o
&&
Ê I ˆ
or VOC = VT ln Á1 + L ˜ (18.6.6)
Ë Io ¯
IL
For low intensity irradiations, 1 > . Under this condition Eqn. 18.6.6 expands to
Io
ÏÔ I 2 3 ¸Ô
1Ê I ˆ 1Ê I ˆ
VOC = VT Ì L - Á L ˜ + Á L ˜ - ◊◊◊◊◊◊◊˝ (18.6.7)
ÔÓ Io 2 Ë Io ¯ 3 Ë Io ¯
˛Ô
Higher terms of Eqn. 18.6.7 are much smaller than the first term and hence Eqn.18.6.7 reduces to
VOC = VT
FG I IJ
L
(18.6.8)
H Io K
Equation 18.6.8 indicates that the open circuit voltage for very weak light intensity is proportional to
the light generated current, i.e.
VOC µ I L (18.6.9)
In other words, this is the region where linear relationship holds good between the open circuit
voltage and light generated current.
For higher light intensities, Eqn. 18.6.6 reduces to
VOC = VT
FG I IJ
L
(18.6.10)
H Io K
For high intensities, the open circuit voltage VOC approaches the bandgap energy of the semiconductor.
In Si solar cell, VOC @ 0.7 V.
The plot of Eqn. 18.6.10 looks like the one shown in Fig. 18.19. The characteristic has been exaggerated
for clarity. It is evident from Fig. 18.19 that the device presents negative conductance in the fourth
quadrant. Therefore, the device can be used to supply power to the external load, if operated in the
fourth quadrant. Hence, it acts as a converter of optical energy into electrical energy. If the diode is
operated in the other three quadrants it functions as a sink of power just like an ordinary resistor.
The output power delivered to an external load by the solar cell is expressed as
RS FG qV IJ - 1UV - I V = I V |RSexpFG V IJ - 1U|V - I V

P = V ¥ I = I oV exp
T H KT K W L o
|T H V K |W T
L
o
FV I
= I V expG J - I V - I V o L (18.6.11)
HV K T
KT
where VT = @ 26 mV
q
&&
Figure 18.19 V-I characteristics of solar cell
The maximum power can be obtained after differentiating and equating Eqn. 18.6.11 to zero, i.e.
|RS FG V IJ - 1|UV - I V = I V expFG V IJ - I V - I V

I oV exp L o o L
|T H V K |W
T HV K T
dP
o
F V I V expFG V IJ - ( I
= I expG J + I o o + IL) = 0
dV HV K V HV K
T T T
IL I + Io Ê V ˆ ÊV ˆ Ê V ˆ ÊV ˆ
or 1+ = L = Á1 + ˜ exp Á ˜ = Á1 + m ˜ expÁ ˜ (18.6.12)
Io Io Ë VT ¯ Ë VT ¯ Ë VT ¯ Ë VT ¯
Io + I L
or I o expVm VT = (18.6.13)
1 + Vm VT
In Eqn. 18.6.13 Vm corresponds to the maximum power condition. This value can be obtained by
solving the transcendental Eqn. 18.6.13. The current corresponding to the maximum power condition
can be obtained from Eqn. 18.6.4 after substituting V = Vm, i.e.
Im = I o expVm /VT - ( I o + I L ) (18.6.14)
Now substituting I o expVm VT from Eqn. 18.6.13 in Eqn. 18.6.14 yields
Im =
Io + I L
- ( Io + I L ) = ( I o + I L )
FG
1 - 1 - Vm VT IJ = ( I + IL )
F -V Im (18.6.15)
1 + Vm VT H
1 + Vm VT K o GH V + V JK
T
m
Now, the maximum power can be expressed as
Pmp = VmIm = Vm ( Io + I L )
FG -V IJ
m
(18.6.16)
HV +V K
m T
&&
F I
1+ L
I
=
F I GG
2
Vm Io JJ (18.6.17)
GH JK G
VT
Io
V
1+ m JK
H VT
The efficiency of the solar cell is expressed as
Ê IL ˆ
Pmp
2 ˆ
Ê Vmp Á 1+ I ˜ Ê 1 ˆ
˜ Io Á
o ˜
h= = Á (18.6.18)
Pin V
Ë T ¯ Á Vmp ˜ ÁË Pin ˜¯
ÁË 1 +
VT ˜¯
where, Pin = incident power of the sunlight impinging on the solar cell
@ 1.35 KW/m2 on normal sunny day
The efficiencies of Si and GaAs solar cells lie somewhere in between 10% to 15%.
18.6.2 Short Circuit Current

The second limiting case occurs when the output of the cell is short circuited, i.e. R = 0 and VOC = 0.
The short circuit current is now only due to light generated current IL. Thus,
Isc = I L (18.6.19)
The other figure of merit of the solar cell is called the fill factor (FF). It is defined as
Vmp ¥ I mp
FF = (18.6.20)
VOC ¥ I sc
The FF gives a measure of how close are the third quadrant characteristics to being rectangular or
ideal. In an ideal diode, the FF is 1. In an actual diode the current is given by I = Io exp
FqV
- 1 . WeI
HKT K
define a practical diode as one whose characteristic can be written as I = Io exp
qVFG IJ
- 1 , where h is
hKT H K
called the ideality factor and is greater than or equal to 1. Hence, for a practical diode, the open circuit
voltage VOC and FF are expressed as
h KT Ê I ˆ Vm ¥ I m
VOC = ln Á 1 + L ˜ and FF = (18.6.21)
q Ë Io ¯ hKT Ï I L ¸
ln Ì1 + ˝ I L
q Ó Io ˛
It is clear from the V-I characteristics that the reverse current decreases with decreasing reverse
voltage. The no load voltage of a photovoltaic cell varies non-linearly with the amount of luminous flux
falling on the surface of the device. This characteristic between the no load voltage and luminous flux
has been shown in Fig. 18.14 As the V-I characteristic in the fourth quadrant approaches a rectangle,
the FF also approaches unity. However, the typical value of the FF for most of the solar cells is
approximately 0.7 V. Let us visualize the short-circuit current in the range where it is a linear function of
&&!
the illumination. In other words, it will double for the same increase in illumination {fcl and 2fcl in
Fig. 18.19} while the change in VOC is less for this region. The major increase in VOC occurs for lower-
level increases in illumination. Eventually, a further increase in illumination will have very little effect on
VOC, although Isc will increase, causing the power capabilities to increase.
Selenium (Se) and silicon (Si) are the most widely used materials for solar cells, although GaAs, InAs
and CdS, among others, are also used. The wavelength of the incident light will affect the response of
the p-n junction to the incident photons. Figure 18.20 shows how closely the selenium cell response
curve matches to that of the eye.
Figure 18.20 Spectral response of Si, Se and human eye

This in fact has widespread application in photographic equipment such as exposure meters and
automatic exposure diaphragms. Silicon also overlaps the visible spectrum but has its peak at the IR
(8000 Å) wavelength which falls in the Infrared Region IR. In general, silicon has a higher conversion
efficiency and greater stability and is less subject to fatigue. Both materials have excellent temperature
characteristics. In other words, they can withstand extremes of high or low temperatures without a
significant drop-off in efficiency.
The electrical characteristics of few solar cells are presented in Table 18.1.
Table 18.1 Electrical characteristics of solar cells
Part No. Active Area Test voltage Max current

2
3013 0.23 cm 0.4 V 4.2 mA
2
3014 0.42 cm 0.4 V 8.4 mA
2
3024 1.87 cm 0.4 V 38 mA
3064 2.1 cm2 0.2 V 8.4 mA
An innovation in the use of solar cell appears in Fig. 18.21. The series arrangement of solar cells
permits a voltage beyond that of a single element. The performance of a typical four-cell array also
appears in this figure.
At a current of approximately 2.6 mA output voltage is about 1.6 V resulting in an output power of
4.16 mW. The Schottky barrier diode is included to prevent battery current drain through the power
converter. The resistance of the Schottky diode is so high that it will not allow any charge flowing down
through (+ to ). The power converter will appear as an open circuit to the rechargeable battery and do
not draw current from it.
&&"
Figure 18.21 Response of solar power converter
The Lockheed Missiles and Space Company acquired a grant from the National Aeronautics and
Space Administration to develop a massive solar-array wing for the space shuttle. The wing size measures
3.5 ¥ 105 ft2 when extended and will contain 41 panels, each carrying 3060 silicon solar cells. The wing
can generate a total of 12.5 KW of electrical power. Typical levels of efficiency range form 10% to 40%
fi a level that should improve measurably if the present interest continues.
18.7 Light Emitting Diodes (LEDs)

The Light Emitting Diodes (LEDs) sometimes back were called Solid State Lamps (SSL). The LED is a
special purpose diode designed for emitting light under forward biased condition. It is a specially prepared
p-n junction diode that gives off visible light when forward biased (energized). The p-n junction of LED
is made from heavily doped (more than 1026/m3) materials (both p- and n-types). It differs from ordinary
rectifying diodes in following ways:
∑ Typical values of forward dc current is in the range of 5 mA to 100 mA
∑ Typical value of reverse voltage maximum is 5 V that is very low w.r.t. a rectifying diode
∑ Typical forward voltage drop VF ranges from 1.65 V to 2.22 V depending upon type and colour
as against forward voltage drop of 0.7 V for a Si diode
The process of giving off light energy by applying an electrical voltage is called electro-luminescence
(emission of light from a solid with the excitation provided by an electrostatic field). Electrons and holes
recombine under the forward biased condition within the structure and primarily very close to the
junction in the depletion region. It is well known that when a free electron recombines with a free hole,
it may fall all the way from an unbounded or higher energy level to its ground state releasing a photon of
wavelength corresponding to the energy level difference associated with the transition. The radiation
due to recombination so produced by the LED may range from near ultraviolet, through the visible down
to the far infrared region of the electromagnetic spectrum. The visible spectrum extends from 0.4 mm to
0.76 mm. The eye has a maximum response to light at 108 cm. As discussed before, the LED p-n
junction is specially prepared to emit electromagnetic radiation that may be visible or non-visible. The
injection luminescence in a p-n junction diode is illustrated in Fig. 18.22(a).
&&#
Under forward bias, majority carriers from both sides of the junction cross the internal potential
barrier and enter the material at the other side. The majority carriers coming from any one side become
the minority carriers for the other side of the p-n junction and increase the population of the minority
carriers from the normal value. The process of injection is called minority carrier injection. The excess
minority carriers diffuse away from the junction as depicted in Fig. 18.22(b).
The excess electron concentration Dn(x) at any distance x in the p-material is described as a function
of distance x from the edge of the depletion region as
F
Dn(x) = Dn ( x = 0) exp -
x I (18.7.1)
GH Lp JK
where, Dn(x = 0) = charge density at the origin, i.e. x = 0.
Figure 18.22(a) Minority carriers injection and radiative recombination

with majority carriers in forward biased p-n junction
Figure 18.22(b) Minority carriers injection in forward bias p-n junction
Ideally in an LED every injected electron should have taken part in a radiative recombination and
given rise to an emitted photon. However, in practice it is not the case, and the efficiency of the device
may be described in terms of the quantum efficiency. The quantum efficiency is defined as the ratio of
the rate of emission of photons to the rate of the supply of electrons.
In the reverse bias, no carrier injection takes place and consequently no light is emitted. Under
reverse bias condition, the diode current is expressed as
&&$
RS FG qV IJ - 1UV
I = I o exp (18.7.2)
T H hKT K W
where, Io = Reverse saturation current and is constant
The numbers of radiative recombination that take place is normally proportional to the carrier injection
rate hence, to the total current flow. If the transitions take place directly between the states at the
bottom of the conduction band to the top of the valence band then emission wavelength lg is related as
hC
= EC EV = EG (18.7.3)
lg
hC
or lg = (18.7.4)
EG
EG = photon energy in joules
h = Plancks constant = 6.624 ¥ 10 34 joules sec .
C = velocity of light = 3 ¥ 108 m/s
lg = wavelength in meters.
For example, the GaAs has an energy gap of 1.43 eV. Hence, corresponding lg is
6.625 ¥ 10 -34 ¥ 3 ¥ 108 19.875 ¥ 10 7
= = = 870 nm.
1.43 2.288
The energy gap and the corresponding wavelength for few semiconductor are shown below.
In fact because of thermal excitations, electrons in the conduction band have most probable energy
that is KT/2 above the bottom of the conduction band. Band-to-band transition therefore results in a
slightly shorter emission wavelength than that given by the Eqn. 18.7.4, and self absorption can further
distort the situation. However, most transitions involve energy levels within the energy gap and hence
Eqn. 18.7.4 represents shorter wavelength limit.
&&%
18.7.1 Radiative Recombination

The radiative recombination in semiconductors occurs predominantly via three different processes,
namely:
∑ Interband transitions
∑ Recombination via impurity centres
∑ Exciton recombination
The radiative recombination/transition takes place between injected electrons into the n-region and holes
into the p-region as shown in Fig. 18.23. In such transition, the electrons move from conduction band
to valence band and the holes move from valence band to conduction band. Figure 18.24 is a general
energy level diagram that is used to describe the possible radiative and non radiative electron transition
involved in LEDs. Actually radiative and non radiative transitions are experienced in any semiconductor
under forward bias but in many cases the non radiative transitions predominate or the photon losses are
too excessive for observation of any external radiation.
All semiconductors p-n junctions always give off this type of energy either in the form of heat or in
the form of photons.
Figure 18.23 Cross section of LED
In Si and Ge semiconductors greater percentage of this energy is given off in the form of heat and
emitted light energy is so insignificant that it does not seem to emit light at all. Two types of radiative
recombination are commonly encountered in LEDs. They are, direct recombination and indirect
recombination
Figure 18.24 Direct and indirect transitions
These two types of recombinations are dependent on the bandgap of the semiconductor material. In
either case of recombination, the wave length l of radiation emitted is related with the bandgap energy
EG of semiconductor by
&&&
hC
EG = hv = (18.7.5)
l
hC 12423 o 1240 1240
or l= = A @ nm = nm (18.7.6)
EG EG EG hn(eV )
6.624 ¥ 10 34 Js
where h = Planks constant = = 4.14 ¥ 10 -15 eV.s
1.6 ¥ 1019 J
C = velocity of light of EM radiation = 3 ¥ 108 m/s.
EG = bandgap in eV
1 Å = 108 cm = 1010 m and 1 mm = 106 m.
It is well known that the light given off is described by its wavelength and intensity.
The colour of LED depends on the energy involved. Most of the LEDs are made of gallium and
indium compounds. The LEDs are low power devices, typically of the order of milliwatts. This suggests
that LEDs are useful as an indicator but are not for illumination. Normally they are used for power
indication and alphanumeric displays.
Figure 18.25 depicts the important phenomenon of emission and absorption of photons from various
materials, which obey Eqn. 18.7.6. Since the four valence electrons of Ge-atoms are farthest from the
nucleus, there is least influence of attractive force between the valence electrons and the positive charges
in the nucleus. When electrons make transition from valence shell to inner cell, i.e. from a higher energy
level to a lower energy level, they give off energy in the form of photons, (Case A) as in Fig. 18.25,
equal to the difference in energy levels, i.e.
E4 E3 = hv (18.7.7)
On the contrary, for making transition from valence shell to any higher shell, (Case B) as shown in
Fig. 18.25, the energy has to be supplied externally. The amount of energy required is equal to the
energy required for detaching it from valence shell. This process of detaching electrons is called ionization.
Figure 18.25 Transition of valence electrons

The direct bandgap and indirect bandgap transitions can also be explained with the help of E K
diagram shown in Fig. 18.26. In E K diagram only vertical transitions are allowed. The non-vertical
transitions can occur as shown in right side of Fig. 18.26, but to conserve the wave vector K, a photon
must either be created or destroyed at the same time. The equation for the wavelength of the emitted
photon is given by
&&'
hC
= EG ± Ep (18.7.7)
l
where Ep = photon energy.
The + and signs correspond to photon annihilation (absorption) and creation respectively. The
photon energy is of the order of 0.01 eV and hence photon wavelength in fact differs little from lg. In
Fig. 18.26 there is no change in the electron k value whereas in right side of Fig. 18.26 it does change.
18.7.2 LED materials

The wave length range of visible spectrum extends from 4000 Å (0.4 mm = 400 nm) to 7600 Å
(0.76 mm = 760 nm). Hence, it is essential that semiconductors suitable for visible emitters should have
EG in the range from 1.75 eV to 3.15 eV. Element semiconductors like Ge and Si have EG outside this
range, i.e. 0.72 eV and 1.12 eV respectively as indicated in Table 18.2 hence, they are not suitable for
use as LEDs.
Figure 18.26 Direct and indirect band transitions

The optical bandgaps of several materials are presented in Table 18.2. Many group III V semiconductors
possess EG in the above range which make them useful for LEDs. In addition, some group IIIV
semiconductors also appear to be attractive for LEDs but their technology being difficult, they are not
exploited for this purpose.
Table 18.2 Optical energy band-gaps
Name Chemical name Optical energy band-gap (eV)
Cadmium sulfide CdS 2.4
Gallium phosphide GaP 2.2
Cadmium selenide CdSe 1.7
Gallium arsenide GaAs 1.4
Silicon Si 1.12
Germanium Ge 0.72
Indium arsenide InAs 0.43
Lead sulfide PbS 0.37
Lead telluride PbTe 0.29
Lead selenide PbSe 0.26
Indium antimonide InSb 0.23
&'
The requirements of a good LED material are:

∑ The ability to fabricate a p-n junction to achieve good injection and illumination efficiencies and
at the same time
∑ Extract a reasonable fraction of generated light
The choice is mainly confined to GaP and GaAsP although LEDs from other materials have also been
produced. The gallium aluminium arsenide ( Al xGa 1-x As ) is fairly newcomer to the family of LEDs. It is
used in highly efficient red and infrared LEDs.
Thus, the main requirements for suitability of the LED material is:
∑ it must have energy gap in the range of visible range, i.e. 1.75 eV to 3.15 eV. Generally for
visible raiation, gap should be more than 2 eV
∑ both n- and p-type should have low resistivity. Unfortunately materials with large band gap have
high resistivity even after doping
∑ efficient radiative path must be provided
In most of the cases, there are difficulties in preparing the material with wider energy gap. This is
because the materials have high melting temperature and low structural stability. The GaAs1- x Px compound
behaves as direct band gap semiconductor for 0.45 ≥ x and has an indirect band gap for larger values of
x. Any composition can be derived using vapour-phase epitaxial growth. However, commercially available
LEDs employ compositions that emit red, yellow and orange emissions.
18.7.3 Direct Bandgap LEDs

Gallium arsenide (GaAs) is one of the earliest preferred materials used for Infrared LEDs (IREDs).
Other popular direct bandgap semiconductors for LEDs are InAs, InP and GaSb. But all these
semiconductors have EG below 1.75 eV. Therefore, the resulting emission of p-n junction of these
materials is outside the visible spectrum, i.e. in IR region.
In the direct bandgap semiconductors (GaAs, GaSb) the probability of recombination is high, because
electrons and holes have the same value of momentum. Hence, in this case, the internal conversion
efficiency, i.e. efficiency of converting electrical input to EM radiation is high. Most of the electrons
give up energy in the form of radiant energy approximately equal to GaAs band gap of 1.4 eV, i.e. the
transition takes place all the way from conduction band to valence band as shown by A in Fig. 18.25.
A suitable upconverting phosphor can be coated on an IR-emitting LED so that visible light can be
produced by excitation of the phosphor. The colour of light produced in this manner is governed by the
characteristic of the phosphor. As an example, a GaAs p-n junction diode coated with phosphor particles
held in an adherent binder serves as a visible emitter. But, such a device has poor efficiency as the
upconversion operation is inefficient.
The ternary alloys can be formed between a binary compound with low direct band-gap (i.e. GaAs)
and another binary compound (which may be of the indirect band-gap type) having large EG (i.e. GaP).
Such an alloy has the advantage of varying EG of the semiconductor monotonically between values of
its constituents by controlling their proportion. Thus, GaAs1 xPx can have its EG varied smoothly from
1.44 eV (i.e. EG of GaAs) to 2.66 eV (i.e. EG of GaP by controlling x from 0 to 1). Where x represents
the fraction of p-atoms on the volume sites. For example, a crystal designated as GaAs0.8P0.2 has 80%
As and 20% P atoms on the non-gallium sites of the lattice. The band-gap of the resulting material varies
&'
almost linearly with x until the 0.44 composition is reached and electron-hole recombination is direct
over this range. The most commonly used alloy composition for LED display exists at x = 0.4. Moreover,
the alloy continues to remain as the direct band-gap type for values of x below a crossover value (which
in this case is x = 0.46) for which EG is 1.99 eV. This makes it possible to obtain visible emitters using
such a ternary alloy. Ternary alloys suitable for visible emitters are given in Table 18.3 along with their
important properties.
Although the above LEDs have high internal conversion efficiency, they have the disadvantage of
poor external efficiency. This is primarily due to the strong internal absorption of the light generated due
to the crystalline structure of the material. Typically, GaAsP LED has external efficiency of the order of
0.5% only. However, some improvement in this parameter is possible by proper shaping of the LED, i.e.
in the form of a dome that increases the transmissivity of the device's surface. But this is expensive. An
alternative technique which is preferred uses hemispherical domes and lenses cast from epoxy or other
resins over the LEDs. With this approach, commercial GaAsP LEDs have yielded external efficiency in
the range of 0.5 to 2%.
Table 18.3 Popular ternary alloys for visible LEDs
Direct-indirect transition
Material Bandgap (Gap) xo (eV) Colour
GaAs1xPx 1.44 to 2.66 0.46 1.99 Red, Green
Al xGa 1-x As 1.44 to 2.16 0.31 1.90 Red, Green
In1- xGa x P 1.34 to 2.26 0.70 2.18 Yellow
18.7.4 Indirect Bandgap LEDs

Popular indirect bandgap semiconductors such as GaP, GaN, AlAs and SiC are used to produce visible
light LEDs and their most probable transition is in Fig. 18.26. Indirect bandgap semiconductors have
very poor efficiency. The indirect transition occurs when the electron and hole momentums (mass ¥
velocity) differ. In this case an intermediate transition must be made and most of the energy is given off
in the form of heat. The probability of recombination of electrons and holes in p-n junctions of these
materials being low, impurity centres in controlled quantities are usually introduced during device
fabrication to improve internal conversion efficiency of the LEDs. Only limited number of impurities are
suitable for this purpose. For example, the selective introduction of N in GaP p-n junction diode facilitates
green emission with the internal efficiency (1%). Also, the use of Zn and O as impurities in GaP p-n
junctions makes it possible to realize red emission with low internal absorption of GaP devices (and in
general LEDs in the indirect bandgap material) that leads to high external efficiency of the LEDs.
Typically the external efficiency of red-emitting GaP LEDs is 3% to 7%, whereas that of green-emitting
GaP LEDs is about 0.6%.
The typical single element LEDs can be in TO 5 or TO 18 type packages with a suitable lens cover or
in epoxy or in epoxy package with a hemispherical dome at the top. The LED arrays are generally
packed in DIP and similar packages do exist for compatibility with ICs in system applications.
&'
Figure 18.27 gives the performance characteristics of LEDs in different materials (Thomas publication,
1971). It is of interest to note that red, green and yellow emissions are directly realizable whereas blue
emission is possible only through upconversion of IR emission. A comparison of LEDs (Bergh and
Dean loc. cit., Nuesse 1972) from the point of view of several important parameters is given in
Table 18.4.
While these LEDs are suitable for instrument displays, opto-electronics, etc. their radiance (i.e.
optical power radiated into a solid-angle, per unit area of emitting surface) is low, generally below
0.25 W/sr/cm2. However, small-area LEDs in AlxGa1xAs using double hetrostructure (Christian 1974,
Burrus and Ulmer 1971) construction and mounted on heat sink, have yielded radiance of
20100 W/sr/cm2, making it possible to deliver power of about 1 mW into optical-fiber waveguides.
This family of devices is now growing.
Figure 18.27 LED performance in different materials
Table 18.4 Performance characteristics of LEDs

Material Availability Colour Brightness Luminous efficiency Brightness
(lm/mW) (ft/cm2)
GaP:ZnO Yes Red 670 20 350
Al 0.3Ga 0.7As No Red 675 16 140
As0.6P0.4 Yes Red 660 42 145
In0.42Ga 0.58 P No Amber 617 284 110
GaAs0.5P0.5 Yes Amber 610 342 35
GaAs0.25P0.75:N No Amber 610 342 40 100
SiC Yes Yellow 590 515 10
In0.4Ga 0.5P No Yellow 570 648 115
PGaP:N Yes Green 550 677 470
The luminous efficiency of low-power visible LEDs varies from 50 to 1000 lumen/Watt (Lm/W). As
the energy gap of the LED is increased (emission wavelength decreased), the probability of direct
&'!
radiative transition decreases because the crystal flows provide intermediate energy levels (through,
which two step radiationless transition can be made). Three optical phenomena that contribute to the
LEDs low quantum efficiency are:
∑ Photon absorption due to the capacity of the LED material
∑ Reflection from air/LED material interface due to the difference in index of refraction
∑ Total internal reflection of photons incident at angles greater than the critical angle
18.7.5 LED Specifications

Since LED is basically a diode, it is current dependent. The maximum value of the continuous forward
current of a typical LED at 25°C is 100 mA and at 100°C it becomes 20 mA. Table 18.5 depicts the
maximum power rating, maximum DC current and the forward voltage of a typical LED of various
colours. Most important characteristic of the LED is the maximum rating.
The light emitted by the LED is a function of the current. As the current increases, the light intensity
also increases to a maximum limit of the current above which the device fails. Thus, the current through
the LED is limited to achieve a particular light level. The other ratings of LEDs are shown in Table 18.6
and 18.7. Table 18.7 gives the LED radiant output power Po at a given forward current IF. The nominal
efficiency thus, can be calculated as
Po Po 550 ¥ 10 6W
h= ¥ 100 = ¥ 100 = ¥ 100 = 0.92%.
Pin VF I F 50 ¥ 10 3 A ¥ 1.2V
Table 18.5 Colours and ratings of LEDs
Colour Max power rating Max DC current Forward voltage

Red 100 mW 35 mA 1.65 V
Green 100 mW 35 mA 2.2 V
Yellow 100 mW 35 mA 2.1 V
Orrange 100 mW 35 mA 2.0 V
The forward current voltage characteristics of GaAs LED is shown in Figs. 18.28 and 18.29. It
demonstrates the non-linearity of the LED radiant output power with forward current above a few
hundred milliamps. The radiant output power approximately doubles as IF doubles.
Table 18.6 Maximum ratings and thermal characteristics of GaAs

Ratings Symbol Value
Reverse voltage VR 3V
Forward current IF 80 mA
Total device dissipation at 25°C PD 120 mW
Derate above 25°C PD 2 mW/°C
Operating and storage junction temp. Tj,Tstg 40°C to 85°C
Thermal resistance(junction to ambient) qjA 500°C/W
&'"
Table 18.7 Electrical and optical characteristics of GaAs
Characteristic Symbol Min. Typical Max.

Reverse leakage current (VR = 3 V, RL = 1 MW) IR 50
Reverse breakdown voltage (IR = 100 mA) BVR 3V
Forward voltage (IF = 50 mA) VF 1.2 V 1.5 V
Total capacitance (VR = 0 V, f = 1 MHz) CT 150pF
Optical Characteristic
Total power output(IF = 50 mA) PO 200 mW 550 mW --
Radiant intensity (IO = 10 mA) IO 2.4 mW/sterdian --
Peak emission l 900 nm
Special line half-width 40 nm
Figure 18.28 shows that the radiant output power of an LED decreases as its junction temperature
increases. This phenomenon can be explained by the fact that as the LED temperature is increased,
more electron-hole recombinations become non-radiative.
Figure 18.28 Instantaneous forward current (mA)
Figure 18.29 Normalized power output with junction temperature

&'#
Advantages of LEDs
Solid state light emitting devices whether they are discrete units or comprises of entire arrays, have
some very desirable features which include:
∑ High reliability
∑ Very fast response time (few nano seconds)
∑ Low cost
∑ Low voltage DC operation
∑ Adaptability to miniaturization
∑ High stability
∑ Rugged
∑ Low power consumption
∑ Longevity as compared to lamps
∑ Linearity in output power with forward current (above some nominal value of I) over a wide
range
∑ Available in variety of colours
Another interesting feature is that solid-state devices are almost monochromatic (single colour) which is
attributed to the fact that their emitted radiation is distributed over a very narrow bandwidth. The
fabrication process to yield a variety of colours for different applications, of course may change this
colour. Because of their inherent solid structure such exemplary devices as light emitting diodes (LEDs)
can be built with integral lenses to magnify and focus the light.
Disadvantages of LEDs
∑ Temperature dependence of radiant output power and wavelength
∑ Sensitivity to damage by over voltage or over current
∑ Theoretical overall efficiency is not achieved except in specially cooled or pulsed condition
∑ Wide optical bandwidth compared to the LASER (10 versus 102 nm)
∑ Washout under high ambient light conditions
∑ High cost for large digits (0.5 or 12.7 mm)
The ability of a material to produce a cold light has been known for almost 70 years but practical devices
entered the electronics realm very late. The earliest reported incidence of solid state light emission was
with a crystal of carborandum (silicon carbide, SiC). The carborandum crystal required a potential of
almost 30 V whereas LEDs require only a few volts. The introduction of the LED has greatly enhanced
electronics, particularly in the areas of indicators, readouts, and in remote control devices. One of the
many varieties of LEDs is the semiconductor injection LASER. Unfortunately most injection LASER
diodes operate in the pulse mode only, yet a few diodes have been designed recently that will operate
continuously at ordinary room temperatures.
18.7.6 Geometry of LEDs

The solid state readout has caused the older multiple (one character in format of the other) glow tube
readout to be almost extinct now. Where the glow tube was ambiguous in its ability to represent a
&'$
number or figure without confusion, the LED readout matrix presents any of its readout characters in
the same plane. The glow tubes and filament readouts that operated in one plane consume much more
power both in terms of increased voltage requirements and current drain. The liquid crystal readout may
seem to be in direct opposition to the LED readout but it does not generate light, therefore, a light source
is required with these readouts. These devices are semiconductor p-n junction diodes that emit light
when holes and electrons combine under forward-bias conditions. The material used in the construction
of the more commonly available LEDs is gallium arsenide phosphide (GaAsP) and gallium phosphide
(GaP) which are complex chemical substances derived from gallium, arsenic and phosphorus and are
generally driven by a constant current source. The LED alphanumeric displays are available with either
segmented or dot matrix characters as shown in Fig. 18.30.
Figure 18.30 Symbolic array geometry
In segmented display (GaAsP) device, current ranges from 5 mA to 30 mA per segment, depending
on display size. Segmented alphanumeric LED displays can have as many as seven segments per character
or as many as twenty two. The segments may be inter connected internally in either a common cathode
or common anode configuration. Common cathode display requires a current source drive circuit and
common anode devices use current sink drives. Low voltage and current requirements enable LED
displays to interface with most IC families. Wherever IC cannot meet drive requirements, transistors
can be inserted between the ICs and the display devices.
18.7.7 Colours of LEDs

The GaAsP on a GaAs substrate and GaP technologies continue to be the work horses of the LED
industry for producing efficient red LEDs. However, the addition of nitrogen impurities to GaP devices
produces an efficient green colour. The same impurity added to GaAsP and GaP on GaP substrate
produces orange and yellow in addition to green. The GaAsP LEDs output is in the wavelength region of
670 nm that appears to be red to the human eye. Ofcourse, LEDs are made from compounds other than
GaAsP, but the most common are the gallium arsenide. Figure 18.3 shows different LED light sources
in comparison with the vision of the human eye and with the vision or more appropriately the sensitivity
of silicon photosensor devices. The curve for a standard tungsten filament lamp is included to give an
idea of the different emission regions. The LED sources are restricted and are relatively narrow in
bandwidth, while the tungsten source is extremely broad. The maximum output of the tungsten lamp
occurs at a point where the human eye has no sensitivity at all.
A sensitivity curve for the human eye is shown in Fig. 18.3. In order to enable comparisons to be
made it is both greatly expanded and calibrated in relative response in lumens/watt. The characteristics
&'%
of various LEDs were presented in Tables 18.5. Many more types exist, but we will use these for a basis
to begin with. These characteristics differ in many respects yet, they do posses parameters that are
similar in nature. LEDs in general are low-heat-generating devices. The cliché cold light does apply
here, especially if you compare the thermal output of a solid state lamp with that of a tungsten lamp.
Figure 18.3 shows the typical curve of a tungsten lamp with a temperature (colour temperature) of
2580 K. Notice that most of its output energy is in the nonvisible portions of the electromagnetic
spectrum. Human vision extends roughly from 0.360 mm to 0.760 mm. The relative eye sensitivity is
maximum for l = 0.550 mm and is V(0.550 mm) = 1. The value of V(l) falls to nearly zero at the two
extremities of visible spectrum, i.e. l = 0.360 mm to 0.760 mm. The maximum output of tungsten lamp
occurs at 1.1 mm and it extends deeply into the infrared region. It can be said that the tungsten lamp is
as good, if not better, a thermal source than a light source. Also notice that its energy output is extremely
broad. The reason is that it is an incandescent lamp and uses the heating effect of an electric current
through its filament. This brings up other advantages of the solid-state lamp. A filament must be heated
to a high temperature but the filament will undergo chemical combination with the gases within the bulb
of the lamp. The higher the operating temperature, the faster the combinations will occur, decreasing
the life time of the bulb. In contrast, the LED enjoys a particularly long expected operating life of about
100,000 hours. (Note: some modern incandescent displays are completely evacuated and provide
comparable life expectancies).
The filament takes time to heat up therefore, the tungsten lamp cannot be modulated very high in
frequency, whereas the semiconductor light source can be modulated at frequencies above 100 kHz
easily. The LED has a fast response with a rise time and a fall time measured in microsecond. This
means that the response to an electric excitation will be quick (rise time) and also that the LED will
extinguish its output almost immediately with the removal of the excitation energy. The filament lamp
will continue to glow even after the current is removed since the filament must cool from its temperature.
Needless to say, filament lamps are more fragile than LEDs. Most filament lamps also require some
sort of holder while the LED because of its built-in strength, rarely requires any support. By strength,
we mean here the structural strength. The LED has a very small weight, so the leads (contact wires) will
generally support the light source. In some cases a positioner is used to keep the LED in position with
reference to associated components. For compatibility the low impedance of the solid state lamp makes
it ideal in conjunction with most semiconductor circuitry. The light-emitting diode looks like a forward-
biased diode with a breakdown voltage of approximately 1.6 V which indicates that a low voltage power
supply is required. The LEDs are usually fabricated using a plastic or metal-plastic encapsulation. An
LED can be made into various sizes and shapes as depicted in Fig. 18.31. LEDs are used not only as
status indicators (light sources) but also as readouts and light sources for detectors and monitors.
Figure 18.31 Shapes of LEDs
Because an alphanumeric display is designed to impart visual information to the viewer, the first
consideration for selecting a particular display is readability that is a function of character size and
&'&
brightness. Required brightness depends on ambient light intensity in the intended environment. As the
size of the display character increases, luminous intensity must likewise increase to maintain the same
brightness level. Ambient light level of the operating environment can either be measured or estimated
from information provided in Table 18.8. Once ambient light level is determined the required luminous
intensity is then obtained for a given character size and ambient light level.
Table 18.8 Typical ambient light levels intensity
Ambient light (ftcd)

Day light: bright and clear 8500 and 1600
Office: general and typing and computer operation 100 and 150
Manufacturing: electrical assembly and tests and rough bench wire 100 and 50
Residence: kitchen, study, and general 150, 70, 10
18.7.8 Intelligent Display Modules

The most common LED display is a seven segment display as shown in Fig. 18.32. Each of the segment
of the display contains actually an LED. If power is applied to a particular segment, that segment starts
emitting light. The displays come individually or in packages containing two or more digits worth
display.
Minimum luminous intensity (brightness) in segmented characters varies between colours. For example,
the opto-electronics division of General Instrument Corp. (Palo Alto, Calif.) offers their seven segment
display in all four colours. A single segment in their 0.3" characters varies in minimum brightness from
125 cd for red and green to 320 cd for high-efficiency red and yellow to 510 cd for orange with a 10 nA
drive current.
Figure 18.32 Seven and eight-segment displays
The display packages including driver and logic circuitry are called smart or intelligent displays.
These devices range from displays with integral circuits that reduce the need for external interface to
display panels equipped with a microprocessor. The seven segment displays are available basically in
two forms: common anode and common cathode.
Figure 18.33 shows arrangements of common anode and common cathode types of LED displays.
Seven segments a, b, c, d, e, f and g of a seven segment display consists of seven LEDs or LCDs. Thus,
each segment requires at least one LED or LCD. One extra LED or LCD is added to represent the
decimal point. LT542 and 543 are commonly used seven segment display devices which are readily
available in the market.
&''
Figure 18.33 Common anode and common cathode type seven segment displays
The 7447 is a TTL compatible seven segment decoder/driver. The BCD input to be decoded is
applied to A, B, C and D as shown in Fig. 18.34(a). The output of Fig. 18.34(a) is used to drive a seven
segment display. The pin representation of the 7447 is depicted in Fig. 18.34(b). The BCD inputs allow
the 7447 to output a low for a particular segment represented by the BCD inputs in common anode
configuration. This is called static display as a constant current always flows through the segments.
Fig. 18.34(c) is an integrated circuit of Fig. 18.34(a).
Each segment takes about 20 mA to 40 mA to get lighted. The voltage drop across the LED, when
lighted, is approximately 1.5 V. The output voltage of the 7447 goes down maximum by 0.4 V at 40 mA.
Hence, it can be assumed that at 20 mA, it goes down by 0.2 V. Thus, voltage drop across the current
3◊ 3 V
limiting resistor is = 5 (1.5 + 0.2) = 3.3 V. Then the value of current limiting resistor =
20 mA
= 165 W.
The corresponding standard value is 150W. A simple arrangement of 7447 and seven segment display
is shown in Fig. 18.34(c). Microprocessor control in both units provides a variety of display features
including left/right display entry, horizontal scroll, carriage return/line feed, editing capability, insert or
delete characters and blinking ON/OFF cursor. Data input can be upper and lower-case full ASCII
character set. However, the units only display upper-case character set. Data output retains the same
upper and lower case format as the input of the devices.
Figure 18.34 (a) Seven segment decoder/driver Figure 18.34 (b) 7447 Pin diagram
'
Figure 18.34 (c) 7447 and 7-segment display connected
18.8 LED Fabrication

The LEDs of GaP and GaAsP are fabricated by successive growth of appropriately doped n- and p-
layers of these compounds onto a GaP or GaAs substrate. These layers are grown either by liquid phase
or vapour phase epitaxy. The device structure may vary depending upon the applications and the material
used. The basic LED structure has the flat-diode configuration as shown in Fig. 18.35. The performance
of LED can further be improved by designing the diode geometry so that more emitted light arrives at an
angle lower than the critical angle qC and coating the surface with a medium of refractive index n =
(n1n2)1/2. The fraction of the total diode current that is carried by electrons being injected into the p-side
of the junction ae is given by
Dn n p
-1
ae =
Ln
=
1 R| F D I F p I F L I U|
= S1 + G p n n
(18.8.1)
Dn n p Dp pn F D IF p IF L I | H J V
D K GH n JK GH L JK |
+ 1+ G
p n n T n p p W
Ln Lp H D JK GH n JK GH L JK
n p p
Figure 18.35 LED construction
KT KT
Using Einstein relationship Dn = m n and Dp = mp (18.8.2)
q q
and also np*pp = n2i = pn*nn (18.8.3)
'
Ï KT ¸
mp Ê ˆ Ê 2
ÔÔ q Ln ni / nn ˆ ÔÔ ÔÏ Ê m p ˆ Ê Ln ˆ Ê p p ˆ Ô¸
or ae = Ì1 -
KT Á ˜Á 2 ˜ ˝ = Ì1 Á ˜ Á ˜ Á ˜ ˝ (18.8.4)
Ô m n Ë Lp ¯ Ë ni / p p ¯ Ô ÔÓ Ë m n ¯ Ë Lp ¯ Ë nn ¯ Ô˛
ÔÓ q Ô˛
It is well known that in III IV compounds mn >> mp and also Lp ≥ Ln and if nn >> pp (by making n+p
diode), there is a natural tendency of ae to be closer to unity. It is but obvious requirement that most
radiative recombinations should take place from the side of the junction nearest to the surface as the
probability of reabsorptions is lessened. A shallow p-n junction is formed as shown in Fig. 18.35. The
upper surface of the p-material is uncovered so that the radiation available from the device is as high as
possible.
Figure 18.36 Absorption effect of light

Although the internal quantum efficiencies of LED materials can approach 100%, the external efficiency
is much lower. It is due to the fact that number of photons escaping from the semiconductor is not the
same as the number of photons generated internally. Approximately three types of losses exist inside the
LED which reduce the quantity of emitted photons:
∑ Absorption within the material
∑ Critical angle
∑ Fresnel loss
The absorption loss for LED on GaAs substrate is large (Fig. 18.36) as the substrate is opaque to light
and absorb about 85% of the photons emitted at the junction. For LED on GaAs substrate as depicted in
Fig. 18.37, the photons emitted down can be reflected back with only about 25% absorption, and hence
efficiency can be improved.
Figure 18.37 Absorption effect of light

'
When photons pass from a medium with a refractive index of n2 (= 3.66 in GaAs) to another medium
of refractive index n1 (=1 in air), a portion of light is reflected back to the medium surface. This loss of
light is called Fresnel loss. The reflection co-efficient for normal incident rays is expressed as
2
Fn
R=G 2 - n1 IJ (18.8.5)
Hn 2 + n1 K
The third loss is caused by total internal reflections of photons incident on the surface at an angle larger
than the critical angle qC, defined by Snells law as
n1sinq1 = n2 sinq2
sin q1 n
or = 2
sin q 2 n1
where n1 and n2 are refractive indices of the two mediums and q1 and q2 are the angles of incidence and
refraction respectively as depicted in Fig. 18.38. All rays striking with the angles more than or equal to
the critical angle, do not get refracted, rather they get totally reflected as shown in this figure. For
incident angle larger than qC, transmission of light does not take place, i.e. total internal reflection occurs
as indicated in this figure. Hence, for critical angle, previous equation reduces to
n1sinqC = n2 sin90∞ = n2 (18.8.6)
n2
or sinqC = (18.8.7)
n1
or qC = sin -1
FG n IJ
2
(18.8.8)
Hn K
1
For GaAs qC = 16° and for GaP with n = 4.45, qC = 17°
Figure 18.38 Reflection of light
LEDs with different cross sections are shown in Fig. 18.39.

The light originating at recombination centres near the p-n junction get radiated isotropically, whereas
only that which falls within the cone of the critical angle qC will escape. The main reason is that most of
'!
the emitted radiations strike the material interface at larger than the critical angle hence, remain trapped.
Those rays with angles q < qC enter the second medium. For the radiation incident on the boundary at
an angle q < qC, the transmittance T(q) is identical with that obtained at normal incidence, i.e.
2
T(q) = T(0) = 1 -
FG n - n IJ
1 2
(18.8.9)
Hn + n K
1 2
Figure 18.39 Hemispherical, truncated hemispherical and paraboloid cross sections of LEDs
The fraction F of the total generated radiations that is actually transmitted to the second medium is
F=
1 n2FG IJ R|S2 - FG n - n IJ U|V
2
1 2
2
(18.8.10)
4 n1 H K |T H n + n K |W
1 2
There are two obvious ways to increase F. Firstly by ensuring that most of the rays strike the surface
at less than the critical angle. This can be achieved by shaping the semiconductor-air interface into a
hemisphere, as shown in Fig. 18.39. This is very difficult and expensive in most of the situations except
for high power diodes. Secondly and the most commonly used technique is to encapsulate the junction
into a transparent medium of high refractive index. This is usually a plastic material with refractive index
of about 1.5. In Fig. 18.40 the p-material is made into a hemispherical dome. In Fig. 18.40 the p-n
junction is surrounded by plastic encapsulation. Losses at the plane semiconductor-plastic interface are
less than for a corresponding semiconductor-air interface.
The visible LEDs are used as indicator lamps and displays and for optoisolation applications. The
LED lamp contains LED chip and plastic lens which is usually coloured to serve as optical filters and to
enhance the contrast. The plastic lens determines the light emission pattern and the viewing angle of the
device. The LEDs have typical voltage drop of 1.5 V to 2.5 V and currents between 10 mA to 50 mA.
Figure 18.40 Shapes of LED encapsulation Figure 18.41 Lead connection

'"
18.8.1 Using an LED

An LED requires a dc voltage supply and a resistor to make it work. If an LED is connected to a dc
power supply directly without any current limiting resistor it might get permanently damaged because
the internal resistance of the LED is very small and a high current passes through it. In order to connect
the LED, power supply and resistor, we have to identify the two leads (anode and cathode). The easiest
way to do so is to look for the longer lead. The longer lead belongs to the anode. Then connect the
resistor either to the anode side or to the cathode side and the power supply positive terminal to the
anode side of the LED as in Fig. 18.41. The value of resistor may be in between 150 W to 500 W. With
the glowing LEDs, the current starts flowing from the positive leg of the LED to its negative leg. If we
turn the LED other way, it should not light up. No current can flow from the negative leg of the LED to
the positive leg.
18.9 Liquid Crystal Displays (LCDs)

Though LCD is not a semiconductor device yet, it has infused into the semiconductor so much that it
needs explanation. The Liquid Crystal Display (LCD) is a material that normally look like a liquid crystal
but its molecular structure has some properties which are associated with that of the solids. Thus,
LCDs are material having rod-like molecules that are free to twist in the crystal around certain axis. In
the temperature range from 10°C is 50°C, the molecules form an ordered sequence. Since the molecules
have strong dielectric anisotropy, the crystal sequence can be disturbed by a strong electric field. The
molecules have optical anisotropy also so that when light passes through them, the molecules can cause
a change in the polarization of the light. The LCDs are fabricated by placing the crystal in between two
glass plates as shown in Fig. 18.42.
The glass plates have preferential directions (produced either by rubbing the surface or by any other
lithographic technique) so that these directions orient the liquid crystal molecules. The plates are arranged
such that the preferential directions are perpendicular to each other causing 90° twist to the liquid crystal
molecules. The molecules in the space between the front and the rear plate undergo gradual twist of 90°
as they go from rear to the front plate. The plates have one polaroid each attached to them so that these
polaroids are crossed in the absence of the twisted nematic liquid crystal. As the direction of polarization
of light emerging from the cell is in the same direction as the light, the plane polarized light is able to pass
through the front polaroid. This is shown in Fig. 18.42 marked by A.
Due to the positive dielectric anisotropy, the molecules of LC have strong dipole moments along the
long axis of the molecules. If an AC or DC (preferably AC for long life of TN LCD) voltage of a few
volts is applied to the cell, the molecules align themselves along the direction of electric field thus, the
twisted structure is destroyed. As a result the incidence of plane polarized light on the front polaroid falls
without 90° rotation and the light is absorbed by the front polaroid giving rise to dark appearance of the
cell. This is illustrated in Fig. 18.42 marked B. A digit or alphabet on an LCD display may have the
segment appearance shown in Fig. 18.43. The black area is actually the clear conducting surface
connected to the terminal for external control. Two similar masks must be placed on opposite sides of
a sealed thick layer of liquid crystal material. If a digit 2 is to be displayed the terminals a, b, d, e, g would
be energised and those regions would look like frosted while the other areas would appear clear.
905
Figure 18.42 LCD molecule with and without field
Figure 18.43 Eight segment LCD
Questions for Practice 5. What is a thermistor?

6. What is a photo diode?
1. Enumerate uses of LDR.
7. What are the limiting conditions of a Solar
2. What do you understand by dar current of cell? Explain them.
a LDR?
8. How does the voltage drop across LED
3. How many modes of operation a photo diode
compares with that of a signal diode?
has?
4. What precautions are taken for using an
LED?
906
Multiple Choice Questions 8. Rating and control capabilities of an LDR

depend upon the
1. Photo-conductive devices are made of (a) type of light rays imparted on its sur-
(a) highly conductive material face
(b) semiconductor material (b) temperature of the surrounding
(c) radioactive material (c) voltage applied
(d) photo-resistive device (d) amount of semiconductors film de-
2. Light dependent resistor is type of posited on the insulating base.
(a) photo-voltaic device 9. A light dependent resistor behaves like a
(b) photo-emissive device (a) capacitor
(c) radioactive device (b) dielectric medium
(d) photo-resistive device (c) switch
3. In a photo-emissive device the number of (d) battery
electrodes is 10. The light emitting diode (LED) is a
(a) 2 (b) 3 (a) display device
(c) 4 (d) 6 (b) storing device
4. Efficiency of emission of a photo-emissive (c) Zener diode
device can be increased by (d) voltage regulator
(a) cooling the cathode plate 11. Radiation emitted by LED can be seen in
(b) decreasing the distance between the the
anode and the cathode (a) ultraviolet region
(c) decreasing the area of the cathode (b) visible spectrum
plate (c) infrared region
(d) coating the cathode plate with an ac- (d) visible as well as infrared region
tive metal 12. An LED causes emission of light due to
5. Solar cell is a type of (a) emission of electrons
(a) photo-conductive device (b) generation of electromagnetic radia-
(b) photo-emissive device tion
(c) photo-voltaic device (c) conversion of heat energy into light
(d) electromotive device energy
6. Light activated silicon controlled rectifier (d) the photo-voltaic effect
is a type of 13. LEDs that radiate infrared rays are manu-
(a) semiconductor photoelectric switch factured by using
(b) photo-emissive device (a) arsenide phosphide
(c) electromotive device (b) gallium phosphide
(d) radioactive device (c) gallium arsenide
7. Light dependent resistors are prepared (d) gallium arsenide phosphide
from 14. The forward-bias required by an LED for
(a) intrinsic semiconductors emission of light is
(b) highly doped semiconductors (a) 1 V to 2 V (b) 4 V
(c) lightly doped semiconductors (c) 8 V (d) 5 V
(d) insulating materials
907
15. The efficiency of an LED for generating (b) type of phototransistor

light is directly proportional to the (c) light dependent resistor
(a) temperature (d) photodiode with reverse bias voltage
(b) voltage applied 22. Photo-voltaic emf of semiconductor pho-
(c) level of doping used todiode is that voltage at which the result-
(d) current injected ant current flowing through the device be-
16. A photodiode is a type of comes
(a) photo-conductive cell (a) minimum
(b) photo-voltaic cell (b) maximum
(c) semiconductor p-n junction diode (c) zero
(d) light dependent resistor (d) twice the value of the normal
17. In case a reverse biased photodiode is kept 23. Short circuit current starts flowing in a
in dark condition, the current flowing photo-voltaic cell when
through the device corresponds to (a) it is kept in darkness
(a) maximum value of current which can (b) it is kept in presence of luminous flux
flow through the device (c) its terminals are shorted in the absence
(b) value of reverse saturation current of luminous flux
(c) normal value of current (d) its terminals are shorted in the pres-
(d) zero ence of luminous flux
18. The volt-ampere characteristic of a 24. A photo-conductive cell is basically a
photodiode passes through the origin (a) light emitting diode (LED)
when light flux is (b) light dependent resistor (LDR)
(a) maximum (c) photo-diode
(b) minimum (d) photoelectric relay
(c) zero 25. The value of dark-current of a photo-con-
(d) average of maximum and minimum ductive cell is
value (a) negligibly small
19. A phototransistor is connected in a circuit (b) very high
generally in (c) zero
(a) common emitter configuration (d) high
(b) common collector configuration 26. The cadmium sulphide layer of a cadmium
(c) common base configuration sulphide cell purposely has some impuri-
(d) any of the above ties in it to increase the
20. Sensitivity of a phototransistor as com- (a) voltage rating of the cell
pared to any other photosensitive semi- (b) efficiency of the cell
conductor device is (c) ampere-hour rating of the cell
(a) the same 27. The process of emission of light from a
(b) slightly less solid with the excitation provided by an
(c) slightly more electrostatic field is called
(d) much more (a) luminance
21. A photo-voltaic cell is (b) electroluminescence
(a) a photodiode without reverse bias (c) electroemission
voltage (d) none
908
28. The injection process in the LED is 38. The output colour of the GaAsP LED is
(a) minority carrier injection (a) yellow (b) green
(b) majority carrier injection (c) amber (d) red
29. Ge or Si semiconductors do not emit light 39. The breakdown voltage for LED is ap-
because most of the energy is proximately
(a) dissipated in generation of holes (a) 1.6 V (b) 0.72 V
(b) dissipated in generation of electrons (c) 1.12 V (d) 9 V
(c) dissipated in heat 40. The quantity of emitted photon does not
30. The colour of LED depends on depend on
(a) energy involved (a) the LED material
(b) colour used (b) critical angle loss
(c) heat evolved (c) Fresnel loss
31. LEDs are devices with the power in the (d) none
range of 41. When photons pass from one medium to
(a) kilowatt (b) watt another, a portion of light is reflected back
(c) megawatt (d) milliwatt to the medium interface causing
32. A good material for LED should have en- (a) heat
ergy gap in the (b) critical angle loss
(a) ultraviolet range (c) fresnel loss
(b) visible range 42. Best suited spectral response for the hu-
(c) infrared range man eye can be obtained from
33. Direct bandgap LEDs have emission in the (a) germanium (b) selenium
(a) UV range (b) visible range (c) silicon
(c) infrared range 43. For the GaAsP red the wavelength lies in
34. Photon absorption due to the capacity of the range between
LED material causes (a) 600 nm to 700 nm
(a) low quantum efficiency (b) 550 nm to 650 nm
(b) high quantum efficiency (c) 700 nm to 750 nm
(c) no change in efficiency (d) none.
35. The light emitted by the LED is a func- 44. Thermistor is a
tion of the (a) junction device
(a) voltage (b) temperature (b) temperature sensitive device
(c) current (c) current sensitive device
36. If the forward current in the LED doubles, (d) none of these
the radiant output power approximately 45. The photo-conductive compound used in
(a) doubles LDR is
(b) remains the same (a) CdS (b) Ni
(c) become half (c) cobalt oxide (d) GaAsP
37. If the junction temperature of LED is in- 46. The dark resistance of the LDR is of the
creased, the radiant output power order of
(a) decreases (b) increases (a) KW (b) mW
(c) remains same (c) MW (d) W
909
47. The drawback of LDR is that its resistance 51. With increase in the luminous flux, the in-
is dependent on ternal resistance of photo-voltaic cell
(a) current (b) temperature (a) increases (b) decreases
(c) material used (d) none (c) remain the same
48. The variation of output current w.r.t. the 52. Infrared-emitting diodes emit radiant flux
illumination flux in the photodiode is under
(a) linear (b) exponential (a) forward bias (b) reverse bias
(c) circular (d) parabolic (c) no bias
49. In photorelay circuits, the device used as 53. IR-emitters are composed of
actuator is (a) GaAs (b) CdS
(a) photodiode (b) LDR (c) Si (d) Ge
(c) phototransistor (d) thermistor 54. The fill factor for the solar cells is approxi-
50. The variation of short circuit current with mately
luminous flux in photo-voltaic cell is (a) 0.2 (b) 0.1
(a) linear (b) exponential (c) 0.7 (d) 1
(c) non-linear

1. (b) 2. (d) 3. (a) 4. (d) 5. (c) 6. (a)
7. (c) 8. (d) 9. (c) 10. (a) 11. (d) 12. (b)
13. (c) 14. (a) 15. (d) 16. (c) 17. (b) 18. (c)
19. (a) 20. (d) 21. (a) 22. (c) 23. (d) 24. (b)
25. (a) 26. (b) 27. (b) 28. (a) 29. (c) 30. (a)
31. (d) 32. (b) 33. (c) 34. (a) 35. (c) 36. (b)
37. (a) 38. (d) 39. (a) 40. (d) 41. (c) 42. (b)
43. (a) 44. (b) 45. (a) 46. (c) 47. (b) 48. (a)
49. (c) 50. (a) 51. (b) 52. (a) 53. (b) 54. (c)
19
Tuned Amplifier
19.1 Introduction
Audio amplifiers are used in radio receivers, tape recorders, television receivers, etc. The audio amplifier
amplifies the signal falling in the audio range of 20 Hz to 20 kHz. This audio range of frequency can not
be transmitted to distant places as it gets attenuated very fast. This range of frequency can propagate to
small distances and the propagated signals from one station will be similar to those from other stations.
Hence, the signal transmitted from one station will overlap with the signal of the other station and it will
be difficult to extract the desired signal from other similar signals. Thus, we require a circuit that selects
a particular station signal and rejects the signals of all other stations. A frequency much higher than the
frequency range of the audio signal is required to carry the audio signal frequency to distant places. The
carrier frequency falls in the range of Radio Frequency (RF). The carrier frequencies used by different
radio transmitting stations are given in Table 19.1.
Table 19.1 Frequency and wavelength of few Radio stations
Radio stations Frequency wavelength
Lucknow A 747 KHz 401.6 m
Delhi B 1017 kHz 294.9 m
Bombay C 1188 kHz 252.5 m
Chandigarh 1431 kHz 209.6 m
Gorakhpur M W 909 kHz 330.0 m
SW1 3945 kHz (day frequency) 760.5 m
SW2 7250 kHz (evening frequency) 413.8 m
FM 100.1 MHz 2.997 m
Tuned Amplifier
'
The transmitted wave is a modulated signal with RF carrier. The modulated wave has very narrow
band of frequencies f2 f1 centered around the carrier frequency fc. The modulated RF signal reaching
the antenna at any distant place is of the order of few mV. Hence, this weak signal has to be first
amplified before the desired signal is extracted from RF modulated wave. This suggests that a narrow
band amplifier is the requirement under such situation. The narrow band amplifier is the tuned voltage
amplifier. The tuned amplifier does the dual functions of :
∑ Selecting the desired RF modulated signal from any particular transmitting station
∑ Amplifying the weak RF wave reaching the antenna of any radio receiver.
The tuned circuit is a parallel combination of a capacitor and an inductor. It is called anti-resonant
circuit as its behaviour is opposite to the behaviour of the series resonant circuit as indicated in
Fig. 19.1.
The current at resonant frequency in the series resonant circuit is the maximum as the impedance
V
offered at the resonant frequency is only the small resistance of the coil winding resistance, i.e Ir = s .
rs
In contrast to the response of the series resonant circuit, the parallel resonance response indicates
maximum impedance at the anti-resonant frequency that results into minimum current. The sharpness
of the resonant response curve depends on the quality factor of the circuit. Higher the value of the
quality factor, steep is the response of the resonant circuit.
Figure 19.1 Series and parallel resonance circuit and its responses
Here Zs, Is and Zp, Ip stand for the impedances and currents of series and parallel circuits.
The tuned amplifier is a good example of transformer coupled amplifier. The tuned amplifier is a
frequency selective circuit that amplifies the voltage of a particular frequency or a very narrow band of
frequencies. Tuned amplifiers are very widely used in radio and television receiver circuits.
Almost all communication equipments use tuned circuits/tuned amplifiers. We are familiar with tuning
the radio receiver. What we do while tuning is that the carrier frequency wo is varied keeping the
bandwidth wH wL as demonstrated in Fig. 19.2 constant.
In tuning the radio receiver, the dial is set at the carrier frequency of the transmitting station, typically
at 455 kHz for AM and a signal of the same frequency is supplied to its input. The threaded screw type
ferrite material of the Intermediate Frequency Transformer (IFT) is varied slowly and its output voltage
is measured. When the indication of the meter becomes the maximum the IFT is tuned at the frequency
455 kHz as indicated by wo in Fig. 19.2. Here wH and wL are 3 dB frequencies of the tuned circuit having
'
the maximum value of the signal voltage at wo. The IFT alongwith parallel capacitor works as a band-
pass filter. In other words, it develops sufficient amount of voltage across its secondary winding for the
frequency range of wH wL to wH + wL only. The frequencies other than these, do not develop
sufficient amount of voltage and the output will be much below the 3 dB level. Thus, its effect will not
be seen in the output. Hence, frequencies other than 455 kHz are rejected.
Figure 19.2 Response of tuned circuit
wo = carrier frequency of the broadcasting station

wH wL = required bandwidth to receive the signal without significant distortion
We know that low frequency signal cannot be transmitted directly for long distance reception as
between ground station to aircraft or space vehicle, two cities like Delhi and Patna, etc. Its magnitude
gets attenuated fast with the distance and at the same time other low frequency signals also interfere.
Hence, for long distance transmission, the broadband amplifier (such as RC coupled) is not at all
suitable. In such situations only narrow band amplifier is suitable.
The Class C amplifier is a narrow band amplifier. Here, it is important to note that the Class C
amplifier introduces considerable distortion in amplification of signals having large number of frequencies.
Hence, it becomes essential to use Class C amplifier for constant amplitude single frequency signal
called the carrier wo. In broadcasting, the intelligence (modulating signal) and the carrier voltages are
amplified separately. Class AB amplifier amplifies the intelligence voltage where as Class C amplifier
amplifies the carrier voltage.
The tuned amplifier contains invariably a parallel tuned circuit as shown in Fig. 19.3. The winding
resistance is represented by r and is negligible small w.r.t. other impedances.
Figure 19.3 Parallel tuned circuit and its response

Tuned Amplifier
'!
From Fig. 19.3,

vi v v v
IL = @ i = - j i = i – 90° (as r << |XL|) (19.1.1)
r + jX L jw L wL wL
vi vi
IC = = j = jw Cvi = |w C| –90° (19.1.2)
- jX C 1/ wC
I = IL + IC (19.1.3)
where XL and XC are reactances of the inductor and the capacitor respectively.
From Eqns. 19.1.1 and 19.1.2 it is clear that the current in the ideal inductor lags by 90° w.r.t. the
voltage applied whereas that in the capacitor leads by 90°.
1 r - jX L r jX L 1 j
YL = = = - , YC = =
r + jX L r 2 + X L2 r 2 + X L2 r 2 + X L2 0 - jX C X C
r jX j r Ê 1 X ˆ
Y = YL + YC = 2 2
- 2 L 2+ = 2 2
+ jÁ - 2 L 2˜
r + X L r + X L XC r + X L Ë XC r + X L ¯
At resonance frequency (w r) imaginary part of the impedance becomes zero i.e.
1 X 1 L
- 2 L 2 = 0, r2 + wr2 L 2 = wr L =
XC r + XL wrC C
L r2 1 r2
or wr2 = - = - 2
CL2 L2 CL L
1 r2
wr = 2
LC L
1 1 r2 1 1
or, f 0 = 2 @ (for r fi very small ideally zero resistance of the coil) (19.1.4)
2p LC L 2p LC
We know that impedance of parallel tuned circuit is maximum and resistive at tuned frequency.
Further more, higher the value of Q of the circuit, lower the resistive impedance at tuned frequency.
The parallel impedance of inductive and capacitive branches is expressed as
Z L ¥ ZC jw L ¥ (1/ jw C) jX L ¥ jX C
Zp = impedance of parallel tuned circuit = = =
Z L + ZC jw L + (1/ jw C) jX L + jX C
XL ¥ XC X L ¥ XC X ¥ XC
= = = L (19.1.5)
j (X L XC ) jX L jX C ZS
Here, Zp and Zs are impedances of parallel and series tuned circuits respectively.
w L ¥ XC X2
At resonance Zs = r and XL = Xc, Zp = = QX C = L
r r
'"
wL
=Q r = Q2 r (For Q > 10, ZL = jw L) (19.1.6)
r
wL L
Zp = = resistive impedance at resonance frequency
w Cr Cr
w L ¥ 1 / w C L /C
= = (19.1.7)
ZS ZS
fo
Band width of resonant circuit = f2 f1 = (19.1.8)
Q
19.2 Single Tuned Amplifier

One of the simplest band-pass amplifiers is the single tuned amplifier. A common emitter amplifier is
converted to a tuned band-pass amplifier using a single parallel tuned circuit as shown in Figs. 19.4(a).
The tuned amplifiers are also coupled
∑ Capacitively
∑ Inductively
The voltage gain of CE configuration from chapter 8 can be written as
b R2
Av = (R1 fi load of the tank circuit) (19.2.1)
Rln
The tank circuit impedance becomes maximum at anti-resonant frequency that is expressed as
L
Zp(max) = (resistive) (19.2.2)
CR
bL
Av = (19.2.3)
Rin CR
19.3 Input Side Single Tuned Amplifier

The single tuned (band-pass) amplifier may employ BJT, FET or Op. Amp. as the active device. The
bias components have been omitted in Fig. 19.4(b) for simplicity. Following assumptions have been
implemented in Fig. 19.4(c) wherein the series combination of the inductance L and its associated small
loss components r are represented in parallel. Also,
RL << R C (19.3.1)
and rbb¢ = 0 (19.3.2)
Tuned Amplifier
'#
Fig. 19.4(a) Capacitive coupled single tuned amplifier
Figure 19.4(b) Inductively coupled single tuned amplifier
Figure 19.4(c) Simplified circuit of single tuned amplifier
The series circuit of the inductor is changed to parallel circuit as in Fig. 19.4(d).
1 1 r - jwL s r wL s
Ys = = = 2s = 2 s 2 2 j 2
Zs rs + jwL s 2
rs + w L s2
rs + w L s rs + w 2 L 2s
rs wL s wL s
= j ,Q= (19.3.3)
rs2 ( 1 + Q 2 ) rs2 ( 1 + Q 2 ) rs
'$
Figure 19.4 (d) Equivalent circuit of the inductor
As Q2 >> 1, Eqn. 19.3.3 reduces to

1 wL 1 1
Ys = 2
j 2 s2 = j
rs Q rs Q rs (w Ls / rs )Q rs Q
1 1 1 1
= + = + (19.3.4)
w LsQ jrs (w Ls / rs ) w Ls Q jw Ls
The admittance of parallel resistive and inductive circuits can be expressed as
1 1
Yp = + (19.3.5)
rp jw L p
w 2 L 2s
where rp = w LsQ = and, Lp = L S (19.3.6)
rs
The hybrid-p model of Fig. 19.4(b) is drawn as in Fig. 19.4(e) assuming that rm and rce are very large
resistances in comparison to their parallel counter parts.
Figure 19.4(e) Equivalent circuit of single tuned amplifier
Using Miller theorem Cm is reflected as parallel capacitance

CM = (1 + gmRL)Cm (19.3.7)
The circuit of Fig. 19.4(e) is further simplified as Fig. 19.4(f).
Hence, total capacitance across the input terminals is equated as
C = C1 + Cp + (1 + gmRL)Cm (19.3.8)
Tuned Amplifier
'%
Figure 19.4 (f) Equivalent circuit of single tuned amplifier
Now Fig. 19.4(f) is reduced to Fig. 19.4(g).
Figure 19.4 (g) Simplified equivalent circuit
where R = rp| |rp| |rs (19.3.9)

From Fig. 19.4(g) iL = gmvp (19.3.10)
Ï 1 ¸ ii Rii
vp = Ì R jw C ˝ ii = =
Ó jw L ˛ 1 1 1 FG IJ
+ + jw C 1 + jw CR 1 - 2
R jw L w LC H K
Rii Rii
= = (19.3.11)
Ï w Êw2 ˆ w ¸ Ê w wo ˆ
1 + jw o Ì - Á o2 ˜ ˝ CR 1 + jw o C Á - R
ÓÔ w o Ë w ¯ w o ˛Ô Ë w o w ˜¯
1
where w 2o =
LC
iL gm R
Ai = = (19.3.12)
ii Ê w wo ˆ
1 + jw o CR Á -
Ë w o w ˜¯
Now the quality factor of the parallel tuned circuit at resonant frequency wo is derived as
rp * jw L (rp * jw L ) (rp - jw L w 2 L2 rp + jw Lrp2

Zp = = =
rp + jw L rp2 + w 2 L2 rp2 + w 2 L2
w Lrp2 rp
Q= = (19.3.13)
w 2 L2 rp wL
'&
rp (1/ jw C) rp (1 - jw Crp )
Similarly using R and C, Zp = =
rp + 1/ jw C 1 + w 2 C 2 rp2
Qp = w Crp (19.3.14)
The analysis and design of single parallel tuned amplifier is based on the assumption that the value of
Q and Qo are much larger than 5. This condition is known as high Q approximation. Hence, Eqn.
19.3.12 is now modified as
gm R
Ai = - (19.3.15)
Ê w wo ˆ
1 + jQo Á -
Ë w o w ˜¯
It is evident from Eqn. 19.3.15 that the current gain is the function of frequency. It is also clear from
Fig. 19.4(h) that the current gain Ai becomes maximum at w = wo and is
Ai(max) = gmRL (19.3.16)
Its bandwidth can be obtained by equating the magnitude of Eqn. 19.3.15 at 3 dB frequencies, i.e.
gm R
Ai = - (19.3.17)
2
Thus, equating Eqns. 19.3.15 and 19.3.17 yields
gm R gm R
Ai = - = - 2
(19.3.18)
2 Ê w wo ˆ
2
1+ Q Á -
Ë w o w ˜¯
o
wo
w2 - w - w o2 = 0 (19.3.19)
Q
2
w=
wo
±
1 FG w IJ
o
+ 4 w o2 @
wo
± w o for large Qo (19.3.20)
2 Qo 2 HQ Ko 2 Qo
wo wo
wH = w o + and wL = w o - (19.3.21)
2 Qo 2 Qo
wo
The bandwidth wH wL = (19.3.22)
Qo
fo 1
fH fL = = (19.3.23)
Qo 2 pCR
gm R gm
The gain bandwidth product = GBW = |Ai| ( fH fL ) = = (19.3.24)
2 pCR 2 pC
Tuned Amplifier
''
Figure 19.4(h) Response of single tuned amplifier
19.4 Impedance Transformation

The practical values of L and C for parallel resonant circuit elements can be achieved using a suitable
impedance transformation network. The choice of a particular impedance, out of many types, depends
upon the frequency range and impedance transformation levels. One of such types of attractive network
for the tuned amplifier case is the autotransformer as indicated in Fig. 19.5. The coils are wound on a
ferrite core that results in the coefficient of coupling very close to unity. The relationship between
voltage and currents of an ideal transformer can be obtained from Fig. 19.5 as
-i2 v1
= = n >1 (19.4.1)
i1 v2
Figure 19.5 Autotransformation of impedance
The ideal model of the autotransformer neglecting the losses depicted in Fig. 19.6(a) has L as the
total magnetizing inductance on the primary side with its turn ratio of n. It should be remembered that in
1
the case of step-down transformer, the voltage is reduced by but the current is increased by n times.
n
This is the reason why one considers the power gain in tuned amplifiers. Often double tapped or
combination of tapped primary is used in tuned amplifiers as illustrated in Figs. 19.6(b) and (c).
'
Figure 19.6 (a) Equivalent model of ideal transformer
Fig. 19.6 (b) Double tapped tansformer Figure 19.6 (c) Tapped transformer
19.5 Output Side Single Tuned Amplifier

The single stage tuned amplifier is seldom used. The double tuned amplifiers are commonly used in IF
(Intermediate Frequency) stage in both AM and FM radio receivers. This is because this type of amplifiers
are able to provide substantially constant amplification over a band of frequencies and the gain falls very
sharply outside this band than that in the case of single tuned amplifiers. The frequencies outside that
band are rejected very efficiently.
19.5.1 Double Tuned Circuit

A double tuned circuit contains two tuned circuits
∑ L 1, C1, and
∑ L 2, C2
as shown in Fig. 19.7. The L1, C1 and L2, C2 form the primary and secondary side tuned circuits. The
tuned circuit offers very large impedance of the signal frequency equal to the tuned frequency.
Consequently, the voltage across the primary side of the tuned circuit L1C1 becomes large. This large
voltage appearing in the primary side of the tuned circuit is coupled to the secondary side of the tuned
circuit through mutual inductance.
19.5.2 Frequency Response

The frequency response of the double tuned circuit depends on the degree of coupling. In other words,
it depends upon the amount of mutual inductance between the two tuned circuits. The load resistance
RL is coupled to the primary side through the coupling between L1 and L2 (as a resistance in series with
L 1.
Tuned Amplifier
'
Figure 19.7 Double tuned circuit and its response
If the coils are spaced far apart, all the flux from the primary side of the tuned circuit may not link the
secondary side of the tuned circuit. This type of coupling is called loose coupling. In such circumstances
the reflected load resistance from the secondary tuned circuit to the primary tuned circuit is not very
large. Hence, the Q of the tank circuit is large and the response is sharp as shown in Fig. 19.7. If the two
coils are kept in the close vicinity, all the flux from the primary side of the tuned circuit links the
secondary tuned circuit. This type of coupling is called the tight coupling. Under such circumstances
the reflected load resistance from secondary side of the double tuned amplifier to the primary side
becomes very large. The Q of the circuit becomes very low and the response is not very sharp, rather
it is flat as shown in Fig. 19.7.
Hence, for the sake of clarity of discussion in double tuned amplifier, the analysis of output side
single tuned amplifier is taken up here as shown in Fig. 19.7. For the inductive coupling, the Miller
approach can lead to erroneous results. In other words, if the tuned circuit is at the output, as shown in
Fig. 19.8, the unilateral model cannot be used as the output impedance of the transistor is very high and
can be inductive or capacitive near the resonant frequency. It is likely that the circuit may start oscillating.
In majority of the cases, the treatment is done for a narrow band pass amplifier i.e.
w3dB £ 0.1wo (19.5.1)
Figure 19.8 Output side tune amplifier and its equivalent circuit
This leads to considerable simplification in the analysis and design of the tuned amplifier. Since, all
elements of y-equivalent circuit of BJT are in parallel, the same model of BJT near the tuned frequency
is drawn in Fig. 19.8. The YL in Fig. 19.8 is
1
YL = G + jwC + (19.5.2)
jw L
Taylor series at high frequencies provides comprehensive results of variation in capacitive parameter
with variation in frequency. It is expressed as
'
f ¢ (w o ) f ¢¢ (w o )
f (w) = f (wo) + (w - w o ) + (w - w o ) 2 +º (19.5.3)
1 2
The y-parameters are represented by Taylor series expansion about wo such that
Yie = gie + jwoCie + j(w wo)C¢ie (19.5.4)
d { I maginary term of ( Yie )}
where C¢ie = (19.5.5)
dw w =w o
The capacitance C¢ie represents the variation in the input admittance Yie as a function of frequency.
Some of the parameters have little or no variation w.r.t. frequency and they are represented as constants,
but others particularly Yie and Yoe are strongly dependent upon frequency. Thus, Eqn. 19.5.4 is the first
order approximation in the variation of the Cie. In similar manner other parameters are also written as
Yfe = gfe + jwoCfe + j(w wo)Cfe (19.5.6)
Yre = gre + jwoCre + j(w wo)C¢re (19.5.7)
Yoe = goe + jwoCoe + j (w wo)C¢oe (19.5.8)
Writing node equation at output node of Fig. 19.8 node results as
Yfev1 + (Yoe + YL )v2 = 0 (19.5.9)
v2 - Y fe - Y fe
Voltage gain = Av = = = (19.5.10)
v1 Yoe + Y L 1
Y oe + G + jwC +
jwL
Substituting expanded value of Yoe from Eqn. 19.5.8 in Eqn. 19.5.10 yields
-Yfe
Av = (19.5.11)
1
goe + G + jw (C + Coe¢ ) + jw o (Coe - Coe¢ ) +
jw L
It is clear from Eqn. 19.5.11 that Yfe (in the numerator) does not contain any inductive component so
it will not participate in the resonance. Hence, the expanded form of Yfe has not been substituted in
Eqn. 19.5.11.
If we assume that Coe = C¢oe (19.5.12)
1
jwo(C + C¢oe ) = (19.5.13)
jw L
then the imaginary part in the denominator of Eqn. 19.5.11 becomes zero at w = wo. Here, it is very
1
important to note that the resonant frequency now is π , but the resonant frequency of the tuned
LC
circuit external to the transistor includes the transistor capacitance also.
1
w 2o = (19.5.14)
( C + C oe ) L
Tuned Amplifier
' !
Now, at w = wo Eqn. 19.5.11 reduces to

Y fe
|Av(jw )| = (19.5.15)
g oe + G
In order to find out the bandwidth, let us assume that w¢ = (w wo) << wo. Then Eqn.(19.5.11) can
be written with C = C¢oe as
- Y fe
Av = (19.5.16)
1
goe + G + j ( w ¢ + w o )( C + C oe
¢ ) +
j (w ¢ + w o ) L
The inductive part in the denominator of Eqn. 19.5.16 can be approximated using Binomial expansion
as
-1
1
=
1
1+
w¢ FG IJ =
1
1-
FG
w¢ IJ (19.5.17)
j (w ¢ + w o ) L jw o L wo H K jw o L H
wo K
1
Substituting for from Eqn. 19.5.13 in Eqn. 19.5.17 yields
woL
1 Ê w¢ˆ
= jw o (C + C ¢ oe ) Á 1 - ˜ = jw ¢ (C + C ¢ oe ) - jw o (C + C ¢ oe ) (19.5.18)
j (w ¢ + w o ) L Ë w o¯
The denominator of Eqn. 19.5.16 becomes as

goe + G + jw¢(C + C¢oe + C + C¢oe) + jwo(C + C¢oe C C¢oe)
= goe + G + jw ¢2 (C + C¢oe) = goe + G + j2w ¢(C + C¢oe)
-Y fe
Now, the gain of the amplifier = Av = (19.5.19)
goe + G + j 2w ¢(C + C ¢oe )
The 3 dB point in Eqn. 19.5.19 exists if the square of the imaginary part is equal to the square of the
real part of the denominator, i.e.
4 w¢2 (C + C¢oe)2 = (goe + G)2 (19.5.20)
2
2 w¢ (C + C¢oe) = ± (goe + G) (19.5.21)
goe + G
w¢ = w wo = ±
2(C + C ¢oe )
goe + G g oe + G
w2 = wo + , w1 = w o - (19.5.22)
2(C + C ¢oe ) 2(C + C ¢oe )
Hence, bandwidth of single stage tuned amplifier is
2( goe + G ) G
w2 w1 = = A (19.5.23)
2(C + C ¢oe ) CA
' "
where goe + G = GA, CA = C + C¢oe (19.5.24)

Now, voltage gain is expressed as
- Y fe - Yfe -K
Av = = = (19.5.25)
( G A + jw ¢ C A G A {1 + jw ¢ (C A / G A )} 1 + jw ¢ C A / G A
Y fe
where K= - (19.5.27)
GA
19.6 Multistage Tuned Amplifier

It is desirable to cascade tuned amplifiers in many practical situations because of the insufficient gain of
the single stage. It is very important to note that the characteristics of single stage tuned amplifier are
quite different from that of the multistage tuned amplifier. If n identical stages of tuned amplifiers are
cascaded together, then the over all voltage gain is expressed as
A(n stages) = Avn (19.6.1)
n
Avn = ( - 1 ) n
FG K 1 IJ (19.6.2)
H 1 + jw ¢ C A /GA K
The magnitude of the gain expressed in Eqn. 19.6.2 is
( K1 ) n
n n
( Av ) = ( -1 ) (19.6.3)
{1 + jw ¢ ( C A / G A )} n / 2
This magnitude at 3 dB points is expressed as
( K1 ) n
n
( Av ) = (19.6.4)
2
Hence, equating the magnitudes of Eqns. 19.6.3 and 19.6.4 yields
2
FG w ¢ C IJA
= 21/n 1 (19.6.5)
H G K A
GA
w¢ = w w0 = ± 2 1/ n - 1 (19.6.6)
CA
Thus, the bandwidth of n-stage identically tuned amplifier is
GA GA
w2 = w0 + 2 1/ n - 1 , w1 = w o - 2 1/ n - 1
CA CA
2GA
w2 w1 = 2 1/ n - 1 (19.6.7)
CA
Tuned Amplifier
' #
From Eqn. 19.6.7 it is clear that the overall bandwidth of cascaded stages of synchronously tuned
amplifier is reduced.
19.7 Integrated Circuit Tuned Amplifier

An simplified circuit of the integrated circuit tuned amplifier is shown in Fig. 19.9. The input signal is
applied to the base of transistor T1 through a tuned input transformer. The load resistor RL is connected
across the secondary of the output tuned transformer (connected to the collector of transistor T3).
Transistor T3 and T2 form cascode circuit providing the input impedance of CE amplifier and output
impedance of the CC amplifier configurations. The reverse voltage gain of the cascode device is given
by hr = hrehrb @ 107. This extremely low value of hr = 107 reduces internal reverse voltage feedback of
the cascode device that further reduces the chance of oscillations resulting into good stability of operation
of the amplifier.
The VAGC is applied to the base of transistor T2 to automatically control the gain. The VAGC should be
at least 119mV higher than the voltage VR to keep transistor T3 cut-off. As transistor T3 is cut-off and
entire current of T1 flows through T2, the transconductance of T3 falls to zero (0) resulting in the voltage
gain Av = vo /vi = 0. If the VAGC is 120mV lower than VR, transistor T2 is cut-off and all the collector
current of T1 flows through the transistor T3 increasing its transconductance sufficiently that results
into maximum value of the voltage gain.
Figure 19.9 Integrated circuit of tuned amplifier (Motorola Semiconductor Inc.)
A special feature of this circuit is its voltage gain (Av) control by the voltage VAGC without detuning
the input circuit. Also the VAGC causes a change in the current between T3 and T2 without affecting the
current flow through T1. Thus, the input impedance of transistor T1 remains constant and the input
926
circuit is not detuned. The voltage V and resistance R establish a current through the diode D1. As both,
diode D1 and transistor T1 are on the same silicon chip and close to each other, with VDI = VBEI, the
collector current of T1 is within ±5% of the diode current ID1.
1. Obtain the value of L in the circuit of the single tuned amplifier of Fig. 19.10(a). The circuit
resonates at 10 MHz. Obtain the bandwidth and the current gain of the amplifier for f T =
500 MHz.
Figure 19.10 (a)
Figure 19.10 (b) Equivalent circuit
Solution: 1
= = 0.123 mH
h fe 100 4p ¥ 10 ¥ 234 ¥ 10-12
2 12
gm = = = 0.1S,
rp 1000 vp = 500ii and iL = 0.1vp
gm 0.1 iL
Cp = = = 32 pF = 500 ¥ 0.1 = 50
wT 2p ¥ 500 ¥ 106 ii
fo 1
CM = (1 + 0.1 ¥ 1 K)2 pF = 202 pF, fH fL = =
Qo 2 p RC
C = CM + Cp = 234 pF
1 1012
L= = = 1.38 ¥ 106 Hz
4p 2 f 2 C 2p ¥ 234 ¥ 500
Tuned Amplifier
927
2. The tuned circuit shown in Fig. 19.11(a) FG - v IJ FG v IJ

L p
resonates at 10 MHz with 3 dB bandwidth Avm =
n2
H v KH v K
p i
of 1 MHz. Obtain the turn ratio at reso-
n1 Ê n ˆ 1 Ê 1 K ¥ 9( n1 / n2 ) 2 K ˆ
= - 5Á 2 ˜
nant frequency and the maximum voltage. Ë n1 ¯ 9 K ÁË 1 K + 9(n1 / n2 ) 2 K ˜¯
n2
Also obtain the turn ratio to achieve the n1 / n2
n1 = -5
required bandwidth. Calculate the value of L. 1 + 9(n1 / n2 ) 2
Solution: hfe = 50, hie = 1 K, Cp = 10 pF,
CM = gmRLCm = 0.05 ¥ 100 ¥ 1 pF = 5 pF cm = 1pF, RL = 0.1 K, C = 10 pF
h fe
gm = = 0.055
hie
Figure 19.11(a)
∂A vm 1
=
This would be maximum at ÏÔ 2
b
∂ n1 / n 2 g Ê n ˆ ¸Ô
2p Ì1 K 9 K Á 1 ˜ ˝
ÔÓ Ë n2 ¯ Ô
{1 + 9( n1 / n2 ) 2} ˛
ÏÔ 2¸
- n1 / n2 ¥ 18( n1 / n2 ) -12 -12 Ê n ˆ Ô
= -5 2
=0 Ì15 ¥ 10 + 10 ¥ 10 ÁË n ˜¯ ˝
È1 + 9( n1 / n2 ) 2 ˘ ÓÔ 1 ˛Ô
Î ˚
n1 1
FG n IJ 2
1 n1 1 Substituting the value of = yields
1
= , = n2 3
Hn K
2 9 n2 3 2
fH fL = 106
F n IJ
15 + 10 G =
1000
Hn K 1 p
928
FG n IJ 2 Solution:
n
= 30.3, = 5.5 hfe = 100, rp = 100 W, fT = 100 MHz,
Hn K
1 n1
2 Cb¢ c = 1 pF
Ê n1 ˆ 1
ÁË n ˜¯ L = h fe 100 gm
4p 2 ¥ 1014 gm = = = 1S, Cp =
(15 + 10 ¥ 30.3)10 -12 rp 100 wT
1
10 -2 = = 1590 pF = 1600 pF
= = 7.966 ¥ 107 2p ¥ 100 ¥ 106
12554 .14
1
2 At 10 ¥ 106 Hz,
F n IJ
L=G 7.966 ¥ 107 = 24.14 mH w Cp
Hn K 1
=
1
= 9.95 W
3. Obtain the value of C1 such that the circuit 2p ¥ 10 ¥ 1600 ¥ 10 -12
7
of Fig. 19.12(a) resonate at 10 MHz. Cal-

rp assumed to be open w.r.t. the reactance
culate the voltage gain and 3 dB bandwidth.
of Cp.
Figure 19.12(a) Series tuned amp.
1
C1 + 1600 = 2 14 -6
= 0.2533 ¥ 108, C1 = 2533 1600 = 933 pF
4p ¥ 10 ¥ 0.1 ¥ 10

Tuned Amplifier
929
1 100vi
Hence, BW = |Avm| =
2 p RC 20 ¥ 2p ¥ 10 7 ¥ 16 ¥10 -10
1
= = 3.14 MHz vi ¥ 104
2p ¥ 20 ¥ 2533 ¥ 10 -12 = = 49.
4p ¥ 16
|Avm| =
vL
=
FG v IJ FG v IJ ,
L p 4. Calculate the transfer function vi/ii for the
vi Hv KH v K
p i two stage synchronously tuned amplifier
vL = gmRLvp = 100vp resonated at 100 kHz with its bandwidth 2
kHz shown in Fig. 19.13(a). Obtain C1,
=
FG v IJ 1
i
=
vi C2, L1, and L2 also. Given hfe = 100, rp =
H 20 K jw C p 20 ¥ jw ¥ 1600 ¥ 10 -12 1 K, rbb¢ = 0, Cb¢c = 2 pF, fT = 105 MHz.
Figure 19.13(a) Double tuned Amplifier

930
Solution: The value of L = 0.5 mH and transistors

gm parameters at 100 MHz are
0.1
Cp = = = 16pF, C = Cp + gm = gfe = 30 mS, Cfe = 70 pF, C¢fe = 0,
wT 2p ¥ 1011
CM goe = 0.4 mS, Coe = 2 pF, C¢oe= 2 pF
CM1 = gm1RLC¢b¢c = 0.1 ¥ 1000 ¥ 2 pF gie = 4 mS, Cie = 8 pF, C¢ie= 2 pF,
= 200 pF
gre = 0.02 mS, Cre= 1.4 pF,
CM2 = gm2RLC¢b¢c = 0.1 ¥ 100 ¥ 2 pF
= 20 pF Cre = 0
1 Solution:
|ZC| =
w o ( Cp + C M ) 1 1
Coe + C¢oe = =
1 2
w L
o 1016 ¥ 0.5 ¥ 10-6
= 5
2p ¥ 10 ¥ (20 + 16) pF
10-10
= = 200 pF
107 0.5
= = 44.2 KW
36 ¥ 2p C = 200 Coe = 200 2 = 198 pF
rp = 1K << |ZC| hence kept open circuited. g oe + G
wH wL = = 20 ¥ 106
Bandwidth of two-stage synchronously C oe + C oe
¢
C+
0 . 643 2
tuned amplifier =
2 pRC 2
0.4 ¥ 10-3 + G
=
0.643 200 ¥ 10 -12
C2 =
2p ¥ 2 ¥ 103 ¥ 103
G + 0.4 ¥ 103 = 4 ¥ 103,
= 0.51 ¥ 106 = 0.51 mF, 1000
R= = 277.8 W
1 3. 6
L2 =
4p ¥ 10 ¥ 0.51 ¥ 10 -6
2 10
- y fe
Av =
= 49.5 mH g oe + G
If R1 = 10 K >> 1 K, C1 = C2, and
- 30 ¥ 10 -3 + j108 ¥ 70 ¥ 10 -12
L1 = L2, then =
0.4 ¥ 10-3 + 3.6 ¥ 10 -3
zLi =
vL
=
F v IFv IFv I
L p2 p1
ii GH v JK GH v JK GH i JK
p2 p1 i
= 7.5 + j1.75
6. A parallel RLC circuit has a resonant fre-
= (0.1 ¥ 100)(0.1 ¥ 1000)1000 = 106 quency fo = 106, Q = 100. Find out the
5. Obtain the value of R, C, and Av(wo) of the frequency at which its impedance be-
tuned amplifier with tune frequency of comes 0.707Zmax.
100 Mrad/s and a bandwidth of 20 Mrad/s.
Tuned Amplifier
931
Solution: 50 ¥ 400
L= = 0.2 H
Band width of resonant circuit = f2 f1 105
fo 106 1 1
= = = 104 Hz CL = 10
,C= 10
= 500 pF
Q 100 10 10 ¥ 0.2
Hence, frequency for 0.707 Zmax
= 106 ± 0.5 ¥ 104
= 106 Hz
7. An RLC tuned circuit has Zmax = 70 KW
at f = 100 kHz, and Q = 100. Obtain the
frequency at which the impedance
becomes 50 KW. Figure 19.14
Solution: 10. Obtain resonant frequency for the tank cir-
fo = 100 kHz, Zmax (at resonance) cuit shown in Fig. 19.15. Also calculate
the current flowing through the inductive
fo 105 and capacitive branch of the tank circuit.
= 70 KW, f2 f1 = = = 103 Hz,
Q 100 How much is the line current at resonant
The impedance at 3 dB down from frequency?
maximum value = 0.707 ¥ 70 K Solution:
= 49.49 KW @ 50 KW 1
fo =
Hence, the frequency at which the 2p LC
impedance becomes 50 KW
1
= 105 ± 0.5 ¥ 103. =
-6
8. A constant current signal across a parallel 2p 100 ¥ 10 ¥ 100 ¥ 10-12
RLC circuit gives an output of 1.5V at
107
signal frequencies 3.9 kHz and 4.1 kHz. = = 1.59 MHz
Fin out the voltage at 4 kHz frequency. 2p
Solution: XL = wL = 2pfoL
Vm = 2p ¥ 1.59 ¥ 106 ¥ 100 ¥ 106 = 999 W
= 1.5 V or, Vm = 2 ¥ 15
. = 2.1 V
2
9. The resonant circuit shown in Fig. 19.14
has wo = 105, Q = 50, R = 400 W. Obtain
the value of capacitance.
Solution:
1 wL
w= , Q = 50 =
LC R Figure 19.15
932
1 1
XC = =
wC 2p f o C
1
= = 1000 W
. ¥ 106 ¥ 100 ¥ 10-12
2p ¥ 159
L
Zp (at resonance) = Figure 19.16
CR
100 ¥ 10-6 2p ¥ 1.3 ¥ 106 ¥ 150 ¥ 10 -6
= = 105 W Q= = 122.5
100 ¥ 10-12 ¥ 10 10
As resistance in the inductive reactance is f 1.3 ¥ 106
f2 f1 = o = = 10.6 kHz
= 10 W that is much smaller than the in- Q 122.5
ductive reactance. Hence, in calculating 12. A tank circuit has a gang capacitor with
the magnitude of current through induc- minimum and maximum values of 40pF
tive branch, resistance is neglected. and 400 pF respectively. The highest fre-
Hence, quency to be tuned is 2 MHz. Calculate the
V 100 value of inductor required. What is the
IL = = = 0.1 A and
XL 999 minimum value of tuned frequency of the
100 tank circuit? What is the resistance of the
V
IC = = = 0.1 A, coil if the bandwidth of the amplifier is 10
XC 1000 kHz Also calculate the maximum gain of
100 the amplifier with b = 100 for the dynamic
Line current = 5 = 103 A
10 input resistance of the amplifier to be
11. Obtain the impedance of the tank circuit 1 KW.
shown in Fig. 19.16. Also calculate Q and Solution:
bandwidth of the resonant circuit.
1 0.159
Solution: fr(max) = =
2p LC 40 ¥ 10 -12 L
1
fo = = 2 ¥ 106,
2p LC
0159
.
1 40 ¥ 10-12 L =
= 2 ¥ 106
2p 150 ¥ 10 -6 ¥ 100 ¥ 10-12 = 0.0795 ¥ 106 = 7.95 ¥ 108
7
10 63.2 ¥ 10 -16
= = 1.3 MHz L=
2p 15
. 40 ¥ 10 -12
L = 1.58 ¥ 104 = 158 mH
Zp (at resonant) =
CR
1 0159
.
150 ¥ 10-6 fr(min) = =
= = 150 ¥ 103 W 2p LC 400 ¥ 10 -12 L
100 ¥ 10-12 ¥ 10
Tuned Amplifier
933
0159
. bL
= Av(max) = -
400 ¥ 10 -12
¥ 158 ¥ 10 -6 CRrin
100 ¥ 16 ¥ 10 -3
0159
. ¥ 109 0159
. ¥ 109 =- = 1600
= = . ¥ 10 -6 ¥ 10 ¥ 103
01
400 ¥ 158 2514
.
= 20 log 1600 = 64 dB
= 6.32 ¥ 105 = 0.632 MHz.
wL 2p ¥ 3.98 ¥ 103 ¥ 16 ¥ 10-3
f 2 ¥ 106 Q= =
f2 f1 = 10 kHz = o = , R 10
Q Q
= 40
wL 3.98 ¥ 103
Q = 200, R = f2 f1 = Bandwidth =
Q 40
2p ¥ 2 ¥ 106 ¥ 158 ¥ 10-6 = 99.5 Hz
= = 9.9 W @ 10 W 14. A tank circuit has L = 1.6mH, C = 400 pF,
200
and R = 10 W. Calculate (a) the resonant
bL frequency, (b) impedance of the circuit at
Av(max) = -
CRrin resonance, (c) Q of the circuit, (d) band-
width and line current at resonance when
100 ¥ 185 ¥ 10 6
= - 1V is applied to the tank circuit.
40 ¥ 10 12 ¥ 10 ¥ 10 3
Solution:
100 ¥ 185 ¥ 10 1
=- = 46250 fr =
4 1 R2
= 20 log 46250 = 93.3 dB 2p - 2
LC L
13. The load of a tuned amplifier is a tank cir-
cuit having L = 16 mH, C = 0.1 mF, and 1 100
= 0159
. -3 -12
-
Rcoil = 10 W. Calculate (a) maximum gain 1.6 ¥ 10 ¥ 400 ¥ 10 2.56 ¥ 10 -6
of the amplifier and the frequency at which
it becomes maximum, (b) Q of the coil, 1013 108
= 0.159 -
and (c) bandwidth of the amplifier. As- 6.4 2.56
sume that the dynamic input resistance of
the amplifier is 1 KW and current amplifi- 1013
= 0159
. = 0159
. . ¥ 1012
156
cation factor of the BJT is 100. 6.4
Solution: = 0.159 ¥ 1.25 ¥ 106 = 0.198 MHz
1 0159
. w r L 2p f r L
fr = = Q= =
2p LC 16 ¥ 10 -3
¥ 01
. ¥ 10 -6
R R
5
0159
. ¥ 10 2p ¥ 0198
. ¥ 106 ¥ 1.6 ¥ 10 -3
= =
16 10
2
0.159 ¥ 105 = 1.99 ¥ 10 = 199
= = 0.0398 ¥ 105 = 3.98 kHz
4
934
L 1.6 ¥ 10-3 1.6 ¥ 106 eters of the JFET as rd = 60 KW, gm = 3

Zp = = = mS, Cds = 10 pF and external components
CR 400 ¥ 10-12 ¥ 10 4
connected to the amplifier are L = 10 mH
= 0.4 MW = 400 KW in parallel with R = 80 KW, RD = 30 KW,
and C = 90 pF. Determine the resonant fre-
15. A JFET amplifier of Fig. 19.17 has a tank quency, bandwidth and voltage gain of the
circuit as the load with the internal param- amplifier.
Fig. 19.17
Solution: Bandwidth of the amplifier = f2 f1

60 ¥ 30 ¥ 80 fo 159 kHz
rd | |RD | |R = = = = 99.4 kHz
60 ¥ 30 + 30 ¥ 80 + 60 ¥ 80 QCKT 1.6
60 ¥ 30 ¥ 80 16. A tank circuit is connected to non-invert-
= K ing terminal of the op-amp as shown in
1800 + 2400 + 4800
Fig. 19.18 has non-inverting gain = 12.
60 ¥ 30 ¥ 80 K Determine the resonant frequency and
= = 16 KW
9000 bandwidth of the amplifier. If the input is a
current source Is, obtain the output voltage
1 1
wo = = and the transfer function between output
LC 10 ¥ 10 -3
¥ 100 ¥ 10-12 voltage and the source current.
107 Solution:
= = 1 Mrad/s,
100 1 1
wo = =
106 LC 5 ¥ 10 -3 ¥ 1250 ¥ 10-12
fo = = 159 kHz
2p
Voltage gain = gmReq = 3 ¥ 16 = 48 107 107
= = = 400 Krad/s
625 25
rp
Qckt = 400 K
woL fo = = 63.7 kHz
2p
16 ¥ 103 16 Qcoil = woL/r = 400 ¥ 103 ¥ 5 ¥ 103/80
= 6 -3
= = 1.6
10 ¥ 10 ¥ 10 10
Tuned Amplifier
935
Fig. 19.18
= 200/8 = 25 fo
Bandwidth = f2 f1 =
Rp = Q2r = 625 ¥ 80 = 50 KW, QCKT
Reffect = 50 K| |50 K = 25 KW 63.7 kHz
= = 5.12 kHz
Quality factor of the circuit = QCKT 12.5
Reffect 25 K Input voltage at resonance = isReffect,
= = Output voltage = vo = 12vi
wo L 400 K ¥ 5 ¥ 10-3
= 12 ¥ is ¥ Reffect = 12 ¥ 25Kis
25000
= = 12.5 vo
2000 = 300 KW
is
Multiple Choice Questions 4. The overall voltage gain of n-stage tuned

amplifier is expressed as
1. BW of synchronously tuned amplifier is (a) (Av)n (b) nAv
(c) (Av)n
(a) e 2 1/ n - 1 w o / 2 p Q
j 5. If cascaded stage amplifier has the same
(b) ( 2 1/ n - 1 ) w o / 2 p Q center frequency as the individual stages,
it is called
(c) ( 2 1/ n - 1 ) f o / Q (a) synchronously tuned
(d) e 2 1/ n - 1 f o / Q
j (b) staggered tuned
6. The overall bandwidth of synchronously
2. BW of staggered tuned amplifier is tuned amplifier is
(a) w o / 2p Q o (a) increased (b) decreased
(b) f o / 2Q o 7. The impedance offered at resonant fre-
quency in series resonant circuit is ideally
(c) 2p f o Q o (a) zero (b) infinite
3. Staggered tuned amplifier provides an op- (c) equal to its resistance
portunity for stabilizing a more (d) inverse of its resistance
(a) desired band-pass characteristic 8. The impedance offered at resonant fre-
(b) undesirable band-pass characteristic quency in parallel resonant circuit is
936
(a) low (b) high 15. The gain of the amplifier is

(c) equal to its resistance (a) independent of Q
(d) inverse of its resistance (b) dependent on Q
9. The tuned amplifier is operated as 16. The IF(Intermediate Frequency) stage of a
(a) Class AB (b) Class B radio receiver contains
(c) Class C (d) Class A (a) tuned amplifier
10. The Q of the series resonant circuit is ex- (b) DC amplifier
pressed as (c) RC coupled amplifier
(a) wL/R (b) wLR 17. The bandwidth of the double tuned ampli-
(c) R/wL (d) 1/wLR fier is adjusted by varying
(a) inductance
11. The Q of the parallel resonant circuit is
(b) coefficient of coupling
expressed as
(c) emitter resistance
(a) w CR (b) 1/ w CR
18. The bandwidth of a tuned circuit is
(c) w C/R (d) R/w C
(a) fo /Q (b) f oQ
12. Tuned amplifier amplifies voltage of
(c) Q/f o (d) (f2 f1)/Q
(a) all low frequencies
19. The maximum gain in double tuned voltage
(b) all high frequencies
amplifier is possible through
(c) only one particular frequency
(a) tapping of inductor of the tank circuit
(d) very wide band of frequency
(b) tapping of the capacitor of the tank
13. The amplifier used in the PA system is
circuit
(a) broad band type
(c) both
(b) very narrow band type
20. In cascaded tuned amplifier, the imped-
(c) audio amplifier
ance transformation is achieved through
14. The bandwidth of a tuned amplifier de-
(a) tapping of inductor of the tank circuit
creases for
(b) tapping of the capacitor of the tank
(a) increasing value of Q
circuit
(b) decreasing value of Q
(c) tapping both of these
1. (a) 2. (a) 3. (a) 4. (a) 5. (a) 6. (b)
7. (a) 8. (b) 9. (c) 10. (a) 11. (a) 12. (c)
13. (c) 14. (a) 15. (b) 16. (a) 17. (b) 18. (a)
19. (a) 20. (c)
Bibliography
1. G.A. Campbell, Physical theory of the wave filters, Bell Syst. Tech. J., Vol.1, No.2,. Nov.
1922.
2. O.J. Zobell, Theory and design of wave filter, Ibid, Vol.1, No. 1, Jan. 1923.
3. H.H. Scott, A new type of selective circuit and some applications, Proc. IRE, Vol. 26(2),
pp.226-235, 1938.
4. J.C. Linvill, Transistor negative-Impedance convertors, Proc. IRE, Vol.41, pp.725-729, 1953.
5. R.P. Sallen and E.L. Key, A practical method of designing RC active filters, IRE Trans, Vol.
CT-2, pp.74-85, Mar. 1955.
6. S. K. Mitra, Analysis and synthesis of linear active networks, Wiley-Interscience, New York,
1969.
7. A.S. Sedra, A survey of recent trend in active filters design, VII Int. comm. conf. on dig. tech,
Montreal, June. 1971.
8. A.S. Sedra, Generation and classification of single amplifier filters, Int. J.Circ. and Theory
Appl., Vol.2, p.50-67, Mar.1974.
9. Nobu Fujii, On the minimum gain pole-sensitivity product of single amplifier RC active net-
work, IEEE Trans., Vol. CAS-24, No.9, p.504-510, Sept.1977.
10. E. Moustakas and S.P.Chan, Sensitivity considerations in a multiple feedback universal active
filters, IEEE Trans., Vol. CAS-24, No.12, p.695-703, Dec. 1977.
11. K.R. Rao, and S.Srinivasan, A bandpass filter using the operational amplifier pole, IEEE J.
Solid-State Circuits,. Vol. SC-8, p.245-246, June. 1973.
12. B.P. Singh, A novel circuit for superc-apacitor simulation, Int. J. Electron, Vol.52, No.4,
p.337-339, 1982.
13. Paul M. Chirlian, Analysis and design of integrated electronic circuits, Harper & Row Publica-
tion, New York.
14. Sedra & Smith, Microelectronic circuits, Oxford Univ. Press.
Index
(see MOSFET, 215, 216, 219, 221, 223 Bridge rectifier, 146-149, 161

Abrupt anisotype heterojunction, 101 Brownian motion, 13, 16
Abrupt junction, 100, 102, 103, 57
Carrier concentration, 7, 10, 12, 39, 40
Acceptors, 7
Carrier frequency, 910-912
Active filters responses, 715
Cascode amplifier, 482, 483, 501, 503, 507
Active filters, 712, 713, 715, 730, 735, 738
CB amplifier, 323, 336-339, 363, 365
Active gyrator, 730
CC amplifier, 323, 339-342, 364
Amplification factor, 228, 230
CE amplifier, 333, 334, 364, 365
Analog computer, 722, 747, 748, 749, 752, 753, 759
Charge control model of BJT, 189
Analog multiplier, 708, 709
Clamper, 686, 687
Antilog amplifier, 699
Clapp oscillator, 574, 577, 578
Balancing differential amplifier, 491 Class A push-pull amplifier, 624, 625, 642, 643, 651
Bandwidth modification, 516 Class-A amplifier, 314, 363
Barkhausen criteria, 561, 601 Class-B amplifier, 314, 315
Base transport factor, 176, 195 Class-C amplifier, 314, 315, 363
Bel, 473, 474 Class-D amplifier, 314, 315
BiFET, 747 Classification of feedback, 519
BiMOS, 747 Clipper, 685, 686
Binding energy, 22 CMOS, 246, 247
Biquadratic function, 714, 722 Colpitts oscillator, 573-577
BJT phase splitter, 342, 346 Common gate amplifier, 370, 372, 380, 384, 385, 418
BJT ratings, 319 Compensation techniques, 663
BJT, 171, 179, 185, 187, 189 Complementary symmetry output stage, 631
Bleeder resistance, 156, 166, 167 Complementary symmetry scheme, 609
Bootstrap amplifier, 350, 351, 353, 365 Concentration gradient, 101, 102, 105
Index
'!'
Conduction band, 4 -7, 11, 12, 20, 22, 28 Donors, 6, 20

Covalent bond rupture, 13 Doping, 6, 7, 15, 19, 27
Covalent bond, 3, 4, 6, 7, 10-12 Double ended power amplifier, 607
Critical angle, 893, 900, 901, 902, 903, 908 Double tuned circuit, 920, 921
Critical inductance, 154, 165 Drain conductance, 367
Crossover distortion, 609, 629, 631-635 Drain resistance, 228, 229, 239, 248, 255
Crystal controlled Hartley Oscillator, 583 Drift current, 13, 14
Crystal oscillators, 560, 580 Drift, 12-14, 17, 18
CS-CB amplifier ac circuit, 495 Dual Gate MOSFET, 249
CS-CB amplifier, 497 DVCCS, 730, 731, 743, 744
CS-CE amplifier, 498 DVCVS, 730, 743, 744
Current feedback current error, 532, 558
Early effect, 432
Current feedback voltage error, 530, 531, 556, 557
Early voltage, 184, 204, 206, 207, 287, 288
Current mirror, 292-294, 296, 298, 307
Effect of cascading on bandwidth , 475
Current series feedback for output resistance, 522
Electrical pinch-off, 219
Current series feedback, 519, 520, 522, 523, 530, 558
Electroluminescence, 907
Current shunt feedback, 519, 520, 524, 525, 531, 532
Emitter coupled amplifier, 499, 500
Current sink, 291, 292, 299
Emitter coupled differential amplifier, 495
Current source, 278, 287, 288, 291, 292, 295
Emitter efficiency, 175, 214
Current steering circuit, 293
Emitter follower amplifier, 526
Current to voltage converters, 694
Emitter follower, 339, 346, 350, 351, 356, 362
Curtice and raytheon models, 244
Energy band, 2-5
Cut-in voltage, 124
Energy gap, 4, 5, 10, 12, 13
Darlington configuration, 346, 348, 350 Enhancement mode, 231, 233, 234, 235, 237
Darlington connection, 659 Enhancement type MOSFET, 230, 233, 234
DC stabilization, 675 Equivalent circuit of diode, 112
Decibel for voltage and current ratios, 474 Error amplifier, 851
Decibel, 474 Extrinsic semiconductor, 7, 18, 27, 32, 35, 43, 48, 51
Density of states, 39, 45, 46, 55
Factor, 173, 180, 189, 198, 199
Depletion capacitance, 99, 100, 105
FDNC, 734
Depletion mode, 230-233
FDNR, 734
Depletion region, 102, 104
Feed forward method, 727
Depletion type MOSFET, 231-233
Fermi level in intrinsic semiconductor, 13
Derating curve, 640
Fermi level, 5, 13, 18, 22, 48
Dielectric anisotropy, 904
FET parameters, 228, 248
Difference logarithmic amplifier, 698
FET phase splitter, 369
Differential amplifier (DC Analysis), 654
FET-BJT darlington, 500
Differential amplifier with active load, 658
FET-FET cascode amplifier, 501
Differential amplifier with long tail, 487, 656
Figure of merit, 613, 619, 627, 631
Diffusion capacitance, 102, 103, 105
Filters, 713, 714, 722, 730, 735, 737
Diffusion current, 16, 25, 39, 55
Fixed base bias, 264, 267, 302, 311, 312
Direct coupled amplifier, 425
FM output, 855
Discharge time constant, 846
Forward bias, 261, 270, 276, 278, 311
Distinct energy level, 2
Frequency response of CD amplifier, 380
Dominant pole compensation, 663, 664
Frequency response of CS amplifier, 376
Dominant pole, 477
Index
'"
Fresnel loss, 902 Long tail differential amplifier, 492

Full-wave rectifier, 142-146 Lossy inductor simulation, 732
Low-Pass high-cut RC circuit, 428
GaAs amplifier, 387
LT542, 898
Gain-Bandwidth product, 666, 678, 729, 735,
Luminous efficiency, 892
Germanium, 1, 2, 7, 8
Graded junction, 101, 102 Magneto resistor, 864
Majority charge carriers, 20
Half-wave rectifier, 136-138, 140, 141
Maximum current and voltage swings, 606, 612
Hall effect, 39
MESFET, 217, 242-246
Hartley oscillator, 574, 575, 583, 599, 600, 602, 603
Metal oxide semiconductor field effect transistor
Heterojunction, 99, 101
Miller theorem, 374
High-Pass low-cut RC circuit, 429
Minority charge carriers, 19
Holes, 5-8, 10
Missing pulse detector, 840
Homojunction, 99, 101-104
Monostable multivibrator, 707, 708
IC biasing, 287, 293 MOS current mirror, 388, 389
Ideality factor, 109, 119, 873, 882 MOSFET inverter, 239, 240
Impedance transformation, 919 Multistage tuned amplifier, 924
Inductively coupled single tuned amplifier, 915 Mutual conductance, 226, 229, 367
Input characteristics of BJT, 179, 182
NE555, 834
Instantaneous forward current, 894
NE565, 855
Insulator, 1, 2, 4, 5
Negative feedback, 514-519, 524
Integrated circuit class A amplifier, 619
Negative resistance, 560, 587, 588
Intelligent display modules, 898
Noise reduction, 518, 519
Intrinsic concentration, 7, 10, 42, 43, 47
n-type material, 6, 7, 8, 10, 18
Intrinsic conductivity, 12, 15, 42, 45
Intrinsic semiconductor, 7, 12, 13, 18, 27 Offset compensation and Nulling, 6
IR emitting diode, 878 OTA LM3080, 692
OTA, 688, 690-693
JFET, 215-219, 225, 226
Output characteristics of BJT, 179, 183
Joint current, 866
Output side single tuned amplifier, 920, 921
Junction capacitors, 424, 425, 426, 437
Output stage, 654, 690
Junction current, 108
Passive filters, 149
KHN biquad, 725
Passive filters, 713, 714
Large signal amplifier, 316 Paulis exclusion principle, 2
LCD, 898, 904, 905 Peak detector, 684, 685
LDR, 864, 865, 867, 868 Periodic table, 9
LED fabrication, 900 Permissible power dissipation, 319
LED materials, 889, 901 Phase detector, 851-855, 861
LED, 103, 884, 885, 887-889 Phase-lead RC oscillator, 563
Level shifter, 653, 654, 766 Photo conductive compounds, 865
Lifetime of carriers, 15 Photo resistive device, 865, 906
Linear ramp generator, 841 Photo resistor, 866
Linear range, 218, 224, 225, 240 Photodiode, 869, 873, 877, 907
Liquid crystal molecule, 904 Phototransistor, 875, 876, 907, 909
Logarithmic amplifiers, 696 Photovoltaic cell, 876, 877, 882
Index
'"
Physical pinch-off, 218, 238 Single tuned amplifier, 914-917, 919, 920, 921

Pinch-off voltage, 219, 222, 226, 250, 251 Slew rate, 747, 667, 690, 712, 767, 768
pMOSFET, 240-242, 246 Small signal equivalent circuit of FET, 366
Polaroid, 904 Small signal model of BJT, 327
Pole frequency, 714, 722, 664, 667 Snells Law, 902
Pole quality factor, 715, 722 Soloar cell, 873, 878-881
Pole-Zero compensation, 663, 665 Space charge region, 102
Positive feedback, 514, 519 Square wave generator, 705
Potential barrier, 102-104 State variable biquad, 722
Power amplifier, 606, 613, 616, 619, 622 Static characteristics of BJT, 178
Power dissipated in biasing resistors, 613 Stray capacitance , 742, 743
Power gain, 324, 325, 359, 364 Supercapacitor, 734
Power transistors, 639 Superdiode Half-Wave Rectifier, 701
Precision full wave rectifier, 703, 704 Superdiode, 700-702
Precision rectifier, 700-703 Switched capacitor filter, 713, 737, 738
photocurrent, 870 Switched capacitor integrator, 741
p-type material, 7, 8, 22, 32, 34
p-type material, 7, 8, 22, 48, 50 Temperature compensated current sink, 299
Punch through, 432 Tetravalent elements, 2, 10
Push-Pull power amplifier, 623, 628, 641, 642, 650 Thermal resistance, 639, 640
Thermally generated electrons, 19
Radiative recombination, 885-887, 901 Thermally generated holes, 19
Radio frequency oscillators, 560, 572 Thermistor, 864, 868, 905, 908, 909
RC oscillators, 560, 563 Transconductance amplifier, 522, 530
RC phase-lead BJT oscillator, 566
Transconductance, 225, 228, 230, 244, 245
Reach Through, 432
Transfer characteristics, 227, 239, 240
Realization of resistor using capacitor, 718
Transfer function of All Pass Filter, 725
Relaxation oscillator, 588, 591, 592, 600, 603
Transfer function of Band Pass Filter, 723
Resistance of material, 15
Transfer function of Low Pass Filter, 718
Reverse bias, 261, 311
Transformer coupled amplifier, 422-425
Reverse saturation current, 109-111, 121, 123
Transformer coupled Class A amplifier, 617
Riordan circuit, 730, 734, 784
Transition capacitance, 435-437, 469
Sallen-Key filters, 716 Transport factor, 176, 195
Sample-and-Hold circuit , 695, 696 Triangular wave generator, 705, 706
Saturation range, 225 Tuned collector, 560, 572, 579, 602
Schmitt trigger, 782 Tuned potential amplifier, 422
Schottky diode, 103, 105
Schottky-barrier diode, 242-244 UJT, 584-592, 600
SE555, 834 Unijunction transistor, 584
Self bias, 267, 311, 312 Unity gain frequency of FET, 375
Sensitivity figure, 714, 715, 722, 737 Valence band, 4-7, 11
Sensitivity to gain variation, 515 Valence electrons, 1-3, 6
Silicon, 1-3, 7 Varactor diode, 103
Simulated inductance approach, 730 Voltage divider emitter bias, 277-279, 302, 304
Single ended power amplifier, 607, 643, 644 Voltage doubler, 158, 159, 167
Single ended transformer coupled stage, 617 Voltage feedback current error, 529, 551, 558
Index
'"
Voltage feedback voltage error, 527, 539, 558 Weinbridge oscillator, 568-570, 599, 600
Voltage gain, 323-325, 339, 348, 350, 352, 357 Widlar circuit, 290, 295, 296
Voltage multiplier, 158 Wilson source, 298
Voltage regulation, 160 Window detector, 680, 681
Voltage series feedback for output resistance, 521 Work function, 5
Voltage series feedback, 519-522, 526, 558
Zener diode, 104
Voltage shunt feedback, 519, 520, 523, 524, 528, 558
Zener regulator, 115

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ELECTRONIC DEVICES

2. Physical Phenomenon in Homojunction 57

2.6 Depletion/Transition Layer Capacitance Across Homojunction 72

3. Diode as Circuit Element 107

4. Junction Diode Rectifier 136

5. Physical Phenomenon in BJT 171

5.5 DC Equivalent Circuit 177

6. Physical Phenomenon in JFET and MOSFET 215

Questions for Practice 311

8. BJT Amplifiers 313

9. FET Amplifiers 366

10. Frequency Response of BJT Amplifiers 421

11. Multistage Amplifiers 472

12. Feedback in Amplifiers 514

13. Oscillators 560

14. Power Amplifiers 605

15. Operational Amplifier 652

15.13 Simulated Inductance Approach 729

16. Regulated Power Supplies 786

16.1 Introduction 786

17. Integrated Circuit Timers 833

18. Special Two Terminal Devices 864

Questions for Practice 905

19. Tuned Amplifier 910

Figure 1.1 Representation of tetravalent element Si

1.1.4 Energy Band

Figure 1.2 Two isolated atomic orbits

Figure 1.3 Energy levels in two isolated atoms

Figure 1.4 Shifting of energy level

Figure 1.5 Silicon atom with orbits and available states

Figure 1.6 Covalent bonding of tetravalent element

Figure 1.8 Energy band diagram of insulators, semiconductors, and metals

1.2 Current Flow and Concept of Holes

Figure 1.9 Simplified energy band diagram to describe semiconductor

1.3 Free Carriers—Excitation and Doping

Figure 1.10 Thermal excitation of a semiconductor doped with donor

1.4 Intrinsic and Extrinsic Semiconductor

Table 1.1 Classification of materials based on conductivity, resistivity, and bandgap

Material Conductivity(S/m) Resistivities Bandgap Classification

Table 1.2 Periodic table of useful materials

Table 1.3 Physical properties of silicon and germanium

Why n-type material is mainly used in manufacturing the semiconductor devices?

1.5 Tetravalent Elements

Figure 1.13 Covalent bonds in intrinsic Si

Figure 1.14 Thermal generation of electron-hole pair

Figure 1.15 Intrinsic semiconductor energy band

1.6 Effect of Temperature on Intrinsic Conductivity

Figure 1.16 Forces due to drift of holes and electrons

1.7 Conduction of Current

1.7.1 Drift Current

Figure 1.17 Brownian motion of electrons

Figure 1.18 (a) Drift of electrons (b) Drift of holes

Hence, conductivity of the material = sn + sp = s = q nm n + pm p d i (1.7.10)

Figure 1.18 (c) Drift of holes and electrons

1.7.3 Diffusion Current

Figure 1.19 Diffusion of holes in Brownian motion

J = J n(Drift) + J p(Diffusion) = qnm n E + qDn F dn I = qm |RSnE + FG D IJ F dnI |UV

Dividing Jn = qDn RS d(Dn) UV by m yields

Similarly, total electron current due to drift and diffusion is

Figure 1.20 Intrinsic semiconductor energy band

1.8 Extrinsic Semiconductor

1.8.1 n-type Material

= 2 (1.97 ¥ 10 44 )3/ 2 (meT )3/ 2 = 2 ¥ 2.776 ¥ 10 66 (meT )3/ 2

= 4.57 ¥ 1022 / m 3 EC EF = 0.25 eV, NC(300 K)