CS612

Algorithms for Electronic Design Automation

Background and Introduction

Mustafa Ozdal

CS 612 – Lecture 2 Mustafa Ozdal 1

Computer Engineering Department, Bilkent University
 © KLMH
SOME SLIDES ARE FROM THE BOOK:
VLSI Physical Design: From Graph Partitioning to Timing Closure
MODIFICATIONS WERE MADE ON THE ORIGINAL SLIDES

Chapter 1 – Introduction

Original Authors:
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 2

Lienig
 1.1 Electronic Design Automation (EDA)

© KLMH
Moore’s Law

Moore: „Cramming more components onto integrated circuits"

In 1965, Gordon Moore (Fairchild)
stated that the number of
transistors on an IC would double
every year. 10 years later, he
revised his statement, asserting
that they double every 18 months.
Since then, this “rule” has been

Electronics, Vol. 38, No. 8, 1965

famously known as Moore’s Law.

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 3

Lienig
 1.1 Electronic Design Automation (EDA)

© KLMH
Without the design technology
innovations between 1993 and
2007, the design cost of a chip
would have been $1800M

ITRS 2009 Cost Chart

ITRS (in2009
Millions of Chart
Cost Dollars)
(in Millions of Dollars)
120.0
120.0
120.0
100.0
100.0
100.080.0
80.0
55.7
55.7
79.0
79.0 46.7
46.7
80.060.0
60.0 42.5
42.5 46.6
46.6 55.7
56.479.0 33.646.7
33.6 35.2
35.2 40.5
40.5
60.040.0 40.7 56.4 31.142.5
31.1 34.046.6
34.0
40.0 40.7 27.2
27.2 29.440.5
29.4
29.6
29.6 56.4 33.6 35.2 21.4
40.020.0 40.7 44.931.1 34.0 21.4 43.5
43.5
20.0 32.9 44.9 39.827.2
39.8 32.6 36.9
36.9 29.4 31.7
29.6 26.3 32.9 29.5
29.5 25.2 32.6 27.0 27.0 23.1 31.7
15.7 20.3
15.7 19.4 26.3
20.3 19.4 25.2 21.416.9
16.9 23.1 43.5
20.0 0.0
0.0 44.9 39.8 36.9
32.9 29.5 32.6 27.0 31.7
15.7 20.3 19.4 26.3 25.2 16.9202123.12022 2023 2024
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018
0.0 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 20242019 2020
2009 2010 HW
Total 2011 2012 2013
Engineering Costs2014 2015
+ EDA
EDA 2016 2017
Tool Costs
Costs Total2018 2019 2020Costs
SW Engineering
Engineering 2021+ ESDA
2022 Tool
2023 2024
Costs
Total HW Engineering Costs + Tool Total SW Costs + ESDA Tool Costs
Total HW Engineering Costs + EDA Tool Costs Total SW Engineering Costs + ESDA Tool Costs

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 4

Lienig
 1.1 Electronic Design Automation (EDA)

© KLMH
Time Period Circuit and Physical Design Process Advancements

1950 -1965 Manual design only.

1965 -1975 Layout editors, e.g., place and route tools, first developed for
printed circuit boards.

1975 -1985 More advanced tools for ICs and PCBs, with more sophisticated
algorithms.

1985 -1990 First performance-driven tools and parallel optimization algorithms

for layout; better understanding of underlying theory (graph theory,
solution complexity, etc.).

1990 -2000 First over-the-cell routing, first 3D and multilayer placement and
routing techniques developed. Automated circuit synthesis and
routability-oriented design become dominant. Start of parallelizing
workloads. Emergence of physical synthesis.

© 2011 Springer Verlag

2000 - now Design for Manufacturability (DFM), optical proximity correction
(OPC), and other techniques emerge at the design-manufacturing
interface. Increased reusability of blocks, including intellectual
property (IP) blocks.

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 5

Lienig
 1.2 VLSI Design Flow

© KLMH
System Specification
Goals and requirements:
Functionality, performance,
Architectural Design
ENTITY test is dimensions, etc.
port a: in bit;
end ENTITY test;
Functional Design
and Logic Design

Circuit Design

Physical Design

Physical Verification
DRC
LVS
and Signoff
ERC

Fabrication

© 2011 Springer Verlag

Packaging and
Testing

Chip

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 6

Lienig
 1.2 VLSI Design Flow

© KLMH
System Specification

Architectural Design e.g. Instruction set, memory

ENTITY test is
port a: in bit;
end ENTITY test; system, number of cores,
Functional Design
communication protocols, …
and Logic Design

Circuit Design

Physical Design

Physical Verification
DRC
LVS
and Signoff
ERC

Fabrication

© 2011 Springer Verlag

Packaging and
Testing

Chip

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 7

Lienig
 1.2 VLSI Design Flow

© KLMH
System Specification

Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design Hardware description using
and Logic Design
RTL. Logic synthesis tools to
Circuit Design generate netlists.

Physical Design

Physical Verification
DRC
LVS
and Signoff
ERC

Fabrication

© 2011 Springer Verlag

Packaging and
Testing

Chip

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 8

Lienig
 1.2 VLSI Design Flow

© KLMH
System Specification

Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design
and Logic Design

Circuit Design Transistor-level design of

low level elements, e.g.
Physical Design SRAMs, IO, critical blocks,…

Physical Verification
DRC
LVS
and Signoff
ERC

Fabrication

© 2011 Springer Verlag

Packaging and
Testing

Chip

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 9

Lienig
 1.2 VLSI Design Flow

© KLMH
System Specification

Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design Chip Planning
and Logic Design

Circuit Design Placement

Physical Design
Clock Tree Synthesis

Physical Verification
DRC and Signoff
LVS Signal Routing
ERC
Fabrication

Timing Closure

© 2011 Springer Verlag

Packaging and Testing

Chip

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 10

Lienig
Physical Design

E
A

C D Logic gates & connections

B F
Netlist

Shapes on chip layers

Metal layers

Device layers

Chip Layers
- 11 -
 1.2 VLSI Design Flow

© KLMH
System Specification

Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design
and Logic Design

Circuit Design

Physical Design

Physical Verification
DRC
and Signoff
Design rule checking (DRC)
LVS
ERC Layout vs. schematic (LVS)
Fabrication Electrical rule checking (ERC)

© 2011 Springer Verlag

Packaging and
Testing

Chip

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 12

Lienig
 1.2 VLSI Design Flow

© KLMH
System Specification

Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design
and Logic Design

Circuit Design

Physical Design

Physical Verification
DRC
LVS
and Signoff
ERC

Fabrication
Layout sent to a fab (tapeout).
Photomasks used to print the

© 2011 Springer Verlag

Packaging and
Testing layout patterns onto layers.

Chip

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 13

Lienig
 1.2 VLSI Design Flow

© KLMH
System Specification

Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design
and Logic Design

Circuit Design

Physical Design

Physical Verification
DRC
LVS
and Signoff
ERC

Fabrication

© 2011 Springer Verlag

Packaging and Die is positioned in a package.
Testing
Pins connected to the package
Chip pins. Multiple chips can be
integrated.

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 14

Lienig
VLSI Design Styles

 Full-custom design
Direct transistor-level design
Max flexibility, few constraints
Potential to highly optimize, but high design cost
Critical and high-volume parts that will be replicated

 Semi-custom design
 Cell-based: Standard and macro cells
Many pre-designed elements in the libraries
 Array-based: Configure the pre-fabricated elements
e.g. FPGA
CS 612 – Lecture 2 Mustafa Ozdal 15
Computer Engineering Department, Bilkent University
 Cell Based Design

© KLMH
Common digital cells

AND OR INV NAND NOR

IN1 IN2 OUT IN1 IN2 OUT IN OUT IN1 IN2 OUT IN1 IN2 OUT

0 0 0 0 0 0 0 1 0 0 1 0 0 1
1 0 0 1 0 1 1 0 1 0 1 1 0 0
0 1 0 0 1 1 1 0 0 1 1 0 1 0
1 1 1 1 1 1 1 1 1 1 0 1 1 0

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 16

Lienig
 1.3 VLSI Design Styles Vdd Contact

Metal layer

© KLMH
Vdd IN2 Poly layer
IN2
IN1 OUT Diffusion layer
OUT
IN1 p-type
transistor

n-type
GND
transistor
GND
IN1
OUT
IN2

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 17

Lienig
 1.3 VLSI Design Styles Vdd Contact

Metal layer

© KLMH
Vdd IN2 Poly layer
IN2
IN1 OUT Diffusion layer
OUT
IN1 p-type
transistor

n-type
GND
transistor
GND
IN1
OUT
IN2 Power (Vdd)-Rail

Ground (GND)-Rail

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 18

Lienig
Cell Placement

E
A

C D
B F Implementation on
device layers
available in cell library
(e.g. AND, OR,
NAND, NOR, INV,
etc.)

Cells arranged in
rows on metal1
Metal 1
Device layers

- 19 -
 1.3 VLSI Design Styles

© KLMH
Standard cell layout with Standard cell layout using
a feedthrough cell over-the-cell (OTC routing

Power Standard Ground Power Standard Ground

Pad Pad
Pad Cells Pad Pad Cells Pad

A A
VDD VDD

GND
A’ GND

A’

© 2011 Springer Verlag

Feedthrough Routing
Cell Channel
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 20

Lienig
Over-the-cell routing
a
o
a A o E
b
a
o a D o
C
b a
aB o o
F
All terminals on
b
metal1

Connect terminals
Metal5
using metal layers
Metal4
Metal3 Each layer is either
Metal2 horizontal or vertical
Metal1

- 21 -
Routing Between Two Pins

a
Metal3 C o a D o
b

Route from C/o to

D/a

Metal2
Metal3: vertical
Metal2: horizontal
Metal1: escape-only
o a
Metal1 D
o a b Interlayer
connection: “via”
C

- 22 -
 Cell Based Design

© KLMH
Layout with macro cells

RAM
PLA
VDD

RAM
Standard Cell GND
Block
PLA

© 2011 Springer Verlag

Pad Routing Regions

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 23

Lienig
Why Cell Based Design?

 Easier to design, optimize and verify

 Reuse of components
 Performance of each cell pre-characterized

 Transistor-level design constraints already handled

 Complexities abstracted in the cell definition

 Optimization easier

 Disadvantage: Less room for optimization

 Cannot have a cell for every single complex logic function

CS 612 – Lecture 2 Mustafa Ozdal 24

Computer Engineering Department, Bilkent University
 Field Programmable Gate Array (FPGA)

© KLMH
After fabrication:
Each logic element can be configured to implement different functions
Each switchbox can be configured to change the connectivity

Logic Element
LB LB LB
Switchbox Connection
SB SB

LB LB LB

SB SB

© 2011 Springer Verlag

LB LB LB LB

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 25

Lienig
 1.4. Design Rules

© KLMH
Categories of design rules

 Size rules, such as minimum width: The dimensions of any component (shape),
e.g., length of a boundary edge or area of the shape, cannot be smaller than given
minimum values. These values vary across different metal layers.

 Separation rules, such as minimum separation: Two shapes, either on the

same layer or on adjacent layers, must be a minimum (rectilinear or Euclidean
diagonal) distance apart.

 Overlap rules, such as minimum overlap: Two connected shapes on adjacent

layers must have a certain amount of overlap due to inaccuracy of mask alignment
to previously-made patterns on the wafer.

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 26

Lienig
 1.4. Design Rules

© KLMH
Categories of design rules

: smallest meaningful technology-

dependent unit of length

a 
c
Minimum Width: a
Minimum Separation: b, c, d
e Minimum Overlap: e
d
b

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 27

Lienig
 1.5 Physical Design Optimizations

© KLMH
Types of constraints

 Technology constraints enable fabrication for a specific technology node

and are derived from technology restrictions. Examples include minimum layout
widths and spacing values between layout shapes.

 Electrical constraints ensure the desired electrical behavior of the design.

Examples include meeting maximum timing constraints for signal delay and staying
below maximum coupling capacitances.

 Geometry (design methodology) constraints are introduced to

reduce the overall complexity of the design process. Examples include the use of
preferred wiring directions during routing, and the placement of standard cells in
rows.

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 28

Lienig
 1.6 Algorithms and Complexity

© KLMH
Runtime complexity

 Runtime complexity: the time required by the algorithm to

complete as a function of some natural measure of the problem size,
allows comparing the scalability of various algorithms
 Complexity is represented in an asymptotic sense, with respect to the
input size n, using big-Oh notation or O(…)
 Runtime t(n) is order f (n), written as t(n) = O(f (n))
t(n)
where k is a real number
lim =k
n®¥ f (n)

 Example: t(n) = 7n! + n2 + 100, then t(n) = O(n!)

because n! is the fastest growing term as n  .
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 29

Lienig
 1.6 Algorithms and Complexity

© KLMH
Runtime complexity

 Example: Exhaustively Enumerating All Placement Possibilities

 Given: n cells
 Task: find a single-row placement of n cells with minimum total wirelength by using
exhaustive enumeration.
 Solution: The solution space consists of n! placement options. If generating and
evaluating the wirelength of each possible placement solution takes 1 s and
n = 20, the total time needed to find an optimal solution would be 77,147 years!

 A number of physical design problems have best-known algorithm complexities that

grow exponentially with n, e.g., O(n!), O(nn), and O(2n).
 Many of these problems are NP-hard (NP: non-deterministic polynomial time)
 No known algorithms can ensure, in a time-efficient manner, globally optimal solution
 Heuristic algorithms are used to find near-optimal solutions

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 30

Lienig
 1.6 Algorithms and Complexity

© KLMH
Heuristic algorithms

 Deterministic: All decisions made by the algorithm are repeatable, i.e., not
random. One example of a deterministic heuristic is A* shortest path algorithm.

 Stochastic: Some decisions made by the algorithm are made randomly, e.g.,
using a pseudo-random number generator. Thus, two independent runs of the
algorithm will produce two different solutions with high probability. One example of a
stochastic algorithm is simulated annealing.

 In terms of structure, a heuristic algorithm can be

 Constructive: The heuristic starts with an initial, incomplete (partial) solution and
adds components until a complete solution is obtained.

 Iterative: The heuristic starts with a complete solution and repeatedly improves
the current solution until a preset termination criterion is reached.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 31

Lienig
 1.6 Algorithms and Complexity

© KLMH
Heuristic algorithms

Problem Instance
Constructive Algorithm
Initial Solution

Iterative Improvement

no
Termination
Criterion Met?

yes
Return Best-Seen Solution

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 32

Lienig
 1.7 Graph Theory Terminology

© KLMH
Graph Hypergraph Multigraph

b b b
a e

f
a a
c d
e g f
d c c

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 33

Lienig
 1.7 Graph Theory Terminology

© KLMH
Directed graphs with cycles Directed acyclic graph

c f c f
a a
a b
b d g b d g

e e

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 34

Lienig
 1.7 Graph Theory Terminology

© KLMH
Undirected graph with maximum node degree 3 Directed tree

b a
a

f b c d
c

e g e f g h i j k
d

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 35

Lienig
 1.7 Graph Theory Terminology

© KLMH
Rectilinear minimum spanning Rectilinear Steiner minimum
tree (RMST) tree (RSMT)

b (2,6) b (2,6)

Steiner point

c (6,4) c (6,4)

a (2,1) a (2,1)

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 36

Lienig
 1.8 Common EDA Terminology

© KLMH
Netlist

(a: N1) (N1: a, x.IN1, y.IN1)

a x (b: N2) (N2: b, x.IN2, y.IN2)
N3 N5 (c: N5) (N3: x.OUT, z.IN1)
N1 N2 z c (x: IN1 N1, IN2 N2, OUT N3)
N4 (N4: y.OUT, z.IN2)
(y: IN1 N1, IN2 N2, OUT N4) (N5: z.OUT, c)
y
b (z: IN1 N3, IN2 N4, OUT N5)

Pin-Oriented Netlist Net-Oriented Netlist

© 2011 Springer
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 37

Lienig
 1.8 Common EDA Terminology

© KLMH
Connectivity graph

a x a x
N3 N5
N1 N2 z c z c
N4
y
b b y

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 38

Lienig
 1.8 Common EDA Terminology

© KLMH
Connectivity matrix

a b x y z c

a 0 0 1 1 0 0
b 0 0 1 1 0 0
a x
x 1 1 0 2 1 0
N3 N5
N1 N2 z c y 1 1 2 0 1 0
N4
z 0 0 1 1 0 1
y
b c 0 0 0 0 1 0

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 39

Lienig
 1.8 Common EDA Terminology

© KLMH
Distance metric between two points P1 (x1,y1) and P2 (x2,y2)

d  x2  x1  y2  y1
n n
n

with n = 2: Euclidean distance d E ( P1 , P2 )  ( x2  x1 ) 2  ( y 2  y1 ) 2

n = 1: Manhattan distance d M ( P1 , P2 )  x2  x1  y2  y1

P1 (2,4) dM = 7

dE = 5

dM = 7 P2 (6,1)

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 40

Lienig
 Next Lecture: Netlist and System Partitioning

© KLMH
2.1 Introduction
2.2 Terminology
2.3 Optimization Goals
2.4 Partitioning Algorithms
2.4.1 Kernighan-Lin (KL) Algorithm
2.4.2 Extensions of the Kernighan-Lin Algorithm
2.4.3 Fiduccia-Mattheyses (FM) Algorithm
2.5 Framework for Multilevel Partitioning
2.5.1 Clustering
2.5.2 Multilevel Partitioning
2.6 System Partitioning onto Multiple FPGAs

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 41

Lienig