5-01-2019 Physical design

lef&def is common formats used by several EDA tools. Power mesh requires less
resistance & high current carrying capacity, so top metal layers are used as
these are more thick. For cell delay is higher for low voltage & Cmax. For
wire delay is higher at high temp and Rcmax corner. Power mesh act as decap.
After each stage check qor. After placement check qor for congestion & timing
analysis.

Placement & Optimization

Tasks

1. Give legal locations to all std cells

2. optimize design for best routability,timing(DRV/setup), power&area

Goals:

1. Achieve a placed design for best routability & timing clean

Steps:

1. Pre place

Before placing std cells

1. Add End cap cells(At the start & end of the rows to avoid well proximity
effects*)

2. Tap cells are placed at regular intervals based on well tap placing info
given by foundry depends on latchup phenomena, so that power IRdrop
requirement is achived. To avoid latchup back2back paracitic BJT leads to
power ground shorting tapcells/guard rings are used.

3. IO port buffers (signals are buffered at IO ports for strengthening)

4. Spare cells(used for ECOs / post tape out ECO) without spare cells, all
base layers/metal layers are to be changed for ECO implimentination, if spare
cells were present only metal layers can be redone. If mask changes are less
will cause less cost

5. placement guidance(placement bounds sync cells are placed

closely(soft/hard/exclusive bound no other cells can sit in the defined
boundary)/blockages/keepouts)

2. placement: Standard cells are placed

A. Coarse placement(timing/congestion driven)

B. Leagal placement (right location & orientation)

3.Trial/global route

4.Optimisation:Congestion/timing ICC UserGuide refer 2 placement chapter

4. post placement: Tie cell addition/scan chain reordering. Tie cell contains
Low pass filter which filters power ground high frequency noise/fluctuations
during circuit operation. Scan chain reordering is done to reduce scan wire
length optimisation&congestion.

5.QOR checked for routabilty(congestion),timing(DRV max tran/max cap,setup

violations),power,area

Congestion is the measure of routability. Tool reports metrics as OVERCON,

WIRELENGTH & congestion map

Reasons of congestion: Higher global placement density, higher local placement

density, higher pin density

Impact of congestion: Routability (DRC,shorts,timing detouring,cross talk)

Horizantal & vertical overcon numbers

1000 Gcells 500 -> -2 track deficiency

0.5(H) & 0.2(V) cong = Number of routs%number of tracks preferred value is

less than 1

1. Global congestion: Congestion is every where in the design

2. Local congestion: Congestion present in local area.

To analyze/mitigate congestion: Congestion maps open placement density map &

pin density map.

Methods to resolve congestion: Tool switches (high congestion effort, magnet

placement(closer placement), bounds,placement blockage,keepout,max
utilization,re floor plan

For Global congestion try max utilization, for high pin desnity try
keepout/halo/cell padding partial blockage around high pin count cells OR keep
higher channel width between macros.

Lab

After power mesh is performed

Add missing power vias

High fanout synthesis is performed on clock reset scan clk enable

Legalise placement makes all cells sit on site rows

GRC global route congestion should be less than 0.5