16_2_19 week10

Jitter will have impact on setup check (2Tj) as serup check takes place at different edges. Jitter has
not effect on Hold check as it takes place at same edge. But for the Half cycle path setup check
takes place between rising edge & next falling edge 2Tj jitter has impact on setup. In this case hold
check takes place between two different edges 2Tj jitter has impact on hold check.
https://vlsiuniverse.blogspot.com/2013/07/setup-and-hold-checks-static-timing.html

6. Optimisation techniques
7. OCV On Chip Variation
All dies in each waferhave same opearting condition SS/TT/FF.
Within a wafer every die has some variation. Not all mosfets in
the same day have same voltage/temp/process. Local ocv. All small
variations in PVT. Global variations are modelled in timing libs
Local variations are modelled in derates.
OCV derate 10% is valid (by fab) @ max_tran & max_cap
2. 10% of clock period
DRM (Delay rule manual) Imp & signoff guide lines(derate values)
document is obtained from fab. OACV is provided by library vendor
8. CPRR
Cell present in common path STA calculates max delay for setup
path & min delay for hold path which adds pessimism.
9. Low power
10. Synthesis
SIGN OFF
Finish routeing & op -> add decap (more size mosfet) & filler cells(less size has n well continues)
-> Generate outputs Signoff with different tools tasks(STA/PT) Extractor(Quantus/StarRc)A -->
GDS --> Dummy base metal fill (base & netal poly min max density rule) --> filled GDS -->
DRC+LVS+ERC+DFM(lpc/pattern matching) + PERC
A-FV
A-Rail analysis Redok (EM/Power/IR drop)
After all of these passed signoff
PBA mode path based analysis takes lot of time by STA tool