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Array Hybrid Multiplier versus Modified Booth Multiplier: Comparing Area and
Power Consumption of Layout Implementations of Signed Radix-4 Architectures
Leonardo L.de Oliveira Eduardo Costa Sergio Bampi
UFSM/PPGEE – Santa Maria, Brazil UCPel, Pelotas, Brazil UFRGS,P.Alegre,Brazil
leonardo@mail.ufsm.br ecosta@atlas.ucpel.tche.br bampi@inf.ufrgs.br
João Baptista José Monteiro
UFSM/PPGEE – Santa Maria, Brazil IST/INESC,Lisboa,Portugal
batista@inf.ufsm.br jcm@inesc.pt
Abstract- In this paper, we describe the fully automated custom A. Hybrid Code
layout implementations of two architectures for signed The idea of the hybrid code is to split the operands in
multiplication. Performance comparisons between the two, groups of m-bits, encode each group using the Gray code and
namely in terms of their power consumption and area estimation to use the Binary approach to propagate the carry between the
are provided for 8 and 16-bit operands. The first architecture groups. In this way, a compromise between the minimum
consists of a signed array multiplier that uses a radix-4 hybrid Hamming distance between consecutive values of the Gray
encoding to reduce the partial product lines and switching code and the minimum bit dependency of the Binary code is
activity in the data buses. This new arithmetic operand encoding achieved [3]. Table I shows the 2’s complement Hybrid
was recently proposed in [4], however only results at the logic encoding for 4-bit numbers and m=2.
level were presented. The second architecture implemented was
the widely used modified Booth multiplier [9]. The layout of TABLE I
both multipliers was generated by an automatic layout synthesis 2’S COMPLEMENT HYBRID CODE REPRESENTATION FOR M=2.
tool called TROPIC [10]. We compare the layout Dec Hyb Dec Hyb Dec Hyb Dec Hyb
implementations in terms of area and power, as well as provide
0 0000 4 0100 -8 1100 -4 1000
comparisons to first-order area estimates done in the logic design 1 0001 5 0101 -7 1101 -3 1001
phase. The results show that the new hybrid array multiplier 2 0011 6 0111 -6 1111 -2 1011
can be significantly more efficient, with close to 30% power 3 0010 7 0110 -5 1110 -1 1010
savings. B. Radix-2m Hybrid Array Multiplier
I. INTRODUCTION The radix-2m operation in 2’s complement representation is
Multiplier modules are common to many DSP applications. given by Equation 1.
W
−1
The fastest types of multipliers are parallel multipliers. m
Among these, the Wallace multiplier [13] is among the R × Y = R′ × Y ′ − R′yW −1 yW −1 2W − m − rW −1rW −1 ∑ y j 2W − m + j
m m
j=0
fastest. However, they do not have such a regular structure as (1)
the conventional array [8] or Booth [9] multipliers. Hence, This operation is illustrated in Fig. 1. For the case of radix-
when layout regularity, high-performance and low power are 4 we have a conversion from hybrid code to binary code at
primary concerns, Booth multipliers tend to be the primary the input of values. After that, the bits are calculated to
choice [2], [5], [7], [9], [11]. In this paper, we present layout binary encoding. Finally, at the end of multiplication, the
implementations for both the Modified Booth multiplier and final value is converted to hybrid encoding.
the new array multiplier using hybrid code proposed in [4]. HYBRID
REPRESENTATION -1 3 1 2 Decimal Representation
BINARY REPRESENTATION
the ELDO which is a spice-like simulator and is part of the (1 0)1 1 1 1 1 0 1 1 0 0 + 1110 Type II
+ 1101 Type II
Mentor Graphics environment, was used. The results show + 1111100010 1111101100 1111100010
the radix for the Booth architecture is a difficult task, thus not 0000010100 1111110110
being able to leverage from the potential savings of higher 00 00 00 10 10 01 01 00
radices. This paper is organized as follows. The next section 214x0 212 x0 210 x0 28x3 26x3 24x1 22x1 20x0
HYBRID
REPRESENTATION
* * * *
Type II Type I Type I Type I
2 2 2 2 2 2 2
* * * * + + + +
1 1 1
Type II Type I Type I Type I
2 2 2 2 2 2 2 2 2 2 2
* * * * + + + +
Type II Type I Type I Type I 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2
* * * * + + + +
Type III Type II Type II Type II 1 1 1
sign extension
2 2 2 2 2 2 2 2 2 2 2 2
- - - - + 1 + 1 + 1 + 1 +
1 1 1
2 2 2 2
2 2 2 2 2
sign extension
+ 1 + 1 + 1 + 1 +
2 2 2 2
sign extension
+ 1 + 1 + 1 + 1 +
2 2 2 2 2 2 2 2