Week12 09/03/2019

Difference across various technology nodes

1. Channel length reduces

2. size of die reduces as transistor shrinks

3. Speed increased

4. Voltage is lowered as low Vt

4. Leakage power % increases, dynamic power reduces as

voltage is lowered and cells occupy less area so net
capacitance load is reduced. Wire delay is increased for
lower nodes as wires became thinner

5. power density is increased & more IR drop

6. Congestion issue becomes more

7. Tap based vs tap less libraries

8. cross talk impact is increased as nets are placed closely

9. LPC(DFM) pattern matching

10. FINFET & DPT duel/multi pattern

11. OCV impact is increased

12. DRC foundry rules are more

13. Number of metal layers is increased as demanded more

14. setup time of flop depends on data tran & clock tran

15. 3D & 2.5D ASIC packaging related

16. Latch based & flop based timing time borrowing is

allowed in latches

17. Lockup latch: Two different clock domains during DFT

flops are scan chains are connected randomly. Clk1 ID 3 ns
clk2 IS 5ns. Skew is higher and setup path is relaxed. Hold
may violated for +ve skew. Lockup latch induces -ve skew and
helps hold violation
Voltage Process spef temp

.95 SS CW -40

.75 FS RCW 125

.615 SF CB 0

.510 FF RCB

TP

setup hold tran cap fanout derate uncertainity

clk min period min pulse width

Tran upsize buffering vt swap fan splitt buf replace with

invertor pair

Small slack is fixed in last stage use vt swap

Tran of FF out is fixed by adding buffer when setup slac is +ve

NBUF normal buffer which doesn’t have equal rise fall times

pt_shell> insert_buffer DFFQ NBUF2 adds NBUF after DFFQ port

saves as eco text file

pt_shell > size_cell DFF_LVT upsizng/downsizing/vt swapping

pt_shell>insert_buffer{input pin1 p2 ... p8} BUFF2X

Fringes? CMOS

Always add buffer at end point 2 fix hold violation

buffer/delay cells?

Vt swap cells have io pins but different poly

USE PBA to report timing

for fixing setup violation upsize the cells in the setup path

Max tran cap setup & hold fix violations

pt_shell>write_changes -format icctcl -output pt_eco.tcl writes
all the pt_eco commands to pt.tcl which can be read by icc and
execute to update the netlist then do leagalize_placement and tun
eco_route

Routing ->starRC->pt_shell->write_changes_file->executein ICC-

>eco_leagalize->eco_route ->report_qor

PG netlist contains VDD VSS connections to each standard cell.

usually dumped after routed stage. If any analog macro like DDR3 phy
is there in top level netlist, it has lef/def/gdf & spice views.
During PD DDR3 phy is treated as like a macro in placement phase and
PD flow continued