Zr7 System Block Diagram: Ver: 1A

5 4 3 2 1
VER : 1A BOM MARK

BOM P/N Description ZR7 SYSTEM BLOCK DIAGRAM IV@ INT VGA
EV@ DISCRETE
SW@ SW VGA
11P@ N11P VGA
11M@ N11P VGA
11EP@ N11P + N11E VGA
D
Clarksfield <Discrete only Channel A 3D@ N11E VGA +3D D
64MB/128MB x 8 ES@ N11X+SW VGA

w/4 DIMM> N11M-GE1 Channel C
CSP@ Option P/N (ARD&R D)
P21, 22
Arrandale <UMA only> N11P-GE1 VSP@ Option P/N (GPU/ VRAM)
DDRIII-SODIMM2
Dual Channel DDR III Auburndale <UMA/SG> EXT_LVDS
DDRIII-SODIMM1 Nvidia-GPU
800/1066 MHZ IMC rPGA 989 PCI-E x16
P14,15 P4, 5, 6, 7
GFX EXT_CRT
P16, 17, 18, 19, 20, 21, 22,
CRT Con.
TS3DV421 P23
EXT_LVDS
FDI DMI
SN74CBT3257 x3
LVDS/CRT
X'TAL SLG8LV595 DMI(x4)
SWITCH
14.318MHz CLOCK USB-8
LVDS/CCD/MIC
FDI DMI
INT_CRT
GENERATOR P3 Con.
INT_LVDS P23 Int. MIC P23
CLK
Display
SATA 0
C SATA - HDD C
P28 INT_HDMI PS8101

SATA
LS P24 HDMI Con.
SATA - ODD SATA 1
P28 EXT_LVDS P24
PCIE-6
USB Port x4 PCI-E x1
USB-1/3/9/11 MINI CARD
P33 USB Ibex Peak-M USB-13
WLAN
P27
PCH
USB-4 P8, 9, 10, 11, 12, 13
Bluetooth Con.
P33
PCIE-1 AR8151
X'TAL RJ45
32.768KHz GIGA LAN P25 P26
Cardreader AU6437 USB-12
P31
Cardreader control
P31 X'TAL
B X'TAL 25MHz 25MHz B
P8 BATTERY RTC
BOM Option Table
Reference Description
for UMA only SKU ISL88731A MAX8792ETD+T
IV@
for Switchable Graphic only SKU Azalia SPI SPI ROM (ME) Batery Charger +VGPU_CORE
SW@ IHDA P37 P43
P9
SP@ special case component LPC
* do not stuff RT8206B
LPC 3V/5V P38
ISL62881HRZ-T
Int. MIC ALC271 NPCE781 +VGFX_AXG P46
X'TAL
AUDIO CODEC EC P36 32.768KHz
P29 UP6111AQDD HPA00835RTER
P40 +1.8V P45
Speaker MIC JACK HP/SPDIF Power CIR Function Touch Pad

P30 P30 P30 Board Con. Board Board Con.
A Con. A
P33 P37 P33 P35
P42
K/B Con. W25X16VSS1G EM-6781-T3
HALL SENSOR Fan Driver
SPI FLASH
P35 P37 P24
(PWM Type) P35 Quanta Computer Inc.
PROJECT : ZR7
Size Document Number Rev
3B
Block Diagram
Date: Monday, February 22, 2010 Sheet 1 of 49
5 4 3 2 1
1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V
VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A
+3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU A
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
Thermal Follow Chart

Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION SIGNAL ACTIVE IN
B VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B
+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC

Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
Protection
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS
+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V

H_ORICHOT# PM_THRMTRIP# SYS_SHDN#
CORE PWR
CPU WIRE-AND SYS PWR
+5V_S5 +5V USB POWER S5_ON S0-S5 H/W Throttling
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0

SML1ALERT#
+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
PCH FAN Driver FAN
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0
+VGFX_AXG variation Internal GPU POWER GFX_ON S0

SM-Bus
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0
C C
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0

EC
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 CPUFAN#
+1.05V +1.05V PCH CORE POWER MAINON S0
+VCC_CORE variation CPU CORE POWER VRON S0
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0
+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable
+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable
+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable
+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable
+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable
+1V +1V DP/PEG POWER PG_1V_EN Discrete enable
D D
Quanta Computer Inc.

PROJECT : ZR7
3B
PWR Status & GPU PWR CRL & THRM
1 2 3 4 5 6 7 8
5 4 3 2 1
CLK GEN.
L40
595@PBY160808T-181Y-N/2A/180ohm_6 150mA(30mil) L36
+1.5V +1.5V_CLK 80mA(20mil) PBY160808T/2A/180ohm_6
+VDDIO_CLK +1.05V
C697 C698 C719
D 11/19 Change U39 PN. C696 C702 C695 C700 D
.1u/16V_4 .1u/16V_4 .1u/16V_4
R617 .1u/16V_4 .1u/16V_4 10u/Y5V_8 10u/Y5V_8
*585@0_6 U39
Place each 0.1uF cap as close as
1 VDD_DOT possible to each VDD IO pin. Place
17 VDD_SRC VDD_SRC_I/O 15 the 10uF caps on the VDD_IO plane.
L41 24 18
BLM18AG601SN1D/200mA/600ohm_6 VDD_CPU VDD_CPU_I/O
20mil 5 VDD_27
+3V_CLK 29 3
+3V
CLK_SDATA
VDD_REF DOT_96
DOT_96# 4
CLK_BUF_DREFCLK
CLK_BUF_DREFCLK#
10
10
9/16
31 SDA
C723 C494 C720 CLK_SCLK 32 6 27M_CLK 18
SCL 27M CLK_VGA_27M_SS R595 *ES@33_4
27M_SS 7 CLK_27M_SS 18
4.7u/10V_8 .1u/16V_4 .1u/16V_4 C718 *ES@10p/50V/COG_4
R598 33_4 CPU_SEL 30 10
10 CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_PCIE_3GPLL 10
SRC_1#/SATA# 11 CLK_BUF_PCIE_3GPLL# 10
SRC_2 13 CLK_BUF_DREFSSCLK 10
SRC_2# 14 CLK_BUF_DREFSSCLK# 10
C707 33p/50V_4 XTAL_IN 28 XTAL_IN
C C
XTAL_OUT 27 16 R579 10K_4 +3V
Y5 XTAL_OUT *CPU_STOP#
14.318MHz 2 VSS_DOT CPU_1 20 T46
8 VSS_27 CPU_1# 19 T45
9 VSS_SATA CPU_0 23 CLK_BUF_BCLK 10
C701 33p/50V_4 12 22
VSS_SRC CPU_0# CLK_BUF_BCLK# 10
21 VSS_CPU
26 25 CK_PWRGD_R
VSS_REF CKPWRGD/PD#
IDT: AL003197001 (ICS9LVS3197AKLFT) 33 GND
Realtek: AL000890000 (RTM890N-632-GRT)
Silego: AL000595000 (SLG8LV595VTR) ICS9LVS3197AKLFT/SLG8LV595V
+3V
CPU_CLK select SMBus CLK Enable +3V
B B
+1.05V
R406 R578
1K/F_4
2
R599 2.2K_4
*10K_4
3 1 CLK_SDATA CLK_SDATA 14,15,27 CK_PWRGD_R
10 ICH_SMBDATA
3
CPU_SEL Q27 Q48
2N7002D 2N7002D
R603 C722 39 VR_PWRGD_CK505# 2 R577

+3V 100K/F_4
10K_4 *10p/50V/COG_4
1
R407
2
2.2K_4
A A
0 1
3 1 CLK_SCLK
10 ICH_SMBCLK
Q28
CLK_SCLK 14,15,27
CPU_SEL CPU0/1=133MHz CPU0/1=100MHz
2N7002D
(default) PROJECT : ZR7
3B
Clock Generator
5 4 3 2 1
5 4 3 2 1
AR@ --> ARD CPU ARRANDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI)

CF@ --> CFD CPU ARRANDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
ES@ --> External VGA SKU AR@ --> ARD CPU
Processor Compensation Signals CF@ --> CFD CPU
U37A U37B
B26 R497 49.9/F_4 R523 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
A26 A16 CLK_CPU_BCLK 11
PEG_ICOMPO BCLK
MISC
A24 B27 R522 20/F_4 H_COMP2 AT24 B16
8 DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK# CLK_CPU_BCLK# 11
C23 A25 R498 750/F_4
8 DMI_TXN1 DMI_RX#[1] PEG_RBIAS
CLOCKS
B22 PEG_RXN[0..15] 16 R123 49.9/F_4 H_COMP1 G16 AR30
8 DMI_TXN2 DMI_RX#[2] PEG_RXN0 COMP1 BCLK_ITP T30
8 DMI_TXN3 A21 K35 AT30 T34
D DMI_RX#[3] PEG_RX#[0] PEG_RXN1 R520 49.9/F_4 H_COMP0 BCLK_ITP# D
J34 AT26
PEG_RX#[1] PEG_RXN2 COMP0
8 DMI_TXP0 B24 J33 E16 CLK_PCIE_3GPLL 10
DMI_RX[0] PEG_RX#[2] PEG_RXN3 PEG_CLK
8 DMI_TXP1 D23 G35 D16 CLK_PCIE_3GPLL# 10
DMI_RX[1] PEG_RX#[3] PEG_CLK#
DMI
B23 G32 PEG_RXN4 AH24
8 DMI_TXP2 DMI_RX[2] PEG_RX#[4] PEG_RXN5 T40 SKTOCC# DPLL_REF_SSCLK_R
A22 F34 A18 R496 AR@0_4
8 DMI_TXP3 DMI_RX[3] PEG_RX#[5]
PEG_RX#[6]
F31 PEG_RXN6 PCIE 16X DPLL_REF_SSCLK
DPLL_REF_SSCLK#
A17 DPLL_REF_SSCLK#_R R500 AR@0_4
DPLL_REF_SSCLK 10
DPLL_REF_SSCLK# 10
D24 D35 PEG_RXN7 H_CATERR# AK14 R495 EV@0_4
8 DMI_RXN0 DMI_TX#[0] PEG_RX#[7]
Use reverse type CATERR#
THERMAL
G24 E33 PEG_RXN8 R499 EV@0_4
8 DMI_RXN1 DMI_TX#[1] PEG_RX#[8] PEG_RXN9
8 DMI_RXN2 F23 C33
DMI_TX#[2] PEG_RX#[9]
8 DMI_RXN3 H23
DMI_TX#[3] PEG_RX#[10]
D32
B32
PEG_RXN10
PEG_RXN11
(at GPU side) AT15
SM_DRAMRST#
F6 CPU_DDR3_DRAMRST# 35 Layout Note: Place
D25
PEG_RX#[11]
C31 PEG_RXN12 11 H_PECI PECI
AL1 SM_RCOMP_0 R182 100/F_4 these resistors
8 DMI_RXP0 DMI_TX[0] PEG_RX#[12] SM_RCOMP[0]
8 DMI_RXP1 F24
DMI_TX[1] PEG_RX#[13]
B28 PEG_RXN13
SM_RCOMP[1]
AM1 SM_RCOMP_1 R184 24.9/F_4 near Processor
E23 B30 PEG_RXN14 AN1 SM_RCOMP_2 R195 130/F_4
8 DMI_RXP2 DMI_TX[2] PEG_RX#[14] PEG_RXN15 H_PROCHOT# SM_RCOMP[2]
8 DMI_RXP3 G23 A31 39 H_PROCHOT# AN26
DMI_TX[3] PEG_RX#[15] PROCHOT#
PEG_RXP[0..15] 16 AN15 PM_EXTTS#0 14
PM_EXT_TS#[0]
DDR3
MISC
J35 PEG_RXP0 AP15 R224 10K_4
PEG_RX[0] PEG_RXP1 PM_EXT_TS#[1]
H34 +1.1V_VTT
PEG_RX[1] PEG_RXP2 R210 10K_4
H33 11 PM_THRMTRIP# AK15
PEG_RX[2] PEG_RXP3 THERMTRIP#
8 FDI_TXN0 E22 F35 PM_EXTTS#1 15
FDI_TX#[0] PEG_RX[3] PEG_RXP4
8 FDI_TXN1 D21 G33
FDI_TX#[1] PEG_RX[4] PEG_RXP5
8 FDI_TXN2 D19 E34 AT28 T27
FDI_TX#[2] PEG_RX[5] PEG_RXP6 PRDY# XDP_PREQ#
8 FDI_TXN3 D18 F32 AP27 T102
FDI_TX#[3] PEG_RX[6] PEG_RXP7 PREQ#
8 FDI_TXN4 G21 D34
FDI_TX#[4] PEG_RX[7]
PCI EXPRESS -- GRAPHICS
E19 F33 PEG_RXP8 AN28 XDP_TCLK
8 FDI_TXN5 FDI_TX#[5] PEG_RX[8] PEG_RXP9 H_CPURST# TCK XDP_TMS T31
8 FDI_TXN6 F21 B33 AP26 AP28 T37
FDI_TX#[6] PEG_RX[9] RESET_OBS# TMS
Intel(R) FDI
PWR MANAGEMENT
G18 D31 PEG_RXP10 AT27 XDP_TRST#
8 FDI_TXN7 FDI_TX#[7] PEG_RX[10] TRST# T103
JTAG & BPM

A32 PEG_RXP11
PEG_RX[11]
PEG_RX[12]
C30 PEG_RXP12
PEG_RXP13
ES@ --> External VGA SKU 8 PM_SYNC AL15
PM_SYNC TDI
AT29 XDP_TDI_R
XDP_TDO_R T106
8 FDI_TXP0 D22 A28 AR27 T104
FDI_TX[0] PEG_RX[13] PEG_RXP14 TDO XDP_TDI_M
8 FDI_TXP1 C21 B29 AR29 T105
FDI_TX[1] PEG_RX[14] PEG_RXP15 TDI_M XDP_TDO_M
8 FDI_TXP2 D20 A30 PEG_TXN[0..15] 16 AN14 AP29 T107
FDI_TX[2] PEG_RX[15] VCCPWRGOOD_1 TDO_M
8 FDI_TXP3 C18
FDI_TX[3] CPEG_TXN0 C245 ES@.1u/10V_4 PEG_TXN0 H_DBR#_R R229 *SHORT_4
8 FDI_TXP4 G22 L33 AN25 XDP_DBRST# 8
C FDI_TX[4] PEG_TX#[0] CPEG_TXN1 C635 ES@.1u/10V_4 PEG_TXN1 DBR# C
8 FDI_TXP5 E20 M35 11 H_PWRGOOD AN27
FDI_TX[5] PEG_TX#[1] CPEG_TXN2 PEG_TXN2 VCCPWRGOOD_0
8 FDI_TXP6 F20
FDI_TX[6] PEG_TX#[2]
M33 C248 ES@.1u/10V_4 1/7 modify.
G19 M30 CPEG_TXN3 C232 ES@.1u/10V_4 PEG_TXN3 AJ22 XDP_OBS0
8 FDI_TXP7 FDI_TX[7] PEG_TX#[3] CPEG_TXN4 PEG_TXN4 BPM#[0] XDP_OBS1 T26
L31 C235 ES@.1u/10V_4 AK13 AK22
FDI_FSYNC0_R PEG_TX#[4] CPEG_TXN5 PEG_TXN5 8,35 PM_DRAM_PWRGD SM_DRAMPWROK BPM#[1] XDP_OBS2 T29
F17 K32 C230 ES@.1u/10V_4 AK24
FDI_FSYNC1_R FDI_FSYNC[0] PEG_TX#[5] CPEG_TXN6 PEG_TXN6 BPM#[2] XDP_OBS3 T24
E17 M29 C236 ES@.1u/10V_4 AJ24
FDI_FSYNC[1] PEG_TX#[6] CPEG_TXN7 PEG_TXN7 H_VTTPWRGD BPM#[3] XDP_OBS4 T32
J31 C221 ES@.1u/10V_4 AM15 AJ25
FDI_INT_R PEG_TX#[7] CPEG_TXN8 PEG_TXN8 VTTPWRGOOD BPM#[4] XDP_OBS5 T38
C17 K29 C627 ES@.1u/10V_4 AH22
FDI_INT PEG_TX#[8] CPEG_TXN9 PEG_TXN9 BPM#[5] XDP_OBS6 T33
H30 C618 ES@.1u/10V_4 AK23
FDI_LSYNC0_R PEG_TX#[9] CPEG_TXN10 PEG_TXN10 BPM#[6] XDP_OBS7 T39
F18 H29 C620 ES@.1u/10V_4 AM26 AH23
FDI_LSYNC1_R FDI_LSYNC[0] PEG_TX#[10] CPEG_TXN11 PEG_TXN11 T28 TAPPWRGOOD BPM#[7] T41
D17 F29 C607 ES@.1u/10V_4
FDI_LSYNC[1] PEG_TX#[11] CPEG_TXN12 C622 ES@.1u/10V_4 PEG_TXN12
E28
PEG_TX#[12] CPEG_TXN13 C609 ES@.1u/10V_4 PEG_TXN13 R220 1.5K/F_4 CPU_PLTRST#
D29 AL14
PEG_TX#[13] CPEG_TXN14 C624 ES@.1u/10V_4 PEG_TXN14 10,11,16,25,27,31,36 PLTRST# RSTIN#
D27
PEG_TX#[14] CPEG_TXN15 PEG_TXN15
PEG_TX#[15]
C26 C611 ES@.1u/10V_4 PEG_TXP[0..15] 16 SI 2/5
Modified R211
L34 CPEG_TXP0 C238 ES@.1u/10V_4 PEG_TXP0 750/F_4 Clarksfield/Auburndale
PEG_TX[0] CPEG_TXP1 C634 ES@.1u/10V_4 PEG_TXP1
M34
M32
L30
M31
K31
M28
PEG_TX[6] CPEG_TXP7 C220 ES@.1u/10V_4 PEG_TXP7 R278 AR@0_4 FDI_FSYNC0_R
H31 8 FDI_FSYNC0
PEG_TX[7] CPEG_TXP8 C628 ES@.1u/10V_4 PEG_TXP8 R545 AR@0_4 FDI_FSYNC1_R
K28
PEG_TX[8]
PEG_TX[9]
G30 CPEG_TXP9
CPEG_TXP10
C619
C621
ES@.1u/10V_4
ES@.1u/10V_4
PEG_TXP9
PEG_TXP10
8 FDI_FSYNC1
R543 AR@0_4 FDI_INT_R
AR@ --> ARD CPU
G29
PEG_TX[10]
PEG_TX[11]
F28 CPEG_TXP11
CPEG_TXP12
C608
C623
ES@.1u/10V_4
ES@.1u/10V_4
PEG_TXP11
PEG_TXP12
8 FDI_INT
R546 AR@0_4 FDI_LSYNC0_R
CF@ --> CFD CPU
E27 8 FDI_LSYNC0
PEG_TX[12] CPEG_TXP13 C610 ES@.1u/10V_4 PEG_TXP13 R544 AR@0_4 FDI_LSYNC1_R
D28 8 FDI_LSYNC1
C27
PEG_TX[14] CPEG_TXP15 C612 ES@.1u/10V_4 PEG_TXP15 R277 EV@1K_4
C25
PEG_TX[15] R561 EV@1K_4
R556 EV@1K_4
B R563 EV@1K_4 B
Clarksfield/Auburndale R559 EV@1K_4
VTT Rail Values are

Thermaltrip protect VTT PWR_Good Processor pull-up Arrandale VTT=1.05V +1.1V_VTT
JTAG MAPPING 2/4 modify.
Clarksfield VTT=1.1V
XDP_TDI_R XDP_TDI
XDP_TDO R529 51/F_4 R538 *SHORT_4
+1.1V_VTT H_CATERR# R174 49.9/F_4 XDP_TDO_M XDP_TDO
H_PROCHOT# R521 68_4 R536 *0_4
H_CPURST# R233 *68_4
+3V XDP_TMS R232 *51_4 R535

3
XDP_TDI_R R537 *51_4 *SHORT_4

XDP_PREQ# R527 *51_4
XDP_TDI_M
2 Q22 XDP_TCLK R213 *51/F_4 R534 *0_4
8,39 DELAY_VR_PWRGOOD XDP_TRST# XDP_TDO_R
R524 51/F_4
FDV301N C383 R528 *SHORT_4
.1u/10V_4
1
Scan Chain STUFF -> R535, R538, R528

5
R226 +1.5V_CPUVDDQ (Default) NO STUFF -> R536, R534

1K_4 36 MPWROK 2 R223
4 H_VTTPWRGD
1 CPU Only STUFF -> R538, R536
2K/F_4 NO STUFF -> R535, R534, R528
U20 R214
3
2
A R209 1.1K/F_4 A
Q21 TC7SH08FU 1K_4 GMCH Only STUFF -> R534, R528
11 PM_THRMTRIP#
PM_THRMTRIP# 1 3 MMBT3904 SYS_SHDN# 38,46
PM_DRAM_PWRGD NO STUFF -> R535, R536, R538
Use a voltage divider with VDDQ (1.5 V)
pull-up 56ohm close to PCH R212 rail (ON in S3) and resistor combination
3K/F_4 of 1.1K/F (to VDDQ)/3K/F (to GND) to
convert to processor VTT level.
Note: CRB uses a 3.3 V (always ON) rail
with 1 k and 3 k combination. PROJECT : ZR7
3B
ARRANDALE/CLARKSFIELD 1/4
5 4 3 2 1
5 4 3 2 1
ARRANDALE/CLARKSFIELD PROCESSOR (DDR3) U37D
U37C
15 M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 15

SB_CK#[0] W9 M_B_CLK0# 15
M_B_DQ0 B5 M3
SB_DQ[0] SB_CKE[0] M_B_CKE0 15
M_B_DQ1 A5
M_B_DQ2 SB_DQ[1]
SA_CK[0] AA6 M_A_CLK0 14 C3 SB_DQ[2]
AA7 M_B_DQ3 B3 V7
D SA_CK#[0] M_A_CLK0# 14 SB_DQ[3] SB_CK[1] M_B_CLK1 15 D
P7 M_B_DQ4 E4 V6
14 M_A_DQ[63:0] SA_CKE[0] M_A_CKE0 14 SB_DQ[4] SB_CK#[1] M_B_CLK1# 15
M_A_DQ0 A10 M_B_DQ5 A6 M2 M_B_CKE1 15
M_A_DQ1 SA_DQ[0] M_B_DQ6 SB_DQ[5] SB_CKE[1]
C10 SA_DQ[1] A4 SB_DQ[6]
M_A_DQ2 C7 M_B_DQ7 C4
M_A_DQ3 SA_DQ[2] M_B_DQ8 SB_DQ[7]
A7 SA_DQ[3] SA_CK[1] Y6 M_A_CLK1 14 D1 SB_DQ[8]
M_A_DQ4 B10 Y5 M_A_CLK1# 14 M_B_DQ9 D2
M_A_DQ5 SA_DQ[4] SA_CK#[1] M_B_DQ10 SB_DQ[9]
D10 SA_DQ[5] SA_CKE[1] P6 M_A_CKE1 14 F2 SB_DQ[10] SB_CS#[0] AB8 M_B_CS#0 15
M_A_DQ6 E10 M_B_DQ11 F1 AD6
SA_DQ[6] SB_DQ[11] SB_CS#[1] M_B_CS#1 15
M_A_DQ7 A8 M_B_DQ12 C2
D8 SA_DQ[8] F5 SB_DQ[13]
M_A_DQ9 F10 AE2 M_A_CS#0 14 M_B_DQ14 F3
M_A_DQ10 SA_DQ[9] SA_CS#[0] M_B_DQ15 SB_DQ[14]
E6 SA_DQ[10] SA_CS#[1] AE8 M_A_CS#1 14 G4 SB_DQ[15] SB_ODT[0] AC7 M_B_ODT0 15
M_A_DQ11 F7 M_B_DQ16 H6 AD1 M_B_ODT1 15
M_A_DQ12 SA_DQ[11] M_B_DQ17 SB_DQ[16] SB_ODT[1]
E9 SA_DQ[12] G2 SB_DQ[17]
M_A_DQ13 B7 M_B_DQ18 J6
E7 SA_DQ[14] SA_ODT[0] AD8 M_A_ODT0 14 J3 SB_DQ[19]
M_A_DQ15 C6 AF9 M_B_DQ20 G1
SA_DQ[15] SA_ODT[1] M_A_ODT1 14 SB_DQ[20] M_B_DM[7:0] 15
M_A_DQ16 H10 M_B_DQ21 G5 D4 M_B_DM0
M_A_DQ17 SA_DQ[16] M_B_DQ22 SB_DQ[21] SB_DM[0] M_B_DM1
G8 SA_DQ[17] J2 SB_DQ[22] SB_DM[1] E1
M_A_DQ18 K7 M_B_DQ23 J1 H3 M_B_DM2
J8 SA_DQ[19] J5 SB_DQ[24] SB_DM[3] K1
M_A_DQ20 G7 M_B_DQ25 K2 AH1 M_B_DM4
G10 SA_DQ[21] M_A_DM[7:0] 14 L3 SB_DQ[26] SB_DM[5] AL2
M_A_DQ22 J7 B9 M_A_DM0 M_B_DQ27 M1 AR4 M_B_DM6
M_A_DQ23 SA_DQ[22] SA_DM[0] M_A_DM1 M_B_DQ28 SB_DQ[27] SB_DM[6] M_B_DM7
J10 SA_DQ[23] SA_DM[1] D7 K5 SB_DQ[28] SB_DM[7] AT8
M_A_DQ24 L7 H7 M_A_DM2 M_B_DQ29 K4
M_A_DQ25 SA_DQ[24] SA_DM[2] M_A_DM3 M_B_DQ30 SB_DQ[29]
M6 SA_DQ[25] SA_DM[3] M7 M4 SB_DQ[30]
M_A_DQ26 M8 AG6 M_A_DM4 M_B_DQ31 N5
M_A_DQ27 SA_DQ[26] SA_DM[4] M_A_DM5 M_B_DQ32 SB_DQ[31]
L9 SA_DQ[27] SA_DM[5] AM7 AF3 SB_DQ[32]
C M_A_DQ28 L6 AN10 M_A_DM6 M_B_DQ33 AG1 C
M_A_DQ29 SA_DQ[28] SA_DM[6] M_A_DM7 M_B_DQ34 SB_DQ[33] M_B_DQS#0 M_B_DQS#[7:0] 15
K8 SA_DQ[29] SA_DM[7] AN13 AJ3 SB_DQ[34] SB_DQS#[0] D5
M_A_DQ30 N8 M_B_DQ35 AK1 F4 M_B_DQS#1
M_A_DQ31 SA_DQ[30] M_B_DQ36 SB_DQ[35] SB_DQS#[1] M_B_DQS#2
P9 SA_DQ[31] AG4 SB_DQ[36] SB_DQS#[2] J4
M_A_DQ32 AH5 M_B_DQ37 AG3 L4 M_B_DQS#3
M_A_DQ33 SA_DQ[32] M_B_DQ38 SB_DQ[37] SB_DQS#[3] M_B_DQS#4
AF5 SA_DQ[33] M_A_DQS#[7:0] 14 AJ4 SB_DQ[38] SB_DQS#[4] AH2
DDR SYSTEM MEMORY - B

M_A_DQ34 AK6 C9 M_A_DQS#0 M_B_DQ39 AH4 AL4 M_B_DQS#5
SA_DQ[34] SA_DQS#[0] SB_DQ[39] SB_DQS#[5]
DDR SYSTEM MEMORY A
M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ40 AK3 AR5 M_B_DQS#6

M_A_DQ36 SA_DQ[35] SA_DQS#[1] M_A_DQS#2 M_B_DQ41 SB_DQ[40] SB_DQS#[6] M_B_DQS#7
AF6 SA_DQ[36] SA_DQS#[2] J9 AK4 SB_DQ[41] SB_DQS#[7] AR8
M_A_DQ37 AG5 N9 M_A_DQS#3 M_B_DQ42 AM6
M_A_DQ38 SA_DQ[37] SA_DQS#[3] M_A_DQS#4 M_B_DQ43 SB_DQ[42]
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AN2 SB_DQ[43]
M_A_DQ39 AJ6 AK9 M_A_DQS#5 M_B_DQ44 AK5
M_A_DQ40 SA_DQ[39] SA_DQS#[5] M_A_DQS#6 M_B_DQ45 SB_DQ[44]
AJ10 SA_DQ[40] SA_DQS#[6] AP11 AK2 SB_DQ[45]
M_A_DQ41 AJ9 AT13 M_A_DQS#7 M_B_DQ46 AM4
M_A_DQ42 SA_DQ[41] SA_DQS#[7] M_B_DQ47 SB_DQ[46]
AL10 SA_DQ[42] AM3 SB_DQ[47] M_B_DQS[7:0] 15
M_A_DQ43 AK12 M_B_DQ48 AP3 C5 M_B_DQS0
M_A_DQ44 SA_DQ[43] M_B_DQ49 SB_DQ[48] SB_DQS[0] M_B_DQS1
AK8 SA_DQ[44] AN5 SB_DQ[49] SB_DQS[1] E3
M_A_DQ45 AL7 M_B_DQ50 AT4 H4 M_B_DQS2
SA_DQ[45] M_A_DQS[7:0] 14 SB_DQ[50] SB_DQS[2]
M_A_DQ46 AK11 C8 M_A_DQS0 M_B_DQ51 AN6 M5 M_B_DQS3
M_A_DQ47 SA_DQ[46] SA_DQS[0] M_A_DQS1 M_B_DQ52 SB_DQ[51] SB_DQS[3] M_B_DQS4
AL8 SA_DQ[47] SA_DQS[1] F9 AN4 SB_DQ[52] SB_DQS[4] AG2
M_A_DQ48 AN8 H9 M_A_DQS2 M_B_DQ53 AN3 AL5 M_B_DQS5
M_A_DQ49 SA_DQ[48] SA_DQS[2] M_A_DQS3 M_B_DQ54 SB_DQ[53] SB_DQS[5] M_B_DQS6
AM10 SA_DQ[49] SA_DQS[3] M9 AT5 SB_DQ[54] SB_DQS[6] AP5
M_A_DQ50 AR11 AH8 M_A_DQS4 M_B_DQ55 AT6 AR7 M_B_DQS7
M_A_DQ51 SA_DQ[50] SA_DQS[4] M_A_DQS5 M_B_DQ56 SB_DQ[55] SB_DQS[7]
AL11 SA_DQ[51] SA_DQS[5] AK10 AN7 SB_DQ[56]
M_A_DQ52 AM9 AN11 M_A_DQS6 M_B_DQ57 AP6
M_A_DQ53 SA_DQ[52] SA_DQS[6] M_A_DQS7 M_B_DQ58 SB_DQ[57]
AN9 SA_DQ[53] SA_DQS[7] AR13 AP8 SB_DQ[58]
M_A_DQ54 AT11 M_B_DQ59 AT9
AP12 SA_DQ[55] AT7 SB_DQ[60]
M_A_DQ56 AM12 M_B_DQ61 AP9
B
AN12 SA_DQ[57] M_A_A[15:0] 14 AR10 SB_DQ[62] M_B_A[15:0] 15 B
M_A_DQ58 AM13 Y3 M_A_A0 M_B_DQ63 AT10 U5 M_B_A0
M_A_DQ59 SA_DQ[58] SA_MA[0] M_A_A1 SB_DQ[63] SB_MA[0] M_B_A1
AT14 SA_DQ[59] SA_MA[1] W1 SB_MA[1] V2
M_A_DQ60 AT12 AA8 M_A_A2 T5 M_B_A2
M_A_DQ61 SA_DQ[60] SA_MA[2] M_A_A3 SB_MA[2] M_B_A3
AL13 SA_DQ[61] SA_MA[3] AA3 SB_MA[3] V3
M_A_DQ62 AR14 V1 M_A_A4 R1 M_B_A4
M_A_DQ63 SA_DQ[62] SA_MA[4] M_A_A5 SB_MA[4] M_B_A5
AP14 SA_DQ[63] SA_MA[5] AA9 15 M_B_BS#0 AB1 SB_BS[0] SB_MA[5] T8
V8 M_A_A6 W5 R2 M_B_A6
SA_MA[6] 15 M_B_BS#1 SB_BS[1] SB_MA[6]
T1 M_A_A7 R7 R6 M_B_A7
SA_MA[7] 15 M_B_BS#2 SB_BS[2] SB_MA[7]
Y9 M_A_A8 R4 M_B_A8
SA_MA[8] M_A_A9 SB_MA[8] M_B_A9
14 M_A_BS#0 AC3 SA_BS[0] SA_MA[9] U6 SB_MA[9] R5
AB2 AD4 M_A_A10 AC5 AB5 M_B_A10
14 M_A_BS#1 SA_BS[1] SA_MA[10] 15 M_B_CAS# SB_CAS# SB_MA[10]
U7 T2 M_A_A11 Y7 P3 M_B_A11
14 M_A_BS#2 SA_BS[2] SA_MA[11] 15 M_B_RAS# SB_RAS# SB_MA[11]
U3 M_A_A12 AC6 R3 M_B_A12
SA_MA[12] 15 M_B_WE# SB_WE# SB_MA[12]
AG8 M_A_A13 AF7 M_B_A13
SA_MA[13] M_A_A14 SB_MA[13] M_B_A14
SA_MA[14] T3 SB_MA[14] P5
AE1 V9 M_A_A15 N1 M_B_A15
14 M_A_CAS# SA_CAS# SA_MA[15] SB_MA[15]
14 M_A_RAS# AB3 SA_RAS#
14 M_A_WE# AE9 SA_WE#
Clarksfield/Auburndale Clarksfield/Auburndale
A A
Channel A DQ[11,15,19,32,35,42,46,48,54,60], DM[5] Channel B DQ[11,16,18,19,36,42,51,55,56,57,60,61,62]
Requires minimum 12mils spacing Requires minimum 12mils spacing
with all other signals, including data signals. with all other signals, including data signals.

PROJECT : ZR7
3B
5 4 3 2 1
5 4 3 2 1
AR@ --> ARD CPU ARRANDALE/CLARKSFIELD PROCESSOR (POWER) ARRANDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)
CF@ --> CFD CPU VTT Rail Values are
Arrandale VTT=1.05V
U37F
Clarksfield VTT=1.1V AR@ --> ARD CPU
CPU Core Power
CF@ --> CFD CPU
+VGFX_AXG
+VCC_CORE
+1.1V_VTT U37G
ARD:48A 18A
CFD:52A
22A AT21
AT19
VAXG1
AR22 VCC_AXG_SENSE 44
D C310 22U/6.3V_8 VAXG2 VAXG_SENSE D
SENSE
LINES
AG35 VCC1 VTT0_1 AH14 AT18 VAXG3 VSSAXG_SENSE AT22 VSS_AXG_SENSE 44
C661 22U/6.3V_8 AG34 AH12 AT16
C314 22U/6.3V_8 VCC2 VTT0_2 VAXG4
AG33 VCC3 VTT0_3 AH11 AR21 VAXG5
C249 22U/6.3V_8 AG32 AH10 C655 10U/6.3V_8 AR19
C648 22U/6.3V_8 VCC4 VTT0_4 C652 10U/6.3V_8 + VAXG6
AG31 VCC5 VTT0_5 J14 AR18 VAXG7
C653 22U/6.3V_8 AG30 J13 C638 10U/6.3V_8 C667 C325 C324 AR16 AM22 GFX_VID0 44
C650 22U/6.3V_8 VCC6 VTT0_6 C328 10U/6.3V_8 AR@330u/2V_7343 AR@22u/6.3V_8 AR@22u/6.3V_8 VAXG8 GFX_VID[0]
AG29 VCC7 VTT0_7 H14 AP21 VAXG9 GFX_VID[1] AP22 GFX_VID1 44
C358 22U/6.3V_8 C660 10U/6.3V_8
GRAPHICS VIDs
AG28 VCC8 VTT0_8 H12 AP19 VAXG10 GFX_VID[2] AN22 GFX_VID2 44
C318 22U/6.3V_8 AG27 G14 C640 10U/6.3V_8 AP18 AP23 GFX_VID3 44
C644 22U/6.3V_8 VCC9 VTT0_9 C639 10U/6.3V_8 VAXG11 GFX_VID[3]
AG26 VCC10 VTT0_10 G13 AP16 VAXG12 GFX_VID[4] AM23 GFX_VID4 44
C268 22U/6.3V_8 AF35 G12 C662 22U/6.3V_8 AN21 AP24 GFX_VID5 44
VCC11 VTT0_11 VAXG13 GFX_VID[5]
GRAPHICS
C332 22U/6.3V_8 AF34 G11 C616 22U/6.3V_8 AN19 AN24 GFX_VID6 44
C296 10U/6.3V_8 VCC12 VTT0_12 C288 22U/6.3V_8 VAXG14 GFX_VID[6]
AF33 VCC13 VTT0_13 F14 AN18 VAXG15
C300 10U/6.3V_8 AF32 F13 AN16
C283 10U/6.3V_8 VCC14 VTT0_14 VAXG16
AF31 VCC15 VTT0_15 F12 C251 AM21 VAXG17 GFX_VR_EN AR25 GFX_ON 44
C651 10U/6.3V_8 AF30 F11 AM19 AT25 GFX_DPRSLPVR 44 ARD:3A
C642 10U/6.3V_8 VCC16 VTT0_16 VAXG18 GFX_DPRSLPVR
+
AF29 VCC17 VTT0_17 E14 AM18 VAXG19 GFX_IMON AM24 GFX_IMON 44
C659 10U/6.3V_8 AF28 VCC18 VTT0_18 E12 + AM16 VAXG20
CFD:6A
C654 10U/6.3V_8 AF27 D14 C666 C326 C327 AL21 R236 EV@1K_4
C362 10U/6.3V_8 VCC19 VTT0_19 330u/2V_7343 AR@330u/2V_7343 AR@10u/6.3V_8 AR@10u/6.3V_8 VAXG21 +1.5V_CPUVDDQ
AF26 VCC20 VTT0_20 D13 AL19 VAXG22
C645 10U/6.3V_8 AD35 D12 AL18 CF@ --> CFD CPU
1.1V RAIL POWER

C322 10U/6.3V_8 VCC21 VTT0_21 VAXG23
AD34 VCC22 VTT0_22 D11 AL16 VAXG24
C323 10U/6.3V_8 AD33 C14 AK21 AJ1
C281 10U/6.3V_8 VCC23 VTT0_23 VAXG25 VDDQ1
AD32 VCC24 VTT0_24 C13 AK19 VAXG26 VDDQ2 AF1
C647 10U/6.3V_8 AD31 C12 AK18 AE7
- 1.5V RAILS
C284 10U/6.3V_8 VCC25 VTT0_25 VAXG27 VDDQ3 C337 C246 C252 C341
AD30 VCC26 VTT0_26 C11 Add it for discrete only AK16 VAXG28 VDDQ4 AE4
C273 10U/6.3V_8 AD29 B14 AJ21 AC1
C658 10U/6.3V_8 VCC27 VTT0_27 VAXG29 VDDQ5 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
AD28 VCC28 VTT0_28 B12 AJ19 VAXG30 VDDQ6 AB7
C308 .1u/10V_4 AD27 A14 R215 EV@0_4 AJ18 AB4
C258 .1u/10V_4 VCC29 VTT0_29 VAXG31 VDDQ7
AD26 VCC30 VTT0_30 A13 AJ16 VAXG32 VDDQ8 Y1
AC35 VCC31 VTT0_31 A12 AH21 VAXG33 VDDQ9 W7
+
POWER
C272 330u/2V_7343 AC34 A11 AH19 W4
C VCC32 VTT0_32 VAXG34 VDDQ10 C
AC33 VCC33 AH18 VAXG35 VDDQ11 U1
+
C304 330u/2V_7343 AC32 +1.1V_VTT AH16 T7 C340 C331 C271 + C257

VCC34 VAXG36 VDDQ12
AC31 VCC35 VDDQ13 T4
AC30 AF10 P1 1U/6.3V_4 22U/6.3V_8 22U/6.3V_8 330u/2V_7343
VCC36 VTT0_33 VDDQ14
AC29 VCC37 VTT0_34 AE10 VTT Rail Values are VDDQ15 N7
AC28 VCC38 VTT0_35 AC10 VDDQ16 N4
+1.1V_VTT Arrandale VTT=1.05V
CPU CORE SUPPLY
DDR3
AC27 AB10 C239 22U/6.3V_8 L1
VCC39 VTT0_36 VDDQ17
AC26 VCC40 VTT0_37 Y10 Clarksfield VTT=1.1V J24 VTT1_45 VDDQ18 H1
FDI
AA35 W10 C240 22U/6.3V_8 J23
VCC41 VTT0_38 VTT1_46
AA34 VCC42 VTT0_39 U10 H25 VTT1_47
AA33 VCC43 VTT0_40 T10
AA32 VCC44 VTT0_41 J12
AA31 J11 1/7 modify. C242 C646 P10 +1.1V_VTT
VCC45 VTT0_42 VTT0_59
AA30 VCC46 VTT0_43 J16 +VTT_43 R125 *SHORT_4 22u/6.3V_8 22u/6.3V_8
VTT0_60 N10
AA29 VCC47 VTT0_44 J15 +VTT_44 R129 *SHORT_4
VTT0_61 L10 C641 10U/6.3V_8
AA28 K10 C643 10U/6.3V_8
AA27
VCC48
VCC49
(15mils) VTT0_62
VTT Rail Values are
AA26 VCC50
Y35 C211 Arrandale VTT=1.05V
VCC51 1u/10V_4
Y34 VCC52 Clarksfield VTT=1.1V
1.1V
Y33 VCC53 VTT1_63 J22
Y32 K26 J20 C636 22U/6.3V_8
VCC54 VTT1_48 VTT1_64 C637 22U/6.3V_8
Y31 VCC55 J27 VTT1_49 VTT1_65 J18
PEG & DMI

Y30 VCC56 J26 VTT1_50 VTT1_66 H21
Y29 C309 C649 C241 C297 J25 H20
VCC57 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 VTT1_51 VTT1_67
Y28 VCC58 H27 VTT1_52 VTT1_68 H19
Y27 VCC59 G28 VTT1_53
Y26 VCC60 G27 VTT1_54
V35 AN33 H_PSI# H_PSI# 39 G26
VCC61 PSI# VTT1_55
V34 F26 0.6A
POWER
VCC62 VTT1_56
V33 VCC63 E26 VTT1_57 VCCPLL1 L26 +1.8V
1.8V
V32 AK35 H_VID0 H_VID0 39 E25 L27
B VCC64 VID[0] H_VID1 VTT1_58 VCCPLL2 C243 22U/6.3V_8 B
V31 VCC65 VID[1] AK33 H_VID1 39 VCCPLL3 M26
V30 AK34 H_VID2 H_VID2 39 C244 4.7U/6.3V_6
VCC66 VID[2] H_VID3 C204 2.2U/6.3V_6
V29 VCC67 VID[3] AL35 H_VID3 39
CPU VIDS
V28 AL33 H_VID4 H_VID4 39 C210 1U/6.3V_4

VCC68 VID[4] H_VID5 C209 1U/6.3V_4
V27 VCC69 VID[5] AM33 H_VID5 39
V26 AM35 H_VID6 H_VID6 39
VCC70 VID[6] H_DPRSLPVR
U35 VCC71 PROC_DPRSLPVR AM34 H_DPRSLPVR 39
U34 VCC72
U33 Clarksfield/Auburndale
VCC73
U32 VCC74
U31 G15 H_VTTVID1 T12
VCC75 VTT_SELECT
U30 VCC76
U29 VCC77 H_VTTVID1=Low, 1.1V
U28 VCC78
U27 H_VTTVID1=High, 1.05V
VCC79
U26 VCC80 1
VTT Rail Values are
R35 H_VID0 R539 1K_4 +1.1V_VTT
VCC81 R540 *1K/F_4 Arrandale VTT=1.05V
R34 VCC82
R33 1 H_VID1 R541 1K_4 Clarksfield VTT=1.1V
VCC83 R542 *1K/F_4
R32 VCC84 ISENSE AN35 I_MON 39
R31 1 H_VID2 R240 1K_4
VCC85 R239 *1K/F_4
R30 VCC86
R29 R178 100/F_4 +VCC_CORE
0 H_VID3 R532 *1K/F_4
VCC87 R533 1K_4
R28 AJ34
SENSE LINES
VCC88 VCC_SENSE VCCSENSE 39

R27 AJ35 0 H_VID4 R235 *1K/F_4
VCC89 VSS_SENSE VSSSENSE 39
R26 R234 1K_4
VCC90 R181 100/F_4 1 H_VID5 R526 1K_4
P35 VCC91
P34 B15 VTT_SENSE T98 R519 *1K/F_4
VCC92 VTT_SENSE VSS_SENSE_VTT 0 H_VID6 R530 *1K/F_4
P33 VCC93 VSS_SENSE_VTT A15 T100
P32 R531 1K_4
VCC94 1 H_DPRSLPVR R244 1K_4
P31 VCC95
P30 R243 *1K/F_4
A VCC96 0 H_PSI# R525 *1K/F_4 A
P29 VCC97
P28 R518 1K_4
VCC98
P27 VCC99
P26 VCC100
Note: HFM_VID : Max 1.4V
For Validating IMVP VR R6451 should be STUFF
and R2N1 NO_STUFF LFM_VID : Min 0.65V
PROJECT : ZR7
Clarksfield/Auburndale Size Document Number Rev
3B
ARRANDALE/CLARKSFIELD 3/4 (PWR)
5 4 3 2 1
5 4 3 2 1
ARRANDALE/CLARKSFIELD PROCESSOR (GND) ARRANDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

U37H U37I U37E
AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AT17 AE33 AJ12
VSS2 VSS82 RSVD33
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162 AP25 RSVD1
AR26 AE30 K6 AL25 AH25
VSS5 VSS85 VSS163 RSVD2 RSVD34
AR24 AE29 K3 AL24 AK26
AR23 AE28 J32 AL22
VSS7 VSS87 VSS165 RSVD4
AR20 VSS8 VSS88 AE27 J30 VSS166 AJ33 RSVD5 RSVD36 AL26
AR17 VSS9 VSS89 AE26 J21 VSS167 AG9 RSVD6 RSVD_NCTF_37 AR2
AR15 AE6 J19 M27
D VSS10 VSS90 VSS168 RSVD7 D
AR12 AD10 H35 L28 AJ26
AR9 AC8 H32 14,35 VREF_DQ_DIMM0 J17 AJ27
VSS12 VSS92 VSS170 SA_DIMM_VREF RSVD39
AR6 VSS13 VSS93 AC4 H28 VSS171 15,35 VREF_DQ_DIMM1 H17 SB_DIMM_VREF
AR3 VSS14 VSS94 AC2 H26 VSS172 G25 RSVD11
AP20 AB35 H24 G17
VSS15 VSS95 VSS173 RSVD12
AP17 AB34 H22 E31 AP1
VSS16 VSS96 VSS174 RSVD13 RSVD_NCTF_40
AP13 VSS17 VSS97 AB33 H18 VSS175 E30 RSVD14 RSVD_NCTF_41 AT2
AP10 AB32 H15
VSS18 VSS98 VSS176
AP7 AB31 H13 AT3
VSS19 VSS99 VSS177 RSVD_NCTF_42
AP4 AB30 H11 AR1
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181
AN23 VSS24 VSS104 AB26 G34 VSS182 RSVD45 AL28
AN20 AB6 G31 CFG0 AM30 AL29
VSS25 VSS105 VSS183 CFG[0] RSVD46
AN17 VSS26 VSS106 AA10 G20 VSS184 AM28 CFG[1] RSVD47 AP30
AM29 VSS27 VSS107 Y8 G9 VSS185 AP31 CFG[2] RSVD48 AP32
AM27 Y4 G6 CFG3 AL32 AL27
VSS28 VSS108 VSS186 CFG4 CFG[3] RSVD49
AM25 VSS29 VSS109 Y2 G3 VSS187 AL30 CFG[4] RSVD50 AT31
AM20 W35 F30 AM31 AT32
AM17 VSS31 VSS111 W34 F27 VSS189 AN29 CFG[6] RSVD52 AP33
AM14 W33 F25 CFG7 AM32 AR33
AM11 VSS33 VSS113 W32 F22 VSS191 AK32 CFG[8] RSVD_NCTF_54 AT33
AM8 W31 F19 AK31 AT34
RESERVED
VSS34 VSS114 VSS192 CFG[9] RSVD_NCTF_55
AM5 VSS35 VSS115 W30 F16 VSS193 AK28 CFG[10] RSVD_NCTF_56 AP35
AM2 VSS36 VSS116 W29 E35 VSS194 AJ28 CFG[11] RSVD_NCTF_57 AR35
AL34 W28 E32 AN30 AR32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E29
E24
VSS195
VSS196
VSS197
VSS AN32
AJ32
CFG[12]
CFG[13]
CFG[14]
RSVD58
AL20 VSS40 VSS120 W6 E21 VSS198 AJ29 CFG[15] RSVD_TP_59 E15

C AL17 VSS41 VSS121 V10 E18 VSS199 AJ30 CFG[16] RSVD_TP_60 F15 C
AL12 U8 E13 AK30 A2
VSS42 VSS122 VSS200 CFG[17] KEY
AL9 VSS43 VSS123 U4 E11 VSS201 H16 RSVD_TP_86 RSVD62 D15
AL6 VSS44 VSS124 U2 E8 VSS202 RSVD63 C15
AL3 VSS45 VSS125 T35 E5 VSS203 RSVD64 AJ15 T25
AK29 VSS46 VSS126 T34 E2 VSS204 VSS_NCTF1 AT35 RSVD65 AH15 T35
AK27 T33 D33 AT1
VSS47 VSS127 VSS205 VSS_NCTF2
AK25 T32 D30 AR34 T22 B19
VSS48 VSS128 VSS206 VSS_NCTF3 RSVD15
AK20 T31 D26 B34 T13 A19
AK17 T30 D9 B2 T14
NCTF
VSS50 VSS130 VSS208 VSS_NCTF5
AJ31 T29 D6 B1 T99 A20
AJ23 VSS52 VSS132 T28 D3 VSS210 VSS_NCTF7 A35 T97 B20 RSVD18
AJ20 T27 C34 AA5 M_A_CLK2 14
VSS53 VSS133 VSS211 RSVD_TP_66
AJ17 VSS54 VSS134 T26 C32 VSS212 U9 RSVD19 RSVD_TP_67 AA4 M_A_CLK2# 14
AJ14 T6 C29 T9 R8 M_A_CKE2 14
VSS55 VSS135 VSS213 RSVD20 RSVD_TP_68
AJ11 R10 C28 AD3 M_A_CS#2 14
AJ8 P8 C24 AC9 AD2 M_A_ODT2 14
AJ5 P4 C22 AB9 AA2 M_A_CLK3 14
AJ2 VSS59 VSS139 P2 C20 VSS217 RSVD_TP_72 AA1 M_A_CLK3# 14
AH35 N35 C19 R9 M_A_CKE3 14
AH34 N34 C16 AG7 M_A_CS#3 14
AH33 N33 B31 C1 AE3 M_A_ODT3 14
VSS62 VSS142 VSS220 RSVD_NCTF_23 RSVD_TP_75
AH32 VSS63 VSS143 N32 B25 VSS221 A3 RSVD_NCTF_24
AH31 VSS64 VSS144 N31 B21 VSS222
AH30 N30 B18 V4 M_B_CLK2 15
AH29 N29 B17 V5 M_B_CLK2# 15
AH28 N28 B13 N2 M_B_CKE2 15
AH27 VSS68 VSS148 N27 B11 VSS226 J29 RSVD26 RSVD_TP_79 AD5 M_B_CS#2 15
AH26 VSS69 VSS149 N26 B8 VSS227 J28 RSVD27 RSVD_TP_80 AD7 M_B_ODT2 15
AH20 N6 B6 W3 M_B_CLK3 15
B AH17 M10 B4 A34 W2 M_B_CLK3# 15 B
AH13 L35 A29 A33 N3 M_B_CKE3 15
AH9 L32 A27 AE5 M_B_CS#3 15
AH6 L29 A23 C35 AD9 M_B_ODT3 15
AH3 L8 A9 B35
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2 VSS AP34 T21
AF4 K34
VSS78 VSS158 AP34 can be NC on CRB; EDS/DG suggestion to GND
AF2 K33
VSS79 VSS159
AE35 K30
VSS80 VSS160
Clarksfield/Auburndale
Clarksfield/Auburndale Clarksfield/Auburndale
Processor Strapping VTT Rail Values are +1.1V_VTT

Arrandale VTT=1.05V
Clarksfield VTT=1.1V
1 0 DEFAULT CFG4
R185 3.01K/F_4 R183 *3.01K
CFG0 CFG0
R227 3.01K/F_4 R219 *3.01K_NC
(PCI-Epress Single PEG Bifurcation enabled 1
R198 *3.01K/F_4 CFG3 R192 3.01K/F_4
Configuration Select) Use reverse type
CFG3 CFG7
Normal Operation Lane Numbers Reversed R203 *3.01K/F_4
(PCI-Epress Static 1
A A
Lane Reversal)
CFG4 Enabled; An external Display port
(Embended Disabled; No Physical Display Port device is connected to the Embedded
attached to Embedded Diplay Port 1
Display Port Presence) Display port
The Clarkfield processor's PCI Express interface may not meet PCI Express 2.0 jitter Quanta Computer Inc.
specifications.
Intel recommends placing a 3.01K +/- 5% pull down resistor to VSS on CFG[7] pin for both rPGA PROJECT : ZR7
and BGA Size Document Number Rev
components. This pull down resistor should be removed when this issue is fixed. 3B
5 4 3 2 1
5 4 3 2 1
AR@ --> ARD CPU AR@ --> ARD CPU

CF@ --> CFD CPU IBEX PEAK-M (DMI,FDI,GPIO)
CF@ --> CFD CPU AR@ --> ARD CPU
IV@ --> iGPU only
Arrandale only IBEX PEAK-M (LVDS,DDI)
U40C
BA18 FDI_TXN0_R R567 AR@0_4
FDI_RXN0 FDI_TXN0 4
BC24 BH17 FDI_TXN1_R R554 AR@0_4 U40D
4 DMI_RXN0 DMI0RXN FDI_RXN1 FDI_TXN1 4
BJ22 BD16 FDI_TXN2_R R552 AR@0_4 INT_LVDS_BLON T48 BJ46
4 DMI_RXN1 DMI1RXN FDI_RXN2 FDI_TXN2 4 23 INT_LVDS_BLON L_BKLTEN SDVO_TVCLKINN
D AW20 BJ16 FDI_TXN3_R R565 AR@0_4 INT_LVDS_DIGON T47 BG46 D
4 DMI_RXN2 DMI2RXN FDI_RXN3 FDI_TXN3 4 23 INT_LVDS_DIGON L_VDD_EN SDVO_TVCLKINP
BJ20 BA16 FDI_TXN4_R R548 AR@0_4
4 DMI_RXN3 DMI3RXN FDI_RXN4 FDI_TXN4 4
BE14 FDI_TXN5_R R572 AR@0_4 Y48 BJ48
FDI_RXN5 FDI_TXN5 4 23 INT_LVDS_BRIGHT L_BKLTCTL SDVO_STALLN
BD24 BA14 FDI_TXN6_R R569 AR@0_4 BG48
4 DMI_RXP0 DMI0RXP FDI_RXN6 FDI_TXN6 4 SDVO_STALLP
BG22 BC12 FDI_TXN7_R R550 AR@0_4 AB48
4 DMI_RXP1 DMI1RXP FDI_RXN7 FDI_TXN7 4 23 INT_LVDS_EDIDCLK L_DDC_CLK
4 DMI_RXP2 BA20 DMI2RXP 23 INT_LVDS_EDIDDATA Y45 L_DDC_DATA SDVO_INTN BF45
BG20 BB18 FDI_TXP0_R R568 AR@0_4 BH45
4 DMI_RXP3 DMI3RXP FDI_RXP0 FDI_TXP0 4 SDVO_INTP
BF17 FDI_TXP1_R R555 AR@0_4 +3V R329 AR@10K_4 L_CTRL_CLK AB46
FDI_RXP1 FDI_TXP1 4 L_CTRL_CLK
BE22 BC16 FDI_TXP2_R R553 AR@0_4 R333 AR@10K_4 L_CTRL_DATA V48
4 DMI_TXN0 DMI0TXN FDI_RXP2 FDI_TXP2 4 L_CTRL_DATA
BF21 BG16 FDI_TXP3_R R564 AR@0_4
4 DMI_TXN1 DMI1TXN FDI_RXP3 FDI_TXP3 4
BD20 AW16 FDI_TXP4_R R549 AR@0_4 R307 AR@2.37K/F_4 LVD_IBG AP39 T51 SDVO_CTRLCLK
4 DMI_TXN2 DMI2TXN FDI_RXP4 FDI_TXP4 4 LVD_IBG SDVO_CTRLCLK SDVO_CTRLCLK 24
BE18 BD14 FDI_TXP5_R R573 AR@0_4 AP41 T53 SDVO_CTRLDAT
4 DMI_TXN3 DMI3TXN FDI_RXP5 FDI_TXP5 4 LVD_VBG SDVO_CTRLDATA SDVO_CTRLDAT 24
BB14 FDI_TXP6_R R570 AR@0_4
FDI_RXP6 FDI_TXP6 4
BD22 BD12 FDI_TXP7_R R551 AR@0_4 R300 AR@0_4 LVD_VREFH AT43
4 DMI_TXP0 DMI0TXP FDI_RXP7 FDI_TXP7 4 LVD_VREFH
BH21 R305 AR@0_4 LVD_VREFL AT42 BG44 T109
4 DMI_TXP1 DMI1TXP LVD_VREFL DDPB_AUXN
4 DMI_TXP2 BC20 DMI2TXP DDPB_AUXP BJ44 T108
4 DMI_TXP3 BD18 DMI3TXP FDI_INT BJ14 FDI_INT 4 DDPB_HPD AU38 INT_HDMI_HPD 24
LVDS
R557 *CF@1K_4 23 INT_TXLCLKOUT- INT_TXLCLKOUT- AV53
DMI
FDI
INT_TXLCLKOUT+ AV51 LVDSA_CLK# INT_HDMITX2N_R C408 IV@.1u/10V_4
FDI_FSYNC0 BF13 FDI_FSYNC0 4 23 INT_TXLCLKOUT+ LVDSA_CLK DDPB_0N BD42 INT_HDMITX2N 24
BH25 R276 *CF@1K_4 BC42 INT_HDMITX2P_R C409 IV@.1u/10V_4
DMI_ZCOMP DDPB_0P INT_HDMITX2P 24
BH13 INT_TXLOUT0- BB47 BJ42 INT_HDMITX1N_R C411 IV@.1u/10V_4
FDI_FSYNC1 FDI_FSYNC1 4 23 INT_TXLOUT0- LVDSA_DATA#0 DDPB_1N INT_HDMITX1N 24
Digital Display Interface

+1.05V R566 49.9/F_4 BF25 R560 *CF@1K_4 INT_TXLOUT1- BA52 BG42 INT_HDMITX1P_R C410 IV@.1u/10V_4
DMI_IRCOMP 23 INT_TXLOUT1- LVDSA_DATA#1 DDPB_1P INT_HDMITX1P 24
BJ12 INT_TXLOUT2- AY48 BB40 INT_HDMITX0N_R C453 IV@.1u/10V_4
FDI_LSYNC0 FDI_LSYNC0 4 23 INT_TXLOUT2- LVDSA_DATA#2 DDPB_2N INT_HDMITX0N 24
R562 *CF@1K_4 AV47 BA40 INT_HDMITX0P_R C452 IV@.1u/10V_4
LVDSA_DATA#3 DDPB_2P INT_HDMITX0P 24
BG14 AW38 INT_HDMICLK-_R C426 IV@.1u/10V_4
FDI_LSYNC1 FDI_LSYNC1 4 DDPB_3N INT_HDMICLK- 24
R558 *CF@1K_4 23 INT_TXLOUT0+ INT_TXLOUT0+ BB48 BA38 INT_HDMICLK+_R C425 IV@.1u/10V_4
LVDSA_DATA0 DDPB_3P INT_HDMICLK+ 24
23 INT_TXLOUT1+ INT_TXLOUT1+ BA50
INT_TXLOUT2+ LVDSA_DATA1
C 23 INT_TXLOUT2+ AY49 LVDSA_DATA2 C
AV48 Y49
10/20 Modify Unstuff LVDSA_DATA3 DDPC_CTRLCLK
AB49
DDPC_CTRLDATA
IV@ --> iGPU only
AP48 LVDSB_CLK#
XDP_DBRST# T6 J12 AP47 BE44
4 XDP_DBRST# SYS_RESET# WAKE# PCIE_WAKE# 25,27 LVDSB_CLK DDPC_AUXN
DDPC_AUXP BD44
AY53 LVDSB_DATA#0 DDPC_HPD AV40
SYS_PWROK M6 Y1 AT49
SYS_PWROK CLKRUN# / GPIO32 CLKRUN# 36 LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40
AT53 BD40
System Power Management
LVDSB_DATA#3 DDPC_0P
B17 PWROK DDPC_1N BF41
AY51 LVDSB_DATA0 DDPC_1P BH41
AT48 LVDSB_DATA1 DDPC_2N BD38
K5 P8 SUS_STAT# T49 AU50 BC38
MEPWROK SUS_STAT# / GPIO61 LVDSB_DATA2 DDPC_2P
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36
RSV_ICH_LAN_RST# A10 F3
LAN_RST# SUSCLK / GPIO62 ICH_SUSCLK 36
INT_CRT_BLU AA52 U50 AR@ --> ARD CPU
23 INT_CRT_BLU CRT_BLUE DDPD_CTRLCLK
D9 E4 SLP_S5#_R INT_CRT_GRN AB53 U52
4,35 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 T59 23 INT_CRT_GRN CRT_GREEN DDPD_CTRLDATA
INT_CRT_RED AD53
23 INT_CRT_RED CRT_RED
36 ICH_RSMRST# C16 RSMRST# SLP_S4# H7 SUSC# 36 DDPD_AUXN BC46

23 INT_CRT_DDCCLK V51 CRT_DDC_CLK DDPD_AUXP BD46 R place close to PCH
23 INT_CRT_DDCDAT V53 CRT_DDC_DATA DDPD_HPD AT38
SUS_PWR_ACK_R M1 P12 R596 AR@150_4 INT_CRT_BLU
SUS_PWR_DN_ACK / GPIO30 SLP_S3# SUSB# 36
B DDPD_0N BJ40 B
Y53 BG40 R587 AR@150_4 INT_CRT_GRN
23 INT_HSYNC CRT_HSYNC DDPD_0P
P5 K8 SLP_M# R354 *0_4 Y51 BJ38
36 DNBSWON# PWRBTN# SLP_M# 23 INT_VSYNC CRT_VSYNC DDPD_1N
BG38 R584 AR@150_4 INT_CRT_RED
DDPD_1P
CRT
DDPD_2N BF37
R345 *0_4 ACIN_R P7 N2 T55 DAC_IREF AD48 BH37
36 PCH_ACIN ACPRESENT / GPIO31 TP23 DAC_IREF DDPD_2P
AB51 CRT_IRTN DDPD_3N BE36
DDPD_3P BD36
PM_BATLOW# A6 BJ10 R317
BATLOW# / GPIO72 PMSYNCH PM_SYNC 4
1K/F_4 IbexPeak-M_R1P0
PM_RI# F14 F6 PM_SLP_LAN# T58

RI# SLP_LAN# / GPIO29
IbexPeak-M_R1P0
PCH Pull-high/low AR@ --> ARD CPU System PWR_OK

+3V +3V_S5
CLKRUN# R586 8.2K_4 PM_RI# R372 10K_4 +3V_S5

R132 AR@100K_4 INT_LVDS_BLON DELAY_VR_PWRGOOD need PU 2K to +3V.
XDP_DBRST# R352 1K_4 PM_BATLOW# R632 8.2K_4 C778 *.1u/10V_4
A
R119 AR@100K_4 INT_LVDS_DIGON
PU at power side A
PCIE_WAKE# R365 1K_4
5
ICH_RSMRST# R650 10K_4 1 DELAY_VR_PWRGOOD 4,39
PM_SLP_LAN# R369 *10K_4 SYS_PWROK 4
+3V RSV_ICH_LAN_RST# R662 10K_4 2
SUS_PWR_ACK_R R619 10K_4 U45
PWROK_EC 36
3
SYS_PWROK R670 10K_4 R695 100K_4
R160 AR@4.7K_4 SDVO_CTRLCLK ACIN_R R346 10K_4 TC7SH08FU
PROJECT : ZR7
R161 AR@4.7K_4 SDVO_CTRLDAT Size Document Number Rev
3B
IBEX PEAK-M 1/6
5 4 3 2 1
5 4 3 2 1
RTC Circuitry C758

15p/50V_4
+3VPCU +VCCRTC
2
1
CR1
Y6 R647
R676 20K/F_4 RTC_RST# 10M_4 U40A
VCCRTC_1 32.768KHZ
3
4
C757
1
RTC_X1 B13 D33
RTC_X2 RTCX1 FWH0 / LAD0 LPC_LAD0 27,36
BAT54C C768 J1 15p/50V_4 D13 B33
RTCX2 FWH1 / LAD1 LPC_LAD1 27,36
1u/10V_4 *SHORT_PAD C32
FWH2 / LAD2 LPC_LAD2 27,36
A32
2
FWH3 / LAD3 LPC_LAD3 27,36
RTC_RST# C14
RTCRST#
FWH4 / LFRAME# C34 LPC_LFRAME# 27,36
SRTC_RST# D17
D
R405 20K/F_4 SRTC_RST# SRTCRST# D
A34
RTC
LPC
R663 1M_4 SM_INTRUDER# LDRQ0# R327 10K_4
+VCCRTC A16 INTRUDER# LDRQ1# / GPIO23 F34 +3V
1
R677
1K_4 C784 C753 J2 PCH_INVRMEN A14 AB9
INTVRMEN SERIRQ IRQ_SERIRQ 36
1u/10V_4 1u/10V_4 *SHORT_PAD
2
HDA_SYNC (PCH strap pin) ACZ_BIT_CLK A30
HDA_BCLK
SATA0RXN AK7 SATA_RXN0 28
Internal weak pull-down ACZ_SYNC D29 AK6
HDA_SYNC SATA0RXP SATA_RXP0 28
VCCVRM=>+1.8V (default) AK11 SATA_TXN0_C C483 .01u/25V_4
SATA0TXN SATA_TXN0 28
VCCRTC_2 1 3 RTC_N01 R674 *22K/F_6 external pull-up SPKR P1 AK9 SATA_TXP0_C C484 .01u/25V_4 SATA_TXP0 28
+5V_S5 29 SPKR SPKR SATA0TXP
Q55 R673 VCCVRM=>+1.5V ACZ_RST# C30 HDA_RST#
SATA1RXN AH6 SATA_RXN1 28
*MMBT3904 *68.1K/F_4 AH5 SATA_RXP1 28
SATA1RXP SATA_TXN1_C C495 .01u/25V_4
G30 AH9 SATA_TXN1 28
2
29 PCH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA1TXN

BT1 RTC_N03 AH8 SATA_TXP1_C C487 .01u/25V_4
SATA1TXP SATA_TXP1 28
1 1 F30 HDA_SDIN1
2
2 SATA2RXN
AF11 10/20 Modify
R678 E32 AF9
IHDA
HDA_SDIN2 SATA2RXP
RTC_CONN AF7
*150K/F_6 SATA2TXN
F32 HDA_SDIN3 SATA2TXP AF6 Note:
SATA port2/3 may not be available on all PCH sku
AH3
ACZ_SDOUT SATA3RXN (HM55 support 3 port only)
B29 HDA_SDO SATA3RXP AH1
SATA3TXN AF3
1/7 Change P/N by ME. SATA3TXP AF1
PCH_GPIO33 H32
SATA
HDA_DOCK_EN# / GPIO33
SATA4RXN AD9
R652 *10K_4 PCH_GPIO13 J30 AD8
+3V_S5 HDA_DOCK_RST# / GPIO13 SATA4RXP
AD6
HDA Bus SATA4TXN
SATA4TXP AD5
M3 AD3
JTAG_TCK SATA5RXN
AD1
SATA5RXP
K3 JTAG_TMS SATA5TXN AB3
C
SATA5TXP AB1 C
K1 JTAG_TDI
JTAG
R653 33_4 ACZ_SYNC J2 AF16
29 PCH_AZ_CODEC_SYNC JTAG_TDO SATAICOMPO
J4 AF15 SATAICOMP R319 37.4/F_4
TRST# SATAICOMPI +1.05V
R659 33_4 ACZ_RST#
29 PCH_AZ_CODEC_RST#
R658 33_4 ACZ_SDOUT SPI_CLK_R BA2

29 PCH_AZ_CODEC_SDOUT SPI_CLK
SPI_CS0#_R AV3 SPI_CS0#
R575 *10K_4 SPI_CS1# AY3 T3
+3VPCU SPI_CS1# SATALED# SATA_ACT# 32
R654 33_4 ACZ_BIT_CLK
29 PCH_AZ_CODEC_BITCLK PCH_ODD_EN 28
SPI_SI_R AY1 Y9 R338 10K_4 +3V
SPI_MOSI SATA0GP / GPIO21
C759 11/5 R338 and R594
SPI
*27p/50V_4 SPI_SO_R AV1 V1 R594 10K_4
SPI_MISO SATA1GP / GPIO19 +3V Modify to 10K ohm.
IbexPeak-M_R1P0
PCH Strap Pin Configuration Table-1

INTVRMEN Integrated 1.05V VRM Enable / 1 = Integrated VRM is enabled
R685 330K_6 PCH_INVRMEN
Disable 0 = Integrated VRM is disabled +VCCRTC
SPI_MOSI TPM Functionality 1 = Enabled

R618 *1K_4 SPI_SI_R
Disable 0 = Disable +3V
PCH SPI
SPKR Reboot option at power-up 0 = Default Mode (Internal weak Pull-down)
R611 *1K/F_4SPKR
10/29 Modify P/N to 2M 1 = No Reboot Mode with TCO Disabled +3V
B
12/7 Modify P/N to 4M +3V
HDA_DOCK_EN Flash Descriptor
0 = Flash Descriptor Security will be overridden
1 = Security measure defined in the Flash
PCH_GPIO33
R370 *1K/F_4 12/1 Add by SPI ROM
B
#/GPIO33 Security Override Descriptor will be enabled.

R382 *10K_4 +3V +3V
U41
SPI_CS0#_R 1 8
SPI_CLK_R CE# VDD
6 SCK
SPI_SI_R 5 GNT0#, (0,0) = LPC (0,1) = Reserved NAND 10 PCI_GNT0# R360 *1K_4 PCI_GNT0# R708 1K_4
SPI_SO_R SI
2 7 R613 3.3K/F_4 Boot BIOS Strap
SO HOLD# GNT1# (1,0) = PCI (1,1) = SPI R363 *1K_4 PCI_GNT1# R709 1K_4
10 PCI_GNT1#
+3V R608 3.3K/F_4 3 4
WP# VSS C717 GNT2#/ ESI compatible mode is for server
W25X32QVSSIG .1u/10V_4 ESI Strap
GPIO53 platforms only R364 *1K/F_4
(Server Only) 10,23 PWM_SELECT#
GNT3#/ Top-Block 0 = Top Block Swap Mode

R628 *10K/F_4
SPI_CLK_R C463 *22p_4 GPIO55 Swap Override 1 = Default Mode (Internal pull-up) 10 PCI_GNT3#
IntelR Anti-Theft Technology

HDD Data Protection 1 = Enabled
NV_ALE R296 *1K/F_4
(Intel AT-d) Enable 0 = Disabled (Default) 10 NV_ALE +1.8V
NV_CLE DMI Termination DMI termination voltage. Weak

R295 *1K/F_4
Voltage internal pull-up. Do not pull low. 10 NV_CLE +1.8V
GPIO8 Reserved This signal has a weak internal pull up. 11 RSV_GPIO8 R380 10K_4 +3V_S5
NOTE: This signal should not be pulled low R371 *1K_4
0 = Intel ME Crypto Transport Layer Security

(TLS) cipher suite with no confidentiality
GPIO15 Reserved
A 1 = Intel ME Crypto Transport Layer Security 11 CR_WAKE# R341 1K_4 +3V_S5 A
(TLS) cipher suite with confidentiality
GPIO27 On-Die PLL Voltage 0 = Disables the VccVRM.

Regulator 1 = Enables the internal VccVRM to have
<internal weak pull-up> a clean supply for analog rails. 11 PCH_GPIO27 R324 *10K_4

PROJECT : ZR7
3B
IBEX PEAK-M 2/6
5 4 3 2 1
5 4 3 2 1
IV@ --> iGPU only

EV@ --> dGPU only
SW@ --> iGPU & dGPU Switch
U40B
U40E
H40 AY9 BG30 B9 RSV_SMBALERT#
AD0 NV_CE#0 25 PCIE_RX1- PERN1 SMBALERT# / GPIO11
N34 BD1 25 PCIE_RX1+ BJ30
AD1 NV_CE#1 C679 .1u/10V_4 PCIE_TXN1_C PERP1 ICH_SMBCLK
C44
AD2 NV_CE#2
AP15 GLAN 25 PCIE_TX1- BF29
PETN1 SMBCLK
H14 ICH_SMBCLK 3
A38 BD8 C680 .1u/10V_4 PCIE_TXP1_C BH29
AD3 NV_CE#3 25 PCIE_TX1+ PETP1
C36 C8 ICH_SMBDATA
AD4 SMBDATA ICH_SMBDATA 3
J34 AV9 AW30
AD5 NV_DQS0 PERN2
A40 BG8 BA30
AD6 NV_DQS1 PERP2 RSV_SML0ALERT#
D
D45
AD7 3G BC30
PETN2 SML0ALERT# / GPIO60
J14
D
E36 AP7 BD30
AD8 NV_DQ0 / NV_IO0 PETP2 SMB_CLK_ME0
H48 AP6 C6 SMB_CLK_ME0 25
AD9 NV_DQ1 / NV_IO1 11/18 Delete R597, C444,C445 for cancel 3G function. SML0CLK
E40 AT6 AU30
SMBus
AD10 NV_DQ2 / NV_IO2 PERN3 SMB_DATA_ME0
C40 AT9 AT30 G8 SMB_DATA_ME0 25
AD11 NV_DQ3 / NV_IO3 PERP3 SML0DATA
M48 BB1 AU32
AD12 NV_DQ4 / NV_IO4 PETN3
M45 AV6 AV32
AD13 NV_DQ5 / NV_IO5 PETP3 RSV_SML1ALERT# R336 *0_4
F53 BB3 M14 SML1ALERT# 11,34,36
AD14 NV_DQ6 / NV_IO6 SML1ALERT# / GPIO74
M40 BA4 BA32
AD15 NV_DQ7 / NV_IO7 PERN4
NVRAM
M43 BE4 BB32 E10 SMB_CLK_ME1
AD16 NV_DQ8 / NV_IO8 PERP4 SML1CLK / GPIO58
J36 BB6 BD32
AD17 NV_DQ9 / NV_IO9 PETN4 SMB_DATA_ME1
K48 BD6 BE32 G12
AD18 NV_DQ10 / NV_IO10 PETP4 SML1DATA / GPIO75
F40 BB7
PCI-E*
AD19 NV_DQ11 / NV_IO11
C42 BC8 BF33
AD20 NV_DQ12 / NV_IO12 PERN5 CL_CLK1
K46 BJ8 BH33 T13 CL_CLK1 27
AD21 NV_DQ13 / NV_IO13 PERP5 CL_CLK1
Controller
M51 BJ6 BG32 SW@ --> iGPU & dGPU Switch
AD22 NV_DQ14 / NV_IO14 PETN5 CL_DATA1
J52 BG6 BJ32 T11 CL_DATA1 27
AD23 NV_DQ15 / NV_IO15 PETP5 CL_DATA1
K51
Link
AD24 CL_RST1#
L34 BD3 NV_ALE 9 27 PCIE_RX6- BA34 T9 CL_RST1# 27
AD25 NV_ALE PERN6 CL_RST1#
F42 AY6 NV_CLE 9 27 PCIE_RX6+ AW34
AD26 NV_CLE C451 .1u/10V_4 PCIE_TXN6_C PERP6
J40
AD27 WLAN 27 PCIE_TX6- BC34
PETN6
G46 C450 .1u/10V_4 PCIE_TXP6_C BD34
AD28 27 PCIE_TX6+ PETP6
F44 AU2 NV_RCOMP R574 *32.4/F_4 H1 PEG_CLKREQ#_R R620 SW@0_4
AD29 NV_RCOMP PEG_A_CLKRQ# / GPIO47 PEG_CLKREQ# 16
M47 AT34
AD30 PERN7
PCI
H36 AV7 AU34
AD31 NV_RB# PERP7
AU36 AD43 CLK_PCIE_VGA# 16
PETN7 CLKOUT_PEG_A_N
J50 AY8 AV36 AD45 CLK_PCIE_VGA 16
C/BE0# NV_WR#0_RE# PETP7 CLKOUT_PEG_A_P
G42 AY5
C/BE1# NV_WR#1_RE#
H47 BG34 AN4 CLK_PCIE_3GPLL# 4
PEG
C/BE2# PERN8 CLKOUT_DMI_N
G34 AV11 BJ34 AN2 CLK_PCIE_3GPLL 4
C/BE3# NV_WE#_CK0 PERP8 CLKOUT_DMI_P
BF5 BG36
PCI_PIRQA# NV_WE#_CK1 PETN8
G38 BJ36
PCI_PIRQB# PIRQA# PETP8
H51 AT1 DPLL_REF_SSCLK# 4
PCI_PIRQC# PIRQB# CLKOUT_DP_N / CLKOUT_BCLK1_N
B37
PIRQC# USBP0N
H18 T57 Port1 and port9 can be used on debug mode CLKOUT_DP_P / CLKOUT_BCLK1_P
AT3 DPLL_REF_SSCLK 4
PCI_PIRQD# A44 J18 T52 AK48
PIRQD# USBP0P CLKOUT_PCIE0N
A18 USBP1- 33 AK47
USBP1N CLKOUT_PCIE0P
From CLK BUFFER

PCI_REQ0# F51 C18 MB USB AW24
C REQ0# USBP1P USBP1+ 33 CLKIN_DMI_N CLK_BUF_PCIE_3GPLL# 3 C
PCI_REQ1# A46 N20 T50 CLK_PCIE_REQ0# P9 BA24
REQ1# / GPIO50 USBP2N PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK_BUF_PCIE_3GPLL 3
dGPU_SELECT# B45 P20 T48
23 dGPU_SELECT# REQ2# / GPIO52 USBP2P
PCI_REQ3# M53 J20
REQ3# / GPIO54 USBP3N USBP3- 33
USBP3P
L20 USBP3+ 33 USB/B-USB1-3 AM43
CLKOUT_PCIE1N CLKIN_BCLK_N
AP3 CLK_BUF_BCLK# 3
9 PCI_GNT0# F48
GNT0# USBP4N
F20 USBP4- 33 EHCI1 AM45
CLKOUT_PCIE1P CLKIN_BCLK_P
AP1 CLK_BUF_BCLK 3
9 PCI_GNT1# K45
GNT1# / GPIO51 USBP4P
G20 USBP4+ 33 BLUETOOTH
F36 A20 CLK_PCIE_REQ1#_R U4
9,23 PWM_SELECT# GNT2# / GPIO53 USBP5N USBP5- 27 PCIECLKRQ1# / GPIO18
9 PCI_GNT3# H53
GNT3# / GPIO55 USBP5P
C20 USBP5+ 27 Reserve Touch Screen CLKIN_DOT_96N
F18 CLK_BUF_DREFCLK# 3
M22 E18 CLK_BUF_DREFCLK 3 11/27 Modify
PCI_PIRQE# USBP6N USB port6/7 may not be available on all PCH sku CLKIN_DOT_96P
B41 N22 27 CLK_PCH_SRC2# AM47
PCI_PIRQF# PIRQE# / GPIO2 USBP6P (HM55 support 12port only) CLKOUT_PCIE2N C699,C703 to 27pF
K53 B21 27 CLK_PCH_SRC2 AM48
PCI_PIRQG# PIRQF# / GPIO3 USBP7N CLKOUT_PCIE2P
A36 D21 AH13 CLK_BUF_DREFSSCLK# 3
PCI_PIRQH# PIRQG# / GPIO4 USBP7P R616 *SHORT_4 CLK_PCIE_REQ2#_R CLKIN_SATA_N / CKSSCD_N
A48 H22 USBP8- 23 27 PCIE_CLK_REQ2# N4 AH12 CLK_BUF_DREFSSCLK 3
PIRQH# / GPIO5 USBP8N PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P R699 EV@0_4
USBP8P
J22 USBP8+ 23 Camera
USB
27 PCI_RST# K6 E22 USBP9- 33

PCIRST# USBP9N
USBP9P
F22 USBP9+ 33 USB/B-USB1-2 AH42
CLKOUT_PCIE3N REFCLK14IN
P41 CLK_ICH_14M 3
PCI_SERR# E44 A22 AH41
SERR# USBP10N USBP10- 27 CLKOUT_PCIE3P
PCI_PERR# E50 C22 Touch Screen AR@27p/50V_4
PERR# USBP10P USBP10+ 27
G24 EHCI2 CLK_PCIE_REQ3# A8 J42 CLK_PCI_FB
USBP11N USBP11- 33 PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK
H24 USB/B-USB1-1 C699
USBP11+ 33
1
PCI_IRDY# USBP11P
A42 L24 USBP12- 31
PCI_PAR IRDY# USBP12N XTAL25_IN R581 Y4
T63 H44
PAR USBP12P
M24 USBP12+ 31 Card Reader AM51
CLKOUT_PCIE4N XTAL25_IN
AH51
PCI_DEVSEL# F46 A24 AM53 AH53 XTAL25_OUT AR@25MHz
DEVSEL# USBP13N USBP13- 27 CLKOUT_PCIE4P XTAL25_OUT
PCI_FRAME# C46 C24 Mini Card (WLAN) AR@1M_4
USBP13+ 27
2
FRAME# USBP13P CLK_PCIE_REQ4# XCLK_RCOMP R312 90.9/F_4 AR@27p/50V_4
M9 AF38
PCI_PLOCK# PCIECLKRQ4# / GPIO26 XCLK_RCOMP
D49
PLOCK# USB_BIAS R651 22.6/F_4 C703
B25 +1.05V
PCI_STOP# USBRBIAS# BOARD_ID1
D41 AJ50 T45
PCI_TRDY# STOP# CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
C48 D25 AJ52
TRDY# USBRBIAS CLKOUT_PCIE5P
ICH_PME# M7 CLK_PCIE_REQ5# H6 P43 BOARD_ID2 11/5 Add R699 connect
Clock Flex
T54 PME# PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65
N16 USB_OC0# XTAL25_IN to Gnd.
OC0# / GPIO59 USB_OC0# 33
PCI_PLTRST# D5 J16 USB_OC1#
PLTRST# OC1# / GPIO40 USB_OC1# 33
F16 USB_OC2# AK53 T42 BOARD_ID3
R612 22_4 CLK_LPC_DEBUG_C OC2# / GPIO41 USB_OC3#
T51 25 CLK_PCIE_LOM# CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66 11/18 Modify
27 CLK_LPC_DEBUG N52 L16 T53 25 CLK_PCIE_LOM AK51
CLK_PCI_PCCARD CLKOUT_PCI0 OC3# / GPIO42 USB_OC4_5# CLKOUT_PEG_B_P
T56 P53 E14 USB_OC4_5# 33
B R358 22_4 CLK_PCI_775_C CLKOUT_PCI1 OC4# / GPIO43 R591 *SHORT_4 PCIE_CLK_REQB# B
36 CLK_PCI_775 P46 G16 25 CLK_PCIE_LAN_REQ# P13 N50 dGPU_EDIDSEL# 23,24
CLK_PCI_FB R606 22_4 CLK_PCI_FB_C CLKOUT_PCI2 OC5# / GPIO9 USB_OC6# PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67
P51 F12 T62
CLKOUT_PCI3 OC6# / GPIO10 USB_OC7#
P48 T15 T61
CLKOUT_PCI4 OC7# / GPIO14 IbexPeak-M_R1P0 R349 10K_4 +3V
IbexPeak-M_R1P0
+3V_S5 +3V +3V +3V_S5

Main Board ID
R353 10K_4 CLK_PCIE_REQ0#
R634 10K_4 CLK_PCIE_REQ3# R374 *10K_4 BOARD_ID1 R355 10K_4
R357 10K_4 CLK_PCIE_REQ4# R387
R362 10K_4 CLK_PCIE_REQ5# R373 *10K_4 BOARD_ID2 R359 10K_4
2
R600 10K_4 PCIE_CLK_REQB# 2.2K_4
+3V_S5 R347 *10K_4 BOARD_ID3 R342 10K_4
RP1 1 3 SMB_CLK_ME1
36 2ND_MBCLK
USB_OC7# 6 5 11/18 Modify Q26
USB_OC6# 7 4 USB_OC0# +3V *2N7002D
USB_OC4_5# 8 3 USB_OC1#
9 2 USB_OC2# R700 0_4
+3V_S5
+3V_S5 10 1 USB_OC3# R390 10K_4 dGPU_SELECT#
+3V_S5
11/25 Modify.
8.2K_10P8R R593 10K_4 CLK_PCIE_REQ1#_R
R649 10K_4 RSV_SMBALERT#
C524 R385 10K_4 RSV_SML0ALERT# +3V +3V_S5
+3V R376 8.2K_4 PCI_PIRQE# R340 10K_4 RSV_SML1ALERT#
.1u/10V_4 RP4 R348 8.2K_4 PCI_PIRQF# R404 2.2K_4 ICH_SMBCLK
PCI_PIRQD# 6 5 R669 8.2K_4 PCI_PIRQG# R403 2.2K_4 ICH_SMBDATA R381
5
PCI_REQ1# 7 4 PCI_REQ3# R665 10K_4 PCIE_CLK_REQ2# R627 2.2K_4 SMB_CLK_ME0

PCI_PLTRST# 2 PCI_FRAME# 8 3 PCI_PIRQB# R622 2.2K_4 SMB_DATA_ME0 2.2K_4
2
4 PCI_TRDY# 9 2 PCI_REQ0#
PLTRST# 4,11,16,25,27,31,36
1 +3V 10 1 PCI_PIRQH#
A 1 3 SMB_DATA_ME1 A
36 2ND_MBDATA
U25 R389 8.2K_10P8R IV@ --> iGPU only EV@ --> dGPU only Q29
3
TC7SH08FU *2N7002D
100K_4
+3V R701 0_4
RP5
PCI_PIRQC# +3V_S5
6 5 11/25 Modify.
R388 *0_4 PCI_PIRQA# 7 4 PCI_PERR#
PCI_STOP# 8 3 PCI_PLOCK#
PCI_IRDY# 9 2 PCI_DEVSEL# R624 IV@10K_4 PEG_CLKREQ#_R R625 EV@10K/F_4
+3V 10 1 PCI_SERR# Quanta Computer Inc.
8.2K_10P8R
PROJECT : ZR7
3B
IBEX PEAK-M 3/6
5 4 3 2 1
5 4 3 2 1
+3V
IV@ --> iGPU only GPU RST#
EV@ --> dGPU only C596 *SW@.1u_4
SW@ --> iGPU & dGPU Switch
5
1
ES@ --> External VGA SKU 16 GPU_RST# 4
PLTRST# 4,10,16,25,27,31,36
2 dGPU_HOLD_RST#
IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)
3
U35
SW@ --> SW@TC7SH08FU R470
U40F SW@100K_4
D iGPU & dGPU D
BMBUSY# Y3 AH45
BMBUSY# / GPIO0 CLKOUT_PCIE6N
AH46
Switch
SIO_EXT_SMI# CLKOUT_PCIE6P
36 SIO_EXT_SMI# C38
TACH1 / GPIO1
SIO_EXT_SCI# D37
36 SIO_EXT_SCI# TACH2 / GPIO6
AF48
GPIO Pull-up/Pull-down +3V_S5
CLKOUT_PCIE7N
MISC
11/18 Modify BOARD_ID0 J32 AF47
TACH3 / GPIO7 CLKOUT_PCIE7P
RSV_GPIO8 F10 TP_PCH_GPIO28 R602 10K_4
9 RSV_GPIO8 GPIO8
LAN_DISABLE# K9 U2 GPIO45 R626 10K_4
LAN_PHY_PWR_CTRL / GPIO12 A20GATE SIO_A20GATE 36
CR_WAKE# T7 RST_GATE# R402 10K_4
9 CR_WAKE# GPIO15
11/27 Del R440 dGPU_HOLD_RST# GPIO57 R386 *10K_4
AA2 AM3 CLK_CPU_BCLK# 4
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N
18,36 dGPU_PWROK dGPU_PWROK F38 AM1 LAN_DISABLE# R356 10K_4
TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLK 4
GPIO22 Y7 BG10 EV@ --> dGPU only
SCLOCK / GPIO22 PECI H_PECI 4
GPIO
+3V
T60 H10 GPIO24 RCIN# T1 SIO_RCIN# 36
SIO_EXT_SMI# R401 10K_4
PCH_GPIO27 AB12 BE10
9 PCH_GPIO27 GPIO27 PROCPWRGD H_PWRGOOD 4
CPU
SIO_EXT_SCI# R660 10K_4
dGPU_PWR_EN# should be stable TP_PCH_GPIO28 V13 BD10 PCH_THRMTRIP#_R R286 56/F_4
GPIO28 THRMTRIP# PM_THRMTRIP# 4
before dGPU_VRON enable
STP_PCI# M11
10/19 dGPU_PWR_EN R326 EV@10K_4
STP_PCI# / GPIO34 R294 56/F_4
C +1.1V_VTT C
43,47 dGPU_VRON V6 SATACLKREQ# / GPIO35 SIO_RCIN# R605 10K_4
45 dGPU_PWR_EN dGPU_PWR_EN AB7 BA22 VTT Rail Values are
SATA2GP / GPIO36 TP1 SIO_A20GATE R604 10K_4
dGPU_PRSNT# AB13 AW22 Arrandale VTT=1.05V
SATA3GP / GPIO37 TP2 dGPU_HOLD_RST# R321 10K_4
10/19 Clarksfield VTT=1.1V 11/19 Modify.
GPIO38 V3 BB22
SLOAD / GPIO38 TP3 SATA5GP R325 10K_4
SAVE_LED# P3 AY45
SDATAOUT0 / GPIO39 TP4 GPIO22 R337 10K_4
GPIO45 H3 AY46
PCIECLKRQ6# / GPIO45 TP5 SAVE_LED# R610 10K_4
35 RST_GATE# F1 PCIECLKRQ7# / GPIO46 TP6 AV43
STP_PCI# R351 10K_4
SV_SET_UP AB6 AV45
SDATAOUT1 / GPIO48 TP7 GPIO38 R585 10K_4
10,34,36 SML1ALERT# R331 *SHORT_4 SATA5GP AA4 AF13
SATA5GP / GPIO49 TP8 BMBUSY# R328 8.2K_4
EC suggestion use GPIO49 for FAN control GPIO57 F8 M18
GPIO57 TP9 SV_SET_UP R332 10K_4
1/7 Modify.
N18
TP10 dGPU_PWROK R442 IV@10K_4
11/26 Modify.
A4 VSS_NCTF_1 TP11 AJ24
A49 11/19 Modify. BOARD_ID0 R667 10K_4
NCTF
VSS_NCTF_2
RSVD
SATA5GP / GPIO49 / TEMP_ALERT# is used to A5

VSS_NCTF_3 TP12
AK41
A50 R439 *10K_4
alert for EC when CPU or Graph/Memory A52
VSS_NCTF_4
AK42
VSS_NCTF_5 TP13
B controllers' temperature go out of limit. A53
VSS_NCTF_6 B
So connecting GPIO49 to EC and avoid this B2 M32
VSS_NCTF_7 TP14
B4 VSS_NCTF_8
pin to be used for other purpose B52 N32
VSS_NCTF_9 TP15
B53
VSS_NCTF_10
BE1
VSS_NCTF_11 TP16
M30 SV_SET_UP 1-X High = Strong (Default)
BE53
VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
BF53 GPIO57 stuff PD and not stuff PU for Intel suggestion at 6/1
VSS_NCTF_14
BH1 H12
VSS_NCTF_15 TP18
BH2
VSS_NCTF_16 GPIO57 R379 10K_4
BH52 AA23
VSS_NCTF_17 TP19 +3V
BH53 VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
BJ2
VSS_NCTF_20
BJ49 R320 IV@10K_4 dGPU_PRSNT# R316 ES@10K_4
VSS_NCTF_22
BJ5 AB42
VSS_NCTF_23 NC_3
BJ50
VSS_NCTF_24 dGPU always exist --> PD 10K
BJ53 VSS_NCTF_26
D1 VSS_NCTF_27 NC_5 T39 IV@ --> iGPU only ES@ --> External VGA SKU
D2
VSS_NCTF_28
D53
VSS_NCTF_29 TP_INT3_3V
E1 VSS_NCTF_30 INIT3_3V# P6 T47
E53 VSS_NCTF_31
Integrated Clock Chip Enable
C10
TP24 High = Disable
IbexPeak-M_R1P0 RSV_GPIO8
A A
Low = Enable

PROJECT : ZR7
3B
IBEX PEAK-M 4/6
5 4 3 2 1
5 4 3 2 1
VCCADAC= 69mA(15mils)
IBEX PEAK-M (POWER) U40G POWER PBY160808T/2A/180ohm_6
R315 *SHORT_8 +1.05V_VCCCORE_ICH AB24 AE50 +VCCA_DAC_1_2 L39 AR@ --> ARD CPU
+1.05V VCCCORE[1] VCCADAC[1] +3V
AB26
R314 *SHORT_8 AB28
VCCCORE[2]
AE52
CF@ --> CFD CPU
C498 C496 VCCCORE[3] VCCADAC[2] C713 C711 C714
AD26
VCCCORE[4]
CRT
AD28 AF53 VCCACLK= 52mA(15mils)
AR@ --> ARD CPU 10u/6.3V_8 1u/6.3V_4 AF26
VCCCORE[5]
VCCCORE[6]
VSSA_DAC[1] .01u/25V_4 10u/6.3V_6 .1u/10V_4 U40J POWER VCCIO = 3.208A(150mils)
VCC CORE
AF28 AF51 L35 *10uh_8
CF@ --> CFD CPU AF30
VCCCORE[7]
VCCCORE[8]
VSSA_DAC[2]
+1.05V +V1.1LAN_VCCA_CLK AP51 VCCACLK[1] VCCIO[5] V24 +1.05V
AF31
VCCCORE[9]
VCCALVDS= 1mA C692 *10u/6.3V_6
VCCIO[6]
V26
AH26 VCCALVDS +3V C694 *1u/6.3V_4 AP53 Y24 C507 1U/6.3V_4
VCCCORE(+1.05V) = 1.432A(80mils) VCCCORE[10] R322 AR@0_4 VCCACLK[2] VCCIO[7]
AH28 Y26
VCCCORE[11] VCCIO[8]
AH30 VCCCORE[12]
AH31 AH38 R313 C490 +1.05V R318 *0_6 +1.05V_VCCAUX AF23 V28 +3V_S5_VCCPUSB R384 *SHORT_8 +3V_S5
D VCCCORE[13] VCCALVDS VCCLAN[1] VCCSUS3_3[1] D
AJ30
VCCCORE[14] EV@0_4 AR@.1u/10V_4 VCCLAN = 320mA(30mils) VCCSUS3_3[2]
U28
AJ31 AH39 AF24 U26 C513 .1u/10V_4
VCCCORE[15] VSSA_LVDS VCCLAN[2] VCCSUS3_3[3]
VCCTX_LVDS= 59mA(15mils) VCCSUS3_3[4]
U24 C514 .1u/10V_4
R698 P28 C518 0.022U/16V_4
VCCTX_LVDS TP_PCH_VCCDSW VCCSUS3_3[5]
AP43 +1.8V 0_4 Y20 P26
VCCTX_LVDS[1] L26 DCPSUSBYP VCCSUS3_3[6]
AP45 N28
VCCTX_LVDS[2] AR@0.1UH_8 VCCSUS3_3[7]
AT46 N26
LVDS
R287 *SHORT_6 +1.05V_PCH_VCCDPLL_EXP AK24 VCCTX_LVDS[3] C480 C481 C482 C506 VCCSUS3_3[8]
+1.05V VCCIO[24] VCCTX_LVDS[4] AT45 AD38 VCCME[1] VCCSUS3_3[9] M28
R304 .1u/10V_4 M26
AR@.01u/25V_4 AR@.01u/25V_4 AR@22u/6.3V_8 VCCSUS3_3[10]
EV@0_4 AD39 L28
VCCSUS3_3 = 0.163A(20mils)
USB
+V1.1LAN_VCCAPLL_EXP VCCME[2] VCCSUS3_3[11]
40mA(15mils) +1.05V L23 *1uh_6 BJ24
VCCAPLLEXP VCCSUS3_3[12]
L26
VCC3_3[2] AB34 10/20 Change to 0.1uF AD41 VCCME[3] VCCSUS3_3[13] J28
C448 *10u/6.3V_6 J26
VCCSUS3_3[14]
AN20
VCCIO[25] VCC3_3[3]
AB35 VCC3_3 = 357mA(30mils) AF43
VCCME[4] VCCSUS3_3[15]
H28 R343 *SHORT_6 +1.05V
AN22 H26
HVCMOS
VCCIO[26] +3V_VCC_GIO VCCSUS3_3[16]
AN23 AD35 R339 *SHORT_6 VCCME(+1.05V) = 1.849A(100mils) AF41 G28
AN24
VCCIO[27]
VCCIO[28]
VCC3_3[4] +3V VCCME[5] VCCSUS3_3[17]
VCCSUS3_3[18] G26 V5REF_SUS< 1mA
AN26 C500 +1.05V R323 *SHORT_8 +1.05V_VCCEPW AF42 F28 R664 100/F_4 +5V_S5
VCCIO[29] VCCME[6] VCCSUS3_3[19]
VCCIO = 3.062A(150mils) AN28 VCCIO[30] VCCSUS3_3[20] F26
+1.05V BJ26 .1u/10V_4 R334 *SHORT_8 V39 E28 D18 RB500V-40 +3V_S5
Clock and Miscellaneous

BJ28 VCCIO[32] VCCSUS3_3[22] E26
AT26 VCCIO[33] V41 VCCME[8] VCCSUS3_3[23] C28
AT28 VCCIO[34] VCCSUS3_3[24] C26
AU26 C502 22U/6.3V_8 V42 B27 C762 .1u/10V_4
AU28 VCCIO[36]
VCCVRM= 196mA(15mils) VCCSUS3_3[26] A28
C479 10U/6.3V_8 AV26 C508 22U/6.3V_8 Y39 A26 10/20 Change to 0.1uF
C457 1U/6.3V_4 VCCIO[37] +VCCVRM R310 *SHORT_6 VCCME[10] VCCSUS3_3[27]
AV28 AT24
C470 1U/6.3V_4 AW26
VCCIO[38]
VCCIO[39]
VCCVRM[2] +V1.5S_1.8S
C504 1U/6.3V_4 Y41
VCCME[11] VCCSUS3_3[28]
U23 V5REF< 1mA
C493 1U/6.3V_4 AW28 R366 100/F_4 +5V
VCCIO[40]
DMI
C464 1U/6.3V_4 BA26 AT16 +VCCDMI R303 *SHORT_4 +1.1V_VTT VCCDMI= 61mA(15mils) C505 1U/6.3V_4 Y42 V23
VCCIO[41] VCCDMI[1] VCCME[12] VCCIO[56] D10 RB500V-40
BA28 +3V
VCCIO[42] V5REF_SUS
BB26 VCCIO[43] VCCDMI[2] AU16 V5REF_SUS F24
C C516 1U/6.3V_4 C
BB28 VCCIO[44] VTT Rail Values are
BC26 +VCCRTCEXT V9
VCCIO[45] Arrandale VTT=1.05V DCPRTC
PCI E*
BC28 C475 C509 .1u/10V_4
VCCIO[46] 1u/10V_4
BD26
VCCIO[47] Clarksfield VTT=1.1V
BD28 K49 V5REF
VCCIO[48] V5REF
BE26 AM16 AU24
PCI/GPIO/LPC
VCCIO[49] VCCPNAND[1] +V1.5S_1.8S VCCVRM[3]
BE28 AK16 VCCPNAND= 156mA(15mils)
VCCIO[50] VCCPNAND[2] +3V_VCCPPCI R361 *SHORT_6
BG26 VCCIO[51] VCCPNAND[3] AK20 VCC3_3[8] J38 +3V
BG28 AK19 VCCPNAND R291 *SHORT_8 +1.8V BB51
VCCIO[52] VCCPNAND[4] VCCADPLLA[1]
BH27 AK15 68mA(15mils) +V1.1LAN_VCCA_A_DPL BB53 L38 VCC3_3 = 0.357A(30mils)
VCCIO[53] VCCPNAND[5] C492 VCCADPLLA[2] VCC3_3[9] C517 .1u/10V_4
AK13
VCCPNAND[6]
AN30 VCCIO[54] VCCPNAND[7] AM12 VCC3_3[10] M36
NAND / SPI
AN31 AM13 .1u/10V_4 69mA(15mils) +V1.1LAN_VCCA_B_DPL BD51
VCCIO[55] VCCPNAND[8] VCCADPLLB[1]
AM15 BD53 N36
VCCPNAND[9] VCCADPLLB[2] VCC3_3[11] C515 .1u/10V_4
+3V R306 *SHORT_6 +3V_VCCA3GBG AN35 +1.05V AH23 P36
VCC3_3[1] VCCIO[21] VCC3_3[12]
AJ35
37mA(15mils) VCCIO[22]
VCCIO = 3.062A(150mils) AH35
VCCIO[23] VCC3_3[13]
U35
+V1.5S_1.8S R308 *SHORT_6 +VCCAFDI_VRM AT22
VCCVRM[1]
VCCME3_3= 85mA(15mils) C491 1U/6.3V_4 AF34
+V1.1LAN_VCCAPLL_FDI VCCIO[2]
+1.05V L22 *1uH_6 BJ18
VCCFDIPLL VCCME3_3[1]
AM8 C488 1U/6.3V_4
VCC3_3[14]
AD13 31mA(15mils)
AM9 +3V_VCCME_SPI R309 *SHORT_6 +3V C489 1U/6.3V_4 AH34
VCCME3_3[2] VCCIO[3]
FDI
+1.05V_VCCDPLL_FDI AM23 AP11 +V1.1LAN_VCCAPLL L37 *10uh_8 +1.05V

C447 VCCIO[1] VCCME3_3[3] C486
VCCME3_3[4] AP9 AF32 VCCIO[4]
*10u/6.3V_6 AK3
.1u/10V_4 +VCCSST VCCSATAPLL[1] C705 C704
V12 DCPSST VCCSATAPLL[2] AK1
C510 .1u/10V_4 *1u/6.3V_4 *10u/6.3V_6
IbexPeak-M_R1P0
VCCIO = 3.062A(150mils)
+V1.1LAN_INT_VCCSUS Y22
C501 .1u/10V_4 DCPSUS +V1.1LAN_VCC_SATA R335 *SHORT_1206+1.05V
AH22
R311 *SHORT_6 VCCIO[9]
B
+1.05V B
VCCSUS3_3 = 163mA(20mils) P18 VCCSUS3_3[29] VCCVRM[4] AT20 +V1.5S_1.8S C497
1u/10V_4
VCCVRM=196mA(15mils) HDA_SYNC (PCH strap pin) +3V_S5 R378 *SHORT_6 +3V_S5_VCCPSUS U19
SATA
VCCSUS3_3[30]
PCI/GPIO/LPC
VCCIO[10] AH19
+1.8V R289 *SHORT_6 +V1.5S_1.8S Internal weak pull-down U20
VCCSUS3_3[31]
VCCVRM=>+1.8V (default) VCCIO[11] AD20
external pull-up U22
C456 C455 C511 .1u/10V_4 VCCSUS3_3[32]
AF22
.1u/10V_4 .1u/10V_4 VCCVRM=>+1.5V VCC3_3 = 0.357A(30mils) VCCIO[12]
VRM enable by strap pin GPIO27 VCCIO[13] AD19
R330 *SHORT_6 +3V_VCCPCORE V15 AF20
which supply clean 1.05V for +3V VCC3_3[5] VCCIO[14]
VCCIO[15] AF19
[VCCACLK,VCCAPLLEXP,VCCFDIPLL,VCCSATAPLL] V16 AH20
VCC3_3[6] VCCIO[16]
Y16 VCC3_3[7] VCCIO[17] AB19
V_CPU_IO >1mA(15mils) C503 .1u/10V_4
VCCIO[18]
AB20
+1.05V L33 10uh_8 +V1.1LAN_VCCA_A_DPL AB22
VCCIO[19]
VTT Rail Values are AD22
+ *SHORT_6 +VTT_VCCPCPU VCCIO[20]
C685 Arrandale VTT=1.05V +1.1V_VTT R299 AT18 V_CPU_IO[1]
VCCME = 1.849A(100mils)
C691 R571 AA34 +1.05V_VCCEPW
CPU
Clarksfield VTT=1.1V VCCME[13]
220u_3528 1u/10V_4 *0_8 C471 4.7U/6.3V_6 Y34
C473 .1u/10V_4 VCCME[14]
AU18 Y35
C474 .1u/10V_4 V_CPU_IO[2] VCCME[15] R344 *0_4
AA35 +1.5V_SUS
VCCME[16]
L34 10uh_8 +V1.1LAN_VCCA_B_DPL
RTC
A12 L30 +V3.3A_1.5A_HDA_IO R350 *SHORT_4
+VCCRTC VCCRTC VCCSUSHDA +3V_S5
HDA
C671 +
C674 VCCRTC= 2mA(15mils) C754 .1u/10V_4 VCCSUSHDA= 6mA(15mils)
220u_3528 1u/10V_4 C743 .1u/10V_4 IbexPeak-M_R1P0 C519
1u/10V_4
A 10/22 Stuff A

PROJECT : ZR7
3B
IBEX PEAK-M 5/6
5 4 3 2 1
5 4 3 2 1
U40I
AY7 H49
IBEX PEAK-M (GND) B11
B15
VSS[159]
VSS[160]
VSS[259]
VSS[260] H5
J24
VSS[161] VSS[261]
B19 K11
VSS[162] VSS[262]
B23 K43
VSS[163] VSS[263]
B31 VSS[164] VSS[264] K47
B35 K7
VSS[165] VSS[265]
B39 VSS[166] VSS[266] L14
B43 L18
D VSS[167] VSS[267] D
B47 VSS[168] VSS[268] L2
B7 L22
VSS[169] VSS[269]
BG12 L32
VSS[170] VSS[270]
BB12 L36
U40H VSS[171] VSS[271]
BB16 L40
VSS[172] VSS[272]
AB16 VSS[0] BB20 VSS[173] VSS[273] L52
BB24 M12
VSS[174] VSS[274]
AA19 VSS[1] VSS[80] AK30 BB30 VSS[175] VSS[275] M16
AA22 VSS[3] VSS[82] AK32 BB38 VSS[177] VSS[277] N38
AM19 AK34 BB42 M34
VSS[4] VSS[83] VSS[178] VSS[278]
AA28 AK43 BC10 M46
VSS[7] VSS[86] VSS[181] VSS[281]
AA30 VSS[8] VSS[87] AK46 BC14 VSS[182] VSS[282] M49
AA31 AK49 BC18 M5
VSS[9] VSS[88] VSS[183] VSS[283]
AA32 VSS[10] VSS[89] AK5 BC2 VSS[184] VSS[284] M8
AB11 VSS[11] VSS[90] AK8 BC22 VSS[185] VSS[285] N24
AB15 AL2 BC32 P11
VSS[12] VSS[91] VSS[186] VSS[286]
AB23 VSS[13] VSS[92] AL52 BC36 VSS[187] VSS[287] AD15
AB30 VSS[14] VSS[93] AM11 BC40 VSS[188] VSS[288] P22
AB31 VSS[15] VSS[94] BB44 BC44 VSS[189] VSS[289] P30
AB32 AD24 BC52 P32
VSS[16] VSS[95] VSS[190] VSS[290]
AB39 VSS[17] VSS[96] AM20 BH9 VSS[191] VSS[291] P34
AB43 VSS[18] VSS[97] AM22 BD48 VSS[192] VSS[292] P42
AB8 AM28 BE12 R2
VSS[21] VSS[100] VSS[195] VSS[295]
C AC2 VSS[22] VSS[101] BA42 BE16 VSS[196] VSS[296] R52 C
AC52 VSS[23] VSS[102] AM30 BE20 VSS[197] VSS[297] T12
AD11 VSS[24] VSS[103] AM31 BE24 VSS[198] VSS[298] T41
AD16 AM34 BE34 T49
VSS[26] VSS[105] VSS[200] VSS[300]
AD30 AM38 BE42 T8
VSS[28] VSS[107] VSS[202] VSS[302]
AD31 VSS[29] VSS[108] AM39 BE46 VSS[203] VSS[303] U30
AD32 VSS[30] VSS[109] AM42 BE48 VSS[204] VSS[304] U31
AD34 AU20 BE50 U32
VSS[31] VSS[110] VSS[205] VSS[305]
AU22 VSS[32] VSS[111] AM46 BE6 VSS[206] VSS[306] U34
AD42 VSS[33] VSS[112] AV22 BE8 VSS[207] VSS[307] P38
AD46 AM49 BF3 V11
VSS[34] VSS[113] VSS[208] VSS[308]
AD49 VSS[35] VSS[114] AM7 BF49 VSS[209] VSS[309] P16
AD7 VSS[36] VSS[115] AA50 BF51 VSS[210] VSS[310] V19
AE2 BB10 BG18 V20
VSS[37] VSS[116] VSS[211] VSS[311]
AE4 AN32 BG24 V22
VSS[38] VSS[117] VSS[212] VSS[312]
AF12 AN50 BG4 V30
VSS[39] VSS[118] VSS[213] VSS[313]
Y13 VSS[40] VSS[119] AN52 BG50 VSS[214] VSS[314] V31
AH49 VSS[41] VSS[120] AP12 BH11 VSS[215] VSS[315] V32
AU4 AP42 BH15 V34
VSS[42] VSS[121] VSS[216] VSS[316]
AF35 AP46 BH19 V35
VSS[43] VSS[122] VSS[217] VSS[317]
AP13 AP49 BH23 V38
VSS[44] VSS[123] VSS[218] VSS[318]
AN34 VSS[45] VSS[124] AP5 BH31 VSS[219] VSS[319] V43
AF45 VSS[46] VSS[125] AP8 BH35 VSS[220] VSS[320] V45
AF46 AR2 BH39 V46
VSS[47] VSS[126] VSS[221] VSS[321]
AF49 AR52 BH43 V47
VSS[48] VSS[127] VSS[222] VSS[322]
AF5 AT11 BH47 V49
VSS[49] VSS[128] VSS[223] VSS[323]
B AF8 BA12 BH7 V5 B
VSS[50] VSS[129] VSS[224] VSS[324]
AG2 AH48 C12 V7
VSS[51] VSS[130] VSS[225] VSS[325]
AG52 VSS[52] VSS[131] AT32 C50 VSS[226] VSS[326] V8
AH11 VSS[53] VSS[132] AT36 D51 VSS[227] VSS[327] W2
AH15 AT41 E12 W52
VSS[54] VSS[133] VSS[228] VSS[328]
AH16 AT47 E16 Y11
VSS[55] VSS[134] VSS[229] VSS[329]
AH24 AT7 E20 Y12
VSS[56] VSS[135] VSS[230] VSS[330]
AH32 VSS[57] VSS[136] AV12 E24 VSS[231] VSS[331] Y15
AV18 VSS[58] VSS[137] AV16 E30 VSS[232] VSS[332] Y19
AH43 AV20 E34 Y23
VSS[59] VSS[138] VSS[233] VSS[333]
AH47 AV24 E38 Y28
VSS[60] VSS[139] VSS[234] VSS[334]
AH7 AV30 E42 Y30
VSS[61] VSS[140] VSS[235] VSS[335]
AJ19 VSS[62] VSS[141] AV34 E46 VSS[236] VSS[336] Y31
AJ20 AV42 E6 Y38
VSS[64] VSS[143] VSS[238] VSS[338]
AJ23 VSS[66] VSS[145] AV49 F49 VSS[240] VSS[340] Y46
AJ26 AV5 F5 P49
VSS[67] VSS[146] VSS[241] VSS[341]
AJ28 AV8 G10 Y5
VSS[68] VSS[147] VSS[242] VSS[342]
AJ32 VSS[69] VSS[148] AW14 G14 VSS[243] VSS[343] Y6
AJ34 VSS[70] VSS[149] AW18 G18 VSS[244] VSS[344] Y8
AT5 VSS[71] VSS[150] AW2 G2 VSS[245] VSS[345] P24
AJ4 BF9 G22 T43
VSS[72] VSS[151] VSS[246] VSS[346]
AK12 AW32 G32 AD51
VSS[73] VSS[152] VSS[247] VSS[347]
AM41 VSS[74] VSS[153] AW36 G36 VSS[248] VSS[348] AT8
AN19 VSS[75] VSS[154] AW40 G40 VSS[249] VSS[349] AD47
AK26 AW52 G44 Y47
VSS[76] VSS[155] VSS[250] VSS[350]
AK22 AY11 G52 AT12
VSS[77] VSS[156] VSS[251] VSS[351]
AK23 VSS[78] VSS[157] AY43 AF39 VSS[252] VSS[352] AM6
A A
AK28 VSS[79] VSS[158] AY47 H16 VSS[253] VSS[353] AT13
H20 AM5
IbexPeak-M_R1P0 VSS[254] VSS[354]
H30 VSS[255] VSS[355] AK45
H34 VSS[256] VSS[356] AK39
H38 VSS[257] VSS[366] AV14
H42 VSS[258]
PROJECT : ZR7
IbexPeak-M_R1P0 Size Document Number Rev
3B
IBEX PEAK-M 6/6
5 4 3 2 1
5 4 3 2 1
DIMM A0 M_A_DQ[63:0] 5
+1.5V_SUS
JDIM4B
JDIM4A
5 M_A_A[15:0] 75 44
M_A_A0 M_A_DQ0 VDD1 VSS16
98 A0 DQ0 5 76 VDD2 VSS17 48
M_A_A1 97 7 M_A_DQ1 81 49
M_A_A2 A1 DQ1 M_A_DQ2 VDD3 VSS18
96 15 82 54
M_A_A3 95
A2
A3
DQ2
DQ3 17 M_A_DQ3 87
VDD4
VDD5
VSS19
VSS20 55 Place these Caps near So-Dimm0. +SMDDR_VREF_DIMM
M_A_A4 92 4 M_A_DQ4 88 60
91 A5 DQ5 6 93 VDD7 VSS22 61
M_A_A6 90 16 M_A_DQ6 94 65
M_A_A7 86
A6 DQ6
18 M_A_DQ7
2.48A 99
VDD8 VSS23
66 +1.5V_SUS C365 C367
89 A8 DQ8 21 100 VDD10 VSS25 71
M_A_A9 85 23 M_A_DQ9 105 72 C276 C280 C320 C302 C294 .1u/10V_4 2.2u/6.3V_6
M_A_A10 A9 DQ9 M_A_DQ10 VDD11 VSS26 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/10V_4 .1u/10V_4
107 33 106 127
PC2100 DDR3 SDRAM SO-DIMM

M_A_A11 A10/AP DQ10 M_A_DQ11 VDD12 VSS27
84 35 111 128
M_A_A12 A11 DQ11 M_A_DQ12 VDD13 VSS28 + C267
83 A12/BC# DQ12 22 112 VDD14 VSS29 133
M_A_A13 119 24 M_A_DQ13 117 134 330u/2V_7343
D
M_A_A14 A13 DQ13 M_A_DQ14 VDD15 VSS30 D
80 34 118 138
M_A_A15 A14 DQ14 M_A_DQ15 VDD16 VSS31 +SMDDR_VREF_DQ0
78 A15 DQ15 36 123 VDD17 VSS32 139

39 M_A_DQ16 124 144 C256 C261 C319 C254 C301 C312
DQ16 M_A_DQ17 VDD18 VSS33 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/10V_4 .1u/10V_4 .1u/10V_4
5 M_A_BS#0 109 41 145
BA0 DQ17 M_A_DQ18 VSS34
5 M_A_BS#1 108 BA1 DQ18 51 +3V 199 VDDSPD VSS35 150
79 53 M_A_DQ19 151 C202 C201
5 M_A_BS#2 BA2 DQ19 VSS36
114 40 M_A_DQ20 77 155
5 M_A_CS#0 S0# DQ20 NC1 VSS37
121 42 M_A_DQ21 122 156 .1u/10V_4 2.2u/6.3V_6
101 50 M_A_DQ22 125 161
5 M_A_CLK0 CK0 DQ22 M_A_DQ23 NCTEST VSS39
5 M_A_CLK0# 103 52 162
CK0# DQ23 M_A_DQ24 VSS40 +3V +0.75V_DDR_VTT
5 M_A_CLK1 102 CK1 DQ24 57 4 PM_EXTTS#0 198 EVENT# VSS41 167
104 59 M_A_DQ25 30 168
5 M_A_CLK1# CK1# DQ25 15,35 DDR3_DRAMRST# RESET# VSS42
73 67 M_A_DQ26 172
5 M_A_CKE0 CKE0 DQ26 VSS43
74 69 M_A_DQ27 173
5 M_A_CKE1 CKE1 DQ27 M_A_DQ28 +SMDDR_VREF_DQ0 VSS44
115 56 1 178 C398 C407 C435 C436 C418 C437 C421 C419 C420
5 M_A_CAS# CAS# DQ28 VREF_DQ VSS45
110 58 M_A_DQ29 R116 M1@0_6 +SMDDR_VREF_DIMM 126 179
5 M_A_RAS# RAS# DQ29 +SMDDR_VREF VREF_CA VSS46
113 68 M_A_DQ30 184 2.2u/6.3V_6 .1u/10V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6
5 M_A_WE# WE# DQ30 VSS47
R284 10K_4 DIMM0_SA0 197 70 M_A_DQ31 R124 *M3@0_6 185
SA0 DQ31 7,35 VREF_DQ_DIMM0 VSS48
R283 10K_4 DIMM0_SA1 201 129 M_A_DQ32 2 189
CLK_SCLK SA1 DQ32 M_A_DQ33 VSS1 VSS49
202 131 35 +SMDDR_VREF_DQ0 3 190
3,15,27 CLK_SCLK CLK_SDATA SCL DQ33 M_A_DQ34 VSS2 VSS50 maybe can save
200 141 8 195
(204P)
3,15,27 CLK_SDATA SDA DQ34 M_A_DQ35 VSS3 VSS51
143 9 196
DQ35 M_A_DQ36 VSS4 VSS52
5 M_A_ODT0 116 ODT0 DQ36 130 13 VSS5
120 132 M_A_DQ37 14
5 M_A_ODT1 ODT1 DQ37 M_A_DQ38 VSS6
5 M_A_DM[7:0] 140 19
M_A_DM0 DQ38 M_A_DQ39 VSS7
11 DM0 DQ39 142 20 VSS8
M_A_DM1 28 147 M_A_DQ40 25
M_A_DM2 DM1 DQ40 M_A_DQ41 VSS9
46 149 26 203
M_A_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_A_DQ42
+1.5V_SUS +SMDDR_VREF_DIMM
31
VSS10
VSS11
VTT1
VTT2 204
+0.75V_DDR_VTT
M_A_DM4 136 159 M_A_DQ43 32
153 DM5 DQ44 146 37 VSS13 GND 205
M_A_DM6 170 148 M_A_DQ45 38 206
M_A_DM7 DM6 DQ45 M_A_DQ46 VSS14 GND
187 DM7 DQ46 158 43 VSS15
160 M_A_DQ47 R193
5 M_A_DQS[7:0] M_A_DQS0 DQ47 M_A_DQ48
12 163 *10K_4
M_A_DQS1 DQS0 DQ48 M_A_DQ49 M_A_DM0 R130 *CF@0_4
29 165 DDR3-DIMM0_H=8.0_Standard
47 DQS2 DQ50 175
C M_A_DQS3 64 177 M_A_DQ51 R186 *SHORT_6 +SMDDR_VREF_DIMM M_A_DM2 R147 *CF@0_4 C
DQS3 DQ51 +SMDDR_VREF
M_A_DQS4 137 164 M_A_DQ52 M_A_DM3 R148 *CF@0_4
154 DQS5 DQ53 166
M_A_DQS6 171 174 M_A_DQ54 R194 C366 M_A_DM5 R221 *CF@0_4
5 M_A_DQS#[7:0] 188 DQS7 DQ55 176 *10K_4 470p/X7R_4
M_A_DQS#0 10 181 M_A_DQ56 M_A_DM7 R248 *CF@0_4
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57
27 183
M_A_DQS#2 DQS#1 DQ57 M_A_DQ58 Close to SO-DIMM
45 DQS#2 DQ58 191
M_A_DQS#3 62 193 M_A_DQ59
135 DQS#4 DQ60 180
M_A_DQS#5 152 182 M_A_DQ61
169 DQS#6 DQ62 192
M_A_DQS#7 186 194 M_A_DQ63
DQS#7 DQ63
DDR3-DIMM0_H=8.0_Standard
DIMM A1 4D@ --> 4 SO-DIMM M_A_DQ[63:0] 5

+1.5V_SUS
JDIM3B
JDIM3A
5 M_A_A[15:0] 75 44
M_A_A0 M_A_DQ0 VDD1 VSS16
98 A0 DQ0 5 76 VDD2 VSS17 48
M_A_A1 97 7 M_A_DQ1 81 49
96 15 82 54
M_A_A3 95
A2
A3
DQ2
DQ3
17 M_A_DQ3 87
VDD4
VDD5
VSS19
VSS20
55 Place these Caps near So-Dimm0.
M_A_A4 92 4 M_A_DQ4 88 60 +SMDDR_VREF_DIMM
91 6 93 61
90 A6 DQ6 16 2.48A 94 VDD8 VSS23 65
M_A_A7 86 18 M_A_DQ7 99 66 +1.5V_SUS C259 C278
M_A_A8 A7 DQ7 M_A_DQ8 VDD9 VSS24 4D@10u/6.3V_6 4D@.1u/10V_4 C363 C364
89 21 100 71
M_A_A9 A8 DQ8 M_A_DQ9 VDD10 VSS25 C334 C260 C298
85 23 105 72
M_A_A10 A9 DQ9 M_A_DQ10 VDD11 VSS26 4D@10u/6.3V_6 4D@10u/6.3V_6 4D@.1u/10V_4 4D@.1u/10V_4 4D@2.2u/6.3V_6
107 33 106 127

M_A_A11 A10/AP DQ10 M_A_DQ11 VDD12 VSS27
84 35 111 128
M_A_A12 A11 DQ11 M_A_DQ12 VDD13 VSS28 + C266
83 22 112 133
M_A_A13 A12/BC# DQ12 M_A_DQ13 VDD14 VSS29 4D@330u/2V_7343
B
119 A13 DQ13 24 117 VDD15 VSS30 134 B
M_A_A14 80 34 M_A_DQ14 118 138
78 A15 DQ15 36 123 VDD17 VSS32 139
39 M_A_DQ16 124 144 C270 C335 C285 +SMDDR_VREF_DQ0

DQ16 M_A_DQ17 VDD18 VSS33 4D@10u/6.3V_6 4D@10u/6.3V_6 4D@.1u/10V_4
5 M_A_BS#0 109 BA0 DQ17 41 VSS34 145
108 51 M_A_DQ18 199 150 C269 C277 C313
5 M_A_BS#1 BA1 DQ18 +3V VDDSPD VSS35
79 53 M_A_DQ19 151 4D@10u/6.3V_6 4D@.1u/10V_4 4D@.1u/10V_4
5 M_A_BS#2 BA2 DQ19 VSS36
114 40 M_A_DQ20 77 155 C212 C213
121 42 M_A_DQ21 122 156
101 50 M_A_DQ22 125 161 4D@.1u/10V_4 4D@2.2u/6.3V_6
7 M_A_CLK2 CK0 DQ22 M_A_DQ23 NCTEST VSS39
7 M_A_CLK2# 103 CK0# DQ23 52 VSS40 162
102 57 M_A_DQ24 198 167
7 M_A_CLK3 CK1 DQ24 4 PM_EXTTS#0 EVENT# VSS41
104 59 M_A_DQ25 30 168
7 M_A_CLK3# CK1# DQ25 15,35 DDR3_DRAMRST# RESET# VSS42
73 67 M_A_DQ26 172
7 M_A_CKE2 CKE0 DQ26 VSS43 +3V
74 69 M_A_DQ27 173 +0.75V_DDR_VTT
7 M_A_CKE3 CKE1 DQ27 M_A_DQ28 +SMDDR_VREF_DQ0 VSS44
115 56 1 178 C429 C430 C413
5 M_A_CAS# CAS# DQ28 VREF_DQ VSS45
110 58 M_A_DQ29 +SMDDR_VREF_DIMM 126 179 4D@1U/6.3V_4 4D@1U/6.3V_4 4D@10u/6.3V_6
5 M_A_RAS# RAS# DQ29 VREF_CA VSS46
113 68 M_A_DQ30 184
5 M_A_WE# WE# DQ30 VSS47
R282 4D@10K_4 DIMM0_SA2 197 70 M_A_DQ31 185 C412
+3V SA0 DQ31 VSS48
R281 4D@10K_4 DIMM0_SA3 201 129 M_A_DQ32 2 189 C405 C416 4D@10u/6.3V_6
CLK_SCLK SA1 DQ32 M_A_DQ33 VSS1 VSS49 4D@2.2u/6.3V_6 4D@.1u/10V_4
202 SCL DQ33 131 3 VSS2 VSS50 190
3,15,27 CLK_SCLK CLK_SDATA 200 141 M_A_DQ34 8 195
(204P)
3,15,27 CLK_SDATA SDA DQ34 M_A_DQ35 VSS3 VSS51 C428 C415 C414
DQ35 143 9 VSS4 VSS52 196
116 130 M_A_DQ36 13 4D@1U/6.3V_4 4D@1U/6.3V_4 4D@10u/6.3V_6
7 M_A_ODT2 ODT0 DQ36 VSS5
120 132 M_A_DQ37 14 maybe can save
7 M_A_ODT3 ODT1 DQ37 M_A_DQ38 VSS6
5 M_A_DM[7:0] DQ38 140 19 VSS7
M_A_DM0 11 142 M_A_DQ39 20
28 147 25
46 149 26 203
(204P)
DM2 DQ41 VSS10 VTT1 +0.75V_DDR_VTT

M_A_DM3 63 157 M_A_DQ42 31 204
M_A_DM4 DM3 DQ42 M_A_DQ43 VSS11 VTT2
136 DM4 DQ43 159 32 VSS12
M_A_DM5 153 146 M_A_DQ44 37 205
M_A_DM6 DM5 DQ44 M_A_DQ45 VSS13 GND
170 DM6 DQ45 148 38 VSS14 GND 206
M_A_DM7 187 158 M_A_DQ46 43
DM7 DQ46 M_A_DQ47 VSS15
5 M_A_DQS[7:0] 160
M_A_DQS0 DQ47 M_A_DQ48
12 DQS0 DQ48 163
M_A_DQS1 29 165 M_A_DQ49
DQS1 DQ49 4D@DDR3-DIMM0_H=4.0_Standard
M_A_DQS2 47 175 M_A_DQ50
M_A_DQS3 DQS2 DQ50 M_A_DQ51
A 64 177 A
137 164
154 166
171 174
5 M_A_DQS#[7:0] 188 176
M_A_DQS#0 DQS7 DQ55 M_A_DQ56
10 DQS#0 DQ56 181
M_A_DQS#1 27 183 M_A_DQ57
45 DQS#2 DQ58 191
M_A_DQS#3 62 193 M_A_DQ59
135 DQS#4 DQ60 180
M_A_DQS#5 152 182 M_A_DQ61
M_A_DQS#6
M_A_DQS#7
169
DQS#5
DQS#6
DQ61
DQ62 192 M_A_DQ62
M_A_DQ63
186 194
DQS#7 DQ63
PROJECT : ZR7
4D@DDR3-DIMM0_H=4.0_Standard Size Document Number Rev
3B
DDRIII SO-DIMM-A0/A1
5 4 3 2 1
5 4 3 2 1
DIMM B0 M_B_DQ[63:0] 5
+1.5V_SUS
JDIM2A JDIM2B
5 M_B_A[15:0]
M_B_A0 98 5 M_B_DQ0 75 44
M_B_A1 A0 DQ0 M_B_DQ1 VDD1 VSS16
97 A1 DQ1 7 76 VDD2 VSS17 48
M_B_A2 96 15 M_B_DQ2 81 49
95 17 82 54
M_B_A4 92
A3
A4
DQ3
DQ4 4 M_B_DQ4 87
VDD4
VDD5
VSS19
VSS20 55 +1.5V_SUS Place these Caps near So-Dimm1.
M_B_A5 91 6 M_B_DQ5 88 60 +SMDDR_VREF_DIMM
M_B_A6 A5 DQ5 M_B_DQ6 VDD6 VSS21 C265 C361 C307 C255 C343
90 16 93 61
M_B_A7 A6 DQ6 M_B_DQ7 VDD7 VSS22 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/10V_4 .1u/10V_4
86 18 94 65
89 A8 DQ8 21 2.48A 99 VDD9 VSS24 66
M_B_A9 85 23 M_B_DQ9 100 71 + C329 C369 C371
M_B_A10 A9 DQ9 M_B_DQ10 VDD10 VSS25 330u/2V_7343
107 A10/AP DQ10 33 105 VDD11 VSS26 72
M_B_A11 84 35 M_B_DQ11 106 127 .1u/10V_4 2.2u/6.3V_6

83 A12/BC# DQ12 22 111 VDD13 VSS28 128
M_B_A13 119 24 M_B_DQ13 112 133 C356 C354 C299 C305 C342 C345
D
M_B_A14 A13 DQ13 M_B_DQ14 VDD14 VSS29 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/10V_4 .1u/10V_4 .1u/10V_4
D
80 34 117 134
78 A15 DQ15 36 118 VDD16 VSS31 138

39 M_B_DQ16 123 139 +SMDDR_VREF_DQ1
DQ16 M_B_DQ17 VDD17 VSS32
5 M_B_BS#0 109 41 124 144
BA0 DQ17 M_B_DQ18 VDD18 VSS33
5 M_B_BS#1 108 BA1 DQ18 51 VSS34 145
79 53 M_B_DQ19 199 150
5 M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ20 151 C207 C206
5 M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ21 77 155
5 M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ22 122 156 .1u/10V_4 2.2u/6.3V_6
5 M_B_CLK0 CK0 DQ22 M_B_DQ23 NC2 VSS38
5 M_B_CLK0# 103 52 125 161
CK0# DQ23 M_B_DQ24 NCTEST VSS39
5 M_B_CLK1 102 CK1 DQ24 57 VSS40 162
104 59 M_B_DQ25 198 167 +3V +0.75V_DDR_VTT
5 M_B_CLK1# CK1# DQ25 4 PM_EXTTS#1 EVENT# VSS41
73 67 M_B_DQ26 30 168
5 M_B_CKE0 CKE0 DQ26 14,35 DDR3_DRAMRST# RESET# VSS42
74 69 M_B_DQ27 172
5 M_B_CKE1 CKE1 DQ27 M_B_DQ28 VSS43
5 M_B_CAS# 115 CAS# DQ28 56 VSS44 173
110 58 M_B_DQ29 R113 M1@0_6 +SMDDR_VREF_DQ1 1 178 C401 C399 C403 C432 C423 C402 C397 C434 C404
5 M_B_RAS# RAS# DQ29 +SMDDR_VREF VREF_DQ VSS45
113 68 M_B_DQ30 +SMDDR_VREF_DIMM 126 179
5 M_B_WE# WE# DQ30 VREF_CA VSS46
R262 10K_4 DIMM1_SA0 197 70 M_B_DQ31 R120 *M3@0_6 184 2.2u/6.3V_6 .1u/10V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6
SA0 DQ31 7,35 VREF_DQ_DIMM1 VSS47
R280 10K_4 DIMM1_SA1 201 129 M_B_DQ32 185
+3V SA1 DQ32 M_B_DQ33 VSS48
202 131 35 +SMDDR_VREF_DQ1 2 189
3,14,27 CLK_SCLK SCL DQ33 M_B_DQ34 VSS1 VSS49
200 141 3 190
3,14,27 CLK_SDATA SDA DQ34 M_B_DQ35 VSS2 VSS50
143 8 195
(204P)
DQ35 M_B_DQ36 VSS3 VSS51 maybe can save
5 M_B_ODT0 116 ODT0 DQ36 130 9 VSS4 VSS52 196
120 132 M_B_DQ37 13
5 M_B_ODT1 ODT1 DQ37 M_B_DQ38 VSS5
5 M_B_DM[7:0] 140 14
M_B_DM0 DQ38 M_B_DQ39 VSS6
11 DM0 DQ39 142 19 VSS7
M_B_DM1 28 147 M_B_DQ40 20
M_B_DM2 DM1 DQ40 M_B_DQ41 VSS8
46 149 25
(204P)
63 DM3 DQ42 157 26 VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DM4 136 159 M_B_DQ43 31 204
M_B_DM5 DM4 DQ43 M_B_DQ44 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
M_B_DM6 170 148 M_B_DQ45 37 205
M_B_DM7 DM6 DQ45 M_B_DQ46 VSS13 GND M_B_DM0 R131 *CF@0_4
187 DM7 DQ46 158 38 VSS14 GND 206
160 M_B_DQ47 43 M_B_DM1 R136 *CF@0_4
5 M_B_DQS[7:0] M_B_DQS0 DQ47 M_B_DQ48 VSS15 M_B_DM2
12 163 R145 *CF@0_4
M_B_DQS1 DQS0 DQ48 M_B_DQ49 M_B_DM3 R149 *CF@0_4
29 165
M_B_DQS2 DQS1 DQ49 M_B_DQ50 DDR3-DIMM1_H=4.0_Reverse M_B_DM4 R204 *CF@0_4
47 DQS2 DQ50 175
C M_B_DQS3 64 177 M_B_DQ51 M_B_DM5 R216 *CF@0_4 C
M_B_DQS4 DQS3 DQ51 M_B_DQ52 M_B_DM6 R237 *CF@0_4
137 DQS4 DQ52 164
M_B_DQS5 154 166 M_B_DQ53 M_B_DM7 R257 *CF@0_4
M_B_DQS6 DQS5 DQ53 M_B_DQ54
171 174
M_B_DQS7 DQS6 DQ54 M_B_DQ55 Close to SO-DIMM
5 M_B_DQS#[7:0] 188 DQS7 DQ55 176
M_B_DQS#0 10 181 M_B_DQ56
M_B_DQS#1 DQS#0 DQ56 M_B_DQ57
27 183
45 DQS#2 DQ58 191
M_B_DQS#3 62 193 M_B_DQ59
135 DQS#4 DQ60 180
M_B_DQS#5 152 182 M_B_DQ61
169 DQS#6 DQ62 192
M_B_DQS#7 186 194 M_B_DQ63
DQS#7 DQ63
DDR3-DIMM1_H=4.0_Reverse
DIMM B1 4D@ --> 4 SO-DIMM

+1.5V_SUS
JDIM1A M_B_DQ[63:0] 5 JDIM1B
5 M_B_A[15:0]
M_B_A0 98 5 M_B_DQ0 75 44
M_B_A1 97
A0
A1
DQ0
DQ1 7 M_B_DQ1 76
VDD1
VDD2
VSS16
VSS17 48 Place these Caps near So-Dimm1.
M_B_A2 96 15 M_B_DQ2 81 49 +SMDDR_VREF_DIMM
95 17 82 54
M_B_A4 A3 DQ3 M_B_DQ4 VDD4 VSS19 +1.5V_SUS C263 C303
92 A4 DQ4 4 87 VDD5 VSS20 55
M_B_A5 91 6 M_B_DQ5 88 60 4D@10u/6.3V_6 4D@.1u/10V_4
M_B_A6 A5 DQ5 M_B_DQ6 VDD6 VSS21 C262 C264 C289 C372 C370
90 A6 DQ6 16 93 VDD7 VSS22 61
M_B_A7 86 18 M_B_DQ7 94 65 4D@10u/6.3V_6 4D@10u/6.3V_6 4D@.1u/10V_4
M_B_A8 A7 DQ7 M_B_DQ8 VDD8 VSS23 4D@.1u/10V_4 4D@2.2u/6.3V_6
89 21 2.48A 99 66
M_B_A9 A8 DQ8 M_B_DQ9 VDD9 VSS24 + C373
85 23 100 71
107 33 105 72
M_B_A11 A10/AP DQ10 M_B_DQ11 VDD11 VSS26 4D@330u/2V_7343
84 35 106 127

83 22 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ13 VDD13 VSS28 C315 C346 C316
B
119 A13 DQ13 24 112 VDD14 VSS29 133 B
M_B_A14 80 34 M_B_DQ14 117 134 4D@10u/6.3V_6 4D@10u/6.3V_6 4D@.1u/10V_4 +SMDDR_VREF_DQ1
M_B_A15 A14 DQ14 M_B_DQ15 VDD15 VSS30 C359 C336 C330
78 A15 DQ15 36 118 VDD16 VSS31 138
39 M_B_DQ16 123 139 4D@10u/6.3V_6 4D@.1u/10V_4 4D@.1u/10V_4

DQ16 M_B_DQ17 VDD17 VSS32
5 M_B_BS#0 109 BA0 DQ17 41 124 VDD18 VSS33 144
108 51 M_B_DQ18 145 C208 C205
5 M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ19 199 150
5 M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ20 151 4D@.1u/10V_4 4D@2.2u/6.3V_6
7 M_B_CS#2 S0# DQ20 VSS36
121 42 M_B_DQ21 77 155
7 M_B_CS#3 S1# DQ21 NC1 VSS37
101 50 M_B_DQ22 122 156
7 M_B_CLK2 CK0 DQ22 M_B_DQ23 NC2 VSS38
7 M_B_CLK2# 103 CK0# DQ23 52 125 NCTEST VSS39 161
102 57 M_B_DQ24 162
7 M_B_CLK3 CK1 DQ24 VSS40
104 59 M_B_DQ25 198 167
7 M_B_CLK3# CK1# DQ25 4 PM_EXTTS#1 EVENT# VSS41 +3V
73 67 M_B_DQ26 30 168 +0.75V_DDR_VTT
7 M_B_CKE2 CKE0 DQ26 14,35 DDR3_DRAMRST# RESET# VSS42
74 69 M_B_DQ27 172 C422 C438 C446
7 M_B_CKE3 CKE1 DQ27 M_B_DQ28 VSS43
115 56 173 4D@1U/6.3V_4 4D@1U/6.3V_4 4D@10u/6.3V_6
5 M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ29 +SMDDR_VREF_DQ1 1 178
5 M_B_RAS# RAS# DQ29 VREF_DQ VSS45
113 68 M_B_DQ30 +SMDDR_VREF_DIMM 126 179 C406
5 M_B_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R290 4D@10K_4 DIMM1_SA2 197 70 M_B_DQ31 184 C454 C441
+3V SA0 DQ31 VSS47
R285 4D@10K_4 DIMM1_SA3 201 129 M_B_DQ32 185 4D@2.2u/6.3V_6 4D@10u/6.3V_6
SA1 DQ32 M_B_DQ33 VSS48 4D@.1u/10V_4
202 SCL DQ33 131 2 VSS1 VSS49 189
3,14,27 CLK_SCLK 200 141 M_B_DQ34 3 190 C440 C439 C433
3,14,27 CLK_SDATA SDA DQ34 M_B_DQ35 VSS2 VSS50 4D@1U/6.3V_4 4D@1U/6.3V_4 4D@10u/6.3V_6
143 8 195
(204P)
DQ35 M_B_DQ36 VSS3 VSS51
7 M_B_ODT2 116 130 9 196
ODT0 DQ36 M_B_DQ37 VSS4 VSS52 maybe can save
7 M_B_ODT3 120 ODT1 DQ37 132 13 VSS5
140 M_B_DQ38 14
5 M_B_DM[7:0] DQ38 VSS6
M_B_DM0 11 142 M_B_DQ39 19
28 147 20
46 149 25
(204P)

63 157 26 203 +0.75V_DDR_VTT
M_B_DM4 DM3 DQ42 M_B_DQ43 VSS10 VTT1
136 DM4 DQ43 159 31 VSS11 VTT2 204
M_B_DM5 153 146 M_B_DQ44 32
170 DM6 DQ45 148 37 VSS13 GND 205
M_B_DM7 187 158 M_B_DQ46 38 206
DM7 DQ46 M_B_DQ47 VSS14 GND
5 M_B_DQS[7:0] 160 43
M_B_DQS0 DQ47 M_B_DQ48 VSS15
12 DQS0 DQ48 163
M_B_DQS1 29 165 M_B_DQ49
M_B_DQS2 DQS1 DQ49 M_B_DQ50 4D@DDR3-DIMM1_H=8.0_Reverse
47 175
A 64 177 A
137 164
154 166
171 174
5 M_B_DQS#[7:0] 188 176
M_B_DQS#0 DQS7 DQ55 M_B_DQ56
10 DQS#0 DQ56 181
M_B_DQS#1 27 183 M_B_DQ57
45 DQS#2 DQ58 191
M_B_DQS#3 62 193 M_B_DQ59
135 DQS#4 DQ60 180
M_B_DQS#5 152 182 M_B_DQ61
M_B_DQS#6
M_B_DQS#7
169
DQS#5
DQS#6
DQ61
DQ62 192 M_B_DQ62
M_B_DQ63
186 194
DQS#7 DQ63
PROJECT : ZR7
4D@DDR3-DIMM1_H=8.0_Reverse Size Document Number Rev
3B
DDRIII SO-DIMM-B0/B1
5 4 3 2 1
1 2 3 4 5 6 7 8
EV@ --> dGPU only

PEX_IOVDD+PEX_IOVDDQ+PEX_PLLVDD >2.2A SW@ --> iGPU & dGPU Switch
U33A ES@ --> External VGA SKU
VSP@N11P-GE-A1/H
+1.05V_GFX COMMON VSP@ --> Operation P/N (VGA)
AK16 AP17 PEG_TXP15
~ 500mA C62
C85
ES@.1u/10V_4
ES@.1u/10V_4
AK17
PEX_IOVDD_1
PEX_IOVDD_2
PEX_RX0
PEX_RX0* AN17 PEG_TXN15
PEG_TXP14
PEG_TXP15 4
PEG_TXN15 4 power up sequence
AK21 PEX_IOVDD_3 PEX_RX1 AN19 PEG_TXP14 4
C100 ES@1U/6.3V_4 AK24 AP19 PEG_TXN14 PEG_TXN14 4
C66 ES@1U/6.3V_4 PEX_IOVDD_4 PEX_RX1* PEG_TXP13
AK27 PEX_IOVDD_5 PEX_RX2 AR19 PEG_TXP13 4
A C63 ES@4.7U/6.3V_6 AR20 PEG_TXN13 PEG_TXN13 4 A
C71 ES@4.7U/6.3V_6 PEX_RX2* PEG_TXP12
PEX_RX3 AP20 PEG_TXP12 4
AN20 PEG_TXN12 PEG_TXN12 4
C109 ES@10U/6.3V_6 PEX_RX3* PEG_TXP11
PEX_RX4 AN22 PEG_TXP11 4
AP22 PEG_TXN11 PEG_TXN11 4 PXE 1.05VDD
PEX_RX4* PEG_TXP10
11/27 Modify to CC0603 AG11 PEX_IOVDDQ_1 PEX_RX5 AR22 PEG_TXP10 4
+1.05V_GFX AG12 AR23 PEG_TXN10 PEG_TXN10 4
PEX_IOVDDQ_2 PEX_RX5* PEG_TXP9
AG13 PEX_IOVDDQ_3 PEX_RX6 AP23 PEG_TXP9 4
C99 ES@.1u/10V_4 AG15 AN23 PEG_TXN9
1600mA C74
C80
ES@.1u/10V_4
ES@1U/6.3V_4
AG16
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_RX6*
PEX_RX7 AN25 PEG_TXP8
PEG_TXN8
PEG_TXN9 4
PEG_TXP8 4 I/O 3.3V
AG17 PEX_IOVDDQ_6 PEX_RX7* AP25 PEG_TXN8 4
C134 ES@1U/6.3V_4 AG18 AR25 PEG_TXP7 PEG_TXP7 4
C124 ES@4.7U/6.3V_6 PEX_IOVDDQ_7 PEX_RX8 PEG_TXN7
AG22 PEX_IOVDDQ_8 PEX_RX8* AR26 PEG_TXN7 4
C96 ES@4.7U/6.3V_6 AG23 AP26 PEG_TXP6 PEG_TXP6 4
PEX_IOVDDQ_9 PEX_RX9 PEG_TXN6
Near BGA AG24 PEX_IOVDDQ_10 PEX_RX9* AN26 PEG_TXN6 4 NVCORE
C84 ES@10U/6.3V_6 AG25 AN28 PEG_TXP5 PEG_TXP5 4
AG26 PEX_IOVDDQ_12 PEX_RX10* AP28 PEG_TXN5 4
11/27 Modify to CC0603 AJ14 AR28 PEG_TXP4 PEG_TXP4 4
AJ15 PEX_IOVDDQ_14 PEX_RX11* AR29 PEG_TXN4 4
AJ19 AP29 PEG_TXP3 PEG_TXP3 4 1.5VFBDDQ
AJ21 PEX_IOVDDQ_16 PEX_RX12* AN29 PEG_TXN3 4
AJ22 AN31 PEG_TXP2 PEG_TXP2 4
AJ24 PEX_IOVDDQ_18 PEX_RX13* AP31 PEG_TXN2 4
AJ25 AR31 PEG_TXP1 PEG_TXP1 4
AJ27 PEX_IOVDDQ_20 PEX_RX14* AR32 PEG_TXN1 4
AK18 AR34 PEG_TXP0 PEG_TXP0 4 NB9M: VGACORE +0.90V (Normal) , +1.09V
AK20 PEX_IOVDDQ_22 PEX_RX15* AP34 PEG_TXN0 4
AK23
AK26
PEX_IOVDDQ_23 NVVDD Maximum Settling Time
PEX_IOVDDQ_24 CPEG_RXP15 C129 ES@.1u/10V_4
B AL16 PEX_IOVDDQ_25 PEX_TX0 AL17 PEG_RXP15 4 B
+3V_GFX AM17 CPEG_RXN15 C122 ES@.1u/10V_4 PEG_RXN15 4
PEX_TX0* CPEG_RXP14 C123 ES@.1u/10V_4
C126 ES@4.7U/6.3V_6 PCI EXPRESS PEX_TX1 AM18
AM19 CPEG_RXN14 C111 ES@.1u/10V_4
PEG_RXP14 4
PEG_RXN14 4
C141 ES@1U/6.3V_4 PEX_TX1* CPEG_RXP13 C110 ES@.1u/10V_4
J10 VDD33_1 PEX_TX2 AL19 PEG_RXP13 4
C130 ES@.1u/10V_4 J11 AK19 CPEG_RXN13 C103 ES@.1u/10V_4 PEG_RXN13 4
C127 ES@.1u/10V_4 VDD33_2 PEX_TX2* CPEG_RXP12 C104 ES@.1u/10V_4
C112 ES@.1u/10V_4
J12 VDD33_3 PEX_TX3 AL20
CPEG_RXN12 C98 ES@.1u/10V_4
PEG_RXP12 4 NVVDD
J13 VDD33_4 PEX_TX3* AM20 PEG_RXN12 4
J9 AM21 CPEG_RXP11 C88 ES@.1u/10V_4 PEG_RXP11 4
VDD33_5 PEX_TX4 CPEG_RXN11 C83 ES@.1u/10V_4
PEX_TX4* AM22 PEG_RXN11 4
10/20 add T7 AD20 AL22 CPEG_RXP10 C87 ES@.1u/10V_4 PEG_RXP10 4
VDD_SENSE PEX_TX5 CPEG_RXN10 C97 ES@.1u/10V_4
T1 D35 NC_9/ VDD_SENSE PEX_TX5* AK22 PEG_RXN10 4
T10 P7 AL23 CPEG_RXP9 C82 ES@.1u/10V_4 PEG_RXP9 4
NC_16/ VDD_SENSE PEX_TX6 CPEG_RXN9 C76 ES@.1u/10V_4
AM24 CPEG_RXP8 C68 ES@.1u/10V_4
12~16 mils width 110mA +1.05V_GFX AD19 GND_SENSE
PEX_TX7
PEX_TX7* AM25 CPEG_RXN8 C77 ES@.1u/10V_4
PEG_RXP8 4
PEG_RXN8 4
E35 AL25 CPEG_RXP7 C60 ES@.1u/10V_4 PEG_RXP7 4
C118 ES@1U/6.3V_4 NC_10/ GND_SENSE PEX_TX8 CPEG_RXN7 C67 ES@.1u/10V_4
R7 NC_17/ GND_SENSE PEX_TX8* AK25 PEG_RXN7 4
C119 ES@1U/6.3V_4 L3 AL26 CPEG_RXP6 C61 ES@.1u/10V_4 PEG_RXP6 4 GPIO
ES@100nH_6 PEX_TX9 CPEG_RXN6 C51 ES@.1u/10V_4
AM27 CPEG_RXP5 C50 ES@.1u/10V_4 PEG_RXP5 4
C133 ES@1U/6.3V_4 +PEX_PLLVDD PEX_TX10 CPEG_RXN5 C42 ES@.1u/10V_4
AG14 PEX_PLLVDD PEX_TX10* AM28 PEG_RXN5 4
C132 ES@4.7U/6.3V_6 AL28 CPEG_RXP4 C40 ES@.1u/10V_4 PEG_RXP4 4
PEX_TX11 CPEG_RXN4 C43 ES@.1u/10V_4
PEX_TX11* AK28 PEG_RXN4 4
10/20 del C3553,C3554 AK29 CPEG_RXP3 C39 ES@.1u/10V_4 PEG_RXP3 4 tsNVVDD<= 192us
PEX_TX12 CPEG_RXN3 C36 ES@.1u/10V_4
AL29
12~16 mils width PEX_TX12*
PEX_TX13 AM29 CPEG_RXP2
CPEG_RXN2
C37
C35
ES@.1u/10V_4
ES@.1u/10V_4
PEG_RXN3 4
PEG_RXP2 4
+3V_GFX L5 ES@0_6 +PEX_SVDD_3V3 AG19 AM31 CPEG_RXP1 C32 ES@.1u/10V_4 PEG_RXP1 4
PEX_CAL_PD_VDDQ/ PEX_SVDD_3V3 PEX_TX14 CPEG_RXN1 C30 ES@.1u/10V_4
C F7 NC_12/ PEX_SVDD_3V3 PEX_TX14* AM32 PEG_RXN1 4 C
AN32 CPEG_RXP0 C31 ES@.1u/10V_4 PEG_RXP0 4
C149 ES@1U/6.3V_4 PEX_TX15 CPEG_RXN0 C28 ES@.1u/10V_4
10/20 Modify to 1uF PEX_TX15* AP32 PEG_RXN0 4 SW@ --> iGPU & dGPU Switch
C93
C144
ES@.1u/10V_4
ES@4.7U/6.3V_6
AG20
A2
PEX_CAL_PU_GND/ NC PEX_REFCLK AR16
AR17
CLK_PCIE_VGA 10
CLK_PCIE_VGA# 10
PEX_RST timing
NC_1 PEX_REFCLK* R459 SW@100K_4
AB7 NC_2
AD6 NC_3
AF6 AJ17 PEX_TSTCLK R34 *ES@200_4
NC_4 PEX_TSTCLK_OUT PEX_TSTCLK#
AG6 NC_5 PEX_TSTCLK_OUT* AJ18
AJ5 R460 SW@0_4 GPU_RST# 11 I/O 3.3V
NC_6
AK15 NC_7
AL7 AM16 VGA_RST# R456 EV@0_4 PLTRST# 4,10,11,25,27,31,36
NC_8 PEX_RST*
E7 NC_11 PEX_RST
H32 AR13 PEX_CLKREQ# R449 ES@10K/F_4 +3V_GFX
NC_13 PEX_CLKREQ*
M7 NC_14
P6 AG21 PEX_TERMP R42 ES@2.49K/F_4 EV@ --> dGPU only
NC_15 PEX_TERMP
U7 NC_18
V6 AP35 TESTMODE R435 ES@10K/F_4 R456 un-mount for switchable function Trise >= 1uS Tfail <=500nS
NC_19 TESTMODE
R434 *ES@10K/F_4
+3V_GFX
+3V_GFX
Only for Hybrid R487 SW@10K/F_4 +3V_S5
PEG_CLKREQ# 10
SW@ --> iGPU & dGPU Switch R483
3
D SW@10K/F_4 D
2 Q41
SW@DTC144EUA
3
PEX_CLKREQ# 2 Q40
SW@DTC144EUA Quanta Computer Inc.
PROJECT : ZR7
1

3B
N11P-GE (PCIE I/F) 1/5
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
VSP@ --> Operation P/N (VGA) 11EP@ --> N11P/N11E-GE1 Setting 21 VMA_DQ[63..0]
ES@ --> External VGA SKU U33B

12/02 modify
21 VMA_DM[7..0] U33C
fcbga973-nvidia-n11p-es-a1 fcbga973-nvidia-n11p-es-a1
COMMON package for N10 21 VMA_WDQS[7..0] COMMON
12/02 modify
21 VMA_CMD0 V32 21 VMA_RDQS[7..0] 22 VMC_CMD0 C17 B13 VMC_DQ0 package for N10
FBA_CMD0 VMA_DQ0 FBC_CMD0 FBC_D00 VMC_DQ1
21 VMA_CMD1 W31 FBA_CMD1 FBA_D00 L32 22 VMC_CMD1 B19 FBC_CMD1 FBC_D01 D13
21 VMA_CMD2 U31 N33 VMA_DQ1 22 VMC_DQ[63..0] 22 VMC_CMD2 D18 A13 VMC_DQ2
FBA_CMD2 FBA_D01 VMA_DQ2 FBC_CMD2 FBC_D02 VMC_DQ3
21 VMA_CMD3 Y32 FBA_CMD3 FBA_D02 L33 22 VMC_CMD3 F21 FBC_CMD3 FBC_D03 A14
21 VMA_CMD4 AB35 N34 VMA_DQ3 22 VMC_DM[7..0] 22 VMC_CMD4 A23 C16 VMC_DQ4
21 VMA_CMD5 AB34 FBA_CMD5 FBA_D04 N35 22 VMC_CMD5 D21 FBC_CMD5 FBC_D05 B16
21 VMA_CMD6 W35 P35 VMA_DQ5 22 VMC_WDQS[7..0] 22 VMC_CMD6 B23 A17 VMC_DQ6
A 21 VMA_CMD7 W33 FBA_CMD7 FBA_D06 P33 22 VMC_CMD7 E20 FBC_CMD7 FBC_D07 D16 A
21 VMA_CMD8 W30 P34 VMA_DQ7 22 VMC_RDQS[7..0] 22 VMC_CMD8 G21 C13 VMC_DQ8
21 VMA_CMD9 T34 FBA_CMD9 FBA_D08 K35 22 VMC_CMD9 F20 FBC_CMD9 FBC_D09 B11
21 VMA_CMD10 T35 K33 VMA_DQ9 22 VMC_CMD10 F19 C11 VMC_DQ10
21 VMA_CMD11 AB31 FBA_CMD11 FBA_D10 K34 22 VMC_CMD11 F23 FBC_CMD11 FBC_D11 A11
21 VMA_CMD12 Y30 H33 VMA_DQ11 22 VMC_CMD12 A22 C10 VMC_DQ12
21 VMA_CMD13 Y34 FBA_CMD13 FBA_D12 G34 22 VMC_CMD13 C22 FBC_CMD13 FBC_D13 C8
21 VMA_CMD14 W32 G33 VMA_DQ13 22 VMC_CMD14 B17 B8 VMC_DQ14
VMA_CMD15 AA30 FBA_CMD14 FBA_D13 VMA_DQ14 VMC_CMD15 F24 FBC_CMD14 FBC_D14 VMC_DQ15
T3 FBA_CMD15 FBA_D14 E34 T6 FBC_CMD15 FBC_D15 A8
21 VMA_CMD16 AA32 E33 VMA_DQ15 22 VMC_CMD16 C25 E8 VMC_DQ16
21 VMA_CMD17 Y33 FBA_CMD17 FBA_D16 G31 22 VMC_CMD17 E22 FBC_CMD17 FBC_D17 F8
21 VMA_CMD18 U32 F30 VMA_DQ17 22 VMC_CMD18 C20 F10 VMC_DQ18
21 VMA_CMD19 Y31 FBA_CMD19 FBA_D18 G30 22 VMC_CMD19 B22 FBC_CMD19 FBC_D19 F9
21 VMA_CMD20 U34 G32 VMA_DQ19 22 VMC_CMD20 A19 F12 VMC_DQ20
21 VMA_CMD21 Y35 FBA_CMD21 FBA_D20 K30 22 VMC_CMD21 D22 FBC_CMD21 FBC_D21 D8
21 VMA_CMD22 W34 K32 VMA_DQ21 22 VMC_CMD22 D20 D11 VMC_DQ22
VMA_CMD23 V30 FBA_CMD22 FBA_D21 VMA_DQ22 VMC_CMD23 E19 FBC_CMD22 FBC_D22 VMC_DQ23
T2 FBA_CMD23 FBA_D22 H30 T8 FBC_CMD23 FBC_D23 E11
21 VMA_CMD24 U35 K31 VMA_DQ23 22 VMC_CMD24 D19 D12 VMC_DQ24
21 VMA_CMD25 U30 FBA_CMD25 FBA_D24 L31 22 VMC_CMD25 F18 FBC_CMD25 FBC_D25 E13
21 VMA_CMD26 U33 L30 VMA_DQ25 22 VMC_CMD26 C19 F13 VMC_DQ26
21 VMA_CMD27 AB30 FBA_CMD27 FBA_D26 M32 22 VMC_CMD27 F22 FBC_CMD27 FBC_D27 F14
21 VMA_CMD28 AB33 N30 VMA_DQ27 22 VMC_CMD28 C23 F15 VMC_DQ28
21 VMA_CMD29 T33 FBA_CMD29 FBA_D28 M30 22 VMC_CMD29 B20 FBC_CMD29 FBC_D29 E16
21 VMA_CMD30 W29 P31 VMA_DQ29 22 VMC_CMD30 A20 F16 VMC_DQ30
FBA_D30 R32 FBC_D31 F17
VMA_DM0 P32 R30 VMA_DQ31 VMC_DM0 A16 D29 VMC_DQ32
VMA_DM1 FBA_DQM0 FBA_D31 VMA_DQ32 VMC_DM1 FBC_DQM0 FBC_D32 VMC_DQ33
H34 FBA_DQM1 FBA_D32 AG30 D10 FBC_DQM1 FBC_D33 F27
VMA_DM2 J30 AG32 VMA_DQ33 VMC_DM2 F11 F28 VMC_DQ34
VMA_DM3 FBA_DQM2 FBA_D33 VMA_DQ34 VMA_CMD25 R16 ES@10K/F_4 VMC_DM3 FBC_DQM2 FBC_D34 VMC_DQ35
P30 FBA_DQM3 FBA_D34 AH31 D15 FBC_DQM3 FBC_D35 E28
B VMA_DM4 AF32 AF31 VMA_DQ35 VMC_DM4 D27 D26 VMC_DQ36 B
AL32 FBA_DQM5 FBA_D36 AF30 D34 FBC_DQM5 FBC_D37 F25
VMA_DM6 AL34 AE30 VMA_DQ37 VMC_DM6 A34 D24 VMC_DQ38
AF35 FBA_DQM7 FBA_D38 AC32 D28 FBC_DQM7 FBC_D39 E25
AD30 VMA_DQ39 E32 VMC_DQ40
VMA_WDQS0 FBA_D39 VMA_DQ40 VMA_CMD27 R20 ES@10K/F_4 VMC_WDQS0 FBC_D40 VMC_DQ41
L34 FBA_DQS_WP0 FBA_D40 AN33 C14 FBC_DQS_WP0 FBC_D41 F32
VMA_WDQS1 H35 AL31 VMA_DQ41 VMC_WDQS1 A10 D33 VMC_DQ42
VMA_WDQS2 FBA_DQS_WP1 FBA_D41 VMA_DQ42 VMA_CMD28 R11 ES@10K/F_4 VMC_WDQS2 FBC_DQS_WP1 FBC_D42 VMC_DQ43
J32 FBA_DQS_WP2 FBA_D42 AM33 E10 FBC_DQS_WP2 FBC_D43 E31
VMA_WDQS3 N31 AL33 VMA_DQ43 VMC_WDQS3 D14 C33 VMC_DQ44
VMA_WDQS4 FBA_DQS_WP3 FBA_D43 VMA_DQ44 VMC_WDQS4 FBC_DQS_WP3 FBC_D44 VMC_DQ45
AE31 FBA_DQS_WP4 FBA_D44 AK30 E26 FBC_DQS_WP4 FBC_D45 F29
VMA_WDQS5 AJ32 AK32 VMA_DQ45 VMC_CMD25 R32 11EP@10K/F_4 VMC_WDQS5 D32 D30 VMC_DQ46
VMA_WDQS6 FBA_DQS_WP5 FBA_D45 VMA_DQ46 VMC_WDQS6 FBC_DQS_WP5 FBC_D46 VMC_DQ47
AJ34 FBA_DQS_WP6 FBA_D46 AJ30 A32 FBC_DQS_WP6 FBC_D47 E29
VMA_WDQS7 AC33 AH30 VMA_DQ47 VMC_CMD16 R22 11EP@10K/F_4 VMC_WDQS7 B26 B29 VMC_DQ48
FBA_DQS_WP7 FBA_D47 VMA_DQ48 FBC_DQS_WP7 FBC_D48 VMC_DQ49
FBA_D48 AH33 FBC_D49 C31
VMA_RDQS0 L35 AH35 VMA_DQ49 VMC_CMD0 R35 11EP@10K/F_4 VMC_RDQS0 B14 C29 VMC_DQ50
VMA_RDQS1 FBA_DQS_RN0 FBA_D49 VMA_DQ50 VMC_RDQS1 FBC_DQS_RN0 FBC_D50 VMC_DQ51
G35 FBA_DQS_RN1 FBA_D50 AH34 B10 FBC_DQS_RN1 FBC_D51 B31
VMA_RDQS2 H31 AH32 VMA_DQ51 VMC_CMD27 R27 11EP@10K/F_4 VMC_RDQS2 D9 C32 VMC_DQ52
N32 FBA_DQS_RN3 FBA_D52 AJ33 E14 FBC_DQS_RN3 FBC_D53 B32
VMA_RDQS4 AD32 AL35 VMA_DQ53 VMC_CMD28 R24 11EP@10K/F_4 VMC_RDQS4 F26 B35 VMC_DQ54
AJ31 FBA_DQS_RN5 FBA_D54 AM34 D31 FBC_DQS_RN5 FBC_D55 B34
VMA_RDQS6 AJ35 AM35 VMA_DQ55 VMC_RDQS6 A31 A29 VMC_DQ56
AC34 FBA_DQS_RN7 FBA_D56 AF33 Un-stuff for N11M A26 FBC_DQS_RN7 FBC_D57 B28
12/02 modify AE32 VMA_DQ57 Stuff for N11P ,N11E A28 VMC_DQ58
FBA_D57 VMA_DQ58 FBC_D58 VMC_DQ59
package for N10 P29 FBA_WCK0 FBA_D58 AF34 12/02 modify G14 FBC_WCK0 FBC_D59 C28
R29 AE35 VMA_DQ59 package for N10 G15 C26 VMC_DQ60
FBA_WCK0_N FBA_D59 VMA_DQ60 FBC_WCK0_N FBC_D60 VMC_DQ61
L29 FBA_WCK1 FBA_D60 AE34 G11 FBC_WCK1 FBC_D61 D25
VMA_DQ61 VMC_DQ62
M29
AG29
FBA_WCK1_N FBA_D61 AE33
AB32 VMA_DQ62 11EP@ --> N11P/N11E-GE1 Setting G12
G27
FBC_WCK1_N FBC_D62 B25
A25 VMC_DQ63
FBA_WCK2 FBA_D62 VMA_DQ63 FBC_WCK2 FBC_D63
AH29 FBA_WCK2_N FBA_D63 AC35 G28 FBC_WCK2_N
C AD29 FBA_WCK3 G24 FBC_WCK3 C
+1.5V_GFX AE29 T32 +1.5V_GFX G25 E17
FBA_WCK3_N FBA_CLK0 VMA_CLKP0 21 FBC_WCK3_N FBC_CLK0 VMC_CLKP0 22
FBA_CLK0* T31 VMA_CLKN0 21 FBC_CLK0* D17 VMC_CLKN0 22
FBA_CLK1 AC31 VMA_CLKP1 21 FBC_CLK1 D23 VMC_CLKP1 22
AA27 FBVDDQ_1 FBA_CLK1* AC30 VMA_CLKN1 21 N27 FBVDDQ_28 FBC_CLK1* E23 VMC_CLKN1 22
AA29 FBVDDQ_2 P27 FBVDDQ_29
AA31 FBVDDQ_3 R27 FBVDDQ_30
AB27 FBVDDQ_4 T27 FBVDDQ_31
AB29 J27 +FB_VREF1 T4 U27
FBVDDQ_5 FB_VREF FBVDDQ_32
AC27
AD27
FBVDDQ_6
15mils width
U29
V27
FBVDDQ_33 MEMORY I/F C
FBVDDQ_7 FBVDDQ_34
AE27 FBVDDQ_8 V29 FBVDDQ_35
AJ28 FBVDDQ_9 V34 FBVDDQ_36
B18 W27 K27 FB_CAL_PD_VDDQ R26 ES@40.2/F_4 +1.5V_GFX
FBVDDQ_10 FBVDDQ_37 FB_CAL_PD_VDDQ
E21 FBVDDQ_11 Y27 FBVDDQ_38
G17 FBVDDQ_12
G18 L27 FB_CAL_PU_GND R25 ES@40.2/F_4
FBVDDQ_13 FB_CAL_PU_GND
G22 FBVDDQ_14
G8
G9
FBVDDQ_15 MEMORY I/F A M27 FB_CAL_TERM_GND R18 VSP@40.2/F_4
FBVDDQ_16 FB_CAL_TERM_GND
H29 FBVDDQ_17 For Debug only
J14 FBVDDQ_18
2/16
J15 T30 FBA_DEBUG R19 *ES@10K/F_4 +1.5V_GFX G19 FBC_DEBUG R33 *ES@10K/F_4 +1.5V_GFX
FBVDDQ_19 FBA_DEBUG FBC_DEBUG
J16 FBVDDQ_20
J17 15mils width +1.5V_GFX
FBVDDQ_21 ES@PBY160808T-301Y-N_6
J20 FBVDDQ_22 +FB_PLLAVDD L1 N11P/N11E-GE1 Stuff 40.2 ohm
J21
J22
FBVDDQ_23 FB_DLLAVDD0 AG27 +1.05V_GFX
C107 ES@.01u/25V_4 NC/ FB_DLLAVDD1 J19
VSP@
FBVDDQ_24 C45 ES@4.7U/6.3V_6 C52 ES@.01u/25V_4
J23 FBVDDQ_25 FB_PLLAVDD0 AF27 NC/ FB_PLLAVDD1 J18 N11M-GE1 Stuff 60.4 ohm
D J24 C54 ES@1U/6.3V_4 C57 ES@.01u/25V_4 D
FBVDDQ_26 C53 ES@.1u/10V_4 C47 ES@.01u/25V_4
J29 FBVDDQ_27 C44 ES@.1u/10V_4
C101 ES@.1u/10V_4
C56 ES@.1u/10V_4
C59 ES@0.047U/10V_4
C79 ES@0.047U/10V_4
C58 ES@0.047U/10V_4 Quanta Computer Inc.
C48 ES@4.7U/6.3V_6
C86 ES@4.7U/6.3V_6
PROJECT : ZR7
All need stuff for N10P N11P-GE (MEMORY I/F) 2/5 3B

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
ES@ --> External VGA SKU

VSP@ --> Operation P/N (VGA) fcbga973-nvidia-n11p-es-a1
COMMON
ES@FBMA-10-160808-300T_6 U33D
+1.05V_GFX L8 +IFPAB_PLLVDD 220 mA AK9 AM11 EV_TXLCLKOUT+ 23
IFPAB_PLLVDD IFPA_TXC
IFPA_TXC* AM12 EV_TXLCLKOUT- 23
C170 ES@1U/6.3V_4 IFPAB(LVDS) IFPA_TXD0 AM8
AL8
EV_TXLOUT0+ 23
EV_TXLOUT0- 23
C169 ES@4.7U/6.3V_6 IFPA_TXD0*
IFPA_TXD1 AM10 EV_TXLOUT1+ 23
AM9 EV_TXLOUT1- 23
LVDS clk spread : Center
IFPA_TXD1*
10/20 Del C3647 IFPA_TXD2 AK10 EV_TXLOUT2+ 23 +/-0.5% ( 30~33KHZ)
IFPA_TXD2* AL10 EV_TXLOUT2- 23
A R49 *ES@1K/F_4 IFPAB_RSET AJ11 AK11 A
IFPAB_RSET IFPA_TXD3
IFPA_TXD3* AL11
ES@FBMA-10-160808-300T_6
+1.8V_GFX L9 +IFPAB_IOVDD 200 mA AG9
AG10
IFPA_IOVDD IFPB_TXC AP13
AN13
EV_TXUCLKOUT+ 23
EV_TXUCLKOUT- 23
IFPB_IOVDD IFPB_TXC*
IFPB_TXD4 AN8 EV_TXUOUT0+ 23
C146 ES@.1u/10V_4 AP8 11/16 Change LVDS to two channel.
IFPB_TXD4* EV_TXUOUT0- 23
C176 ES@.1u/10V_4 AP10
IFPB_TXD5 EV_TXUOUT1+ 23
C179 ES@1U/6.3V_4 AN10
IFPB_TXD5* EV_TXUOUT1- 23
C184 ES@4.7U/6.3V_6 AR11
IFPB_TXD6 EV_TXUOUT2+ 23
IFPB_TXD6* AR10 EV_TXUOUT2- 23
IFPB_TXD7 AN11
ES@FBMA-10-160808-300T_6 220 mA IFPB_TXD7* AP11
+3V_GFX L11 +IFPCD_PLLVDD AJ9 AN3 MXM_DDCDAT_C MXM_DDCDAT_C 24

IFPCD_PLLVDD/ I2CW_SDA/ IFPC_AUX_N MXM_DDCCK_C
C160 ES@.1u/10V_4 IFPC_PLLVDD I2CW_SCL/ IFPC_AUX AP2 MXM_DDCCK_C 24 10/20 +3V_GFX
AC6 DACB_VDD/ IFPC_L3_N AR2 HDMICLK- 24
C178 ES@1U/6.3V_4 AP1
IFPD_PLLVDD IFPC_L3 HDMICLK+ 24
C180 ES@.1u/10V_4 AM4
IFPC_L2_N HDMITX0N 24 +3V_S5
C145 ES@.1u/10V_4 IFPC AM3
IFPC_L2 HDMITX0P 24
C186 ES@4.7U/6.3V_6 AM5 10/23 Modify R480
IFPC_L1_N HDMITX1N 24
ES@10K_4
IFPC_L1 AL5
AM6
HDMITX1P 24 GPU all PWROK
IFPC_L0_N HDMITX2N 24
IFPC_L0 AM7 HDMITX2P 24
R60 ES@1K/F_4 IFPC_RSET AK7 AN4 R484 dGPU_PWROK 11,36
R59 ES@1K/F_4 IFPD_RSET IFPCD_RSET/ IFPC_RSET I2CX_SDA/ IFPD_AUX_N ES@10K_4
AB6 DACB_RSET/ IFPD_RSET I2CX_SCL/ IFPD_AUX AP4
3
IFPD_L3_N AR4
IFPCD IFPD_L3 AR5
ES@MLB-201209-0030P-N1-RU_8 285 mA AJ8 IFPD

IFPD_L2_N AP5
AN5 TMDS channel two 2 Q38
L7 +IFPCD_IOVDD IFPC_IOVDD IFPD_L2 ES@2N7002D
B (1.05V +/- 3% ) +1.05V_GFX AK8 IFPD_IOVDD IFPD_L1_N AN7
AP7
B
IFPD_L1
3
C168 ES@.1u/10V_4 AR7
C165 ES@.1u/10V_4 IFPD_L0_N
AR8
1
C158 ES@1U/6.3V_4 IFPD_L0
+1.8V_GFX 2
C173 ES@4.7U/6.3V_6 AE4
I2CY_SCL/ IFPE_AUX
I2CY_SDA/ IFPE_AUX* AD4
AH6 Q39
1
IFPE_L0 ES@PDTC143TT
AL1 IFPEF_RSET IFPE_L0* AH5
IFPE_L1 AH4
IFPEF IFPE_L1* AG4
AF4
R56 ES@10K/F_4 IFPEF_PLLVDD IFPE_L2
AJ6 IFPEF_PLLVDD IFPE_L2* AF5
R67 ES@10K/F_4 IFPEF_IOVDD AE7 AE6
IFPE_IOVDD IFPE_L3
AD7 IFPF_IOVDD IFPE_L3* AE5 Display port output
I2CZ_SCL/ IFPF_AUX AF3
I2CZ_SDA/ IFPF_AUX* AF2
AL2 +3V_GFX
IFPF_L0
ES@PBY160808T-301Y-N_6 IFPF_L0* AL3 10/20 STUFF
IFPF_L1 AJ3
+3V_GFX L6 C153 ES@.1u/10V_4 AJ2
C150 ES@.1u/10V_4 IFPF_L1* R75 ES@4.7K_4 EV_CRTDCLK
IFPF_L2 AJ1
C154 ES@.1u/10V_4 AH1
IFPF_L2* R84 ES@4.7K_4 EV_CRTDDAT
IFPF_L3 AH2
IFPF_L3* AH3
+DACA_VDD 120 mA AJ12 AM15 EV_CRT_RED EV_CRT_RED 23

DACA_VDD DACA_RED R468 ES@4.7K_4 MXM_DDCCK_C
C157 ES@1U/6.3V_4 DACA(CRT) AM14 EV_CRT_GRN EV_CRT_GRN 23
C164 ES@4.7U/6.3V_6 DACA_GREEN R463 ES@4.7K_4 MXM_DDCDAT_C
C C
C155 ES@4700P/25V_4 AL14 EV_CRT_BLU EV_CRT_BLU 23
C156 ES@470p/X7R_4 DACA_BLUE
AM13 EV_HSYNC_R R450 ES@33_4 EV_HSYNC 23
DACA_HSYNC EV_VSYNC_R R453 ES@33_4
DACA_VSYNC AL13 EV_VSYNC 23
C140 ES@.1u/10V_4 DACA_VREF AK12
R48 ES@124/F_4 DACA_RSET DACA_VREF EV_CRTDCLK EV_CRT_RED R36 ES@150/F_4
AK13 DACA_RSET I2CA_SCL G1 EV_CRTDCLK 23
G4 EV_CRTDDAT EV_CRTDDAT 23
I2CA_SDA EV_CRT_GRN R38 ES@150/F_4
R52 ES@10K/F_4 +DACB_VDD AG7 AK4
DACC_VDD/ /DACC_RED EV_CRT_BLU R40 ES@150/F_4
AK6
DACB_VDD DACC(CRT2) DACB_RED
AL4
DACC_VREF/ /DACC_GREEN
DACB_VREF DACB_GREEN
AH7 DACC_RSET/ /DACC_BLUE AJ4
DACB_RSET DACB_BLUE +3V_GFX
DACB_HSYNC/ DACC_HSYNC AM1
DACB_VSYNC/ DACC_VSYNC AM2
G3 I2CB_SCL R477 ES@2.2K_4

I2CB_SCL I2CB_SDA R476 ES@2.2K_4
I2CB_SDA G2
AA4 PLACE CLOSE TO GPU

NC/ DACB_RED XTAL_SSIN R472 ES@10K/F_4
AC5 DACB(TV) NC/ DACB_GREEN AB4
Y4
DACB_VREF/ NC NC/ DACB_BLUE DACB_CSYNC R61 ES@10K/F_4 BXTALOUT R70 ES@10K/F_4
CEC/ DACB_CSYNC AB5
+1.05V_GFX
ES@100nH_6
L4 +NV_PLLVDD 60mA AE9 D2 XTAL_SSIN R91 *ES@22_4 CLK_27M_SS 3 10 k pull-down only if no spread chip used.
PLLVDD XTAL_SSIN BXTALOUT
XTAL_OUTBUFF D1
C136 ES@.1u/10V_4 AD9
C147 ES@.1u/10V_4 VID_PLLVDD XTALI_27M R471 *ES@0_4
D XTAL_IN B1 27M_CLK 3 D
C148 ES@1U/6.3V_4
C137 ES@4.7U/6.3V_6 XTAL_PLL B2 XTALO_27M 2 1
XTAL_OUT
STUFF PDs on XTALSSIN and
Y3 XTALOUTBUFF WHEN
ES@100nH_6
L10 +NV_SPPLLVDD 45mA AF9 C601
ES@27MHZ
C600
EXT_SS IS NOT USED
+1.05V_GFX SP_PLLVDD Quanta Computer Inc.
ES@27P/50V_4 ES@27P/50V_4
C177 ES@1U/6.3V_4
C185 ES@4.7U/6.3V_6 PROJECT : ZR7
10/20 Del C3515 3B
N11P-GE (DISPLAY) 3/5
11/27 Modify C601,C600 to 27pF Date: Monday, February 22, 2010 Sheet 18 of 49
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+3V_GFX 11EP@ --> N11P/N11E-GE1 Setting Logical Logical Logical Logical

10/20 Add Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
fcbga973-nvidia-n11p-es-a1
ROM_SO NB10X 0001

U33E COMMON
11P@ --> N11P-GE1 Setting XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE
R44 ES@0_6 P9 N1
MIOA_VDDQ_1 MIOA_D0 T89
R9 MIOA_VDDQ_2 MIOA MIOA_D1 P4 T96 11M@ --> N11M-GE1 Setting ROM_SCLK PCI_DEVIDE[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM X010
T9 MIOA_VDDQ_3 MIOA_D2 P1 T70
C138 10/20 U9 MIOA_VDDQ_4 MIOA_D3 P2 T83 ES@ --> External VGA SKU ROM_SI RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0] XXXX
MIOA_D4 P3 T95
ES@.1U/10V_4 T3 VSP@ --> Operation P/N (VGA) STRAP2 PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] XXXX
Notice MIOA_D5
MIOA_D6
T2
T88
T82
N11M/N11P : Stuff 0 ohm MIOA_D7 T1 T75 SW@ --> iGPU & dGPU Switch STRAP1 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0] 1110
U4 T74
N11X-FERMI : UnStuff 0 ohm U5
MIOA_D8
U1 STRAP0 USER[3] USER[2] USER[1] USER[0] 1111
MIOA_CAL_PD_VDDQ MIOA_D9
U2
T87 EV@ --> dGPU only
A MIOA_D10 T94 A
MIOA_D11 U3 T81 VRAM Configuration Table
T5 R6
Notice MIOA_CAL_PU_GND MIOA_D12
MIOA_D13
T6
N11M/N11P : Stuff 0.1uF N6 RAMCFG
N11X-FERMI : Stuff 10K ohm N5
MIOA_VREF
MIOA_D14
MIOA_CTL3
P5
N3
[3:0]
0000
DESCRIPTION Vendor
Reserved
Vendor P/N ROM_SI
(Ra)
MIOA_HSYNC
MIOA_VSYNC
L3 0001 DDR3 64Mx16x8, 128bit, 1GB,800MHz Qimonda IDGH1G-04A1F1C-16X PD 10K
MIOA_DE N2 0010 DDR3 64Mx16x8, 128bit, 1GB,800MHz Hynix H5TQ1G63BFR-12C PD 15K AKD5LZGTW04
0011 DDR3 64Mx16x8, 128bit, 1GB,800MHz Samsung K4W1G1646E-HC12 PD 20K AKD5LGGT506
MIOA_CLKOUT R4 0101 Reserved
+3V_GFX 10/20 Add T4 0110
MIOA_CLKOUT* MIOA_CLKIN
MIOA_CLKIN N4 XXXX DDR3 64Mx16x8, 128bit, 1GB,667MHz Hynix H5TQ1G63AFR-14C
R475 ES@10K/F_4 XXXX DDR3 64Mx16x8, 128bit, 1GB,667MHz Samsung K4W1G1646D-EC12
R74 ES@0_6 AA9 Y1
MIOB_VDDQ_1 MIOB_D0 T80
AB9 MIOB_VDDQ_2 MIOB MIOB_D1 Y2 T86 +3V_GFX +3V_GFX
C139
W9 MIOB_VDDQ_3 MIOB_D2 Y3 T79 Logical Strap Bit Mapping VSP@ 11P@
10/20 Y9
MIOB_VDDQ_4 MIOB_D3
AB3 T73 N11E-GE1 N11P-GE1
ES@.1U/10V_4 MIOB_D4 AB2
AB1
T93 PU PD N11M-GE1 Setting
Notice MIOB_D5
MIOB_D6
AC4
T85
T92 5K 1000 0000 Setting
N11M/N11P : Stuff 0 ohm MIOB_D7 AC1 T72
N11X-FERMI : UnStuff 0 ohm MIOB_D8
AC2 T78 10K 1001 0001
AA7 AC3 T91
MIOB_CAL_PD_VDDQ MIOB_D9
MIOB_D10 AE3 T71 15K 1010 0010 R491
*ES@20K/F_4
R482
*ES@4.99K/F_4
R481
VSP@15K/F_4
R71
ES@45.3K/F_4
R68
ES@35.7K/F_4
R490
11P@10K/F_4
AE2 T77
MIOB_D11
Notice AA6
MIOB_CAL_PU_GND MIOB_D12
U6 20K 1011 0011 ROM_SI
ROM_SO
STRAP0
STRAP1
MIOB_D13 W6
N11M/N11P : Stuff 0.1uF MIOB_D14
Y6
STRAP0
25K 1100 0100 ROM_SCLK STRAP2
W5
N11X-FERMI : Stuff 10K ohm STRAP0
AF1
MIOB_VREF STRAP1
W7 STRAP1
STRAP2
30K 1101 0101 VSP@
V7
STRAP2
35K 1110 0110
B R485 R473 R478 R64 R73 R489 B
MIOB_CTL3
MIOB_HSYNC
W3
W1
W2
45K 1111 0111 (Ra) VSP@15K/F_4 ES@10K/F_4 11P@15K/F_4
11P@
*ES@2K/F_4
*ES@35.7K/F_4
VSP@30.1K/F_4
MIOB_VSYNC
MIOB_DE Y5 N11P-GE1 VSP@
Default: Hynix VRAM Setting N11E-GE1
MIOB_CLKOUT
MIOB_CLKOUT*
V4
W4 VSP@ Hynix =15K pull down(64Mx16)
Samsung =20k pull down(64Mx16)
N11M-GE1
MIOB_CLKIN
AE1 MIOB_CLKIN Setting
R66 ES@10K/F_4
20 GPU_D- B4
THERMDN GPIO0
K1 T76 CHIP ROM_SCLK STRAP2 PCI_DEVID 4.99K/F_4: CS24992FB26 [RES CHIP 4.99K 1/16W +1%(0402)]
GPIO1
K2 HDMI_HP_EV 24 10K/F_4: CS31002FB26 [RES CHIP 10K 1/16W +1% (0402)]
GPIO2 K3 EV_LVDS_BRIGHT EV_LVDS_BRIGHT 23 N11M-GE1 PU 15K PD 30K 0x0A75 15K/F_4: CS31502FB24 [RES CHIP 15K 1/16W +1% (0402)]
20 GPU_D+ B5 H3 EV_LVDS_VDDEN EV_LVDS_VDDEN 23 20K/F_4: CS32002FB29 RES CHIP 20K 1/16W +-1%(0402)
THERMDP GPIO3
GPIO4
H2 EV_LVDS_BLON EV_LVDS_BLON 23 N11P-GE1 PD 15K PU 10K 0x0A29 30.1K/F_4: CS33012FB18 [RES CHIP 30.1K 1/16W +-1%(0402)]
H1 GPU_VID1 GPU_VID1 43,47 35.7K/F_4: CS33572FB13 [RES CHIP 35.7K 1/16W +-1%(0402)]
GPIO5
T66 JTAG_TCK AP14
JTAG_TCK MISC1 GPIO6
H4 GPU_VID2 GPU_VID2 43,47 N11E-GE1 PU 15K PD 5K 0x0CB0 45.3K/F_4: CS34532FB18 [RES CHIP 45.3K 1/16W +-1% (0402)]
T67 JTAG_TMS AR14 H5 T90
JTAG_TDI JTAG_TMS (GPIOS,JTAG,THERM,I2C) GPIO7 VGA_OVT#
T68 AN14 H6
JTAG_TDO JTAG_TDI GPIO8 ALERT#
T65 AN16 J7 ALERT# 20
JTAG_TRST# JTAG_TDO GPIO9 +3V_GFX
AP16 K4
T64
SMB_CLK_VGA E2
JTAG_TRST* GPIO10
GPIO11
GPIO12
K5
H7
J4
VGA_ACIN
T84
T9
10/20 Modify DGPU_IDLE_INT# R486 ES@10K/F_4
10/20
GPIO ASSIGNMENTS
SMB_DATA_VGA I2CS_SCL GPIO13 GPU_VID2 R57 *ES@10K/F_4
E1 J6
R63 ES@33_4 I2CC_SCL_G I2CS_SDA GPIO14 GPU_VID1 R83 11EP@10K/F_4
23 EV_LVDS_DDCCLK E3 L1
R62 ES@33_4 I2CC_SDA_G I2CC_SCL GPIO15
23 EV_LVDS_DDCDAT E4 L2
I2CC_SDA GPIO16 JTAG_TMS R444 *ES@10K/F_4
F4 I2CD_SCL/ NC GPIO17 L4
G5 M4 DGPU_IDLE_INT# JTAG_TDI R447 *ES@10K/F_4
I2CD_SDA/ NC GPIO18 VGA_OVT# R82 ES@10K/F_4
D5 I2CE_SCL/ NC GPIO19 L7
E5 L5 ALERT# R85 ES@10K/F_4
I2CE_SDA/ NC GPIO20
K6
C +3V_GFX GPIO21 JTAG_TRST# R441 ES@1K/F_4 C
GPIO22
L6 11EP@ --> N11P/N11E-GE1 Setting 10/16
10/20 STUFF GPIO23
M6
J26 C3 JTAG_TCK R443 *ES@10K/F_4 GPIO I/O ACTIVE USAGE

R76 ES@4.7K_4 EV_LVDS_DDCCLK BBIASN_NC ROM_CS* ROM_SI HDMI_HP_EV R72 *ES@2.2K/J_4
J25
BBIASP_NC MISC2(ROM) ROM_SI
D3
ROM_SO
ROM_SO
C4 A5 N.C due to N11X HAD 0 N/A N/A
R69 ES@4.7K_4 EV_LVDS_DDCDAT D7 D4 ROM_SCLK function is through 10/16
HDA_BCLK/ NC ROM_SCLK EV_LVDS_BRIGHT R65 ES@10K/F_4
D6
C7
HDA_RST*/ NC
F6 HDCP_SCL PCI-E interface 1 IN N/A Hot plug detect for IFP link C
HDA_SDI/ NC I2CH_SCL HDCP_SDA EV_LVDS_VDDEN R90 ES@10K/F_4
B7
A7
HDA_SDO/ NC I2CH_SDA
G6 2 OUT HIGH PANEL BACKLIGHT PWM
HDA_SYNC/ NC SPDIF_VGA EV_LVDS_BLON R81 ES@10K/F_4
R45 ES@40.2K/F_4 STRAP_REF_3V3 N9
SPDIF
A5 T69 3 OUT HIGH PANEL POWER ENABLE
R41 ES@40.2K/F_4 STRAP_REF_MIOB STRAP_REF_3V3/ MULTI_STRAP_REF0_GND
M9 STRAP_REF_MIOB/ MULTI_STRAP_REF1_GND BUFRST* A4
C5
4 OUT HIGH PANEL BACKLIGHT ENABLE
NC
AK14
5 OUT N/A NVVDD VID0
GND
VGA Thermal GND/ NC
K9
HDCP ROM 6 OUT N/A NVVDD VID1
ADDRESS: 9AH R100 EV@0_4
7 OUT N/A NVVDD VID2 11/13
+3V_GFX +3V_GFX
11/4 Modify.
U28
SMB_CLK_VGA 1 3 1 8 C555 *ES@.1u/10V_4
8 I/O LOW OVERT
MXM_SMCLK12 20,36 A0 VCC
10/20 9 I/O LOW ALERT
R103 Q9 +3V_GFX R93 +3V_GFX 2 7 R429 *ES@10K/F_4
SW@4.7K_4 SW@2N7002D *10K_4 A1 WP
10 OUT N/A FBVREF SELECT
2
Q6 3 6 HDCP_SCL
A2 SCL
2
SW@2N7002D R431 ES@2.2K_4

R96
+3V_GFX
VGA_ACIN 3 1 4 HDCP_SDA
+3V_GFX 11 OUT N/A SLI SYNC0
GND SDA 5
47K
SW@4.7K_4 VGA_OVT# R430 ES@2.2K_4

1 3 VGA_THERM# 20,36 12 IN N/A PWR_LEVEL11/13
2
Q7 *ES@AT88SC0808C-SU
10K
SW@2N7002D R112
D SMB_DATA_VGA 1 3 R94 *ES@10K_4
13 OUT N/A MEM_VID or power supply control D
MXM_SMDATA12 20,36
R89 EV@0_4 *0_4 Fill U36 to correct p/n as Top B/S P/N(AR0QT6VB002) 14 OUT N/A PS CONTROL
2
+3V_GFX Q10 DHCP ROM

3
R95 EV@0_4 *ES@DTA114YUA

Q43 Low: Crypto ROM
2
SW@2N7002D HDCP_SCL
EV@ --> dGPU only DGPU_IDLE_INT#
36,37 ACIN 2 Hi: I2C ROM Quanta Computer Inc.
1 3 DGPU_IDLE# 36
Q11
*ES@2N7002D HDCP ROM reserve , Due to N11x had PROJECT : ZR7
1
R488 EV@0_4 support internal HDCP function. Size Document Number Rev
SW@ --> iGPU & dGPU Switch 10/20 3B
N11P-GE (GPIO&STRAPS) 4/5
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+3V_GFX
ES@ --> External VGA SKU Thermal Sensor
NS none
VSP@ --> Operation P/N (VGA)
WINDBOND AL83L771K02
U33F U33G R427
2
*ES@10K_4 GMT AL000780003
+VGPU_CORE fcbga973-nvidia-n11p-es-a1
+VGPU_CORE fcbga973-nvidia-n11p-es-a1
COMMON COMMON
19,36 MXM_SMCLK12 3 1
AB11 P21 AA11 E15 Q30

VDD_001 VDD_057 GND_1 GND_096 *ES@2N7002D
AB13 P23 AA12 E18
VDD_002 VDD_058 GND_2 GND_097 +3V_GFX
AB15
VDD_003 NVVDD VDD_059
P25 AA13
GND_3 GND_098
E24
A AB17
AB19
VDD_004 VDD_060
R11
R12
AA14
AA15
GND_4 GROUND GND_099
E27
E30 +3V_GFX
A
VDD_005 VDD_061 GND_5 GND_100 *ES@.1u/10V_4
AB21 R13 AA16 E6
VDD_006 VDD_062 GND_6 GND_101 *ES@10K_4 C553
AB23 R14 AA17 E9
VDD_007 VDD_063 GND_7 GND_102 R426
AB25 R15 AA18 F2
VDD_008 VDD_064 GND_8 GND_103
2
AC11 R16 AA19 F31
VDD_009 VDD_065 GND_9 GND_104 U27
AC12 R17 AA2 F34
AC13 R18 AA20 F5 19,36 MXM_SMDATA12 3 1
VDD_011 VDD_067 GND_11 GND_106 GPU_SMCLK
AC14 R19 AA21 J2 8 1 GPU_D+ 19
VDD_012 VDD_068 GND_12 GND_107 SCLK VCC
AC15 R20 AA22 J31
VDD_013 VDD_069 GND_13 GND_108 Q31 GPU_SMDATA C554
AC16 R21 AA23 J34 7 2
VDD_014 VDD_070 GND_14 GND_109 *ES@2N7002D SDA DXP
AC17 R22 AA24 J5
VDD_015 VDD_071 GND_15 GND_110 *ES@2200p/50V_4
AC18 R23 AA25 L9 19 ALERT# 6 3
VDD_016 VDD_072 GND_16 GND_111 ALERT# DXN
AC19 R24 AA34 M11 GPU_D- 19
AC20 R25 AA5 M13 19,36 VGA_THERM# 4 5
VDD_018 VDD_074 GND_18 GND_113 OVERT# GND
AC21 T12 AB12 M15
AC22
VDD_020 VDD_076
T14 AB14
GND_20 GND_115
M17 10/20 Modify
AC23 T16 AB16 M19 *ES@G780-1P81U(MSOP)
AC24
VDD_022 VDD_078
T18 AB18
GND_22 GND_117
M2 ADDRESS: 9AH
AC25 T20 AB20 M21
AD12 T22 AB22 M23
AD14 T24 AB24 M25
AD16 V11 AC9 M31
AD18 V13 AD11 M34
AD22 V15 AD13 M5
AD24 V17 AD15 N11
L11 V19 AD17 N12
L12 V21 AD2 N13
L13 V23 AD21 N14
B L14 V25 AD23 N15 B
L15 W11 AD25 N16
L16 W12 AD31 N17
L17 W13 AD34 N18
L18 W14 AD5 N19
L19 W15 AE11 N20
L20 W16 AE12 N21
L21 W17 AE13 N22
L22 W18 AE14 N23
L23 W19 AE15 N24
L24 W20 AE16 N25
L25 W21 AE17 P12
M12 W22 AE18 P14
M14 W23 AE19 P16
M16 W24 AE20 P18
M18 W25 AE21 P20
M20 Y12 AE22 P22
M22 Y14 AE23 P24
M24 Y16 AE24 R2
P11 Y18 AE25 R31
P13 Y20 AG2 R34
P15 Y22 AG31 R5
P17 Y24 AG34 T11
P19 AG5 T13
VDD_056 GND_56 GND_151
AK2 T15
GND_57 GND_152
AK31 T17
GND_58 GND_153
AK34 T19
GND_59 GND_154
AK5 T21
GND_60 GND_155
AL12 T23
GND_61 GND_156
C AL15 T25 C
GND_62 GND_157
AL18 U11
GND_63 GND_158
AL21 U12
GND_64 GND_159
AL24 U13
GND_65 GND_160
AL27 U14
GND_66 GND_161
AL30 U15
GND_67 GND_162
NVVDD Decoupling AL6
GND_68 GND_163
U16
AL9 U17
GND_69 GND_164
AN2 U18
+VGPU_CORE GND_70 GND_165
AN34 U19
GND_71 GND_166
AP12 U20
PLACE UNDER BALLS GND_72 GND_167
2/16 AP15
GND_73 GND_168
U21
C72 ES@.01u/25V_4 AP18 U22
C73 ES@.01u/25V_4 GND_74 GND_169
AP21 U23
C117 ES@.01u/25V_4 GND_75 GND_170
AP24 U24
C108 ES@.01u/25V_4 GND_76 GND_171
AP27 U25
C78 ES@.01u/25V_4 GND_77 GND_172
AP3 V12
C92 ES@.01u/25V_4 GND_78 GND_173
AP30 V14
C125 ES@0.022U/16V_4 GND_79 GND_174
AP33 V16
C95 ES@0.022U/16V_4 GND_80 GND_175
AP6 V18
C115 ES@0.022U/16V_4 GND_081 GND_176
AP9 V2
C116 ES@0.022U/16V_4 GND_082 GND_177
B12 V20
C69 ES@0.047U/25V_4 GND_083 GND_178
B15 V22
C94 ES@0.047U/25V_4 GND_084 GND_179
B21 V24
C75 ES@0.047U/25V_4 GND_085 GND_180
B24 V31
C106 ES@0.22u/6.3V_4 GND_086 GND_181
B27 V5
C91 ES@0.22u/6.3V_4 GND_087 GND_182
B3 V9
C120 ES@1U/6.3V_4 GND_088 GND_183
B30 Y11
GND_089 GND_184
B33 Y13
C113 ES@4.7U/6.3V_6 GND_090 GND_185
D B6 Y15 D
GND_091 GND_186
B9 Y17
C81 ES@10U/6.3V_6 GND_092 GND_187
C2 Y19
C105 ES@10U/6.3V_6 GND_093 GND_188
C34 Y21
GND_094 GND_189
E12 Y23
GND_095 GND_190
11/27 Modify to CC0603 GND_191
Y25
C151 ES@330u/2V_7343
+
11/25 Modify.
PROJECT : ZR7
PLACE NEAR BALLS Size Document Number Rev
3B
N11P-GE (POWER & GND&THM) 5/5
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
ES@ --> External VGA SKU 17 VMA_DQ[63..0]
CHANNEL A: 256MB/512MB DDR3

17 VMA_DM[7..0]
VSP@ --> Operation P/N (VGA-VRAM) 17 VMA_WDQS[7..0]
17 VMA_RDQS[7..0]
U2 U30 U1 U29
VREFC_VMA1 M8 E3 VMA_DQ16 VREFC_VMA1 M8 E3 VMA_DQ30 VREFC_VMA3 M8 E3 VMA_DQ45 VREFC_VMA3 M8 E3 VMA_DQ58

VREFD_VMA1 H1 VREFCA DQL0 VMA_DQ22 VREFD_VMA1 VREFCA DQL0 VMA_DQ26 VREFD_VMA3 VREFCA DQL0 VMA_DQ43 VREFD_VMA3 VREFCA DQL0 VMA_DQ63
VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 VMA_DQ18 F2 VMA_DQ29 F2 VMA_DQ44 F2 VMA_DQ56
DQL2 VMA_DQ23 VMA_CMD7 DQL2 VMA_DQ28 VMA_CMD22 DQL2 VMA_DQ41 VMA_CMD22 DQL2 VMA_DQ61
17 VMA_CMD7 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
A P7 H3 VMA_DQ19 VMA_CMD20 P7 H3 VMA_DQ31 VMA_CMD4 P7 H3 VMA_DQ47 VMA_CMD4 P7 H3 VMA_DQ59 A
17 VMA_CMD20 A1 DQL4 A1 DQL4 A1 DQL4 A1 DQL4
P3 H8 VMA_DQ20 VMA_CMD4 P3 H8 VMA_DQ25 VMA_CMD20 P3 H8 VMA_DQ40 VMA_CMD20 P3 H8 VMA_DQ57
N2 G2 VMA_DQ17 VMA_CMD14 N2 G2 VMA_DQ27 VMA_CMD9 N2 G2 VMA_DQ46 VMA_CMD9 N2 G2 VMA_DQ60
P8 H7 VMA_DQ21 VMA_CMD17 P8 H7 VMA_DQ24 VMA_CMD6 P8 H7 VMA_DQ42 VMA_CMD6 P8 H7 VMA_DQ62
P2 VMA_CMD6 P2 VMA_CMD17 P2 VMA_CMD17 P2
17 VMA_CMD6 A5 A5 A5 A5
R8 VMA_CMD26 R8 VMA_CMD3 R8 VMA_CMD3 R8
17 VMA_CMD26 A6 A6 A6 A6
R2 D7 VMA_DQ7 VMA_CMD3 R2 D7 VMA_DQ12 VMA_CMD26 R2 D7 VMA_DQ36 VMA_CMD26 R2 D7 VMA_DQ51
17 VMA_CMD3 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
T8 C3 VMA_DQ2 VMA_CMD1 T8 C3 VMA_DQ10 VMA_CMD1 T8 C3 VMA_DQ39 VMA_CMD1 T8 C3 VMA_DQ53
R3 C8 VMA_DQ5 VMA_CMD10 R3 C8 VMA_DQ15 VMA_CMD5 R3 C8 VMA_DQ32 VMA_CMD5 R3 C8 VMA_DQ50
L7 C2 VMA_DQ1 VMA_CMD21 L7 C2 VMA_DQ8 VMA_CMD19 L7 C2 VMA_DQ38 VMA_CMD19 L7 C2 VMA_DQ52
17 VMA_CMD21 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3
R7 A7 VMA_DQ6 VMA_CMD5 R7 A7 VMA_DQ13 VMA_CMD10 R7 A7 VMA_DQ33 VMA_CMD10 R7 A7 VMA_DQ48
N7 A2 VMA_DQ0 VMA_CMD22 N7 A2 VMA_DQ11 VMA_CMD7 N7 A2 VMA_DQ37 VMA_CMD7 N7 A2 VMA_DQ54
17 VMA_CMD22 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
T3 B8 VMA_DQ4 VMA_CMD18 T3 B8 VMA_DQ14 VMA_CMD29 T3 B8 VMA_DQ34 VMA_CMD29 T3 B8 VMA_DQ49
T7 A3 VMA_DQ3 VMA_CMD29 T7 A3 VMA_DQ9 VMA_CMD18 T7 A3 VMA_DQ35 VMA_CMD18 T7 A3 VMA_DQ55
M7 VMA_CMD30 M7 VMA_CMD13 M7 VMA_CMD13 M7
17 VMA_CMD30 A15 A15 A15 A15
M2 B2 VMA_CMD12 M2 B2 VMA_CMD12 M2 B2 VMA_CMD12 M2 B2

17 VMA_CMD12 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
N8 D9 VMA_CMD9 N8 D9 VMA_CMD14 N8 D9 VMA_CMD14 N8 D9
17 VMA_CMD9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
M3 G7 VMA_CMD13 M3 G7 VMA_CMD30 M3 G7 VMA_CMD30 M3 G7
17 VMA_CMD13 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
VDD#K2 K2 VDD#K2 K2 VDD#K2 K2 VDD#K2 K2
VDD#N1 N1 VDD#N1 N1 VDD#N1 N1 VDD#N1 N1
J7 N9 VMA_CLKP0 J7 N9 17 VMA_CLKP1 J7 N9 VMA_CLKP1 J7 N9
17 VMA_CLKP0 CK VDD#N9 CK VDD#N9 CK VDD#N9 CK VDD#N9
K7 R1 VMA_CLKN0 K7 R1 17 VMA_CLKN1 K7 R1 VMA_CLKN1 K7 R1
17 VMA_CLKN0 CK VDD#R1 +1.5V_GFX CK VDD#R1 CK VDD#R1 CK VDD#R1 +1.5V_GFX
K9 R9 VMA_CMD0 K9 R9 17 VMA_CMD27 VMA_CMD27 K9 R9 VMA_CMD27 K9 R9
17 VMA_CMD0 CKE VDD#R9 CKE VDD#R9 +1.5V_GFX CKE VDD#R9 +1.5V_GFX CKE VDD#R9
K1 A1 VMA_CMD25 K1 A1 17 VMA_CMD16 VMA_CMD16 K1 A1 VMA_CMD16 K1 A1

17 VMA_CMD25 ODT VDDQ#A1 ODT VDDQ#A1 ODT VDDQ#A1 ODT VDDQ#A1
B L2 A8 VMA_CMD2 L2 A8 17 VMA_CMD11 VMA_CMD11 L2 A8 VMA_CMD11 L2 A8 B
17 VMA_CMD2 CS VDDQ#A8 CS VDDQ#A8 CS VDDQ#A8 CS VDDQ#A8
J3 C1 VMA_CMD24 J3 C1 VMA_CMD24 J3 C1 VMA_CMD24 J3 C1
17 VMA_CMD24 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1
K3 C9 VMA_CMD8 K3 C9 VMA_CMD8 K3 C9 VMA_CMD8 K3 C9
17 VMA_CMD8 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9
L3 D2 VMA_CMD19 L3 D2 VMA_CMD21 L3 D2 VMA_CMD21 L3 D2
17 VMA_CMD19 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2
VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1
VMA_WDQS2 F3 H2 VMA_WDQS3 F3 H2 VMA_WDQS5 F3 H2 VMA_WDQS7 F3 H2
VMA_RDQS2 DQSL VDDQ#H2 VMA_RDQS3 DQSL VDDQ#H2 VMA_RDQS5 DQSL VDDQ#H2 VMA_RDQS7 DQSL VDDQ#H2
G3 DQSL VDDQ#H9 H9 G3 DQSL VDDQ#H9 H9 G3 DQSL VDDQ#H9 H9 G3 DQSL VDDQ#H9 H9
VMA_DM2 E7 A9 VMA_DM3 E7 A9 VMA_DM5 E7 A9 VMA_DM7 E7 A9

VMA_DM0 DML VSS#A9 VMA_DM1 DML VSS#A9 VMA_DM4 DML VSS#A9 VMA_DM6 DML VSS#A9
D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3
VSS#E1 E1 VSS#E1 E1 VSS#E1 E1 VSS#E1 E1
VSS#G8 G8 VSS#G8 G8 VSS#G8 G8 VSS#G8 G8
VMA_WDQS0 C7 J2 VMA_WDQS1 C7 J2 VMA_WDQS4 C7 J2 VMA_WDQS6 C7 J2
VMA_RDQS0 DQSU VSS#J2 VMA_RDQS1 DQSU VSS#J2 VMA_RDQS4 DQSU VSS#J2 VMA_RDQS6 DQSU VSS#J2
B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8
VSS#M1 M1 VSS#M1 M1 VSS#M1 M1 VSS#M1 M1
VSS#P1 P1 VSS#P1 P1 VSS#P1 P1 VSS#P1 P1
17 VMA_CMD28 T2 P9 VMA_CMD28 T2 P9 VMA_CMD28 T2 P9 VMA_CMD28 T2 P9
RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
VSS#T1 T1 VSS#T1 T1 VSS#T1 T1 VSS#T1 T1
VMA_ZQ1 L8 T9 VMA_ZQ2 L8 T9 VMA_ZQ3 L8 T9 VMA_ZQ4 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 Should be 240 Should be 240
Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1
VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B9 B9
R4 D1 R423 D1 R1 D1 R433 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
ES@243/F_4 VSSQ#D8 D8 ES@243/F_4 VSSQ#D8 D8 ES@243/F_4 VSSQ#D8 D8 ES@243/F_4 VSSQ#D8 D8
VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2
C J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 C
L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9
J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9
96-BALL 96-BALL 96-BALL 96-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
VSP@VRAM_DDR3 VSP@VRAM_DDR3 VSP@VRAM_DDR3 VSP@VRAM_DDR3
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX
10/21 Add for NV Request

VMA_CLKP0 R422 R417 R420 R416
10/21 Add for NV Request ES@1.33K/F_4 ES@1.33K/F_4 +1.5V_GFX VMA_CLKP1 ES@1.33K/F_4 ES@1.33K/F_4
R3
ES@243/F_4 R2
+1.5V_GFX VREFC_VMA1 VREFD_VMA1 C14 ES@1U/6.3V_4 ES@243/F_4 VREFC_VMA3 VREFD_VMA3
VMA_CLKN0 C6 ES@1U/6.3V_4
C537 ES@1U/6.3V_4 VMA_CLKN1
C564 ES@1U/6.3V_4 R419 C546 R424 C533 C538 ES@1U/6.3V_4 R421 C542 R418 C545
C539 ES@1U/6.3V_4 C557 ES@1U/6.3V_4
C563 ES@1U/6.3V_4 ES@1.33K/F_4 ES@.1u/10V_4 ES@1.33K/F_4 ES@.1u/10V_4 C559 ES@1U/6.3V_4 ES@1.33K/F_4 ES@.1u/10V_4 ES@1.33K/F_4 ES@.1u/10V_4
C16 ES@1U/6.3V_4 C7 ES@1U/6.3V_4
C15 ES@1U/6.3V_4 C560 ES@1U/6.3V_4
C13 ES@1U/6.3V_4
C1 ES@1U/6.3V_4
C2 ES@1U/6.3V_4
D D
+1.5V_GFX +1.5V_GFX
+1.5V_GFX
+1.5V_GFX C4 ES@.1u/10V_4
C19 ES@.1u/10V_4 C9 ES@.1u/10V_4
C551 *ES@10u/6.3V_6 C3 ES@.1u/10V_4 +1.5V_GFX
C18 ES@1U/6.3V_4 C5 ES@.1u/10V_4 C21 ES@.1u/10V_4 Quanta Computer Inc.
C10 ES@1U/6.3V_4 C17 ES@.1u/10V_4 C534 ES@.1u/10V_4 C544 ES@.1u/10V_4
C541 ES@1U/6.3V_4 C20 ES@.1u/10V_4 C12 ES@.1u/10V_4 C11 ES@.1u/10V_4 C552 ES@.1u/10V_4
C536 ES@1U/6.3V_4 C556 ES@.1u/10V_4 C535 ES@.1u/10V_4 C561 ES@.1u/10V_4 C543 ES@.1u/10V_4 PROJECT : ZR7
C562 ES@.1u/10V_4 C540 ES@.1u/10V_4 C558 ES@.1u/10V_4 Size Document Number Rev
3B
N11P-GE VRAM-1(DDR3 BGA96)
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
11EP@ --> N11P/N11E-GE1 Setting 17 VMC_DQ[63..0]
CHANNEL B: 256MB/512MB DDR3

17 VMC_DM[7..0]
VSP@ --> Operation P/N (VGA-VRAM CH:B N11P/N11E only) 17 VMC_WDQS[7..0]
17 VMC_RDQS[7..0]
U6
U34 U3 U32
VREFC_VMC1 M8 E3 VMC_DQ24
VREFC_VMC1 VMC_DQ22 VREFD_VMC1 VREFCA DQL0 VMC_DQ30 VREFC_VMC3 VMC_DQ36 VREFC_VMC3 VMC_DQ49
M8 VREFCA DQL0 E3 H1 VREFDQ DQL1 F7 M8 VREFCA DQL0 E3 M8 VREFCA DQL0 E3
VREFD_VMC1 H1 F7 VMC_DQ21 F2 VMC_DQ26 VREFD_VMC3 H1 F7 VMC_DQ34 VREFD_VMC3 H1 F7 VMC_DQ48
VREFDQ DQL1 VMC_DQ23 VMC_CMD7 DQL2 VMC_DQ28 VREFDQ DQL1 VMC_DQ39 VREFDQ DQL1 VMC_DQ55
DQL2 F2 N3 A0 DQL3 F8 DQL2 F2 DQL2 F2
N3 F8 VMC_DQ16 VMC_CMD20 P7 H3 VMC_DQ25 VMC_CMD22 N3 F8 VMC_DQ32 VMC_CMD22 N3 F8 VMC_DQ53
17 VMC_CMD7 A0 DQL3 A1 DQL4 A0 DQL3 A0 DQL3
P7 H3 VMC_DQ20 VMC_CMD4 P3 H8 VMC_DQ31 VMC_CMD4 P7 H3 VMC_DQ37 VMC_CMD4 P7 H3 VMC_DQ52
A P3 H8 VMC_DQ17 VMC_CMD14 N2 G2 VMC_DQ27 VMC_CMD20 P3 H8 VMC_DQ35 VMC_CMD20 P3 H8 VMC_DQ50 A
N2 G2 VMC_DQ18 VMC_CMD17 P8 H7 VMC_DQ29 VMC_CMD9 N2 G2 VMC_DQ38 VMC_CMD9 N2 G2 VMC_DQ54
P8 H7 VMC_DQ19 VMC_CMD6 P2 VMC_CMD6 P8 H7 VMC_DQ33 VMC_CMD6 P8 H7 VMC_DQ51
17 VMC_CMD17 A4 DQL7 A5 A4 DQL7 A4 DQL7
P2 VMC_CMD26 R8 VMC_CMD17 P2 VMC_CMD17 P2
17 VMC_CMD6 A5 A6 A5 A5
R8 VMC_CMD3 R2 D7 VMC_DQ8 VMC_CMD3 R8 VMC_CMD3 R8
17 VMC_CMD26 A6 A7 DQU0 A6 A6
R2 D7 VMC_DQ3 VMC_CMD1 T8 C3 VMC_DQ14 VMC_CMD26 R2 D7 VMC_DQ42 VMC_CMD26 R2 D7 VMC_DQ61
17 VMC_CMD3 A7 DQU0 A8 DQU1 A7 DQU0 A7 DQU0
T8 C3 VMC_DQ6 VMC_CMD10 R3 C8 VMC_DQ9 VMC_CMD1 T8 C3 VMC_DQ47 VMC_CMD1 T8 C3 VMC_DQ58
R3 C8 VMC_DQ0 VMC_CMD21 L7 C2 VMC_DQ12 VMC_CMD5 R3 C8 VMC_DQ41 VMC_CMD5 R3 C8 VMC_DQ62
17 VMC_CMD10 A9 DQU2 A10/AP DQU3 A9 DQU2 A9 DQU2
L7 C2 VMC_DQ7 VMC_CMD5 R7 A7 VMC_DQ11 VMC_CMD19 L7 C2 VMC_DQ45 VMC_CMD19 L7 C2 VMC_DQ59
17 VMC_CMD21 A10/AP DQU3 A11 DQU4 A10/AP DQU3 A10/AP DQU3
R7 A7 VMC_DQ1 VMC_CMD22 N7 A2 VMC_DQ13 VMC_CMD10 R7 A7 VMC_DQ44 VMC_CMD10 R7 A7 VMC_DQ60
17 VMC_CMD5 A11 DQU4 A12/BC DQU5 A11 DQU4 A11 DQU4
N7 A2 VMC_DQ5 VMC_CMD18 T3 B8 VMC_DQ10 VMC_CMD7 N7 A2 VMC_DQ43 VMC_CMD7 N7 A2 VMC_DQ56
17 VMC_CMD22 A12/BC DQU5 A13 DQU6 A12/BC DQU5 A12/BC DQU5
T3 B8 VMC_DQ2 VMC_CMD29 T7 A3 VMC_DQ15 VMC_CMD29 T3 B8 VMC_DQ40 VMC_CMD29 T3 B8 VMC_DQ63
T7 A3 VMC_DQ4 VMC_CMD30 M7 VMC_CMD18 T7 A3 VMC_DQ46 VMC_CMD18 T7 A3 VMC_DQ57
17 VMC_CMD29 A14 DQU7 A15 A14 DQU7 A14 DQU7
M7 VMC_CMD13 M7 VMC_CMD13 M7
17 VMC_CMD30 A15 A15 A15
VMC_CMD12 M2 B2
VMC_CMD9 BA0 VDD#B2 VMC_CMD12 VMC_CMD12
17 VMC_CMD12 M2 BA0 VDD#B2 B2 N8 BA1 VDD#D9 D9 M2 BA0 VDD#B2 B2 M2 BA0 VDD#B2 B2
N8 D9 VMC_CMD13 M3 G7 VMC_CMD14 N8 D9 VMC_CMD14 N8 D9
17 VMC_CMD9 BA1 VDD#D9 BA2 VDD#G7 BA1 VDD#D9 BA1 VDD#D9
M3 G7 K2 VMC_CMD30 M3 G7 VMC_CMD30 M3 G7
17 VMC_CMD13 BA2 VDD#G7 VDD#K2 BA2 VDD#G7 BA2 VDD#G7
VDD#K8 K8 VDD#N1 N1 VDD#K8 K8 VDD#K8 K8
N1 VMC_CLKP0 J7 N9 N1 N1
VDD#N1 VMC_CLKN0 CK VDD#N9 VDD#N1 VMC_CLKP1 VDD#N1
17 VMC_CLKP0 J7 CK VDD#N9 N9 K7 CK VDD#R1 R1 17 VMC_CLKP1 J7 CK VDD#N9 N9 J7 CK VDD#N9 N9
K7 R1 VMC_CMD0 K9 R9 17 VMC_CLKN1 K7 R1 VMC_CLKN1 K7 R1
17 VMC_CLKN0 CK VDD#R1 +1.5V_GFX CKE VDD#R9 +1.5V_GFX CK VDD#R1 +1.5V_GFX CK VDD#R1 +1.5V_GFX
K9 R9 17 VMC_CMD27 VMC_CMD27 K9 R9 VMC_CMD27 K9 R9
17 VMC_CMD0 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9
VMC_CMD25 K1 A1
VMC_CMD2 ODT VDDQ#A1 VMC_CMD16 VMC_CMD16
17 VMC_CMD25 K1 ODT VDDQ#A1 A1 L2 CS VDDQ#A8 A8 17 VMC_CMD16 K1 ODT VDDQ#A1 A1 K1 ODT VDDQ#A1 A1
L2 A8 VMC_CMD24 J3 C1 17 VMC_CMD11 VMC_CMD11 L2 A8 VMC_CMD11 L2 A8
17 VMC_CMD2 CS VDDQ#A8 RAS VDDQ#C1 CS VDDQ#A8 CS VDDQ#A8
B J3 C1 VMC_CMD8 K3 C9 VMC_CMD24 J3 C1 VMC_CMD24 J3 C1 B
17 VMC_CMD24 RAS VDDQ#C1 CAS VDDQ#C9 RAS VDDQ#C1 RAS VDDQ#C1
K3 C9 VMC_CMD19 L3 D2 VMC_CMD8 K3 C9 VMC_CMD8 K3 C9
17 VMC_CMD8 CAS VDDQ#C9 WE VDDQ#D2 CAS VDDQ#C9 CAS VDDQ#C9
L3 D2 E9 VMC_CMD21 L3 D2 VMC_CMD21 L3 D2
17 VMC_CMD19 WE VDDQ#D2 VDDQ#E9 WE VDDQ#D2 WE VDDQ#D2
VDDQ#E9 E9 VDDQ#F1 F1 VDDQ#E9 E9 VDDQ#E9 E9
F1 VMC_WDQS3 F3 H2 F1 F1
VMC_WDQS2 VDDQ#F1 VMC_RDQS3 DQSL VDDQ#H2 VMC_WDQS4 VDDQ#F1 VMC_WDQS6 VDDQ#F1
F3 DQSL VDDQ#H2 H2 G3 DQSL VDDQ#H9 H9 F3 DQSL VDDQ#H2 H2 F3 DQSL VDDQ#H2 H2
VMC_RDQS2 G3 H9 VMC_RDQS4 G3 H9 VMC_RDQS6 G3 H9
DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9
VMC_DM3 E7 A9
VMC_DM2 VMC_DM1 DML VSS#A9 VMC_DM4 VMC_DM6
E7 DML VSS#A9 A9 D3 DMU VSS#B3 B3 E7 DML VSS#A9 A9 E7 DML VSS#A9 A9
VMC_DM0 D3 B3 E1 VMC_DM5 D3 B3 VMC_DM7 D3 B3
DMU VSS#B3 VSS#E1 DMU VSS#B3 DMU VSS#B3
VSS#E1 E1 VSS#G8 G8 VSS#E1 E1 VSS#E1 E1
G8 VMC_WDQS1 C7 J2 G8 G8
VMC_WDQS0 VSS#G8 VMC_RDQS1 DQSU VSS#J2 VMC_WDQS5 VSS#G8 VMC_WDQS7 VSS#G8
C7 DQSU VSS#J2 J2 B7 DQSU VSS#J8 J8 C7 DQSU VSS#J2 J2 C7 DQSU VSS#J2 J2
VMC_RDQS0 B7 J8 M1 VMC_RDQS5 B7 J8 VMC_RDQS7 B7 J8
DQSU VSS#J8 VSS#M1 DQSU VSS#J8 DQSU VSS#J8
VSS#M9 M9 VSS#P1 P1 VSS#M9 M9 VSS#M9 M9
P1 VMC_CMD28 T2 P9 P1 P1
VSS#P1 RESET VSS#P9 VMC_CMD28 VSS#P1 VMC_CMD28 VSS#P1
17 VMC_CMD28 T2 RESET VSS#P9 P9 VSS#T1 T1 T2 RESET VSS#P9 P9 T2 RESET VSS#P9 P9
T1 VMC_ZQ2 L8 T9 T1 T1
VMC_ZQ1 VSS#T1 ZQ VSS#T9 VMC_ZQ3 VSS#T1 VMC_ZQ4 VSS#T1
L8 ZQ VSS#T9 T9 L8 ZQ VSS#T9 T9 L8 ZQ VSS#T9 T9
Should be 240 Should be 240 VSSQ#B1 B1 Should be 240 Should be 240

Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B9 B9 Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1
VSSQ#B9 B9 VSSQ#D1 D1 VSSQ#B9 B9 VSSQ#B9 B9
R452 D1 R50 D8 R23 D1 R438 D1
VSSQ#D1 VSSQ#D8 VSSQ#D1 VSSQ#D1
11EP@243/F_4 VSSQ#D8 D8 11EP@243/F_4 VSSQ#E2 E2 11EP@243/F_4 VSSQ#D8 D8 11EP@243/F_4 VSSQ#D8 D8
VSSQ#E2 E2 J1 NC#J1 VSSQ#E8 E8 VSSQ#E2 E2 VSSQ#E2 E2
J1 NC#J1 VSSQ#E8 E8 L1 NC#L1 VSSQ#F9 F9 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8
C L1 NC#L1 VSSQ#F9 F9 J9 NC#J9 VSSQ#G1 G1 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 C
J9 NC#J9 VSSQ#G1 G1 L9 NC#L9 VSSQ#G9 G9 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9
96-BALL
96-BALL SDRAM DDR3 96-BALL 96-BALL
SDRAM DDR3 VSP@VRAM_DDR3 SDRAM DDR3 SDRAM DDR3
VSP@VRAM_DDR3 VSP@VRAM_DDR3 VSP@VRAM_DDR3
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX
VMC_CLKP0 R446 R55 VMC_CLKP1 R14 R437

10/21 Add for NV Request
R451 11EP@1.33K/F_4 11EP@1.33K/F_4 R21 11EP@1.33K/F_4 11EP@1.33K/F_4
11EP@243/F_4 11EP@243/F_4
+1.5V_GFX VREFC_VMC1 VREFD_VMC1 VREFC_VMC3 VREFD_VMC3
VMC_CLKN0 VMC_CLKN1
C49 11EP@1U/6.3V_4 R445 C590 R54 C152 R15 C38 R436 C571
C65 11EP@1U/6.3V_4 10/21 Add for NV Request
C55 11EP@1U/6.3V_4 11EP@1.33K/F_4 11EP@.1u/10V_4 11EP@1.33K/F_4 11EP@.1u/10V_4 11EP@1.33K/F_4 11EP@.1u/10V_4 11EP@1.33K/F_4 11EP@.1u/10V_4
C579 11EP@1U/6.3V_4
C580 11EP@1U/6.3V_4 +1.5V_GFX
C581 11EP@1U/6.3V_4
C567 11EP@1U/6.3V_4
C569 11EP@1U/6.3V_4 C135 11EP@1U/6.3V_4
C131 11EP@1U/6.3V_4
D C142 11EP@1U/6.3V_4 D
C162 11EP@1U/6.3V_4
+1.5V_GFX +1.5V_GFX C587 11EP@1U/6.3V_4
C588 11EP@1U/6.3V_4
+1.5V_GFX C597 11EP@1U/6.3V_4
C595 11EP@.1u/10V_4 C585 11EP@.1u/10V_4 C582 11EP@1U/6.3V_4
+1.5V_GFX C572 11EP@.1u/10V_4 C70 11EP@.1u/10V_4
C592 *11EP@10u/6.3V_6 C591 11EP@.1u/10V_4 Quanta Computer Inc.
C29 11EP@.1u/10V_4 C46 11EP@.1u/10V_4 C570 11EP@.1u/10V_4
C128 11EP@1U/6.3V_4 C114 11EP@.1u/10V_4 C577 11EP@.1u/10V_4 C41 11EP@.1u/10V_4
C25 11EP@1U/6.3V_4 C159 11EP@.1u/10V_4 C575 11EP@.1u/10V_4 C568 11EP@.1u/10V_4 PROJECT : ZR7
C584 11EP@1U/6.3V_4 C121 11EP@.1u/10V_4 C167 11EP@.1u/10V_4 C594 11EP@.1u/10V_4 Size Document Number Rev
C578 11EP@1U/6.3V_4 C593 11EP@.1u/10V_4 C33 11EP@.1u/10V_4 C171 11EP@.1u/10V_4 3B
N11P-GE VRAM-2(DDR3 BGA96)
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
CRT Switch S Yn
dGPU_SELECT# Output
+5V
CRT
dGPU_EDIDSEL#
SW@ --> iGPU & dGPU Switch 3.3V or 5V level? 12/29 Modify C193 .1u/10V_4 updatefootprint 12/11
0 EV C183
L EV_LVDS/CRT U9
IV@ --> iGPU only SW@0.22u/6.3V_4 F1
1 IV H INT_LVDS/CRT 16
VCC GND
8
CRTVDD5
EV@ --> dGPU only 1 2
16
+5V
D4 SSM22LLPT CN13
+5V EV_CRTDCLK 2 SMD1206P110TFT CRT
18 EV_CRTDCLK IA0
EV_CRTDDAT 5 4 CRTDCLK 6
18 EV_CRTDDAT IB0 YA
EV_LVDS_DDCDAT 11 VGA_RED L14 BLM18BA750SN1D/0.3A/75ohm_6 CRT_R1 1 11 CRT_11 T101
19 EV_LVDS_DDCDAT IC0
EV_LVDS_DDCCLK 14 7 CRTDDATA 7
19 EV_LVDS_DDCCLK ID0 YB
C216 VGA_GRN L13 BLM18BA750SN1D/0.3A/75ohm_6 CRT_G1 2 12 DDCDAT_1
U12 INT_CRT_DDCCLK LCD_EDIDDATA
8 INT_CRT_DDCCLK 3 9 8
SW@0.22u/6.3V_4 INT_CRT_DDCDAT IA1 YC VGA_BLU L12 BLM18BA750SN1D/0.3A/75ohm_6 CRT_B1 CRTHSYNC
16 8 8 INT_CRT_DDCDAT 6 3 13
VCC GND INT_LVDS_EDIDDATA IB1
8 INT_LVDS_EDIDDATA 10 12 LCD_EDIDCLK 9
INT_LVDS_EDIDCLK IC1 YD CRTVSYNC
8 INT_LVDS_EDIDCLK 13 4 14
ID1 R139 R128 R109 C219 C214 C199 C200 C203 C217
A 18 EV_CRT_BLU 2 10 A
IA0 VGA_BLU DDCCLK_1
18 EV_CRT_GRN 5 4 5 15
IB0 YA 150/F_4 150/F_4 150/F_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4
18 EV_CRT_RED 11 10,24 dGPU_EDIDSEL# 1 15
IC0 VGA_GRN S OE
14 7
ID0 YB SW@SN74CBT3257CPWR
17
3 9 VGA_RED
8 INT_CRT_BLU IA1 YC
6
8
8
INT_CRT_GRN
INT_CRT_RED 10
13
IB1
IC1
ID1
YD
12 iGPU INT_CRT_RED
INT_CRT_GRN
R133
R110
IV@0_4
IV@0_4
VGA_RED
VGA_GRN
INT_CRT_BLU R111 IV@0_4 VGA_BLU
dGPU_SELECT# 1 15
only INT_VSYNC
INT_HSYNC
R126
R117
IV@0_4
IV@0_4
VSYNC
HSYNC
S OE INT_CRT_DDCDAT R86 IV@0_4 CRTDDATA
SW@SN74CBT3257CPWR INT_CRT_DDCCLK R102 IV@0_4 CRTDCLK
INT_LVDS_EDIDDATA R104 IV@0_4 LCD_EDIDDATA
+3V
INT_LVDS_EDIDCLK R98 IV@0_4 LCD_EDIDCLK
+5V C617 U36
INT_LVDS_DIGON 1 2 LVDS_VDDEN CRTVDD5 1 16 CRT_VSYNC2 R501 0_4 CRTVSYNC C631 *.1u/10V_4 CRTVDD5
U13 INT_LVDS_BLON LVDS_BLON .1u/10V_4 VCC_SYNC SYNC_OUT2 CRT_HSYNC2 R502 0_4 CRTHSYNC
3 4 14
C215 SW@0.22u/6.3V_4 RN10 IV@0_4P2R SYNC_OUT1 C629 *10p/50V_4 CRTVSYNC
16 8 7
VCC GND CRT_BYP VCC_DDC
10/20 Modify C615 .22u/25V_6
8
BYP
15 VSYNC CRTVDD5 C630 *10p/50V_4 CRTHSYNC
SYNC_IN2 HSYNC +3V
19 EV_LVDS_BLON 2 +3V 2 13
IA0 LVDS_BLON_R EV_CRT_RED R134 EV@0_4 VGA_RED VCC_VIDEO SYNC_IN1 C614 10p/50V_4 DDCCLK_1
19 EV_LVDS_VDDEN 5 4
IB0 YA EV_CRT_GRN R107 EV@0_4 VGA_GRN C626 R492 R503
18 EV_HSYNC 11
IC0 LVDS_VDDEN_R EV_CRT_BLU R108 EV@0_4 VGA_BLU CRT_R1 CRTDCLK R493 2.7K_4 C632 10p/50V_4 DDCDAT_1
18 EV_VSYNC 14 7 3 10
ID0 YB EV_VSYNC R127 EV@0_4 VSYNC .1u/10V_4 CRT_G1 VIDEO_1 DDC_IN1 CRTDDATA R494 2.7K_4 2.7K_4 2.7K_4
4 11
HSYNC EV_HSYNC R118 EV@0_4 HSYNC CRT_B1 VIDEO_2 DDC_IN2
8 INT_LVDS_BLON 3 9 5
IA1 YC EV_CRTDDAT R78 EV@0_4 CRTDDATA VIDEO_3 DDCCLK_1
6 9
8 INT_LVDS_DIGON
8 INT_HSYNC 10
IB1
12 VSYNC 10/18 EV_CRTDCLK R101 EV@0_4 CRTDCLK 6
DDC_OUT1
12 DDCDAT_1
IC1 YD EV_LVDS_DDCDAT R87 EV@0_4 LCD_EDIDDATA GND DDC_OUT2
8 INT_VSYNC 13
ID1 EV_LVDS_DDCCLK R88 EV@0_4 LCD_EDIDCLK CM2009-02QR
dGPU_SELECT# 1
S OE
15
dGPU EV_LVDS_VDDEN 1 2 LVDS_VDDEN
EV_LVDS_BLON 3 4 LVDS_BLON
SW@SN74CBT3257CPWR only RN5 EV@0_4P2R
LCD_ON (LCD Power)

LVDS Switch U7
S Yn dGPU_SELECT# Output
LVDS Stuff R713 on 2 CH.
B
+3V 5V_LCD 10/20 Modify B
TXLCLKOUT+ +3V INVCC0

18 EV_TXLCLKOUT+ 46
A2P C2P
6 Stuff R712 on 1 CH.
TXLCLKOUT-
18 EV_TXLCLKOUT- 45
A2N C2N
7 0 EV L EV_LVDS
R712 R713 LVDS_VDDEN_R R121 SW@0_4 LVDS_VDDEN
44 9 TXLOUT2+
18 EV_TXLOUT2+ A1P C1P TXLOUT2- C181 C190 C90 C102
18 EV_TXLOUT2- 43
A1N IN_A OUT_C C1N
10
+1.8V 1 IV H INT_LVDS
V1@0_6 V2@0_1206 U10
41 15 TXLOUT1+ .1u/10V_4 1000p/50V_4 4.7u/25V_8 1000p/50V_4
18 EV_TXLOUT1+ A0P C0P TXLOUT1- LCDVCC
18 EV_TXLOUT1- 40
A0N C0N
16
1/7 Modify. 6 1
3
IN OUT
39 18 TXLOUT0+ 4 2
18 EV_TXLOUT0+ ACLKP CCLKP IN GND
38 19 TXLOUT0- C198 C195 C196 C197 C194
18 EV_TXLOUT0- ACLKN CCLKN
2 C191 LVDS_VDDEN 3 5
ON/OFF GND *.1u/10V_4 *2.2u/10V_8 .1u/10V_4 .01u/25V_4 22u/6.3V_8
SW@2N7002D 10/16 11/27 Add CN5
pin45 to GND 1U/6.3V_4
Q12 AAT4280-4
35 R106
8 INT_TXLCLKOUT+
1
B2P dGPU_SELECT_R VIN CN5

8 INT_TXLCLKOUT- 34
B2N SEL
13 dGPU_SELECT# 10 2A +3V
G_5
G_6
33 SW@0_4 R30 *SHORT_8 INVCC0 *SW@.1u_4
8 INT_TXLOUT2+ B1P 40
32 R97 R31 *SHORT_8 C187 5V_LCD +5V
8 INT_TXLOUT2- B1N 39 J3
1 SW@100K_4
VSS 38
5
30 3 +3V 1 1 2
8 INT_TXLOUT1+ B0P VSS 37 EV_LVDS_VDDEN 19
29 5 *SW@.1u_4 4
8 INT_TXLOUT1- B0N VSS 36 PANEL_COLOR 36
IN_B 8 C192 1/11 Add L48 by EMI R99 *SW@100K_4 2
VSS 36 PANEL_ENG 35 INT_LVDS_DIGON 8
28 11 *SHORT_PAD
8 INT_TXLOUT0+
3
BCLKP VSS BL_ON 34 U8
8 INT_TXLOUT0- 27 14
BCLKN VSS 33
5
dGPU_SELECT# LVDS_BRIGHT L48 LVDS_BRIGHT_R *SW@OR_GATE

VSS
17 1
SBY100505T-121Y-N 32 10/22 Modify Footprint
C182 SW@1000p/50V_4
48
36
VDD VSS
20
22 R105 *SW@100K_4
4
2 EV_LVDS_BRIGHT#
18 EV_TXUCLKOUT+
31 G_4 1/15 Add
C161 SW@1000p/50V_4 VDD VSS 30
25 24 18 EV_TXUCLKOUT-
3
C175 SW@0.22u/6.3V_4 VDD VSS U11 29

23 26
C172 SW@.1u/10V_4 VDD VSS *SW@OR_GATE 28
C189 SW@.1u/10V_4
21
VDD VSS
31 18 EV_TXUOUT2+ 27 Backlight Control 10/20 Modify
12
4
VDD VSS
37
42
10/22 Modify Footprint 18 EV_TXUOUT2- 26
C188 SW@2.2u/6.3V_6 VDD VSS 25
2 47 18 EV_TXUOUT1+
VDD VSS 24 LVDS_BLON_R R122 SW@0_4 LVDS_BLON
18 EV_TXUOUT1- 23
SW@TS3DV421DGVR 22
+1.8V 18 EV_TXUOUT0+ 21
+3V R92 *SW@10K_4 EV_LVDS_BRIGHT#
18 EV_TXUOUT0- 20
C
LID591#,EC intrnal PU C
3
TXLCLKOUT+ 19
TXLCLKOUT- 18
17
TXLOUT2+ 16
19 EV_LVDS_BRIGHT 2
TXLOUT2- 15
14
13 +3V LID591# 33,36
Q8 TXLOUT1+
*SW@2N7002D TXLOUT1- 12
1
11
1
10/16 TXLOUT0+ 10 G_1 D3
Brightness TXLOUT0- 9
8
BAS316
+3V R79 2.2K_4 LCD_EDIDCLK 7 R46
2
R80 2.2K_4 LCD_EDIDDATA 6
+3V 5 R37 10K_4
4 BL_ON
LCDVCC 3 10K_4
2 10/16
3
1
G_0
C143
iGPU only
3
1/14 Change pin3,4 define.
SW@0.22u/6.3V_4 BL# 2
R39 *SW@100K_4 2
U5 EC_FPBACK# 36
3
INT_TXLCLKOUT- RN1 1 2 IV@0_4P2R TXLCLKOUT- GS12401-1011-40P-R-NH Q3
INT_TXLCLKOUT+ 3 4 TXLCLKOUT+ 2N7002D Q2
5 6 INT_TXLOUT0- RN4 1 2 IV@0_4P2R TXLOUT0- 11/19 Change LVDS to two channel. DTC144EU
PWM_SELECT# 9,10
1
VCC S INT_TXLOUT0+ TXLOUT0+ LVDS_BLON
3 4 2
INT_TXLOUT1- RN3 1 2 IV@0_4P2R TXLOUT1-
R47 *ES@0_4 3 4 LVDS_BRIGHT INT_TXLOUT1+ 3 4 TXLOUT1+ Q4
19 EV_LVDS_BRIGHT B0 YA INT_TXLOUT2- RN2 1 2 IV@0_4P2R TXLOUT2- 2N7002D
INT_TXLOUT2+ 3 4 TXLOUT2+ CCD & MIC 11/16 Change CN3 to 8pin conn.
1
8 INT_LVDS_BRIGHT 1 2
B1 GND
CN3 10/22 Modify Footprint
36 CONTRAST
R43 SW@0_4 SW@74LVC1G3157GW
dGPU only 10/18 Add , 10/20 Swap +3V 8
7
10
9 +3V
R51 IV@0_4 USBP8-_R 6
EV_TXLCLKOUT- RN6 3 4 EV@0_4P2R TXLCLKOUT- USBP8+_R 5 C89 *SW@.1u_4
EV_TXLCLKOUT+ TXLCLKOUT+
10/18 1 2 4
5
R53 EV@0_4 EV_TXLOUT0- RN9 3 4 EV@0_4P2R TXLOUT0- 3 1 EV_LVDS_BLON 19
EV_TXLOUT0+ 1 2 TXLOUT0+ DMIC_CLK_1 2 4
29 DMIC_CLK_1
D EV_TXLOUT1- RN8 3 4 EV@0_4P2R TXLOUT1- 29 DMIC0_1 DMIC0_1 1 2 D
INT_LVDS_BLON 8
EV_TXLOUT1+ 1 2 TXLOUT1+
3
EV_TXLOUT2- RN7 3 4 EV@0_4P2R TXLOUT2- 8P_CON U4

EV_TXLOUT2+ 1 2 TXLOUT2+ *SW@OR_GATE
R29 *0_4
L2
2 1 USBP8-_R
10 USBP8- 2 1
3 4 USBP8+_R
10 USBP8+ 3 4
DLW21HN900SQ2L/300mA/90ohm Quanta Computer Inc.
R28 *0_4 PROJECT : ZR7
11/26 Change footprint 3B
1/11 Stuff L2. CRT/LVDS/CAMERA/LID
1 2 3 4 5 6 7 8
5 4 3 2 1
iGPU HDMI LEVEL SHIFTER 36 HDMI_HPD_EC#

+3V_GFX
IV@ --> iGPU only +3V To dGPU HPD

EV@ --> dGPU only OE# control for +3V
To iGPU HPD R479
ES@ --> External VGA SKU power saving ES@10K_4
R505
SW@ --> iGPU & dGPU Switch HDMI_MB_HP SW@10K_4 HDMI_HP_EV 19
MB_HDMI_DDCDATA R504
3
CSP@ --> Operation P/N MB_HDMI_DDCCLK 10K_4
+3V R187 *IV@4.7K_4 HDMI_HPD_EC#
INT_HDMI_HPD R506 SW@0_4
D DDCBUF_EN HDMI_HPD_EC# 2 D
3
+3V CFG
3
+3V +3V Q46 Q42
Active Buffer SW@2N7002D ES@2N7002D
2
1
C287 C355 C664 C290 C656 HDMI_MB_HP 2
U17
36
35
34
33
32
31
30
29
28
27
26
25
IV@2.2u/6.3V_6 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4
10/20 Add Q44
HPD_SINK
SDA_SINK
SCL_SINK
GND
VCC
DDC_EN
GND
GND
VCC
CCT2
CCT1
OE#
1
2N7002D
10/16
1
close to pin2/11/15/21/26/33/40/46 from PCH 10/16 37 24
+5V
R151 *10K_4
+3V GND GND MB_HDMITX0P
8 INT_HDMITX0P 38 IN_D1- OUT_D1- 23
39 22 MB_HDMITX0N
8 INT_HDMITX0N IN_D1+ OUT_D1+
+3V 40 VCC VCC 21 +3V
41 20 MB_HDMITX2N
C663 C665 C657
8 INT_HDMITX2N
8 INT_HDMITX2P 42
IN_D2-
IN_D2+
OUT_D2-
OUT_D2+ 19 MB_HDMITX2P SDVO I2C Control
43 GND GND 18
IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 44 17 MB_HDMITX1P
8 INT_HDMITX1P IN_D3- OUT_D3- +5V
45 16 MB_HDMITX1N Bypass(default)
8 INT_HDMITX1N IN_D3+ OUT_D3+
+3V 46 VCC VCC 15 +3V
47 14 MB_HDMICLK+ MXM_DDCCK_C R150 EV@0_4 MXM_DDCCK
8 INT_HDMICLK+ IN_D4- OUT_D4-
48 13 MB_HDMICLK- MXM_DDCDAT_C R146 EV@0_4 MXM_DDCDAT
8 INT_HDMICLK- IN_D4+ OUT_D4+
49 C229 U14
HPDEN
HPD_S
SDA_S
SCL_S
GND
REXT
SW@SN74CBT3257CPWR
TRIM
GND
GND
GND
VCC
VCC
SW@0.22u/6.3V_4
NC
IV@PS8101 16 VCC GND 8
1
2
3
4
5
6
7
8
9
10
11
12
+3V 2
18 MXM_DDCCK_C IA0
5 4 MXM_DDCCK
18 MXM_DDCDAT_C IB0 YA
C R156 IV@4.7K_4 PC0 11 C
R157 *IV@4.7K_4 +3V IC0 MXM_DDCDAT
14 ID0 YB 7
LS_REXT
PC0 +5V D5 2 RB501V-40
1
R155 *IV@4.7K_4 PC1 PC1 +3V 3 9
from PCH 8 SDVO_CTRLCLK IA1 YC
R189 *IV@4.7K_4 DDCBUF_EN
8 SDVO_CTRLDAT 6
10
IB1
IC1 YD 12 S Yn CSP@ HDMI SDVO I2C
For IV: 2.2K ohm
R162 NV suggestion near
R188 *IV@4.7K_4 R166 IV@499/F_4 MB_HDMITX2P 13 CSP@2.2K_4
Control by pin4 HPDEN_R ID1
For ES:4.7K ohm HDMI connector
R190 *IV@4.7K_4 CFG R173 *IV@100/F_4
R191 *IV@4.7K_4 1 15
0 EV
10,23 dGPU_EDIDSEL# S OE
8 INT_HDMI_HPD INT_HDMI_HPD MB_HDMITX2N
MB_HDMI_DDCCLK R163 *SHORT_6 HDMI_DDCCLK_MB
MB_HDMITX1P
1 IV
R165 IV@0_4 HDMI_DDCDATA_SW R171 *IV@100/F_4 Q45 +5V D6 2 RB501V-40
1 C286
8 SDVO_CTRLDAT
ES@BSN20
R164 IV@0_4 HDMI_DDCCLK_SW MB_HDMITX1N 12/29 Modify *.1u/10V_4
8 SDVO_CTRLCLK
MXM_DDCCK 1 3 MB_HDMI_DDCCLK CSP@ HDMI SDVO I2C
For IV: 2.2K ohm
R158
Equalization Control MB_HDMITX0P CSP@2.2K_4
PC0 internal PD For ES:4.7K ohm
PC1 PC0 R177 *IV@100/F_4
PC1 internal PD
2
PIN4 PIN3 EQ Control DDCBUF_EN internal PD MB_HDMITX0N
+3V
MB_HDMI_DDCDATA R154 *SHORT_6 HDMI_DDCDATA_MB
2
L L 8dB CFG internal PD
L H 4dB MB_HDMICLK+
H L 12dB
DDC_EN internal PU MXM_DDCDAT 1 3 MB_HDMI_DDCDATA C275
H H 0dB R168 *IV@100/F_4
Q16 *.1u/10V_4
MB_HDMICLK- ES@BSN20
B B
GPU Switchable Graphic HDMI source ESD Protect HDMI connector

CN15 1/11 Add C928 by EMI.
12/29 Delete U15, U16, U18. 20
MB_HDMITX2P SHELL1
1 D2+
2 +3V
C339 ES@.1u/10V_4 MB_HDMITX0N MB_HDMITX2N D2 Shield
18 HDMITX0N 3 D2-
C344 ES@.1u/10V_4 MB_HDMITX0P MB_HDMITX1P 4
18 HDMITX0P D1+
5 D1 Shield
C333 ES@.1u/10V_4 MB_HDMITX2N MB_HDMITX1N 6
18 HDMITX2N D1-
C321 ES@.1u/10V_4 MB_HDMITX2P MB_HDMITX0P 7 C928
18 HDMITX2P D0+
8 D0 Shield 2200p/50V_4
C317 ES@.1u/10V_4 MB_HDMITX1P MB_HDMITX0N 9 23
18 HDMITX1P D0- GND
C311 ES@.1u/10V_4 MB_HDMITX1N MB_HDMICLK+ 10
18 HDMITX1N CK+
C306 ES@.1u/10V_4 MB_HDMICLK+ 12/29 Modify MB_HDMICLK-
11
12
CK Shield GND 22
18 HDMICLK+ CK-
C295 ES@.1u/10V_4 MB_HDMICLK- 13
18 HDMICLK- +5V CE Remote
14 NC
HDMI_DDCCLK_MB 15
R507 R508 R509 R511 R512 R513 R515 R514 F2 HDMI_DDCDATA_MB DDC CLK
16
To Discrete ES@562/F_4 17
DDC DATA
GND
1 2 D11 SSM22LLPT +5V_HDMI 18
HP_DET +5V
19 HP DET
ES@562/F_4 ES@562/F_4 ES@562/F_4 ES@562/F_4 SMD1206P110TFT 21
ES@562/F_4 ES@562/F_4 ES@562/F_4 SHELL2
A HDMI A
3
HDMI_MB_HP R159 *SHORT_4
Q47
+5V 2 R152
100K_4
R510 ES@2N7002D
ES@100K_4 Quanta Computer Inc.
1
PROJECT : ZR7
3B
HDMI (PS8101)
5 4 3 2 1
5 4 3 2 1
Giga-LAN AR8151 10/26 Add

+3V_LAN
BCM_CLKREQ# R292 *10K_4
+3V_S5 +3V_LAN
D R297 *SHORT_6 +3V_LAN D
C459 C458 C461 C462 C460
10u/6.3V_8 10u/6.3V_8 1u/6.3V_4 .1u/10V_4 *1000p/50V_4 U23
1 22 AVDDH C424 .1u/10V_4

VDD33 AVDDH
10/26 Add
4,10,11,16,27,31,36 PLTRST# 2 PERSTn CLKREQn/LED2 23
3 24 DVDDL C442 .1u/10V_4

8,27 PCIE_WAKE# WAKEn DVDDL
R288 *SHORT_4 BCM_CLKREQ# 4 25 SMCLK_8151 R298 *0_4
10 CLK_PCIE_LAN_REQ# CLKREQn SMCLK SMB_CLK_ME0 10
C687 .1u/10V_4 +VDDCT 5 VDDCT
AR8151
5X5mm SMDATA 26 SMDATA_8151 R293 *0_4
SMB_DATA_ME0 10
C684 1u/6.3V_4 AVDDL 6 40-Pin QFN 27
AVDDL_REG TESTMODE
C682 .1u/10V_4 XTLO 7 28 T44
10/26 Modify
XTLO TEST_RST
XTLI 8 29 PCIE_RXN1_LAN_R .1u/10V_4 C477
XTLI TX_N PCIE_RX1- 10
C676 1u/6.3V_4 AVDDH 9 30 PCIE_RXP1_LAN_R .1u/10V_4 C478
AVDDH_REG TX_P PCIE_RX1+ 10
C C
C677 .1u/10V_4 R267 2.37K/F_4 RBIAS 10 31 AVDDL C465 .1u/10V_4
RBIAS AVDDL
26 LAN_TRD0P 11 TRXP0 REFCLK_N 32 CLK_PCIE_LOM# 10
26 LAN_TRD0N 12 TRXN0 REFCLK_P 33 CLK_PCIE_LOM 10

C675 .1u/10V_4 AVDDL 13 34 AVDDL C466 .1u/10V_4
NC/AVDDL AVDDL
26 LAN_TRD1P 14 TRXP1 RX_P 35 PCIE_TX1+ 10
26 LAN_TRD1N 15 TRXN1 RX_N 36 PCIE_TX1- 10

C673 .1u/10V_4 AVDDH 16 37 DVDDL C467 1u/6.3V_4
NC/AVDDH DVDDL_REG
C443 33p/50V_4 XTLO 17 38 LAN_ACTLED C468 .1u/10V_4
26 LAN_TRD2P NC/TRXP2 LED0 LAN_ACTLED 26
1
18 39 LAN_LINKLED#
26 LAN_TRD2N NC/TRXN2 LED1 LAN_LINKLED# 26
1.2H Y2
25MHz C672 .1u/10V_4 AVDDL 19 40 LX L24 4.7uH/1A_2X2 +VDDCT
NC/AVDDL LX
2
C427 33p/50V_4 XTLI 20 41 C469 C472 C476

26 LAN_TRD3P NC/TRXP3 GND
21 10u/6.3V_8 .1u/10V_4 *1000p/50V_4
26 LAN_TRD3N NC/TRXN3
B B
AR8151
LAN_TRD0P
LAN_TRD1P
LAN_TRD2P
LAN_TRD3P
LAN_TRD0N
LAN_TRD1N
LAN_TRD2N
LAN_TRD3N
R275
R274
R273
R272
R271
R270
R269
R268
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
LAN_N1
LAN_N2
LAN_N3
LAN_N4
A A
C396 C395 C394 C393
.1u/10V_4 .1u/10V_4 .1u/10V_4 .1u/10V_4

PROJECT : ZR7
3B
GLAN BCM57780
5 4 3 2 1
1 2 3 4 5 6 7 8
TRANSFORMER PBY160808T-181Y-N/2A/180ohm_6
+VDDCT
L21
+VDDCT_TR
C384 C375 C378 C380

C387 1U/10V_4
A A
.1u/10V_4 .1u/10V_4 .1u/10V_4 .1u/10V_4
10/22 modify Footprint

Close to Transformer pin 1,4,7,10
U38
1 TCT1 MCT1 24
LAN_TRD0P 2 23 X-TX0P
25 LAN_TRD0P TD1+ MX1+
LAN_TRD0N 3 22 X-TX0N
25 LAN_TRD0N TD1- MX1-
4 TCT2 MCT2 21
7 TCT3 MCT3 18
B B
10 TCT4 MCT4 15
LFE9276A-R
R206 R218 R228 R241

75/F_8 75/F_8 75/F_8 75/F_8
Delta9276A-R DBBL5MLAN01
Delta9276C-R DB0ZR1LAN00
C368
1500p/3KV_18
C C
LAN_ACT_LED_PWR
RJ45 CN16 LAN_LINKLED#
9 YELLOW_N
R517 220_8 LAN_ACT_LED_PWR 10
25 LAN_ACTLED YELLOW_P
R516 5.1K_4 14 R258 *SHORT_6 C349 C690
X-TX0P GND2 R196 *SHORT_6
1 0+ GND1 13
X-TX0N 2 *.1u//50V_8 *.1u//50V_8
X-TX1P 0-
3 1+
X-TX2P 4
X-TX2N 2+
5 2-
X-TX1N 6
X-TX3P 1-
7 3+
D X-TX3N 8 D
3- Quanta Computer Inc.
25 LAN_LINKLED#
LAN_LINKLED# 11
+3V_LAN R576 220_8 LAN_LNK_LED_PWR 12
GREEN_N PROJECT : ZR7
GREEN_P Size Document Number Rev
RJ45 3B
LAN Transformer and RJ45
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
MINI-CARD WLAN(MPC) Check LED signal. (active high or low)

R680 *0_4 CL_DATA1_WLAN +WL_VDD
+3.3V: 1000mA 10 PCI_RST#
R696 *0_4 CL_CLK1_WLAN
12/30 modify Footprint +3V +WL_VDD
10 CLK_LPC_DEBUG
+3.3Vaux:330mA
+1.5V:500mA H=5.6mm Q49 R635 *SHORT_8 +WL_VDD
2
CN21 MINI_PCIE_H5.6 *2N7002D
51 Reserved +3.3V 52 +WL_VDD
R684 *0_4 CL_RST1#_WLAN 49 50 1 3 C748 C750 C744 C746
10 CL_RST1# Reserved GND
R679 *0_4 CL_DATA1_WLAN 47 48 +1.5V 10u/10V_8 .1u/10V_4 *.1u/10V_4 *.1u/10V_4
10 CL_DATA1 Reserved +1.5V
R686 *0_4 CL_CLK1_WLAN 45 46
10 CL_CLK1 Reserved LED_WPAN#
43 44 RFLED# R633 *SHORT_4
Reserved LED_WLAN# RF_LED# 32,36
+WL_VDD 41 42 R697 *SHORT_4
Reserved LED_WWAN#
39 Reserved GND 40 11/19 Add R697 for WI-FI.
A 37 Reserved USB_D+ 38 USBP13+ 10 A
35 GND USB_D- 36 USBP13- 10
10 PCIE_TX6+ 33 PETp0 GND 34
10 PCIE_TX6- 31 PETn0 SMB_DATA 32
29 30 CLK_SDATA 3,14,15
GND SMB_CLK CLK_SCLK 3,14,15
27 GND +1.5V 28 +1.5V
25 26 11/25 Modify. +1.5V
10 PCIE_RX6+ PERp0 GND
10 PCIE_RX6- 23 PERn0 +3.3Vaux 24 +WL_VDD
21 22 PLTRST#
GND PERST# PLTRST# 4,10,11,16,25,31,36
19 UIM_C4 W_DISABLE# 20 RF_EN 36
17 UIM_C8 GND 18
A_LFRAME#_R R645 0_4

Debug
15 GND UIM_VPP 16 LPC_LFRAME# 9,36
13 14 A_LAD3_R R646 0_4 C745 C747 C741
10 CLK_PCH_SRC2 REFCLK+ UIM_RST LPC_LAD3 9,36
11 12 A_LAD2_R R639 0_4 1000p/50V_4 .1u/10V_4 10u/6.3V_8
10 CLK_PCH_SRC2# REFCLK- UIM_CLK LPC_LAD2 9,36
9 10 A_LAD1_R R640 0_4
GND UIM_DATA LPC_LAD1 9,36
7 8 A_LAD0_R R641 0_4
10 PCIE_CLK_REQ2# CLKREQ# UIM_PWR LPC_LAD0 9,36
5 Reserved +1.5V 6 +1.5V
3 4
GND
GND
PCIE_WAKE#_R Reserved GND
1 WAKE# +3.3V 2 +WL_VDD
+WL_VDD
53
54
2
Q51
*DTC144EUA
3 1 PCIE_WAKE#_R
8,25 PCIE_WAKE#
B B
1/8 Change CN12,CN22 6pin conn footprint for Touch Screen.
+5V
11/27 Add by EMI C499 .1u/16V_4 CN12
*DLW21HN900SQ2L/300mA/90ohm
L46 6
USBP10-_R 5
10 USBP10- 3 3 4 4 4
2 2 USBP10+_R
10 USBP10+ 1 1 3
2
R702 0_4 1
R703 0_4 TS_6P_CON
+5V
C919 *.1u_4
11/27 Add by EMI CN22
L47 6
USBP5-_R 5
10 USBP5- 3 3 4 4 4
2 2 USBP5+_R
1 1
C C
10 USBP5+ 3
2
R704 *0_4 1
R705 *0_4 *3D@IR_CONN
11/18 Reserve C919, CN22 for NV IR signals on B-test
D D

PROJECT : ZR7
3B
MINI PCI-E card/Touch Screen
1 2 3 4 5 6 7 8
1 2 3 4
VIN
EE RETURN-PATH CAPACITORS
MAIN SATA HDD +5V
C8 0.1u/25V_4
C550 0.1u/25V_4
+5V C532 *.01u/25V_4 VIN
CN18
C529 *.1u/10V_4 C605 0.1u/25V_4
23 C613 *.01u/25V_4
GND23 C761 *.1u/10V_4 C604 0.1u/25V_4
A A
GND1 1
2 SATA_TXP0 9 C669 *.1u/10V_4 C547 0.1u/25V_4
RXP
RXN 3 SATA_TXN0 9
4 C293 *.1u/10V_4 C548 0.1u/25V_4
GND2 SATA_RXN0_C C715 .01u/25V_4 C523 *.01u/25V_4
TXN 5 SATA_RXN0 9 +3V VIN
6 SATA_RXP0_C C712 .01u/25V_4 C528 *.1u/10V_4 C603 0.1u/25V_4
TXP SATA_RXP0 9
GND3 7
C292 *.1u/10V_4 C549 0.1u/25V_4
+5V_S5 C520 *.1u/10V_4
8 C668 *.1u/10V_4 C606 0.1u/25V_4
3.3V C521 *.01u/25V_4
3.3V 9
10 C760 *.1u/10V_4 C64 0.1u/25V_4
3.3V
GND 11
GND 12
13 +5V C727 *.01u/25V_4 +3V
GND +5V_HDD
5V 14
5V 15
16 C512 *.1u/10V_4 +3V
5V
GND 17
RSVD 18
GND 19
B R547 *SHORT_8 +5V_HDD C920 0.1u/25V_4 B
12V 20 +5V +1.5V_CPUVDDQ
21 +VCC_CORE C925 0.1u/25V_4
12V C670 C678 C689 C688 C683 C681 C921 0.1u/25V_4
12V 22
+ +1.5V_CPUVDDQ C926 0.1u/25V_4
24 100u/6.3V_3528 10u/10V_8 *.1u/16V_4 *.1u/16V_4 .01u/25V_4 .01u/25V_4 +1.1V_VTT C923 0.1u/25V_4
GND24 C927 0.1u/25V_4
+1.1V_VTT
SATA_HDD +1.5V_SUS C924 0.1u/25V_4
1/14 Change footprint. 11/26 Add for EMI 11/25 Add for EMI
Q17
ODD (SATA) ODD POWER(ODD) +3VPCU +5V AO6402A +5V_ODD +5V
6 R153
5 4
1
2
CN14 R172 1 *0_8
14 100K_4
C GND14 C
R169
3
1 +15V 2 1 MOD_EN_5V
2
GND
A+ 2 SATA_TXP1 9 100K_4
1
A- 3 SATA_TXN1 9
4 C338
GND SATA_RXN1_C C250 .01u/25V_4 .1u/25V_6
5 SATA_RXN1 9
2
B- SATA_RXP1_C C247 .01u/25V_4
B+ 6 SATA_RXP1 9 2
GND 7
3
Q19
+5V_ODD DMN601K-7
8 SATA_DP R142 1K_4
1
DP R176 *SHORT_4 ODD_EN 2
5V 9 36 ODD_POWER
5V 10
11 Q18
MD C226 C231 C234 C222 C218 C633 R179 *0_4 DMN601K-7
+
GND 12 9 PCH_ODD_EN
13
1
GND .01u/25V_4 .01u/25V_4 *.1u/16V_4 *.1u/16V_4 10u/10V_8 100u/6.3V_3528
1
15
GND15 10/20 Unstuff
SATA_ODD R175
*100K_4
D
1/14 Change footprint. D
2
PROJECT : ZR7
3B
SATA-HDD/ODD/USB-ESATA
1 2 3 4
5 4 3 2 1
+5V
Mute(ADO)
R693
2/3 Modify RevD
+5V
HD@1K_4
HP 30 HP-L
R630 *0_4
reverse R441
R681 PD#
NHD@BAS316
D22 PCH_AZ_CODEC_RST#
30 HP-R ADOGND
3
R621 *SHORT_4 MIC1-VREFO-L *HD@10K_4 *BAS316 D20 EAPD#
MIC1-VREFO-L 30
MIC1-VREFO-R BAS316 D21
MIC1-VREFO-R 30 AMP_MUTE# 36
2
D ADOGND D
3
R629 *0_4 MIC1-VREFO-L
Q56
C731 10u/6.3V_6 PCH_AZ_CODEC_RST# 2 Q54 *HD@2N7002D
Codec(ADO) ADOGND
1
*HD@DTC144EUA
C732 Place next to pin 27
1
+
2.2u/6.3V_6
10/22 Add & Modify
C730 C739
C733 ADOGND +5VA
+5VA 10u/6.3V_6 .1u/10V_4 Place next to pin 25
+
2.2u/6.3V_6
C735 C737 C526 C525

10u/6.3V_6 .1u/10V_4
36
35
34
33
32
31
30
29
28
27
26
25
U43
.1u/10V_4 10u/6.3V_6
VREF
CBP
CPVEE
LDO-CAP
CBN
HP-OUT-R
MIC1-VREFO-R
HP-OUT-L
MIC1-VREFO-L
AVSS1
AVDD1
MIC2-VREFO
ADOGND ADOGND
ANALOG
Place next to pin 38
Spilt by AGND 37 AVSS2 LINE1-R 24 T111
38 23 ADOGND
AVDD2 LINE1-L T113
+5V R648 *SHORT_6 +5VPVDD1 39 22 MIC1-R

PVDD1 MIC1-R MIC1-R 30
C756 C752 C755 C751

30 L_SPK+ L_SPK+ 40 SPK-L+ MIC1-L 21 MIC1-L
MIC1-L 30
MIC
30 L_SPK- L_SPK- 41 20
10u/6.3V_6 .1u/10V_4 10u/6.3V_6 .1u/10V_4 SPK-L- MONO-OUT
C C
GND_EARTH R656 20K/F_4
42 PVSS1 (Vista Premium Version) JDREF 19 ADOGND
43 PVSS2 Sense-B 18
30 R_SPK- R_SPK- 44 17
SPK-R- MIC2-R
30 R_SPK+ R_SPK+ 45 16
SPK-R+ MIC2-L
+5V R672 *SHORT_6 +5VPVDD2 46 15

PVDD2 LINE2-R
GPIO0/DMIC-DATA
GPIO1/DMIC-CLK
EAPD# 47 14
C769 C770 C764 C763 SPDIFO2/EAPD LINE2-L
SENSEA R668 39.2K/F_4 LINEOUT_JD
SDATA-OUT
48 SPDIFO Sense A 13 LINEOUT_JD 30
10u/6.3V_6 .1u/10V_4 10u/6.3V_6 .1u/10V_4
SDATA-IN
DVDD-IO
PCBEEP
RESET#
BIT-CLK
49 R671 20K/F_4 MIC1_JD
DVDD1
DVSS2
PGND MIC1_JD 30
SYNC
ANALOG
PD#
Place next to pin 46 Spilt by DGND ALC271X
1
10
11
12
PCBEEP dont coupling any signals if possible
DIGITAL 8/17 separate PCBEEP to Digital from Realtek suggestion
1.6Vrms
30 SPDIF_OUT +3V
PCBEEP C773 1u/10V_6 BEEP_1 R691 47K/F_4
SPKR 9
C780 R690
C772 C779
.1u/10V_4 10u/6.3V_6 100p/50V_4
4.7K_4
1/7 R682 short.
R683 *0_6 +1.5V

B B
SBK160808T-301Y-N/0.2A/300ohm_6 Place next to pin 1 R682 *SHORT_6 +3V
23 DMIC0_1 L45 DMIC0
23 DMIC_CLK_1 DMIC_CLK C775 C774

L44
PCH_AZ_CODEC_RST# 9
SBK160808T-301Y-N/0.2A/300ohm_6 .1u/10V_4 10u/6.3V_6
C766
PCH_AZ_CODEC_SYNC 9
C783 C782 EMI request
*33p/50V_4 *33p/50V_4 ACZ_SDIN0_R R692 22_4 *100p/50V_4
PCH_AZ_CODEC_SDIN0 9
PCH_AZ_CODEC_SDOUT 9
Place next to pin 9
PD#
PCH_AZ_CODEC_BITCLK 9
0V : Power down Class D SPK amplifer
3.3V : Power up Class D SPK amplifer C781 *22p/50V_4
DIGITAL ANALOG
L43
Power (ADO) R689 *0_6
UPB201209T-310Y-N/6A/31ohm_8
+5V R688 *0_6
+5VA
U42 GND_EARTH don't coupling AGND and SPK signals
3 4 R582 *SHORT_6
IN OUT
2 R592 *0_6 GND_EARTH R666 *SHORT_6
GND R687 *0_6
A A
1 5 R631 *29.4K/F_4 R580 *0_6 R655 *0_6
SHDN SET R607 *0_6 R661 *0_6
*G923-330T1UF
R623 + C738 C736 C724 *1000p/50V_4
*10K/F_4 C725 *1000p/50V_4
C728 C734 10u/10V_3216 .1u/10V_4
+ R392 *SHORT_6
.1u/10V_4 R609 *0_4
10u/10V_3216 Quanta Computer Inc.
ADOGND ADOGND PROJECT : ZR7
ADOGND Size Document Number Rev
3B
C730, C787 close U37 pin3 and L65 REALTEK ALC271/MDC
5 4 3 2 1
5 4 3 2 1
MIC MIC1-VREFO-R
Internal Speaker
29 MIC1-VREFO-R
1/5 Modify to black.
29 MIC1-VREFO-L MIC1-VREFO-L
Normal OPEN Jack
R615 R588
4.7K/F_4 4.7K/F_4
CN19 BLACK
1 7
D C726 4.7u/6.3V_6 MIC1_L2 R614 1K/F_4 MIC1_L3 L42 SBK160808T-121Y-N/0.4A/120ohm_6 MIC1_L CN7 D
29 MIC1-L 2
6 29 R_SPK- R_SPK- R202 *SHORT_6 R_SPK-_1
C721 4.7u/6.3V_6 MIC1_R2 R601 1K/F_4 MIC1_R3 L38 SBK160808T-121Y-N/0.4A/120ohm_6 MIC1_R R_SPK+ R201 *SHORT_6 R_SPK+_1 1
29 MIC1-R 3 29 R_SPK+ 25
4 29 L_SPK- L_SPK- R200 *SHORT_6 L_SPK-_1
L_SPK+ R199 *SHORT_6 L_SPK+_1 36
8 29 L_SPK+ 4
29 MIC1_JD MIC1_JD 5
MIC_JACK SPEAKER-CONN
C352 C353 C351 C350
Max. 100mVrms input for Mic-IN *.22u/25V_6 *.22u/25V_6 *.22u/25V_6 *.22u/25V_6
ADOGND
MIC1_JD
C706 C729
1
470p/50V_4 470p/50V_4
D9
2 *VPORT_6
ADOGND
ADOGND
C C
HP/SPDIF
2/3 R368,R393 modify to 75ohm. +3V_SPD
CN20
HP_JD 1
HP-L R368 75_4 HPL-1 L27 SBK160808T-121Y-N/0.4A/120ohm_6 HPL_SYS 2
29 HP-L
3
HP-R R393 75_4 HPR-1 L30 SBK160808T-121Y-N/0.4A/120ohm_6 HPR_SYS 4
29 HP-R
5
R396 R367 C531 C522 7 LED

8 Drive
*1K_4 *1K_4 2200p/50V_4 2200p/50V_4 6 IC
SPDIF
ADOGND
ADOGND
B B
SPDIF_OUT L32 BLM15BD121SN1D/0.3A/120ohm_4 SPDIF_OUT_R

29 SPDIF_OUT
+5VA
+3V_SPD
+3V 1 3 LINEOUT_JD LINEOUT_JD 29

R377
3
Q53 C527 +5VA

ME2347 10K_4
2
0.22u/6.3V_4 HP_JD
LINE_JD# 2
R397 Q50
3
1
ADOGND
20K_4 2N7002D D19
1
A HP_JD 2 *VPORT_6 A
2
Q52
2N7002D ADOGND
ADOGND Quanta Computer Inc.
1
ADOGND PROJECT : ZR7

3B
AMP /AUDIO JACK CONN
5 4 3 2 1
A B C D E
CARD READER Controller

T110
T112
R642 *SHORT_4 XTALSEL C743 close PIN46, 47
+1.8V_VDD
Clock input selection C708 close PIN48, 47

+3V_VDD
XD_WE#/SD_CD#
'1' for 48MHz input [Default]
XD_CLE/SD_WP
C530
'0' for 12MHz input Main DFHD36MS006
4 .1u/16V_4 4
XTALSEL
CRMD_N
DATA1
DATA0
DATA7
DATA6
C742
NBMD
8/14 ZH7 remove R136, R591 and C775
Second DFHD36MS012
R643 *100K_4 +3V_VDD .1u/16V_4
R644 *SHORT_4 CARD_RST#
48
47
46
45
44
43
42
41
40
39
38
37
4,10,11,16,25,27,36 PLTRST# U44
C749 *0.47u/10V_6 CTRL0, CRTL 1 trace length shorter ,
XTALSEL
CTRL1
CTRL3
DATA1
DATA0
DATA7
DATA6
VDDHM
GND
VDD
NBMD
TRIST
and surround with GND.
+3V R636 *SHORT_6 +3V_VDD
C740 1 36 XD_ALE/MS_BS
GPON7 CTRL0 DATA5
2 EXT48IN DATA5 35
4.7u/10V_6 3 34 XD_RDY/SD_CMD
R657 330_4 RSTN CTRL2
4 33
5
REXT
VD33P
GPI4
DATA4 32 DATA4
DATA3
10/19
10 USBP12+ 6 DP DATA3 31
7 AU6437-GBL 30 DATA2
10 USBP12- DM DATA2
8 29 XD_WP#
C765 C767 XI VS33P XDWPN GPI2
9 XI GPI2 28 T115
XO 10 27 XD_CE#
*5p/50V_4 *5p/50V_4 XO XDCEN EEPDATA
11 VDD EEPDATA 26 T114
+1.8V_VDD 12 25 GPI1
VDD GPI1 T116
SDWPEN
AGND5V
EEPCLK
8/14 C707 close PIN11, 12
VDDHM
CF_V33
XDCDN
3 3
VCC33
CTRL4
GND
VDD
V18
V33
13
14
15
16
17
18
19
20
21
22
23
24
crystal trace width needs at least 10 mils.
EEPCLK
T117
8/14 pin13 output 20mils C777
C771 18p/50V_4 XI
4.7u/10V_6
VCC_XD
Y7 R675 *0_4 R694
12MHz 270K_4
XD_CD#
C776 18p/50V_4 XO
XD_RE#/MS_INS#
SD write protect
+1.8V_VDD 1:decided by SDWP[Default]
0:letting SD always
write-able
+3V_VDD +3V_VDD
C785 C786
4.7u/10V_6 .1u/16V_4
2 2
4 IN 1 CARD READER (MMC)

VCC_XD Close to CN14 pin 14 & pin23
4.7u CAP close to pin23
VCC_XD VCC_XD
CN9 R583 C708 C716

XD_RDY/SD_CMD 1 20 DATA1
XD_RE#/MS_INS# XD-R/B MS-DATA1 XD_ALE/MS_BS *5.1K_4 4.7u/10V_6 .1u/16V_4
2 XD-RE MS-BS 21
XD_CE# 3 22
XD_CLE/SD_WP XD-CE 4IN1-GND2
4 XD-CLE SD-VCC 23
XD_ALE/MS_BS 5 24 SD_CLK
XD_WE#/SD_CD# XD-ALE SD-CLK DATA0
6 XD-WE SD-DAT0 25
XD_WP# DATA2
DATA0
7
8
XD-WP XD-D2 26
27 DATA3
Close to connector
DATA1 XD-D0 XD-D3 DATA4 SBK160808T-121Y-N_6
9 XD-D1 XD-D4 28
DATA2 10 29 DATA1
DATA3 SD-DAT2 SD-DAT1 DATA5 XD_ALE/MS_BS R590 SD_CLK C709 *10p/50V/COG_4
11 SD-DAT3 XD-D5 30
XD_RDY/SD_CMD 12 31 DATA6
SD-CMD XD-D6 DATA7 XD_CLE/SD_WP R589 MS_SCLK C710 *10p/50V/COG_4
13 4IN1-GND1 XD-D7 32
14 MS-VCC XD-VCC 33
MS_SCLK 15 34 XD_CD# SBK160808T-121Y-N_6
1 DATA3 MS-SCLK XD-CD-SW XD_CLE/SD_WP 1
16 MS-DATA3 SD-WP-SW 35
XD_RE#/MS_INS# 17 36 XD_WE#/SD_CD# 11/26 Change FILTER by EMI
DATA2 MS-INS SD-CD-SW
18 MS-DATA2
DATA0 19 MS-DATA0
SHIELD1-GND 37 Quanta Computer Inc.

SHIELD2-GND 38
SHIELD3-GND 41 PROJECT : ZR7
SHIELD4-GND 42
CardReader 3B
AU6437 CardReader
A B C D E
5 4 3 2 1
POWER BOARD CONN(UIF) LED
2/4 modify by ME.

+3V_S5
D D
POWER Amber
LED1
+3V_S5 SUSLED# R409 715_4 4 2
36 SUSLED#
PWRLED# R408 20_4 3 1
36 PWRLED#
+3VPCU +3V_S5
1
LED_A/B
Blue
1
PWRLED# 2
PIPE LED will flash while R432 R412 *1M_4
battery insert at C-test +3VPCU
1
*100K/F_6 SUSLED# 2 Q1 R413 *1M_4
BSS84 +3VPCU
3
Q32 Battery
2 *BSS84 +3V Amber
36 ACPRN POWER/B LED2
3
12 R411 715_4 4 2
36 BATLED1#
Q33 PWR_LED 11 14
*BSS84 SUS_LED 10 13 R410 20_4 3 1
36 BATLED0#
3
C PIPE_LED C
9
D2 BAS316 8 LED_A/B
36 NBSWON#
7
36 NUMLED# 6
5
Blue
36 CAPSLED#
SATA_LED#_R 4
3
2
+3V 1 WLAN_LED#
2
CN1 Q57 +3V
R710 BSS84
*0_4
R5
36 WLAN_LED# Amber 3 1
LED3
5
10K/F_4 1
4 SATA_LED#_R R415 715_4 R711 *0_4
27,36 RF_LED#
9 SATA_ACT# 2
U31
3
*TC7SH08FU LED
12/17 Change by EC.
12/1 Modify LED
B R10 *SHORT_4 B
SW /B
+3V
+3V
CN4
1 +3V
R77 330_4 P_SAVE_LED 1
1 3 2 2
36 ODD_EJ 3 3
36 POWER_SAVE 4 C174
Q5 4 7
5 7
2
BSS84 5 8 .1u/10V_4
6 6 8
A A
36 P_SAVE_LED# SW/B_conn

R706 100K_4 ODD_EJ
R707 100K_4 POWER_SAVE PROJECT : ZR7
3B
12/1 Add POWER/MMB/LAUNCH/LED
5 4 3 2 1
5 4 3 2 1
11/16 Rev:B Modify

+5V_S5 BLUETOOTH CONNECTOR
USB Footprint to 5pin.
+3V_S5 BT_POWER
C485 CN8
U24 1 3 BT_POWER 5
1U/6.3V_4 USBPWR1 5
2 IN1 OUT3 8 4 4
3 7 Q23 USBP4+_R 3
IN2 OUT2 + C389 C390 USBP4-_R 3
6 2 7
2
D OUT1 + C693 C686 AO3413 1000p/50V_4 BT_LED 2 7 D
36 USBON# 4 EN# 2.2u/6.3V_6 T42 1 1 6 6
1 GND 36 BT_POWERON#
5 330u/6.3V_6X5.7 1000p/50V_4 BT_CONN_L
OC# C385
G547F2P81U *.01u/16V_4
1/5 Modify footprint.
10 USB_OC0#
CN17
1 1 8 8
USBP1-_R 2 7 11/26 Change footprint
USBP1+_R 2 7
3 3 6 6
11/26 Stuff common choke by EMI 4 4 5 5
USB_CONN_MB L19
DLW21HN900SQ2L/300mA/90ohm 3 USBP4+_R
10 USBP4+ 4 4
1
L25 3 USBP4-_R
10 USBP4- 2 2 1 1
2 2 USBP1-_R RV1 RV2
10 USBP1- 1 1 USBP1+_R
10 USBP1+ 3 3 4 4 *EGA-0402 *EGA-0402 R242 0_4
2
R246 0_4
R301 *0_4
C C
R302 *0_4
USB/B
11/18 Stuff common choke by EMI
11/25 L31 SWAP

L31
DLW21HN900SQ2L/300mA/90ohm +3VPCU +5V_S5 CN10
2 2 USBP3-_R
10 USBP3+ 3 3 4 4 1
2
3
R400 *0_4 4
5
R398 *0_4 6
7
8
B
36 USBON# 9 B
DLW21HN900SQ2L/300mA/90ohm 10
10 USB_OC1#
L29 11
10 USB_OC4_5#
2 2 USBP9-_R
12
10 USBP9+ 3 3 4 4 23,36 LID591# 13
14
15
R391 *0_4 USBP3-_R 16
USBP3+_R 17
R394 *0_4 18
USBP9-_R 19
USBP9+_R 20
21
DLW21HN900SQ2L/300mA/90ohm USBP11-_R 22
L28 USBP11+_R 23
2 USBP11-_R
10 USBP11- 2 1 1 USBP11+_R
24
10 USBP11+ 3 3 4 4
USB/B_CONN
R375 *0_4
R383 *0_4 11/2 Rev:B Change CN10 P/N by PDC.
A A

PROJECT : ZR7
3B
USB/ BT
5 4 3 2 1
5 4 3 2 1
CN2
MY0 1
36 MY0
MY1 2
36 MY1
MY2 3
36 MY2 +5V +5V
7 8 MX2 MY3 4 +3V +3V +3V
36 MY3
5 6 MX3 MY4 5
36 MY4
3 4 MX4 MY5 6
36 MY5
1 2 MX5 MY6 7
36 MY6
CP6 *100p/50Vx4 MY7 8 R457 R454 R467 R455
36 MY7
7 8 MX6 MY8 9
36 MY8
5 6 MX7 MY9 10 10K_4 10K_4 10K_4 10K_4
D 36 MY9 D
3 4 MY17 MY10 11
36 MY10
1 2 MY16 MY11 12 R458
36 MY11
CP5 *100p/50Vx4 MY12 13 FAN_PWM_E
36 MY12
7 8 MY3 MY13 14 *10K_4 CN11
36 MY13 36 FANSIG
5 6 MY2 MY14 15
36 MY14
2
MY1 MY15 1
3 4 36 MY15 16
3
MY0 MY16 2
1 2 36 MY16 17 3
CP1 *100p/50Vx4 MY17 18 2 Q36 1 3 FAN_PWM_CN
36 MY17 10,11,36 SML1ALERT# 4
7 8 MY7 MX7 19 MMBT3904
36 MX7
5 6 MY6 MX6 20 Q37 FAN
36 MX6
1
3 4 MY5 MX5 21 MMBT3904
36 MX5
1 2 MY4 MX4 22
36 MX4 36 CPUFAN#
CP2 *100p/50Vx4 MX3 23
36 MX3
7 8 MY11 MX2 24 27
36 MX2
5 6 MY10 MX1 25 28
36 MX1
3 4 MY9 MX0 26
36 MX0
1 2 MY8
CP3 *100p/50Vx4 KB
7 8 MY15
5 6 MY14 +3VPCU
3 4 MY13
1 2 MY12
CP4 *100p/50Vx4
C565 *100p/50V_4 MX1 RP2 10K_10P8R
C C
C566 *100p/50V_4 MX0 10 1 MX3
MX4 9 2 MX2
MX5 8 3 MX1
MX6 7 4 MX0
MX7 6 5 +5V +5V
L15 *SHORT_8 +TPVDD
C225
R143 R144 .1u/10V_4

10K_4 10K_4
HOLE2 HOLE1 HOLE9 HOLE13 HOLE3 HOLE30 HOLE25 CN6
*HG-C315D110P2 *HG-C315D110P2 *O-ZR7-1-B *HG-C276D110P2 *H-C91D91N *H-C91D91N *H-C91D91N 1
7 6 7 6 7 6 7 6 L16 *SHORT_6 2
36 TPDATA
8 5 8 5 8 5 8 5 TPDATA_R 3
9 4 9 4 9 4 9 4 L17 *SHORT_6 TPCLK_R 4
36 TPCLK
5
C223 C228 6
1
2
3
1
2
3
1
2
3
1
2
3
1
RIGHT# 7
*.01u/25V_4 *.01u/25V_4 8
9
HOLE19 HOLE23 HOLE27 HOLE28 HOLE4 10 13
B *HG-C276D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 HOLE22 HOLE21 11 14 B
7 6 7 6 7 6 7 6 7 6 *HG-C315D110P2 *H-C91D91N LEFT# 12
8 5 8 5 8 5 8 5 8 5 7 6
9 4 9 4 9 4 9 4 9 4 8 5 TP_CONN
9 4
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
SW3 SW2
RIGHT# 3 2 LEFT# 3 2
HOLE31 HOLE16 HOLE29 HOLE8 HOLE24 HOLE12 1 4 1 4
*hg-c236d110p2 *hg-c355d110p2 *hg-c394d110p2 *H-C236D142P2 *h-tc236d162pt *H-C236D142P2
7 6 7 6 7 6 SWITCH_1.5 SWITCH_1.5
8 5 8 5 8 5
9 4 9 4 9 4
1
2
3
1
2
3
1
2
3
HOLE5 HOLE7 HOLE11 HOLE20 HOLE26 HOLE18 HOLE17 HOLE14 HOLE15

A *H-TC197D122PT*H-TC197D122PT*H-TC197D122PT *h-tc236d162pt *h-tc236d162pt *H-TC236D142PT *H-TC236D142PT *H-TC236D142PT *H-TC236D142PT A

1
PROJECT : ZR7
3B
KB/FAN/TP+FP
5 4 3 2 1
1 2 3 4 5 6 7 8
11/12 PR90,PQ22 no stuff.
+0.75V_DDR_VTT +1.5V_CPUVDDQ
PR89 PR90
A A
22_8 *220_8
3
46 MAINON_DIS_G 2 46 MAINON_DIS_G 2
PQ23 PQ22
DMN601K-7 *DMN601K-7
1
+1.5V_SUS C291 *.1u_4
+1.5V_CPUVDDQ
C282 *.1u_4
C279 *.1u_4
C274 *.1u_4
B B
+3V_S5
+3V_S5 +1.5V_SUS
R138
R399
5
*10K/F_4 *1K_4
R395 2 R637
DDR3_DRAMRST# 14,15
*10K/F_4 4 PM_DRAM_PWRGD 4,8
3
3
1 Q15
Q25 *1.5K/F_4
+1.5V_CPUVDDQ *2N7002D U26
3
2 *TC7SH08FU R638 11 RST_GATE# 2

*750/F_4 R137
3
0_4
*BSS138
2
1
1
Q24
*PDTC143TT 4 CPU_DDR3_DRAMRST#
1
PWRGD_1.5VCPU 42
C C
+1.5V_SUS +1.5V_SUS
+1.5V_SUS
R140 R115
*1K/F_4 *1K/F_4
PQ16
1
2
5
6
R170 R167
10/29 Modify +SMDDR_VREF_DQ0 14 10/29 Modify +SMDDR_VREF_DQ1 15
*AO6402A
3
3 0_1206 0_1206
38,42,46 MAIND
Q14 Q13
R135 R114
RST_GATE# 2 *1K/F_4 RST_GATE# 2 *1K/F_4
4
+1.5V_CPUVDDQ
*A03402 *A03402
6A/maximum
1
7,14 VREF_DQ_DIMM0 7,15 VREF_DQ_DIMM1

D D

PROJECT : ZR7
3B
S3 power saving
1 2 3 4 5 6 7 8
5 4 3 2 1
EC(KBC) L18 PBY160808T-250Y-N/3A/25ohm_6 +A3VPCU

+3V
AR@ --> ARD CPU I/O ADDRESS SETTING(KBC)
30mil C382 C381 EV@ --> dGPU Only
+3VPCU
.1u/10V_4 10u/6.3V_6 SW@ --> iGPU & dGPU Switch
E775AGND
D8 C348 C347
1 2 +3VPCU_EC 0.03A(30mils)
R231 2.2_6 BAS316 4.7U/6.3V_6 .1u/10V_4
C379 C377 C391 C392 C376 C357
115
102
19
46
76
88
4
4.7U/6.3V_6 .1u/10V_4 *.1u/16V_4 .1u/10V_4 *.1u/16V_4 .1u/10V_4 U19
VCC1
VCC2
VCC3
VCC4
VCC5
AVCC
VDD
E775AGND C386 10u/6.3V_8 ICMNT SHBM=0: Enable shared memory with host BIOS
D D
C388 .01u/16V_4
9,27 LPC_LFRAME# 3 LFRAME GPIO90/AD0
97 TEMP_MBAT 37
126 98 WL_SW T43
9,27 LPC_LAD0 LAD0 GPIO91/AD1 3G_EN
127 99 SHBM R255 10K_4
9,27 LPC_LAD1 LAD1 GPIO92/AD2 SML1ALERT# 10,11,34
9,27 LPC_LAD2 128
LAD2 A/D GPIO93/AD3
100 ICMNT 37
9,27 LPC_LAD3 1 LAD3 GPIO05 108
CLK_PCI_775 CLK_PCI_775 2 96 VGA_THERM# 10/20 1/13 Comfirm by vendor mail :
10 CLK_PCI_775 LCLK GPIO04 VGA_THERM# 19,20
Disabled ('1') if using FWH device on LPC.
8 CLKRUN# 8 GPIO11/CLKRUN
101
Enabled ('0') if using SPI flash for both system BIOS and EC firmware
GPIO94/DA0 POWER_SAVE 32
R197 121 105 DGPU_IDLE#
11 SIO_A20GATE GPIO85/GA20 GPI95/DA1 DGPU_IDLE# 19
D/A GPI96/DA2 106
*22_4 122 107 10/28
11 SIO_RCIN# KBRST/GPIO86 GPI97
11 SIO_EXT_SCI#
D7 BAS316 29 ECSCI/GPIO54 LPC SM BUS PU(KBC) +3VPCU
GPIO01/TB2 64 ACIN 19,37
C360 EC_FPBACK# 6 95 MBCLK R252 10K_4
23 EC_FPBACK# GPIO24/LDRQ GPIO03 NBSWON# 32
*10p/50V/COG_4 93 MBDATA R251 10K_4
GPIO06/IOX_DOUT LID591# 23,33
NOCIR# 124 94 11/25 Modify unstuff.
T23 GPIO10/LPCPD GPIO07 SUSB# 8
119 +3V 11/25 Modify.
GPIO23/SCL3 MXM_SMCLK12 19,20 +3V
PLTRST# 7 109
4,10,11,16,25,27,31 PLTRST# LREST GPIO30/CIRTX2 ACPRN 32
120 2ND_MBCLK R249 *10K_4
GPIO31/SDA3 MXM_SMDATA12 19,20
USBON# 123 65 2ND_MBDATA R250 *10K_4 MXM_SMCLK12 R208 2.2K_4
33 USBON# GPIO67/PWUREQ GPIO32/D_PWM BATLED0# 32 MXM_SMDATA12
66 R207 2.2K_4
GPIO33/H_PWM BATLED1# 32
IRQ_SERIRQ 125 15
9 IRQ_SERIRQ SERIRQ GPIO36 VRON 39
16 11/25 Modify. +3V
GPIO40/F_PWM SUSLED# 32
9 17 AC_OFF
11 SIO_EXT_SMI# GPIO65/SMI GPIO42/TCK T15
GPIO 20 DGPU_IDLE# R425 SW@10K_4 ODD_EJ R265 *10K_4
GPIO43/TMS AMP_MUTE# 29
21 3G_SW T17 VGA_THERM# R428 SW@10K_4
MX0 GPIO44/TDI ODD_POWER R180 *10K_4
34 MX0 54 22 CPUFAN# 34
MX1 KBSIN0 GPIO45/E_PWM PANEL_COLOR
34 MX1 MX2
55 KBSIN1 GPIO46/CIRRXM/TRST 23 PANEL_COLOR 23 SW@ --> iGPU & dGPU Switch
34 MX2
MX3
56
57
KBSIN2 GPO47/SCL4 24
25
VIN_ON 37 10/26 UnStuff
C 34 MX3 MX4 KBSIN3 GPIO50/TDO D/C# 37 C
34 MX4 58 KBSIN4 GPIO51 26 S5_ON 38,46
MX5 59 27 8/11 modify +3VPCU
34
34
MX5
MX6
MX6
MX7
60
KBSIN5
KBSIN6
GPIO52/CIRTX2/RDY
GPIO53/SDA4
28
HDMI_HPD_EC# 24
ODD_POWER 28
ACER ID(KBC)
34 MX7 61 91 DNBSWON# 8
KBSIN7 GPIO81 U22
110
MY0 GPO82/TEST WLAN_LED MXM_SMCLK12
34 MY0 53
KBSOUT0/JENK GPO84/TRIST
112 WLAN_LED# 32 11/09 6
SCL A0
1
MY1 52 80 PANEL_ENG MXM_SMDATA12 5 2
34 MY1 KBSOUT1/TCK GPIO41 PANEL_ENG 23 SDA A1
MY2 51 3
34 MY2 KBSOUT2/TMS A2
MY3 50
34 MY3 KBSOUT3/TDI
MY4 49 KB 31 ODDLED T20 7 8
34 MY4 MY5 KBSOUT4/JEN0 GPIO56/TA1 WP VCC
34 MY5 48 117 SUSON 42 4
MY6 KBSOUT5/TDO GPIO20/TA2/IOX_DIN GND C417
34 MY6 47 KBSOUT6/RDY GPIO14/TB1 63 FANSIG 34
MY7 43 *ACER_ID_EEPROM
34 MY7 KBSOUT7
MY8 42 TIMER 32 *.1u/10V_4
34 MY8 KBSOUT8 GPIO15/A_PWM CONTRAST 23
MY9 41 118
34 MY9 KBSOUT9/SDP_VIS GPIO21/B_PWM NUMLED# 32
MY10 40 62
34 MY10 KBSOUT10/P80_CLK GPIO13/C_PWM PWRLED# 32
MY11 39 81
34 MY11 KBSOUT11/P80_DAT GPIO66/G_PWM CAPSLED# 32
MY12 38
34 MY12 MY13 KBSOUT12/GPIO64
37 12/7 Change to 512K
34
34
MY13
MY14
MY14
MY15
36
KBSOUT13/GPIO63
KBSOUT14/GPIO62 GPIO77/SPI_DI 84
3G_EN
ODD_EJ 32
SPI FLASH(KBC) +3VPCU
34 MY15
MY16
35 KBSOUT15/GPIO61/XOR_OUT SPI GPO76/SPI_DO/SHBM 83 3G_EN
34 82 11/09 U21
34 MY16 GPIO60/KBSOUT16 GPIO75/SPI_SCK RF_LED# 27,32
MY17 33 SPI_SDI_uR R266 22_4 SPI_SDI_uR_R 2 8
34 MY17 GPIO57/KBSOUT17 SO VDD
75 RSMRST#_uR R254 *SHORT_4 SPI_SDO_uR 5 7 C449
GPIO72/IRRX1/SIN2 ICH_RSMRST# 8 SI HOLD
MBCLK 70 73
37 MBCLK GPIO17/SCL1 GPIO70/IRRX2_IRSL0 SUSC# 8
MBDATA 69 74 PWROK_EC_uR R253 *SHORT_4 SPI_SCK_uR 6 3 .1u/10V_4
37 MBDATA GPIO22/SDA1 GPIO71/IRTX/SOUT2 PWROK_EC 8 SCK WP
2ND_MBCLK 67 SMB IR 113
10 2ND_MBCLK GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR RF_EN 27
10 2ND_MBDATA 2ND_MBDATA 68 14 CIRR_X2 T16 +3VPCU R259 10K_4 SPI_CS0#_uR 1 4
GPIO74/SDA2 GPIO34/CIRRXL HWPG CE VSS
GPIO16/CIRTX 114
111 P_SAVE_LED# W25X40BVSSIG
GPO83/SOUT_CR/XORTR P_SAVE_LED# 32
TPCLK 72
34 TPCLK TPDATA GPIO37/PSCLK1
34 TPDATA 71 GPIO35/PSDAT1 1/13 Comfirm by vendor mail :
PCH_ACIN 10 86 SPI_SDI_uR
B
10/20 8 PCH_ACIN
33 BT_POWERON# 11
GPIO26/PSCLK2
GPIO27PSDAT2 PS/2
F_SDI
F_SDO
87 SPI_SDO_uR_R
SPI_CS0#_uR
R261 22_4 SPI_SDO_uR
If the Southbridge enables 'Long Wait Abort' by
default, the flash device should be 50MHz (or faster)
B
CR_PSAVE
40,41,42,45,46 MAINON 12
GPIO25/PSCLK3 FIU F_CS0
90
SPI_SCK_uR_R SPI_SCK_uR
T18 13 92 R247 22_4
GPIO12/PSDAT3 F_SCK
8 ICH_SUSCLK R263 *SHORT_4 E775_32KX1 77 30 ECDB_CLOCK R260 100K_4 SPI_SDI_uR
GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN T19
+3V
VCC_POR
85 VCC_POR# R256 47K/F_4 +3VPCU HWPG(KBC)
10/27 Modify
VCORF
AGND
GND1
GND2
GND3
GND4
GND5
GND6
R264 *20M_6 E775_32KX2 79 104 VREF_uR R238 *SHORT_4 +A3VPCU R217

GPIO02 VREF
R279 NPCE781 10K_4

5
18
45
78
89
116
103
VCORF_uR 44
D17 BAS316 HWPG

Y1 *33K/F_4
SM BUS ARRANGEMENT TABLE 40,45 HWPG_VTT
1 4 D12 BAS316
45 HWPG_1.8V
SM Bus 1 Battery R222
L20 D14 BAS316
41 HWPG_1.05V
*SHORT_4
C400 *32.768KHz C431 PBY160808T-250Y-N/3A/25ohm_6 C374 SM Bus 2 PCH D13 BAS316
42 HWPG_1.5V
MPWROK 4
*15p/50V_4 *15p/50V_4 1u/6.3V_4 D15 BAS316
38 SYS_HWPG
E775AGND E775AGND SM Bus 3 MMB3 and EEPROM
D16 AR@BAS316 AR@ --> ARD CPU
44 HWPG_AXF
SM Bus 4 HDMI Controller, MMB1, MMB2 and VGA Thermal Add D23 EV@BAS316 EV@ --> dGPU Only
11,18 dGPU_PWROK
POWER-ON Switch(KBC) INTERNAL KEYBOARD STRIP SET(KBC)

A A
10/26 UnStuff +3VPCU
SW1
*SWITCH_1.5 MY0 R230 *10K_4
NBSWON# 1 2
3 4
2
5
D1 6
*VPORT_6 Quanta Computer Inc.
PROJECT : ZR7
1

3B
WPCE781 & FLASH
5 4 3 2 1
5 4 3 2 1
VA PD5 PR133
PL3 SBR1045SP5-13 PQ30 0.01/F_7520 VIN_SRC PQ32
PJ2 HI0805R800R-00_8 1 FDD6685 FDD6685
1 VDC 3 VA1 3 4 1 2 3 4 BAT-V
2 2
3
4
1
1
PC110 PC109 PC108 PR129 PC13 PC11 PR134
POWER_CONN PL4 .1u/50V_6 .1u/50V_6 PD6 .1u/50V_6 220K/F_6 .1u/50V_6 2200p/50V_6 33K_6
HI0805R800R-00_8 SMAJ20A VIN_SRC
9/1 modify
2
D PC114 PC111 PC115 EC1 EC2 CSIP_1 D
.1u/50V_6 2200p/50V_6 *22u/25V_1210 1 6 PR135
.1u/50V_6 *22u/25V_1210 10K_6
PD1 PR125 2 5
SW1010CPT 220K/F_6
2/5 Add by EMI 3 4
3
PQ31
IMD2AT108
VDC 2
36 D/C#
PQ36
DMN601K-7
1
EC3 EC4 EC5 VIN_SRC VIN_SRC
*10u/25V_1206 *10u/25V_1206 *10u/25V_1206
CSIP_1 PC30
1u/16V_6
PR31 PR30
10/F_6 10/F_6
PR25 PC20
PC32 4.7_6 PC23 10u/25V_1206
11/16 Modify PU3 footprint. .1u/50V_6 1u/16V_6
PC116
CSIP CSIN .1u/50V_6
PD7 PC117
33
32
31
30
28
27
26
21
C C
1
+3VPCU PC29 +3VPCU *RB500V-40 2200p/50V_6
5
6
7
8
PU2 .1u/50V_6
VDDP
CSSP
NC
GND
GND
GND
GND
CSSN
VCC
CM1293A-04SO
1 6 MBDATA PR29 PC28 12/30 Modify.
CH1 CH4 2.7_6 .1u/50V_8 88731_DH 4
2 5 +3VPCU PR28 MBDATA 11 25
VN VP 100K/F_6 VDDSMB BOOT PQ5
TEMP_MBAT 3 4 MBCLK AO4468 0.01_3720
CH2 CH3 MBCLK 9 24 PR136
SDA UGATE PL5
6.8uH
3
2
1
10 23 88731_LX 1 2 BAT-V
19,36 ACIN SCL PHASE
5
6
7
8
13 20
ACOK LGATE PR22
PC26 88731_DL 4 *4.7_6 PC7
PR26 .1u/50V_6 19 0.01u/50V_6
PR9 49.9/F_6 PGND
*SHORT_6 DCIN 22
DCIN PU3 PR23 PQ4 PC19
PR34 ISL88731A 10/F_6 AO4710 *680p/50V_6 PC106
82.5K/F_6 18 CSOP CSOP_1 2200p/50V_6
3
2
1
CSOP PC8 PC107
2
PC105 ACIN 10u/25V_1206 10u/25V_1206
.1u/50V_6 PC24
2 1 PR33 3 .1u/50V_6
VREF
B
22K/F_6 17 CSON BAT-V 1/11 Add PC3100 by EMI B
CSON
PC104 4 PR24 CSOP_1 VIN_SRC VIN
100p/50V_6 ICOMP 10/F_6 PQ33
16
NC BAT-V AOL1413
5 PR27 1
HI0805R800R-00_8 NC *SHORT_4 2 5
PJ1 PL2 15 BAT-V 3
MBAT+ BAT-V VBF PC3100
6
10 1 VCOMP PR12
29
2 GND 100_4
GND
4
3
ICM
NC
NC
PL1 PC112 PR19
4 HI0805R800R-00_8 1U/25V_6 150K_6
5 PD4 *10u/25V_1206
7
14
12
6 RB500V-40
7 PR32
9 8 TEMP_MBAT 2.21K/F_6
TEMP_MBAT 36
Batt_Conn PR13
PC5 PC6 *0_6 PR20
9/1 modify 47p/50V_6 47p/50V_6 39K_6
PC36
ICMNT 36 1/11 Add by EMI VIN_SRC 11/23 Modify
+3VPCU
0.01u/50V_6
3
PR17
100K/F_6
2
PR10 PR11 PC33

100_4 100_4 *1u/16V_6 PC35 2
36 VIN_ON
PC34 *0.01u/50V_6
1
MBCLK 36 0.01u/50V_6 PQ3

DMN601K-7
A A
1
MBDATA 36
PC31
3300p/50V_4
PC3101 PC3103 PC3105 PC3107
*10u/25V_1206 *10u/25V_1206 *10u/25V_1206 *10u/25V_1206
1
PC3102 PC3104 PC3106 PC3108

PR18 PC12 *10u/25V_1206 *10u/25V_1206 *10u/25V_1206 *10u/25V_1206
*100K/F_6 0.01u/50V_6
PROJECT : ZR7
2

3B
CHARGER (ISL88731)
5 4 3 2 1
5 4 3 2 1
MAIND
MAIND 35,42,46
PR109 *SHORT_4 VL
4,46 SYS_SHDN# 2/11 Del PD3 and
change PR105 and
PR106.
VIN_SRC
1
D D
PR213 VIN_SRC
39K/F_4 VL
Add 100u cap
PC188 PC192
2
+ .1u/50V_6 10u/25V_1206 PC174
2
3V5V_EN 4.7u/10V_8
PR111
PC187 PC93 0_4
1
2200p/50V_6 *10u/25V_1206 PR211
PR220 PR221 0_4
1
*SHORT_4 *SHORT_4
PC198 PR106 PC90 PR110 PC100 PC97
390K_4 PC173 1u/16V_6 *0_4 .1u/50V_6 10u/25V_1206 OCP : 8A
2
5V_EN
3V_EN
100u/25V_6.3X5.8 .1u/50V_6 PC94
5
6
7
8
PC172 2200p/50V_4
6.21A
2
.01u/16V_4 PC92
.1u/50V_6
1
L(ripple current) REF +3VPCU
OCP: 10A 4
1
3V_DH PQ71
=(19-5)*5/(2.2u*0.4M*19)
8
7
6
5
PR107 *0_6 AO4468
5.64A ~4.18A PR105
+5VPCU 150K_4
8
7
6
5
4
3
2
1
Iocp=10-(4.18/2)=7.91A 4 5V_DH
PL13
LDO
ONLDO
LDOREFIN
VIN
NC
VCC
TON
REF
Vth=7.91A*14.2mOhm=112.322mV
3
2
1
changed on 11/19 2.2uH_14A
R(Ilim)=(112.322mV*10)/5uA PQ69
~220K AO4468 changed on 11/19 PR114 3V_LX
5
6
7
8
1
+5VPCU 9 32 REFIN2 182K/F_6
PL14 BYP REFIN2 PR118 change to 330u/6.3V_6x5.7
10 31 1 2
1
2
3
2.2uH_14A OUT1 ILIM2
C 11 FB1 OUT2 30 *2.2_6 C
5V_LX 1 2 12 PU9 29 SKIP 4
PR115 200K/F_6 DDPWRGD_R 13 ILIM1 RT8206B SKIP# DDPWRGD_R +
28
2
PGOOD1 PGOOD2
1
8
7
6
5
change to 330u/6.3V_6x5.7 5V_EN 14 27 3V_EN
PR216 PR236 EN1 EN2 PR214
15 DH1 DH2 26
*0_4 *2.2_6 16 25 PC99 *SHORT_6 PC169
PC175 5V_DL LX1 LX2 *2200p/50V_6 330u/6.3V_6X5.7
4 37 PAD
+ 36
2
3
2
1
PAD
PGND
PVCC
PC89 PQ70
BST1
BST2
GND
PAD
PAD
PAD
DL1
DL2
.1u/50V_6 PC177 PC178 AO4710 PD9
NC
330u/6.3V_6X5.7 PC199 .1u/50V_6 .1u/50V_6 SX34 1 2
PR112 *2200p/50V_6 PQ72 PR224 PR215 *0_4
35
34
33
17
18
19
20
21
22
23
24
*SHORT_4 AO4710 PR225 1/F_6 1 2
1
2
3
1/F_6 1 2 PR218 *SHORT_4

PD12 1 2 3V_DL
SX34 PC166
.1u/50V_6
PC91 PR227 VL PR212 SKIP PR116 *0_6 REF
10u/25V_1206 *0_6 *SHORT_6 PR113
PC182 *0_6
2 .1u/50V_6 PC180
PD10 1u/16V_6
CHN217UPT 3
OCP:8A PR219
1 *SHORT_6 +3VPCU
PR226 L(ripple current) 0 ohm change to shot pad 2/12 09
*SHORT_6
PC98 2 =(19-3.3)*3.3/(2.2u*0.5M*19)
.1u/50V_6 PD11
3
~2.48A
CHN217UPT PR108
B B
PC183 Iocp=8-(2.48/2)=6.67A 100K/F_4
1 .1u/50V_6
Vth=6.67A*15mOhm=94.714mV
PR233
R(Ilim)=(94.714mV*10)/5uA
+15V_ALWP DDPWRGD_R
+15V ~191K SYS_HWPG 36
PR217 *SHORT_4
22_8 PC196
.1u/50V_6
+5VPCU +3VPCU
VIN_SRC +3V_S5 +5V_S5 +15V +5VPCU
5
6
7
8
5
6
7
8
+3VPCU
PR206 PR190 PR196 PR188 MAIND 4 MAIND 4

1M_6 22_8 22_8 1M_6
5
6
7
8
3
PQ27 PQ25
AO4496 AO4496
S5D 4
S5D 2
3
2
1
3
2
1
3
2 PQ24 2.79A 2.83A

36,46 S5_ON
A AO3404 A
2 2 2 PC160 1
3
2
1
+5V +3V
PR205 PQ26
1
+3V_S5
PQ65 1M_6
DTC144EU AO4496
PQ67 PQ68 2200p/50V_4
0.23A
1
DMN601K-7 DMN601K-7 PQ66

DMN601K-7
+5V_S5
2.85A
PROJECT : ZR7
3B
SYSTEM 5V/3V (RT8206)
5 4 3 2 1
5 4 3 2 1
[PWM]
PR71, PR72, PR73, PR74, PR75, PR76, and PR77 deleted
VR_PWRGD_CK505# 3 VIN
DELAY_VR_PWRGOOD 4,8
1
1
+
PC141 PC61 PC65 PC145 PC132
2200p/50V_6 .1u/50V_6 10u/25V_1206 10u/25V_1206 100u/25V_6X7.7
2
PQ57
5
AOL1448
8/4 EMI request

62882_DH1 4
D
changed on 11/19 20A D
1
2
3
+VCC_CORE
VIN +3V
PL10 0.36uH
62882_LX1 1 2
PR78 PQ58 PQ59
4
5
5
*SHORT_6 AOL1718 AOL1718 PR82
+ PC71
PR172 PR163 *2.2/F_6
+5V_S5 1.91K/F_4 1.91K/F_4 330u/2V_7343
11/16 Modify PU8 footprint. 4 4
PC66
1
2
3
1
2
3
PR77 .22u/25V_6 5/12 Change pr144 from 10K to 1.91K PC68
10_6 *1000p/50V_6
PR62 *SHORT_8
PR171 PR174
16
17
40
1
PU8 *SHORT_4 *SHORT_4
CLK_EN#
VDD
VIN
PGOOD
PC63
1u/6.3V_4
41
+1.1V_VTT PAD
20
7/16 modify UGATE1 PR61 10K/F_4
19 1 2
PR165 BOOT1
*499/F_4 PR164 10K/F_4 2 PR181 VSUM+ PR170 3.65K/F_4
6 H_PSI# PSI# 2.2_6 PC148
PR66 147K/F_6 3 .22u/25V_6
RBIAS VSUM- PR173 1/F_4
21
PHASE1
4 H_PROCHOT# 4
VR_TT# 62882_DL1A
23
PR180 PR55 LGATE1a PR65 10K/F_4
C Close to Phase 1 Inductor *470K_4_NTC *4.02K/F_4 C
5 VIN
PC58 NTC
*.01u/16V/X7R_4 24 62882_DL1B
1
LGATE1b
1 2
1
22 +
VSSP1 PC154 PC75 PC74 PC153 PC155
11 62882_ISEN1 2200p/50V_6 .1u/50V_6 10u/25V_1206 10u/25V_1206 100u/25V_6X7.7
2
H_VID0 ISEN1
6 H_VID0 31
VID0
1
H_VID1 32
6 H_VID1 VID1 PC135 PQ62 8/4 EMI request
5
H_VID2 33 0.22u/10V_4 AOL1448
6 H_VID2
2
VID2 VSUM-
H_VID3 34 8/10 modify
6 H_VID3 VID3 62882_DH2 4
H_VID4 35 25 PR185 0_4 +5V_S5 changed on 11/19
6 H_VID4 VID4 VCCP
ISL62882
20A
1
2
3
H_VID5 36 PC150 1u/6.3V_4
6 H_VID5 VID5 +VCC_CORE
1 2
H_VID6 37
6 H_VID6 VID6 PC70 1u/6.3V_4 PL11 0.36uH
VRON 38 1 2 62882_LX2 1 2
36 VRON VR_ON PQ61 PQ60
5
DPRSLPVR 39 29 AOL1718 AOL1718
6 H_DPRSLPVR
4
DPRSLPVR UGATE2
2
PR175 30 1 2 PR88
PR177 499/F_4 BOOT2 62882_DL2 + PC72
4 4
100K/F_4 PR183 *2.2/F_6
2.2_6 PC149 330u/2V_7343
1
1
2
3
1
2
3
8 .22u/25V_6
FB
28
PHASE2 PR162 PR167
PR67 PC133 26
*10K/F_4 22p/50V_4 LGATE2 PC73 *SHORT_4 *SHORT_4
9 27 *1000p/50V_6
FB2 VSSP2
B B
PR56 10 62882_ISEN2
412K/F_4 PC52 ISEN2
2 1
1
150p/50V_4 7 PC134
COMP 0.22u/10V_4
2
VSUM-
8/10 modify
PC136
10p/50V/COG_4 PR54 6
8.06K/F_4 VW
18 I_MON 6
IMON
PR52 10K/F_4
1
PR182 PC146
PC54 9.76K/F_4 0.033u/16V_4
1000p/50V_4 VSUM+ PR161 3.65K/F_4
2
5/12 Change pr24 rom 2.87K to 2.8K

ISUM+
ISUM-
VSEN
VSSSENSE
RTN
PR57 VSUM- PR166 1/F_4
5/12 Change pc92 rom 0.33u_4 to 0.22u_6

12
13
14
15
2.8K/F_4 5/12 stuff pc26 0.068u_6 PR60 10K/F_4
PC144 PC143
PR58 PC55 0.22u/10V_6 0.068u/25V_6
562/F_4 390p/50V_4 VSUM+
1
+VCC_CORE 1 2 PR168 PR59

PR63 *27.4_4 82.5/F_4 2.61K/F_4
2
PC59
PC142 PR178
PR64 *SHORT_4 330p/50V_4 11K/F_4
6 VCCSENSE
Parallel PC137 PC138 PR184
2700p/50V_4
2
A PR71 *SHORT_4 330p/50V_4 .01u/16V_4 10K_6_NTC Panasonic A

6 VSSSENSE
PC60
PR179 ERT-J1VR103J
1
1 2 1000p/50V_4 *SHORT_4
PR70 *27.4_4
VSUM-
5/12 Change pr34 rom 1K to 1.24K
PR176
1.24K/F_4 PC140
.1u/10V_4 Close to Phase 1 Inductor
PC139 PR169 Load Line setting to 2mV/A
*1000p/50V_4 *100/F_4 PROJECT : ZR7
5/12 un-stuff PC76,PR140 CPU Core ( ISL62882) 3B

5 4 3 2 1
5 4 3 2 1
[PWM]
VIN
SP@ --> Operation P/N +5V_S5
PR156 PD8
10_6 RB500V-40
5
D PR152 D
2.2/F_6
1
PR158 OCP: 18A
1M/F_6 PC123 4 1.1V/15A
4.7u/6.3V_6
2
PR157 PC126 PC125 PC42
1
2
3
PU7 *SHORT_6 PQ52 2200p/50V_4 .1u/50V_6 10u/25V_1206
PR159 UP6111AQDD AOL1448 PC41
*SHORT_6 PC128 *10u/25V_1206
15 13 .1u/50V_6 changed on 11/19
36,41,42,45,46 MAINON EN/DEM BOOT PL8
+3V 16 12 UGATE-VTT 2.2uH
PC45 TON UGATE
*.1u/50V_6 1 11 PHASE-VTT 1.1VVTT_SRC
VOUT PHASE +1.1V_VTT
2 10 PR155 3.3K/F_6
VDD OC
5
PR45 PL7
V2@10K/F_6 3 9 PC124 2.2uH
FB VDDP + +
4 8 1u/16V_6 LGATE-VTT 4 PR151
36,45 HWPG_VTT PGOOD LGATE *4.7_6
6 7 PQ49 PC37
1
2
3
C GND PGND AOL1718 330u/2V_7343 C
5 NC TPAD 17
PC122
stuff on 1/13 14 *680p/50V_6
NC
1
PC43 PC120
330u/2V_7343 .1u/50V_6
PC40 PC44 PC121
2
1u/16V_6 *1000p/50V_6 10u/10V_8
VOUT=(1+R1/R2)*0.75
PR154 PC127
R1 CSP@4.7K/F_6 *33p/50V_6
CSP@ --> Operation P/N (ARD&CFD)
PR42 VTT_FB
*SHORT_6 SP@ BOM change notice
B B
PR153
Arrandale (1.05V) R1 = 4.02K (CS24023F928)
R2 10K/F_6
Clarksfield(1.1V) R1 = 4.75K (CS24753F919)
AO1718 Rdson=3~4.3mOhm
TON=3.85p*RTON*Vout/(Vin-0.5)
L(ripple current)
Frequency=Vout/(Vin*TON) =(19-1.05)*1.05/(1u*272k*19)
~3.64A VIN
TON=3.85p*1M*1/(Vin-0.5) 4.3m*18=RILIM*20uA
RILIM=3.87K --- 3.92K
Frequency=1/(0.0036767)=272K
A C930 C931 C932 C933 C934 A

10u/25V_1206 *10u/25V_1206
10u/25V_1206 10u/25V_1206 *10u/25V_1206
2/11 Add C930~C934 by monitor test.
PROJECT : ZR7
3B
+VTT (UP6111A)
5 4 3 2 1
5 4 3 2 1
VIN
+5V_S5
PR120 PD13
D D
10/F_6 RB500V-40
5
6
7
8
1
PR241
PR234 2.2/F_6 PC205 4 1.05V/8A
4.7u/6.3V_6 PQ73
1M_6 OCP: 10A
2
PR235 AO4468 PC101 PC200 PC202
PU11 *SHORT_6 2200p/50V_4 .1u/50V_6 10u/25V_1206
PR119 UP6111AQDD
*SHORT_6 PC197
15 13 .1u/50V_6
36,40,42,45,46 MAINON
3
2
1
EN/DEM BOOT PL16
+3V 16 12 UGATE-1.05V 2.2uH_8A
PC194 TON UGATE
*.1u/50V_6 1 11 PHASE-1.05V
VOUT PHASE +1.05V
PR240 2 10 PR121 5.76K/F_6 8/24 modify
VDD OC
5
6
7
8
*10K/F_6
3 9 PC203
FB VDDP 1u/16V_6
C C
4 8 LGATE-1.05V 4 PR242
36 HWPG_1.05V PGOOD LGATE +
*4.7_6
6 7
Rds*OCP=RILIM*20uA
GND PGND
5 NC TPAD 17
PQ74 PC206
14 AO4710 *680p/50V_6
3
2
1
NC
1
PC190
10u/10V_8
PC102 PC195 PC193
2
1u/16V_6 *1000p/50V_6 .1u/50V_6

PC204
560u/2.5V_6X5.7
B B
PR237 PC201
R1 4.02K/F_6 *33p/50V_6
1.05V_FB
VOUT=(1+R1/R2)*0.75
PR238
10K/F_6
R2 PR239
*SHORT_6
TON=3.85p*RTON*Vout/(Vin-0.5)
AO4710 Rdson=11.7~14.2mOhm
Frequency=Vout/(Vin*TON) L(ripple current)
A =(19-1.05)*1.05/(1u*272k*19) A
TON=3.85p*1M*1/(Vin-0.5) ~3.646A Quanta Computer Inc.

Frequency=1/(0.0036767)=272K 14.2m*10=RILIM*20uA PROJECT : ZR7
RILIM=7.1K--- 7.15K 3B
VCCP 1.05V(UP6111A)
5 4 3 2 1
5 4 3 2 1
[PWM]
PC49
10u/10V_8
PR50 PC48
*SHORT_6 .1u/50V_6
+0.75V_DDR_VTT
VIN
8207_DH
PC51 PC50
D 2.25A 10u/10V_8 10u/10V_8 8207_LX
D
5
8207_DL
PC130 PC47 PC129 OCP 22A
25
24
23
22
21
20
19
1
2
3
PQ55 2200p/50V_6 10u/25V_1206 10u/25V_1206
AOL1448 PL9 18A
GND
VLDOIN
DRVH
VTT
VBST
LL
DRVL
0.56uH
+1.5V_SRC +1.5V_SUS
1 VTTGND PGND 18
2 VTTSNS CS_GND 17
+ +
5
3 RT8207A 16 PR51
GND PU4 CS 5.6K/F_6 +5V_S5 PR160
4 4 *4.7_6
+1.5V_SUS 4 15
MODE V5IN PR53 PQ56 PQ14
1
2
3
1
2
3
5.1/F_6 AOL1718 AOL1718
+SMDDR_VREF 5 VTTREF V5FILT 14
1
PC56 PC131
C 0.75A C
VDDQSNS
VDDQSET
PC57 +5V_S5 6 13 1u/6.3V_4 PC53 *680p/50V_6 PC152 PC151 PC147
2
0.033u/50V_6 COMP PGOOD 1u/6.3V_4 560u/2.5V_6x5.7 560u/2.5V_6x5.7 10u/10V_8
2
NC
NC
PR73 100K/F_6
S3
S5
+3VPCU
change to 560u/2.5V_6x5.7
FOR DDR III
7
10
11
12
HWPG_1.5V 36
PR74 (For RT8207A 400KHZ )

VIN
620K/F_4
S5_1.8V PR76
*SHORT_6 SUSON 36
S3_1.8V PR75 0/F_6
MAINON 36,40,41,45,46
PR80 *0/F_6 Add it for S3 leakage circuit
PWRGD_1.5VCPU 35
PR69
*0/F_6 +5V_S5 7/23 modify
PR68
*SHORT_6
PC64 PR72
*33p/50V_6 10K/F_4
Vout = (PR150/PR149) X 0.75 + 0.75 AO1718 Rdson=3.8~4.3mOhm
+1.5V_SUS
L(ripple current)
B =(9-1.5)*1.5/(0.56u*400k*9) B
~5.58A
PR79
Vtrip= (22-2.79)(*4.3mohm/2)=0.0413V
3
10K/F_4 PC62
*0.033u/50V_6
RILIM=Vtrip/10uA~4.13K
MAIND 2
35,38,46 MAIND
PQ20
AO3404
1
S3 S5 VTT REF +1.5VSUS
S0 1 1 ON ON ON +1.5V
S3 0 1 OFF ON ON
2.03A
S4/S5 0 0 OFF OFF OFF
A A

PROJECT : ZR7
3B
DDR III 1.5V(TPS51116)
5 4 3 2 1
1 2 3 4 5
11/16 Change VGPU_CORE to two phase solution.

V2@ --> Two Phase dGPU only
EV@ --> External VGA SKU +5V_S5
PR3001
SW@ --> iGPU & dGPU Switch V2@10_6
MAX17007_VCC
11M@ --> N11M-GE1 Setitng

VIN VIN
PC3002
4 18 V2@2.2u/6.3V_6
A VCC VDD A
PC3001
V2@@1u/10V_6 PR3005 PC3004 PC3005
5
SW@ --> iGPU & dGPU Switch MAX17007_BST1
V2@0_6 V2@0.1u/50V_6 V2@10u/25V_1206
16 15 PC3003 PC3006
GND BST1 PQ3001 V2@2200p/50V_4 V2@10u/25V_1206
PR3004 4 V2@AOL1448
PC3007
PR3006 V2@0_6 V2@0.22u/25V_6
1
2
3
*SW@0_4
17007_EN 11 13 MAX17007_DH1 ripple current~=3.2A--> current
11,47 dGPU_VRON EN1 DH1
limit=60mV(Vcc) & Rdcr_eq=2.69mohm
PR3002 V2@100K_4 25 PL3003 DCR=3m
PR124 EN2 V2@1uH -->OCP=(60mV/2.69m+3.2A/2)*2=48A
ES@0_4 14 MAX17007_LX1
LX1
+3V_GFX TDC 36A/OCP 48A
5
PR3003 V2@0_4
MAX17007_VCC 2 +VGPU_CORE
ILIM1 PR3007
EV@ --> dGPU only +VGPU_CORE MAX17007_DL1 +
3 17 4 *V2@2.2_6
ILIM2 DL1 PR3008 PC3009 PC3010
PC3008 PC3011 PQ3002 V2@1.5K/F_4 V2@0.1u/50V_6 V2@330u/2V_7343
1
2
3
V2@120p/50V_4 *V2@2200p/50V_4 PR3011
PC3013 V2@AOL1718 PC3012 V2@10K_6_NTC
MAX17007_REF PR3009 5 V2@0.22U/25V_6 *V2@1000p/50V_4
*V2@0_4 SKIP
PR3010
1/13 Add PR3032. 10 MAX17007_CSH1 V2@3.01K/F_4
MAX17007_VCC PR3032 CSH1
9
B V2@0_4 CSL1 B
+3V PR3012
V2@10_6
PR3013 V2@100K_4 PC3014 +VGPU_CORE
V2@1000p/50V_4
45,47 VGA_PG 12
PGOOD1 PR3014 V2@200K/F_4 VIN
6 VIN
TON1
24
PGOOD2 PR3015 V2@200K/F_4 + PC3030 + PC3015
7
TON2
5
PR3016 *V2@330u/2V_7343 V2@330u/2V_7343
V2@0_6
21 MAX17007_BST2 PQ3003 PC3017 PC3018
BST2 V2@AOL1448
4 V2@0.1u/50V_6 V2@10u/25V_1206
PC3016 PC3019
PC3020 V2@2200p/50V_4 V2@10u/25V_1206
1
2
3
MAX17007_REF 1 V2@0.22u/25V_6
REF
23 MAX17007_DH2
DH2
PL3002 DCR=3m reserved on 11/19
PC3021 V2@1uH
V2@2200p/50V_4 22 MAX17007_LX2
LX2
5
PU3001
V2@MAX17007AGTI+
PR3017
19 MAX17007_DL2 4 *V2@2.2_6 +
PR3018 DL2 PC3022 PC3023
V2@34K/F_4 PQ3004 PR3019 V2@0.1u/50V_6 V2@330u/2V_7343
1
2
3
PC3024 V2@1.5K/F_4
C C
*V2@2200p/50V_4 V2@AOL1718
20
PGND PR3022
MAX17007_REFIN1 8 PC3026 PC3025 V2@10K_6_NTC
REFIN1 V2@0.22u/25V_6 *V2@1000p/50V_4
PR3020
3
V2@196K/F_4 PR3021
26 MAX17007_CSH2 V2@3.01K/F_4
CSH2
27
CSL2
2
19,47 GPU_VID1 PR3023 PR3024
PQ3005 V2@36.5K/F_4 V2@10_6
V2@DMN601K-7 PC3027
V2@1000p/50V_4 VID1 VID2
1
PR3025
11M@100K_4 28 MAX17007_VCC
FB2
GPU_VID1 GPU_VID2 +VGPU_CORE
AGND
AGND
AGND
AGND
AGND
VIN_SRC +VGPU_CORE 0 0 1.035V

11M@ --> N11M-GE1 Setitng PC3028
V2@0.01u/16V_4 1 0 0.95V N11E/N11P
30
31
32
33
29
0 1 0.85V
PR3028 PR3029
PR3026 V2@1M_6 V2@22_8 1 1 0.8V
3
V2@82.5K/F_4
3
2
D
19,47 GPU_VID2 D
3
PQ3006
V2@DMN601K-7 2
17007_EN 2
1
PR3027 PQ7019
V2@100K_4 PR3030 V2@DMN601K-7
PQ7020 V2@1M_6
1
1
V2@DTC144EU
PC3029
V2@0.01u/16V_4
PROJECT : ZR7
3B
GPU CORE(MAX17007)
1 2 3 4 5
A B C D E F G H
Int_VGA [PWM]
AR@ --> ARD CPU 6 GFX_VID0
6 GFX_VID1 +1.1V_VTT +1.1V_VTT

6 GFX_VID2
6 GFX_VID3
1 PR102 PR101 PR192 PR100 PR97 PR92 PR91 1
6 GFX_VID4
*AR@0_6 *AR@0_6 *AR@0_6 *AR@0_6 *AR@0_6 *AR@0_6 *AR@0_6
6 GFX_VID5
6 GFX_VID6
GFX_VID6 GFX_VID5 GFX_VID4 GFX_VID3 GFX_VID2 GFX_VID1 GFX_VID0
PC168
*AR@.01u/25V_4
62881_GND 2 1
PR195 AR@0_4
6 GFX_ON
PR200 AR@0_4
6 GFX_DPRSLPVR
PR193 *AR@SHORT VIN
62881_GND
62881DPRSLPVR
62881_GND
62881VR_ON
1
GFX_VID6
GFX_VID5
GFX_VID4
GFX_VID3
GFX_VID2
PC76 PC77 PC157
AR@10u/25V_1206AR@10u/25V_1206 PC158
2
+3V AR@.1u/50V_6 AR@2200p/50V_4
11/16 Change PU6 footprint by SMT.
30
31
29
28
27
26
25
24
23
22
5
PR207
GFX_VID1
GFX_VID0
VID6
VID5
VID4
VID3
VID2
GND
GND
GND
DPRSLPVR
VR_ON
AR@1.91K/F_4
1
CLK_EN#
2 4 2
PR103 AR@0_4 62881PGOOD 2 21 +5V_S5
36 HWPG_AXF PGOOD VID1
1
2
3
PQ64
PR198 AR@47K/F_4 62881RBIAS 3 20 AR@AOL1448
62881_GND RBIAS VID0
PR199
*AR@150K/F_4 PC78 0616 change to 0.56uH
PR208 AR@8.06K/F_4 62881VW 4 19 1 2
62881_GND VW PU6 VCCP 22A
PC86 AR@4.7u/6.3V_6 +VGFX_AXG
AR@ISL62881HRZ-T 18 62881LGATE
AR@1000p/50V_4 62881COMP 5 LGATE PL12
COMP AR@0.56uH
PR210 PC170 0616 change to 22pF 17
AR@820K/F_4 AR@22p/50V_4 VSSP
62881FB 6
FB
16 62881PHASE
0616 change to 8.87k PHASE
PC171 DCR=1.6~1.8mOhm
AR@100p/50V_4 PR104
Load Line=7mV/A
5
AR@8.87K/F_4 15 62881UGATE
62881VSEN UGATE PR95 + + 1.6m*0.6168=0.986m
7
VSEN PR186 AR@3.65K/F_4 0.986m/.49K=396p
ISUM+
ISUM-
BOOT
IMON 4 4 *AR@4.7_6
VDD
RTN
392p*2*8.87K=7.03m
VIN
PR209 PC87
PR99 PR187 OCP
1
2
3
1
2
3
PQ63 PQ21 AR@2.61K/F_4 AR@10K_6_NTC
20u/2*2.49K=24.9m
8
62881ISUM+ 10
62881VDD 11
12
13
14
AR@17.8K/F_4 AR@150p/25V_4 PC84 PR94 PC79 AR@AOL1718 AR@AOL1718
PC88 AR@330p/50V_4 62881BOOT 1 2 PC156 24.9m/0.6168=40.3m
62881ISUM-
62881VIN
0616 change to 150pF AR@330p/50V_4 AR@1_6 *AR@680p/50V_6 PC167 PC159 PC80

62881RTN AR@.22u/25V_6 PR96 AR@560u/2.5V_6X5.7 AR@560u/2.5V_6X5.7 AR@10u/6.3V_8
40.3m/1.6m=25.2A
GFX_IMON
GFX_IMON 6
PC85 AR@11K/F_4
2
62881_GND PR93
AR@1000p/50V_4 *AR@19.1K/F_4 PC81
*AR@0.022u/25V_4
1
PC162 PC83
3 VSS_AXG_SENSE AR@0.15u/10V_4 AR@.1u/10V_4 3
62881_GND
AR@0_4 PR189 VIN
PC165 62881_GND
PC161 AR@47n/10V_4
AR@.22u/25V_6
62881_GND
+5V_S5 0616 change to 2.49k
PR191 PC163
*AR@180p/50V_4
PR197
PC164 AR@10_6 AR@2.49K/F_4
AR@1u/6.3V_4
PR194
*AR@100/F_4
62881_GND
PR98 PC82
2 1 0616 un-mount
AR@82.5/F_4 AR@.01u/25V_4
Parallel
PR202 AR@10/F_4
PR201 AR@0_4
VSS_AXG_SENSE 6
4 4
PR204 AR@10/F_4
PR203 AR@0_4
VCC_AXG_SENSE 6

PROJECT : ZR7
3B
1.Level 1 Environment-related Substances Should NEVER be Used. +VGFX_AXG (ISL62881)
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners.
A B C D E F G H
5 4 3 2 1
+3VPCU 1A ES@ --> External VGA SKU

+1.8V
SW@ --> iGPU & GPU Switch
PC96
PC185 0.1u/25V_4 11/16 Change PL15 footprint.
10u/10V_8
PU10 HPA00835RTER
16 10 DCR(max)=10mohm
VIN PH
1 11 PL15
VIN PH 1uH_7X7X3
PR117 2 12
*SHORT_4 VIN PH
D D
MAINON 15 13 PR223 *SHORT_6
EN BOOT
54418-1.8_VFB 6 14 PC179 .1u/50V_6 PR232
VSNS PWRGD 51.1/F_4
PC176 7 3
COMP GND
1000p/50V_4 HWPG_1.8V 36
8 RT/CLK GND 4 R1
PAD
PAD
PAD
PAD
PAD
PAD
9 5 PR222
PR228 PR230 SS AGND PR231
100K/F_4
15K/F_4 182K/F_4 +3V 100K/F_4 PC181 PC95 PC184
22
21
20
19
18
17
0.1u/25V_4 10u/10V_8 10u/10V_8
PC189
*100P/50V_4 PC186
MAINON .01u/25V_4 54418-1.8_VFB
MAINON 36,40,41,42,46
PC191
1200p/50V_4 PR229
78.7K/F_4
V0=0.8*(R1+R2)/R2
R2
+5V
5V_LCD
2A
PC3111
PC3110 V2@0.1u/25V_4
V2@10u/10V_8
PU3002 V2@HPA00835RTER
16 10 DCR(max)=10mohm
C VIN PH C
1 11 PL3005
VIN PH V2@1uH_4X4X2
PR3033 2 12
V2@0_4 VIN PH
HWPG_VTT 15 13 PR3034 V2@0_6
EN BOOT
54418-1.8_VFB_1 6 14 HWPG_5V_LCD PC3112V2@.1u/50V_6 PR3035
VSNS PWRGD V2@51.1/F_4
PC3113 7 3
COMP GND
V2@1000p/50V_4
8 RT/CLK GND 4 R1
PAD
PAD
PAD
PAD
PAD
PAD
9 5 PR3039 PR3038
PR3036 PR3037 SS AGND
*V2@100K/F_4
V2@30.1K/F_4 V2@182K/F_4 +3V V2@100K/F_4 PC3114 PC3115 PC3116
22
21
20
19
18
17
V2@10u/10V_8
PC3117 V2@0.1u/25V_4 V2@10u/10V_8
*V2@100P/50V_4 PC3118
V2@.01u/25V_4 54418-1.8_VFB_1
HWPG_VTT 5V_LCD
HWPG_VTT 36,40 5V_LCD 23
PC3119
V2@1000p/50V_4
PR3040
V0=0.8*(R1+R2)/R2
1/13 Add 3D LCD power circuit. R2
V2@26.7K/F_4
VIN_SRC +1.5V_GFX +1.8V_GFX +15V +1.8V +1.5V_SUS

11/19 Del 3G power circuit.
B B
PR47 PR46 PR36 PR49
5
6
7
8
ES@1M/F_6 ES@22_8 ES@22_8 ES@1M/F_6
dGPU_D1 2 dGPU_D1 4
3
10/19
3
PQ53 PQ50
PR44 ES@0_4 ES@AO3404 ES@AO4468 +1.5V_GFX
1
2 2 2 2
43,47 VGA_PG PR40 PC46
3
2
1
+1.8V_GFX
ES@1M/F_6 PQ12 PQ8 PQ13 *ES@2200p/50V_4
PQ11 ES@DMN601K-7 ES@DMN601K-7 ES@DMN601K-7
0.23A(Max0.3A)
1
PC38 ES@DTC144EU
1
ES@1u/10V_4
4.28A(Max5.72A)
VIN_SRC +3V_GFX +1.05V_GFX +15V +1.05V +3VPCU
PR38 PR48 PR37

5
6
7
8
ES@1M/F_6 ES@22_8 ES@22_8 PR43
3
ES@1M/F_6
11/12 dGPU_D 4
dGPU_D 2
3
A A
MAINON PR243 EV@0_4
3
PQ54
PR39 ES@AO4468 PQ51
PR244 SW@0_4 2 ES@1M/F_62 2 2 1 ES@AO3404
11 dGPU_PWR_EN PC39 +1.05V_GFX +3V_GFX
3
2
1
PQ9 PQ6 PQ10 *ES@2200p/50V_4

1
PQ7 ES@DMN601K-7 ES@DMN601K-7 ES@DMN601K-7

1
PR35 ES@DTC144EU
10/19
1
SW@100K_4
2.87A(Max 3.83A) 1.04A(Max1.38A) Quanta Computer Inc.
2
PROJECT : ZR7
SW@ --> iGPU & GPU Switch Size Document Number Rev
3B
Discharge/1.8V)
5 4 3 2 1
1 2 3 4 5
VIN_SRC
PD2 PU5B
SW1010CPT 5
A + A
7
6 -
LM393
PR87
For EC control thermal protection (output 3.3V)
1
1M_6
PQ17
AO3409
2
3
S5_ON
36,38 S5_ON 2
Thermal protection
PQ18
1
DTC144EU PR85
VL VL *SHORT_6
B B
SYS_SHDN# 4,38
PR83 PR84
1.2K/F_4 200K/F_4 PR81
200K_6
PC69
.1u/50V_6
3
8
PR41
10K_6_NTC 2.469V 3 +
1 2
2 - PQ15
PU5A DMN601K-7
4
LM393 PC67
1
.1u/50V_6
PR86
3
200K/F_4
C C
S5_ON 2
PQ19
DMN601K-7
1
+3V +5V +1.1V_VTT +1.5V +1.05V +15V

VIN_SRC
Add it for S3 leakage circuit PR143 PR137 PR140 PR150 PR149 PR145
PR146 22_8 22_8 22_8 22_8 22_8 1M/F_6
35 MAINON_DIS_G 1M/F_6
7/23 modify
MAINON_DIS_G MAIND
MAIND 35,38,42
3
3
3
PR142
D 2 1M/F_6 2 D
36,40,41,42,45 MAINON PC118
2 2
2 2 2 PQ40 *2200p/50V_4
1
PQ47 DMN601K-7
1
PR148 DTC144EU PQ41 PQ45
1
*100K_4 PQ39 PQ42 PQ46 DMN601K-7
1
DMN601K-7
PROJECT : ZR7
1
DMN601K-7 DMN601K-7 DMN601K-7

2

3B
Thermal Protection
1 2 3 4 5
1 2 3 4 5
V1@ --> One Phase dGPU only

+5V_S5
EV@ --> External VGA SKU VIN
VIN
SW@ --> iGPU & dGPU Switch PC3031

V1@10u/25V/X6S_1206
PR128 PQ37 PQ7021 29A
11M@ --> N11M-GE1 Setitng +3V *V1@0_4 V1@AOL1448 11P@AOL1448 OCP=35A
A PR16 PC16 PC18 A
5
V1@200K/F_4 V1@.1u/50V_6 V1@10u/25V/X6S_1206 +VGPU_CORE
11P@ --> N11P-GE1 Setitng PC4 V1@1u/10V_6 2
VDD TON
7 8792TON
PR4 5 8792DH 4 4
V1@100K_4 PC2 V1@1u/10V_6 8792VCC DH
13 VCC PC17 PC113
8792_GND
1
2
3
1
2
3
6 8792BST V1@2200p/50V_4 V1@10u/25V/X6S_1206
BST PR15 PC10 11P@
43,45 VGA_PG 14
PGOOD V1@1_6 V1@0.22u/X5R_6 N11P-GE1 PL6
8792EN 1 PU1 Setitng 11P@0.68uH
11,43 dGPU_VRON EN 8792LX +VGPU_CORE
4
PR123 change net name V1@MAX8792ETD+TLX
SW@ --> iGPU & GPU Switch *SW@0_4 PC1 8792SKIP# 12 PL3004
SKIP# 8792DL 11M@0.36uH
DL 3
5
+3V_GFX V1@.1u/10V_4 PR8 *V1@0_4
8792REFIN 10 PR21
PR3031 REFIN V1@1_8
FB 8
EV@ --> GPU only ES@0_4 PR122 4 4 11M@ + + +
REF-2V N11M-GE1
V1@100K_4 8792REF 8792ILIM PC25
10/19 11 9
1
2
3
1
2
3
REF ILIM Setitng V1@330u/2V
PC15
EP
8792_GND V1@1000p/50V_4
8792_GND
15
B B
PR130
V1@34K/F_4 PR131
V1@62K/F_4 PR1 PC14
V1@ES0_6 *V1@4700P/25V_4 PQ35 PQ34 PC27 PC21 PC22
8792_GND V1@AOL1718 V1@AOL1718 V1@.1u/50V_6 V1@330u/2V V1@330u/2V
Place near GND pin15
PR127 PC9
3
V1@196K/F_4 V1@1000P/50V_4
PR14
VID1 V1@100K_4
2 PQ28
19,43 GPU_VID1 V1@2N7002D Frequency(PR220=200K) 300K
PR126 Changed VID table
11M@100K_4 8792_GND 8792_GND
1
PR132
V1@36.5K/F_4 VID1 VID2
changed value on 09/17
11M@ --> N11M-GE1 Setitng PC103
V1@.01u/16V_4
GPU_VID1 GPU_VID2 +VGPU_CORE
0 0 1.035V N11M
C C
8792_GND 8792_GND 1 0 0.95V
changed to GND_VGA8792 N11E/N11P VIN_SRC +VGPU_CORE
PR5 0 1 0.85V
3
V1@82.5K/F_4
VID2 1 1 0.8V
2 PQ1 PR7 PR2
19,43 GPU_VID2 V1@2N7002D V1@1M_6 V1@22_8
PR3
V1@100K_4 10/20 Modify Power table
1
3
10/22 Power CKT updated change net name
3
2
8792EN 2
PC3
V1@.01u/16V_4 PR6 PQ2
PQ29 V1@1M_6 V1@2N7002D
1
8792_GND V1@DTC144EU
D D

PROJECT : ZR7
3B
GPU CORE(MAX8792)
1 2 3 4 5
5 4 3 2 1
300 mil ISL62882 1800 mil 1800 mil CPU

VCC_CORE
PU7 U3031
U38 U3035 U50 CN27 U6 U22 U33 CN1 CN2 CN34 CN36 CN30 CN15
40 mil 20 mil 40 mil 40 mil 20 mil 20 mil 20 mil 30 mil 20 mil 80 mil 80 mil 80 mil 20 mil
200 mil
CN19 CN20 CN10 CN43 CN12 CN16 CN41 U2
200 mil AO6402A +5V
20 mil 20 mil 20 mil 20 mil 20 mil 20 mil 20 mil 20 mil
PQ35
D
520 mil +5VPCU D
280 mil AO4496 280 mil CN9

+5V_TMA
400 mil PQ82 280 mil
ISL6237
PU4
40 mil AO6402A 40 mil U3035 PU7 PU8 PU9 PU10 PU6 PU11
+5V_S5
PQ38 20 mil 20 mil 20 mil 20 mil 20 mil 20 mil 20 mil
200 mil
AC System +5VPCU R330 R3691 U45 ESD1 U23 CN15 CN14
Charger 20 mil 10 mil 20 mil 30 mil 20 mil 20 mil 20 mil
ISL6251A VIN
DC CN39 CN6 U4 U19 U14 CN5 R428
PU2 20 mil 10 mil 70 mil 10 mil 70 mil 130 mil 20 mil
40 mil D30 MR1 CN14 U16 U8 R429 PU12 R164 R586 R437 L22 U9 PU2
+3VPCU
C
20 mil 15 mil 20 mil 30 mil 20 mil 20 mil 20 mil 15 mil 20 mil 10 mil 10 mil 20 mil 10 mil C
250 mil AO4496 250 mil L26 U15 R3343 R649 R462 L3035 R184 R3587 R167 R192 R195 U3010 CN27
+3VPCU
+3V
PQ25 20 mil 10 mil 20 mil 20 mil 30 mil 15 mil 30 mil 15 mil 10 mil 30 mil 30 mil 10 mil 80 mil
U5 Q6 U33 U27 U18 U44 R655 R619 R710 L57 CN11 R496 R499
R327 CN12 CN18 U29 U13 CN5 R158 R36 R11 R29 CN3 R3289 R3292
150 mil AO6402A 150 mil 30 mil G973 40 mil U3031 R3301 R3268 L25 R711 L28 R3291
+3V_S5 +1.8V
PQ7 PU11 30 mil 15 mil 15 mil 15 mil 40 mil 25 mil 20 mil
120 mil
R654 Q22 CN17 R198 U21 U3017 U29 R17 U3044 U11 R151
20 mil 120 mil 30 mil 20 mil 15 mil 20 mil 30 mil 20 mil 20 mil 15 mil 30 mil
B B
20 mil G909 20 mil

R3234 R34
PU12 +1.5V_S5
15 mil 15 mil
R3340 R448 R165 L3055 R3570 R3056 R180 R3304 L3046 L3048 R186 R454 R455
200 mil UP6111A 400 mil 20 mil 80 mil 20 mil 15 mil 150 mil 15 mil 15 mil 15 mil 15 mil 15 mil 40 mil 50 mil 50 mil
+1.05V
PU10
L3047 R185 R3644 L3058 R195
15 mil 30 mil 60 mil 15 mil 30 mil
250 mil UP6111A 600 mil
+VTT Q39 U3031 R3243 R195
PU9
10 mil 600 mil 15 mil 15 mil
80 mil JDIM3001 JDIM3002
+SMDDR_VTERM
40 mil 40 mil
200 mil 20 mil R3326

TPS51116 +SMDDR_VREF
20 mil
PU6
A
600 mil 300 mil AO4496 300 mil R3302 CN17 CN9 U18 R69 R668 U29 R676 A
+1.5VSUS +1.5V
PQ23 15 mil 30 mil 180 mil 20 mil 30 mil 30 mil 60 mil 30 mil
400 mil
JDIM3001 JDIM3002 U3031
100 mil 100 mil 350 mil
200 mil ISL62881 400 mil U3031
+VAXG
PU8 350 mil Quanta Computer Inc.
PROJECT : ZR7
3B
POWER MANAGEMENT
5 4 3 2 1
5 4 3 2 1
MODEL
ZR7
Model REV CHANGE LIST FROM To
1A 2A
11/2 Page33 Change CN10 P/N by PDC.
1A 2A
11/5 Page9 change R338 and R594 to 10K ohm by checklist.
ZR7 MB 11/5 Page10 Add R699 connect XTAL25_IN to Gnd on EV sku and stuff Xtal components by checklist.
1A 2A
1A 2A
11/5 Page12 un-stuff R318 and del C499 and add R698 contact VCCLAN to GND by checklist.
1A 2A
11/9 Page32 change W/L LED signal to control by EC.
1A 2A
11/9 Page36 Add EC pin82/112 for W/L LED control by EC.
1A 2A
11/12 Page35 PR90,PQ22 no stuff.
1A 2A
11/12 Page45 Add PR243,PR244 for option.
1A 2A
11/16 Page23 CN5 Add LVDS signal to two channel and change CN3 to 8pin conn.
1A 2A
D 11/16 Page43 GPU VCORE power change to two phase solution. D
1A 2A
11/16 Page27 Add CN12 8pin conn for Touch Screen by ME.
1A 2A
11/16 Page44 Change PU6 footprint by SMT.
1A 2A
11/16 Page45 Change PL15 footprint to CHOKE-PCMC063T-3R3MN-NB4 by SMT.
1A 2A
11/16 Page39 Change PU8 footprint to qfn40-5x5-4-41p-0_75h-smt by SMT.
1A 2A
11/16 Page37 Change PU3 footprint to QFN28-5X5-5-33P-SMT by SMT.
1A 2A
11/18 Page10 Delete R597, C444,C445 for cancel 3G function.
1A 2A
11/18 Page30 R368,R393 modify from 47ohm to 56ohm by Realtek.
1A 2A
11/18 Page10 Change BOARD_ID0~2 to BOARD_ID1~3.
1A 2A
2A 11/18 Page11 Change GPIO7 to BOARD_ID0 and reserve R439 PD.
1A 2A
11/18 Page36 Add D23 to connect to dGPU_PWROK on EV sku.
1A 2A
11/18 Page9 Change P/N follow ZR7B that use right angle connector.
1A 2A
11/18 Page27 Reserve C919, CN22 for NV IR signals on B-test.
1A 2A
11/19 Page3 Change U39 PN to AL003197002 by vendor.
1A 2A
11/19 Page31 Change CN9 footprint & P/N follow ZR7B.
1A 2A
11/19 Page27 Add R697 for WI-FI.
1A 2A
11/19 Page11 Add R442, R440 to dGPU_PWROK_R and stuff R321 on EV sku.
1A 2A
11/19 Page23 Modify CN5 pin define.
1A 2A
11/20 Page43 Add PR124 on EV sku.
1A 2A
11/20 Page12~14 Change core logic cap .1uF CH41003ZB35 to CH4102K1B03 by SMT.
1A 2A
11/20 Page45 del 3G power circuit.
1A 2A
11/20 Page34 del HOLE10,Add HOLE5,HOLE6,HOLE7,HOLE8,HOLE11,HOLE12,HOLE14,HOLE15,HOLE17,HOLE18,HOLE20,HOLE24,HOLE25,HOLE26,HOLE30 P/N
1A 2A
11/25 Page10 Q26,Q29 change to unstuff , Add R700,R701 0 ohm for S3 leakage
1A 2A
11/25 Page20 C151 change to CC7343 package
1A 2A
11/25 Page34 Change HOLE8,HOLE12 footprint to H-C236D142P2 , Change HOLE5,HOLE7,HOLE11 footprint to H-TC197D122PT ,
Change HOLE14,HOLE15,HOLE17,HOLE18 footprint to H-TC236D142PT , Change HOLE20,HOLE24,HOLE26 footprint to 1A 2A
H-TC236D162PT , Change HOLE9 footprint to O-ZR7-1-B 1A 2A
1A 2A
C 11/25 Page36 R425 change to DGPU_IDLE# signal and value to SW SKU , R428 change value to SW SKU , R249,R250 change to unstuff C
1A 2A
11/25 Page28 Add C920,C921,C923,C924 0.1uF for EMI
1A 2A
11/25 Page33 L31 SWAP for Layout House
1A 2A
11/25 Page27 Modify LTRST#_7726 net name to PLTRST#
1A 2A
11/26 Page33 Change L19/L25 footprint , Stuff L25 common choke & unstuff R301,R302 by EMI
1A 2A
11/26 Page23 Change L2 footprint
1A 2A
11/26 Page23 Change R589,R590 to FLITER for EMI
1A 2A
11/26 Page28 Add C925,C926,C927 for EMI
1A 2A
11/26 Page11 Modify R422 Value to IV@ SKU
1A 2A
11/27 Page11 Del R440 1A 2A
11/27 Page20 C81,C105 change CC0603 package 1A 2A
11/27 Page16 C84,C109 change CC0603 package 1A 2A
11/27 Page23 Add CN5 pin45 to GND 1A 2A
11/27 Page27 Add L46,L47,R702,R703,R704,R705 by EMI 1A 2A
11/27 Page10 Modify C699,C703 to 27pF 1A 2A
11/27 Page18 Modify C601,C600 to 27pF 1A 2A
12/1 Page27 Modify CN12 to 6 pin connector 1A 2A
12/1 Page32 Modify LED3 & Add R706,R707 PD by EC ODD_EJ & POWER_SAVE 1A 2A
12/1 Page9 Add R708,R709 by SPI ROM 1A 2A
2A 3A
12/18 Page32 Add R710,R711,Q57 by EC.
2A 3A
12/18 Page23 Add R712,R713 by 3D feature.
2A 3A
12/18 Page47 Change PL6 footprint to choke-mpl136-2r2-smt by SMT.
2A 3A
12/29 Page27 Change CN21 footprint to MIPCI-800055FB052GX00pl-52P-smt by SMT.
2A 3A
12/29 Page23 Add F1 by safety.
2A 3A
3A 12/29 Page24 Change Q16, Q45 P/N & add F2 by HMDI submit and safety; del U15, U16, U18.
2A 3A
12/29 Page30 Change CN19 color to black P/N: DFTJ08FR130 by ACER.
2A 3A
1/5 Page33 Change CN17 footprint to USB-UB111GC-RABED-7F-4P-R-V-SMT by PDC.
B 2A 3A B
1/7 Page23 Change Q12 of dGPU_select# signal design by leakage issue.
2A 3A
1/7 Page9 Change BT1 P/N to DFHD02MS784 by ME issue.
2A 3A
1/8 Page27 Change CN12,CN22 6pin conn footprint for Touch Screen and IR.
2A 3A
1/11 Page23 Add L48 & stuff L2 and un-stuff R28 and R29 by EMI.
2A 3A
1/11 Page24 Add C928 by EMI.
2A 3A
1/13 Page12,36 Change C711,C382 to 10U 6.3V.
2A 3A
1/14 Page23 Change LVDS connector Pin4 define from NC to LCDVCC & add J3 by 3D PWR.
2A 3A
1/14 Page28 Change C218,C678 to 10U/10V_8 and footprint 0805.
2A 3A
2/3 Page 16~22 Change U33 footprint to fcbga973-nvidia-n11p-es-a1 by NV. 3A 3B
3B
2/3 Page 30 Change R368,R393 to 75ohm. 3A 3B
Power modify: 1A 2A
11/19 Take out JP12, JP9, JP5, JP6, JP7, JP19, JP20, JP8, JP10, JP11,JP13, JP15, JP16, JP1, JP17, JP14, JP18. 1A 2A
2A
11/19 Page38 Change PC198 value; change PR114 from 191K to 182K, PR115 from 220K to 200K,PR106 from 100K to 1K,PR105 from 200K to 1A 2A
150K. 1A 2A
11/19 Page40 Change PL7,PL8 from 1.0uH to 2.2uH.
1A 2A
11/19 Page39 Change PL10,PL11 from DC+36T0M000 to CV+18V0MZ04.
1A 2A
11/19 Page43 Reserve PC3030.
1A 2A
11/23 Page37 PR19 change to 150K , PR20 change to 39K , PC112 change to 1U 25V
1A 2A
12/29 Page47 Change PL7,PL8,PL15,PL16 footprint to CHOKE-PCMC063T-3R3MN-SMT by SMT. 2A 3A
3A 12/29 Page37 Change PR136 footprint to RC3720-SMT by SMT. 2A 3A
1/5 Page37~48 Change footprint from CHOKE-ETQP4LR36WFC to CHOKE-ETQP4LR36WFC-SMT by PDC. 2A 3A
1/11 Page37 Add PC3100~PC3109 by EMI. 2A 3A
1/11 Page47 Change value of PQ7021,PL6,PL3004 by BOM. 2A 3A
1/13 Page43 Reserve PR3032 by PWR. 2A 3A
1/13 Page45 Reserve circuit of LCDVCC by PWR. 2A 3A
2/10 Page37 Reserve EC1~EC5 by EMI. 3A 3B
2/11 Page38 Del PD3 by power. 3A 3B
A
3B A
2/11 Page40 Add C930~C934 by monitor test. 3A 3B

3A 3B

PROJECT : ZR7 DOC NO.
PROJECT MODEL : ZR7 APPROVED BY: DATE: 2009/11/06
3B
Change list2 PART NUMBER: DRAWING BY: REVISON: 1A
5 4 3 2 1

Zr7 System Block Diagram: Ver: 1A

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Zr7 System Block Diagram: Ver: 1A

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5 4 3 2 1

VER : 1A BOM MARK

64MB/128MB x 8 ES@ N11X+SW VGA

P28 INT_HDMI PS8101

Speaker MIC JACK HP/SPDIF Power CIR Function Touch Pad

GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

Thermal Follow Chart

B VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B

+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC

+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS

+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V

+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0

+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0

+VGFX_AXG variation Internal GPU POWER GFX_ON S0

+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0

+1.05V +1.05V PCH CORE POWER MAINON S0

+VCC_CORE variation CPU CORE POWER VRON S0

LCDVCC +3.3V LCD POWER LVDS_VDDEN S0

+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable

+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable

+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable

+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable

+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable

+1V +1V DP/PEG POWER PG_1V_EN Discrete enable

Quanta Computer Inc.

R603 C722 39 VR_PWRGD_CK505# 2 R577

AR@ --> ARD CPU ARRANDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI)

JTAG & BPM

VTT Rail Values are

+3V XDP_TMS R232 *51_4 R535

XDP_TDI_R R537 *51_4 *SHORT_4

Scan Chain STUFF -> R535, R538, R528

R226 +1.5V_CPUVDDQ (Default) NO STUFF -> R536, R534

ARRANDALE/CLARKSFIELD PROCESSOR (DDR3) U37D

15 M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 15

DDR SYSTEM MEMORY - B

M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ40 AK3 AR5 M_B_DQS#6

Quanta Computer Inc.

1.1V RAIL POWER

C304 330u/2V_7343 AC32 +1.1V_VTT AH16 T7 C340 C331 C271 + C257

PEG & DMI

V28 AL33 H_VID4 H_VID4 39 C210 1U/6.3V_4

VCC88 VCC_SENSE VCCSENSE 39

ARRANDALE/CLARKSFIELD PROCESSOR (GND) ARRANDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AL20 VSS40 VSS120 W6 E21 VSS198 AJ29 CFG[15] RSVD_TP_59 E15

Processor Strapping VTT Rail Values are +1.1V_VTT

AR@ --> ARD CPU AR@ --> ARD CPU

Digital Display Interface

36 ICH_RSMRST# C16 RSMRST# SLP_S4# H7 SUSC# 36 DDPD_AUXN BC46

PM_RI# F14 F6 PM_SLP_LAN# T58

PCH Pull-high/low AR@ --> ARD CPU System PWR_OK

CLKRUN# R586 8.2K_4 PM_RI# R372 10K_4 +3V_S5

PCIE_WAKE# R365 1K_4

RTC Circuitry C758

29 PCH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA1TXN

R658 33_4 ACZ_SDOUT SPI_CLK_R BA2

PCH Strap Pin Configuration Table-1

SPI_MOSI TPM Functionality 1 = Enabled

#/GPIO33 Security Override Descriptor will be enabled.

GNT3#/ Top-Block 0 = Top Block Swap Mode

IntelR Anti-Theft Technology

XDP_TDI_R R537 51_4 SHORT_4